Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Global Instruction Selector for the Mips target *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
10 : const unsigned MAX_SUBTARGET_PREDICATES = 41;
11 : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12 : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13 :
14 : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 : mutable MatcherState State;
16 : typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 : typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18 : const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19 : static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 : static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21 : bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 : bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 : bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 : const int64_t *getMatchTable() const override;
25 : bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26 : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27 :
28 : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29 : , State(0),
30 20614 : ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31 : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32 :
33 : #ifdef GET_GLOBALISEL_IMPL
34 : // Bits for subtarget features that participate in instruction matching.
35 : enum SubtargetFeatureBits : uint8_t {
36 : Feature_HasMips2Bit = 7,
37 : Feature_HasMips3Bit = 16,
38 : Feature_HasMips4_32Bit = 26,
39 : Feature_NotMips4_32Bit = 27,
40 : Feature_HasMips4_32r2Bit = 17,
41 : Feature_HasMips32Bit = 3,
42 : Feature_HasMips32r2Bit = 6,
43 : Feature_HasMips32r6Bit = 28,
44 : Feature_NotMips32r6Bit = 4,
45 : Feature_IsGP64bitBit = 21,
46 : Feature_IsPTR64bitBit = 23,
47 : Feature_HasMips64Bit = 24,
48 : Feature_HasMips64r2Bit = 22,
49 : Feature_HasMips64r6Bit = 29,
50 : Feature_NotMips64r6Bit = 5,
51 : Feature_InMips16ModeBit = 30,
52 : Feature_NotInMips16ModeBit = 0,
53 : Feature_HasCnMipsBit = 25,
54 : Feature_NotCnMipsBit = 8,
55 : Feature_IsN64Bit = 37,
56 : Feature_RelocNotPICBit = 9,
57 : Feature_RelocPICBit = 36,
58 : Feature_NoNaNsFPMathBit = 20,
59 : Feature_HasStdEncBit = 1,
60 : Feature_NotDSPBit = 11,
61 : Feature_InMicroMipsBit = 34,
62 : Feature_NotInMicroMipsBit = 2,
63 : Feature_IsLEBit = 39,
64 : Feature_IsBEBit = 40,
65 : Feature_IsNotNaClBit = 18,
66 : Feature_HasEVABit = 35,
67 : Feature_HasMSABit = 33,
68 : Feature_HasMadd4Bit = 19,
69 : Feature_UseIndirectJumpsHazardBit = 12,
70 : Feature_NoIndirectJumpGuardsBit = 10,
71 : Feature_AllowFPOpFusionBit = 38,
72 : Feature_IsFP64bitBit = 15,
73 : Feature_NotFP64bitBit = 14,
74 : Feature_IsNotSoftFloatBit = 13,
75 : Feature_HasDSPBit = 31,
76 : Feature_HasDSPR2Bit = 32,
77 : };
78 :
79 0 : PredicateBitset MipsInstructionSelector::
80 : computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
81 0 : PredicateBitset Features;
82 0 : if (Subtarget->hasMips2())
83 0 : Features[Feature_HasMips2Bit] = 1;
84 0 : if (Subtarget->hasMips3())
85 0 : Features[Feature_HasMips3Bit] = 1;
86 0 : if (Subtarget->hasMips4_32())
87 0 : Features[Feature_HasMips4_32Bit] = 1;
88 0 : if (!Subtarget->hasMips4_32())
89 0 : Features[Feature_NotMips4_32Bit] = 1;
90 0 : if (Subtarget->hasMips4_32r2())
91 0 : Features[Feature_HasMips4_32r2Bit] = 1;
92 : if (Subtarget->hasMips32())
93 0 : Features[Feature_HasMips32Bit] = 1;
94 : if (Subtarget->hasMips32r2())
95 0 : Features[Feature_HasMips32r2Bit] = 1;
96 : if (Subtarget->hasMips32r6())
97 0 : Features[Feature_HasMips32r6Bit] = 1;
98 : if (!Subtarget->hasMips32r6())
99 0 : Features[Feature_NotMips32r6Bit] = 1;
100 0 : if (Subtarget->isGP64bit())
101 0 : Features[Feature_IsGP64bitBit] = 1;
102 0 : if (Subtarget->isABI_N64())
103 0 : Features[Feature_IsPTR64bitBit] = 1;
104 0 : if (Subtarget->hasMips64())
105 0 : Features[Feature_HasMips64Bit] = 1;
106 0 : if (Subtarget->hasMips64r2())
107 0 : Features[Feature_HasMips64r2Bit] = 1;
108 0 : if (Subtarget->hasMips64r6())
109 0 : Features[Feature_HasMips64r6Bit] = 1;
110 0 : if (!Subtarget->hasMips64r6())
111 0 : Features[Feature_NotMips64r6Bit] = 1;
112 0 : if (Subtarget->inMips16Mode())
113 0 : Features[Feature_InMips16ModeBit] = 1;
114 0 : if (!Subtarget->inMips16Mode())
115 0 : Features[Feature_NotInMips16ModeBit] = 1;
116 0 : if (Subtarget->hasCnMips())
117 0 : Features[Feature_HasCnMipsBit] = 1;
118 0 : if (!Subtarget->hasCnMips())
119 0 : Features[Feature_NotCnMipsBit] = 1;
120 0 : if (Subtarget->isABI_N64())
121 0 : Features[Feature_IsN64Bit] = 1;
122 0 : if (!TM.isPositionIndependent())
123 0 : Features[Feature_RelocNotPICBit] = 1;
124 0 : if (TM.isPositionIndependent())
125 0 : Features[Feature_RelocPICBit] = 1;
126 0 : if (TM.Options.NoNaNsFPMath)
127 0 : Features[Feature_NoNaNsFPMathBit] = 1;
128 0 : if (Subtarget->hasStandardEncoding())
129 0 : Features[Feature_HasStdEncBit] = 1;
130 0 : if (!Subtarget->hasDSP())
131 0 : Features[Feature_NotDSPBit] = 1;
132 0 : if (Subtarget->inMicroMipsMode())
133 0 : Features[Feature_InMicroMipsBit] = 1;
134 : if (!Subtarget->inMicroMipsMode())
135 0 : Features[Feature_NotInMicroMipsBit] = 1;
136 0 : if (Subtarget->isLittle())
137 0 : Features[Feature_IsLEBit] = 1;
138 0 : if (!Subtarget->isLittle())
139 0 : Features[Feature_IsBEBit] = 1;
140 0 : if (!Subtarget->isTargetNaCl())
141 0 : Features[Feature_IsNotNaClBit] = 1;
142 0 : if (Subtarget->hasEVA())
143 0 : Features[Feature_HasEVABit] = 1;
144 0 : if (Subtarget->hasMSA())
145 0 : Features[Feature_HasMSABit] = 1;
146 0 : if (!Subtarget->disableMadd4())
147 0 : Features[Feature_HasMadd4Bit] = 1;
148 : if (Subtarget->useIndirectJumpsHazard())
149 0 : Features[Feature_UseIndirectJumpsHazardBit] = 1;
150 : if (!Subtarget->useIndirectJumpsHazard())
151 0 : Features[Feature_NoIndirectJumpGuardsBit] = 1;
152 0 : if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
153 0 : Features[Feature_AllowFPOpFusionBit] = 1;
154 0 : if (Subtarget->isFP64bit())
155 0 : Features[Feature_IsFP64bitBit] = 1;
156 0 : if (!Subtarget->isFP64bit())
157 0 : Features[Feature_NotFP64bitBit] = 1;
158 0 : if (!Subtarget->useSoftFloat())
159 0 : Features[Feature_IsNotSoftFloatBit] = 1;
160 0 : if (Subtarget->hasDSP())
161 0 : Features[Feature_HasDSPBit] = 1;
162 0 : if (Subtarget->hasDSPR2())
163 0 : Features[Feature_HasDSPR2Bit] = 1;
164 0 : return Features;
165 : }
166 :
167 0 : PredicateBitset MipsInstructionSelector::
168 : computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
169 : PredicateBitset Features;
170 0 : return Features;
171 : }
172 :
173 : // LLT Objects.
174 : enum {
175 : GILLT_s16,
176 : GILLT_s32,
177 : GILLT_s64,
178 : GILLT_v2s16,
179 : GILLT_v2s64,
180 : GILLT_v4s8,
181 : GILLT_v4s32,
182 : GILLT_v8s16,
183 : GILLT_v16s8,
184 : };
185 : const static size_t NumTypeObjects = 9;
186 : const static LLT TypeObjects[] = {
187 : LLT::scalar(16),
188 : LLT::scalar(32),
189 : LLT::scalar(64),
190 : LLT::vector(2, 16),
191 : LLT::vector(2, 64),
192 : LLT::vector(4, 8),
193 : LLT::vector(4, 32),
194 : LLT::vector(8, 16),
195 : LLT::vector(16, 8),
196 : };
197 :
198 : // Feature bitsets.
199 : enum {
200 : GIFBS_Invalid,
201 : GIFBS_HasCnMips,
202 : GIFBS_HasDSP,
203 : GIFBS_HasDSPR2,
204 : GIFBS_HasMSA,
205 : GIFBS_InMicroMips,
206 : GIFBS_InMips16Mode,
207 : GIFBS_IsFP64bit,
208 : GIFBS_NotFP64bit,
209 : GIFBS_HasDSP_InMicroMips,
210 : GIFBS_HasDSP_NotInMicroMips,
211 : GIFBS_HasDSPR2_InMicroMips,
212 : GIFBS_HasMSA_HasStdEnc,
213 : GIFBS_HasMSA_IsBE,
214 : GIFBS_HasMSA_IsLE,
215 : GIFBS_HasMips32r6_HasStdEnc,
216 : GIFBS_HasMips32r6_InMicroMips,
217 : GIFBS_HasMips64r2_HasStdEnc,
218 : GIFBS_HasMips64r6_HasStdEnc,
219 : GIFBS_HasStdEnc_IsNotSoftFloat,
220 : GIFBS_HasStdEnc_NotInMicroMips,
221 : GIFBS_HasStdEnc_NotMips4_32,
222 : GIFBS_InMicroMips_IsFP64bit,
223 : GIFBS_InMicroMips_IsNotSoftFloat,
224 : GIFBS_InMicroMips_NotFP64bit,
225 : GIFBS_InMicroMips_NotMips32r6,
226 : GIFBS_IsGP64bit_NotInMips16Mode,
227 : GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
228 : GIFBS_HasMSA_HasMips64_HasStdEnc,
229 : GIFBS_HasMips3_HasStdEnc_IsGP64bit,
230 : GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
231 : GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
232 : GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
233 : GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
234 : GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
235 : GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
236 : GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
237 : GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
238 : GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
239 : GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
240 : GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
241 : GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
242 : GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
243 : GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
244 : GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
245 : GIFBS_InMicroMips_NotMips32r6_RelocPIC,
246 : GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
247 : GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
248 : GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
249 : GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
250 : GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
251 : GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
252 : GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
253 : GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
254 : GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
255 : GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
256 : GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
257 : GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
258 : GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
259 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
260 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
261 : GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
262 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
263 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
264 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
265 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
266 : };
267 : const static PredicateBitset FeatureBitsets[] {
268 : {}, // GIFBS_Invalid
269 : {Feature_HasCnMipsBit, },
270 : {Feature_HasDSPBit, },
271 : {Feature_HasDSPR2Bit, },
272 : {Feature_HasMSABit, },
273 : {Feature_InMicroMipsBit, },
274 : {Feature_InMips16ModeBit, },
275 : {Feature_IsFP64bitBit, },
276 : {Feature_NotFP64bitBit, },
277 : {Feature_HasDSPBit, Feature_InMicroMipsBit, },
278 : {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
279 : {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
280 : {Feature_HasMSABit, Feature_HasStdEncBit, },
281 : {Feature_HasMSABit, Feature_IsBEBit, },
282 : {Feature_HasMSABit, Feature_IsLEBit, },
283 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
284 : {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
285 : {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
286 : {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
287 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
288 : {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
289 : {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
290 : {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
291 : {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
292 : {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
293 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
294 : {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
295 : {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
296 : {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
297 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
298 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
299 : {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
300 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
301 : {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
302 : {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
303 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
304 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
305 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
306 : {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
307 : {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
308 : {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
309 : {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
310 : {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
311 : {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
312 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
313 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
314 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
315 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
317 : {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
318 : {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
319 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
320 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
321 : {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
322 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
323 : {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
324 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
325 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
326 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
327 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
328 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329 : {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
330 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
331 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
332 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
333 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
334 : };
335 :
336 : // ComplexPattern predicates.
337 : enum {
338 : GICP_Invalid,
339 : };
340 : // See constructor for table contents
341 :
342 : // PatFrag predicates.
343 : enum {
344 : GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
345 : GIPFP_I64_Predicate_immSExt10,
346 : GIPFP_I64_Predicate_immSExt6,
347 : GIPFP_I64_Predicate_immSExtAddiur2,
348 : GIPFP_I64_Predicate_immSExtAddius5,
349 : GIPFP_I64_Predicate_immZExt1,
350 : GIPFP_I64_Predicate_immZExt10,
351 : GIPFP_I64_Predicate_immZExt1Ptr,
352 : GIPFP_I64_Predicate_immZExt2,
353 : GIPFP_I64_Predicate_immZExt2Lsa,
354 : GIPFP_I64_Predicate_immZExt2Ptr,
355 : GIPFP_I64_Predicate_immZExt2Shift,
356 : GIPFP_I64_Predicate_immZExt3,
357 : GIPFP_I64_Predicate_immZExt3Ptr,
358 : GIPFP_I64_Predicate_immZExt4,
359 : GIPFP_I64_Predicate_immZExt4Ptr,
360 : GIPFP_I64_Predicate_immZExt5,
361 : GIPFP_I64_Predicate_immZExt5_64,
362 : GIPFP_I64_Predicate_immZExt6,
363 : GIPFP_I64_Predicate_immZExt8,
364 : GIPFP_I64_Predicate_immZExtAndi16,
365 : GIPFP_I64_Predicate_immi32Cst15,
366 : GIPFP_I64_Predicate_immi32Cst31,
367 : GIPFP_I64_Predicate_immi32Cst7,
368 : };
369 14 : bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
370 14 : switch (PredicateID) {
371 0 : case GIPFP_I64_Predicate_immLi16: {
372 0 : return Imm >= -1 && Imm <= 126;
373 : llvm_unreachable("ImmediateCode should have returned");
374 : return false;
375 : }
376 : case GIPFP_I64_Predicate_immSExt10: {
377 0 : return isInt<10>(Imm);
378 : llvm_unreachable("ImmediateCode should have returned");
379 : return false;
380 : }
381 : case GIPFP_I64_Predicate_immSExt6: {
382 0 : return isInt<6>(Imm);
383 : llvm_unreachable("ImmediateCode should have returned");
384 : return false;
385 : }
386 0 : case GIPFP_I64_Predicate_immSExtAddiur2: {
387 0 : return Imm == 1 || Imm == -1 ||
388 0 : ((Imm % 4 == 0) &&
389 0 : Imm < 28 && Imm > 0);
390 : llvm_unreachable("ImmediateCode should have returned");
391 : return false;
392 : }
393 0 : case GIPFP_I64_Predicate_immSExtAddius5: {
394 0 : return Imm >= -8 && Imm <= 7;
395 : llvm_unreachable("ImmediateCode should have returned");
396 : return false;
397 : }
398 0 : case GIPFP_I64_Predicate_immZExt1: {
399 0 : return isUInt<1>(Imm);
400 : llvm_unreachable("ImmediateCode should have returned");
401 : return false;
402 : }
403 0 : case GIPFP_I64_Predicate_immZExt10: {
404 0 : return isUInt<10>(Imm);
405 : llvm_unreachable("ImmediateCode should have returned");
406 : return false;
407 : }
408 0 : case GIPFP_I64_Predicate_immZExt1Ptr: {
409 0 : return isUInt<1>(Imm);
410 : llvm_unreachable("ImmediateCode should have returned");
411 : return false;
412 : }
413 0 : case GIPFP_I64_Predicate_immZExt2: {
414 0 : return isUInt<2>(Imm);
415 : llvm_unreachable("ImmediateCode should have returned");
416 : return false;
417 : }
418 0 : case GIPFP_I64_Predicate_immZExt2Lsa: {
419 0 : return isUInt<2>(Imm - 1);
420 : llvm_unreachable("ImmediateCode should have returned");
421 : return false;
422 : }
423 0 : case GIPFP_I64_Predicate_immZExt2Ptr: {
424 0 : return isUInt<2>(Imm);
425 : llvm_unreachable("ImmediateCode should have returned");
426 : return false;
427 : }
428 0 : case GIPFP_I64_Predicate_immZExt2Shift: {
429 0 : return Imm >= 1 && Imm <= 8;
430 : llvm_unreachable("ImmediateCode should have returned");
431 : return false;
432 : }
433 0 : case GIPFP_I64_Predicate_immZExt3: {
434 0 : return isUInt<3>(Imm);
435 : llvm_unreachable("ImmediateCode should have returned");
436 : return false;
437 : }
438 0 : case GIPFP_I64_Predicate_immZExt3Ptr: {
439 0 : return isUInt<3>(Imm);
440 : llvm_unreachable("ImmediateCode should have returned");
441 : return false;
442 : }
443 0 : case GIPFP_I64_Predicate_immZExt4: {
444 0 : return isUInt<4>(Imm);
445 : llvm_unreachable("ImmediateCode should have returned");
446 : return false;
447 : }
448 0 : case GIPFP_I64_Predicate_immZExt4Ptr: {
449 0 : return isUInt<4>(Imm);
450 : llvm_unreachable("ImmediateCode should have returned");
451 : return false;
452 : }
453 14 : case GIPFP_I64_Predicate_immZExt5: {
454 14 : return Imm == (Imm & 0x1f);
455 : llvm_unreachable("ImmediateCode should have returned");
456 : return false;
457 : }
458 0 : case GIPFP_I64_Predicate_immZExt5_64: {
459 0 : return Imm == (Imm & 0x1f);
460 : llvm_unreachable("ImmediateCode should have returned");
461 : return false;
462 : }
463 0 : case GIPFP_I64_Predicate_immZExt6: {
464 0 : return Imm == (Imm & 0x3f);
465 : llvm_unreachable("ImmediateCode should have returned");
466 : return false;
467 : }
468 0 : case GIPFP_I64_Predicate_immZExt8: {
469 0 : return isUInt<8>(Imm);
470 : llvm_unreachable("ImmediateCode should have returned");
471 : return false;
472 : }
473 0 : case GIPFP_I64_Predicate_immZExtAndi16: {
474 0 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
475 0 : Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
476 0 : Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
477 : llvm_unreachable("ImmediateCode should have returned");
478 : return false;
479 : }
480 0 : case GIPFP_I64_Predicate_immi32Cst15: {
481 0 : return isUInt<32>(Imm) && Imm == 15;
482 : llvm_unreachable("ImmediateCode should have returned");
483 : return false;
484 : }
485 0 : case GIPFP_I64_Predicate_immi32Cst31: {
486 0 : return isUInt<32>(Imm) && Imm == 31;
487 : llvm_unreachable("ImmediateCode should have returned");
488 : return false;
489 : }
490 0 : case GIPFP_I64_Predicate_immi32Cst7: {
491 0 : return isUInt<32>(Imm) && Imm == 7;
492 : llvm_unreachable("ImmediateCode should have returned");
493 : return false;
494 : }
495 : }
496 0 : llvm_unreachable("Unknown predicate");
497 : return false;
498 : }
499 0 : bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
500 0 : llvm_unreachable("Unknown predicate");
501 : return false;
502 : }
503 0 : bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
504 0 : llvm_unreachable("Unknown predicate");
505 : return false;
506 : }
507 0 : bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
508 : const MachineFunction &MF = *MI.getParent()->getParent();
509 : const MachineRegisterInfo &MRI = MF.getRegInfo();
510 : (void)MRI;
511 0 : llvm_unreachable("Unknown predicate");
512 : return false;
513 : }
514 :
515 : MipsInstructionSelector::ComplexMatcherMemFn
516 : MipsInstructionSelector::ComplexPredicateFns[] = {
517 : nullptr, // GICP_Invalid
518 : };
519 :
520 : // Custom renderers.
521 : enum {
522 : GICR_Invalid,
523 : };
524 : MipsInstructionSelector::CustomRendererFn
525 : MipsInstructionSelector::CustomRenderers[] = {
526 : nullptr, // GICP_Invalid
527 : };
528 :
529 144 : bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
530 144 : MachineFunction &MF = *I.getParent()->getParent();
531 144 : MachineRegisterInfo &MRI = MF.getRegInfo();
532 : // FIXME: This should be computed on a per-function basis rather than per-insn.
533 144 : AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
534 144 : const PredicateBitset AvailableFeatures = getAvailableFeatures();
535 : NewMIVector OutMIs;
536 : State.MIs.clear();
537 144 : State.MIs.push_back(&I);
538 :
539 144 : if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
540 64 : return true;
541 : }
542 :
543 : return false;
544 : }
545 :
546 0 : const int64_t *MipsInstructionSelector::getMatchTable() const {
547 : constexpr static int64_t MatchTable0[] = {
548 : GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 42*/ 38274,
549 : /*TargetOpcode::G_ADD*//*Label 0*/ 106,
550 : /*TargetOpcode::G_SUB*//*Label 1*/ 1283,
551 : /*TargetOpcode::G_MUL*//*Label 2*/ 1895,
552 : /*TargetOpcode::G_SDIV*//*Label 3*/ 2271,
553 : /*TargetOpcode::G_UDIV*//*Label 4*/ 2492,
554 : /*TargetOpcode::G_SREM*//*Label 5*/ 2713,
555 : /*TargetOpcode::G_UREM*//*Label 6*/ 2934,
556 : /*TargetOpcode::G_AND*//*Label 7*/ 3155,
557 : /*TargetOpcode::G_OR*//*Label 8*/ 3599,
558 : /*TargetOpcode::G_XOR*//*Label 9*/ 3901, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
559 : /*TargetOpcode::G_BITCAST*//*Label 10*/ 4695, 0, 0,
560 : /*TargetOpcode::G_LOAD*//*Label 11*/ 8348,
561 : /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8414,
562 : /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8480, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
563 : /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8546,
564 : /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25057, 0,
565 : /*TargetOpcode::G_TRUNC*//*Label 16*/ 29981,
566 : /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30038, 0, 0, 0,
567 : /*TargetOpcode::G_SEXT*//*Label 18*/ 30098,
568 : /*TargetOpcode::G_ZEXT*//*Label 19*/ 30126,
569 : /*TargetOpcode::G_SHL*//*Label 20*/ 30211,
570 : /*TargetOpcode::G_LSHR*//*Label 21*/ 30735,
571 : /*TargetOpcode::G_ASHR*//*Label 22*/ 31259, 0, 0,
572 : /*TargetOpcode::G_SELECT*//*Label 23*/ 31740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
573 : /*TargetOpcode::G_FADD*//*Label 24*/ 33194,
574 : /*TargetOpcode::G_FSUB*//*Label 25*/ 34073,
575 : /*TargetOpcode::G_FMUL*//*Label 26*/ 34649,
576 : /*TargetOpcode::G_FMA*//*Label 27*/ 35086,
577 : /*TargetOpcode::G_FDIV*//*Label 28*/ 35176, 0, 0, 0,
578 : /*TargetOpcode::G_FEXP2*//*Label 29*/ 35427, 0,
579 : /*TargetOpcode::G_FLOG2*//*Label 30*/ 35485,
580 : /*TargetOpcode::G_FNEG*//*Label 31*/ 35543,
581 : /*TargetOpcode::G_FPEXT*//*Label 32*/ 36839,
582 : /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36988,
583 : /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37116,
584 : /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37174,
585 : /*TargetOpcode::G_SITOFP*//*Label 36*/ 37232,
586 : /*TargetOpcode::G_UITOFP*//*Label 37*/ 37385, 0, 0, 0,
587 : /*TargetOpcode::G_BR*//*Label 38*/ 37443, 0, 0, 0, 0, 0,
588 : /*TargetOpcode::G_CTLZ*//*Label 39*/ 37528, 0,
589 : /*TargetOpcode::G_CTPOP*//*Label 40*/ 37963,
590 : /*TargetOpcode::G_BSWAP*//*Label 41*/ 38122,
591 : // Label 0: @106
592 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 51*/ 1282,
593 : /*GILLT_s32*//*Label 43*/ 120,
594 : /*GILLT_s64*//*Label 44*/ 469,
595 : /*GILLT_v2s16*//*Label 45*/ 632,
596 : /*GILLT_v2s64*//*Label 46*/ 659,
597 : /*GILLT_v4s8*//*Label 47*/ 808,
598 : /*GILLT_v4s32*//*Label 48*/ 835,
599 : /*GILLT_v8s16*//*Label 49*/ 984,
600 : /*GILLT_v16s8*//*Label 50*/ 1133,
601 : // Label 43: @120
602 : GIM_Try, /*On fail goto*//*Label 52*/ 468,
603 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
605 : GIM_Try, /*On fail goto*//*Label 53*/ 198, // Rule ID 2309 //
606 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
608 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
609 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
610 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
611 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
612 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
613 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
614 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
615 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
616 : // MIs[2] Operand 1
617 : // No operand predicates
618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
619 : GIM_CheckIsSafeToFold, /*InsnID*/1,
620 : GIM_CheckIsSafeToFold, /*InsnID*/2,
621 : // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
622 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
623 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
624 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
626 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
627 : GIR_EraseFromParent, /*InsnID*/0,
628 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
629 : // GIR_Coverage, 2309,
630 : GIR_Done,
631 : // Label 53: @198
632 : GIM_Try, /*On fail goto*//*Label 54*/ 266, // Rule ID 802 //
633 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
634 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
636 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
637 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
638 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
639 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
640 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
641 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
642 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
643 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
644 : // MIs[2] Operand 1
645 : // No operand predicates
646 : GIM_CheckIsSafeToFold, /*InsnID*/1,
647 : GIM_CheckIsSafeToFold, /*InsnID*/2,
648 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
649 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
650 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
651 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
652 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
653 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
654 : GIR_EraseFromParent, /*InsnID*/0,
655 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
656 : // GIR_Coverage, 802,
657 : GIR_Done,
658 : // Label 54: @266
659 : GIM_Try, /*On fail goto*//*Label 55*/ 309, // Rule ID 2084 //
660 : GIM_CheckFeatures, GIFBS_InMicroMips,
661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
662 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
663 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
664 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
665 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
666 : // MIs[1] Operand 1
667 : // No operand predicates
668 : GIM_CheckIsSafeToFold, /*InsnID*/1,
669 : // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
670 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
671 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
672 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
673 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
674 : GIR_EraseFromParent, /*InsnID*/0,
675 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
676 : // GIR_Coverage, 2084,
677 : GIR_Done,
678 : // Label 55: @309
679 : GIM_Try, /*On fail goto*//*Label 56*/ 352, // Rule ID 2085 //
680 : GIM_CheckFeatures, GIFBS_InMicroMips,
681 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
682 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
683 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
684 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
685 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
686 : // MIs[1] Operand 1
687 : // No operand predicates
688 : GIM_CheckIsSafeToFold, /*InsnID*/1,
689 : // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
690 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
691 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
692 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
693 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
694 : GIR_EraseFromParent, /*InsnID*/0,
695 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
696 : // GIR_Coverage, 2085,
697 : GIR_Done,
698 : // Label 56: @352
699 : GIM_Try, /*On fail goto*//*Label 57*/ 375, // Rule ID 1174 //
700 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
704 : // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
705 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
706 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
707 : // GIR_Coverage, 1174,
708 : GIR_Done,
709 : // Label 57: @375
710 : GIM_Try, /*On fail goto*//*Label 58*/ 398, // Rule ID 34 //
711 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
712 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
713 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
715 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
716 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
717 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
718 : // GIR_Coverage, 34,
719 : GIR_Done,
720 : // Label 58: @398
721 : GIM_Try, /*On fail goto*//*Label 59*/ 421, // Rule ID 1028 //
722 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
723 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
724 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
726 : // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
727 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
728 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
729 : // GIR_Coverage, 1028,
730 : GIR_Done,
731 : // Label 59: @421
732 : GIM_Try, /*On fail goto*//*Label 60*/ 444, // Rule ID 1040 //
733 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
734 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
735 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
736 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
737 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
738 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
739 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
740 : // GIR_Coverage, 1040,
741 : GIR_Done,
742 : // Label 60: @444
743 : GIM_Try, /*On fail goto*//*Label 61*/ 467, // Rule ID 1745 //
744 : GIM_CheckFeatures, GIFBS_InMips16Mode,
745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
747 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
748 : // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
749 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
750 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
751 : // GIR_Coverage, 1745,
752 : GIR_Done,
753 : // Label 61: @467
754 : GIM_Reject,
755 : // Label 52: @468
756 : GIM_Reject,
757 : // Label 44: @469
758 : GIM_Try, /*On fail goto*//*Label 62*/ 631,
759 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
760 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
762 : GIM_Try, /*On fail goto*//*Label 63*/ 547, // Rule ID 2310 //
763 : GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
764 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
765 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
766 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
767 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
768 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
769 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
770 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
771 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
772 : // MIs[2] Operand 1
773 : // No operand predicates
774 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
775 : GIM_CheckIsSafeToFold, /*InsnID*/1,
776 : GIM_CheckIsSafeToFold, /*InsnID*/2,
777 : // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
778 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
779 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
780 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
781 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
782 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
783 : GIR_EraseFromParent, /*InsnID*/0,
784 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
785 : // GIR_Coverage, 2310,
786 : GIR_Done,
787 : // Label 63: @547
788 : GIM_Try, /*On fail goto*//*Label 64*/ 611, // Rule ID 803 //
789 : GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
790 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
791 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
792 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
793 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
794 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
795 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
796 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
797 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
798 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
799 : // MIs[2] Operand 1
800 : // No operand predicates
801 : GIM_CheckIsSafeToFold, /*InsnID*/1,
802 : GIM_CheckIsSafeToFold, /*InsnID*/2,
803 : // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
804 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
805 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
807 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
808 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
809 : GIR_EraseFromParent, /*InsnID*/0,
810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
811 : // GIR_Coverage, 803,
812 : GIR_Done,
813 : // Label 64: @611
814 : GIM_Try, /*On fail goto*//*Label 65*/ 630, // Rule ID 180 //
815 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
818 : // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
819 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
820 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
821 : // GIR_Coverage, 180,
822 : GIR_Done,
823 : // Label 65: @630
824 : GIM_Reject,
825 : // Label 62: @631
826 : GIM_Reject,
827 : // Label 45: @632
828 : GIM_Try, /*On fail goto*//*Label 66*/ 658, // Rule ID 1844 //
829 : GIM_CheckFeatures, GIFBS_HasDSP,
830 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
831 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
832 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
833 : // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
834 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
835 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
836 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
837 : // GIR_Coverage, 1844,
838 : GIR_Done,
839 : // Label 66: @658
840 : GIM_Reject,
841 : // Label 46: @659
842 : GIM_Try, /*On fail goto*//*Label 67*/ 807,
843 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
844 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
845 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
846 : GIM_Try, /*On fail goto*//*Label 68*/ 730, // Rule ID 2314 //
847 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
848 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
849 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
850 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
851 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
852 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
853 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
855 : GIM_CheckIsSafeToFold, /*InsnID*/1,
856 : // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
857 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
859 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
860 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
861 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
862 : GIR_EraseFromParent, /*InsnID*/0,
863 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
864 : // GIR_Coverage, 2314,
865 : GIR_Done,
866 : // Label 68: @730
867 : GIM_Try, /*On fail goto*//*Label 69*/ 787, // Rule ID 811 //
868 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
869 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
870 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
871 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
872 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
873 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
874 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
875 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
876 : GIM_CheckIsSafeToFold, /*InsnID*/1,
877 : // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
878 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
880 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
881 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
883 : GIR_EraseFromParent, /*InsnID*/0,
884 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885 : // GIR_Coverage, 811,
886 : GIR_Done,
887 : // Label 69: @787
888 : GIM_Try, /*On fail goto*//*Label 70*/ 806, // Rule ID 478 //
889 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
892 : // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
893 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
894 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
895 : // GIR_Coverage, 478,
896 : GIR_Done,
897 : // Label 70: @806
898 : GIM_Reject,
899 : // Label 67: @807
900 : GIM_Reject,
901 : // Label 47: @808
902 : GIM_Try, /*On fail goto*//*Label 71*/ 834, // Rule ID 1850 //
903 : GIM_CheckFeatures, GIFBS_HasDSP,
904 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
905 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
906 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
907 : // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
908 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
909 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
910 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
911 : // GIR_Coverage, 1850,
912 : GIR_Done,
913 : // Label 71: @834
914 : GIM_Reject,
915 : // Label 48: @835
916 : GIM_Try, /*On fail goto*//*Label 72*/ 983,
917 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
918 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
919 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
920 : GIM_Try, /*On fail goto*//*Label 73*/ 906, // Rule ID 2313 //
921 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
922 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
923 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
924 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
925 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
926 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
927 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
928 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
929 : GIM_CheckIsSafeToFold, /*InsnID*/1,
930 : // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
931 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
932 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
935 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
936 : GIR_EraseFromParent, /*InsnID*/0,
937 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
938 : // GIR_Coverage, 2313,
939 : GIR_Done,
940 : // Label 73: @906
941 : GIM_Try, /*On fail goto*//*Label 74*/ 963, // Rule ID 810 //
942 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
943 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
944 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
946 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
947 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
948 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
949 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
950 : GIM_CheckIsSafeToFold, /*InsnID*/1,
951 : // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
952 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
954 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
955 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
956 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
957 : GIR_EraseFromParent, /*InsnID*/0,
958 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
959 : // GIR_Coverage, 810,
960 : GIR_Done,
961 : // Label 74: @963
962 : GIM_Try, /*On fail goto*//*Label 75*/ 982, // Rule ID 477 //
963 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
964 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
966 : // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
967 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
968 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
969 : // GIR_Coverage, 477,
970 : GIR_Done,
971 : // Label 75: @982
972 : GIM_Reject,
973 : // Label 72: @983
974 : GIM_Reject,
975 : // Label 49: @984
976 : GIM_Try, /*On fail goto*//*Label 76*/ 1132,
977 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
978 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
979 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
980 : GIM_Try, /*On fail goto*//*Label 77*/ 1055, // Rule ID 2312 //
981 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
982 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
984 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
985 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
986 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
987 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
988 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
989 : GIM_CheckIsSafeToFold, /*InsnID*/1,
990 : // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
991 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
992 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
993 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
994 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
995 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
996 : GIR_EraseFromParent, /*InsnID*/0,
997 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
998 : // GIR_Coverage, 2312,
999 : GIR_Done,
1000 : // Label 77: @1055
1001 : GIM_Try, /*On fail goto*//*Label 78*/ 1112, // Rule ID 809 //
1002 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1004 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1005 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1006 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1007 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1008 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1009 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1010 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1011 : // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1012 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1013 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1014 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1015 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1016 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1017 : GIR_EraseFromParent, /*InsnID*/0,
1018 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1019 : // GIR_Coverage, 809,
1020 : GIR_Done,
1021 : // Label 78: @1112
1022 : GIM_Try, /*On fail goto*//*Label 79*/ 1131, // Rule ID 476 //
1023 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1026 : // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1027 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1028 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1029 : // GIR_Coverage, 476,
1030 : GIR_Done,
1031 : // Label 79: @1131
1032 : GIM_Reject,
1033 : // Label 76: @1132
1034 : GIM_Reject,
1035 : // Label 50: @1133
1036 : GIM_Try, /*On fail goto*//*Label 80*/ 1281,
1037 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1038 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1039 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1040 : GIM_Try, /*On fail goto*//*Label 81*/ 1204, // Rule ID 2311 //
1041 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1042 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1043 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1045 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1046 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1047 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1048 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1049 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1050 : // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1051 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1052 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1054 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1055 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1056 : GIR_EraseFromParent, /*InsnID*/0,
1057 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058 : // GIR_Coverage, 2311,
1059 : GIR_Done,
1060 : // Label 81: @1204
1061 : GIM_Try, /*On fail goto*//*Label 82*/ 1261, // Rule ID 808 //
1062 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1063 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1064 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1065 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1066 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1067 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1068 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1069 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1070 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1071 : // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1072 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1073 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1074 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1075 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077 : GIR_EraseFromParent, /*InsnID*/0,
1078 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1079 : // GIR_Coverage, 808,
1080 : GIR_Done,
1081 : // Label 82: @1261
1082 : GIM_Try, /*On fail goto*//*Label 83*/ 1280, // Rule ID 475 //
1083 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1086 : // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1087 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1089 : // GIR_Coverage, 475,
1090 : GIR_Done,
1091 : // Label 83: @1280
1092 : GIM_Reject,
1093 : // Label 80: @1281
1094 : GIM_Reject,
1095 : // Label 51: @1282
1096 : GIM_Reject,
1097 : // Label 1: @1283
1098 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 92*/ 1894,
1099 : /*GILLT_s32*//*Label 84*/ 1297,
1100 : /*GILLT_s64*//*Label 85*/ 1456,
1101 : /*GILLT_v2s16*//*Label 86*/ 1488,
1102 : /*GILLT_v2s64*//*Label 87*/ 1515,
1103 : /*GILLT_v4s8*//*Label 88*/ 1603,
1104 : /*GILLT_v4s32*//*Label 89*/ 1630,
1105 : /*GILLT_v8s16*//*Label 90*/ 1718,
1106 : /*GILLT_v16s8*//*Label 91*/ 1806,
1107 : // Label 84: @1297
1108 : GIM_Try, /*On fail goto*//*Label 93*/ 1455,
1109 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1110 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1111 : GIM_Try, /*On fail goto*//*Label 94*/ 1339, // Rule ID 1744 //
1112 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1113 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1114 : GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1115 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1116 : // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1117 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1120 : GIR_EraseFromParent, /*InsnID*/0,
1121 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1122 : // GIR_Coverage, 1744,
1123 : GIR_Done,
1124 : // Label 94: @1339
1125 : GIM_Try, /*On fail goto*//*Label 95*/ 1362, // Rule ID 1176 //
1126 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1127 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1128 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1129 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1130 : // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1131 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1132 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1133 : // GIR_Coverage, 1176,
1134 : GIR_Done,
1135 : // Label 95: @1362
1136 : GIM_Try, /*On fail goto*//*Label 96*/ 1385, // Rule ID 35 //
1137 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1139 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1140 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1141 : // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1142 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1143 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1144 : // GIR_Coverage, 35,
1145 : GIR_Done,
1146 : // Label 96: @1385
1147 : GIM_Try, /*On fail goto*//*Label 97*/ 1408, // Rule ID 1032 //
1148 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1149 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1150 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1151 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1152 : // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1153 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1154 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1155 : // GIR_Coverage, 1032,
1156 : GIR_Done,
1157 : // Label 97: @1408
1158 : GIM_Try, /*On fail goto*//*Label 98*/ 1431, // Rule ID 1041 //
1159 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1160 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1163 : // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1164 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1165 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1166 : // GIR_Coverage, 1041,
1167 : GIR_Done,
1168 : // Label 98: @1431
1169 : GIM_Try, /*On fail goto*//*Label 99*/ 1454, // Rule ID 1749 //
1170 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1171 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1172 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1173 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1174 : // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1175 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1176 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1177 : // GIR_Coverage, 1749,
1178 : GIR_Done,
1179 : // Label 99: @1454
1180 : GIM_Reject,
1181 : // Label 93: @1455
1182 : GIM_Reject,
1183 : // Label 85: @1456
1184 : GIM_Try, /*On fail goto*//*Label 100*/ 1487, // Rule ID 181 //
1185 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1186 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1187 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1188 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1189 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1190 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1191 : // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1192 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1193 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194 : // GIR_Coverage, 181,
1195 : GIR_Done,
1196 : // Label 100: @1487
1197 : GIM_Reject,
1198 : // Label 86: @1488
1199 : GIM_Try, /*On fail goto*//*Label 101*/ 1514, // Rule ID 1846 //
1200 : GIM_CheckFeatures, GIFBS_HasDSP,
1201 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1202 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1203 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1204 : // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1205 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1206 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1207 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1208 : // GIR_Coverage, 1846,
1209 : GIR_Done,
1210 : // Label 101: @1514
1211 : GIM_Reject,
1212 : // Label 87: @1515
1213 : GIM_Try, /*On fail goto*//*Label 102*/ 1602,
1214 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1215 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1216 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1217 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1218 : GIM_Try, /*On fail goto*//*Label 103*/ 1586, // Rule ID 867 //
1219 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1220 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1223 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1224 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1225 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1226 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1227 : // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1228 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1229 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1230 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1233 : GIR_EraseFromParent, /*InsnID*/0,
1234 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1235 : // GIR_Coverage, 867,
1236 : GIR_Done,
1237 : // Label 103: @1586
1238 : GIM_Try, /*On fail goto*//*Label 104*/ 1601, // Rule ID 996 //
1239 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1240 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1241 : // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1242 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1243 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244 : // GIR_Coverage, 996,
1245 : GIR_Done,
1246 : // Label 104: @1601
1247 : GIM_Reject,
1248 : // Label 102: @1602
1249 : GIM_Reject,
1250 : // Label 88: @1603
1251 : GIM_Try, /*On fail goto*//*Label 105*/ 1629, // Rule ID 1852 //
1252 : GIM_CheckFeatures, GIFBS_HasDSP,
1253 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1254 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1255 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1256 : // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1257 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1258 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1260 : // GIR_Coverage, 1852,
1261 : GIR_Done,
1262 : // Label 105: @1629
1263 : GIM_Reject,
1264 : // Label 89: @1630
1265 : GIM_Try, /*On fail goto*//*Label 106*/ 1717,
1266 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1267 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1268 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1270 : GIM_Try, /*On fail goto*//*Label 107*/ 1701, // Rule ID 866 //
1271 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1272 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1273 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1274 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1275 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1276 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1277 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1278 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1279 : // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1280 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1282 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1283 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1284 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1285 : GIR_EraseFromParent, /*InsnID*/0,
1286 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287 : // GIR_Coverage, 866,
1288 : GIR_Done,
1289 : // Label 107: @1701
1290 : GIM_Try, /*On fail goto*//*Label 108*/ 1716, // Rule ID 995 //
1291 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1292 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1293 : // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1294 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1295 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1296 : // GIR_Coverage, 995,
1297 : GIR_Done,
1298 : // Label 108: @1716
1299 : GIM_Reject,
1300 : // Label 106: @1717
1301 : GIM_Reject,
1302 : // Label 90: @1718
1303 : GIM_Try, /*On fail goto*//*Label 109*/ 1805,
1304 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1306 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1307 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1308 : GIM_Try, /*On fail goto*//*Label 110*/ 1789, // Rule ID 865 //
1309 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1310 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1311 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1312 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1313 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1314 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1315 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1316 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1317 : // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1318 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1321 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1322 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1323 : GIR_EraseFromParent, /*InsnID*/0,
1324 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1325 : // GIR_Coverage, 865,
1326 : GIR_Done,
1327 : // Label 110: @1789
1328 : GIM_Try, /*On fail goto*//*Label 111*/ 1804, // Rule ID 994 //
1329 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1330 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1331 : // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1332 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1333 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334 : // GIR_Coverage, 994,
1335 : GIR_Done,
1336 : // Label 111: @1804
1337 : GIM_Reject,
1338 : // Label 109: @1805
1339 : GIM_Reject,
1340 : // Label 91: @1806
1341 : GIM_Try, /*On fail goto*//*Label 112*/ 1893,
1342 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1343 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1344 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1345 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1346 : GIM_Try, /*On fail goto*//*Label 113*/ 1877, // Rule ID 864 //
1347 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1348 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1349 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1350 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1351 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1352 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1353 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1354 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1355 : // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1358 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1359 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1360 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1361 : GIR_EraseFromParent, /*InsnID*/0,
1362 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1363 : // GIR_Coverage, 864,
1364 : GIR_Done,
1365 : // Label 113: @1877
1366 : GIM_Try, /*On fail goto*//*Label 114*/ 1892, // Rule ID 993 //
1367 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1368 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1369 : // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1370 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1371 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1372 : // GIR_Coverage, 993,
1373 : GIR_Done,
1374 : // Label 114: @1892
1375 : GIM_Reject,
1376 : // Label 112: @1893
1377 : GIM_Reject,
1378 : // Label 92: @1894
1379 : GIM_Reject,
1380 : // Label 2: @1895
1381 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 122*/ 2270,
1382 : /*GILLT_s32*//*Label 115*/ 1909,
1383 : /*GILLT_s64*//*Label 116*/ 2054,
1384 : /*GILLT_v2s16*//*Label 117*/ 2115,
1385 : /*GILLT_v2s64*//*Label 118*/ 2142, 0,
1386 : /*GILLT_v4s32*//*Label 119*/ 2174,
1387 : /*GILLT_v8s16*//*Label 120*/ 2206,
1388 : /*GILLT_v16s8*//*Label 121*/ 2238,
1389 : // Label 115: @1909
1390 : GIM_Try, /*On fail goto*//*Label 123*/ 2053,
1391 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1392 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1393 : GIM_Try, /*On fail goto*//*Label 124*/ 1948, // Rule ID 36 //
1394 : GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1395 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1396 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1397 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1398 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1399 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1400 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1401 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1402 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1403 : // GIR_Coverage, 36,
1404 : GIR_Done,
1405 : // Label 124: @1948
1406 : GIM_Try, /*On fail goto*//*Label 125*/ 1971, // Rule ID 304 //
1407 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1408 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1410 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1411 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1412 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1413 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1414 : // GIR_Coverage, 304,
1415 : GIR_Done,
1416 : // Label 125: @1971
1417 : GIM_Try, /*On fail goto*//*Label 126*/ 2000, // Rule ID 1042 //
1418 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1420 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1422 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1423 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1424 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1425 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1426 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1427 : // GIR_Coverage, 1042,
1428 : GIR_Done,
1429 : // Label 126: @2000
1430 : GIM_Try, /*On fail goto*//*Label 127*/ 2023, // Rule ID 1145 //
1431 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1432 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1433 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1435 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1436 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1437 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1438 : // GIR_Coverage, 1145,
1439 : GIR_Done,
1440 : // Label 127: @2023
1441 : GIM_Try, /*On fail goto*//*Label 128*/ 2052, // Rule ID 1747 //
1442 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1444 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1445 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1446 : // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1447 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1448 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1449 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1451 : // GIR_Coverage, 1747,
1452 : GIR_Done,
1453 : // Label 128: @2052
1454 : GIM_Reject,
1455 : // Label 123: @2053
1456 : GIM_Reject,
1457 : // Label 116: @2054
1458 : GIM_Try, /*On fail goto*//*Label 129*/ 2114,
1459 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1460 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1461 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1462 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1464 : GIM_Try, /*On fail goto*//*Label 130*/ 2102, // Rule ID 246 //
1465 : GIM_CheckFeatures, GIFBS_HasCnMips,
1466 : // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1467 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1468 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1469 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1470 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1471 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1472 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1473 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1474 : // GIR_Coverage, 246,
1475 : GIR_Done,
1476 : // Label 130: @2102
1477 : GIM_Try, /*On fail goto*//*Label 131*/ 2113, // Rule ID 319 //
1478 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1479 : // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1480 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1481 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482 : // GIR_Coverage, 319,
1483 : GIR_Done,
1484 : // Label 131: @2113
1485 : GIM_Reject,
1486 : // Label 129: @2114
1487 : GIM_Reject,
1488 : // Label 117: @2115
1489 : GIM_Try, /*On fail goto*//*Label 132*/ 2141, // Rule ID 1848 //
1490 : GIM_CheckFeatures, GIFBS_HasDSPR2,
1491 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1492 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1493 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1494 : // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1495 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1496 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1497 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1498 : // GIR_Coverage, 1848,
1499 : GIR_Done,
1500 : // Label 132: @2141
1501 : GIM_Reject,
1502 : // Label 118: @2142
1503 : GIM_Try, /*On fail goto*//*Label 133*/ 2173, // Rule ID 875 //
1504 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1505 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1506 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1507 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1508 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1509 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1510 : // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1511 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1512 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1513 : // GIR_Coverage, 875,
1514 : GIR_Done,
1515 : // Label 133: @2173
1516 : GIM_Reject,
1517 : // Label 119: @2174
1518 : GIM_Try, /*On fail goto*//*Label 134*/ 2205, // Rule ID 874 //
1519 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1520 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1521 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1522 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1523 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1525 : // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1526 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1527 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528 : // GIR_Coverage, 874,
1529 : GIR_Done,
1530 : // Label 134: @2205
1531 : GIM_Reject,
1532 : // Label 120: @2206
1533 : GIM_Try, /*On fail goto*//*Label 135*/ 2237, // Rule ID 873 //
1534 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1535 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1536 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1538 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1539 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1540 : // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1541 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1542 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1543 : // GIR_Coverage, 873,
1544 : GIR_Done,
1545 : // Label 135: @2237
1546 : GIM_Reject,
1547 : // Label 121: @2238
1548 : GIM_Try, /*On fail goto*//*Label 136*/ 2269, // Rule ID 872 //
1549 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1550 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1551 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1552 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1553 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1555 : // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1556 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1557 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1558 : // GIR_Coverage, 872,
1559 : GIR_Done,
1560 : // Label 136: @2269
1561 : GIM_Reject,
1562 : // Label 122: @2270
1563 : GIM_Reject,
1564 : // Label 3: @2271
1565 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 143*/ 2491,
1566 : /*GILLT_s32*//*Label 137*/ 2285,
1567 : /*GILLT_s64*//*Label 138*/ 2331, 0,
1568 : /*GILLT_v2s64*//*Label 139*/ 2363, 0,
1569 : /*GILLT_v4s32*//*Label 140*/ 2395,
1570 : /*GILLT_v8s16*//*Label 141*/ 2427,
1571 : /*GILLT_v16s8*//*Label 142*/ 2459,
1572 : // Label 137: @2285
1573 : GIM_Try, /*On fail goto*//*Label 144*/ 2330,
1574 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1575 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1576 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1577 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1578 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1579 : GIM_Try, /*On fail goto*//*Label 145*/ 2318, // Rule ID 298 //
1580 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1581 : // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1582 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1583 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1584 : // GIR_Coverage, 298,
1585 : GIR_Done,
1586 : // Label 145: @2318
1587 : GIM_Try, /*On fail goto*//*Label 146*/ 2329, // Rule ID 1138 //
1588 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1589 : // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1590 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1591 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1592 : // GIR_Coverage, 1138,
1593 : GIR_Done,
1594 : // Label 146: @2329
1595 : GIM_Reject,
1596 : // Label 144: @2330
1597 : GIM_Reject,
1598 : // Label 138: @2331
1599 : GIM_Try, /*On fail goto*//*Label 147*/ 2362, // Rule ID 313 //
1600 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1601 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1602 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1603 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1604 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1605 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1606 : // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1607 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1608 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1609 : // GIR_Coverage, 313,
1610 : GIR_Done,
1611 : // Label 147: @2362
1612 : GIM_Reject,
1613 : // Label 139: @2363
1614 : GIM_Try, /*On fail goto*//*Label 148*/ 2394, // Rule ID 615 //
1615 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1616 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1617 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1619 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1620 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1621 : // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1622 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1623 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624 : // GIR_Coverage, 615,
1625 : GIR_Done,
1626 : // Label 148: @2394
1627 : GIM_Reject,
1628 : // Label 140: @2395
1629 : GIM_Try, /*On fail goto*//*Label 149*/ 2426, // Rule ID 614 //
1630 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1631 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1632 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1633 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1634 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1636 : // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1637 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1638 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639 : // GIR_Coverage, 614,
1640 : GIR_Done,
1641 : // Label 149: @2426
1642 : GIM_Reject,
1643 : // Label 141: @2427
1644 : GIM_Try, /*On fail goto*//*Label 150*/ 2458, // Rule ID 613 //
1645 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1646 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1647 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1648 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1649 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1650 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1651 : // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1652 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1653 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1654 : // GIR_Coverage, 613,
1655 : GIR_Done,
1656 : // Label 150: @2458
1657 : GIM_Reject,
1658 : // Label 142: @2459
1659 : GIM_Try, /*On fail goto*//*Label 151*/ 2490, // Rule ID 612 //
1660 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1661 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1662 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1663 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1664 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1665 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1666 : // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1667 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1668 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1669 : // GIR_Coverage, 612,
1670 : GIR_Done,
1671 : // Label 151: @2490
1672 : GIM_Reject,
1673 : // Label 143: @2491
1674 : GIM_Reject,
1675 : // Label 4: @2492
1676 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 158*/ 2712,
1677 : /*GILLT_s32*//*Label 152*/ 2506,
1678 : /*GILLT_s64*//*Label 153*/ 2552, 0,
1679 : /*GILLT_v2s64*//*Label 154*/ 2584, 0,
1680 : /*GILLT_v4s32*//*Label 155*/ 2616,
1681 : /*GILLT_v8s16*//*Label 156*/ 2648,
1682 : /*GILLT_v16s8*//*Label 157*/ 2680,
1683 : // Label 152: @2506
1684 : GIM_Try, /*On fail goto*//*Label 159*/ 2551,
1685 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1686 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1690 : GIM_Try, /*On fail goto*//*Label 160*/ 2539, // Rule ID 299 //
1691 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1692 : // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1693 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1694 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1695 : // GIR_Coverage, 299,
1696 : GIR_Done,
1697 : // Label 160: @2539
1698 : GIM_Try, /*On fail goto*//*Label 161*/ 2550, // Rule ID 1139 //
1699 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1700 : // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1702 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1703 : // GIR_Coverage, 1139,
1704 : GIR_Done,
1705 : // Label 161: @2550
1706 : GIM_Reject,
1707 : // Label 159: @2551
1708 : GIM_Reject,
1709 : // Label 153: @2552
1710 : GIM_Try, /*On fail goto*//*Label 162*/ 2583, // Rule ID 314 //
1711 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1712 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1713 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1715 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1716 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1717 : // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1718 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1719 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1720 : // GIR_Coverage, 314,
1721 : GIR_Done,
1722 : // Label 162: @2583
1723 : GIM_Reject,
1724 : // Label 154: @2584
1725 : GIM_Try, /*On fail goto*//*Label 163*/ 2615, // Rule ID 619 //
1726 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1727 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1728 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1729 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1730 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1731 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1732 : // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1733 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1734 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1735 : // GIR_Coverage, 619,
1736 : GIR_Done,
1737 : // Label 163: @2615
1738 : GIM_Reject,
1739 : // Label 155: @2616
1740 : GIM_Try, /*On fail goto*//*Label 164*/ 2647, // Rule ID 618 //
1741 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1742 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1743 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1747 : // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1748 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1749 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1750 : // GIR_Coverage, 618,
1751 : GIR_Done,
1752 : // Label 164: @2647
1753 : GIM_Reject,
1754 : // Label 156: @2648
1755 : GIM_Try, /*On fail goto*//*Label 165*/ 2679, // Rule ID 617 //
1756 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1757 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1758 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1759 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1762 : // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1763 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1764 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1765 : // GIR_Coverage, 617,
1766 : GIR_Done,
1767 : // Label 165: @2679
1768 : GIM_Reject,
1769 : // Label 157: @2680
1770 : GIM_Try, /*On fail goto*//*Label 166*/ 2711, // Rule ID 616 //
1771 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1772 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1773 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1774 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1775 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1776 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1777 : // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1778 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1779 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780 : // GIR_Coverage, 616,
1781 : GIR_Done,
1782 : // Label 166: @2711
1783 : GIM_Reject,
1784 : // Label 158: @2712
1785 : GIM_Reject,
1786 : // Label 5: @2713
1787 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 173*/ 2933,
1788 : /*GILLT_s32*//*Label 167*/ 2727,
1789 : /*GILLT_s64*//*Label 168*/ 2773, 0,
1790 : /*GILLT_v2s64*//*Label 169*/ 2805, 0,
1791 : /*GILLT_v4s32*//*Label 170*/ 2837,
1792 : /*GILLT_v8s16*//*Label 171*/ 2869,
1793 : /*GILLT_v16s8*//*Label 172*/ 2901,
1794 : // Label 167: @2727
1795 : GIM_Try, /*On fail goto*//*Label 174*/ 2772,
1796 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1797 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1798 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1799 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1800 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1801 : GIM_Try, /*On fail goto*//*Label 175*/ 2760, // Rule ID 300 //
1802 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1803 : // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1804 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1805 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1806 : // GIR_Coverage, 300,
1807 : GIR_Done,
1808 : // Label 175: @2760
1809 : GIM_Try, /*On fail goto*//*Label 176*/ 2771, // Rule ID 1143 //
1810 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1811 : // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1813 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1814 : // GIR_Coverage, 1143,
1815 : GIR_Done,
1816 : // Label 176: @2771
1817 : GIM_Reject,
1818 : // Label 174: @2772
1819 : GIM_Reject,
1820 : // Label 168: @2773
1821 : GIM_Try, /*On fail goto*//*Label 177*/ 2804, // Rule ID 315 //
1822 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1823 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1824 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1825 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1828 : // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1829 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1830 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1831 : // GIR_Coverage, 315,
1832 : GIR_Done,
1833 : // Label 177: @2804
1834 : GIM_Reject,
1835 : // Label 169: @2805
1836 : GIM_Try, /*On fail goto*//*Label 178*/ 2836, // Rule ID 855 //
1837 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1838 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1839 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1842 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1843 : // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1844 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1845 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1846 : // GIR_Coverage, 855,
1847 : GIR_Done,
1848 : // Label 178: @2836
1849 : GIM_Reject,
1850 : // Label 170: @2837
1851 : GIM_Try, /*On fail goto*//*Label 179*/ 2868, // Rule ID 854 //
1852 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1853 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1854 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1855 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1856 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1857 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1858 : // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1859 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1860 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1861 : // GIR_Coverage, 854,
1862 : GIR_Done,
1863 : // Label 179: @2868
1864 : GIM_Reject,
1865 : // Label 171: @2869
1866 : GIM_Try, /*On fail goto*//*Label 180*/ 2900, // Rule ID 853 //
1867 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1868 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1869 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1870 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1871 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1873 : // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1874 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1875 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1876 : // GIR_Coverage, 853,
1877 : GIR_Done,
1878 : // Label 180: @2900
1879 : GIM_Reject,
1880 : // Label 172: @2901
1881 : GIM_Try, /*On fail goto*//*Label 181*/ 2932, // Rule ID 852 //
1882 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1883 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1884 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1885 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1886 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1887 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1888 : // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1889 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1890 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891 : // GIR_Coverage, 852,
1892 : GIR_Done,
1893 : // Label 181: @2932
1894 : GIM_Reject,
1895 : // Label 173: @2933
1896 : GIM_Reject,
1897 : // Label 6: @2934
1898 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 188*/ 3154,
1899 : /*GILLT_s32*//*Label 182*/ 2948,
1900 : /*GILLT_s64*//*Label 183*/ 2994, 0,
1901 : /*GILLT_v2s64*//*Label 184*/ 3026, 0,
1902 : /*GILLT_v4s32*//*Label 185*/ 3058,
1903 : /*GILLT_v8s16*//*Label 186*/ 3090,
1904 : /*GILLT_v16s8*//*Label 187*/ 3122,
1905 : // Label 182: @2948
1906 : GIM_Try, /*On fail goto*//*Label 189*/ 2993,
1907 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1908 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1909 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1911 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1912 : GIM_Try, /*On fail goto*//*Label 190*/ 2981, // Rule ID 301 //
1913 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1914 : // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1915 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1916 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917 : // GIR_Coverage, 301,
1918 : GIR_Done,
1919 : // Label 190: @2981
1920 : GIM_Try, /*On fail goto*//*Label 191*/ 2992, // Rule ID 1144 //
1921 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1922 : // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1923 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1924 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1925 : // GIR_Coverage, 1144,
1926 : GIR_Done,
1927 : // Label 191: @2992
1928 : GIM_Reject,
1929 : // Label 189: @2993
1930 : GIM_Reject,
1931 : // Label 183: @2994
1932 : GIM_Try, /*On fail goto*//*Label 192*/ 3025, // Rule ID 316 //
1933 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1934 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1935 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1936 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1937 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1938 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1939 : // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1940 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1941 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942 : // GIR_Coverage, 316,
1943 : GIR_Done,
1944 : // Label 192: @3025
1945 : GIM_Reject,
1946 : // Label 184: @3026
1947 : GIM_Try, /*On fail goto*//*Label 193*/ 3057, // Rule ID 859 //
1948 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1949 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1950 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1951 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1952 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1953 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1954 : // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1955 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1956 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1957 : // GIR_Coverage, 859,
1958 : GIR_Done,
1959 : // Label 193: @3057
1960 : GIM_Reject,
1961 : // Label 185: @3058
1962 : GIM_Try, /*On fail goto*//*Label 194*/ 3089, // Rule ID 858 //
1963 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1964 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1965 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1968 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1969 : // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1970 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1971 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1972 : // GIR_Coverage, 858,
1973 : GIR_Done,
1974 : // Label 194: @3089
1975 : GIM_Reject,
1976 : // Label 186: @3090
1977 : GIM_Try, /*On fail goto*//*Label 195*/ 3121, // Rule ID 857 //
1978 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1979 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1980 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1981 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1982 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1984 : // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1985 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
1986 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1987 : // GIR_Coverage, 857,
1988 : GIR_Done,
1989 : // Label 195: @3121
1990 : GIM_Reject,
1991 : // Label 187: @3122
1992 : GIM_Try, /*On fail goto*//*Label 196*/ 3153, // Rule ID 856 //
1993 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1994 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1995 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1996 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1997 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1998 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1999 : // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2000 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2001 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2002 : // GIR_Coverage, 856,
2003 : GIR_Done,
2004 : // Label 196: @3153
2005 : GIM_Reject,
2006 : // Label 188: @3154
2007 : GIM_Reject,
2008 : // Label 7: @3155
2009 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 203*/ 3598,
2010 : /*GILLT_s32*//*Label 197*/ 3169,
2011 : /*GILLT_s64*//*Label 198*/ 3382, 0,
2012 : /*GILLT_v2s64*//*Label 199*/ 3470, 0,
2013 : /*GILLT_v4s32*//*Label 200*/ 3502,
2014 : /*GILLT_v8s16*//*Label 201*/ 3534,
2015 : /*GILLT_v16s8*//*Label 202*/ 3566,
2016 : // Label 197: @3169
2017 : GIM_Try, /*On fail goto*//*Label 204*/ 3381,
2018 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2019 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2020 : GIM_Try, /*On fail goto*//*Label 205*/ 3222, // Rule ID 2087 //
2021 : GIM_CheckFeatures, GIFBS_InMicroMips,
2022 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2024 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2025 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2026 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2027 : // MIs[1] Operand 1
2028 : // No operand predicates
2029 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2030 : // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2031 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2032 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2033 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2034 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2035 : GIR_EraseFromParent, /*InsnID*/0,
2036 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2037 : // GIR_Coverage, 2087,
2038 : GIR_Done,
2039 : // Label 205: @3222
2040 : GIM_Try, /*On fail goto*//*Label 206*/ 3265, // Rule ID 2240 //
2041 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2044 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2045 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2046 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2047 : // MIs[1] Operand 1
2048 : // No operand predicates
2049 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2050 : // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2051 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2052 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2054 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2055 : GIR_EraseFromParent, /*InsnID*/0,
2056 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2057 : // GIR_Coverage, 2240,
2058 : GIR_Done,
2059 : // Label 206: @3265
2060 : GIM_Try, /*On fail goto*//*Label 207*/ 3288, // Rule ID 39 //
2061 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2062 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2063 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2065 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2066 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2067 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2068 : // GIR_Coverage, 39,
2069 : GIR_Done,
2070 : // Label 207: @3288
2071 : GIM_Try, /*On fail goto*//*Label 208*/ 3311, // Rule ID 1029 //
2072 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2073 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2075 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2076 : // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2077 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2078 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2079 : // GIR_Coverage, 1029,
2080 : GIR_Done,
2081 : // Label 208: @3311
2082 : GIM_Try, /*On fail goto*//*Label 209*/ 3334, // Rule ID 1045 //
2083 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2087 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2088 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2089 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2090 : // GIR_Coverage, 1045,
2091 : GIR_Done,
2092 : // Label 209: @3334
2093 : GIM_Try, /*On fail goto*//*Label 210*/ 3357, // Rule ID 1136 //
2094 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2095 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2096 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2097 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2098 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2099 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2100 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101 : // GIR_Coverage, 1136,
2102 : GIR_Done,
2103 : // Label 210: @3357
2104 : GIM_Try, /*On fail goto*//*Label 211*/ 3380, // Rule ID 1746 //
2105 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2107 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2108 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2109 : // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2110 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2111 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2112 : // GIR_Coverage, 1746,
2113 : GIR_Done,
2114 : // Label 211: @3380
2115 : GIM_Reject,
2116 : // Label 204: @3381
2117 : GIM_Reject,
2118 : // Label 198: @3382
2119 : GIM_Try, /*On fail goto*//*Label 212*/ 3469,
2120 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2121 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2122 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2123 : GIM_Try, /*On fail goto*//*Label 213*/ 3449, // Rule ID 241 //
2124 : GIM_CheckFeatures, GIFBS_HasCnMips,
2125 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2126 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2127 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2128 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2129 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2130 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2131 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2132 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2133 : // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2134 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2135 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2136 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2137 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2138 : GIR_EraseFromParent, /*InsnID*/0,
2139 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140 : // GIR_Coverage, 241,
2141 : GIR_Done,
2142 : // Label 213: @3449
2143 : GIM_Try, /*On fail goto*//*Label 214*/ 3468, // Rule ID 184 //
2144 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2146 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2147 : // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2148 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2149 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2150 : // GIR_Coverage, 184,
2151 : GIR_Done,
2152 : // Label 214: @3468
2153 : GIM_Reject,
2154 : // Label 212: @3469
2155 : GIM_Reject,
2156 : // Label 199: @3470
2157 : GIM_Try, /*On fail goto*//*Label 215*/ 3501, // Rule ID 486 //
2158 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2159 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2160 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2163 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2164 : // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2165 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2166 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167 : // GIR_Coverage, 486,
2168 : GIR_Done,
2169 : // Label 215: @3501
2170 : GIM_Reject,
2171 : // Label 200: @3502
2172 : GIM_Try, /*On fail goto*//*Label 216*/ 3533, // Rule ID 485 //
2173 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2174 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2175 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2177 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2178 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2179 : // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2180 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2181 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2182 : // GIR_Coverage, 485,
2183 : GIR_Done,
2184 : // Label 216: @3533
2185 : GIM_Reject,
2186 : // Label 201: @3534
2187 : GIM_Try, /*On fail goto*//*Label 217*/ 3565, // Rule ID 484 //
2188 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2189 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2190 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2191 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2192 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2193 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2194 : // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2195 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2196 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2197 : // GIR_Coverage, 484,
2198 : GIR_Done,
2199 : // Label 217: @3565
2200 : GIM_Reject,
2201 : // Label 202: @3566
2202 : GIM_Try, /*On fail goto*//*Label 218*/ 3597, // Rule ID 483 //
2203 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2204 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2205 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2207 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2208 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2209 : // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2210 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2211 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2212 : // GIR_Coverage, 483,
2213 : GIR_Done,
2214 : // Label 218: @3597
2215 : GIM_Reject,
2216 : // Label 203: @3598
2217 : GIM_Reject,
2218 : // Label 8: @3599
2219 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 225*/ 3900,
2220 : /*GILLT_s32*//*Label 219*/ 3613,
2221 : /*GILLT_s64*//*Label 220*/ 3740, 0,
2222 : /*GILLT_v2s64*//*Label 221*/ 3772, 0,
2223 : /*GILLT_v4s32*//*Label 222*/ 3804,
2224 : /*GILLT_v8s16*//*Label 223*/ 3836,
2225 : /*GILLT_v16s8*//*Label 224*/ 3868,
2226 : // Label 219: @3613
2227 : GIM_Try, /*On fail goto*//*Label 226*/ 3739,
2228 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2229 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2230 : GIM_Try, /*On fail goto*//*Label 227*/ 3646, // Rule ID 40 //
2231 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2232 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2234 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2235 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2236 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2237 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2238 : // GIR_Coverage, 40,
2239 : GIR_Done,
2240 : // Label 227: @3646
2241 : GIM_Try, /*On fail goto*//*Label 228*/ 3669, // Rule ID 1031 //
2242 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2243 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2244 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2245 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2246 : // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2247 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2248 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249 : // GIR_Coverage, 1031,
2250 : GIR_Done,
2251 : // Label 228: @3669
2252 : GIM_Try, /*On fail goto*//*Label 229*/ 3692, // Rule ID 1046 //
2253 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2254 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2255 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2256 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2257 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2258 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2260 : // GIR_Coverage, 1046,
2261 : GIR_Done,
2262 : // Label 229: @3692
2263 : GIM_Try, /*On fail goto*//*Label 230*/ 3715, // Rule ID 1149 //
2264 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2265 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2266 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2267 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2268 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2269 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2270 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2271 : // GIR_Coverage, 1149,
2272 : GIR_Done,
2273 : // Label 230: @3715
2274 : GIM_Try, /*On fail goto*//*Label 231*/ 3738, // Rule ID 1748 //
2275 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2277 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2278 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2279 : // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2280 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2281 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2282 : // GIR_Coverage, 1748,
2283 : GIR_Done,
2284 : // Label 231: @3738
2285 : GIM_Reject,
2286 : // Label 226: @3739
2287 : GIM_Reject,
2288 : // Label 220: @3740
2289 : GIM_Try, /*On fail goto*//*Label 232*/ 3771, // Rule ID 185 //
2290 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2291 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2292 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2293 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2296 : // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2297 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2298 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299 : // GIR_Coverage, 185,
2300 : GIR_Done,
2301 : // Label 232: @3771
2302 : GIM_Reject,
2303 : // Label 221: @3772
2304 : GIM_Try, /*On fail goto*//*Label 233*/ 3803, // Rule ID 892 //
2305 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2306 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2307 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2308 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2310 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2311 : // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2312 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2313 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2314 : // GIR_Coverage, 892,
2315 : GIR_Done,
2316 : // Label 233: @3803
2317 : GIM_Reject,
2318 : // Label 222: @3804
2319 : GIM_Try, /*On fail goto*//*Label 234*/ 3835, // Rule ID 891 //
2320 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2321 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2322 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2323 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2324 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2325 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2326 : // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2327 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2328 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2329 : // GIR_Coverage, 891,
2330 : GIR_Done,
2331 : // Label 234: @3835
2332 : GIM_Reject,
2333 : // Label 223: @3836
2334 : GIM_Try, /*On fail goto*//*Label 235*/ 3867, // Rule ID 890 //
2335 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2336 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2337 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2338 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2339 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2340 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2341 : // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2342 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2343 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344 : // GIR_Coverage, 890,
2345 : GIR_Done,
2346 : // Label 235: @3867
2347 : GIM_Reject,
2348 : // Label 224: @3868
2349 : GIM_Try, /*On fail goto*//*Label 236*/ 3899, // Rule ID 889 //
2350 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2351 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2352 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2353 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2354 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2355 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2356 : // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2357 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2358 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2359 : // GIR_Coverage, 889,
2360 : GIR_Done,
2361 : // Label 236: @3899
2362 : GIM_Reject,
2363 : // Label 225: @3900
2364 : GIM_Reject,
2365 : // Label 9: @3901
2366 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4694,
2367 : /*GILLT_s32*//*Label 237*/ 3915,
2368 : /*GILLT_s64*//*Label 238*/ 4478, 0,
2369 : /*GILLT_v2s64*//*Label 239*/ 4566, 0,
2370 : /*GILLT_v4s32*//*Label 240*/ 4598,
2371 : /*GILLT_v8s16*//*Label 241*/ 4630,
2372 : /*GILLT_v16s8*//*Label 242*/ 4662,
2373 : // Label 237: @3915
2374 : GIM_Try, /*On fail goto*//*Label 244*/ 4477,
2375 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2376 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2377 : GIM_Try, /*On fail goto*//*Label 245*/ 3982, // Rule ID 42 //
2378 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2380 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2381 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2382 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2383 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2384 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2385 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2386 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2387 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2388 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2389 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2391 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2392 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2393 : GIR_EraseFromParent, /*InsnID*/0,
2394 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2395 : // GIR_Coverage, 42,
2396 : GIR_Done,
2397 : // Label 245: @3982
2398 : GIM_Try, /*On fail goto*//*Label 246*/ 4039, // Rule ID 1048 //
2399 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2400 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2401 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2402 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2403 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2404 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2405 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2406 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2407 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2408 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2409 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2410 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2411 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2412 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2413 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2414 : GIR_EraseFromParent, /*InsnID*/0,
2415 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2416 : // GIR_Coverage, 1048,
2417 : GIR_Done,
2418 : // Label 246: @4039
2419 : GIM_Try, /*On fail goto*//*Label 247*/ 4096, // Rule ID 1148 //
2420 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2422 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2423 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2424 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2425 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2426 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2427 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2428 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2429 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2430 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2431 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2432 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2434 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2435 : GIR_EraseFromParent, /*InsnID*/0,
2436 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2437 : // GIR_Coverage, 1148,
2438 : GIR_Done,
2439 : // Label 247: @4096
2440 : GIM_Try, /*On fail goto*//*Label 248*/ 4128, // Rule ID 1175 //
2441 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2444 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2445 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2446 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2447 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2448 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2449 : GIR_EraseFromParent, /*InsnID*/0,
2450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451 : // GIR_Coverage, 1175,
2452 : GIR_Done,
2453 : // Label 248: @4128
2454 : GIM_Try, /*On fail goto*//*Label 249*/ 4160, // Rule ID 1030 //
2455 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2457 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2458 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2459 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2460 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2461 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2462 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2463 : GIR_EraseFromParent, /*InsnID*/0,
2464 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465 : // GIR_Coverage, 1030,
2466 : GIR_Done,
2467 : // Label 249: @4160
2468 : GIM_Try, /*On fail goto*//*Label 250*/ 4195, // Rule ID 1362 //
2469 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2470 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2471 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2472 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2473 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2474 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2475 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2476 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2477 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2478 : GIR_EraseFromParent, /*InsnID*/0,
2479 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2480 : // GIR_Coverage, 1362,
2481 : GIR_Done,
2482 : // Label 250: @4195
2483 : GIM_Try, /*On fail goto*//*Label 251*/ 4227, // Rule ID 1743 //
2484 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2487 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2488 : // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2489 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2490 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2491 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2492 : GIR_EraseFromParent, /*InsnID*/0,
2493 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2494 : // GIR_Coverage, 1743,
2495 : GIR_Done,
2496 : // Label 251: @4227
2497 : GIM_Try, /*On fail goto*//*Label 252*/ 4259, // Rule ID 2082 //
2498 : GIM_CheckFeatures, GIFBS_InMicroMips,
2499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2500 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2501 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2502 : // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2503 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2504 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2505 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2506 : GIR_EraseFromParent, /*InsnID*/0,
2507 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2508 : // GIR_Coverage, 2082,
2509 : GIR_Done,
2510 : // Label 252: @4259
2511 : GIM_Try, /*On fail goto*//*Label 253*/ 4294, // Rule ID 2083 //
2512 : GIM_CheckFeatures, GIFBS_InMicroMips,
2513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2515 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2516 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2517 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2519 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2520 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2521 : GIR_EraseFromParent, /*InsnID*/0,
2522 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2523 : // GIR_Coverage, 2083,
2524 : GIR_Done,
2525 : // Label 253: @4294
2526 : GIM_Try, /*On fail goto*//*Label 254*/ 4326, // Rule ID 2243 //
2527 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2528 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2529 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2530 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2531 : // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2532 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2533 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2534 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2535 : GIR_EraseFromParent, /*InsnID*/0,
2536 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2537 : // GIR_Coverage, 2243,
2538 : GIR_Done,
2539 : // Label 254: @4326
2540 : GIM_Try, /*On fail goto*//*Label 255*/ 4361, // Rule ID 2244 //
2541 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2542 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2543 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2544 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2545 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2546 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2547 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2548 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2549 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2550 : GIR_EraseFromParent, /*InsnID*/0,
2551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2552 : // GIR_Coverage, 2244,
2553 : GIR_Done,
2554 : // Label 255: @4361
2555 : GIM_Try, /*On fail goto*//*Label 256*/ 4384, // Rule ID 41 //
2556 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2557 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2560 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2561 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2562 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2563 : // GIR_Coverage, 41,
2564 : GIR_Done,
2565 : // Label 256: @4384
2566 : GIM_Try, /*On fail goto*//*Label 257*/ 4407, // Rule ID 1033 //
2567 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2568 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2569 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2570 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2571 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2572 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2573 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574 : // GIR_Coverage, 1033,
2575 : GIR_Done,
2576 : // Label 257: @4407
2577 : GIM_Try, /*On fail goto*//*Label 258*/ 4430, // Rule ID 1047 //
2578 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2579 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2582 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2583 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2584 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2585 : // GIR_Coverage, 1047,
2586 : GIR_Done,
2587 : // Label 258: @4430
2588 : GIM_Try, /*On fail goto*//*Label 259*/ 4453, // Rule ID 1152 //
2589 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2590 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2591 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2593 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2595 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2596 : // GIR_Coverage, 1152,
2597 : GIR_Done,
2598 : // Label 259: @4453
2599 : GIM_Try, /*On fail goto*//*Label 260*/ 4476, // Rule ID 1750 //
2600 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2601 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2602 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2603 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2604 : // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2605 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2606 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2607 : // GIR_Coverage, 1750,
2608 : GIR_Done,
2609 : // Label 260: @4476
2610 : GIM_Reject,
2611 : // Label 244: @4477
2612 : GIM_Reject,
2613 : // Label 238: @4478
2614 : GIM_Try, /*On fail goto*//*Label 261*/ 4565,
2615 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2616 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2617 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2618 : GIM_Try, /*On fail goto*//*Label 262*/ 4545, // Rule ID 187 //
2619 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2620 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2621 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2622 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2623 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2624 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2625 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2626 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2627 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2628 : // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2629 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2632 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2633 : GIR_EraseFromParent, /*InsnID*/0,
2634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2635 : // GIR_Coverage, 187,
2636 : GIR_Done,
2637 : // Label 262: @4545
2638 : GIM_Try, /*On fail goto*//*Label 263*/ 4564, // Rule ID 186 //
2639 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2640 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2641 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2642 : // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2643 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2644 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2645 : // GIR_Coverage, 186,
2646 : GIR_Done,
2647 : // Label 263: @4564
2648 : GIM_Reject,
2649 : // Label 261: @4565
2650 : GIM_Reject,
2651 : // Label 239: @4566
2652 : GIM_Try, /*On fail goto*//*Label 264*/ 4597, // Rule ID 1008 //
2653 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2654 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2655 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2656 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2659 : // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2660 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2661 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2662 : // GIR_Coverage, 1008,
2663 : GIR_Done,
2664 : // Label 264: @4597
2665 : GIM_Reject,
2666 : // Label 240: @4598
2667 : GIM_Try, /*On fail goto*//*Label 265*/ 4629, // Rule ID 1007 //
2668 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2669 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2670 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2671 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2672 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2673 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2674 : // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2675 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2676 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677 : // GIR_Coverage, 1007,
2678 : GIR_Done,
2679 : // Label 265: @4629
2680 : GIM_Reject,
2681 : // Label 241: @4630
2682 : GIM_Try, /*On fail goto*//*Label 266*/ 4661, // Rule ID 1006 //
2683 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2684 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2685 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2686 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2689 : // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2690 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2691 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2692 : // GIR_Coverage, 1006,
2693 : GIR_Done,
2694 : // Label 266: @4661
2695 : GIM_Reject,
2696 : // Label 242: @4662
2697 : GIM_Try, /*On fail goto*//*Label 267*/ 4693, // Rule ID 1005 //
2698 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2699 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2700 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2704 : // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2705 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2706 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2707 : // GIR_Coverage, 1005,
2708 : GIR_Done,
2709 : // Label 267: @4693
2710 : GIM_Reject,
2711 : // Label 243: @4694
2712 : GIM_Reject,
2713 : // Label 10: @4695
2714 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 276*/ 8347,
2715 : /*GILLT_s32*//*Label 268*/ 4709,
2716 : /*GILLT_s64*//*Label 269*/ 4948,
2717 : /*GILLT_v2s16*//*Label 270*/ 4994,
2718 : /*GILLT_v2s64*//*Label 271*/ 5040,
2719 : /*GILLT_v4s8*//*Label 272*/ 6013,
2720 : /*GILLT_v4s32*//*Label 273*/ 6059,
2721 : /*GILLT_v8s16*//*Label 274*/ 6962,
2722 : /*GILLT_v16s8*//*Label 275*/ 7760,
2723 : // Label 268: @4709
2724 : GIM_Try, /*On fail goto*//*Label 277*/ 4732, // Rule ID 117 //
2725 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2726 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2727 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2728 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2729 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2730 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2731 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2732 : // GIR_Coverage, 117,
2733 : GIR_Done,
2734 : // Label 277: @4732
2735 : GIM_Try, /*On fail goto*//*Label 278*/ 4755, // Rule ID 118 //
2736 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2737 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2738 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2739 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2740 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2741 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2742 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743 : // GIR_Coverage, 118,
2744 : GIR_Done,
2745 : // Label 278: @4755
2746 : GIM_Try, /*On fail goto*//*Label 279*/ 4778, // Rule ID 1128 //
2747 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2748 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2749 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2750 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2751 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2752 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2753 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2754 : // GIR_Coverage, 1128,
2755 : GIR_Done,
2756 : // Label 279: @4778
2757 : GIM_Try, /*On fail goto*//*Label 280*/ 4801, // Rule ID 1129 //
2758 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2759 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2762 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2763 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2764 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2765 : // GIR_Coverage, 1129,
2766 : GIR_Done,
2767 : // Label 280: @4801
2768 : GIM_Try, /*On fail goto*//*Label 281*/ 4824, // Rule ID 1141 //
2769 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2770 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2772 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2773 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2774 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2775 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2776 : // GIR_Coverage, 1141,
2777 : GIR_Done,
2778 : // Label 281: @4824
2779 : GIM_Try, /*On fail goto*//*Label 282*/ 4847, // Rule ID 1142 //
2780 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2781 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2782 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2783 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2784 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2785 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787 : // GIR_Coverage, 1142,
2788 : GIR_Done,
2789 : // Label 282: @4847
2790 : GIM_Try, /*On fail goto*//*Label 283*/ 4872, // Rule ID 1831 //
2791 : GIM_CheckFeatures, GIFBS_HasDSP,
2792 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2793 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2794 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2795 : // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2796 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2797 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2798 : // GIR_Coverage, 1831,
2799 : GIR_Done,
2800 : // Label 283: @4872
2801 : GIM_Try, /*On fail goto*//*Label 284*/ 4897, // Rule ID 1832 //
2802 : GIM_CheckFeatures, GIFBS_HasDSP,
2803 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2804 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2805 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2806 : // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2807 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2808 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2809 : // GIR_Coverage, 1832,
2810 : GIR_Done,
2811 : // Label 284: @4897
2812 : GIM_Try, /*On fail goto*//*Label 285*/ 4922, // Rule ID 1835 //
2813 : GIM_CheckFeatures, GIFBS_HasDSP,
2814 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2817 : // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2818 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2819 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2820 : // GIR_Coverage, 1835,
2821 : GIR_Done,
2822 : // Label 285: @4922
2823 : GIM_Try, /*On fail goto*//*Label 286*/ 4947, // Rule ID 1836 //
2824 : GIM_CheckFeatures, GIFBS_HasDSP,
2825 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2828 : // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2829 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2830 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2831 : // GIR_Coverage, 1836,
2832 : GIR_Done,
2833 : // Label 286: @4947
2834 : GIM_Reject,
2835 : // Label 269: @4948
2836 : GIM_Try, /*On fail goto*//*Label 287*/ 4993,
2837 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2838 : GIM_Try, /*On fail goto*//*Label 288*/ 4973, // Rule ID 119 //
2839 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2842 : // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2843 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2844 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2845 : // GIR_Coverage, 119,
2846 : GIR_Done,
2847 : // Label 288: @4973
2848 : GIM_Try, /*On fail goto*//*Label 289*/ 4992, // Rule ID 120 //
2849 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2850 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2852 : // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2853 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2854 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2855 : // GIR_Coverage, 120,
2856 : GIR_Done,
2857 : // Label 289: @4992
2858 : GIM_Reject,
2859 : // Label 287: @4993
2860 : GIM_Reject,
2861 : // Label 270: @4994
2862 : GIM_Try, /*On fail goto*//*Label 290*/ 5039,
2863 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2864 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2865 : GIM_Try, /*On fail goto*//*Label 291*/ 5021, // Rule ID 1833 //
2866 : GIM_CheckFeatures, GIFBS_HasDSP,
2867 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2868 : // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2869 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2870 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2871 : // GIR_Coverage, 1833,
2872 : GIR_Done,
2873 : // Label 291: @5021
2874 : GIM_Try, /*On fail goto*//*Label 292*/ 5038, // Rule ID 1837 //
2875 : GIM_CheckFeatures, GIFBS_HasDSP,
2876 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2877 : // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2878 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2879 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2880 : // GIR_Coverage, 1837,
2881 : GIR_Done,
2882 : // Label 292: @5038
2883 : GIM_Reject,
2884 : // Label 290: @5039
2885 : GIM_Reject,
2886 : // Label 271: @5040
2887 : GIM_Try, /*On fail goto*//*Label 293*/ 5061, // Rule ID 1918 //
2888 : GIM_CheckFeatures, GIFBS_HasMSA,
2889 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2891 : // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2892 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2893 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2894 : // GIR_Coverage, 1918,
2895 : GIR_Done,
2896 : // Label 293: @5061
2897 : GIM_Try, /*On fail goto*//*Label 294*/ 5082, // Rule ID 1921 //
2898 : GIM_CheckFeatures, GIFBS_HasMSA,
2899 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2900 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2901 : // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2902 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2903 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2904 : // GIR_Coverage, 1921,
2905 : GIR_Done,
2906 : // Label 294: @5082
2907 : GIM_Try, /*On fail goto*//*Label 295*/ 5103, // Rule ID 1938 //
2908 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2909 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2911 : // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2912 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2913 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2914 : // GIR_Coverage, 1938,
2915 : GIR_Done,
2916 : // Label 295: @5103
2917 : GIM_Try, /*On fail goto*//*Label 296*/ 5124, // Rule ID 1939 //
2918 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2919 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2920 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2921 : // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2922 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2923 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2924 : // GIR_Coverage, 1939,
2925 : GIR_Done,
2926 : // Label 296: @5124
2927 : GIM_Try, /*On fail goto*//*Label 297*/ 5145, // Rule ID 1940 //
2928 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2929 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2931 : // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2932 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2933 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2934 : // GIR_Coverage, 1940,
2935 : GIR_Done,
2936 : // Label 297: @5145
2937 : GIM_Try, /*On fail goto*//*Label 298*/ 5166, // Rule ID 1941 //
2938 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2939 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2940 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2941 : // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2942 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2943 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2944 : // GIR_Coverage, 1941,
2945 : GIR_Done,
2946 : // Label 298: @5166
2947 : GIM_Try, /*On fail goto*//*Label 299*/ 5187, // Rule ID 1942 //
2948 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2949 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2950 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2951 : // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2952 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2953 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2954 : // GIR_Coverage, 1942,
2955 : GIR_Done,
2956 : // Label 299: @5187
2957 : GIM_Try, /*On fail goto*//*Label 300*/ 5208, // Rule ID 1948 //
2958 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2959 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2961 : // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2962 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2963 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2964 : // GIR_Coverage, 1948,
2965 : GIR_Done,
2966 : // Label 300: @5208
2967 : GIM_Try, /*On fail goto*//*Label 301*/ 5229, // Rule ID 1949 //
2968 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2969 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2970 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2971 : // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2972 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2973 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2974 : // GIR_Coverage, 1949,
2975 : GIR_Done,
2976 : // Label 301: @5229
2977 : GIM_Try, /*On fail goto*//*Label 302*/ 5250, // Rule ID 1950 //
2978 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2979 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2980 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2981 : // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2982 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2983 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2984 : // GIR_Coverage, 1950,
2985 : GIR_Done,
2986 : // Label 302: @5250
2987 : GIM_Try, /*On fail goto*//*Label 303*/ 5271, // Rule ID 1951 //
2988 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2989 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2990 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2991 : // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2992 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2993 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2994 : // GIR_Coverage, 1951,
2995 : GIR_Done,
2996 : // Label 303: @5271
2997 : GIM_Try, /*On fail goto*//*Label 304*/ 5292, // Rule ID 1952 //
2998 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2999 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3000 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3001 : // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3002 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3003 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3004 : // GIR_Coverage, 1952,
3005 : GIR_Done,
3006 : // Label 304: @5292
3007 : GIM_Try, /*On fail goto*//*Label 305*/ 5392, // Rule ID 1957 //
3008 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3009 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3011 : // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3012 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3013 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3014 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3015 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3016 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3017 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3018 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3019 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3020 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3021 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3022 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3023 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3024 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3025 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3026 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3027 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3028 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3029 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3030 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3031 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3032 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3033 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3034 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3036 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3037 : GIR_EraseFromParent, /*InsnID*/0,
3038 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3039 : // GIR_Coverage, 1957,
3040 : GIR_Done,
3041 : // Label 305: @5392
3042 : GIM_Try, /*On fail goto*//*Label 306*/ 5492, // Rule ID 1958 //
3043 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3044 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3046 : // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3047 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3048 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3049 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3050 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3051 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3052 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3053 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3054 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3055 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3056 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3057 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3058 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3059 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3060 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3061 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3062 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3063 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3064 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3065 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3066 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3067 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3068 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3069 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3070 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3071 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3072 : GIR_EraseFromParent, /*InsnID*/0,
3073 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3074 : // GIR_Coverage, 1958,
3075 : GIR_Done,
3076 : // Label 306: @5492
3077 : GIM_Try, /*On fail goto*//*Label 307*/ 5557, // Rule ID 1962 //
3078 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3079 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3080 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3081 : // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3082 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3083 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3084 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3085 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3086 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3087 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3088 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3089 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3090 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3091 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3092 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3093 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3094 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3095 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3096 : GIR_EraseFromParent, /*InsnID*/0,
3097 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3098 : // GIR_Coverage, 1962,
3099 : GIR_Done,
3100 : // Label 307: @5557
3101 : GIM_Try, /*On fail goto*//*Label 308*/ 5622, // Rule ID 1963 //
3102 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3103 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3105 : // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3106 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3107 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3108 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3109 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3110 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3111 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3112 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3113 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3114 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3115 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3116 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3117 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3119 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3120 : GIR_EraseFromParent, /*InsnID*/0,
3121 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3122 : // GIR_Coverage, 1963,
3123 : GIR_Done,
3124 : // Label 308: @5622
3125 : GIM_Try, /*On fail goto*//*Label 309*/ 5687, // Rule ID 1967 //
3126 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3127 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3128 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3129 : // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3130 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3131 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3132 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3133 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3134 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3135 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3136 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3137 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3138 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3139 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3140 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3141 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3143 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3144 : GIR_EraseFromParent, /*InsnID*/0,
3145 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3146 : // GIR_Coverage, 1967,
3147 : GIR_Done,
3148 : // Label 309: @5687
3149 : GIM_Try, /*On fail goto*//*Label 310*/ 5752, // Rule ID 1968 //
3150 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3151 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3152 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3153 : // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3154 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3155 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3156 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3157 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3158 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3159 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3160 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3161 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3162 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3163 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3164 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3165 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3167 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3168 : GIR_EraseFromParent, /*InsnID*/0,
3169 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3170 : // GIR_Coverage, 1968,
3171 : GIR_Done,
3172 : // Label 310: @5752
3173 : GIM_Try, /*On fail goto*//*Label 311*/ 5817, // Rule ID 1972 //
3174 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3175 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3177 : // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3178 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3179 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3180 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3181 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3182 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3183 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3184 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3185 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3186 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3187 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3188 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3189 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3190 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3191 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3192 : GIR_EraseFromParent, /*InsnID*/0,
3193 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3194 : // GIR_Coverage, 1972,
3195 : GIR_Done,
3196 : // Label 311: @5817
3197 : GIM_Try, /*On fail goto*//*Label 312*/ 5882, // Rule ID 1973 //
3198 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3199 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3200 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3201 : // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3202 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3203 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3204 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3205 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3206 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3207 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3208 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3209 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3210 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3211 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3212 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3213 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3214 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3215 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3216 : GIR_EraseFromParent, /*InsnID*/0,
3217 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3218 : // GIR_Coverage, 1973,
3219 : GIR_Done,
3220 : // Label 312: @5882
3221 : GIM_Try, /*On fail goto*//*Label 313*/ 5947, // Rule ID 1977 //
3222 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3223 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3224 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3225 : // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3226 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3227 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3228 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3229 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3230 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3231 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3232 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3233 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3234 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3235 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3237 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3239 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3240 : GIR_EraseFromParent, /*InsnID*/0,
3241 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3242 : // GIR_Coverage, 1977,
3243 : GIR_Done,
3244 : // Label 313: @5947
3245 : GIM_Try, /*On fail goto*//*Label 314*/ 6012, // Rule ID 1978 //
3246 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3247 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3248 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3249 : // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3250 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3251 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3252 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3253 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3254 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3255 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3256 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3257 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3258 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3259 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3260 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3261 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3262 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3263 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3264 : GIR_EraseFromParent, /*InsnID*/0,
3265 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3266 : // GIR_Coverage, 1978,
3267 : GIR_Done,
3268 : // Label 314: @6012
3269 : GIM_Reject,
3270 : // Label 272: @6013
3271 : GIM_Try, /*On fail goto*//*Label 315*/ 6058,
3272 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3273 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3274 : GIM_Try, /*On fail goto*//*Label 316*/ 6040, // Rule ID 1834 //
3275 : GIM_CheckFeatures, GIFBS_HasDSP,
3276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3277 : // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3278 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3279 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3280 : // GIR_Coverage, 1834,
3281 : GIR_Done,
3282 : // Label 316: @6040
3283 : GIM_Try, /*On fail goto*//*Label 317*/ 6057, // Rule ID 1838 //
3284 : GIM_CheckFeatures, GIFBS_HasDSP,
3285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3286 : // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3287 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3288 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3289 : // GIR_Coverage, 1838,
3290 : GIR_Done,
3291 : // Label 317: @6057
3292 : GIM_Reject,
3293 : // Label 315: @6058
3294 : GIM_Reject,
3295 : // Label 273: @6059
3296 : GIM_Try, /*On fail goto*//*Label 318*/ 6080, // Rule ID 1917 //
3297 : GIM_CheckFeatures, GIFBS_HasMSA,
3298 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3299 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3300 : // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3301 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3302 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3303 : // GIR_Coverage, 1917,
3304 : GIR_Done,
3305 : // Label 318: @6080
3306 : GIM_Try, /*On fail goto*//*Label 319*/ 6101, // Rule ID 1920 //
3307 : GIM_CheckFeatures, GIFBS_HasMSA,
3308 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3310 : // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3311 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3312 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3313 : // GIR_Coverage, 1920,
3314 : GIR_Done,
3315 : // Label 319: @6101
3316 : GIM_Try, /*On fail goto*//*Label 320*/ 6122, // Rule ID 1933 //
3317 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3318 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3319 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3320 : // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3321 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3322 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3323 : // GIR_Coverage, 1933,
3324 : GIR_Done,
3325 : // Label 320: @6122
3326 : GIM_Try, /*On fail goto*//*Label 321*/ 6143, // Rule ID 1934 //
3327 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3328 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3329 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3330 : // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3331 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3332 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3333 : // GIR_Coverage, 1934,
3334 : GIR_Done,
3335 : // Label 321: @6143
3336 : GIM_Try, /*On fail goto*//*Label 322*/ 6164, // Rule ID 1935 //
3337 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3338 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3339 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3340 : // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3341 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3342 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3343 : // GIR_Coverage, 1935,
3344 : GIR_Done,
3345 : // Label 322: @6164
3346 : GIM_Try, /*On fail goto*//*Label 323*/ 6185, // Rule ID 1936 //
3347 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3348 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3349 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3350 : // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3351 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3352 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3353 : // GIR_Coverage, 1936,
3354 : GIR_Done,
3355 : // Label 323: @6185
3356 : GIM_Try, /*On fail goto*//*Label 324*/ 6206, // Rule ID 1937 //
3357 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3358 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3360 : // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3361 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3362 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3363 : // GIR_Coverage, 1937,
3364 : GIR_Done,
3365 : // Label 324: @6206
3366 : GIM_Try, /*On fail goto*//*Label 325*/ 6227, // Rule ID 1943 //
3367 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3368 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3369 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3370 : // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3371 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3372 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3373 : // GIR_Coverage, 1943,
3374 : GIR_Done,
3375 : // Label 325: @6227
3376 : GIM_Try, /*On fail goto*//*Label 326*/ 6248, // Rule ID 1944 //
3377 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3378 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3380 : // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3381 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3382 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3383 : // GIR_Coverage, 1944,
3384 : GIR_Done,
3385 : // Label 326: @6248
3386 : GIM_Try, /*On fail goto*//*Label 327*/ 6269, // Rule ID 1945 //
3387 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3388 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3389 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3390 : // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3391 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3392 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3393 : // GIR_Coverage, 1945,
3394 : GIR_Done,
3395 : // Label 327: @6269
3396 : GIM_Try, /*On fail goto*//*Label 328*/ 6290, // Rule ID 1946 //
3397 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3398 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3399 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3400 : // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3401 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3402 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3403 : // GIR_Coverage, 1946,
3404 : GIR_Done,
3405 : // Label 328: @6290
3406 : GIM_Try, /*On fail goto*//*Label 329*/ 6311, // Rule ID 1947 //
3407 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3408 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3410 : // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3411 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3412 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3413 : // GIR_Coverage, 1947,
3414 : GIR_Done,
3415 : // Label 329: @6311
3416 : GIM_Try, /*On fail goto*//*Label 330*/ 6376, // Rule ID 1955 //
3417 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3418 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3420 : // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3421 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3422 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3423 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3424 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3425 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3426 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3427 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3428 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3429 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3430 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3431 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3432 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3434 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3435 : GIR_EraseFromParent, /*InsnID*/0,
3436 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3437 : // GIR_Coverage, 1955,
3438 : GIR_Done,
3439 : // Label 330: @6376
3440 : GIM_Try, /*On fail goto*//*Label 331*/ 6441, // Rule ID 1956 //
3441 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3442 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3444 : // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3445 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3446 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3447 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3448 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3449 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3451 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3452 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3453 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3454 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3455 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3457 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3458 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3459 : GIR_EraseFromParent, /*InsnID*/0,
3460 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3461 : // GIR_Coverage, 1956,
3462 : GIR_Done,
3463 : // Label 331: @6441
3464 : GIM_Try, /*On fail goto*//*Label 332*/ 6506, // Rule ID 1960 //
3465 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3466 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3467 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3468 : // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3469 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3470 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3471 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3472 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3473 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3474 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3475 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3476 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3477 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3478 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3479 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3480 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3481 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3482 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3483 : GIR_EraseFromParent, /*InsnID*/0,
3484 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3485 : // GIR_Coverage, 1960,
3486 : GIR_Done,
3487 : // Label 332: @6506
3488 : GIM_Try, /*On fail goto*//*Label 333*/ 6571, // Rule ID 1961 //
3489 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3490 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3491 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3492 : // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3493 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3494 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3495 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3496 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3497 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3498 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3499 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3500 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3501 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3502 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3503 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3504 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3505 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3506 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3507 : GIR_EraseFromParent, /*InsnID*/0,
3508 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3509 : // GIR_Coverage, 1961,
3510 : GIR_Done,
3511 : // Label 333: @6571
3512 : GIM_Try, /*On fail goto*//*Label 334*/ 6636, // Rule ID 1965 //
3513 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3514 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3515 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3516 : // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3517 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3518 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3519 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3520 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3521 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3522 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3523 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3524 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3525 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3526 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3527 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3528 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3530 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3531 : GIR_EraseFromParent, /*InsnID*/0,
3532 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3533 : // GIR_Coverage, 1965,
3534 : GIR_Done,
3535 : // Label 334: @6636
3536 : GIM_Try, /*On fail goto*//*Label 335*/ 6701, // Rule ID 1966 //
3537 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3538 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3539 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3540 : // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3541 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3542 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3543 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3544 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3545 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3546 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3547 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3548 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3549 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3550 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3552 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3553 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3554 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3555 : GIR_EraseFromParent, /*InsnID*/0,
3556 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3557 : // GIR_Coverage, 1966,
3558 : GIR_Done,
3559 : // Label 335: @6701
3560 : GIM_Try, /*On fail goto*//*Label 336*/ 6766, // Rule ID 1982 //
3561 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3562 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3563 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3564 : // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3565 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3566 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3567 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3568 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3569 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3570 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3571 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3572 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3573 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3574 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3575 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3576 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3577 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3578 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3579 : GIR_EraseFromParent, /*InsnID*/0,
3580 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3581 : // GIR_Coverage, 1982,
3582 : GIR_Done,
3583 : // Label 336: @6766
3584 : GIM_Try, /*On fail goto*//*Label 337*/ 6831, // Rule ID 1983 //
3585 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3586 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3587 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3588 : // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3589 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3590 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3591 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3592 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3593 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3594 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3595 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3596 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3597 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3598 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3599 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3600 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3601 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3602 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3603 : GIR_EraseFromParent, /*InsnID*/0,
3604 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3605 : // GIR_Coverage, 1983,
3606 : GIR_Done,
3607 : // Label 337: @6831
3608 : GIM_Try, /*On fail goto*//*Label 338*/ 6896, // Rule ID 1987 //
3609 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3610 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3611 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3612 : // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3613 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3614 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3615 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3616 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3617 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3618 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3619 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3620 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3621 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3622 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3623 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3624 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3626 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3627 : GIR_EraseFromParent, /*InsnID*/0,
3628 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3629 : // GIR_Coverage, 1987,
3630 : GIR_Done,
3631 : // Label 338: @6896
3632 : GIM_Try, /*On fail goto*//*Label 339*/ 6961, // Rule ID 1988 //
3633 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3634 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3636 : // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3637 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3638 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3639 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3640 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3641 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3642 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3643 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3644 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3645 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3646 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3647 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3648 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3649 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3650 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3651 : GIR_EraseFromParent, /*InsnID*/0,
3652 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3653 : // GIR_Coverage, 1988,
3654 : GIR_Done,
3655 : // Label 339: @6961
3656 : GIM_Reject,
3657 : // Label 274: @6962
3658 : GIM_Try, /*On fail goto*//*Label 340*/ 6983, // Rule ID 1916 //
3659 : GIM_CheckFeatures, GIFBS_HasMSA,
3660 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3662 : // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3663 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3664 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3665 : // GIR_Coverage, 1916,
3666 : GIR_Done,
3667 : // Label 340: @6983
3668 : GIM_Try, /*On fail goto*//*Label 341*/ 7004, // Rule ID 1919 //
3669 : GIM_CheckFeatures, GIFBS_HasMSA,
3670 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3671 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3672 : // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3673 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3675 : // GIR_Coverage, 1919,
3676 : GIR_Done,
3677 : // Label 341: @7004
3678 : GIM_Try, /*On fail goto*//*Label 342*/ 7025, // Rule ID 1928 //
3679 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3680 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3681 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3682 : // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3683 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3684 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3685 : // GIR_Coverage, 1928,
3686 : GIR_Done,
3687 : // Label 342: @7025
3688 : GIM_Try, /*On fail goto*//*Label 343*/ 7046, // Rule ID 1929 //
3689 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3690 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3691 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3692 : // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3693 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3694 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3695 : // GIR_Coverage, 1929,
3696 : GIR_Done,
3697 : // Label 343: @7046
3698 : GIM_Try, /*On fail goto*//*Label 344*/ 7067, // Rule ID 1930 //
3699 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3700 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3702 : // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3703 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3704 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3705 : // GIR_Coverage, 1930,
3706 : GIR_Done,
3707 : // Label 344: @7067
3708 : GIM_Try, /*On fail goto*//*Label 345*/ 7088, // Rule ID 1931 //
3709 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3710 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3711 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3712 : // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3713 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3715 : // GIR_Coverage, 1931,
3716 : GIR_Done,
3717 : // Label 345: @7088
3718 : GIM_Try, /*On fail goto*//*Label 346*/ 7109, // Rule ID 1932 //
3719 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3720 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3722 : // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3723 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3725 : // GIR_Coverage, 1932,
3726 : GIR_Done,
3727 : // Label 346: @7109
3728 : GIM_Try, /*On fail goto*//*Label 347*/ 7174, // Rule ID 1953 //
3729 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3730 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3731 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3732 : // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3733 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3734 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3735 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3736 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3737 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3738 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3739 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3740 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3741 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3742 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3743 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3744 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3745 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3746 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3747 : GIR_EraseFromParent, /*InsnID*/0,
3748 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3749 : // GIR_Coverage, 1953,
3750 : GIR_Done,
3751 : // Label 347: @7174
3752 : GIM_Try, /*On fail goto*//*Label 348*/ 7239, // Rule ID 1954 //
3753 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3754 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3755 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3756 : // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3757 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3758 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3759 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3760 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3761 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3762 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3763 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3764 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3765 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3766 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3767 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3768 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3770 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3771 : GIR_EraseFromParent, /*InsnID*/0,
3772 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3773 : // GIR_Coverage, 1954,
3774 : GIR_Done,
3775 : // Label 348: @7239
3776 : GIM_Try, /*On fail goto*//*Label 349*/ 7304, // Rule ID 1970 //
3777 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3778 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3779 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3780 : // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3781 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3782 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3783 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3784 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3785 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3787 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3788 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3789 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3790 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3791 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3792 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3793 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3794 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3795 : GIR_EraseFromParent, /*InsnID*/0,
3796 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3797 : // GIR_Coverage, 1970,
3798 : GIR_Done,
3799 : // Label 349: @7304
3800 : GIM_Try, /*On fail goto*//*Label 350*/ 7369, // Rule ID 1971 //
3801 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3802 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3803 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3804 : // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3805 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3806 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3807 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3808 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3809 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3811 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3812 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3813 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3814 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3815 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3816 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3817 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3818 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3819 : GIR_EraseFromParent, /*InsnID*/0,
3820 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3821 : // GIR_Coverage, 1971,
3822 : GIR_Done,
3823 : // Label 350: @7369
3824 : GIM_Try, /*On fail goto*//*Label 351*/ 7434, // Rule ID 1975 //
3825 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3826 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3828 : // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3829 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3830 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3831 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3832 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3833 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3834 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3835 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3836 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3837 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3838 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3839 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3840 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3841 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3842 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3843 : GIR_EraseFromParent, /*InsnID*/0,
3844 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3845 : // GIR_Coverage, 1975,
3846 : GIR_Done,
3847 : // Label 351: @7434
3848 : GIM_Try, /*On fail goto*//*Label 352*/ 7499, // Rule ID 1976 //
3849 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3850 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3852 : // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3853 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3854 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3855 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3856 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3857 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3858 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3859 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3860 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3861 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3862 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3863 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3864 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3865 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3866 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3867 : GIR_EraseFromParent, /*InsnID*/0,
3868 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3869 : // GIR_Coverage, 1976,
3870 : GIR_Done,
3871 : // Label 352: @7499
3872 : GIM_Try, /*On fail goto*//*Label 353*/ 7564, // Rule ID 1980 //
3873 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3874 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3875 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3876 : // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3877 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3878 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3879 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3880 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3881 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3882 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3883 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3884 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3885 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3886 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3887 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3888 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3890 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3891 : GIR_EraseFromParent, /*InsnID*/0,
3892 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3893 : // GIR_Coverage, 1980,
3894 : GIR_Done,
3895 : // Label 353: @7564
3896 : GIM_Try, /*On fail goto*//*Label 354*/ 7629, // Rule ID 1981 //
3897 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3898 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3899 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3900 : // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3901 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3902 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3903 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3904 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3905 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3906 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3907 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3908 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3909 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3910 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3911 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3912 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3913 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3914 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3915 : GIR_EraseFromParent, /*InsnID*/0,
3916 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3917 : // GIR_Coverage, 1981,
3918 : GIR_Done,
3919 : // Label 354: @7629
3920 : GIM_Try, /*On fail goto*//*Label 355*/ 7694, // Rule ID 1985 //
3921 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3922 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3923 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3924 : // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3925 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3926 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3927 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3928 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3929 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3930 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3931 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3932 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3933 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3934 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3935 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3936 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3937 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3938 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3939 : GIR_EraseFromParent, /*InsnID*/0,
3940 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3941 : // GIR_Coverage, 1985,
3942 : GIR_Done,
3943 : // Label 355: @7694
3944 : GIM_Try, /*On fail goto*//*Label 356*/ 7759, // Rule ID 1986 //
3945 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3946 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3947 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3948 : // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3949 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3950 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3951 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3952 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3953 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3954 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3955 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3956 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3957 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3958 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3959 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3960 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3961 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3962 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3963 : GIR_EraseFromParent, /*InsnID*/0,
3964 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3965 : // GIR_Coverage, 1986,
3966 : GIR_Done,
3967 : // Label 356: @7759
3968 : GIM_Reject,
3969 : // Label 275: @7760
3970 : GIM_Try, /*On fail goto*//*Label 357*/ 7781, // Rule ID 1922 //
3971 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3972 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3973 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3974 : // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3975 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3976 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3977 : // GIR_Coverage, 1922,
3978 : GIR_Done,
3979 : // Label 357: @7781
3980 : GIM_Try, /*On fail goto*//*Label 358*/ 7802, // Rule ID 1923 //
3981 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3982 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3984 : // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3985 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3986 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3987 : // GIR_Coverage, 1923,
3988 : GIR_Done,
3989 : // Label 358: @7802
3990 : GIM_Try, /*On fail goto*//*Label 359*/ 7823, // Rule ID 1924 //
3991 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3992 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3994 : // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3995 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3996 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3997 : // GIR_Coverage, 1924,
3998 : GIR_Done,
3999 : // Label 359: @7823
4000 : GIM_Try, /*On fail goto*//*Label 360*/ 7844, // Rule ID 1925 //
4001 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4002 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4004 : // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4005 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4006 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4007 : // GIR_Coverage, 1925,
4008 : GIR_Done,
4009 : // Label 360: @7844
4010 : GIM_Try, /*On fail goto*//*Label 361*/ 7865, // Rule ID 1926 //
4011 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4012 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4013 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4014 : // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4015 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4016 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4017 : // GIR_Coverage, 1926,
4018 : GIR_Done,
4019 : // Label 361: @7865
4020 : GIM_Try, /*On fail goto*//*Label 362*/ 7886, // Rule ID 1927 //
4021 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4022 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4024 : // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4025 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4026 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4027 : // GIR_Coverage, 1927,
4028 : GIR_Done,
4029 : // Label 362: @7886
4030 : GIM_Try, /*On fail goto*//*Label 363*/ 7951, // Rule ID 1959 //
4031 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4032 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4033 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4034 : // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4035 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4036 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4037 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4038 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4039 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4040 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4041 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4042 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4043 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4044 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4045 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4046 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4047 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4048 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4049 : GIR_EraseFromParent, /*InsnID*/0,
4050 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4051 : // GIR_Coverage, 1959,
4052 : GIR_Done,
4053 : // Label 363: @7951
4054 : GIM_Try, /*On fail goto*//*Label 364*/ 8016, // Rule ID 1964 //
4055 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4056 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4058 : // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4059 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4060 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4061 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4062 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4063 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4065 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4066 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4067 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4068 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4069 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4070 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4071 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4072 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4073 : GIR_EraseFromParent, /*InsnID*/0,
4074 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4075 : // GIR_Coverage, 1964,
4076 : GIR_Done,
4077 : // Label 364: @8016
4078 : GIM_Try, /*On fail goto*//*Label 365*/ 8081, // Rule ID 1969 //
4079 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4080 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4082 : // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4083 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4084 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4085 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4086 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4087 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4089 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4090 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4091 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4092 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4093 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4094 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4095 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4096 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4097 : GIR_EraseFromParent, /*InsnID*/0,
4098 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4099 : // GIR_Coverage, 1969,
4100 : GIR_Done,
4101 : // Label 365: @8081
4102 : GIM_Try, /*On fail goto*//*Label 366*/ 8146, // Rule ID 1974 //
4103 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4104 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4106 : // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4107 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4108 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4109 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4110 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4111 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4112 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4113 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4114 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4115 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4116 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4117 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4118 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4120 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4121 : GIR_EraseFromParent, /*InsnID*/0,
4122 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4123 : // GIR_Coverage, 1974,
4124 : GIR_Done,
4125 : // Label 366: @8146
4126 : GIM_Try, /*On fail goto*//*Label 367*/ 8246, // Rule ID 1979 //
4127 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4128 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4129 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4130 : // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4131 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4132 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4133 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4134 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4135 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4136 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4137 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4138 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4139 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4140 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4141 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4142 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4143 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4144 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4145 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4146 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4147 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4148 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4149 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4150 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4151 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4152 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4153 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4154 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4155 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4156 : GIR_EraseFromParent, /*InsnID*/0,
4157 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4158 : // GIR_Coverage, 1979,
4159 : GIR_Done,
4160 : // Label 367: @8246
4161 : GIM_Try, /*On fail goto*//*Label 368*/ 8346, // Rule ID 1984 //
4162 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4163 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4165 : // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4166 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4167 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4168 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4169 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4170 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4171 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4172 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4173 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4174 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4175 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4176 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4177 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4178 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4179 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4181 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4182 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4183 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4184 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4185 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4186 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4187 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4188 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4189 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4190 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4191 : GIR_EraseFromParent, /*InsnID*/0,
4192 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4193 : // GIR_Coverage, 1984,
4194 : GIR_Done,
4195 : // Label 368: @8346
4196 : GIM_Reject,
4197 : // Label 276: @8347
4198 : GIM_Reject,
4199 : // Label 11: @8348
4200 : GIM_Try, /*On fail goto*//*Label 369*/ 8413, // Rule ID 1907 //
4201 : GIM_CheckFeatures, GIFBS_HasDSP,
4202 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4203 : GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4204 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4206 : // MIs[0] Operand 1
4207 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4208 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4209 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4210 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4211 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4212 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4213 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4214 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4215 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4216 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4217 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4218 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4219 : GIR_EraseFromParent, /*InsnID*/0,
4220 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221 : // GIR_Coverage, 1907,
4222 : GIR_Done,
4223 : // Label 369: @8413
4224 : GIM_Reject,
4225 : // Label 12: @8414
4226 : GIM_Try, /*On fail goto*//*Label 370*/ 8479, // Rule ID 1906 //
4227 : GIM_CheckFeatures, GIFBS_HasDSP,
4228 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4229 : GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4230 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4232 : // MIs[0] Operand 1
4233 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4234 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4235 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4236 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4237 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4238 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4239 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4240 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4241 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4242 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4243 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4244 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4245 : GIR_EraseFromParent, /*InsnID*/0,
4246 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4247 : // GIR_Coverage, 1906,
4248 : GIR_Done,
4249 : // Label 370: @8479
4250 : GIM_Reject,
4251 : // Label 13: @8480
4252 : GIM_Try, /*On fail goto*//*Label 371*/ 8545, // Rule ID 1905 //
4253 : GIM_CheckFeatures, GIFBS_HasDSP,
4254 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4255 : GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4256 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4257 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4258 : // MIs[0] Operand 1
4259 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4260 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4261 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4262 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4263 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4264 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4265 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4266 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4267 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4268 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4270 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4271 : GIR_EraseFromParent, /*InsnID*/0,
4272 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4273 : // GIR_Coverage, 1905,
4274 : GIR_Done,
4275 : // Label 371: @8545
4276 : GIM_Reject,
4277 : // Label 14: @8546
4278 : GIM_Try, /*On fail goto*//*Label 372*/ 10740,
4279 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4280 : GIM_Try, /*On fail goto*//*Label 373*/ 8598, // Rule ID 400 //
4281 : GIM_CheckFeatures, GIFBS_HasDSP,
4282 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4283 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4284 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4286 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4287 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4288 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4289 : // MIs[1] Operand 1
4290 : // No operand predicates
4291 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4292 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4293 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4294 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4295 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4296 : GIR_EraseFromParent, /*InsnID*/0,
4297 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4298 : // GIR_Coverage, 400,
4299 : GIR_Done,
4300 : // Label 373: @8598
4301 : GIM_Try, /*On fail goto*//*Label 374*/ 8645, // Rule ID 401 //
4302 : GIM_CheckFeatures, GIFBS_HasDSP,
4303 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4304 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4306 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4307 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4308 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4309 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4310 : // MIs[1] Operand 1
4311 : // No operand predicates
4312 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4313 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4314 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4315 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4316 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4317 : GIR_EraseFromParent, /*InsnID*/0,
4318 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4319 : // GIR_Coverage, 401,
4320 : GIR_Done,
4321 : // Label 374: @8645
4322 : GIM_Try, /*On fail goto*//*Label 375*/ 8692, // Rule ID 1254 //
4323 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4324 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4325 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4326 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4327 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4328 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4329 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4330 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4331 : // MIs[1] Operand 1
4332 : // No operand predicates
4333 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4334 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4335 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4336 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4337 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4338 : GIR_EraseFromParent, /*InsnID*/0,
4339 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4340 : // GIR_Coverage, 1254,
4341 : GIR_Done,
4342 : // Label 375: @8692
4343 : GIM_Try, /*On fail goto*//*Label 376*/ 8739, // Rule ID 1255 //
4344 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4345 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4346 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4347 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4348 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4349 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4350 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4351 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4352 : // MIs[1] Operand 1
4353 : // No operand predicates
4354 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4355 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4358 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4359 : GIR_EraseFromParent, /*InsnID*/0,
4360 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361 : // GIR_Coverage, 1255,
4362 : GIR_Done,
4363 : // Label 376: @8739
4364 : GIM_Try, /*On fail goto*//*Label 377*/ 8779, // Rule ID 334 //
4365 : GIM_CheckFeatures, GIFBS_HasDSP,
4366 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4367 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4368 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4369 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4370 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4371 : // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4372 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4373 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4374 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4375 : GIR_EraseFromParent, /*InsnID*/0,
4376 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4377 : // GIR_Coverage, 334,
4378 : GIR_Done,
4379 : // Label 377: @8779
4380 : GIM_Try, /*On fail goto*//*Label 378*/ 8819, // Rule ID 341 //
4381 : GIM_CheckFeatures, GIFBS_HasDSP,
4382 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4383 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4384 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4385 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4386 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4387 : // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4388 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4389 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4391 : GIR_EraseFromParent, /*InsnID*/0,
4392 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393 : // GIR_Coverage, 341,
4394 : GIR_Done,
4395 : // Label 378: @8819
4396 : GIM_Try, /*On fail goto*//*Label 379*/ 8859, // Rule ID 342 //
4397 : GIM_CheckFeatures, GIFBS_HasDSP,
4398 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4399 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4400 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4401 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4403 : // (intrinsic_wo_chain:{ *:[i32] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4404 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4405 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4406 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4407 : GIR_EraseFromParent, /*InsnID*/0,
4408 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4409 : // GIR_Coverage, 342,
4410 : GIR_Done,
4411 : // Label 379: @8859
4412 : GIM_Try, /*On fail goto*//*Label 380*/ 8899, // Rule ID 343 //
4413 : GIM_CheckFeatures, GIFBS_HasDSP,
4414 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4415 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4416 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4417 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4418 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4419 : // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4420 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4421 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4422 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4423 : GIR_EraseFromParent, /*InsnID*/0,
4424 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4425 : // GIR_Coverage, 343,
4426 : GIR_Done,
4427 : // Label 380: @8899
4428 : GIM_Try, /*On fail goto*//*Label 381*/ 8939, // Rule ID 344 //
4429 : GIM_CheckFeatures, GIFBS_HasDSP,
4430 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4431 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4432 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4433 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4435 : // (intrinsic_wo_chain:{ *:[v2i16] } 3492:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4436 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4437 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4438 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4439 : GIR_EraseFromParent, /*InsnID*/0,
4440 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4441 : // GIR_Coverage, 344,
4442 : GIR_Done,
4443 : // Label 381: @8939
4444 : GIM_Try, /*On fail goto*//*Label 382*/ 8979, // Rule ID 345 //
4445 : GIM_CheckFeatures, GIFBS_HasDSP,
4446 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4447 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4448 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4449 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4450 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4451 : // (intrinsic_wo_chain:{ *:[v2i16] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4452 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4453 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4454 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4455 : GIR_EraseFromParent, /*InsnID*/0,
4456 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457 : // GIR_Coverage, 345,
4458 : GIR_Done,
4459 : // Label 382: @8979
4460 : GIM_Try, /*On fail goto*//*Label 383*/ 9019, // Rule ID 346 //
4461 : GIM_CheckFeatures, GIFBS_HasDSP,
4462 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4463 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4464 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4465 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4466 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4467 : // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4468 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4469 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4470 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4471 : GIR_EraseFromParent, /*InsnID*/0,
4472 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4473 : // GIR_Coverage, 346,
4474 : GIR_Done,
4475 : // Label 383: @9019
4476 : GIM_Try, /*On fail goto*//*Label 384*/ 9059, // Rule ID 347 //
4477 : GIM_CheckFeatures, GIFBS_HasDSP,
4478 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4479 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4480 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4481 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4482 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4483 : // (intrinsic_wo_chain:{ *:[v2i16] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4484 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4485 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4486 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4487 : GIR_EraseFromParent, /*InsnID*/0,
4488 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4489 : // GIR_Coverage, 347,
4490 : GIR_Done,
4491 : // Label 384: @9059
4492 : GIM_Try, /*On fail goto*//*Label 385*/ 9099, // Rule ID 348 //
4493 : GIM_CheckFeatures, GIFBS_HasDSP,
4494 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4495 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4496 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4497 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4498 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4499 : // (intrinsic_wo_chain:{ *:[v2i16] } 3496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4500 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4501 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4502 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4503 : GIR_EraseFromParent, /*InsnID*/0,
4504 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4505 : // GIR_Coverage, 348,
4506 : GIR_Done,
4507 : // Label 385: @9099
4508 : GIM_Try, /*On fail goto*//*Label 386*/ 9139, // Rule ID 349 //
4509 : GIM_CheckFeatures, GIFBS_HasDSP,
4510 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4511 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4512 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4515 : // (intrinsic_wo_chain:{ *:[v2i16] } 3495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4516 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4517 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4519 : GIR_EraseFromParent, /*InsnID*/0,
4520 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4521 : // GIR_Coverage, 349,
4522 : GIR_Done,
4523 : // Label 386: @9139
4524 : GIM_Try, /*On fail goto*//*Label 387*/ 9179, // Rule ID 350 //
4525 : GIM_CheckFeatures, GIFBS_HasDSP,
4526 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4527 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4528 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4529 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4530 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4531 : // (intrinsic_wo_chain:{ *:[v2i16] } 3497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4532 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4533 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4534 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4535 : GIR_EraseFromParent, /*InsnID*/0,
4536 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4537 : // GIR_Coverage, 350,
4538 : GIR_Done,
4539 : // Label 387: @9179
4540 : GIM_Try, /*On fail goto*//*Label 388*/ 9219, // Rule ID 398 //
4541 : GIM_CheckFeatures, GIFBS_HasDSP,
4542 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4543 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4544 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4545 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4546 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4547 : // (intrinsic_wo_chain:{ *:[i32] } 3064:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4548 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4549 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4550 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4551 : GIR_EraseFromParent, /*InsnID*/0,
4552 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4553 : // GIR_Coverage, 398,
4554 : GIR_Done,
4555 : // Label 388: @9219
4556 : GIM_Try, /*On fail goto*//*Label 389*/ 9259, // Rule ID 402 //
4557 : GIM_CheckFeatures, GIFBS_HasDSP,
4558 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4559 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4560 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4561 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4562 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4563 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4564 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4565 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4566 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4567 : GIR_EraseFromParent, /*InsnID*/0,
4568 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4569 : // GIR_Coverage, 402,
4570 : GIR_Done,
4571 : // Label 389: @9259
4572 : GIM_Try, /*On fail goto*//*Label 390*/ 9299, // Rule ID 403 //
4573 : GIM_CheckFeatures, GIFBS_HasDSP,
4574 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4575 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4576 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4577 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4578 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4579 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4580 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4581 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4582 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4583 : GIR_EraseFromParent, /*InsnID*/0,
4584 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585 : // GIR_Coverage, 403,
4586 : GIR_Done,
4587 : // Label 390: @9299
4588 : GIM_Try, /*On fail goto*//*Label 391*/ 9339, // Rule ID 648 //
4589 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4590 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4591 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4592 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4593 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4594 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4595 : // (intrinsic_wo_chain:{ *:[v4i32] } 3216:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4596 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4597 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4598 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4599 : GIR_EraseFromParent, /*InsnID*/0,
4600 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4601 : // GIR_Coverage, 648,
4602 : GIR_Done,
4603 : // Label 391: @9339
4604 : GIM_Try, /*On fail goto*//*Label 392*/ 9379, // Rule ID 649 //
4605 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4606 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4607 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4608 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4609 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4610 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4611 : // (intrinsic_wo_chain:{ *:[v2i64] } 3215:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4612 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4613 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4614 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4615 : GIR_EraseFromParent, /*InsnID*/0,
4616 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4617 : // GIR_Coverage, 649,
4618 : GIR_Done,
4619 : // Label 392: @9379
4620 : GIM_Try, /*On fail goto*//*Label 393*/ 9419, // Rule ID 672 //
4621 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4622 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4623 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4624 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4625 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4627 : // (intrinsic_wo_chain:{ *:[v4f32] } 3242:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4628 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4629 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4631 : GIR_EraseFromParent, /*InsnID*/0,
4632 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4633 : // GIR_Coverage, 672,
4634 : GIR_Done,
4635 : // Label 393: @9419
4636 : GIM_Try, /*On fail goto*//*Label 394*/ 9459, // Rule ID 673 //
4637 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4638 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4639 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4640 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4641 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4642 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4643 : // (intrinsic_wo_chain:{ *:[v2f64] } 3241:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4644 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4645 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4646 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4647 : GIR_EraseFromParent, /*InsnID*/0,
4648 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4649 : // GIR_Coverage, 673,
4650 : GIR_Done,
4651 : // Label 394: @9459
4652 : GIM_Try, /*On fail goto*//*Label 395*/ 9499, // Rule ID 674 //
4653 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4654 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4655 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4656 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4659 : // (intrinsic_wo_chain:{ *:[v4f32] } 3244:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4660 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4661 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4662 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4663 : GIR_EraseFromParent, /*InsnID*/0,
4664 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4665 : // GIR_Coverage, 674,
4666 : GIR_Done,
4667 : // Label 395: @9499
4668 : GIM_Try, /*On fail goto*//*Label 396*/ 9539, // Rule ID 675 //
4669 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4670 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4671 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4672 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4673 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4674 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4675 : // (intrinsic_wo_chain:{ *:[v2f64] } 3243:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4676 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4677 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4678 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4679 : GIR_EraseFromParent, /*InsnID*/0,
4680 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681 : // GIR_Coverage, 675,
4682 : GIR_Done,
4683 : // Label 396: @9539
4684 : GIM_Try, /*On fail goto*//*Label 397*/ 9579, // Rule ID 680 //
4685 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4686 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
4687 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4688 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4690 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4691 : // (intrinsic_wo_chain:{ *:[v4f32] } 3250:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4692 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4693 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4694 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4695 : GIR_EraseFromParent, /*InsnID*/0,
4696 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4697 : // GIR_Coverage, 680,
4698 : GIR_Done,
4699 : // Label 397: @9579
4700 : GIM_Try, /*On fail goto*//*Label 398*/ 9619, // Rule ID 681 //
4701 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4702 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
4703 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4704 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4705 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4706 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4707 : // (intrinsic_wo_chain:{ *:[v2f64] } 3249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4708 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
4709 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4710 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4711 : GIR_EraseFromParent, /*InsnID*/0,
4712 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4713 : // GIR_Coverage, 681,
4714 : GIR_Done,
4715 : // Label 398: @9619
4716 : GIM_Try, /*On fail goto*//*Label 399*/ 9659, // Rule ID 682 //
4717 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4718 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
4719 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4720 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4722 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4723 : // (intrinsic_wo_chain:{ *:[v4f32] } 3252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
4725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4727 : GIR_EraseFromParent, /*InsnID*/0,
4728 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4729 : // GIR_Coverage, 682,
4730 : GIR_Done,
4731 : // Label 399: @9659
4732 : GIM_Try, /*On fail goto*//*Label 400*/ 9699, // Rule ID 683 //
4733 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4734 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d,
4735 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4736 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4737 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4738 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4739 : // (intrinsic_wo_chain:{ *:[v2f64] } 3251:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4740 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
4741 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4742 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4743 : GIR_EraseFromParent, /*InsnID*/0,
4744 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4745 : // GIR_Coverage, 683,
4746 : GIR_Done,
4747 : // Label 400: @9699
4748 : GIM_Try, /*On fail goto*//*Label 401*/ 9739, // Rule ID 708 //
4749 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4750 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w,
4751 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4752 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4753 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4754 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4755 : // (intrinsic_wo_chain:{ *:[v4f32] } 3274:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4756 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
4757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4759 : GIR_EraseFromParent, /*InsnID*/0,
4760 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4761 : // GIR_Coverage, 708,
4762 : GIR_Done,
4763 : // Label 401: @9739
4764 : GIM_Try, /*On fail goto*//*Label 402*/ 9779, // Rule ID 709 //
4765 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4766 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d,
4767 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4768 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4769 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4770 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4771 : // (intrinsic_wo_chain:{ *:[v2f64] } 3273:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4772 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
4773 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4774 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4775 : GIR_EraseFromParent, /*InsnID*/0,
4776 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4777 : // GIR_Coverage, 709,
4778 : GIR_Done,
4779 : // Label 402: @9779
4780 : GIM_Try, /*On fail goto*//*Label 403*/ 9819, // Rule ID 710 //
4781 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4782 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w,
4783 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4784 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4785 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4786 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4787 : // (intrinsic_wo_chain:{ *:[v4f32] } 3278:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4788 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
4789 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4790 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4791 : GIR_EraseFromParent, /*InsnID*/0,
4792 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4793 : // GIR_Coverage, 710,
4794 : GIR_Done,
4795 : // Label 403: @9819
4796 : GIM_Try, /*On fail goto*//*Label 404*/ 9859, // Rule ID 711 //
4797 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4798 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d,
4799 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4800 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4801 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4802 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4803 : // (intrinsic_wo_chain:{ *:[v2f64] } 3277:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4804 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
4805 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4807 : GIR_EraseFromParent, /*InsnID*/0,
4808 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4809 : // GIR_Coverage, 711,
4810 : GIR_Done,
4811 : // Label 404: @9859
4812 : GIM_Try, /*On fail goto*//*Label 405*/ 9899, // Rule ID 738 //
4813 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4814 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w,
4815 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4816 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4818 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4819 : // (intrinsic_wo_chain:{ *:[v4i32] } 3306:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4820 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
4821 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4822 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4823 : GIR_EraseFromParent, /*InsnID*/0,
4824 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4825 : // GIR_Coverage, 738,
4826 : GIR_Done,
4827 : // Label 405: @9899
4828 : GIM_Try, /*On fail goto*//*Label 406*/ 9939, // Rule ID 739 //
4829 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4830 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d,
4831 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4832 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4833 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4835 : // (intrinsic_wo_chain:{ *:[v2i64] } 3305:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4836 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
4837 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4838 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4839 : GIR_EraseFromParent, /*InsnID*/0,
4840 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4841 : // GIR_Coverage, 739,
4842 : GIR_Done,
4843 : // Label 406: @9939
4844 : GIM_Try, /*On fail goto*//*Label 407*/ 9979, // Rule ID 740 //
4845 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4846 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w,
4847 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4848 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4849 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4850 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4851 : // (intrinsic_wo_chain:{ *:[v4i32] } 3308:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4852 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
4853 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4854 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4855 : GIR_EraseFromParent, /*InsnID*/0,
4856 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4857 : // GIR_Coverage, 740,
4858 : GIR_Done,
4859 : // Label 407: @9979
4860 : GIM_Try, /*On fail goto*//*Label 408*/ 10019, // Rule ID 741 //
4861 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4862 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d,
4863 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4864 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4865 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4866 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4867 : // (intrinsic_wo_chain:{ *:[v2i64] } 3307:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4868 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
4869 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4871 : GIR_EraseFromParent, /*InsnID*/0,
4872 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4873 : // GIR_Coverage, 741,
4874 : GIR_Done,
4875 : // Label 408: @10019
4876 : GIM_Try, /*On fail goto*//*Label 409*/ 10059, // Rule ID 876 //
4877 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4878 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b,
4879 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
4880 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4881 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4882 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
4883 : // (intrinsic_wo_chain:{ *:[v16i8] } 3461:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
4884 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
4885 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4886 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4887 : GIR_EraseFromParent, /*InsnID*/0,
4888 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4889 : // GIR_Coverage, 876,
4890 : GIR_Done,
4891 : // Label 409: @10059
4892 : GIM_Try, /*On fail goto*//*Label 410*/ 10099, // Rule ID 877 //
4893 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4894 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h,
4895 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
4896 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4899 : // (intrinsic_wo_chain:{ *:[v8i16] } 3463:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4900 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
4901 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4902 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4903 : GIR_EraseFromParent, /*InsnID*/0,
4904 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4905 : // GIR_Coverage, 877,
4906 : GIR_Done,
4907 : // Label 410: @10099
4908 : GIM_Try, /*On fail goto*//*Label 411*/ 10139, // Rule ID 878 //
4909 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4910 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w,
4911 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4912 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4913 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4914 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4915 : // (intrinsic_wo_chain:{ *:[v4i32] } 3464:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4916 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
4917 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4918 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4919 : GIR_EraseFromParent, /*InsnID*/0,
4920 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4921 : // GIR_Coverage, 878,
4922 : GIR_Done,
4923 : // Label 411: @10139
4924 : GIM_Try, /*On fail goto*//*Label 412*/ 10179, // Rule ID 879 //
4925 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4926 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d,
4927 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4928 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4931 : // (intrinsic_wo_chain:{ *:[v2i64] } 3462:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
4932 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
4933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4935 : GIR_EraseFromParent, /*InsnID*/0,
4936 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4937 : // GIR_Coverage, 879,
4938 : GIR_Done,
4939 : // Label 412: @10179
4940 : GIM_Try, /*On fail goto*//*Label 413*/ 10219, // Rule ID 1217 //
4941 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4942 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4943 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4944 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4945 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4946 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4947 : // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
4948 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
4949 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4950 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4951 : GIR_EraseFromParent, /*InsnID*/0,
4952 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4953 : // GIR_Coverage, 1217,
4954 : GIR_Done,
4955 : // Label 413: @10219
4956 : GIM_Try, /*On fail goto*//*Label 414*/ 10259, // Rule ID 1218 //
4957 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4958 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4959 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4960 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4963 : // (intrinsic_wo_chain:{ *:[i32] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
4964 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
4965 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4966 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4967 : GIR_EraseFromParent, /*InsnID*/0,
4968 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4969 : // GIR_Coverage, 1218,
4970 : GIR_Done,
4971 : // Label 414: @10259
4972 : GIM_Try, /*On fail goto*//*Label 415*/ 10299, // Rule ID 1219 //
4973 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4974 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4975 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4976 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4977 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4978 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4979 : // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
4980 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
4981 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4982 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4983 : GIR_EraseFromParent, /*InsnID*/0,
4984 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4985 : // GIR_Coverage, 1219,
4986 : GIR_Done,
4987 : // Label 415: @10299
4988 : GIM_Try, /*On fail goto*//*Label 416*/ 10339, // Rule ID 1220 //
4989 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4990 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4991 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4992 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4994 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4995 : // (intrinsic_wo_chain:{ *:[v2i16] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
4996 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
4997 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4998 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4999 : GIR_EraseFromParent, /*InsnID*/0,
5000 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5001 : // GIR_Coverage, 1220,
5002 : GIR_Done,
5003 : // Label 416: @10339
5004 : GIM_Try, /*On fail goto*//*Label 417*/ 10379, // Rule ID 1221 //
5005 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5006 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
5007 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5008 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5009 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5011 : // (intrinsic_wo_chain:{ *:[v2i16] } 3492:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5012 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
5013 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5014 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5015 : GIR_EraseFromParent, /*InsnID*/0,
5016 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5017 : // GIR_Coverage, 1221,
5018 : GIR_Done,
5019 : // Label 417: @10379
5020 : GIM_Try, /*On fail goto*//*Label 418*/ 10419, // Rule ID 1222 //
5021 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5022 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
5023 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5024 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5027 : // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
5029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5031 : GIR_EraseFromParent, /*InsnID*/0,
5032 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5033 : // GIR_Coverage, 1222,
5034 : GIR_Done,
5035 : // Label 418: @10419
5036 : GIM_Try, /*On fail goto*//*Label 419*/ 10459, // Rule ID 1223 //
5037 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5038 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
5039 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5040 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5041 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5043 : // (intrinsic_wo_chain:{ *:[v2i16] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5044 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
5045 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5046 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5047 : GIR_EraseFromParent, /*InsnID*/0,
5048 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5049 : // GIR_Coverage, 1223,
5050 : GIR_Done,
5051 : // Label 419: @10459
5052 : GIM_Try, /*On fail goto*//*Label 420*/ 10499, // Rule ID 1224 //
5053 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5054 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
5055 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5056 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5058 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5059 : // (intrinsic_wo_chain:{ *:[v2i16] } 3495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5060 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
5061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5063 : GIR_EraseFromParent, /*InsnID*/0,
5064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5065 : // GIR_Coverage, 1224,
5066 : GIR_Done,
5067 : // Label 420: @10499
5068 : GIM_Try, /*On fail goto*//*Label 421*/ 10539, // Rule ID 1225 //
5069 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5070 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
5071 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5072 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5073 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5075 : // (intrinsic_wo_chain:{ *:[v2i16] } 3496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5076 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
5077 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5078 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5079 : GIR_EraseFromParent, /*InsnID*/0,
5080 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5081 : // GIR_Coverage, 1225,
5082 : GIR_Done,
5083 : // Label 421: @10539
5084 : GIM_Try, /*On fail goto*//*Label 422*/ 10579, // Rule ID 1226 //
5085 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5086 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
5087 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5088 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5089 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5090 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5091 : // (intrinsic_wo_chain:{ *:[v2i16] } 3497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5092 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
5093 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5094 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5095 : GIR_EraseFromParent, /*InsnID*/0,
5096 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5097 : // GIR_Coverage, 1226,
5098 : GIR_Done,
5099 : // Label 422: @10579
5100 : GIM_Try, /*On fail goto*//*Label 423*/ 10619, // Rule ID 1252 //
5101 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5102 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
5103 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5104 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5107 : // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
5108 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
5109 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5111 : GIR_EraseFromParent, /*InsnID*/0,
5112 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5113 : // GIR_Coverage, 1252,
5114 : GIR_Done,
5115 : // Label 423: @10619
5116 : GIM_Try, /*On fail goto*//*Label 424*/ 10659, // Rule ID 1256 //
5117 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5118 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
5119 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5120 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5121 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5122 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5123 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
5124 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
5125 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5126 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5127 : GIR_EraseFromParent, /*InsnID*/0,
5128 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5129 : // GIR_Coverage, 1256,
5130 : GIR_Done,
5131 : // Label 424: @10659
5132 : GIM_Try, /*On fail goto*//*Label 425*/ 10699, // Rule ID 1257 //
5133 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5134 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
5135 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5136 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5137 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5139 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
5140 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
5141 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5143 : GIR_EraseFromParent, /*InsnID*/0,
5144 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5145 : // GIR_Coverage, 1257,
5146 : GIR_Done,
5147 : // Label 425: @10699
5148 : GIM_Try, /*On fail goto*//*Label 426*/ 10739, // Rule ID 1267 //
5149 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5150 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
5151 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5152 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5153 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5154 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5155 : // (intrinsic_wo_chain:{ *:[i32] } 3064:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
5156 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
5157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5158 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5159 : GIR_EraseFromParent, /*InsnID*/0,
5160 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5161 : // GIR_Coverage, 1267,
5162 : GIR_Done,
5163 : // Label 426: @10739
5164 : GIM_Reject,
5165 : // Label 372: @10740
5166 : GIM_Try, /*On fail goto*//*Label 427*/ 22008,
5167 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
5168 : GIM_Try, /*On fail goto*//*Label 428*/ 10804, // Rule ID 357 //
5169 : GIM_CheckFeatures, GIFBS_HasDSP,
5170 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5171 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5172 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5173 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5174 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5175 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5176 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5177 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5178 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5179 : // MIs[1] Operand 1
5180 : // No operand predicates
5181 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5182 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5183 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
5184 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5185 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5186 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5187 : GIR_EraseFromParent, /*InsnID*/0,
5188 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5189 : // GIR_Coverage, 357,
5190 : GIR_Done,
5191 : // Label 428: @10804
5192 : GIM_Try, /*On fail goto*//*Label 429*/ 10863, // Rule ID 361 //
5193 : GIM_CheckFeatures, GIFBS_HasDSP,
5194 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5195 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5196 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5197 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5198 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5199 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5200 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5201 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5202 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5203 : // MIs[1] Operand 1
5204 : // No operand predicates
5205 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5206 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5207 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
5208 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5209 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5210 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5211 : GIR_EraseFromParent, /*InsnID*/0,
5212 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5213 : // GIR_Coverage, 361,
5214 : GIR_Done,
5215 : // Label 429: @10863
5216 : GIM_Try, /*On fail goto*//*Label 430*/ 10922, // Rule ID 452 //
5217 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5218 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5219 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5220 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5221 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5222 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5223 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5224 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5225 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5226 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5227 : // MIs[1] Operand 1
5228 : // No operand predicates
5229 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5230 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5231 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
5232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5233 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5234 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5235 : GIR_EraseFromParent, /*InsnID*/0,
5236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5237 : // GIR_Coverage, 452,
5238 : GIR_Done,
5239 : // Label 430: @10922
5240 : GIM_Try, /*On fail goto*//*Label 431*/ 10981, // Rule ID 906 //
5241 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5242 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b,
5243 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5244 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5245 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5246 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5248 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5249 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5250 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5251 : // MIs[1] Operand 1
5252 : // No operand predicates
5253 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5254 : // (intrinsic_wo_chain:{ *:[v16i8] } 3510:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5255 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
5256 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5258 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5259 : GIR_EraseFromParent, /*InsnID*/0,
5260 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5261 : // GIR_Coverage, 906,
5262 : GIR_Done,
5263 : // Label 431: @10981
5264 : GIM_Try, /*On fail goto*//*Label 432*/ 11040, // Rule ID 907 //
5265 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5266 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h,
5267 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5268 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5269 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5272 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5273 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5274 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5275 : // MIs[1] Operand 1
5276 : // No operand predicates
5277 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5278 : // (intrinsic_wo_chain:{ *:[v8i16] } 3512:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5279 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
5280 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5282 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5283 : GIR_EraseFromParent, /*InsnID*/0,
5284 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5285 : // GIR_Coverage, 907,
5286 : GIR_Done,
5287 : // Label 432: @11040
5288 : GIM_Try, /*On fail goto*//*Label 433*/ 11099, // Rule ID 908 //
5289 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5290 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w,
5291 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5292 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5293 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5296 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5297 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5298 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5299 : // MIs[1] Operand 1
5300 : // No operand predicates
5301 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5302 : // (intrinsic_wo_chain:{ *:[v4i32] } 3513:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5303 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
5304 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5305 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5306 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5307 : GIR_EraseFromParent, /*InsnID*/0,
5308 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5309 : // GIR_Coverage, 908,
5310 : GIR_Done,
5311 : // Label 433: @11099
5312 : GIM_Try, /*On fail goto*//*Label 434*/ 11158, // Rule ID 909 //
5313 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5314 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d,
5315 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5316 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5317 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5318 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5319 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5320 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5321 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5322 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5323 : // MIs[1] Operand 1
5324 : // No operand predicates
5325 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5326 : // (intrinsic_wo_chain:{ *:[v2i64] } 3511:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5327 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
5328 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5329 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5330 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5331 : GIR_EraseFromParent, /*InsnID*/0,
5332 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5333 : // GIR_Coverage, 909,
5334 : GIR_Done,
5335 : // Label 434: @11158
5336 : GIM_Try, /*On fail goto*//*Label 435*/ 11217, // Rule ID 910 //
5337 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5338 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b,
5339 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5340 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5341 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5342 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5343 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5344 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5345 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5346 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5347 : // MIs[1] Operand 1
5348 : // No operand predicates
5349 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5350 : // (intrinsic_wo_chain:{ *:[v16i8] } 3514:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5351 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
5352 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5353 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5354 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5355 : GIR_EraseFromParent, /*InsnID*/0,
5356 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5357 : // GIR_Coverage, 910,
5358 : GIR_Done,
5359 : // Label 435: @11217
5360 : GIM_Try, /*On fail goto*//*Label 436*/ 11276, // Rule ID 911 //
5361 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5362 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h,
5363 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5364 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5365 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5366 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5367 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5368 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5369 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5370 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5371 : // MIs[1] Operand 1
5372 : // No operand predicates
5373 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5374 : // (intrinsic_wo_chain:{ *:[v8i16] } 3516:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5375 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
5376 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5377 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5378 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5379 : GIR_EraseFromParent, /*InsnID*/0,
5380 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5381 : // GIR_Coverage, 911,
5382 : GIR_Done,
5383 : // Label 436: @11276
5384 : GIM_Try, /*On fail goto*//*Label 437*/ 11335, // Rule ID 912 //
5385 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5386 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w,
5387 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5388 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5389 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5392 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5393 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5394 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5395 : // MIs[1] Operand 1
5396 : // No operand predicates
5397 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5398 : // (intrinsic_wo_chain:{ *:[v4i32] } 3517:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5399 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
5400 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5401 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5402 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5403 : GIR_EraseFromParent, /*InsnID*/0,
5404 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5405 : // GIR_Coverage, 912,
5406 : GIR_Done,
5407 : // Label 437: @11335
5408 : GIM_Try, /*On fail goto*//*Label 438*/ 11394, // Rule ID 913 //
5409 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5410 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d,
5411 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5412 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5413 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5414 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5415 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5416 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5417 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5418 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5419 : // MIs[1] Operand 1
5420 : // No operand predicates
5421 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5422 : // (intrinsic_wo_chain:{ *:[v2i64] } 3515:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5423 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
5424 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5425 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5426 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5427 : GIR_EraseFromParent, /*InsnID*/0,
5428 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5429 : // GIR_Coverage, 913,
5430 : GIR_Done,
5431 : // Label 438: @11394
5432 : GIM_Try, /*On fail goto*//*Label 439*/ 11453, // Rule ID 953 //
5433 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5434 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b,
5435 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5436 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5437 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5438 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5439 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5440 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5441 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5442 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5443 : // MIs[1] Operand 1
5444 : // No operand predicates
5445 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5446 : // (intrinsic_wo_chain:{ *:[v16i8] } 3569:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5447 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
5448 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5449 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5450 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5451 : GIR_EraseFromParent, /*InsnID*/0,
5452 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5453 : // GIR_Coverage, 953,
5454 : GIR_Done,
5455 : // Label 439: @11453
5456 : GIM_Try, /*On fail goto*//*Label 440*/ 11512, // Rule ID 954 //
5457 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5458 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h,
5459 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5460 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5461 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5462 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5464 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5465 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5466 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5467 : // MIs[1] Operand 1
5468 : // No operand predicates
5469 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5470 : // (intrinsic_wo_chain:{ *:[v8i16] } 3571:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5471 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
5472 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5473 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5474 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5475 : GIR_EraseFromParent, /*InsnID*/0,
5476 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5477 : // GIR_Coverage, 954,
5478 : GIR_Done,
5479 : // Label 440: @11512
5480 : GIM_Try, /*On fail goto*//*Label 441*/ 11571, // Rule ID 955 //
5481 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5482 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w,
5483 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5484 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5485 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5487 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5488 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5489 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5490 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5491 : // MIs[1] Operand 1
5492 : // No operand predicates
5493 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5494 : // (intrinsic_wo_chain:{ *:[v4i32] } 3572:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5495 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
5496 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5497 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5498 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5499 : GIR_EraseFromParent, /*InsnID*/0,
5500 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5501 : // GIR_Coverage, 955,
5502 : GIR_Done,
5503 : // Label 441: @11571
5504 : GIM_Try, /*On fail goto*//*Label 442*/ 11630, // Rule ID 956 //
5505 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5506 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d,
5507 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5508 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5509 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5510 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5511 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5512 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5513 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5514 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5515 : // MIs[1] Operand 1
5516 : // No operand predicates
5517 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5518 : // (intrinsic_wo_chain:{ *:[v2i64] } 3570:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5519 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
5520 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5521 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5522 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5523 : GIR_EraseFromParent, /*InsnID*/0,
5524 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5525 : // GIR_Coverage, 956,
5526 : GIR_Done,
5527 : // Label 442: @11630
5528 : GIM_Try, /*On fail goto*//*Label 443*/ 11689, // Rule ID 969 //
5529 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5530 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b,
5531 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5532 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5533 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5534 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5536 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5537 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5538 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5539 : // MIs[1] Operand 1
5540 : // No operand predicates
5541 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5542 : // (intrinsic_wo_chain:{ *:[v16i8] } 3585:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5543 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
5544 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5545 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5546 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5547 : GIR_EraseFromParent, /*InsnID*/0,
5548 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5549 : // GIR_Coverage, 969,
5550 : GIR_Done,
5551 : // Label 443: @11689
5552 : GIM_Try, /*On fail goto*//*Label 444*/ 11748, // Rule ID 970 //
5553 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5554 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h,
5555 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5556 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5557 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5560 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5561 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5562 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5563 : // MIs[1] Operand 1
5564 : // No operand predicates
5565 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5566 : // (intrinsic_wo_chain:{ *:[v8i16] } 3587:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5567 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
5568 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5569 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5570 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5571 : GIR_EraseFromParent, /*InsnID*/0,
5572 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5573 : // GIR_Coverage, 970,
5574 : GIR_Done,
5575 : // Label 444: @11748
5576 : GIM_Try, /*On fail goto*//*Label 445*/ 11807, // Rule ID 971 //
5577 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5578 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w,
5579 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5580 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5581 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5582 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5583 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5584 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5585 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5586 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5587 : // MIs[1] Operand 1
5588 : // No operand predicates
5589 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5590 : // (intrinsic_wo_chain:{ *:[v4i32] } 3588:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5591 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
5592 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5593 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5594 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5595 : GIR_EraseFromParent, /*InsnID*/0,
5596 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5597 : // GIR_Coverage, 971,
5598 : GIR_Done,
5599 : // Label 445: @11807
5600 : GIM_Try, /*On fail goto*//*Label 446*/ 11866, // Rule ID 972 //
5601 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5602 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d,
5603 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5605 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5608 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5609 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5610 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5611 : // MIs[1] Operand 1
5612 : // No operand predicates
5613 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5614 : // (intrinsic_wo_chain:{ *:[v2i64] } 3586:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5615 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
5616 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5617 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5618 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5619 : GIR_EraseFromParent, /*InsnID*/0,
5620 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5621 : // GIR_Coverage, 972,
5622 : GIR_Done,
5623 : // Label 446: @11866
5624 : GIM_Try, /*On fail goto*//*Label 447*/ 11925, // Rule ID 1211 //
5625 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5626 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5627 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5628 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5629 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5630 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5631 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5632 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5633 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5634 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5635 : // MIs[1] Operand 1
5636 : // No operand predicates
5637 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5638 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
5639 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
5640 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5641 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5642 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5643 : GIR_EraseFromParent, /*InsnID*/0,
5644 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5645 : // GIR_Coverage, 1211,
5646 : GIR_Done,
5647 : // Label 447: @11925
5648 : GIM_Try, /*On fail goto*//*Label 448*/ 11984, // Rule ID 1215 //
5649 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5650 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5651 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5652 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5653 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5654 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5655 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5656 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5657 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5658 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5659 : // MIs[1] Operand 1
5660 : // No operand predicates
5661 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5662 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
5663 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
5664 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5665 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5666 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5667 : GIR_EraseFromParent, /*InsnID*/0,
5668 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5669 : // GIR_Coverage, 1215,
5670 : GIR_Done,
5671 : // Label 448: @11984
5672 : GIM_Try, /*On fail goto*//*Label 449*/ 12043, // Rule ID 1290 //
5673 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
5674 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5675 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5676 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5677 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5678 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5679 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5680 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5681 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5682 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5683 : // MIs[1] Operand 1
5684 : // No operand predicates
5685 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5686 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
5687 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
5688 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5689 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5690 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5691 : GIR_EraseFromParent, /*InsnID*/0,
5692 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5693 : // GIR_Coverage, 1290,
5694 : GIR_Done,
5695 : // Label 449: @12043
5696 : GIM_Try, /*On fail goto*//*Label 450*/ 12098, // Rule ID 1861 //
5697 : GIM_CheckFeatures, GIFBS_HasDSP,
5698 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
5699 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5700 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5701 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5703 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5704 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5705 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5706 : // MIs[1] Operand 1
5707 : // No operand predicates
5708 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5709 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
5710 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
5711 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5712 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5713 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5714 : GIR_EraseFromParent, /*InsnID*/0,
5715 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5716 : // GIR_Coverage, 1861,
5717 : GIR_Done,
5718 : // Label 450: @12098
5719 : GIM_Try, /*On fail goto*//*Label 451*/ 12153, // Rule ID 1862 //
5720 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5721 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
5722 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5723 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5724 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5726 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5727 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5728 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5729 : // MIs[1] Operand 1
5730 : // No operand predicates
5731 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5732 : // (intrinsic_wo_chain:{ *:[v2i16] } 3531:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
5733 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
5734 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5735 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5736 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5737 : GIR_EraseFromParent, /*InsnID*/0,
5738 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5739 : // GIR_Coverage, 1862,
5740 : GIR_Done,
5741 : // Label 451: @12153
5742 : GIM_Try, /*On fail goto*//*Label 452*/ 12208, // Rule ID 1867 //
5743 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5744 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
5745 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5746 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5747 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5748 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5749 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5750 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5751 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5752 : // MIs[1] Operand 1
5753 : // No operand predicates
5754 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5755 : // (intrinsic_wo_chain:{ *:[v4i8] } 3527:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
5756 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
5757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5759 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5760 : GIR_EraseFromParent, /*InsnID*/0,
5761 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5762 : // GIR_Coverage, 1867,
5763 : GIR_Done,
5764 : // Label 452: @12208
5765 : GIM_Try, /*On fail goto*//*Label 453*/ 12263, // Rule ID 1868 //
5766 : GIM_CheckFeatures, GIFBS_HasDSP,
5767 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
5768 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5769 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5770 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5772 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5773 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5774 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5775 : // MIs[1] Operand 1
5776 : // No operand predicates
5777 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5778 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
5779 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
5780 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5781 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5782 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5783 : GIR_EraseFromParent, /*InsnID*/0,
5784 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5785 : // GIR_Coverage, 1868,
5786 : GIR_Done,
5787 : // Label 453: @12263
5788 : GIM_Try, /*On fail goto*//*Label 454*/ 12315, // Rule ID 327 //
5789 : GIM_CheckFeatures, GIFBS_HasDSP,
5790 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
5791 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5792 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5793 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
5794 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5795 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5796 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5797 : // (intrinsic_wo_chain:{ *:[v4i8] } 3000:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
5798 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
5799 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5800 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5801 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5802 : GIR_EraseFromParent, /*InsnID*/0,
5803 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5804 : // GIR_Coverage, 327,
5805 : GIR_Done,
5806 : // Label 454: @12315
5807 : GIM_Try, /*On fail goto*//*Label 455*/ 12367, // Rule ID 328 //
5808 : GIM_CheckFeatures, GIFBS_HasDSP,
5809 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
5810 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5811 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5812 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
5813 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5814 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5816 : // (intrinsic_wo_chain:{ *:[v4i8] } 3619:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
5817 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
5818 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5819 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5820 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5821 : GIR_EraseFromParent, /*InsnID*/0,
5822 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5823 : // GIR_Coverage, 328,
5824 : GIR_Done,
5825 : // Label 455: @12367
5826 : GIM_Try, /*On fail goto*//*Label 456*/ 12419, // Rule ID 329 //
5827 : GIM_CheckFeatures, GIFBS_HasDSP,
5828 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
5829 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5830 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5831 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5832 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5833 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5835 : // (intrinsic_wo_chain:{ *:[v2i16] } 2978:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5836 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
5837 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5838 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5839 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5840 : GIR_EraseFromParent, /*InsnID*/0,
5841 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5842 : // GIR_Coverage, 329,
5843 : GIR_Done,
5844 : // Label 456: @12419
5845 : GIM_Try, /*On fail goto*//*Label 457*/ 12471, // Rule ID 330 //
5846 : GIM_CheckFeatures, GIFBS_HasDSP,
5847 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
5848 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5849 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5850 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5852 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5854 : // (intrinsic_wo_chain:{ *:[v2i16] } 3594:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5855 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
5856 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5857 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5859 : GIR_EraseFromParent, /*InsnID*/0,
5860 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5861 : // GIR_Coverage, 330,
5862 : GIR_Done,
5863 : // Label 457: @12471
5864 : GIM_Try, /*On fail goto*//*Label 458*/ 12523, // Rule ID 333 //
5865 : GIM_CheckFeatures, GIFBS_HasDSP,
5866 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
5867 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5868 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5869 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5870 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5871 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5873 : // (intrinsic_wo_chain:{ *:[i32] } 3426:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
5874 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
5875 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5876 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5877 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5878 : GIR_EraseFromParent, /*InsnID*/0,
5879 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5880 : // GIR_Coverage, 333,
5881 : GIR_Done,
5882 : // Label 458: @12523
5883 : GIM_Try, /*On fail goto*//*Label 459*/ 12575, // Rule ID 337 //
5884 : GIM_CheckFeatures, GIFBS_HasDSP,
5885 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
5886 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5887 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5888 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5889 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5892 : // (intrinsic_wo_chain:{ *:[v4i8] } 3502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5893 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
5894 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5895 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5896 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5897 : GIR_EraseFromParent, /*InsnID*/0,
5898 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5899 : // GIR_Coverage, 337,
5900 : GIR_Done,
5901 : // Label 459: @12575
5902 : GIM_Try, /*On fail goto*//*Label 460*/ 12627, // Rule ID 338 //
5903 : GIM_CheckFeatures, GIFBS_HasDSP,
5904 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
5905 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5906 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5907 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5908 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5909 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5911 : // (intrinsic_wo_chain:{ *:[v2i16] } 3501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
5912 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
5913 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5914 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5915 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5916 : GIR_EraseFromParent, /*InsnID*/0,
5917 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5918 : // GIR_Coverage, 338,
5919 : GIR_Done,
5920 : // Label 460: @12627
5921 : GIM_Try, /*On fail goto*//*Label 461*/ 12679, // Rule ID 352 //
5922 : GIM_CheckFeatures, GIFBS_HasDSP,
5923 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
5924 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5925 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5926 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5927 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5928 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5930 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5931 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
5932 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5935 : GIR_EraseFromParent, /*InsnID*/0,
5936 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5937 : // GIR_Coverage, 352,
5938 : GIR_Done,
5939 : // Label 461: @12679
5940 : GIM_Try, /*On fail goto*//*Label 462*/ 12731, // Rule ID 356 //
5941 : GIM_CheckFeatures, GIFBS_HasDSP,
5942 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
5943 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5944 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5945 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5946 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5947 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5948 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5949 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5950 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
5951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5952 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5954 : GIR_EraseFromParent, /*InsnID*/0,
5955 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5956 : // GIR_Coverage, 356,
5957 : GIR_Done,
5958 : // Label 462: @12731
5959 : GIM_Try, /*On fail goto*//*Label 463*/ 12783, // Rule ID 358 //
5960 : GIM_CheckFeatures, GIFBS_HasDSP,
5961 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5962 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5963 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5964 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5968 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5969 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
5970 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5971 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5972 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5973 : GIR_EraseFromParent, /*InsnID*/0,
5974 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5975 : // GIR_Coverage, 358,
5976 : GIR_Done,
5977 : // Label 463: @12783
5978 : GIM_Try, /*On fail goto*//*Label 464*/ 12835, // Rule ID 362 //
5979 : GIM_CheckFeatures, GIFBS_HasDSP,
5980 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5981 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5982 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5983 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5984 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5985 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5987 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5988 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
5989 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5990 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5992 : GIR_EraseFromParent, /*InsnID*/0,
5993 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5994 : // GIR_Coverage, 362,
5995 : GIR_Done,
5996 : // Label 464: @12835
5997 : GIM_Try, /*On fail goto*//*Label 465*/ 12887, // Rule ID 399 //
5998 : GIM_CheckFeatures, GIFBS_HasDSP,
5999 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
6000 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6001 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6002 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6004 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6006 : // (intrinsic_wo_chain:{ *:[v2i16] } 3473:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6007 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
6008 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6009 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6011 : GIR_EraseFromParent, /*InsnID*/0,
6012 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6013 : // GIR_Coverage, 399,
6014 : GIR_Done,
6015 : // Label 465: @12887
6016 : GIM_Try, /*On fail goto*//*Label 466*/ 12939, // Rule ID 423 //
6017 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6018 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
6019 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6020 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6021 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6022 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6025 : // (intrinsic_wo_chain:{ *:[v4i8] } 3001:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6026 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
6027 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6028 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6030 : GIR_EraseFromParent, /*InsnID*/0,
6031 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6032 : // GIR_Coverage, 423,
6033 : GIR_Done,
6034 : // Label 466: @12939
6035 : GIM_Try, /*On fail goto*//*Label 467*/ 12991, // Rule ID 424 //
6036 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6037 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
6038 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6039 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6040 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6041 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6044 : // (intrinsic_wo_chain:{ *:[v4i8] } 3002:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6045 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
6046 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6047 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6048 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6049 : GIR_EraseFromParent, /*InsnID*/0,
6050 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6051 : // GIR_Coverage, 424,
6052 : GIR_Done,
6053 : // Label 467: @12991
6054 : GIM_Try, /*On fail goto*//*Label 468*/ 13043, // Rule ID 425 //
6055 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6056 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
6057 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6058 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6059 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6060 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6061 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6062 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6063 : // (intrinsic_wo_chain:{ *:[v4i8] } 3620:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6064 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
6065 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6066 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6067 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6068 : GIR_EraseFromParent, /*InsnID*/0,
6069 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6070 : // GIR_Coverage, 425,
6071 : GIR_Done,
6072 : // Label 468: @13043
6073 : GIM_Try, /*On fail goto*//*Label 469*/ 13095, // Rule ID 426 //
6074 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6075 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
6076 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6077 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6078 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6079 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6080 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6082 : // (intrinsic_wo_chain:{ *:[v4i8] } 3621:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6083 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
6084 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6085 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6086 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6087 : GIR_EraseFromParent, /*InsnID*/0,
6088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6089 : // GIR_Coverage, 426,
6090 : GIR_Done,
6091 : // Label 469: @13095
6092 : GIM_Try, /*On fail goto*//*Label 470*/ 13147, // Rule ID 427 //
6093 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6094 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
6095 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6096 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6097 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6098 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6099 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6100 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6101 : // (intrinsic_wo_chain:{ *:[v2i16] } 2980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6102 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
6103 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6104 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6105 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6106 : GIR_EraseFromParent, /*InsnID*/0,
6107 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6108 : // GIR_Coverage, 427,
6109 : GIR_Done,
6110 : // Label 470: @13147
6111 : GIM_Try, /*On fail goto*//*Label 471*/ 13199, // Rule ID 428 //
6112 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6113 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
6114 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6115 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6116 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6117 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6118 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6119 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6120 : // (intrinsic_wo_chain:{ *:[v2i16] } 2981:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6121 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
6122 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6123 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6124 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6125 : GIR_EraseFromParent, /*InsnID*/0,
6126 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6127 : // GIR_Coverage, 428,
6128 : GIR_Done,
6129 : // Label 471: @13199
6130 : GIM_Try, /*On fail goto*//*Label 472*/ 13251, // Rule ID 429 //
6131 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6132 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
6133 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6134 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6135 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6136 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6137 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6139 : // (intrinsic_wo_chain:{ *:[v2i16] } 3596:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6140 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
6141 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6143 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6144 : GIR_EraseFromParent, /*InsnID*/0,
6145 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6146 : // GIR_Coverage, 429,
6147 : GIR_Done,
6148 : // Label 472: @13251
6149 : GIM_Try, /*On fail goto*//*Label 473*/ 13303, // Rule ID 430 //
6150 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6151 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
6152 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6153 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6154 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6155 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6156 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6157 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6158 : // (intrinsic_wo_chain:{ *:[v2i16] } 3597:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6159 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
6160 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6161 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6162 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6163 : GIR_EraseFromParent, /*InsnID*/0,
6164 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6165 : // GIR_Coverage, 430,
6166 : GIR_Done,
6167 : // Label 473: @13303
6168 : GIM_Try, /*On fail goto*//*Label 474*/ 13355, // Rule ID 431 //
6169 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6170 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
6171 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6172 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6173 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6174 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6175 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6177 : // (intrinsic_wo_chain:{ *:[i32] } 2983:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6178 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
6179 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6180 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6181 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6182 : GIR_EraseFromParent, /*InsnID*/0,
6183 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6184 : // GIR_Coverage, 431,
6185 : GIR_Done,
6186 : // Label 474: @13355
6187 : GIM_Try, /*On fail goto*//*Label 475*/ 13407, // Rule ID 432 //
6188 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6189 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
6190 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6191 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6192 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6193 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6194 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6195 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6196 : // (intrinsic_wo_chain:{ *:[i32] } 2982:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6197 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
6198 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6199 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6200 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6201 : GIR_EraseFromParent, /*InsnID*/0,
6202 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6203 : // GIR_Coverage, 432,
6204 : GIR_Done,
6205 : // Label 475: @13407
6206 : GIM_Try, /*On fail goto*//*Label 476*/ 13459, // Rule ID 433 //
6207 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6208 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
6209 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6210 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6211 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6212 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6213 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6214 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6215 : // (intrinsic_wo_chain:{ *:[i32] } 3599:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6216 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
6217 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6218 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6219 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6220 : GIR_EraseFromParent, /*InsnID*/0,
6221 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6222 : // GIR_Coverage, 433,
6223 : GIR_Done,
6224 : // Label 476: @13459
6225 : GIM_Try, /*On fail goto*//*Label 477*/ 13511, // Rule ID 434 //
6226 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6227 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
6228 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6229 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6230 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6232 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6234 : // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6235 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
6236 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6237 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6239 : GIR_EraseFromParent, /*InsnID*/0,
6240 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6241 : // GIR_Coverage, 434,
6242 : GIR_Done,
6243 : // Label 477: @13511
6244 : GIM_Try, /*On fail goto*//*Label 478*/ 13563, // Rule ID 451 //
6245 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6246 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6247 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6248 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6249 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6250 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6251 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6252 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6253 : // (intrinsic_wo_chain:{ *:[v4i8] } 3527:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6254 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
6255 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6256 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6258 : GIR_EraseFromParent, /*InsnID*/0,
6259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6260 : // GIR_Coverage, 451,
6261 : GIR_Done,
6262 : // Label 478: @13563
6263 : GIM_Try, /*On fail goto*//*Label 479*/ 13615, // Rule ID 453 //
6264 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6265 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
6266 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6267 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6268 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6272 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6273 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
6274 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6275 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6276 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6277 : GIR_EraseFromParent, /*InsnID*/0,
6278 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6279 : // GIR_Coverage, 453,
6280 : GIR_Done,
6281 : // Label 479: @13615
6282 : GIM_Try, /*On fail goto*//*Label 480*/ 13667, // Rule ID 454 //
6283 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6284 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6285 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6286 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6287 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6288 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6289 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6290 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6291 : // (intrinsic_wo_chain:{ *:[v2i16] } 3531:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6292 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
6293 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6294 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6295 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6296 : GIR_EraseFromParent, /*InsnID*/0,
6297 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6298 : // GIR_Coverage, 454,
6299 : GIR_Done,
6300 : // Label 480: @13667
6301 : GIM_Try, /*On fail goto*//*Label 481*/ 13719, // Rule ID 459 //
6302 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6303 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b,
6304 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6306 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6307 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6308 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6310 : // (intrinsic_wo_chain:{ *:[v16i8] } 2973:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6311 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
6312 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6313 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6314 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6315 : GIR_EraseFromParent, /*InsnID*/0,
6316 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6317 : // GIR_Coverage, 459,
6318 : GIR_Done,
6319 : // Label 481: @13719
6320 : GIM_Try, /*On fail goto*//*Label 482*/ 13771, // Rule ID 460 //
6321 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6322 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h,
6323 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6324 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6325 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6326 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6327 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6328 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6329 : // (intrinsic_wo_chain:{ *:[v8i16] } 2975:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6330 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
6331 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6332 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6333 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6334 : GIR_EraseFromParent, /*InsnID*/0,
6335 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6336 : // GIR_Coverage, 460,
6337 : GIR_Done,
6338 : // Label 482: @13771
6339 : GIM_Try, /*On fail goto*//*Label 483*/ 13823, // Rule ID 461 //
6340 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6341 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w,
6342 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6343 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6344 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6345 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6346 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6347 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6348 : // (intrinsic_wo_chain:{ *:[v4i32] } 2976:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6349 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
6350 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6351 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6352 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6353 : GIR_EraseFromParent, /*InsnID*/0,
6354 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6355 : // GIR_Coverage, 461,
6356 : GIR_Done,
6357 : // Label 483: @13823
6358 : GIM_Try, /*On fail goto*//*Label 484*/ 13875, // Rule ID 462 //
6359 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6360 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d,
6361 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6362 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6363 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6364 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6365 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6366 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6367 : // (intrinsic_wo_chain:{ *:[v2i64] } 2974:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6368 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
6369 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6370 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6371 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6372 : GIR_EraseFromParent, /*InsnID*/0,
6373 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6374 : // GIR_Coverage, 462,
6375 : GIR_Done,
6376 : // Label 484: @13875
6377 : GIM_Try, /*On fail goto*//*Label 485*/ 13927, // Rule ID 463 //
6378 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6379 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b,
6380 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6381 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6382 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6383 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6384 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6385 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6386 : // (intrinsic_wo_chain:{ *:[v16i8] } 2984:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6387 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
6388 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6389 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6391 : GIR_EraseFromParent, /*InsnID*/0,
6392 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6393 : // GIR_Coverage, 463,
6394 : GIR_Done,
6395 : // Label 485: @13927
6396 : GIM_Try, /*On fail goto*//*Label 486*/ 13979, // Rule ID 464 //
6397 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6398 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h,
6399 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6400 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6401 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6403 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6404 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6405 : // (intrinsic_wo_chain:{ *:[v8i16] } 2986:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6406 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
6407 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6408 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6409 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6410 : GIR_EraseFromParent, /*InsnID*/0,
6411 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6412 : // GIR_Coverage, 464,
6413 : GIR_Done,
6414 : // Label 486: @13979
6415 : GIM_Try, /*On fail goto*//*Label 487*/ 14031, // Rule ID 465 //
6416 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6417 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w,
6418 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6419 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6420 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6422 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6423 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6424 : // (intrinsic_wo_chain:{ *:[v4i32] } 2987:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6425 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
6426 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6427 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6428 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6429 : GIR_EraseFromParent, /*InsnID*/0,
6430 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6431 : // GIR_Coverage, 465,
6432 : GIR_Done,
6433 : // Label 487: @14031
6434 : GIM_Try, /*On fail goto*//*Label 488*/ 14083, // Rule ID 466 //
6435 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6436 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d,
6437 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6438 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6439 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6440 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6441 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6443 : // (intrinsic_wo_chain:{ *:[v2i64] } 2985:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6444 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
6445 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6446 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6447 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6448 : GIR_EraseFromParent, /*InsnID*/0,
6449 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6450 : // GIR_Coverage, 466,
6451 : GIR_Done,
6452 : // Label 488: @14083
6453 : GIM_Try, /*On fail goto*//*Label 489*/ 14135, // Rule ID 467 //
6454 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6455 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b,
6456 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6457 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6458 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6459 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6460 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6461 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6462 : // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6463 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
6464 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6465 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6466 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6467 : GIR_EraseFromParent, /*InsnID*/0,
6468 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6469 : // GIR_Coverage, 467,
6470 : GIR_Done,
6471 : // Label 489: @14135
6472 : GIM_Try, /*On fail goto*//*Label 490*/ 14187, // Rule ID 468 //
6473 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6474 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h,
6475 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6476 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6477 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6478 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6479 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6480 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6481 : // (intrinsic_wo_chain:{ *:[v8i16] } 2990:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6482 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
6483 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6484 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6485 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6486 : GIR_EraseFromParent, /*InsnID*/0,
6487 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6488 : // GIR_Coverage, 468,
6489 : GIR_Done,
6490 : // Label 490: @14187
6491 : GIM_Try, /*On fail goto*//*Label 491*/ 14239, // Rule ID 469 //
6492 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6493 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w,
6494 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6495 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6496 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6497 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6498 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6500 : // (intrinsic_wo_chain:{ *:[v4i32] } 2991:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6501 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
6502 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6503 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6504 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6505 : GIR_EraseFromParent, /*InsnID*/0,
6506 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6507 : // GIR_Coverage, 469,
6508 : GIR_Done,
6509 : // Label 491: @14239
6510 : GIM_Try, /*On fail goto*//*Label 492*/ 14291, // Rule ID 470 //
6511 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6512 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d,
6513 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6514 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6515 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6516 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6517 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6518 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6519 : // (intrinsic_wo_chain:{ *:[v2i64] } 2989:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6520 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
6521 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6522 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6523 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6524 : GIR_EraseFromParent, /*InsnID*/0,
6525 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6526 : // GIR_Coverage, 470,
6527 : GIR_Done,
6528 : // Label 492: @14291
6529 : GIM_Try, /*On fail goto*//*Label 493*/ 14343, // Rule ID 471 //
6530 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6531 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b,
6532 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6533 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6534 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6536 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6538 : // (intrinsic_wo_chain:{ *:[v16i8] } 2992:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6539 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
6540 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6541 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6542 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6543 : GIR_EraseFromParent, /*InsnID*/0,
6544 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6545 : // GIR_Coverage, 471,
6546 : GIR_Done,
6547 : // Label 493: @14343
6548 : GIM_Try, /*On fail goto*//*Label 494*/ 14395, // Rule ID 472 //
6549 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6550 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h,
6551 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6552 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6553 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6555 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6556 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6557 : // (intrinsic_wo_chain:{ *:[v8i16] } 2994:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6558 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
6559 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6560 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6561 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6562 : GIR_EraseFromParent, /*InsnID*/0,
6563 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6564 : // GIR_Coverage, 472,
6565 : GIR_Done,
6566 : // Label 494: @14395
6567 : GIM_Try, /*On fail goto*//*Label 495*/ 14447, // Rule ID 473 //
6568 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6569 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w,
6570 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6571 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6572 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6573 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6574 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6575 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6576 : // (intrinsic_wo_chain:{ *:[v4i32] } 2995:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6577 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
6578 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6579 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6580 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6581 : GIR_EraseFromParent, /*InsnID*/0,
6582 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6583 : // GIR_Coverage, 473,
6584 : GIR_Done,
6585 : // Label 495: @14447
6586 : GIM_Try, /*On fail goto*//*Label 496*/ 14499, // Rule ID 474 //
6587 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6588 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d,
6589 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6590 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6591 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6593 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6594 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6595 : // (intrinsic_wo_chain:{ *:[v2i64] } 2993:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6596 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
6597 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6598 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6599 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6600 : GIR_EraseFromParent, /*InsnID*/0,
6601 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6602 : // GIR_Coverage, 474,
6603 : GIR_Done,
6604 : // Label 496: @14499
6605 : GIM_Try, /*On fail goto*//*Label 497*/ 14551, // Rule ID 488 //
6606 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6607 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b,
6608 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6609 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6610 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6611 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6612 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6613 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6614 : // (intrinsic_wo_chain:{ *:[v16i8] } 3015:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6615 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
6616 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6617 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6618 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6619 : GIR_EraseFromParent, /*InsnID*/0,
6620 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6621 : // GIR_Coverage, 488,
6622 : GIR_Done,
6623 : // Label 497: @14551
6624 : GIM_Try, /*On fail goto*//*Label 498*/ 14603, // Rule ID 489 //
6625 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6626 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h,
6627 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6628 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6629 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6630 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6631 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6632 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6633 : // (intrinsic_wo_chain:{ *:[v8i16] } 3017:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6634 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
6635 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6636 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6637 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6638 : GIR_EraseFromParent, /*InsnID*/0,
6639 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6640 : // GIR_Coverage, 489,
6641 : GIR_Done,
6642 : // Label 498: @14603
6643 : GIM_Try, /*On fail goto*//*Label 499*/ 14655, // Rule ID 490 //
6644 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6645 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w,
6646 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6647 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6648 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6649 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6650 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6651 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6652 : // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6653 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
6654 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6655 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6656 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6657 : GIR_EraseFromParent, /*InsnID*/0,
6658 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6659 : // GIR_Coverage, 490,
6660 : GIR_Done,
6661 : // Label 499: @14655
6662 : GIM_Try, /*On fail goto*//*Label 500*/ 14707, // Rule ID 491 //
6663 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6664 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d,
6665 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6666 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6667 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6668 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6669 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6670 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6671 : // (intrinsic_wo_chain:{ *:[v2i64] } 3016:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6672 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
6673 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6674 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6675 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6676 : GIR_EraseFromParent, /*InsnID*/0,
6677 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6678 : // GIR_Coverage, 491,
6679 : GIR_Done,
6680 : // Label 500: @14707
6681 : GIM_Try, /*On fail goto*//*Label 501*/ 14759, // Rule ID 492 //
6682 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6683 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b,
6684 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6685 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6686 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6690 : // (intrinsic_wo_chain:{ *:[v16i8] } 3019:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6691 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
6692 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6693 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6694 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6695 : GIR_EraseFromParent, /*InsnID*/0,
6696 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6697 : // GIR_Coverage, 492,
6698 : GIR_Done,
6699 : // Label 501: @14759
6700 : GIM_Try, /*On fail goto*//*Label 502*/ 14811, // Rule ID 493 //
6701 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6702 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h,
6703 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6704 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6705 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6706 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6707 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6708 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6709 : // (intrinsic_wo_chain:{ *:[v8i16] } 3021:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6710 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
6711 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6712 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6713 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6714 : GIR_EraseFromParent, /*InsnID*/0,
6715 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6716 : // GIR_Coverage, 493,
6717 : GIR_Done,
6718 : // Label 502: @14811
6719 : GIM_Try, /*On fail goto*//*Label 503*/ 14863, // Rule ID 494 //
6720 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6721 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w,
6722 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6723 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6724 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6726 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6727 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6728 : // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6729 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
6730 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6731 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6732 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6733 : GIR_EraseFromParent, /*InsnID*/0,
6734 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6735 : // GIR_Coverage, 494,
6736 : GIR_Done,
6737 : // Label 503: @14863
6738 : GIM_Try, /*On fail goto*//*Label 504*/ 14915, // Rule ID 495 //
6739 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6740 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d,
6741 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6742 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6743 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6747 : // (intrinsic_wo_chain:{ *:[v2i64] } 3020:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6748 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
6749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6751 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6752 : GIR_EraseFromParent, /*InsnID*/0,
6753 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6754 : // GIR_Coverage, 495,
6755 : GIR_Done,
6756 : // Label 504: @14915
6757 : GIM_Try, /*On fail goto*//*Label 505*/ 14967, // Rule ID 496 //
6758 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6759 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b,
6760 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6761 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6762 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6763 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6764 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6765 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6766 : // (intrinsic_wo_chain:{ *:[v16i8] } 3023:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6767 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
6768 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6770 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6771 : GIR_EraseFromParent, /*InsnID*/0,
6772 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6773 : // GIR_Coverage, 496,
6774 : GIR_Done,
6775 : // Label 505: @14967
6776 : GIM_Try, /*On fail goto*//*Label 506*/ 15019, // Rule ID 497 //
6777 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6778 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h,
6779 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6780 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6781 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6782 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6783 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6784 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6785 : // (intrinsic_wo_chain:{ *:[v8i16] } 3025:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6786 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
6787 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6788 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6789 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6790 : GIR_EraseFromParent, /*InsnID*/0,
6791 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6792 : // GIR_Coverage, 497,
6793 : GIR_Done,
6794 : // Label 506: @15019
6795 : GIM_Try, /*On fail goto*//*Label 507*/ 15071, // Rule ID 498 //
6796 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6797 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w,
6798 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6799 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6800 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6801 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6802 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6803 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6804 : // (intrinsic_wo_chain:{ *:[v4i32] } 3026:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6805 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
6806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6807 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6808 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6809 : GIR_EraseFromParent, /*InsnID*/0,
6810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6811 : // GIR_Coverage, 498,
6812 : GIR_Done,
6813 : // Label 507: @15071
6814 : GIM_Try, /*On fail goto*//*Label 508*/ 15123, // Rule ID 499 //
6815 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6816 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d,
6817 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6818 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6819 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6820 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6821 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6822 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6823 : // (intrinsic_wo_chain:{ *:[v2i64] } 3024:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6824 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
6825 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6826 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6827 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6828 : GIR_EraseFromParent, /*InsnID*/0,
6829 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6830 : // GIR_Coverage, 499,
6831 : GIR_Done,
6832 : // Label 508: @15123
6833 : GIM_Try, /*On fail goto*//*Label 509*/ 15175, // Rule ID 500 //
6834 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6835 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b,
6836 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6837 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6838 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6839 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6842 : // (intrinsic_wo_chain:{ *:[v16i8] } 3027:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6843 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
6844 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6845 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6846 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6847 : GIR_EraseFromParent, /*InsnID*/0,
6848 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6849 : // GIR_Coverage, 500,
6850 : GIR_Done,
6851 : // Label 509: @15175
6852 : GIM_Try, /*On fail goto*//*Label 510*/ 15227, // Rule ID 501 //
6853 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6854 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h,
6855 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6856 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6857 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6858 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6859 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6860 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6861 : // (intrinsic_wo_chain:{ *:[v8i16] } 3029:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6862 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
6863 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6864 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6865 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6866 : GIR_EraseFromParent, /*InsnID*/0,
6867 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6868 : // GIR_Coverage, 501,
6869 : GIR_Done,
6870 : // Label 510: @15227
6871 : GIM_Try, /*On fail goto*//*Label 511*/ 15279, // Rule ID 502 //
6872 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6873 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w,
6874 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6875 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6876 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6877 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6878 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6879 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6880 : // (intrinsic_wo_chain:{ *:[v4i32] } 3030:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6881 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
6882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6883 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6884 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6885 : GIR_EraseFromParent, /*InsnID*/0,
6886 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6887 : // GIR_Coverage, 502,
6888 : GIR_Done,
6889 : // Label 511: @15279
6890 : GIM_Try, /*On fail goto*//*Label 512*/ 15331, // Rule ID 503 //
6891 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6892 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d,
6893 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6894 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6895 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6896 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6899 : // (intrinsic_wo_chain:{ *:[v2i64] } 3028:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6900 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
6901 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6902 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6903 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6904 : GIR_EraseFromParent, /*InsnID*/0,
6905 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6906 : // GIR_Coverage, 503,
6907 : GIR_Done,
6908 : // Label 512: @15331
6909 : GIM_Try, /*On fail goto*//*Label 513*/ 15383, // Rule ID 504 //
6910 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6911 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b,
6912 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6913 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6914 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6915 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6916 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6917 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6918 : // (intrinsic_wo_chain:{ *:[v16i8] } 3031:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6919 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
6920 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6921 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6922 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6923 : GIR_EraseFromParent, /*InsnID*/0,
6924 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6925 : // GIR_Coverage, 504,
6926 : GIR_Done,
6927 : // Label 513: @15383
6928 : GIM_Try, /*On fail goto*//*Label 514*/ 15435, // Rule ID 505 //
6929 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6930 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h,
6931 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6932 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6933 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6934 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6935 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6936 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6937 : // (intrinsic_wo_chain:{ *:[v8i16] } 3033:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6938 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
6939 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6940 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6941 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6942 : GIR_EraseFromParent, /*InsnID*/0,
6943 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6944 : // GIR_Coverage, 505,
6945 : GIR_Done,
6946 : // Label 514: @15435
6947 : GIM_Try, /*On fail goto*//*Label 515*/ 15487, // Rule ID 506 //
6948 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6949 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w,
6950 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6951 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6952 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6953 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6954 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6955 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6956 : // (intrinsic_wo_chain:{ *:[v4i32] } 3034:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6957 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
6958 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6959 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6960 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6961 : GIR_EraseFromParent, /*InsnID*/0,
6962 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6963 : // GIR_Coverage, 506,
6964 : GIR_Done,
6965 : // Label 515: @15487
6966 : GIM_Try, /*On fail goto*//*Label 516*/ 15539, // Rule ID 507 //
6967 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6968 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d,
6969 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6970 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6971 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6972 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6973 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6974 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6975 : // (intrinsic_wo_chain:{ *:[v2i64] } 3032:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6976 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
6977 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6978 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6979 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6980 : GIR_EraseFromParent, /*InsnID*/0,
6981 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6982 : // GIR_Coverage, 507,
6983 : GIR_Done,
6984 : // Label 516: @15539
6985 : GIM_Try, /*On fail goto*//*Label 517*/ 15591, // Rule ID 508 //
6986 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6987 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b,
6988 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6989 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6990 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6991 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6992 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6994 : // (intrinsic_wo_chain:{ *:[v16i8] } 3035:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6995 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
6996 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6997 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6998 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6999 : GIR_EraseFromParent, /*InsnID*/0,
7000 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7001 : // GIR_Coverage, 508,
7002 : GIR_Done,
7003 : // Label 517: @15591
7004 : GIM_Try, /*On fail goto*//*Label 518*/ 15643, // Rule ID 509 //
7005 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7006 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h,
7007 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7008 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7009 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7011 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7012 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7013 : // (intrinsic_wo_chain:{ *:[v8i16] } 3037:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7014 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
7015 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7016 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7017 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7018 : GIR_EraseFromParent, /*InsnID*/0,
7019 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7020 : // GIR_Coverage, 509,
7021 : GIR_Done,
7022 : // Label 518: @15643
7023 : GIM_Try, /*On fail goto*//*Label 519*/ 15695, // Rule ID 510 //
7024 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7025 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w,
7026 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7027 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7028 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7029 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7030 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7031 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7032 : // (intrinsic_wo_chain:{ *:[v4i32] } 3038:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7033 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
7034 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7036 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7037 : GIR_EraseFromParent, /*InsnID*/0,
7038 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7039 : // GIR_Coverage, 510,
7040 : GIR_Done,
7041 : // Label 519: @15695
7042 : GIM_Try, /*On fail goto*//*Label 520*/ 15747, // Rule ID 511 //
7043 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7044 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d,
7045 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7046 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7047 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7048 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7049 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7050 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7051 : // (intrinsic_wo_chain:{ *:[v2i64] } 3036:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7052 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
7053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7054 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7055 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7056 : GIR_EraseFromParent, /*InsnID*/0,
7057 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7058 : // GIR_Coverage, 511,
7059 : GIR_Done,
7060 : // Label 520: @15747
7061 : GIM_Try, /*On fail goto*//*Label 521*/ 15799, // Rule ID 620 //
7062 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7063 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h,
7064 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7065 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7066 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7067 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7068 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7069 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7070 : // (intrinsic_wo_chain:{ *:[v8i16] } 3170:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7071 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
7072 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7073 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7074 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7075 : GIR_EraseFromParent, /*InsnID*/0,
7076 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7077 : // GIR_Coverage, 620,
7078 : GIR_Done,
7079 : // Label 521: @15799
7080 : GIM_Try, /*On fail goto*//*Label 522*/ 15851, // Rule ID 621 //
7081 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7082 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w,
7083 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7084 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7085 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7087 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7088 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7089 : // (intrinsic_wo_chain:{ *:[v4i32] } 3171:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7090 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
7091 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7092 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7093 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7094 : GIR_EraseFromParent, /*InsnID*/0,
7095 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7096 : // GIR_Coverage, 621,
7097 : GIR_Done,
7098 : // Label 522: @15851
7099 : GIM_Try, /*On fail goto*//*Label 523*/ 15903, // Rule ID 622 //
7100 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7101 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d,
7102 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7103 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7104 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7107 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7108 : // (intrinsic_wo_chain:{ *:[v2i64] } 3169:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7109 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
7110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7111 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7112 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7113 : GIR_EraseFromParent, /*InsnID*/0,
7114 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7115 : // GIR_Coverage, 622,
7116 : GIR_Done,
7117 : // Label 523: @15903
7118 : GIM_Try, /*On fail goto*//*Label 524*/ 15955, // Rule ID 623 //
7119 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7120 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h,
7121 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7122 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7123 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7124 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7125 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7126 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7127 : // (intrinsic_wo_chain:{ *:[v8i16] } 3173:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7128 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
7129 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7130 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7131 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7132 : GIR_EraseFromParent, /*InsnID*/0,
7133 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7134 : // GIR_Coverage, 623,
7135 : GIR_Done,
7136 : // Label 524: @15955
7137 : GIM_Try, /*On fail goto*//*Label 525*/ 16007, // Rule ID 624 //
7138 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7139 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w,
7140 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7141 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7142 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7143 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7144 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7146 : // (intrinsic_wo_chain:{ *:[v4i32] } 3174:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7147 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
7148 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7149 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7150 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7151 : GIR_EraseFromParent, /*InsnID*/0,
7152 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7153 : // GIR_Coverage, 624,
7154 : GIR_Done,
7155 : // Label 525: @16007
7156 : GIM_Try, /*On fail goto*//*Label 526*/ 16059, // Rule ID 625 //
7157 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7158 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d,
7159 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7160 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7161 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7163 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7165 : // (intrinsic_wo_chain:{ *:[v2i64] } 3172:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7166 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
7167 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7168 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7169 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7170 : GIR_EraseFromParent, /*InsnID*/0,
7171 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7172 : // GIR_Coverage, 625,
7173 : GIR_Done,
7174 : // Label 526: @16059
7175 : GIM_Try, /*On fail goto*//*Label 527*/ 16111, // Rule ID 640 //
7176 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7177 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w,
7178 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7179 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7180 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7181 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7182 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7183 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7184 : // (intrinsic_wo_chain:{ *:[v4i32] } 3212:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7185 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
7186 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7187 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7188 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7189 : GIR_EraseFromParent, /*InsnID*/0,
7190 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7191 : // GIR_Coverage, 640,
7192 : GIR_Done,
7193 : // Label 527: @16111
7194 : GIM_Try, /*On fail goto*//*Label 528*/ 16163, // Rule ID 641 //
7195 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7196 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d,
7197 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7198 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7199 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7200 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7201 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7202 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7203 : // (intrinsic_wo_chain:{ *:[v2i64] } 3211:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7204 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
7205 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7206 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7207 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7208 : GIR_EraseFromParent, /*InsnID*/0,
7209 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7210 : // GIR_Coverage, 641,
7211 : GIR_Done,
7212 : // Label 528: @16163
7213 : GIM_Try, /*On fail goto*//*Label 529*/ 16215, // Rule ID 666 //
7214 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7215 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h,
7216 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7217 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7218 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7219 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7220 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7221 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7222 : // (intrinsic_wo_chain:{ *:[v8f16] } 3237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7223 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
7224 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7225 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7226 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7227 : GIR_EraseFromParent, /*InsnID*/0,
7228 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7229 : // GIR_Coverage, 666,
7230 : GIR_Done,
7231 : // Label 529: @16215
7232 : GIM_Try, /*On fail goto*//*Label 530*/ 16267, // Rule ID 667 //
7233 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7234 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w,
7235 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7236 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7237 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7238 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7239 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7240 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7241 : // (intrinsic_wo_chain:{ *:[v4f32] } 3238:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7242 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
7243 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7244 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7245 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7246 : GIR_EraseFromParent, /*InsnID*/0,
7247 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7248 : // GIR_Coverage, 667,
7249 : GIR_Done,
7250 : // Label 530: @16267
7251 : GIM_Try, /*On fail goto*//*Label 531*/ 16319, // Rule ID 694 //
7252 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7253 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w,
7254 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7255 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7256 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7257 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7258 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7259 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7260 : // (intrinsic_wo_chain:{ *:[v4f32] } 3264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7261 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
7262 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7263 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7264 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7265 : GIR_EraseFromParent, /*InsnID*/0,
7266 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7267 : // GIR_Coverage, 694,
7268 : GIR_Done,
7269 : // Label 531: @16319
7270 : GIM_Try, /*On fail goto*//*Label 532*/ 16371, // Rule ID 695 //
7271 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7272 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d,
7273 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7274 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7275 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7277 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7278 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7279 : // (intrinsic_wo_chain:{ *:[v2f64] } 3263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7280 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
7281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7282 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7283 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7284 : GIR_EraseFromParent, /*InsnID*/0,
7285 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7286 : // GIR_Coverage, 695,
7287 : GIR_Done,
7288 : // Label 532: @16371
7289 : GIM_Try, /*On fail goto*//*Label 533*/ 16423, // Rule ID 696 //
7290 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7291 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w,
7292 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7293 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7294 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7296 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7297 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7298 : // (intrinsic_wo_chain:{ *:[v4f32] } 3262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7299 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
7300 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7301 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7302 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7303 : GIR_EraseFromParent, /*InsnID*/0,
7304 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7305 : // GIR_Coverage, 696,
7306 : GIR_Done,
7307 : // Label 533: @16423
7308 : GIM_Try, /*On fail goto*//*Label 534*/ 16475, // Rule ID 697 //
7309 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7310 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d,
7311 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7312 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7313 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7314 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7315 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7316 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7317 : // (intrinsic_wo_chain:{ *:[v2f64] } 3261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7318 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
7319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7321 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7322 : GIR_EraseFromParent, /*InsnID*/0,
7323 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7324 : // GIR_Coverage, 697,
7325 : GIR_Done,
7326 : // Label 534: @16475
7327 : GIM_Try, /*On fail goto*//*Label 535*/ 16527, // Rule ID 698 //
7328 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7329 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w,
7330 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7331 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7332 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7333 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7334 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7335 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7336 : // (intrinsic_wo_chain:{ *:[v4f32] } 3268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7337 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
7338 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7339 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7340 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7341 : GIR_EraseFromParent, /*InsnID*/0,
7342 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7343 : // GIR_Coverage, 698,
7344 : GIR_Done,
7345 : // Label 535: @16527
7346 : GIM_Try, /*On fail goto*//*Label 536*/ 16579, // Rule ID 699 //
7347 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7348 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d,
7349 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7350 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7351 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7352 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7353 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7354 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7355 : // (intrinsic_wo_chain:{ *:[v2f64] } 3267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
7357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7358 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7359 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7360 : GIR_EraseFromParent, /*InsnID*/0,
7361 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7362 : // GIR_Coverage, 699,
7363 : GIR_Done,
7364 : // Label 536: @16579
7365 : GIM_Try, /*On fail goto*//*Label 537*/ 16631, // Rule ID 700 //
7366 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7367 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w,
7368 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7369 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7370 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7371 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7372 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7373 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7374 : // (intrinsic_wo_chain:{ *:[v4f32] } 3266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7375 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
7376 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7377 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7378 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7379 : GIR_EraseFromParent, /*InsnID*/0,
7380 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7381 : // GIR_Coverage, 700,
7382 : GIR_Done,
7383 : // Label 537: @16631
7384 : GIM_Try, /*On fail goto*//*Label 538*/ 16683, // Rule ID 701 //
7385 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7386 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d,
7387 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7388 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7389 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7392 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7393 : // (intrinsic_wo_chain:{ *:[v2f64] } 3265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7394 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
7395 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7396 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7397 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7398 : GIR_EraseFromParent, /*InsnID*/0,
7399 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7400 : // GIR_Coverage, 701,
7401 : GIR_Done,
7402 : // Label 538: @16683
7403 : GIM_Try, /*On fail goto*//*Label 539*/ 16735, // Rule ID 712 //
7404 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7405 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w,
7406 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7407 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7408 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7410 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7411 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7412 : // (intrinsic_wo_chain:{ *:[v4i32] } 3280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7413 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
7414 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7415 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7416 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7417 : GIR_EraseFromParent, /*InsnID*/0,
7418 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7419 : // GIR_Coverage, 712,
7420 : GIR_Done,
7421 : // Label 539: @16735
7422 : GIM_Try, /*On fail goto*//*Label 540*/ 16787, // Rule ID 713 //
7423 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7424 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d,
7425 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7426 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7427 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7428 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7429 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7430 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7431 : // (intrinsic_wo_chain:{ *:[v2i64] } 3279:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7432 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
7433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7434 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7435 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7436 : GIR_EraseFromParent, /*InsnID*/0,
7437 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7438 : // GIR_Coverage, 713,
7439 : GIR_Done,
7440 : // Label 540: @16787
7441 : GIM_Try, /*On fail goto*//*Label 541*/ 16839, // Rule ID 714 //
7442 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7443 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w,
7444 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7445 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7446 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7447 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7448 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7449 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7450 : // (intrinsic_wo_chain:{ *:[v4i32] } 3282:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7451 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
7452 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7453 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7454 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7455 : GIR_EraseFromParent, /*InsnID*/0,
7456 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7457 : // GIR_Coverage, 714,
7458 : GIR_Done,
7459 : // Label 541: @16839
7460 : GIM_Try, /*On fail goto*//*Label 542*/ 16891, // Rule ID 715 //
7461 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7462 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d,
7463 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7464 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7465 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7466 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7467 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7468 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7469 : // (intrinsic_wo_chain:{ *:[v2i64] } 3281:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7470 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
7471 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7472 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7473 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7474 : GIR_EraseFromParent, /*InsnID*/0,
7475 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7476 : // GIR_Coverage, 715,
7477 : GIR_Done,
7478 : // Label 542: @16891
7479 : GIM_Try, /*On fail goto*//*Label 543*/ 16943, // Rule ID 716 //
7480 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7481 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w,
7482 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7483 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7484 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7487 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7488 : // (intrinsic_wo_chain:{ *:[v4i32] } 3284:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7489 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
7490 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7491 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7492 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7493 : GIR_EraseFromParent, /*InsnID*/0,
7494 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7495 : // GIR_Coverage, 716,
7496 : GIR_Done,
7497 : // Label 543: @16943
7498 : GIM_Try, /*On fail goto*//*Label 544*/ 16995, // Rule ID 717 //
7499 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7500 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d,
7501 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7502 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7503 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7504 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7505 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7506 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7507 : // (intrinsic_wo_chain:{ *:[v2i64] } 3283:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7508 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
7509 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7510 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7512 : GIR_EraseFromParent, /*InsnID*/0,
7513 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7514 : // GIR_Coverage, 717,
7515 : GIR_Done,
7516 : // Label 544: @16995
7517 : GIM_Try, /*On fail goto*//*Label 545*/ 17047, // Rule ID 718 //
7518 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7519 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w,
7520 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7521 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7522 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7523 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7526 : // (intrinsic_wo_chain:{ *:[v4i32] } 3286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7527 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
7528 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7530 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7531 : GIR_EraseFromParent, /*InsnID*/0,
7532 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7533 : // GIR_Coverage, 718,
7534 : GIR_Done,
7535 : // Label 545: @17047
7536 : GIM_Try, /*On fail goto*//*Label 546*/ 17099, // Rule ID 719 //
7537 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7538 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d,
7539 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7540 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7541 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7542 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7543 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7544 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7545 : // (intrinsic_wo_chain:{ *:[v2i64] } 3285:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7546 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
7547 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7548 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7549 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7550 : GIR_EraseFromParent, /*InsnID*/0,
7551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7552 : // GIR_Coverage, 719,
7553 : GIR_Done,
7554 : // Label 546: @17099
7555 : GIM_Try, /*On fail goto*//*Label 547*/ 17151, // Rule ID 720 //
7556 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7557 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w,
7558 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7559 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7560 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7561 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7562 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7563 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7564 : // (intrinsic_wo_chain:{ *:[v4i32] } 3288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7565 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
7566 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7567 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7568 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7569 : GIR_EraseFromParent, /*InsnID*/0,
7570 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7571 : // GIR_Coverage, 720,
7572 : GIR_Done,
7573 : // Label 547: @17151
7574 : GIM_Try, /*On fail goto*//*Label 548*/ 17203, // Rule ID 721 //
7575 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7576 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d,
7577 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7578 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7579 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7582 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7583 : // (intrinsic_wo_chain:{ *:[v2i64] } 3287:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7584 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
7585 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7586 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7587 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7588 : GIR_EraseFromParent, /*InsnID*/0,
7589 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7590 : // GIR_Coverage, 721,
7591 : GIR_Done,
7592 : // Label 548: @17203
7593 : GIM_Try, /*On fail goto*//*Label 549*/ 17255, // Rule ID 722 //
7594 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7595 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w,
7596 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7597 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7598 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7599 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7600 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7601 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7602 : // (intrinsic_wo_chain:{ *:[v4i32] } 3290:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7603 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
7604 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7605 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7606 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7607 : GIR_EraseFromParent, /*InsnID*/0,
7608 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7609 : // GIR_Coverage, 722,
7610 : GIR_Done,
7611 : // Label 549: @17255
7612 : GIM_Try, /*On fail goto*//*Label 550*/ 17307, // Rule ID 723 //
7613 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7614 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d,
7615 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7616 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7617 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7619 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7620 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7621 : // (intrinsic_wo_chain:{ *:[v2i64] } 3289:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7622 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
7623 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7624 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7626 : GIR_EraseFromParent, /*InsnID*/0,
7627 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7628 : // GIR_Coverage, 723,
7629 : GIR_Done,
7630 : // Label 550: @17307
7631 : GIM_Try, /*On fail goto*//*Label 551*/ 17359, // Rule ID 728 //
7632 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7633 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w,
7634 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7635 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7636 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7637 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7638 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7639 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7640 : // (intrinsic_wo_chain:{ *:[v4i32] } 3296:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7641 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
7642 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7643 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7644 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7645 : GIR_EraseFromParent, /*InsnID*/0,
7646 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7647 : // GIR_Coverage, 728,
7648 : GIR_Done,
7649 : // Label 551: @17359
7650 : GIM_Try, /*On fail goto*//*Label 552*/ 17411, // Rule ID 729 //
7651 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7652 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d,
7653 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7654 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7655 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7656 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7659 : // (intrinsic_wo_chain:{ *:[v2i64] } 3295:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7660 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
7661 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7662 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7663 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7664 : GIR_EraseFromParent, /*InsnID*/0,
7665 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7666 : // GIR_Coverage, 729,
7667 : GIR_Done,
7668 : // Label 552: @17411
7669 : GIM_Try, /*On fail goto*//*Label 553*/ 17463, // Rule ID 730 //
7670 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7671 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w,
7672 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7673 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7674 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7675 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7676 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7677 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7678 : // (intrinsic_wo_chain:{ *:[v4i32] } 3298:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7679 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
7680 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7681 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7682 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7683 : GIR_EraseFromParent, /*InsnID*/0,
7684 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7685 : // GIR_Coverage, 730,
7686 : GIR_Done,
7687 : // Label 553: @17463
7688 : GIM_Try, /*On fail goto*//*Label 554*/ 17515, // Rule ID 731 //
7689 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7690 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d,
7691 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7692 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7693 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7694 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7695 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7696 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7697 : // (intrinsic_wo_chain:{ *:[v2i64] } 3297:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7698 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
7699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7700 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7701 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7702 : GIR_EraseFromParent, /*InsnID*/0,
7703 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7704 : // GIR_Coverage, 731,
7705 : GIR_Done,
7706 : // Label 554: @17515
7707 : GIM_Try, /*On fail goto*//*Label 555*/ 17567, // Rule ID 732 //
7708 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7709 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w,
7710 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7711 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7712 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7713 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7715 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7716 : // (intrinsic_wo_chain:{ *:[v4i32] } 3300:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7717 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
7718 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7719 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7720 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7721 : GIR_EraseFromParent, /*InsnID*/0,
7722 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7723 : // GIR_Coverage, 732,
7724 : GIR_Done,
7725 : // Label 555: @17567
7726 : GIM_Try, /*On fail goto*//*Label 556*/ 17619, // Rule ID 733 //
7727 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7728 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d,
7729 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7730 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7731 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7732 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7733 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7734 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7735 : // (intrinsic_wo_chain:{ *:[v2i64] } 3299:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7736 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
7737 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7738 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7739 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7740 : GIR_EraseFromParent, /*InsnID*/0,
7741 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7742 : // GIR_Coverage, 733,
7743 : GIR_Done,
7744 : // Label 556: @17619
7745 : GIM_Try, /*On fail goto*//*Label 557*/ 17671, // Rule ID 734 //
7746 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7747 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w,
7748 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7749 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7750 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7751 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7752 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7753 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7754 : // (intrinsic_wo_chain:{ *:[v4i32] } 3302:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7755 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
7756 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7759 : GIR_EraseFromParent, /*InsnID*/0,
7760 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7761 : // GIR_Coverage, 734,
7762 : GIR_Done,
7763 : // Label 557: @17671
7764 : GIM_Try, /*On fail goto*//*Label 558*/ 17723, // Rule ID 735 //
7765 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7766 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d,
7767 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7768 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7769 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7770 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7772 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7773 : // (intrinsic_wo_chain:{ *:[v2i64] } 3301:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7774 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
7775 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7776 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7777 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7778 : GIR_EraseFromParent, /*InsnID*/0,
7779 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7780 : // GIR_Coverage, 735,
7781 : GIR_Done,
7782 : // Label 558: @17723
7783 : GIM_Try, /*On fail goto*//*Label 559*/ 17775, // Rule ID 736 //
7784 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7785 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w,
7786 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7787 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7788 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7789 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7790 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7791 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7792 : // (intrinsic_wo_chain:{ *:[v4i32] } 3304:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7793 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
7794 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7795 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7796 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7797 : GIR_EraseFromParent, /*InsnID*/0,
7798 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7799 : // GIR_Coverage, 736,
7800 : GIR_Done,
7801 : // Label 559: @17775
7802 : GIM_Try, /*On fail goto*//*Label 560*/ 17827, // Rule ID 737 //
7803 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7804 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d,
7805 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7806 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7807 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7808 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7809 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7810 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7811 : // (intrinsic_wo_chain:{ *:[v2i64] } 3303:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7812 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
7813 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7814 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7815 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7816 : GIR_EraseFromParent, /*InsnID*/0,
7817 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7818 : // GIR_Coverage, 737,
7819 : GIR_Done,
7820 : // Label 560: @17827
7821 : GIM_Try, /*On fail goto*//*Label 561*/ 17879, // Rule ID 742 //
7822 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7823 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h,
7824 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7825 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7826 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7828 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7829 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7830 : // (intrinsic_wo_chain:{ *:[v8i16] } 3309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7831 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
7832 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7833 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7834 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7835 : GIR_EraseFromParent, /*InsnID*/0,
7836 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7837 : // GIR_Coverage, 742,
7838 : GIR_Done,
7839 : // Label 561: @17879
7840 : GIM_Try, /*On fail goto*//*Label 562*/ 17931, // Rule ID 743 //
7841 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7842 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w,
7843 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7844 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7845 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7846 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7847 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7848 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7849 : // (intrinsic_wo_chain:{ *:[v4i32] } 3310:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7850 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
7851 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7852 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7853 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7854 : GIR_EraseFromParent, /*InsnID*/0,
7855 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7856 : // GIR_Coverage, 743,
7857 : GIR_Done,
7858 : // Label 562: @17931
7859 : GIM_Try, /*On fail goto*//*Label 563*/ 17983, // Rule ID 748 //
7860 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7861 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h,
7862 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7863 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7864 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7865 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7866 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7867 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7868 : // (intrinsic_wo_chain:{ *:[v8i16] } 3316:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7869 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
7870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7871 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7872 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7873 : GIR_EraseFromParent, /*InsnID*/0,
7874 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7875 : // GIR_Coverage, 748,
7876 : GIR_Done,
7877 : // Label 563: @17983
7878 : GIM_Try, /*On fail goto*//*Label 564*/ 18035, // Rule ID 749 //
7879 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7880 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w,
7881 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7882 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7883 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7884 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7885 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7886 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7887 : // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7888 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
7889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7890 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7891 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7892 : GIR_EraseFromParent, /*InsnID*/0,
7893 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7894 : // GIR_Coverage, 749,
7895 : GIR_Done,
7896 : // Label 564: @18035
7897 : GIM_Try, /*On fail goto*//*Label 565*/ 18087, // Rule ID 750 //
7898 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7899 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d,
7900 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7901 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7902 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7903 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7904 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7905 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7906 : // (intrinsic_wo_chain:{ *:[v2i64] } 3315:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7907 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
7908 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7909 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7910 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7911 : GIR_EraseFromParent, /*InsnID*/0,
7912 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7913 : // GIR_Coverage, 750,
7914 : GIR_Done,
7915 : // Label 565: @18087
7916 : GIM_Try, /*On fail goto*//*Label 566*/ 18139, // Rule ID 751 //
7917 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7918 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h,
7919 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7920 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7921 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7922 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7923 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7924 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7925 : // (intrinsic_wo_chain:{ *:[v8i16] } 3319:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7926 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
7927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7928 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7929 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7930 : GIR_EraseFromParent, /*InsnID*/0,
7931 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7932 : // GIR_Coverage, 751,
7933 : GIR_Done,
7934 : // Label 566: @18139
7935 : GIM_Try, /*On fail goto*//*Label 567*/ 18191, // Rule ID 752 //
7936 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7937 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w,
7938 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7939 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7940 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7941 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7942 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7943 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7944 : // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7945 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
7946 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7947 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7948 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7949 : GIR_EraseFromParent, /*InsnID*/0,
7950 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7951 : // GIR_Coverage, 752,
7952 : GIR_Done,
7953 : // Label 567: @18191
7954 : GIM_Try, /*On fail goto*//*Label 568*/ 18243, // Rule ID 753 //
7955 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7956 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d,
7957 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7958 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7959 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7963 : // (intrinsic_wo_chain:{ *:[v2i64] } 3318:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7964 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
7965 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7966 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7967 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7968 : GIR_EraseFromParent, /*InsnID*/0,
7969 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7970 : // GIR_Coverage, 753,
7971 : GIR_Done,
7972 : // Label 568: @18243
7973 : GIM_Try, /*On fail goto*//*Label 569*/ 18295, // Rule ID 754 //
7974 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7975 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h,
7976 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7977 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7978 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7979 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7980 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7981 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7982 : // (intrinsic_wo_chain:{ *:[v8i16] } 3322:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7983 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
7984 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7985 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7986 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7987 : GIR_EraseFromParent, /*InsnID*/0,
7988 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7989 : // GIR_Coverage, 754,
7990 : GIR_Done,
7991 : // Label 569: @18295
7992 : GIM_Try, /*On fail goto*//*Label 570*/ 18347, // Rule ID 755 //
7993 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7994 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w,
7995 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7996 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7997 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7998 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7999 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8000 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8001 : // (intrinsic_wo_chain:{ *:[v4i32] } 3323:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8002 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
8003 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8004 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8005 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8006 : GIR_EraseFromParent, /*InsnID*/0,
8007 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8008 : // GIR_Coverage, 755,
8009 : GIR_Done,
8010 : // Label 570: @18347
8011 : GIM_Try, /*On fail goto*//*Label 571*/ 18399, // Rule ID 756 //
8012 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8013 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d,
8014 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8015 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8016 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8017 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8018 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8019 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8020 : // (intrinsic_wo_chain:{ *:[v2i64] } 3321:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8021 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
8022 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8023 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8024 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8025 : GIR_EraseFromParent, /*InsnID*/0,
8026 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8027 : // GIR_Coverage, 756,
8028 : GIR_Done,
8029 : // Label 571: @18399
8030 : GIM_Try, /*On fail goto*//*Label 572*/ 18451, // Rule ID 757 //
8031 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8032 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h,
8033 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8034 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8035 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8036 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8037 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8038 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8039 : // (intrinsic_wo_chain:{ *:[v8i16] } 3325:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8040 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
8041 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8042 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8043 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8044 : GIR_EraseFromParent, /*InsnID*/0,
8045 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8046 : // GIR_Coverage, 757,
8047 : GIR_Done,
8048 : // Label 572: @18451
8049 : GIM_Try, /*On fail goto*//*Label 573*/ 18503, // Rule ID 758 //
8050 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8051 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w,
8052 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8053 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8054 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8055 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8056 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8058 : // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8059 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
8060 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8063 : GIR_EraseFromParent, /*InsnID*/0,
8064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8065 : // GIR_Coverage, 758,
8066 : GIR_Done,
8067 : // Label 573: @18503
8068 : GIM_Try, /*On fail goto*//*Label 574*/ 18555, // Rule ID 759 //
8069 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8070 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d,
8071 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8072 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8073 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8075 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8076 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8077 : // (intrinsic_wo_chain:{ *:[v2i64] } 3324:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8078 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
8079 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8080 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8081 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8082 : GIR_EraseFromParent, /*InsnID*/0,
8083 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8084 : // GIR_Coverage, 759,
8085 : GIR_Done,
8086 : // Label 574: @18555
8087 : GIM_Try, /*On fail goto*//*Label 575*/ 18607, // Rule ID 812 //
8088 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8089 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b,
8090 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8091 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8092 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8093 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8094 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8095 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8096 : // (intrinsic_wo_chain:{ *:[v16i8] } 3378:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8097 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
8098 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8099 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8100 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8101 : GIR_EraseFromParent, /*InsnID*/0,
8102 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8103 : // GIR_Coverage, 812,
8104 : GIR_Done,
8105 : // Label 575: @18607
8106 : GIM_Try, /*On fail goto*//*Label 576*/ 18659, // Rule ID 813 //
8107 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8108 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h,
8109 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8110 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8111 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8112 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8113 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8114 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8115 : // (intrinsic_wo_chain:{ *:[v8i16] } 3380:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8116 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
8117 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8120 : GIR_EraseFromParent, /*InsnID*/0,
8121 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8122 : // GIR_Coverage, 813,
8123 : GIR_Done,
8124 : // Label 576: @18659
8125 : GIM_Try, /*On fail goto*//*Label 577*/ 18711, // Rule ID 814 //
8126 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8127 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w,
8128 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8129 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8130 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8131 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8132 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8133 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8134 : // (intrinsic_wo_chain:{ *:[v4i32] } 3381:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8135 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
8136 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8137 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8138 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8139 : GIR_EraseFromParent, /*InsnID*/0,
8140 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8141 : // GIR_Coverage, 814,
8142 : GIR_Done,
8143 : // Label 577: @18711
8144 : GIM_Try, /*On fail goto*//*Label 578*/ 18763, // Rule ID 815 //
8145 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8146 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d,
8147 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8148 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8149 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8150 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8151 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8152 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8153 : // (intrinsic_wo_chain:{ *:[v2i64] } 3379:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8154 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
8155 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8156 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8158 : GIR_EraseFromParent, /*InsnID*/0,
8159 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8160 : // GIR_Coverage, 815,
8161 : GIR_Done,
8162 : // Label 578: @18763
8163 : GIM_Try, /*On fail goto*//*Label 579*/ 18815, // Rule ID 832 //
8164 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8165 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b,
8166 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8167 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8168 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8169 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8170 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8171 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8172 : // (intrinsic_wo_chain:{ *:[v16i8] } 3398:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8173 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
8174 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8175 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8176 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8177 : GIR_EraseFromParent, /*InsnID*/0,
8178 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8179 : // GIR_Coverage, 832,
8180 : GIR_Done,
8181 : // Label 579: @18815
8182 : GIM_Try, /*On fail goto*//*Label 580*/ 18867, // Rule ID 833 //
8183 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8184 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h,
8185 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8186 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8187 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8188 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8189 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8190 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8191 : // (intrinsic_wo_chain:{ *:[v8i16] } 3400:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8192 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
8193 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8194 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8195 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8196 : GIR_EraseFromParent, /*InsnID*/0,
8197 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8198 : // GIR_Coverage, 833,
8199 : GIR_Done,
8200 : // Label 580: @18867
8201 : GIM_Try, /*On fail goto*//*Label 581*/ 18919, // Rule ID 834 //
8202 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8203 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w,
8204 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8205 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8206 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8207 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8208 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8209 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8210 : // (intrinsic_wo_chain:{ *:[v4i32] } 3401:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8211 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
8212 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8213 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8214 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8215 : GIR_EraseFromParent, /*InsnID*/0,
8216 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8217 : // GIR_Coverage, 834,
8218 : GIR_Done,
8219 : // Label 581: @18919
8220 : GIM_Try, /*On fail goto*//*Label 582*/ 18971, // Rule ID 835 //
8221 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8222 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d,
8223 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8224 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8225 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8226 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8227 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8228 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8229 : // (intrinsic_wo_chain:{ *:[v2i64] } 3399:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8230 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
8231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8233 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8234 : GIR_EraseFromParent, /*InsnID*/0,
8235 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8236 : // GIR_Coverage, 835,
8237 : GIR_Done,
8238 : // Label 582: @18971
8239 : GIM_Try, /*On fail goto*//*Label 583*/ 19023, // Rule ID 868 //
8240 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8241 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h,
8242 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8243 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8244 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8245 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8246 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8248 : // (intrinsic_wo_chain:{ *:[v8i16] } 3440:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8249 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
8250 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8251 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8252 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8253 : GIR_EraseFromParent, /*InsnID*/0,
8254 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8255 : // GIR_Coverage, 868,
8256 : GIR_Done,
8257 : // Label 583: @19023
8258 : GIM_Try, /*On fail goto*//*Label 584*/ 19075, // Rule ID 869 //
8259 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8260 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w,
8261 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8262 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8263 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8264 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8265 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8266 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8267 : // (intrinsic_wo_chain:{ *:[v4i32] } 3441:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8268 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
8269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8270 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8271 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8272 : GIR_EraseFromParent, /*InsnID*/0,
8273 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8274 : // GIR_Coverage, 869,
8275 : GIR_Done,
8276 : // Label 584: @19075
8277 : GIM_Try, /*On fail goto*//*Label 585*/ 19127, // Rule ID 870 //
8278 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8279 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h,
8280 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8281 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8282 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8283 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8284 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8286 : // (intrinsic_wo_chain:{ *:[v8i16] } 3451:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8287 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
8288 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8289 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8290 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8291 : GIR_EraseFromParent, /*InsnID*/0,
8292 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8293 : // GIR_Coverage, 870,
8294 : GIR_Done,
8295 : // Label 585: @19127
8296 : GIM_Try, /*On fail goto*//*Label 586*/ 19179, // Rule ID 871 //
8297 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8298 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w,
8299 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8300 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8301 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8302 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8303 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8304 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8305 : // (intrinsic_wo_chain:{ *:[v4i32] } 3452:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8306 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
8307 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8308 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8309 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8310 : GIR_EraseFromParent, /*InsnID*/0,
8311 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8312 : // GIR_Coverage, 871,
8313 : GIR_Done,
8314 : // Label 586: @19179
8315 : GIM_Try, /*On fail goto*//*Label 587*/ 19231, // Rule ID 949 //
8316 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8317 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b,
8318 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8319 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8320 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8321 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8322 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8323 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8324 : // (intrinsic_wo_chain:{ *:[v16i8] } 3565:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8325 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
8326 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8327 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8328 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8329 : GIR_EraseFromParent, /*InsnID*/0,
8330 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8331 : // GIR_Coverage, 949,
8332 : GIR_Done,
8333 : // Label 587: @19231
8334 : GIM_Try, /*On fail goto*//*Label 588*/ 19283, // Rule ID 950 //
8335 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8336 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h,
8337 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8338 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8339 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8340 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8341 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8342 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8343 : // (intrinsic_wo_chain:{ *:[v8i16] } 3567:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8344 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
8345 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8346 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8347 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8348 : GIR_EraseFromParent, /*InsnID*/0,
8349 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8350 : // GIR_Coverage, 950,
8351 : GIR_Done,
8352 : // Label 588: @19283
8353 : GIM_Try, /*On fail goto*//*Label 589*/ 19335, // Rule ID 951 //
8354 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8355 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w,
8356 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8357 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8358 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8360 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8361 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8362 : // (intrinsic_wo_chain:{ *:[v4i32] } 3568:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8363 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
8364 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8365 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8366 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8367 : GIR_EraseFromParent, /*InsnID*/0,
8368 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8369 : // GIR_Coverage, 951,
8370 : GIR_Done,
8371 : // Label 589: @19335
8372 : GIM_Try, /*On fail goto*//*Label 590*/ 19387, // Rule ID 952 //
8373 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8374 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d,
8375 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8376 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8377 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8378 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8380 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8381 : // (intrinsic_wo_chain:{ *:[v2i64] } 3566:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8382 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
8383 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8384 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8385 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8386 : GIR_EraseFromParent, /*InsnID*/0,
8387 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8388 : // GIR_Coverage, 952,
8389 : GIR_Done,
8390 : // Label 590: @19387
8391 : GIM_Try, /*On fail goto*//*Label 591*/ 19439, // Rule ID 965 //
8392 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8393 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b,
8394 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8395 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8396 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8397 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8398 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8399 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8400 : // (intrinsic_wo_chain:{ *:[v16i8] } 3581:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8401 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
8402 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8403 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8404 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8405 : GIR_EraseFromParent, /*InsnID*/0,
8406 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8407 : // GIR_Coverage, 965,
8408 : GIR_Done,
8409 : // Label 591: @19439
8410 : GIM_Try, /*On fail goto*//*Label 592*/ 19491, // Rule ID 966 //
8411 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8412 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h,
8413 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8414 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8415 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8416 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8417 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8418 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8419 : // (intrinsic_wo_chain:{ *:[v8i16] } 3583:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8420 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
8421 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8422 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8423 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8424 : GIR_EraseFromParent, /*InsnID*/0,
8425 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8426 : // GIR_Coverage, 966,
8427 : GIR_Done,
8428 : // Label 592: @19491
8429 : GIM_Try, /*On fail goto*//*Label 593*/ 19543, // Rule ID 967 //
8430 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8431 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w,
8432 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8433 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8434 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8435 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8436 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8437 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8438 : // (intrinsic_wo_chain:{ *:[v4i32] } 3584:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8439 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
8440 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8441 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8442 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8443 : GIR_EraseFromParent, /*InsnID*/0,
8444 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8445 : // GIR_Coverage, 967,
8446 : GIR_Done,
8447 : // Label 593: @19543
8448 : GIM_Try, /*On fail goto*//*Label 594*/ 19595, // Rule ID 968 //
8449 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8450 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d,
8451 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8452 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8453 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8454 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8455 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8457 : // (intrinsic_wo_chain:{ *:[v2i64] } 3582:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8458 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
8459 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8460 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8461 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8462 : GIR_EraseFromParent, /*InsnID*/0,
8463 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8464 : // GIR_Coverage, 968,
8465 : GIR_Done,
8466 : // Label 594: @19595
8467 : GIM_Try, /*On fail goto*//*Label 595*/ 19647, // Rule ID 977 //
8468 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8469 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b,
8470 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8471 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8472 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8473 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8474 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8475 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8476 : // (intrinsic_wo_chain:{ *:[v16i8] } 3600:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8477 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
8478 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8479 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8480 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8481 : GIR_EraseFromParent, /*InsnID*/0,
8482 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8483 : // GIR_Coverage, 977,
8484 : GIR_Done,
8485 : // Label 595: @19647
8486 : GIM_Try, /*On fail goto*//*Label 596*/ 19699, // Rule ID 978 //
8487 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8488 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h,
8489 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8490 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8491 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8492 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8493 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8494 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8495 : // (intrinsic_wo_chain:{ *:[v8i16] } 3602:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8496 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
8497 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8498 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8499 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8500 : GIR_EraseFromParent, /*InsnID*/0,
8501 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8502 : // GIR_Coverage, 978,
8503 : GIR_Done,
8504 : // Label 596: @19699
8505 : GIM_Try, /*On fail goto*//*Label 597*/ 19751, // Rule ID 979 //
8506 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8507 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w,
8508 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8509 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8510 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8511 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8512 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8514 : // (intrinsic_wo_chain:{ *:[v4i32] } 3603:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8515 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
8516 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8517 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8519 : GIR_EraseFromParent, /*InsnID*/0,
8520 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8521 : // GIR_Coverage, 979,
8522 : GIR_Done,
8523 : // Label 597: @19751
8524 : GIM_Try, /*On fail goto*//*Label 598*/ 19803, // Rule ID 980 //
8525 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8526 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d,
8527 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8528 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8529 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8530 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8531 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8532 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8533 : // (intrinsic_wo_chain:{ *:[v2i64] } 3601:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8534 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
8535 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8536 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8537 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8538 : GIR_EraseFromParent, /*InsnID*/0,
8539 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8540 : // GIR_Coverage, 980,
8541 : GIR_Done,
8542 : // Label 598: @19803
8543 : GIM_Try, /*On fail goto*//*Label 599*/ 19855, // Rule ID 981 //
8544 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8545 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b,
8546 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8547 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8548 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8549 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8550 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8551 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8552 : // (intrinsic_wo_chain:{ *:[v16i8] } 3604:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8553 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
8554 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8555 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8556 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8557 : GIR_EraseFromParent, /*InsnID*/0,
8558 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8559 : // GIR_Coverage, 981,
8560 : GIR_Done,
8561 : // Label 599: @19855
8562 : GIM_Try, /*On fail goto*//*Label 600*/ 19907, // Rule ID 982 //
8563 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8564 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h,
8565 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8566 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8567 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8568 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8569 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8570 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8571 : // (intrinsic_wo_chain:{ *:[v8i16] } 3606:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8572 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
8573 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8574 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8575 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8576 : GIR_EraseFromParent, /*InsnID*/0,
8577 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8578 : // GIR_Coverage, 982,
8579 : GIR_Done,
8580 : // Label 600: @19907
8581 : GIM_Try, /*On fail goto*//*Label 601*/ 19959, // Rule ID 983 //
8582 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8583 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w,
8584 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8585 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8586 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8587 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8588 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8589 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8590 : // (intrinsic_wo_chain:{ *:[v4i32] } 3607:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8591 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
8592 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8593 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8594 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8595 : GIR_EraseFromParent, /*InsnID*/0,
8596 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8597 : // GIR_Coverage, 983,
8598 : GIR_Done,
8599 : // Label 601: @19959
8600 : GIM_Try, /*On fail goto*//*Label 602*/ 20011, // Rule ID 984 //
8601 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8602 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d,
8603 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8605 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8608 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8609 : // (intrinsic_wo_chain:{ *:[v2i64] } 3605:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8610 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
8611 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8612 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8613 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8614 : GIR_EraseFromParent, /*InsnID*/0,
8615 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8616 : // GIR_Coverage, 984,
8617 : GIR_Done,
8618 : // Label 602: @20011
8619 : GIM_Try, /*On fail goto*//*Label 603*/ 20063, // Rule ID 985 //
8620 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8621 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b,
8622 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8623 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8624 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8625 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8627 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8628 : // (intrinsic_wo_chain:{ *:[v16i8] } 3608:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8629 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
8630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8632 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8633 : GIR_EraseFromParent, /*InsnID*/0,
8634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8635 : // GIR_Coverage, 985,
8636 : GIR_Done,
8637 : // Label 603: @20063
8638 : GIM_Try, /*On fail goto*//*Label 604*/ 20115, // Rule ID 986 //
8639 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8640 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h,
8641 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8642 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8643 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8644 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8645 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8646 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8647 : // (intrinsic_wo_chain:{ *:[v8i16] } 3610:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8648 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
8649 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8650 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8651 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8652 : GIR_EraseFromParent, /*InsnID*/0,
8653 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8654 : // GIR_Coverage, 986,
8655 : GIR_Done,
8656 : // Label 604: @20115
8657 : GIM_Try, /*On fail goto*//*Label 605*/ 20167, // Rule ID 987 //
8658 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8659 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w,
8660 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8661 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8662 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8663 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8664 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8665 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8666 : // (intrinsic_wo_chain:{ *:[v4i32] } 3611:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8667 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
8668 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8669 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8670 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8671 : GIR_EraseFromParent, /*InsnID*/0,
8672 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8673 : // GIR_Coverage, 987,
8674 : GIR_Done,
8675 : // Label 605: @20167
8676 : GIM_Try, /*On fail goto*//*Label 606*/ 20219, // Rule ID 988 //
8677 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8678 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d,
8679 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8680 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8681 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8682 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8683 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8684 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8685 : // (intrinsic_wo_chain:{ *:[v2i64] } 3609:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8686 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
8687 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8688 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8689 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8690 : GIR_EraseFromParent, /*InsnID*/0,
8691 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8692 : // GIR_Coverage, 988,
8693 : GIR_Done,
8694 : // Label 606: @20219
8695 : GIM_Try, /*On fail goto*//*Label 607*/ 20271, // Rule ID 989 //
8696 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8697 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b,
8698 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8699 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8700 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8704 : // (intrinsic_wo_chain:{ *:[v16i8] } 3612:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8705 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
8706 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8707 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8708 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8709 : GIR_EraseFromParent, /*InsnID*/0,
8710 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8711 : // GIR_Coverage, 989,
8712 : GIR_Done,
8713 : // Label 607: @20271
8714 : GIM_Try, /*On fail goto*//*Label 608*/ 20323, // Rule ID 990 //
8715 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8716 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h,
8717 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8718 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8719 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8720 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8722 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8723 : // (intrinsic_wo_chain:{ *:[v8i16] } 3614:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
8725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8727 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8728 : GIR_EraseFromParent, /*InsnID*/0,
8729 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8730 : // GIR_Coverage, 990,
8731 : GIR_Done,
8732 : // Label 608: @20323
8733 : GIM_Try, /*On fail goto*//*Label 609*/ 20375, // Rule ID 991 //
8734 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8735 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w,
8736 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8737 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8738 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8739 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8740 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8741 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8742 : // (intrinsic_wo_chain:{ *:[v4i32] } 3615:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8743 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
8744 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8745 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8746 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8747 : GIR_EraseFromParent, /*InsnID*/0,
8748 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8749 : // GIR_Coverage, 991,
8750 : GIR_Done,
8751 : // Label 609: @20375
8752 : GIM_Try, /*On fail goto*//*Label 610*/ 20427, // Rule ID 992 //
8753 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8754 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d,
8755 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8756 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8757 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8758 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8759 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8761 : // (intrinsic_wo_chain:{ *:[v2i64] } 3613:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8762 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
8763 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8764 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8765 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8766 : GIR_EraseFromParent, /*InsnID*/0,
8767 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8768 : // GIR_Coverage, 992,
8769 : GIR_Done,
8770 : // Label 610: @20427
8771 : GIM_Try, /*On fail goto*//*Label 611*/ 20479, // Rule ID 1189 //
8772 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8773 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
8774 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8775 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8776 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8777 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8778 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8779 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8780 : // (intrinsic_wo_chain:{ *:[v2i16] } 2978:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8781 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
8782 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8783 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8784 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8785 : GIR_EraseFromParent, /*InsnID*/0,
8786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8787 : // GIR_Coverage, 1189,
8788 : GIR_Done,
8789 : // Label 611: @20479
8790 : GIM_Try, /*On fail goto*//*Label 612*/ 20531, // Rule ID 1191 //
8791 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8792 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
8793 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8794 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8795 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
8796 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8797 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8798 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8799 : // (intrinsic_wo_chain:{ *:[v4i8] } 3000:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8800 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
8801 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8802 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8803 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8804 : GIR_EraseFromParent, /*InsnID*/0,
8805 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8806 : // GIR_Coverage, 1191,
8807 : GIR_Done,
8808 : // Label 612: @20531
8809 : GIM_Try, /*On fail goto*//*Label 613*/ 20583, // Rule ID 1212 //
8810 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8811 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
8812 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8813 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8814 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8818 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8819 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
8820 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8821 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8822 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8823 : GIR_EraseFromParent, /*InsnID*/0,
8824 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8825 : // GIR_Coverage, 1212,
8826 : GIR_Done,
8827 : // Label 613: @20583
8828 : GIM_Try, /*On fail goto*//*Label 614*/ 20635, // Rule ID 1213 //
8829 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8830 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
8831 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8832 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8833 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8835 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8836 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8837 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8838 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
8839 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8840 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8841 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8842 : GIR_EraseFromParent, /*InsnID*/0,
8843 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8844 : // GIR_Coverage, 1213,
8845 : GIR_Done,
8846 : // Label 614: @20635
8847 : GIM_Try, /*On fail goto*//*Label 615*/ 20687, // Rule ID 1214 //
8848 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8849 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
8850 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8851 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8852 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
8854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8855 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8856 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8857 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
8858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8859 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8860 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8861 : GIR_EraseFromParent, /*InsnID*/0,
8862 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8863 : // GIR_Coverage, 1214,
8864 : GIR_Done,
8865 : // Label 615: @20687
8866 : GIM_Try, /*On fail goto*//*Label 616*/ 20739, // Rule ID 1216 //
8867 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8868 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
8869 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8870 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8871 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8873 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8874 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8875 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8876 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
8877 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8878 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8880 : GIR_EraseFromParent, /*InsnID*/0,
8881 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8882 : // GIR_Coverage, 1216,
8883 : GIR_Done,
8884 : // Label 616: @20739
8885 : GIM_Try, /*On fail goto*//*Label 617*/ 20791, // Rule ID 1227 //
8886 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8887 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
8888 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8889 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8890 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8892 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8893 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8894 : // (intrinsic_wo_chain:{ *:[v2i16] } 3594:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8895 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
8896 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8897 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8898 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8899 : GIR_EraseFromParent, /*InsnID*/0,
8900 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8901 : // GIR_Coverage, 1227,
8902 : GIR_Done,
8903 : // Label 617: @20791
8904 : GIM_Try, /*On fail goto*//*Label 618*/ 20843, // Rule ID 1229 //
8905 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8906 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
8907 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8908 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8909 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
8910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8911 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8912 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8913 : // (intrinsic_wo_chain:{ *:[v4i8] } 3619:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8914 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
8915 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8916 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8917 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8918 : GIR_EraseFromParent, /*InsnID*/0,
8919 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8920 : // GIR_Coverage, 1229,
8921 : GIR_Done,
8922 : // Label 618: @20843
8923 : GIM_Try, /*On fail goto*//*Label 619*/ 20895, // Rule ID 1239 //
8924 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8925 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
8926 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8927 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8928 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8931 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8932 : // (intrinsic_wo_chain:{ *:[v2i16] } 3501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8933 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
8934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8935 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8936 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8937 : GIR_EraseFromParent, /*InsnID*/0,
8938 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8939 : // GIR_Coverage, 1239,
8940 : GIR_Done,
8941 : // Label 619: @20895
8942 : GIM_Try, /*On fail goto*//*Label 620*/ 20947, // Rule ID 1240 //
8943 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8944 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
8945 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8946 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8947 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8948 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8949 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8950 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8951 : // (intrinsic_wo_chain:{ *:[v4i8] } 3502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8952 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
8953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8954 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8955 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8956 : GIR_EraseFromParent, /*InsnID*/0,
8957 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8958 : // GIR_Coverage, 1240,
8959 : GIR_Done,
8960 : // Label 620: @20947
8961 : GIM_Try, /*On fail goto*//*Label 621*/ 20999, // Rule ID 1259 //
8962 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8963 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
8964 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8965 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8966 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8968 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8969 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8970 : // (intrinsic_wo_chain:{ *:[v2i16] } 3473:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8971 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
8972 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8973 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8974 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8975 : GIR_EraseFromParent, /*InsnID*/0,
8976 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8977 : // GIR_Coverage, 1259,
8978 : GIR_Done,
8979 : // Label 621: @20999
8980 : GIM_Try, /*On fail goto*//*Label 622*/ 21051, // Rule ID 1265 //
8981 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8982 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
8983 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8984 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8985 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
8987 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8988 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8989 : // (intrinsic_wo_chain:{ *:[i32] } 3426:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8990 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
8991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8992 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8993 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8994 : GIR_EraseFromParent, /*InsnID*/0,
8995 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8996 : // GIR_Coverage, 1265,
8997 : GIR_Done,
8998 : // Label 622: @21051
8999 : GIM_Try, /*On fail goto*//*Label 623*/ 21103, // Rule ID 1278 //
9000 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9001 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
9002 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9003 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9004 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9006 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9007 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9008 : // (intrinsic_wo_chain:{ *:[v2i16] } 2980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9009 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
9010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9011 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9012 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9013 : GIR_EraseFromParent, /*InsnID*/0,
9014 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9015 : // GIR_Coverage, 1278,
9016 : GIR_Done,
9017 : // Label 623: @21103
9018 : GIM_Try, /*On fail goto*//*Label 624*/ 21155, // Rule ID 1279 //
9019 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9020 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
9021 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9022 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9023 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9027 : // (intrinsic_wo_chain:{ *:[v2i16] } 2981:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
9029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9031 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9032 : GIR_EraseFromParent, /*InsnID*/0,
9033 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9034 : // GIR_Coverage, 1279,
9035 : GIR_Done,
9036 : // Label 624: @21155
9037 : GIM_Try, /*On fail goto*//*Label 625*/ 21207, // Rule ID 1280 //
9038 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9039 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
9040 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9041 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9042 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9044 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9046 : // (intrinsic_wo_chain:{ *:[i32] } 2983:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9047 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
9048 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9049 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9050 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9051 : GIR_EraseFromParent, /*InsnID*/0,
9052 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9053 : // GIR_Coverage, 1280,
9054 : GIR_Done,
9055 : // Label 625: @21207
9056 : GIM_Try, /*On fail goto*//*Label 626*/ 21259, // Rule ID 1281 //
9057 : GIM_CheckFeatures, GIFBS_HasDSPR2_In |
