Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Target Instruction Enum Values and Descriptors *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_INSTRINFO_ENUM
10 : #undef GET_INSTRINFO_ENUM
11 : namespace llvm {
12 :
13 : namespace Mips {
14 : enum {
15 : PHI = 0,
16 : INLINEASM = 1,
17 : CFI_INSTRUCTION = 2,
18 : EH_LABEL = 3,
19 : GC_LABEL = 4,
20 : ANNOTATION_LABEL = 5,
21 : KILL = 6,
22 : EXTRACT_SUBREG = 7,
23 : INSERT_SUBREG = 8,
24 : IMPLICIT_DEF = 9,
25 : SUBREG_TO_REG = 10,
26 : COPY_TO_REGCLASS = 11,
27 : DBG_VALUE = 12,
28 : DBG_LABEL = 13,
29 : REG_SEQUENCE = 14,
30 : COPY = 15,
31 : BUNDLE = 16,
32 : LIFETIME_START = 17,
33 : LIFETIME_END = 18,
34 : STACKMAP = 19,
35 : FENTRY_CALL = 20,
36 : PATCHPOINT = 21,
37 : LOAD_STACK_GUARD = 22,
38 : STATEPOINT = 23,
39 : LOCAL_ESCAPE = 24,
40 : FAULTING_OP = 25,
41 : PATCHABLE_OP = 26,
42 : PATCHABLE_FUNCTION_ENTER = 27,
43 : PATCHABLE_RET = 28,
44 : PATCHABLE_FUNCTION_EXIT = 29,
45 : PATCHABLE_TAIL_CALL = 30,
46 : PATCHABLE_EVENT_CALL = 31,
47 : PATCHABLE_TYPED_EVENT_CALL = 32,
48 : ICALL_BRANCH_FUNNEL = 33,
49 : G_ADD = 34,
50 : G_SUB = 35,
51 : G_MUL = 36,
52 : G_SDIV = 37,
53 : G_UDIV = 38,
54 : G_SREM = 39,
55 : G_UREM = 40,
56 : G_AND = 41,
57 : G_OR = 42,
58 : G_XOR = 43,
59 : G_IMPLICIT_DEF = 44,
60 : G_PHI = 45,
61 : G_FRAME_INDEX = 46,
62 : G_GLOBAL_VALUE = 47,
63 : G_EXTRACT = 48,
64 : G_UNMERGE_VALUES = 49,
65 : G_INSERT = 50,
66 : G_MERGE_VALUES = 51,
67 : G_PTRTOINT = 52,
68 : G_INTTOPTR = 53,
69 : G_BITCAST = 54,
70 : G_INTRINSIC_TRUNC = 55,
71 : G_INTRINSIC_ROUND = 56,
72 : G_LOAD = 57,
73 : G_SEXTLOAD = 58,
74 : G_ZEXTLOAD = 59,
75 : G_STORE = 60,
76 : G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77 : G_ATOMIC_CMPXCHG = 62,
78 : G_ATOMICRMW_XCHG = 63,
79 : G_ATOMICRMW_ADD = 64,
80 : G_ATOMICRMW_SUB = 65,
81 : G_ATOMICRMW_AND = 66,
82 : G_ATOMICRMW_NAND = 67,
83 : G_ATOMICRMW_OR = 68,
84 : G_ATOMICRMW_XOR = 69,
85 : G_ATOMICRMW_MAX = 70,
86 : G_ATOMICRMW_MIN = 71,
87 : G_ATOMICRMW_UMAX = 72,
88 : G_ATOMICRMW_UMIN = 73,
89 : G_BRCOND = 74,
90 : G_BRINDIRECT = 75,
91 : G_INTRINSIC = 76,
92 : G_INTRINSIC_W_SIDE_EFFECTS = 77,
93 : G_ANYEXT = 78,
94 : G_TRUNC = 79,
95 : G_CONSTANT = 80,
96 : G_FCONSTANT = 81,
97 : G_VASTART = 82,
98 : G_VAARG = 83,
99 : G_SEXT = 84,
100 : G_ZEXT = 85,
101 : G_SHL = 86,
102 : G_LSHR = 87,
103 : G_ASHR = 88,
104 : G_ICMP = 89,
105 : G_FCMP = 90,
106 : G_SELECT = 91,
107 : G_UADDO = 92,
108 : G_UADDE = 93,
109 : G_USUBO = 94,
110 : G_USUBE = 95,
111 : G_SADDO = 96,
112 : G_SADDE = 97,
113 : G_SSUBO = 98,
114 : G_SSUBE = 99,
115 : G_UMULO = 100,
116 : G_SMULO = 101,
117 : G_UMULH = 102,
118 : G_SMULH = 103,
119 : G_FADD = 104,
120 : G_FSUB = 105,
121 : G_FMUL = 106,
122 : G_FMA = 107,
123 : G_FDIV = 108,
124 : G_FREM = 109,
125 : G_FPOW = 110,
126 : G_FEXP = 111,
127 : G_FEXP2 = 112,
128 : G_FLOG = 113,
129 : G_FLOG2 = 114,
130 : G_FNEG = 115,
131 : G_FPEXT = 116,
132 : G_FPTRUNC = 117,
133 : G_FPTOSI = 118,
134 : G_FPTOUI = 119,
135 : G_SITOFP = 120,
136 : G_UITOFP = 121,
137 : G_FABS = 122,
138 : G_GEP = 123,
139 : G_PTR_MASK = 124,
140 : G_BR = 125,
141 : G_INSERT_VECTOR_ELT = 126,
142 : G_EXTRACT_VECTOR_ELT = 127,
143 : G_SHUFFLE_VECTOR = 128,
144 : G_CTTZ = 129,
145 : G_CTTZ_ZERO_UNDEF = 130,
146 : G_CTLZ = 131,
147 : G_CTLZ_ZERO_UNDEF = 132,
148 : G_CTPOP = 133,
149 : G_BSWAP = 134,
150 : G_ADDRSPACE_CAST = 135,
151 : G_BLOCK_ADDR = 136,
152 : ABSMacro = 137,
153 : ADJCALLSTACKDOWN = 138,
154 : ADJCALLSTACKUP = 139,
155 : AND_V_D_PSEUDO = 140,
156 : AND_V_H_PSEUDO = 141,
157 : AND_V_W_PSEUDO = 142,
158 : ATOMIC_CMP_SWAP_I16 = 143,
159 : ATOMIC_CMP_SWAP_I16_POSTRA = 144,
160 : ATOMIC_CMP_SWAP_I32 = 145,
161 : ATOMIC_CMP_SWAP_I32_POSTRA = 146,
162 : ATOMIC_CMP_SWAP_I64 = 147,
163 : ATOMIC_CMP_SWAP_I64_POSTRA = 148,
164 : ATOMIC_CMP_SWAP_I8 = 149,
165 : ATOMIC_CMP_SWAP_I8_POSTRA = 150,
166 : ATOMIC_LOAD_ADD_I16 = 151,
167 : ATOMIC_LOAD_ADD_I16_POSTRA = 152,
168 : ATOMIC_LOAD_ADD_I32 = 153,
169 : ATOMIC_LOAD_ADD_I32_POSTRA = 154,
170 : ATOMIC_LOAD_ADD_I64 = 155,
171 : ATOMIC_LOAD_ADD_I64_POSTRA = 156,
172 : ATOMIC_LOAD_ADD_I8 = 157,
173 : ATOMIC_LOAD_ADD_I8_POSTRA = 158,
174 : ATOMIC_LOAD_AND_I16 = 159,
175 : ATOMIC_LOAD_AND_I16_POSTRA = 160,
176 : ATOMIC_LOAD_AND_I32 = 161,
177 : ATOMIC_LOAD_AND_I32_POSTRA = 162,
178 : ATOMIC_LOAD_AND_I64 = 163,
179 : ATOMIC_LOAD_AND_I64_POSTRA = 164,
180 : ATOMIC_LOAD_AND_I8 = 165,
181 : ATOMIC_LOAD_AND_I8_POSTRA = 166,
182 : ATOMIC_LOAD_NAND_I16 = 167,
183 : ATOMIC_LOAD_NAND_I16_POSTRA = 168,
184 : ATOMIC_LOAD_NAND_I32 = 169,
185 : ATOMIC_LOAD_NAND_I32_POSTRA = 170,
186 : ATOMIC_LOAD_NAND_I64 = 171,
187 : ATOMIC_LOAD_NAND_I64_POSTRA = 172,
188 : ATOMIC_LOAD_NAND_I8 = 173,
189 : ATOMIC_LOAD_NAND_I8_POSTRA = 174,
190 : ATOMIC_LOAD_OR_I16 = 175,
191 : ATOMIC_LOAD_OR_I16_POSTRA = 176,
192 : ATOMIC_LOAD_OR_I32 = 177,
193 : ATOMIC_LOAD_OR_I32_POSTRA = 178,
194 : ATOMIC_LOAD_OR_I64 = 179,
195 : ATOMIC_LOAD_OR_I64_POSTRA = 180,
196 : ATOMIC_LOAD_OR_I8 = 181,
197 : ATOMIC_LOAD_OR_I8_POSTRA = 182,
198 : ATOMIC_LOAD_SUB_I16 = 183,
199 : ATOMIC_LOAD_SUB_I16_POSTRA = 184,
200 : ATOMIC_LOAD_SUB_I32 = 185,
201 : ATOMIC_LOAD_SUB_I32_POSTRA = 186,
202 : ATOMIC_LOAD_SUB_I64 = 187,
203 : ATOMIC_LOAD_SUB_I64_POSTRA = 188,
204 : ATOMIC_LOAD_SUB_I8 = 189,
205 : ATOMIC_LOAD_SUB_I8_POSTRA = 190,
206 : ATOMIC_LOAD_XOR_I16 = 191,
207 : ATOMIC_LOAD_XOR_I16_POSTRA = 192,
208 : ATOMIC_LOAD_XOR_I32 = 193,
209 : ATOMIC_LOAD_XOR_I32_POSTRA = 194,
210 : ATOMIC_LOAD_XOR_I64 = 195,
211 : ATOMIC_LOAD_XOR_I64_POSTRA = 196,
212 : ATOMIC_LOAD_XOR_I8 = 197,
213 : ATOMIC_LOAD_XOR_I8_POSTRA = 198,
214 : ATOMIC_SWAP_I16 = 199,
215 : ATOMIC_SWAP_I16_POSTRA = 200,
216 : ATOMIC_SWAP_I32 = 201,
217 : ATOMIC_SWAP_I32_POSTRA = 202,
218 : ATOMIC_SWAP_I64 = 203,
219 : ATOMIC_SWAP_I64_POSTRA = 204,
220 : ATOMIC_SWAP_I8 = 205,
221 : ATOMIC_SWAP_I8_POSTRA = 206,
222 : B = 207,
223 : BAL_BR = 208,
224 : BAL_BR_MM = 209,
225 : BEQLImmMacro = 210,
226 : BGE = 211,
227 : BGEImmMacro = 212,
228 : BGEL = 213,
229 : BGELImmMacro = 214,
230 : BGEU = 215,
231 : BGEUImmMacro = 216,
232 : BGEUL = 217,
233 : BGEULImmMacro = 218,
234 : BGT = 219,
235 : BGTImmMacro = 220,
236 : BGTL = 221,
237 : BGTLImmMacro = 222,
238 : BGTU = 223,
239 : BGTUImmMacro = 224,
240 : BGTUL = 225,
241 : BGTULImmMacro = 226,
242 : BLE = 227,
243 : BLEImmMacro = 228,
244 : BLEL = 229,
245 : BLELImmMacro = 230,
246 : BLEU = 231,
247 : BLEUImmMacro = 232,
248 : BLEUL = 233,
249 : BLEULImmMacro = 234,
250 : BLT = 235,
251 : BLTImmMacro = 236,
252 : BLTL = 237,
253 : BLTLImmMacro = 238,
254 : BLTU = 239,
255 : BLTUImmMacro = 240,
256 : BLTUL = 241,
257 : BLTULImmMacro = 242,
258 : BNELImmMacro = 243,
259 : BPOSGE32_PSEUDO = 244,
260 : BSEL_D_PSEUDO = 245,
261 : BSEL_FD_PSEUDO = 246,
262 : BSEL_FW_PSEUDO = 247,
263 : BSEL_H_PSEUDO = 248,
264 : BSEL_W_PSEUDO = 249,
265 : B_MM = 250,
266 : B_MMR6_Pseudo = 251,
267 : B_MM_Pseudo = 252,
268 : BeqImm = 253,
269 : BneImm = 254,
270 : BteqzT8CmpX16 = 255,
271 : BteqzT8CmpiX16 = 256,
272 : BteqzT8SltX16 = 257,
273 : BteqzT8SltiX16 = 258,
274 : BteqzT8SltiuX16 = 259,
275 : BteqzT8SltuX16 = 260,
276 : BtnezT8CmpX16 = 261,
277 : BtnezT8CmpiX16 = 262,
278 : BtnezT8SltX16 = 263,
279 : BtnezT8SltiX16 = 264,
280 : BtnezT8SltiuX16 = 265,
281 : BtnezT8SltuX16 = 266,
282 : BuildPairF64 = 267,
283 : BuildPairF64_64 = 268,
284 : CFTC1 = 269,
285 : CONSTPOOL_ENTRY = 270,
286 : COPY_FD_PSEUDO = 271,
287 : COPY_FW_PSEUDO = 272,
288 : CTTC1 = 273,
289 : Constant32 = 274,
290 : DMULImmMacro = 275,
291 : DMULMacro = 276,
292 : DMULOMacro = 277,
293 : DMULOUMacro = 278,
294 : DROL = 279,
295 : DROLImm = 280,
296 : DROR = 281,
297 : DRORImm = 282,
298 : DSDivIMacro = 283,
299 : DSDivMacro = 284,
300 : DSRemIMacro = 285,
301 : DSRemMacro = 286,
302 : DUDivIMacro = 287,
303 : DUDivMacro = 288,
304 : DURemIMacro = 289,
305 : DURemMacro = 290,
306 : ERet = 291,
307 : ExtractElementF64 = 292,
308 : ExtractElementF64_64 = 293,
309 : FABS_D = 294,
310 : FABS_W = 295,
311 : FEXP2_D_1_PSEUDO = 296,
312 : FEXP2_W_1_PSEUDO = 297,
313 : FILL_FD_PSEUDO = 298,
314 : FILL_FW_PSEUDO = 299,
315 : GotPrologue16 = 300,
316 : INSERT_B_VIDX64_PSEUDO = 301,
317 : INSERT_B_VIDX_PSEUDO = 302,
318 : INSERT_D_VIDX64_PSEUDO = 303,
319 : INSERT_D_VIDX_PSEUDO = 304,
320 : INSERT_FD_PSEUDO = 305,
321 : INSERT_FD_VIDX64_PSEUDO = 306,
322 : INSERT_FD_VIDX_PSEUDO = 307,
323 : INSERT_FW_PSEUDO = 308,
324 : INSERT_FW_VIDX64_PSEUDO = 309,
325 : INSERT_FW_VIDX_PSEUDO = 310,
326 : INSERT_H_VIDX64_PSEUDO = 311,
327 : INSERT_H_VIDX_PSEUDO = 312,
328 : INSERT_W_VIDX64_PSEUDO = 313,
329 : INSERT_W_VIDX_PSEUDO = 314,
330 : JALR64Pseudo = 315,
331 : JALRHB64Pseudo = 316,
332 : JALRHBPseudo = 317,
333 : JALRPseudo = 318,
334 : JalOneReg = 319,
335 : JalTwoReg = 320,
336 : LDMacro = 321,
337 : LD_F16 = 322,
338 : LOAD_ACC128 = 323,
339 : LOAD_ACC64 = 324,
340 : LOAD_ACC64DSP = 325,
341 : LOAD_CCOND_DSP = 326,
342 : LONG_BRANCH_ADDiu = 327,
343 : LONG_BRANCH_DADDiu = 328,
344 : LONG_BRANCH_LUi = 329,
345 : LWM_MM = 330,
346 : LoadAddrImm32 = 331,
347 : LoadAddrImm64 = 332,
348 : LoadAddrReg32 = 333,
349 : LoadAddrReg64 = 334,
350 : LoadImm32 = 335,
351 : LoadImm64 = 336,
352 : LoadImmDoubleFGR = 337,
353 : LoadImmDoubleFGR_32 = 338,
354 : LoadImmDoubleGPR = 339,
355 : LoadImmSingleFGR = 340,
356 : LoadImmSingleGPR = 341,
357 : LwConstant32 = 342,
358 : MFTACX = 343,
359 : MFTC0 = 344,
360 : MFTC1 = 345,
361 : MFTDSP = 346,
362 : MFTGPR = 347,
363 : MFTHC1 = 348,
364 : MFTHI = 349,
365 : MFTLO = 350,
366 : MIPSeh_return32 = 351,
367 : MIPSeh_return64 = 352,
368 : MSA_FP_EXTEND_D_PSEUDO = 353,
369 : MSA_FP_EXTEND_W_PSEUDO = 354,
370 : MSA_FP_ROUND_D_PSEUDO = 355,
371 : MSA_FP_ROUND_W_PSEUDO = 356,
372 : MTTACX = 357,
373 : MTTC0 = 358,
374 : MTTC1 = 359,
375 : MTTDSP = 360,
376 : MTTGPR = 361,
377 : MTTHC1 = 362,
378 : MTTHI = 363,
379 : MTTLO = 364,
380 : MULImmMacro = 365,
381 : MULOMacro = 366,
382 : MULOUMacro = 367,
383 : MultRxRy16 = 368,
384 : MultRxRyRz16 = 369,
385 : MultuRxRy16 = 370,
386 : MultuRxRyRz16 = 371,
387 : NOP = 372,
388 : NORImm = 373,
389 : NORImm64 = 374,
390 : NOR_V_D_PSEUDO = 375,
391 : NOR_V_H_PSEUDO = 376,
392 : NOR_V_W_PSEUDO = 377,
393 : OR_V_D_PSEUDO = 378,
394 : OR_V_H_PSEUDO = 379,
395 : OR_V_W_PSEUDO = 380,
396 : PseudoCMPU_EQ_QB = 381,
397 : PseudoCMPU_LE_QB = 382,
398 : PseudoCMPU_LT_QB = 383,
399 : PseudoCMP_EQ_PH = 384,
400 : PseudoCMP_LE_PH = 385,
401 : PseudoCMP_LT_PH = 386,
402 : PseudoCVT_D32_W = 387,
403 : PseudoCVT_D64_L = 388,
404 : PseudoCVT_D64_W = 389,
405 : PseudoCVT_S_L = 390,
406 : PseudoCVT_S_W = 391,
407 : PseudoDMULT = 392,
408 : PseudoDMULTu = 393,
409 : PseudoDSDIV = 394,
410 : PseudoDUDIV = 395,
411 : PseudoIndirectBranch = 396,
412 : PseudoIndirectBranch64 = 397,
413 : PseudoIndirectBranch64R6 = 398,
414 : PseudoIndirectBranchR6 = 399,
415 : PseudoIndirectBranch_MM = 400,
416 : PseudoIndirectBranch_MMR6 = 401,
417 : PseudoIndirectHazardBranch = 402,
418 : PseudoIndirectHazardBranch64 = 403,
419 : PseudoIndrectHazardBranch64R6 = 404,
420 : PseudoIndrectHazardBranchR6 = 405,
421 : PseudoMADD = 406,
422 : PseudoMADDU = 407,
423 : PseudoMADDU_MM = 408,
424 : PseudoMADD_MM = 409,
425 : PseudoMFHI = 410,
426 : PseudoMFHI64 = 411,
427 : PseudoMFHI_MM = 412,
428 : PseudoMFLO = 413,
429 : PseudoMFLO64 = 414,
430 : PseudoMFLO_MM = 415,
431 : PseudoMSUB = 416,
432 : PseudoMSUBU = 417,
433 : PseudoMSUBU_MM = 418,
434 : PseudoMSUB_MM = 419,
435 : PseudoMTLOHI = 420,
436 : PseudoMTLOHI64 = 421,
437 : PseudoMTLOHI_DSP = 422,
438 : PseudoMTLOHI_MM = 423,
439 : PseudoMULT = 424,
440 : PseudoMULT_MM = 425,
441 : PseudoMULTu = 426,
442 : PseudoMULTu_MM = 427,
443 : PseudoPICK_PH = 428,
444 : PseudoPICK_QB = 429,
445 : PseudoReturn = 430,
446 : PseudoReturn64 = 431,
447 : PseudoSDIV = 432,
448 : PseudoSELECTFP_F_D32 = 433,
449 : PseudoSELECTFP_F_D64 = 434,
450 : PseudoSELECTFP_F_I = 435,
451 : PseudoSELECTFP_F_I64 = 436,
452 : PseudoSELECTFP_F_S = 437,
453 : PseudoSELECTFP_T_D32 = 438,
454 : PseudoSELECTFP_T_D64 = 439,
455 : PseudoSELECTFP_T_I = 440,
456 : PseudoSELECTFP_T_I64 = 441,
457 : PseudoSELECTFP_T_S = 442,
458 : PseudoSELECT_D32 = 443,
459 : PseudoSELECT_D64 = 444,
460 : PseudoSELECT_I = 445,
461 : PseudoSELECT_I64 = 446,
462 : PseudoSELECT_S = 447,
463 : PseudoTRUNC_W_D = 448,
464 : PseudoTRUNC_W_D32 = 449,
465 : PseudoTRUNC_W_S = 450,
466 : PseudoUDIV = 451,
467 : ROL = 452,
468 : ROLImm = 453,
469 : ROR = 454,
470 : RORImm = 455,
471 : RetRA = 456,
472 : RetRA16 = 457,
473 : SDIV_MM_Pseudo = 458,
474 : SDMacro = 459,
475 : SDivIMacro = 460,
476 : SDivMacro = 461,
477 : SEQIMacro = 462,
478 : SEQMacro = 463,
479 : SLTImm64 = 464,
480 : SLTUImm64 = 465,
481 : SNZ_B_PSEUDO = 466,
482 : SNZ_D_PSEUDO = 467,
483 : SNZ_H_PSEUDO = 468,
484 : SNZ_V_PSEUDO = 469,
485 : SNZ_W_PSEUDO = 470,
486 : SRemIMacro = 471,
487 : SRemMacro = 472,
488 : STORE_ACC128 = 473,
489 : STORE_ACC64 = 474,
490 : STORE_ACC64DSP = 475,
491 : STORE_CCOND_DSP = 476,
492 : ST_F16 = 477,
493 : SWM_MM = 478,
494 : SZ_B_PSEUDO = 479,
495 : SZ_D_PSEUDO = 480,
496 : SZ_H_PSEUDO = 481,
497 : SZ_V_PSEUDO = 482,
498 : SZ_W_PSEUDO = 483,
499 : SelBeqZ = 484,
500 : SelBneZ = 485,
501 : SelTBteqZCmp = 486,
502 : SelTBteqZCmpi = 487,
503 : SelTBteqZSlt = 488,
504 : SelTBteqZSlti = 489,
505 : SelTBteqZSltiu = 490,
506 : SelTBteqZSltu = 491,
507 : SelTBtneZCmp = 492,
508 : SelTBtneZCmpi = 493,
509 : SelTBtneZSlt = 494,
510 : SelTBtneZSlti = 495,
511 : SelTBtneZSltiu = 496,
512 : SelTBtneZSltu = 497,
513 : SltCCRxRy16 = 498,
514 : SltiCCRxImmX16 = 499,
515 : SltiuCCRxImmX16 = 500,
516 : SltuCCRxRy16 = 501,
517 : SltuRxRyRz16 = 502,
518 : TAILCALL = 503,
519 : TAILCALL64R6REG = 504,
520 : TAILCALLHB64R6REG = 505,
521 : TAILCALLHBR6REG = 506,
522 : TAILCALLR6REG = 507,
523 : TAILCALLREG = 508,
524 : TAILCALLREG64 = 509,
525 : TAILCALLREGHB = 510,
526 : TAILCALLREGHB64 = 511,
527 : TAILCALLREG_MM = 512,
528 : TAILCALLREG_MMR6 = 513,
529 : TAILCALL_MM = 514,
530 : TAILCALL_MMR6 = 515,
531 : TRAP = 516,
532 : TRAP_MM = 517,
533 : UDIV_MM_Pseudo = 518,
534 : UDivIMacro = 519,
535 : UDivMacro = 520,
536 : URemIMacro = 521,
537 : URemMacro = 522,
538 : Ulh = 523,
539 : Ulhu = 524,
540 : Ulw = 525,
541 : Ush = 526,
542 : Usw = 527,
543 : XOR_V_D_PSEUDO = 528,
544 : XOR_V_H_PSEUDO = 529,
545 : XOR_V_W_PSEUDO = 530,
546 : ABSQ_S_PH = 531,
547 : ABSQ_S_PH_MM = 532,
548 : ABSQ_S_QB = 533,
549 : ABSQ_S_QB_MMR2 = 534,
550 : ABSQ_S_W = 535,
551 : ABSQ_S_W_MM = 536,
552 : ADD = 537,
553 : ADDIUPC = 538,
554 : ADDIUPC_MM = 539,
555 : ADDIUPC_MMR6 = 540,
556 : ADDIUR1SP_MM = 541,
557 : ADDIUR2_MM = 542,
558 : ADDIUS5_MM = 543,
559 : ADDIUSP_MM = 544,
560 : ADDIU_MMR6 = 545,
561 : ADDQH_PH = 546,
562 : ADDQH_PH_MMR2 = 547,
563 : ADDQH_R_PH = 548,
564 : ADDQH_R_PH_MMR2 = 549,
565 : ADDQH_R_W = 550,
566 : ADDQH_R_W_MMR2 = 551,
567 : ADDQH_W = 552,
568 : ADDQH_W_MMR2 = 553,
569 : ADDQ_PH = 554,
570 : ADDQ_PH_MM = 555,
571 : ADDQ_S_PH = 556,
572 : ADDQ_S_PH_MM = 557,
573 : ADDQ_S_W = 558,
574 : ADDQ_S_W_MM = 559,
575 : ADDSC = 560,
576 : ADDSC_MM = 561,
577 : ADDS_A_B = 562,
578 : ADDS_A_D = 563,
579 : ADDS_A_H = 564,
580 : ADDS_A_W = 565,
581 : ADDS_S_B = 566,
582 : ADDS_S_D = 567,
583 : ADDS_S_H = 568,
584 : ADDS_S_W = 569,
585 : ADDS_U_B = 570,
586 : ADDS_U_D = 571,
587 : ADDS_U_H = 572,
588 : ADDS_U_W = 573,
589 : ADDU16_MM = 574,
590 : ADDU16_MMR6 = 575,
591 : ADDUH_QB = 576,
592 : ADDUH_QB_MMR2 = 577,
593 : ADDUH_R_QB = 578,
594 : ADDUH_R_QB_MMR2 = 579,
595 : ADDU_MMR6 = 580,
596 : ADDU_PH = 581,
597 : ADDU_PH_MMR2 = 582,
598 : ADDU_QB = 583,
599 : ADDU_QB_MM = 584,
600 : ADDU_S_PH = 585,
601 : ADDU_S_PH_MMR2 = 586,
602 : ADDU_S_QB = 587,
603 : ADDU_S_QB_MM = 588,
604 : ADDVI_B = 589,
605 : ADDVI_D = 590,
606 : ADDVI_H = 591,
607 : ADDVI_W = 592,
608 : ADDV_B = 593,
609 : ADDV_D = 594,
610 : ADDV_H = 595,
611 : ADDV_W = 596,
612 : ADDWC = 597,
613 : ADDWC_MM = 598,
614 : ADD_A_B = 599,
615 : ADD_A_D = 600,
616 : ADD_A_H = 601,
617 : ADD_A_W = 602,
618 : ADD_MM = 603,
619 : ADD_MMR6 = 604,
620 : ADDi = 605,
621 : ADDi_MM = 606,
622 : ADDiu = 607,
623 : ADDiu_MM = 608,
624 : ADDu = 609,
625 : ADDu_MM = 610,
626 : ALIGN = 611,
627 : ALIGN_MMR6 = 612,
628 : ALUIPC = 613,
629 : ALUIPC_MMR6 = 614,
630 : AND = 615,
631 : AND16_MM = 616,
632 : AND16_MMR6 = 617,
633 : AND64 = 618,
634 : ANDI16_MM = 619,
635 : ANDI16_MMR6 = 620,
636 : ANDI_B = 621,
637 : ANDI_MMR6 = 622,
638 : AND_MM = 623,
639 : AND_MMR6 = 624,
640 : AND_V = 625,
641 : ANDi = 626,
642 : ANDi64 = 627,
643 : ANDi_MM = 628,
644 : APPEND = 629,
645 : APPEND_MMR2 = 630,
646 : ASUB_S_B = 631,
647 : ASUB_S_D = 632,
648 : ASUB_S_H = 633,
649 : ASUB_S_W = 634,
650 : ASUB_U_B = 635,
651 : ASUB_U_D = 636,
652 : ASUB_U_H = 637,
653 : ASUB_U_W = 638,
654 : AUI = 639,
655 : AUIPC = 640,
656 : AUIPC_MMR6 = 641,
657 : AUI_MMR6 = 642,
658 : AVER_S_B = 643,
659 : AVER_S_D = 644,
660 : AVER_S_H = 645,
661 : AVER_S_W = 646,
662 : AVER_U_B = 647,
663 : AVER_U_D = 648,
664 : AVER_U_H = 649,
665 : AVER_U_W = 650,
666 : AVE_S_B = 651,
667 : AVE_S_D = 652,
668 : AVE_S_H = 653,
669 : AVE_S_W = 654,
670 : AVE_U_B = 655,
671 : AVE_U_D = 656,
672 : AVE_U_H = 657,
673 : AVE_U_W = 658,
674 : AddiuRxImmX16 = 659,
675 : AddiuRxPcImmX16 = 660,
676 : AddiuRxRxImm16 = 661,
677 : AddiuRxRxImmX16 = 662,
678 : AddiuRxRyOffMemX16 = 663,
679 : AddiuSpImm16 = 664,
680 : AddiuSpImmX16 = 665,
681 : AdduRxRyRz16 = 666,
682 : AndRxRxRy16 = 667,
683 : B16_MM = 668,
684 : BADDu = 669,
685 : BAL = 670,
686 : BALC = 671,
687 : BALC_MMR6 = 672,
688 : BALIGN = 673,
689 : BALIGN_MMR2 = 674,
690 : BBIT0 = 675,
691 : BBIT032 = 676,
692 : BBIT1 = 677,
693 : BBIT132 = 678,
694 : BC = 679,
695 : BC16_MMR6 = 680,
696 : BC1EQZ = 681,
697 : BC1EQZC_MMR6 = 682,
698 : BC1F = 683,
699 : BC1FL = 684,
700 : BC1F_MM = 685,
701 : BC1NEZ = 686,
702 : BC1NEZC_MMR6 = 687,
703 : BC1T = 688,
704 : BC1TL = 689,
705 : BC1T_MM = 690,
706 : BC2EQZ = 691,
707 : BC2EQZC_MMR6 = 692,
708 : BC2NEZ = 693,
709 : BC2NEZC_MMR6 = 694,
710 : BCLRI_B = 695,
711 : BCLRI_D = 696,
712 : BCLRI_H = 697,
713 : BCLRI_W = 698,
714 : BCLR_B = 699,
715 : BCLR_D = 700,
716 : BCLR_H = 701,
717 : BCLR_W = 702,
718 : BC_MMR6 = 703,
719 : BEQ = 704,
720 : BEQ64 = 705,
721 : BEQC = 706,
722 : BEQC64 = 707,
723 : BEQC_MMR6 = 708,
724 : BEQL = 709,
725 : BEQZ16_MM = 710,
726 : BEQZALC = 711,
727 : BEQZALC_MMR6 = 712,
728 : BEQZC = 713,
729 : BEQZC16_MMR6 = 714,
730 : BEQZC64 = 715,
731 : BEQZC_MM = 716,
732 : BEQZC_MMR6 = 717,
733 : BEQ_MM = 718,
734 : BGEC = 719,
735 : BGEC64 = 720,
736 : BGEC_MMR6 = 721,
737 : BGEUC = 722,
738 : BGEUC64 = 723,
739 : BGEUC_MMR6 = 724,
740 : BGEZ = 725,
741 : BGEZ64 = 726,
742 : BGEZAL = 727,
743 : BGEZALC = 728,
744 : BGEZALC_MMR6 = 729,
745 : BGEZALL = 730,
746 : BGEZALS_MM = 731,
747 : BGEZAL_MM = 732,
748 : BGEZC = 733,
749 : BGEZC64 = 734,
750 : BGEZC_MMR6 = 735,
751 : BGEZL = 736,
752 : BGEZ_MM = 737,
753 : BGTZ = 738,
754 : BGTZ64 = 739,
755 : BGTZALC = 740,
756 : BGTZALC_MMR6 = 741,
757 : BGTZC = 742,
758 : BGTZC64 = 743,
759 : BGTZC_MMR6 = 744,
760 : BGTZL = 745,
761 : BGTZ_MM = 746,
762 : BINSLI_B = 747,
763 : BINSLI_D = 748,
764 : BINSLI_H = 749,
765 : BINSLI_W = 750,
766 : BINSL_B = 751,
767 : BINSL_D = 752,
768 : BINSL_H = 753,
769 : BINSL_W = 754,
770 : BINSRI_B = 755,
771 : BINSRI_D = 756,
772 : BINSRI_H = 757,
773 : BINSRI_W = 758,
774 : BINSR_B = 759,
775 : BINSR_D = 760,
776 : BINSR_H = 761,
777 : BINSR_W = 762,
778 : BITREV = 763,
779 : BITREV_MM = 764,
780 : BITSWAP = 765,
781 : BITSWAP_MMR6 = 766,
782 : BLEZ = 767,
783 : BLEZ64 = 768,
784 : BLEZALC = 769,
785 : BLEZALC_MMR6 = 770,
786 : BLEZC = 771,
787 : BLEZC64 = 772,
788 : BLEZC_MMR6 = 773,
789 : BLEZL = 774,
790 : BLEZ_MM = 775,
791 : BLTC = 776,
792 : BLTC64 = 777,
793 : BLTC_MMR6 = 778,
794 : BLTUC = 779,
795 : BLTUC64 = 780,
796 : BLTUC_MMR6 = 781,
797 : BLTZ = 782,
798 : BLTZ64 = 783,
799 : BLTZAL = 784,
800 : BLTZALC = 785,
801 : BLTZALC_MMR6 = 786,
802 : BLTZALL = 787,
803 : BLTZALS_MM = 788,
804 : BLTZAL_MM = 789,
805 : BLTZC = 790,
806 : BLTZC64 = 791,
807 : BLTZC_MMR6 = 792,
808 : BLTZL = 793,
809 : BLTZ_MM = 794,
810 : BMNZI_B = 795,
811 : BMNZ_V = 796,
812 : BMZI_B = 797,
813 : BMZ_V = 798,
814 : BNE = 799,
815 : BNE64 = 800,
816 : BNEC = 801,
817 : BNEC64 = 802,
818 : BNEC_MMR6 = 803,
819 : BNEGI_B = 804,
820 : BNEGI_D = 805,
821 : BNEGI_H = 806,
822 : BNEGI_W = 807,
823 : BNEG_B = 808,
824 : BNEG_D = 809,
825 : BNEG_H = 810,
826 : BNEG_W = 811,
827 : BNEL = 812,
828 : BNEZ16_MM = 813,
829 : BNEZALC = 814,
830 : BNEZALC_MMR6 = 815,
831 : BNEZC = 816,
832 : BNEZC16_MMR6 = 817,
833 : BNEZC64 = 818,
834 : BNEZC_MM = 819,
835 : BNEZC_MMR6 = 820,
836 : BNE_MM = 821,
837 : BNVC = 822,
838 : BNVC_MMR6 = 823,
839 : BNZ_B = 824,
840 : BNZ_D = 825,
841 : BNZ_H = 826,
842 : BNZ_V = 827,
843 : BNZ_W = 828,
844 : BOVC = 829,
845 : BOVC_MMR6 = 830,
846 : BPOSGE32 = 831,
847 : BPOSGE32C_MMR3 = 832,
848 : BPOSGE32_MM = 833,
849 : BREAK = 834,
850 : BREAK16_MM = 835,
851 : BREAK16_MMR6 = 836,
852 : BREAK_MM = 837,
853 : BREAK_MMR6 = 838,
854 : BSELI_B = 839,
855 : BSEL_V = 840,
856 : BSETI_B = 841,
857 : BSETI_D = 842,
858 : BSETI_H = 843,
859 : BSETI_W = 844,
860 : BSET_B = 845,
861 : BSET_D = 846,
862 : BSET_H = 847,
863 : BSET_W = 848,
864 : BZ_B = 849,
865 : BZ_D = 850,
866 : BZ_H = 851,
867 : BZ_V = 852,
868 : BZ_W = 853,
869 : BeqzRxImm16 = 854,
870 : BeqzRxImmX16 = 855,
871 : Bimm16 = 856,
872 : BimmX16 = 857,
873 : BnezRxImm16 = 858,
874 : BnezRxImmX16 = 859,
875 : Break16 = 860,
876 : Bteqz16 = 861,
877 : BteqzX16 = 862,
878 : Btnez16 = 863,
879 : BtnezX16 = 864,
880 : CACHE = 865,
881 : CACHEE = 866,
882 : CACHEE_MM = 867,
883 : CACHE_MM = 868,
884 : CACHE_MMR6 = 869,
885 : CACHE_R6 = 870,
886 : CEIL_L_D64 = 871,
887 : CEIL_L_D_MMR6 = 872,
888 : CEIL_L_S = 873,
889 : CEIL_L_S_MMR6 = 874,
890 : CEIL_W_D32 = 875,
891 : CEIL_W_D64 = 876,
892 : CEIL_W_D_MMR6 = 877,
893 : CEIL_W_MM = 878,
894 : CEIL_W_S = 879,
895 : CEIL_W_S_MM = 880,
896 : CEIL_W_S_MMR6 = 881,
897 : CEQI_B = 882,
898 : CEQI_D = 883,
899 : CEQI_H = 884,
900 : CEQI_W = 885,
901 : CEQ_B = 886,
902 : CEQ_D = 887,
903 : CEQ_H = 888,
904 : CEQ_W = 889,
905 : CFC1 = 890,
906 : CFC1_MM = 891,
907 : CFC2_MM = 892,
908 : CFCMSA = 893,
909 : CINS = 894,
910 : CINS32 = 895,
911 : CINS64_32 = 896,
912 : CINS_i32 = 897,
913 : CLASS_D = 898,
914 : CLASS_D_MMR6 = 899,
915 : CLASS_S = 900,
916 : CLASS_S_MMR6 = 901,
917 : CLEI_S_B = 902,
918 : CLEI_S_D = 903,
919 : CLEI_S_H = 904,
920 : CLEI_S_W = 905,
921 : CLEI_U_B = 906,
922 : CLEI_U_D = 907,
923 : CLEI_U_H = 908,
924 : CLEI_U_W = 909,
925 : CLE_S_B = 910,
926 : CLE_S_D = 911,
927 : CLE_S_H = 912,
928 : CLE_S_W = 913,
929 : CLE_U_B = 914,
930 : CLE_U_D = 915,
931 : CLE_U_H = 916,
932 : CLE_U_W = 917,
933 : CLO = 918,
934 : CLO_MM = 919,
935 : CLO_MMR6 = 920,
936 : CLO_R6 = 921,
937 : CLTI_S_B = 922,
938 : CLTI_S_D = 923,
939 : CLTI_S_H = 924,
940 : CLTI_S_W = 925,
941 : CLTI_U_B = 926,
942 : CLTI_U_D = 927,
943 : CLTI_U_H = 928,
944 : CLTI_U_W = 929,
945 : CLT_S_B = 930,
946 : CLT_S_D = 931,
947 : CLT_S_H = 932,
948 : CLT_S_W = 933,
949 : CLT_U_B = 934,
950 : CLT_U_D = 935,
951 : CLT_U_H = 936,
952 : CLT_U_W = 937,
953 : CLZ = 938,
954 : CLZ_MM = 939,
955 : CLZ_MMR6 = 940,
956 : CLZ_R6 = 941,
957 : CMPGDU_EQ_QB = 942,
958 : CMPGDU_EQ_QB_MMR2 = 943,
959 : CMPGDU_LE_QB = 944,
960 : CMPGDU_LE_QB_MMR2 = 945,
961 : CMPGDU_LT_QB = 946,
962 : CMPGDU_LT_QB_MMR2 = 947,
963 : CMPGU_EQ_QB = 948,
964 : CMPGU_EQ_QB_MM = 949,
965 : CMPGU_LE_QB = 950,
966 : CMPGU_LE_QB_MM = 951,
967 : CMPGU_LT_QB = 952,
968 : CMPGU_LT_QB_MM = 953,
969 : CMPU_EQ_QB = 954,
970 : CMPU_EQ_QB_MM = 955,
971 : CMPU_LE_QB = 956,
972 : CMPU_LE_QB_MM = 957,
973 : CMPU_LT_QB = 958,
974 : CMPU_LT_QB_MM = 959,
975 : CMP_AF_D_MMR6 = 960,
976 : CMP_AF_S_MMR6 = 961,
977 : CMP_EQ_D = 962,
978 : CMP_EQ_D_MMR6 = 963,
979 : CMP_EQ_PH = 964,
980 : CMP_EQ_PH_MM = 965,
981 : CMP_EQ_S = 966,
982 : CMP_EQ_S_MMR6 = 967,
983 : CMP_F_D = 968,
984 : CMP_F_S = 969,
985 : CMP_LE_D = 970,
986 : CMP_LE_D_MMR6 = 971,
987 : CMP_LE_PH = 972,
988 : CMP_LE_PH_MM = 973,
989 : CMP_LE_S = 974,
990 : CMP_LE_S_MMR6 = 975,
991 : CMP_LT_D = 976,
992 : CMP_LT_D_MMR6 = 977,
993 : CMP_LT_PH = 978,
994 : CMP_LT_PH_MM = 979,
995 : CMP_LT_S = 980,
996 : CMP_LT_S_MMR6 = 981,
997 : CMP_SAF_D = 982,
998 : CMP_SAF_D_MMR6 = 983,
999 : CMP_SAF_S = 984,
1000 : CMP_SAF_S_MMR6 = 985,
1001 : CMP_SEQ_D = 986,
1002 : CMP_SEQ_D_MMR6 = 987,
1003 : CMP_SEQ_S = 988,
1004 : CMP_SEQ_S_MMR6 = 989,
1005 : CMP_SLE_D = 990,
1006 : CMP_SLE_D_MMR6 = 991,
1007 : CMP_SLE_S = 992,
1008 : CMP_SLE_S_MMR6 = 993,
1009 : CMP_SLT_D = 994,
1010 : CMP_SLT_D_MMR6 = 995,
1011 : CMP_SLT_S = 996,
1012 : CMP_SLT_S_MMR6 = 997,
1013 : CMP_SUEQ_D = 998,
1014 : CMP_SUEQ_D_MMR6 = 999,
1015 : CMP_SUEQ_S = 1000,
1016 : CMP_SUEQ_S_MMR6 = 1001,
1017 : CMP_SULE_D = 1002,
1018 : CMP_SULE_D_MMR6 = 1003,
1019 : CMP_SULE_S = 1004,
1020 : CMP_SULE_S_MMR6 = 1005,
1021 : CMP_SULT_D = 1006,
1022 : CMP_SULT_D_MMR6 = 1007,
1023 : CMP_SULT_S = 1008,
1024 : CMP_SULT_S_MMR6 = 1009,
1025 : CMP_SUN_D = 1010,
1026 : CMP_SUN_D_MMR6 = 1011,
1027 : CMP_SUN_S = 1012,
1028 : CMP_SUN_S_MMR6 = 1013,
1029 : CMP_UEQ_D = 1014,
1030 : CMP_UEQ_D_MMR6 = 1015,
1031 : CMP_UEQ_S = 1016,
1032 : CMP_UEQ_S_MMR6 = 1017,
1033 : CMP_ULE_D = 1018,
1034 : CMP_ULE_D_MMR6 = 1019,
1035 : CMP_ULE_S = 1020,
1036 : CMP_ULE_S_MMR6 = 1021,
1037 : CMP_ULT_D = 1022,
1038 : CMP_ULT_D_MMR6 = 1023,
1039 : CMP_ULT_S = 1024,
1040 : CMP_ULT_S_MMR6 = 1025,
1041 : CMP_UN_D = 1026,
1042 : CMP_UN_D_MMR6 = 1027,
1043 : CMP_UN_S = 1028,
1044 : CMP_UN_S_MMR6 = 1029,
1045 : COPY_S_B = 1030,
1046 : COPY_S_D = 1031,
1047 : COPY_S_H = 1032,
1048 : COPY_S_W = 1033,
1049 : COPY_U_B = 1034,
1050 : COPY_U_H = 1035,
1051 : COPY_U_W = 1036,
1052 : CRC32B = 1037,
1053 : CRC32CB = 1038,
1054 : CRC32CD = 1039,
1055 : CRC32CH = 1040,
1056 : CRC32CW = 1041,
1057 : CRC32D = 1042,
1058 : CRC32H = 1043,
1059 : CRC32W = 1044,
1060 : CTC1 = 1045,
1061 : CTC1_MM = 1046,
1062 : CTC2_MM = 1047,
1063 : CTCMSA = 1048,
1064 : CVT_D32_S = 1049,
1065 : CVT_D32_S_MM = 1050,
1066 : CVT_D32_W = 1051,
1067 : CVT_D32_W_MM = 1052,
1068 : CVT_D64_L = 1053,
1069 : CVT_D64_S = 1054,
1070 : CVT_D64_S_MM = 1055,
1071 : CVT_D64_W = 1056,
1072 : CVT_D64_W_MM = 1057,
1073 : CVT_D_L_MMR6 = 1058,
1074 : CVT_L_D64 = 1059,
1075 : CVT_L_D64_MM = 1060,
1076 : CVT_L_D_MMR6 = 1061,
1077 : CVT_L_S = 1062,
1078 : CVT_L_S_MM = 1063,
1079 : CVT_L_S_MMR6 = 1064,
1080 : CVT_PS_S64 = 1065,
1081 : CVT_S_D32 = 1066,
1082 : CVT_S_D32_MM = 1067,
1083 : CVT_S_D64 = 1068,
1084 : CVT_S_D64_MM = 1069,
1085 : CVT_S_L = 1070,
1086 : CVT_S_L_MMR6 = 1071,
1087 : CVT_S_PL64 = 1072,
1088 : CVT_S_PU64 = 1073,
1089 : CVT_S_W = 1074,
1090 : CVT_S_W_MM = 1075,
1091 : CVT_S_W_MMR6 = 1076,
1092 : CVT_W_D32 = 1077,
1093 : CVT_W_D32_MM = 1078,
1094 : CVT_W_D64 = 1079,
1095 : CVT_W_D64_MM = 1080,
1096 : CVT_W_S = 1081,
1097 : CVT_W_S_MM = 1082,
1098 : CVT_W_S_MMR6 = 1083,
1099 : C_EQ_D32 = 1084,
1100 : C_EQ_D32_MM = 1085,
1101 : C_EQ_D64 = 1086,
1102 : C_EQ_D64_MM = 1087,
1103 : C_EQ_S = 1088,
1104 : C_EQ_S_MM = 1089,
1105 : C_F_D32 = 1090,
1106 : C_F_D32_MM = 1091,
1107 : C_F_D64 = 1092,
1108 : C_F_D64_MM = 1093,
1109 : C_F_S = 1094,
1110 : C_F_S_MM = 1095,
1111 : C_LE_D32 = 1096,
1112 : C_LE_D32_MM = 1097,
1113 : C_LE_D64 = 1098,
1114 : C_LE_D64_MM = 1099,
1115 : C_LE_S = 1100,
1116 : C_LE_S_MM = 1101,
1117 : C_LT_D32 = 1102,
1118 : C_LT_D32_MM = 1103,
1119 : C_LT_D64 = 1104,
1120 : C_LT_D64_MM = 1105,
1121 : C_LT_S = 1106,
1122 : C_LT_S_MM = 1107,
1123 : C_NGE_D32 = 1108,
1124 : C_NGE_D32_MM = 1109,
1125 : C_NGE_D64 = 1110,
1126 : C_NGE_D64_MM = 1111,
1127 : C_NGE_S = 1112,
1128 : C_NGE_S_MM = 1113,
1129 : C_NGLE_D32 = 1114,
1130 : C_NGLE_D32_MM = 1115,
1131 : C_NGLE_D64 = 1116,
1132 : C_NGLE_D64_MM = 1117,
1133 : C_NGLE_S = 1118,
1134 : C_NGLE_S_MM = 1119,
1135 : C_NGL_D32 = 1120,
1136 : C_NGL_D32_MM = 1121,
1137 : C_NGL_D64 = 1122,
1138 : C_NGL_D64_MM = 1123,
1139 : C_NGL_S = 1124,
1140 : C_NGL_S_MM = 1125,
1141 : C_NGT_D32 = 1126,
1142 : C_NGT_D32_MM = 1127,
1143 : C_NGT_D64 = 1128,
1144 : C_NGT_D64_MM = 1129,
1145 : C_NGT_S = 1130,
1146 : C_NGT_S_MM = 1131,
1147 : C_OLE_D32 = 1132,
1148 : C_OLE_D32_MM = 1133,
1149 : C_OLE_D64 = 1134,
1150 : C_OLE_D64_MM = 1135,
1151 : C_OLE_S = 1136,
1152 : C_OLE_S_MM = 1137,
1153 : C_OLT_D32 = 1138,
1154 : C_OLT_D32_MM = 1139,
1155 : C_OLT_D64 = 1140,
1156 : C_OLT_D64_MM = 1141,
1157 : C_OLT_S = 1142,
1158 : C_OLT_S_MM = 1143,
1159 : C_SEQ_D32 = 1144,
1160 : C_SEQ_D32_MM = 1145,
1161 : C_SEQ_D64 = 1146,
1162 : C_SEQ_D64_MM = 1147,
1163 : C_SEQ_S = 1148,
1164 : C_SEQ_S_MM = 1149,
1165 : C_SF_D32 = 1150,
1166 : C_SF_D32_MM = 1151,
1167 : C_SF_D64 = 1152,
1168 : C_SF_D64_MM = 1153,
1169 : C_SF_S = 1154,
1170 : C_SF_S_MM = 1155,
1171 : C_UEQ_D32 = 1156,
1172 : C_UEQ_D32_MM = 1157,
1173 : C_UEQ_D64 = 1158,
1174 : C_UEQ_D64_MM = 1159,
1175 : C_UEQ_S = 1160,
1176 : C_UEQ_S_MM = 1161,
1177 : C_ULE_D32 = 1162,
1178 : C_ULE_D32_MM = 1163,
1179 : C_ULE_D64 = 1164,
1180 : C_ULE_D64_MM = 1165,
1181 : C_ULE_S = 1166,
1182 : C_ULE_S_MM = 1167,
1183 : C_ULT_D32 = 1168,
1184 : C_ULT_D32_MM = 1169,
1185 : C_ULT_D64 = 1170,
1186 : C_ULT_D64_MM = 1171,
1187 : C_ULT_S = 1172,
1188 : C_ULT_S_MM = 1173,
1189 : C_UN_D32 = 1174,
1190 : C_UN_D32_MM = 1175,
1191 : C_UN_D64 = 1176,
1192 : C_UN_D64_MM = 1177,
1193 : C_UN_S = 1178,
1194 : C_UN_S_MM = 1179,
1195 : CmpRxRy16 = 1180,
1196 : CmpiRxImm16 = 1181,
1197 : CmpiRxImmX16 = 1182,
1198 : DADD = 1183,
1199 : DADDi = 1184,
1200 : DADDiu = 1185,
1201 : DADDu = 1186,
1202 : DAHI = 1187,
1203 : DALIGN = 1188,
1204 : DATI = 1189,
1205 : DAUI = 1190,
1206 : DBITSWAP = 1191,
1207 : DCLO = 1192,
1208 : DCLO_R6 = 1193,
1209 : DCLZ = 1194,
1210 : DCLZ_R6 = 1195,
1211 : DDIV = 1196,
1212 : DDIVU = 1197,
1213 : DERET = 1198,
1214 : DERET_MM = 1199,
1215 : DERET_MMR6 = 1200,
1216 : DEXT = 1201,
1217 : DEXT64_32 = 1202,
1218 : DEXTM = 1203,
1219 : DEXTU = 1204,
1220 : DI = 1205,
1221 : DINS = 1206,
1222 : DINSM = 1207,
1223 : DINSU = 1208,
1224 : DIV = 1209,
1225 : DIVU = 1210,
1226 : DIVU_MMR6 = 1211,
1227 : DIV_MMR6 = 1212,
1228 : DIV_S_B = 1213,
1229 : DIV_S_D = 1214,
1230 : DIV_S_H = 1215,
1231 : DIV_S_W = 1216,
1232 : DIV_U_B = 1217,
1233 : DIV_U_D = 1218,
1234 : DIV_U_H = 1219,
1235 : DIV_U_W = 1220,
1236 : DI_MM = 1221,
1237 : DI_MMR6 = 1222,
1238 : DLSA = 1223,
1239 : DLSA_R6 = 1224,
1240 : DMFC0 = 1225,
1241 : DMFC1 = 1226,
1242 : DMFC2 = 1227,
1243 : DMFC2_OCTEON = 1228,
1244 : DMFGC0 = 1229,
1245 : DMOD = 1230,
1246 : DMODU = 1231,
1247 : DMT = 1232,
1248 : DMTC0 = 1233,
1249 : DMTC1 = 1234,
1250 : DMTC2 = 1235,
1251 : DMTC2_OCTEON = 1236,
1252 : DMTGC0 = 1237,
1253 : DMUH = 1238,
1254 : DMUHU = 1239,
1255 : DMUL = 1240,
1256 : DMULT = 1241,
1257 : DMULTu = 1242,
1258 : DMULU = 1243,
1259 : DMUL_R6 = 1244,
1260 : DOTP_S_D = 1245,
1261 : DOTP_S_H = 1246,
1262 : DOTP_S_W = 1247,
1263 : DOTP_U_D = 1248,
1264 : DOTP_U_H = 1249,
1265 : DOTP_U_W = 1250,
1266 : DPADD_S_D = 1251,
1267 : DPADD_S_H = 1252,
1268 : DPADD_S_W = 1253,
1269 : DPADD_U_D = 1254,
1270 : DPADD_U_H = 1255,
1271 : DPADD_U_W = 1256,
1272 : DPAQX_SA_W_PH = 1257,
1273 : DPAQX_SA_W_PH_MMR2 = 1258,
1274 : DPAQX_S_W_PH = 1259,
1275 : DPAQX_S_W_PH_MMR2 = 1260,
1276 : DPAQ_SA_L_W = 1261,
1277 : DPAQ_SA_L_W_MM = 1262,
1278 : DPAQ_S_W_PH = 1263,
1279 : DPAQ_S_W_PH_MM = 1264,
1280 : DPAU_H_QBL = 1265,
1281 : DPAU_H_QBL_MM = 1266,
1282 : DPAU_H_QBR = 1267,
1283 : DPAU_H_QBR_MM = 1268,
1284 : DPAX_W_PH = 1269,
1285 : DPAX_W_PH_MMR2 = 1270,
1286 : DPA_W_PH = 1271,
1287 : DPA_W_PH_MMR2 = 1272,
1288 : DPOP = 1273,
1289 : DPSQX_SA_W_PH = 1274,
1290 : DPSQX_SA_W_PH_MMR2 = 1275,
1291 : DPSQX_S_W_PH = 1276,
1292 : DPSQX_S_W_PH_MMR2 = 1277,
1293 : DPSQ_SA_L_W = 1278,
1294 : DPSQ_SA_L_W_MM = 1279,
1295 : DPSQ_S_W_PH = 1280,
1296 : DPSQ_S_W_PH_MM = 1281,
1297 : DPSUB_S_D = 1282,
1298 : DPSUB_S_H = 1283,
1299 : DPSUB_S_W = 1284,
1300 : DPSUB_U_D = 1285,
1301 : DPSUB_U_H = 1286,
1302 : DPSUB_U_W = 1287,
1303 : DPSU_H_QBL = 1288,
1304 : DPSU_H_QBL_MM = 1289,
1305 : DPSU_H_QBR = 1290,
1306 : DPSU_H_QBR_MM = 1291,
1307 : DPSX_W_PH = 1292,
1308 : DPSX_W_PH_MMR2 = 1293,
1309 : DPS_W_PH = 1294,
1310 : DPS_W_PH_MMR2 = 1295,
1311 : DROTR = 1296,
1312 : DROTR32 = 1297,
1313 : DROTRV = 1298,
1314 : DSBH = 1299,
1315 : DSDIV = 1300,
1316 : DSHD = 1301,
1317 : DSLL = 1302,
1318 : DSLL32 = 1303,
1319 : DSLL64_32 = 1304,
1320 : DSLLV = 1305,
1321 : DSRA = 1306,
1322 : DSRA32 = 1307,
1323 : DSRAV = 1308,
1324 : DSRL = 1309,
1325 : DSRL32 = 1310,
1326 : DSRLV = 1311,
1327 : DSUB = 1312,
1328 : DSUBu = 1313,
1329 : DUDIV = 1314,
1330 : DVP = 1315,
1331 : DVPE = 1316,
1332 : DVP_MMR6 = 1317,
1333 : DivRxRy16 = 1318,
1334 : DivuRxRy16 = 1319,
1335 : EHB = 1320,
1336 : EHB_MM = 1321,
1337 : EHB_MMR6 = 1322,
1338 : EI = 1323,
1339 : EI_MM = 1324,
1340 : EI_MMR6 = 1325,
1341 : EMT = 1326,
1342 : ERET = 1327,
1343 : ERETNC = 1328,
1344 : ERETNC_MMR6 = 1329,
1345 : ERET_MM = 1330,
1346 : ERET_MMR6 = 1331,
1347 : EVP = 1332,
1348 : EVPE = 1333,
1349 : EVP_MMR6 = 1334,
1350 : EXT = 1335,
1351 : EXTP = 1336,
1352 : EXTPDP = 1337,
1353 : EXTPDPV = 1338,
1354 : EXTPDPV_MM = 1339,
1355 : EXTPDP_MM = 1340,
1356 : EXTPV = 1341,
1357 : EXTPV_MM = 1342,
1358 : EXTP_MM = 1343,
1359 : EXTRV_RS_W = 1344,
1360 : EXTRV_RS_W_MM = 1345,
1361 : EXTRV_R_W = 1346,
1362 : EXTRV_R_W_MM = 1347,
1363 : EXTRV_S_H = 1348,
1364 : EXTRV_S_H_MM = 1349,
1365 : EXTRV_W = 1350,
1366 : EXTRV_W_MM = 1351,
1367 : EXTR_RS_W = 1352,
1368 : EXTR_RS_W_MM = 1353,
1369 : EXTR_R_W = 1354,
1370 : EXTR_R_W_MM = 1355,
1371 : EXTR_S_H = 1356,
1372 : EXTR_S_H_MM = 1357,
1373 : EXTR_W = 1358,
1374 : EXTR_W_MM = 1359,
1375 : EXTS = 1360,
1376 : EXTS32 = 1361,
1377 : EXT_MM = 1362,
1378 : EXT_MMR6 = 1363,
1379 : FABS_D32 = 1364,
1380 : FABS_D32_MM = 1365,
1381 : FABS_D64 = 1366,
1382 : FABS_D64_MM = 1367,
1383 : FABS_S = 1368,
1384 : FABS_S_MM = 1369,
1385 : FADD_D = 1370,
1386 : FADD_D32 = 1371,
1387 : FADD_D32_MM = 1372,
1388 : FADD_D64 = 1373,
1389 : FADD_D64_MM = 1374,
1390 : FADD_S = 1375,
1391 : FADD_S_MM = 1376,
1392 : FADD_S_MMR6 = 1377,
1393 : FADD_W = 1378,
1394 : FCAF_D = 1379,
1395 : FCAF_W = 1380,
1396 : FCEQ_D = 1381,
1397 : FCEQ_W = 1382,
1398 : FCLASS_D = 1383,
1399 : FCLASS_W = 1384,
1400 : FCLE_D = 1385,
1401 : FCLE_W = 1386,
1402 : FCLT_D = 1387,
1403 : FCLT_W = 1388,
1404 : FCMP_D32 = 1389,
1405 : FCMP_D32_MM = 1390,
1406 : FCMP_D64 = 1391,
1407 : FCMP_S32 = 1392,
1408 : FCMP_S32_MM = 1393,
1409 : FCNE_D = 1394,
1410 : FCNE_W = 1395,
1411 : FCOR_D = 1396,
1412 : FCOR_W = 1397,
1413 : FCUEQ_D = 1398,
1414 : FCUEQ_W = 1399,
1415 : FCULE_D = 1400,
1416 : FCULE_W = 1401,
1417 : FCULT_D = 1402,
1418 : FCULT_W = 1403,
1419 : FCUNE_D = 1404,
1420 : FCUNE_W = 1405,
1421 : FCUN_D = 1406,
1422 : FCUN_W = 1407,
1423 : FDIV_D = 1408,
1424 : FDIV_D32 = 1409,
1425 : FDIV_D32_MM = 1410,
1426 : FDIV_D64 = 1411,
1427 : FDIV_D64_MM = 1412,
1428 : FDIV_S = 1413,
1429 : FDIV_S_MM = 1414,
1430 : FDIV_S_MMR6 = 1415,
1431 : FDIV_W = 1416,
1432 : FEXDO_H = 1417,
1433 : FEXDO_W = 1418,
1434 : FEXP2_D = 1419,
1435 : FEXP2_W = 1420,
1436 : FEXUPL_D = 1421,
1437 : FEXUPL_W = 1422,
1438 : FEXUPR_D = 1423,
1439 : FEXUPR_W = 1424,
1440 : FFINT_S_D = 1425,
1441 : FFINT_S_W = 1426,
1442 : FFINT_U_D = 1427,
1443 : FFINT_U_W = 1428,
1444 : FFQL_D = 1429,
1445 : FFQL_W = 1430,
1446 : FFQR_D = 1431,
1447 : FFQR_W = 1432,
1448 : FILL_B = 1433,
1449 : FILL_D = 1434,
1450 : FILL_H = 1435,
1451 : FILL_W = 1436,
1452 : FLOG2_D = 1437,
1453 : FLOG2_W = 1438,
1454 : FLOOR_L_D64 = 1439,
1455 : FLOOR_L_D_MMR6 = 1440,
1456 : FLOOR_L_S = 1441,
1457 : FLOOR_L_S_MMR6 = 1442,
1458 : FLOOR_W_D32 = 1443,
1459 : FLOOR_W_D64 = 1444,
1460 : FLOOR_W_D_MMR6 = 1445,
1461 : FLOOR_W_MM = 1446,
1462 : FLOOR_W_S = 1447,
1463 : FLOOR_W_S_MM = 1448,
1464 : FLOOR_W_S_MMR6 = 1449,
1465 : FMADD_D = 1450,
1466 : FMADD_W = 1451,
1467 : FMAX_A_D = 1452,
1468 : FMAX_A_W = 1453,
1469 : FMAX_D = 1454,
1470 : FMAX_W = 1455,
1471 : FMIN_A_D = 1456,
1472 : FMIN_A_W = 1457,
1473 : FMIN_D = 1458,
1474 : FMIN_W = 1459,
1475 : FMOV_D32 = 1460,
1476 : FMOV_D32_MM = 1461,
1477 : FMOV_D64 = 1462,
1478 : FMOV_D64_MM = 1463,
1479 : FMOV_S = 1464,
1480 : FMOV_S_MM = 1465,
1481 : FMOV_S_MMR6 = 1466,
1482 : FMSUB_D = 1467,
1483 : FMSUB_W = 1468,
1484 : FMUL_D = 1469,
1485 : FMUL_D32 = 1470,
1486 : FMUL_D32_MM = 1471,
1487 : FMUL_D64 = 1472,
1488 : FMUL_D64_MM = 1473,
1489 : FMUL_S = 1474,
1490 : FMUL_S_MM = 1475,
1491 : FMUL_S_MMR6 = 1476,
1492 : FMUL_W = 1477,
1493 : FNEG_D32 = 1478,
1494 : FNEG_D32_MM = 1479,
1495 : FNEG_D64 = 1480,
1496 : FNEG_D64_MM = 1481,
1497 : FNEG_S = 1482,
1498 : FNEG_S_MM = 1483,
1499 : FNEG_S_MMR6 = 1484,
1500 : FORK = 1485,
1501 : FRCP_D = 1486,
1502 : FRCP_W = 1487,
1503 : FRINT_D = 1488,
1504 : FRINT_W = 1489,
1505 : FRSQRT_D = 1490,
1506 : FRSQRT_W = 1491,
1507 : FSAF_D = 1492,
1508 : FSAF_W = 1493,
1509 : FSEQ_D = 1494,
1510 : FSEQ_W = 1495,
1511 : FSLE_D = 1496,
1512 : FSLE_W = 1497,
1513 : FSLT_D = 1498,
1514 : FSLT_W = 1499,
1515 : FSNE_D = 1500,
1516 : FSNE_W = 1501,
1517 : FSOR_D = 1502,
1518 : FSOR_W = 1503,
1519 : FSQRT_D = 1504,
1520 : FSQRT_D32 = 1505,
1521 : FSQRT_D32_MM = 1506,
1522 : FSQRT_D64 = 1507,
1523 : FSQRT_D64_MM = 1508,
1524 : FSQRT_S = 1509,
1525 : FSQRT_S_MM = 1510,
1526 : FSQRT_W = 1511,
1527 : FSUB_D = 1512,
1528 : FSUB_D32 = 1513,
1529 : FSUB_D32_MM = 1514,
1530 : FSUB_D64 = 1515,
1531 : FSUB_D64_MM = 1516,
1532 : FSUB_S = 1517,
1533 : FSUB_S_MM = 1518,
1534 : FSUB_S_MMR6 = 1519,
1535 : FSUB_W = 1520,
1536 : FSUEQ_D = 1521,
1537 : FSUEQ_W = 1522,
1538 : FSULE_D = 1523,
1539 : FSULE_W = 1524,
1540 : FSULT_D = 1525,
1541 : FSULT_W = 1526,
1542 : FSUNE_D = 1527,
1543 : FSUNE_W = 1528,
1544 : FSUN_D = 1529,
1545 : FSUN_W = 1530,
1546 : FTINT_S_D = 1531,
1547 : FTINT_S_W = 1532,
1548 : FTINT_U_D = 1533,
1549 : FTINT_U_W = 1534,
1550 : FTQ_H = 1535,
1551 : FTQ_W = 1536,
1552 : FTRUNC_S_D = 1537,
1553 : FTRUNC_S_W = 1538,
1554 : FTRUNC_U_D = 1539,
1555 : FTRUNC_U_W = 1540,
1556 : GINVI = 1541,
1557 : GINVI_MMR6 = 1542,
1558 : GINVT = 1543,
1559 : GINVT_MMR6 = 1544,
1560 : HADD_S_D = 1545,
1561 : HADD_S_H = 1546,
1562 : HADD_S_W = 1547,
1563 : HADD_U_D = 1548,
1564 : HADD_U_H = 1549,
1565 : HADD_U_W = 1550,
1566 : HSUB_S_D = 1551,
1567 : HSUB_S_H = 1552,
1568 : HSUB_S_W = 1553,
1569 : HSUB_U_D = 1554,
1570 : HSUB_U_H = 1555,
1571 : HSUB_U_W = 1556,
1572 : HYPCALL = 1557,
1573 : HYPCALL_MM = 1558,
1574 : ILVEV_B = 1559,
1575 : ILVEV_D = 1560,
1576 : ILVEV_H = 1561,
1577 : ILVEV_W = 1562,
1578 : ILVL_B = 1563,
1579 : ILVL_D = 1564,
1580 : ILVL_H = 1565,
1581 : ILVL_W = 1566,
1582 : ILVOD_B = 1567,
1583 : ILVOD_D = 1568,
1584 : ILVOD_H = 1569,
1585 : ILVOD_W = 1570,
1586 : ILVR_B = 1571,
1587 : ILVR_D = 1572,
1588 : ILVR_H = 1573,
1589 : ILVR_W = 1574,
1590 : INS = 1575,
1591 : INSERT_B = 1576,
1592 : INSERT_D = 1577,
1593 : INSERT_H = 1578,
1594 : INSERT_W = 1579,
1595 : INSV = 1580,
1596 : INSVE_B = 1581,
1597 : INSVE_D = 1582,
1598 : INSVE_H = 1583,
1599 : INSVE_W = 1584,
1600 : INSV_MM = 1585,
1601 : INS_MM = 1586,
1602 : INS_MMR6 = 1587,
1603 : J = 1588,
1604 : JAL = 1589,
1605 : JALR = 1590,
1606 : JALR16_MM = 1591,
1607 : JALR64 = 1592,
1608 : JALRC16_MMR6 = 1593,
1609 : JALRC_HB_MMR6 = 1594,
1610 : JALRC_MMR6 = 1595,
1611 : JALRS16_MM = 1596,
1612 : JALRS_MM = 1597,
1613 : JALR_HB = 1598,
1614 : JALR_HB64 = 1599,
1615 : JALR_MM = 1600,
1616 : JALS_MM = 1601,
1617 : JALX = 1602,
1618 : JALX_MM = 1603,
1619 : JAL_MM = 1604,
1620 : JIALC = 1605,
1621 : JIALC64 = 1606,
1622 : JIALC_MMR6 = 1607,
1623 : JIC = 1608,
1624 : JIC64 = 1609,
1625 : JIC_MMR6 = 1610,
1626 : JR = 1611,
1627 : JR16_MM = 1612,
1628 : JR64 = 1613,
1629 : JRADDIUSP = 1614,
1630 : JRC16_MM = 1615,
1631 : JRC16_MMR6 = 1616,
1632 : JRCADDIUSP_MMR6 = 1617,
1633 : JR_HB = 1618,
1634 : JR_HB64 = 1619,
1635 : JR_HB64_R6 = 1620,
1636 : JR_HB_R6 = 1621,
1637 : JR_MM = 1622,
1638 : J_MM = 1623,
1639 : Jal16 = 1624,
1640 : JalB16 = 1625,
1641 : JrRa16 = 1626,
1642 : JrcRa16 = 1627,
1643 : JrcRx16 = 1628,
1644 : JumpLinkReg16 = 1629,
1645 : LB = 1630,
1646 : LB64 = 1631,
1647 : LBE = 1632,
1648 : LBE_MM = 1633,
1649 : LBU16_MM = 1634,
1650 : LBUX = 1635,
1651 : LBUX_MM = 1636,
1652 : LBU_MMR6 = 1637,
1653 : LB_MM = 1638,
1654 : LB_MMR6 = 1639,
1655 : LBu = 1640,
1656 : LBu64 = 1641,
1657 : LBuE = 1642,
1658 : LBuE_MM = 1643,
1659 : LBu_MM = 1644,
1660 : LD = 1645,
1661 : LDC1 = 1646,
1662 : LDC164 = 1647,
1663 : LDC1_D64_MMR6 = 1648,
1664 : LDC1_MM = 1649,
1665 : LDC2 = 1650,
1666 : LDC2_MMR6 = 1651,
1667 : LDC2_R6 = 1652,
1668 : LDC3 = 1653,
1669 : LDI_B = 1654,
1670 : LDI_D = 1655,
1671 : LDI_H = 1656,
1672 : LDI_W = 1657,
1673 : LDL = 1658,
1674 : LDPC = 1659,
1675 : LDR = 1660,
1676 : LDXC1 = 1661,
1677 : LDXC164 = 1662,
1678 : LD_B = 1663,
1679 : LD_D = 1664,
1680 : LD_H = 1665,
1681 : LD_W = 1666,
1682 : LEA_ADDiu = 1667,
1683 : LEA_ADDiu64 = 1668,
1684 : LEA_ADDiu_MM = 1669,
1685 : LH = 1670,
1686 : LH64 = 1671,
1687 : LHE = 1672,
1688 : LHE_MM = 1673,
1689 : LHU16_MM = 1674,
1690 : LHX = 1675,
1691 : LHX_MM = 1676,
1692 : LH_MM = 1677,
1693 : LHu = 1678,
1694 : LHu64 = 1679,
1695 : LHuE = 1680,
1696 : LHuE_MM = 1681,
1697 : LHu_MM = 1682,
1698 : LI16_MM = 1683,
1699 : LI16_MMR6 = 1684,
1700 : LL = 1685,
1701 : LL64 = 1686,
1702 : LL64_R6 = 1687,
1703 : LLD = 1688,
1704 : LLD_R6 = 1689,
1705 : LLE = 1690,
1706 : LLE_MM = 1691,
1707 : LL_MM = 1692,
1708 : LL_MMR6 = 1693,
1709 : LL_R6 = 1694,
1710 : LSA = 1695,
1711 : LSA_MMR6 = 1696,
1712 : LSA_R6 = 1697,
1713 : LUI_MMR6 = 1698,
1714 : LUXC1 = 1699,
1715 : LUXC164 = 1700,
1716 : LUXC1_MM = 1701,
1717 : LUi = 1702,
1718 : LUi64 = 1703,
1719 : LUi_MM = 1704,
1720 : LW = 1705,
1721 : LW16_MM = 1706,
1722 : LW64 = 1707,
1723 : LWC1 = 1708,
1724 : LWC1_MM = 1709,
1725 : LWC2 = 1710,
1726 : LWC2_MMR6 = 1711,
1727 : LWC2_R6 = 1712,
1728 : LWC3 = 1713,
1729 : LWDSP = 1714,
1730 : LWDSP_MM = 1715,
1731 : LWE = 1716,
1732 : LWE_MM = 1717,
1733 : LWGP_MM = 1718,
1734 : LWL = 1719,
1735 : LWL64 = 1720,
1736 : LWLE = 1721,
1737 : LWLE_MM = 1722,
1738 : LWL_MM = 1723,
1739 : LWM16_MM = 1724,
1740 : LWM16_MMR6 = 1725,
1741 : LWM32_MM = 1726,
1742 : LWPC = 1727,
1743 : LWPC_MMR6 = 1728,
1744 : LWP_MM = 1729,
1745 : LWR = 1730,
1746 : LWR64 = 1731,
1747 : LWRE = 1732,
1748 : LWRE_MM = 1733,
1749 : LWR_MM = 1734,
1750 : LWSP_MM = 1735,
1751 : LWUPC = 1736,
1752 : LWU_MM = 1737,
1753 : LWX = 1738,
1754 : LWXC1 = 1739,
1755 : LWXC1_MM = 1740,
1756 : LWXS_MM = 1741,
1757 : LWX_MM = 1742,
1758 : LW_MM = 1743,
1759 : LW_MMR6 = 1744,
1760 : LWu = 1745,
1761 : LbRxRyOffMemX16 = 1746,
1762 : LbuRxRyOffMemX16 = 1747,
1763 : LhRxRyOffMemX16 = 1748,
1764 : LhuRxRyOffMemX16 = 1749,
1765 : LiRxImm16 = 1750,
1766 : LiRxImmAlignX16 = 1751,
1767 : LiRxImmX16 = 1752,
1768 : LwRxPcTcp16 = 1753,
1769 : LwRxPcTcpX16 = 1754,
1770 : LwRxRyOffMemX16 = 1755,
1771 : LwRxSpImmX16 = 1756,
1772 : MADD = 1757,
1773 : MADDF_D = 1758,
1774 : MADDF_D_MMR6 = 1759,
1775 : MADDF_S = 1760,
1776 : MADDF_S_MMR6 = 1761,
1777 : MADDR_Q_H = 1762,
1778 : MADDR_Q_W = 1763,
1779 : MADDU = 1764,
1780 : MADDU_DSP = 1765,
1781 : MADDU_DSP_MM = 1766,
1782 : MADDU_MM = 1767,
1783 : MADDV_B = 1768,
1784 : MADDV_D = 1769,
1785 : MADDV_H = 1770,
1786 : MADDV_W = 1771,
1787 : MADD_D32 = 1772,
1788 : MADD_D32_MM = 1773,
1789 : MADD_D64 = 1774,
1790 : MADD_DSP = 1775,
1791 : MADD_DSP_MM = 1776,
1792 : MADD_MM = 1777,
1793 : MADD_Q_H = 1778,
1794 : MADD_Q_W = 1779,
1795 : MADD_S = 1780,
1796 : MADD_S_MM = 1781,
1797 : MAQ_SA_W_PHL = 1782,
1798 : MAQ_SA_W_PHL_MM = 1783,
1799 : MAQ_SA_W_PHR = 1784,
1800 : MAQ_SA_W_PHR_MM = 1785,
1801 : MAQ_S_W_PHL = 1786,
1802 : MAQ_S_W_PHL_MM = 1787,
1803 : MAQ_S_W_PHR = 1788,
1804 : MAQ_S_W_PHR_MM = 1789,
1805 : MAXA_D = 1790,
1806 : MAXA_D_MMR6 = 1791,
1807 : MAXA_S = 1792,
1808 : MAXA_S_MMR6 = 1793,
1809 : MAXI_S_B = 1794,
1810 : MAXI_S_D = 1795,
1811 : MAXI_S_H = 1796,
1812 : MAXI_S_W = 1797,
1813 : MAXI_U_B = 1798,
1814 : MAXI_U_D = 1799,
1815 : MAXI_U_H = 1800,
1816 : MAXI_U_W = 1801,
1817 : MAX_A_B = 1802,
1818 : MAX_A_D = 1803,
1819 : MAX_A_H = 1804,
1820 : MAX_A_W = 1805,
1821 : MAX_D = 1806,
1822 : MAX_D_MMR6 = 1807,
1823 : MAX_S = 1808,
1824 : MAX_S_B = 1809,
1825 : MAX_S_D = 1810,
1826 : MAX_S_H = 1811,
1827 : MAX_S_MMR6 = 1812,
1828 : MAX_S_W = 1813,
1829 : MAX_U_B = 1814,
1830 : MAX_U_D = 1815,
1831 : MAX_U_H = 1816,
1832 : MAX_U_W = 1817,
1833 : MFC0 = 1818,
1834 : MFC0_MMR6 = 1819,
1835 : MFC1 = 1820,
1836 : MFC1_D64 = 1821,
1837 : MFC1_MM = 1822,
1838 : MFC1_MMR6 = 1823,
1839 : MFC2 = 1824,
1840 : MFC2_MMR6 = 1825,
1841 : MFGC0 = 1826,
1842 : MFGC0_MM = 1827,
1843 : MFHC0_MMR6 = 1828,
1844 : MFHC1_D32 = 1829,
1845 : MFHC1_D32_MM = 1830,
1846 : MFHC1_D64 = 1831,
1847 : MFHC1_D64_MM = 1832,
1848 : MFHC2_MMR6 = 1833,
1849 : MFHGC0 = 1834,
1850 : MFHGC0_MM = 1835,
1851 : MFHI = 1836,
1852 : MFHI16_MM = 1837,
1853 : MFHI64 = 1838,
1854 : MFHI_DSP = 1839,
1855 : MFHI_DSP_MM = 1840,
1856 : MFHI_MM = 1841,
1857 : MFLO = 1842,
1858 : MFLO16_MM = 1843,
1859 : MFLO64 = 1844,
1860 : MFLO_DSP = 1845,
1861 : MFLO_DSP_MM = 1846,
1862 : MFLO_MM = 1847,
1863 : MFTR = 1848,
1864 : MINA_D = 1849,
1865 : MINA_D_MMR6 = 1850,
1866 : MINA_S = 1851,
1867 : MINA_S_MMR6 = 1852,
1868 : MINI_S_B = 1853,
1869 : MINI_S_D = 1854,
1870 : MINI_S_H = 1855,
1871 : MINI_S_W = 1856,
1872 : MINI_U_B = 1857,
1873 : MINI_U_D = 1858,
1874 : MINI_U_H = 1859,
1875 : MINI_U_W = 1860,
1876 : MIN_A_B = 1861,
1877 : MIN_A_D = 1862,
1878 : MIN_A_H = 1863,
1879 : MIN_A_W = 1864,
1880 : MIN_D = 1865,
1881 : MIN_D_MMR6 = 1866,
1882 : MIN_S = 1867,
1883 : MIN_S_B = 1868,
1884 : MIN_S_D = 1869,
1885 : MIN_S_H = 1870,
1886 : MIN_S_MMR6 = 1871,
1887 : MIN_S_W = 1872,
1888 : MIN_U_B = 1873,
1889 : MIN_U_D = 1874,
1890 : MIN_U_H = 1875,
1891 : MIN_U_W = 1876,
1892 : MOD = 1877,
1893 : MODSUB = 1878,
1894 : MODSUB_MM = 1879,
1895 : MODU = 1880,
1896 : MODU_MMR6 = 1881,
1897 : MOD_MMR6 = 1882,
1898 : MOD_S_B = 1883,
1899 : MOD_S_D = 1884,
1900 : MOD_S_H = 1885,
1901 : MOD_S_W = 1886,
1902 : MOD_U_B = 1887,
1903 : MOD_U_D = 1888,
1904 : MOD_U_H = 1889,
1905 : MOD_U_W = 1890,
1906 : MOVE16_MM = 1891,
1907 : MOVE16_MMR6 = 1892,
1908 : MOVEP_MM = 1893,
1909 : MOVEP_MMR6 = 1894,
1910 : MOVE_V = 1895,
1911 : MOVF_D32 = 1896,
1912 : MOVF_D32_MM = 1897,
1913 : MOVF_D64 = 1898,
1914 : MOVF_I = 1899,
1915 : MOVF_I64 = 1900,
1916 : MOVF_I_MM = 1901,
1917 : MOVF_S = 1902,
1918 : MOVF_S_MM = 1903,
1919 : MOVN_I64_D64 = 1904,
1920 : MOVN_I64_I = 1905,
1921 : MOVN_I64_I64 = 1906,
1922 : MOVN_I64_S = 1907,
1923 : MOVN_I_D32 = 1908,
1924 : MOVN_I_D32_MM = 1909,
1925 : MOVN_I_D64 = 1910,
1926 : MOVN_I_I = 1911,
1927 : MOVN_I_I64 = 1912,
1928 : MOVN_I_MM = 1913,
1929 : MOVN_I_S = 1914,
1930 : MOVN_I_S_MM = 1915,
1931 : MOVT_D32 = 1916,
1932 : MOVT_D32_MM = 1917,
1933 : MOVT_D64 = 1918,
1934 : MOVT_I = 1919,
1935 : MOVT_I64 = 1920,
1936 : MOVT_I_MM = 1921,
1937 : MOVT_S = 1922,
1938 : MOVT_S_MM = 1923,
1939 : MOVZ_I64_D64 = 1924,
1940 : MOVZ_I64_I = 1925,
1941 : MOVZ_I64_I64 = 1926,
1942 : MOVZ_I64_S = 1927,
1943 : MOVZ_I_D32 = 1928,
1944 : MOVZ_I_D32_MM = 1929,
1945 : MOVZ_I_D64 = 1930,
1946 : MOVZ_I_I = 1931,
1947 : MOVZ_I_I64 = 1932,
1948 : MOVZ_I_MM = 1933,
1949 : MOVZ_I_S = 1934,
1950 : MOVZ_I_S_MM = 1935,
1951 : MSUB = 1936,
1952 : MSUBF_D = 1937,
1953 : MSUBF_D_MMR6 = 1938,
1954 : MSUBF_S = 1939,
1955 : MSUBF_S_MMR6 = 1940,
1956 : MSUBR_Q_H = 1941,
1957 : MSUBR_Q_W = 1942,
1958 : MSUBU = 1943,
1959 : MSUBU_DSP = 1944,
1960 : MSUBU_DSP_MM = 1945,
1961 : MSUBU_MM = 1946,
1962 : MSUBV_B = 1947,
1963 : MSUBV_D = 1948,
1964 : MSUBV_H = 1949,
1965 : MSUBV_W = 1950,
1966 : MSUB_D32 = 1951,
1967 : MSUB_D32_MM = 1952,
1968 : MSUB_D64 = 1953,
1969 : MSUB_DSP = 1954,
1970 : MSUB_DSP_MM = 1955,
1971 : MSUB_MM = 1956,
1972 : MSUB_Q_H = 1957,
1973 : MSUB_Q_W = 1958,
1974 : MSUB_S = 1959,
1975 : MSUB_S_MM = 1960,
1976 : MTC0 = 1961,
1977 : MTC0_MMR6 = 1962,
1978 : MTC1 = 1963,
1979 : MTC1_D64 = 1964,
1980 : MTC1_D64_MM = 1965,
1981 : MTC1_MM = 1966,
1982 : MTC1_MMR6 = 1967,
1983 : MTC2 = 1968,
1984 : MTC2_MMR6 = 1969,
1985 : MTGC0 = 1970,
1986 : MTGC0_MM = 1971,
1987 : MTHC0_MMR6 = 1972,
1988 : MTHC1_D32 = 1973,
1989 : MTHC1_D32_MM = 1974,
1990 : MTHC1_D64 = 1975,
1991 : MTHC1_D64_MM = 1976,
1992 : MTHC2_MMR6 = 1977,
1993 : MTHGC0 = 1978,
1994 : MTHGC0_MM = 1979,
1995 : MTHI = 1980,
1996 : MTHI64 = 1981,
1997 : MTHI_DSP = 1982,
1998 : MTHI_DSP_MM = 1983,
1999 : MTHI_MM = 1984,
2000 : MTHLIP = 1985,
2001 : MTHLIP_MM = 1986,
2002 : MTLO = 1987,
2003 : MTLO64 = 1988,
2004 : MTLO_DSP = 1989,
2005 : MTLO_DSP_MM = 1990,
2006 : MTLO_MM = 1991,
2007 : MTM0 = 1992,
2008 : MTM1 = 1993,
2009 : MTM2 = 1994,
2010 : MTP0 = 1995,
2011 : MTP1 = 1996,
2012 : MTP2 = 1997,
2013 : MTTR = 1998,
2014 : MUH = 1999,
2015 : MUHU = 2000,
2016 : MUHU_MMR6 = 2001,
2017 : MUH_MMR6 = 2002,
2018 : MUL = 2003,
2019 : MULEQ_S_W_PHL = 2004,
2020 : MULEQ_S_W_PHL_MM = 2005,
2021 : MULEQ_S_W_PHR = 2006,
2022 : MULEQ_S_W_PHR_MM = 2007,
2023 : MULEU_S_PH_QBL = 2008,
2024 : MULEU_S_PH_QBL_MM = 2009,
2025 : MULEU_S_PH_QBR = 2010,
2026 : MULEU_S_PH_QBR_MM = 2011,
2027 : MULQ_RS_PH = 2012,
2028 : MULQ_RS_PH_MM = 2013,
2029 : MULQ_RS_W = 2014,
2030 : MULQ_RS_W_MMR2 = 2015,
2031 : MULQ_S_PH = 2016,
2032 : MULQ_S_PH_MMR2 = 2017,
2033 : MULQ_S_W = 2018,
2034 : MULQ_S_W_MMR2 = 2019,
2035 : MULR_Q_H = 2020,
2036 : MULR_Q_W = 2021,
2037 : MULSAQ_S_W_PH = 2022,
2038 : MULSAQ_S_W_PH_MM = 2023,
2039 : MULSA_W_PH = 2024,
2040 : MULSA_W_PH_MMR2 = 2025,
2041 : MULT = 2026,
2042 : MULTU_DSP = 2027,
2043 : MULTU_DSP_MM = 2028,
2044 : MULT_DSP = 2029,
2045 : MULT_DSP_MM = 2030,
2046 : MULT_MM = 2031,
2047 : MULTu = 2032,
2048 : MULTu_MM = 2033,
2049 : MULU = 2034,
2050 : MULU_MMR6 = 2035,
2051 : MULV_B = 2036,
2052 : MULV_D = 2037,
2053 : MULV_H = 2038,
2054 : MULV_W = 2039,
2055 : MUL_MM = 2040,
2056 : MUL_MMR6 = 2041,
2057 : MUL_PH = 2042,
2058 : MUL_PH_MMR2 = 2043,
2059 : MUL_Q_H = 2044,
2060 : MUL_Q_W = 2045,
2061 : MUL_R6 = 2046,
2062 : MUL_S_PH = 2047,
2063 : MUL_S_PH_MMR2 = 2048,
2064 : Mfhi16 = 2049,
2065 : Mflo16 = 2050,
2066 : Move32R16 = 2051,
2067 : MoveR3216 = 2052,
2068 : NLOC_B = 2053,
2069 : NLOC_D = 2054,
2070 : NLOC_H = 2055,
2071 : NLOC_W = 2056,
2072 : NLZC_B = 2057,
2073 : NLZC_D = 2058,
2074 : NLZC_H = 2059,
2075 : NLZC_W = 2060,
2076 : NMADD_D32 = 2061,
2077 : NMADD_D32_MM = 2062,
2078 : NMADD_D64 = 2063,
2079 : NMADD_S = 2064,
2080 : NMADD_S_MM = 2065,
2081 : NMSUB_D32 = 2066,
2082 : NMSUB_D32_MM = 2067,
2083 : NMSUB_D64 = 2068,
2084 : NMSUB_S = 2069,
2085 : NMSUB_S_MM = 2070,
2086 : NOR = 2071,
2087 : NOR64 = 2072,
2088 : NORI_B = 2073,
2089 : NOR_MM = 2074,
2090 : NOR_MMR6 = 2075,
2091 : NOR_V = 2076,
2092 : NOT16_MM = 2077,
2093 : NOT16_MMR6 = 2078,
2094 : NegRxRy16 = 2079,
2095 : NotRxRy16 = 2080,
2096 : OR = 2081,
2097 : OR16_MM = 2082,
2098 : OR16_MMR6 = 2083,
2099 : OR64 = 2084,
2100 : ORI_B = 2085,
2101 : ORI_MMR6 = 2086,
2102 : OR_MM = 2087,
2103 : OR_MMR6 = 2088,
2104 : OR_V = 2089,
2105 : ORi = 2090,
2106 : ORi64 = 2091,
2107 : ORi_MM = 2092,
2108 : OrRxRxRy16 = 2093,
2109 : PACKRL_PH = 2094,
2110 : PACKRL_PH_MM = 2095,
2111 : PAUSE = 2096,
2112 : PAUSE_MM = 2097,
2113 : PAUSE_MMR6 = 2098,
2114 : PCKEV_B = 2099,
2115 : PCKEV_D = 2100,
2116 : PCKEV_H = 2101,
2117 : PCKEV_W = 2102,
2118 : PCKOD_B = 2103,
2119 : PCKOD_D = 2104,
2120 : PCKOD_H = 2105,
2121 : PCKOD_W = 2106,
2122 : PCNT_B = 2107,
2123 : PCNT_D = 2108,
2124 : PCNT_H = 2109,
2125 : PCNT_W = 2110,
2126 : PICK_PH = 2111,
2127 : PICK_PH_MM = 2112,
2128 : PICK_QB = 2113,
2129 : PICK_QB_MM = 2114,
2130 : PLL_PS64 = 2115,
2131 : PLU_PS64 = 2116,
2132 : POP = 2117,
2133 : PRECEQU_PH_QBL = 2118,
2134 : PRECEQU_PH_QBLA = 2119,
2135 : PRECEQU_PH_QBLA_MM = 2120,
2136 : PRECEQU_PH_QBL_MM = 2121,
2137 : PRECEQU_PH_QBR = 2122,
2138 : PRECEQU_PH_QBRA = 2123,
2139 : PRECEQU_PH_QBRA_MM = 2124,
2140 : PRECEQU_PH_QBR_MM = 2125,
2141 : PRECEQ_W_PHL = 2126,
2142 : PRECEQ_W_PHL_MM = 2127,
2143 : PRECEQ_W_PHR = 2128,
2144 : PRECEQ_W_PHR_MM = 2129,
2145 : PRECEU_PH_QBL = 2130,
2146 : PRECEU_PH_QBLA = 2131,
2147 : PRECEU_PH_QBLA_MM = 2132,
2148 : PRECEU_PH_QBL_MM = 2133,
2149 : PRECEU_PH_QBR = 2134,
2150 : PRECEU_PH_QBRA = 2135,
2151 : PRECEU_PH_QBRA_MM = 2136,
2152 : PRECEU_PH_QBR_MM = 2137,
2153 : PRECRQU_S_QB_PH = 2138,
2154 : PRECRQU_S_QB_PH_MM = 2139,
2155 : PRECRQ_PH_W = 2140,
2156 : PRECRQ_PH_W_MM = 2141,
2157 : PRECRQ_QB_PH = 2142,
2158 : PRECRQ_QB_PH_MM = 2143,
2159 : PRECRQ_RS_PH_W = 2144,
2160 : PRECRQ_RS_PH_W_MM = 2145,
2161 : PRECR_QB_PH = 2146,
2162 : PRECR_QB_PH_MMR2 = 2147,
2163 : PRECR_SRA_PH_W = 2148,
2164 : PRECR_SRA_PH_W_MMR2 = 2149,
2165 : PRECR_SRA_R_PH_W = 2150,
2166 : PRECR_SRA_R_PH_W_MMR2 = 2151,
2167 : PREF = 2152,
2168 : PREFE = 2153,
2169 : PREFE_MM = 2154,
2170 : PREFX_MM = 2155,
2171 : PREF_MM = 2156,
2172 : PREF_MMR6 = 2157,
2173 : PREF_R6 = 2158,
2174 : PREPEND = 2159,
2175 : PREPEND_MMR2 = 2160,
2176 : RADDU_W_QB = 2161,
2177 : RADDU_W_QB_MM = 2162,
2178 : RDDSP = 2163,
2179 : RDDSP_MM = 2164,
2180 : RDHWR = 2165,
2181 : RDHWR64 = 2166,
2182 : RDHWR_MM = 2167,
2183 : RDHWR_MMR6 = 2168,
2184 : RDPGPR_MMR6 = 2169,
2185 : RECIP_D32 = 2170,
2186 : RECIP_D32_MM = 2171,
2187 : RECIP_D64 = 2172,
2188 : RECIP_D64_MM = 2173,
2189 : RECIP_S = 2174,
2190 : RECIP_S_MM = 2175,
2191 : REPLV_PH = 2176,
2192 : REPLV_PH_MM = 2177,
2193 : REPLV_QB = 2178,
2194 : REPLV_QB_MM = 2179,
2195 : REPL_PH = 2180,
2196 : REPL_PH_MM = 2181,
2197 : REPL_QB = 2182,
2198 : REPL_QB_MM = 2183,
2199 : RINT_D = 2184,
2200 : RINT_D_MMR6 = 2185,
2201 : RINT_S = 2186,
2202 : RINT_S_MMR6 = 2187,
2203 : ROTR = 2188,
2204 : ROTRV = 2189,
2205 : ROTRV_MM = 2190,
2206 : ROTR_MM = 2191,
2207 : ROUND_L_D64 = 2192,
2208 : ROUND_L_D_MMR6 = 2193,
2209 : ROUND_L_S = 2194,
2210 : ROUND_L_S_MMR6 = 2195,
2211 : ROUND_W_D32 = 2196,
2212 : ROUND_W_D64 = 2197,
2213 : ROUND_W_D_MMR6 = 2198,
2214 : ROUND_W_MM = 2199,
2215 : ROUND_W_S = 2200,
2216 : ROUND_W_S_MM = 2201,
2217 : ROUND_W_S_MMR6 = 2202,
2218 : RSQRT_D32 = 2203,
2219 : RSQRT_D32_MM = 2204,
2220 : RSQRT_D64 = 2205,
2221 : RSQRT_D64_MM = 2206,
2222 : RSQRT_S = 2207,
2223 : RSQRT_S_MM = 2208,
2224 : Restore16 = 2209,
2225 : RestoreX16 = 2210,
2226 : SAT_S_B = 2211,
2227 : SAT_S_D = 2212,
2228 : SAT_S_H = 2213,
2229 : SAT_S_W = 2214,
2230 : SAT_U_B = 2215,
2231 : SAT_U_D = 2216,
2232 : SAT_U_H = 2217,
2233 : SAT_U_W = 2218,
2234 : SB = 2219,
2235 : SB16_MM = 2220,
2236 : SB16_MMR6 = 2221,
2237 : SB64 = 2222,
2238 : SBE = 2223,
2239 : SBE_MM = 2224,
2240 : SB_MM = 2225,
2241 : SB_MMR6 = 2226,
2242 : SC = 2227,
2243 : SC64 = 2228,
2244 : SC64_R6 = 2229,
2245 : SCD = 2230,
2246 : SCD_R6 = 2231,
2247 : SCE = 2232,
2248 : SCE_MM = 2233,
2249 : SC_MM = 2234,
2250 : SC_MMR6 = 2235,
2251 : SC_R6 = 2236,
2252 : SD = 2237,
2253 : SDBBP = 2238,
2254 : SDBBP16_MM = 2239,
2255 : SDBBP16_MMR6 = 2240,
2256 : SDBBP_MM = 2241,
2257 : SDBBP_MMR6 = 2242,
2258 : SDBBP_R6 = 2243,
2259 : SDC1 = 2244,
2260 : SDC164 = 2245,
2261 : SDC1_D64_MMR6 = 2246,
2262 : SDC1_MM = 2247,
2263 : SDC2 = 2248,
2264 : SDC2_MMR6 = 2249,
2265 : SDC2_R6 = 2250,
2266 : SDC3 = 2251,
2267 : SDIV = 2252,
2268 : SDIV_MM = 2253,
2269 : SDL = 2254,
2270 : SDR = 2255,
2271 : SDXC1 = 2256,
2272 : SDXC164 = 2257,
2273 : SEB = 2258,
2274 : SEB64 = 2259,
2275 : SEB_MM = 2260,
2276 : SEH = 2261,
2277 : SEH64 = 2262,
2278 : SEH_MM = 2263,
2279 : SELEQZ = 2264,
2280 : SELEQZ64 = 2265,
2281 : SELEQZ_D = 2266,
2282 : SELEQZ_D_MMR6 = 2267,
2283 : SELEQZ_MMR6 = 2268,
2284 : SELEQZ_S = 2269,
2285 : SELEQZ_S_MMR6 = 2270,
2286 : SELNEZ = 2271,
2287 : SELNEZ64 = 2272,
2288 : SELNEZ_D = 2273,
2289 : SELNEZ_D_MMR6 = 2274,
2290 : SELNEZ_MMR6 = 2275,
2291 : SELNEZ_S = 2276,
2292 : SELNEZ_S_MMR6 = 2277,
2293 : SEL_D = 2278,
2294 : SEL_D_MMR6 = 2279,
2295 : SEL_S = 2280,
2296 : SEL_S_MMR6 = 2281,
2297 : SEQ = 2282,
2298 : SEQi = 2283,
2299 : SH = 2284,
2300 : SH16_MM = 2285,
2301 : SH16_MMR6 = 2286,
2302 : SH64 = 2287,
2303 : SHE = 2288,
2304 : SHE_MM = 2289,
2305 : SHF_B = 2290,
2306 : SHF_H = 2291,
2307 : SHF_W = 2292,
2308 : SHILO = 2293,
2309 : SHILOV = 2294,
2310 : SHILOV_MM = 2295,
2311 : SHILO_MM = 2296,
2312 : SHLLV_PH = 2297,
2313 : SHLLV_PH_MM = 2298,
2314 : SHLLV_QB = 2299,
2315 : SHLLV_QB_MM = 2300,
2316 : SHLLV_S_PH = 2301,
2317 : SHLLV_S_PH_MM = 2302,
2318 : SHLLV_S_W = 2303,
2319 : SHLLV_S_W_MM = 2304,
2320 : SHLL_PH = 2305,
2321 : SHLL_PH_MM = 2306,
2322 : SHLL_QB = 2307,
2323 : SHLL_QB_MM = 2308,
2324 : SHLL_S_PH = 2309,
2325 : SHLL_S_PH_MM = 2310,
2326 : SHLL_S_W = 2311,
2327 : SHLL_S_W_MM = 2312,
2328 : SHRAV_PH = 2313,
2329 : SHRAV_PH_MM = 2314,
2330 : SHRAV_QB = 2315,
2331 : SHRAV_QB_MMR2 = 2316,
2332 : SHRAV_R_PH = 2317,
2333 : SHRAV_R_PH_MM = 2318,
2334 : SHRAV_R_QB = 2319,
2335 : SHRAV_R_QB_MMR2 = 2320,
2336 : SHRAV_R_W = 2321,
2337 : SHRAV_R_W_MM = 2322,
2338 : SHRA_PH = 2323,
2339 : SHRA_PH_MM = 2324,
2340 : SHRA_QB = 2325,
2341 : SHRA_QB_MMR2 = 2326,
2342 : SHRA_R_PH = 2327,
2343 : SHRA_R_PH_MM = 2328,
2344 : SHRA_R_QB = 2329,
2345 : SHRA_R_QB_MMR2 = 2330,
2346 : SHRA_R_W = 2331,
2347 : SHRA_R_W_MM = 2332,
2348 : SHRLV_PH = 2333,
2349 : SHRLV_PH_MMR2 = 2334,
2350 : SHRLV_QB = 2335,
2351 : SHRLV_QB_MM = 2336,
2352 : SHRL_PH = 2337,
2353 : SHRL_PH_MMR2 = 2338,
2354 : SHRL_QB = 2339,
2355 : SHRL_QB_MM = 2340,
2356 : SH_MM = 2341,
2357 : SH_MMR6 = 2342,
2358 : SLDI_B = 2343,
2359 : SLDI_D = 2344,
2360 : SLDI_H = 2345,
2361 : SLDI_W = 2346,
2362 : SLD_B = 2347,
2363 : SLD_D = 2348,
2364 : SLD_H = 2349,
2365 : SLD_W = 2350,
2366 : SLL = 2351,
2367 : SLL16_MM = 2352,
2368 : SLL16_MMR6 = 2353,
2369 : SLL64_32 = 2354,
2370 : SLL64_64 = 2355,
2371 : SLLI_B = 2356,
2372 : SLLI_D = 2357,
2373 : SLLI_H = 2358,
2374 : SLLI_W = 2359,
2375 : SLLV = 2360,
2376 : SLLV_MM = 2361,
2377 : SLL_B = 2362,
2378 : SLL_D = 2363,
2379 : SLL_H = 2364,
2380 : SLL_MM = 2365,
2381 : SLL_MMR6 = 2366,
2382 : SLL_W = 2367,
2383 : SLT = 2368,
2384 : SLT64 = 2369,
2385 : SLT_MM = 2370,
2386 : SLTi = 2371,
2387 : SLTi64 = 2372,
2388 : SLTi_MM = 2373,
2389 : SLTiu = 2374,
2390 : SLTiu64 = 2375,
2391 : SLTiu_MM = 2376,
2392 : SLTu = 2377,
2393 : SLTu64 = 2378,
2394 : SLTu_MM = 2379,
2395 : SNE = 2380,
2396 : SNEi = 2381,
2397 : SPLATI_B = 2382,
2398 : SPLATI_D = 2383,
2399 : SPLATI_H = 2384,
2400 : SPLATI_W = 2385,
2401 : SPLAT_B = 2386,
2402 : SPLAT_D = 2387,
2403 : SPLAT_H = 2388,
2404 : SPLAT_W = 2389,
2405 : SRA = 2390,
2406 : SRAI_B = 2391,
2407 : SRAI_D = 2392,
2408 : SRAI_H = 2393,
2409 : SRAI_W = 2394,
2410 : SRARI_B = 2395,
2411 : SRARI_D = 2396,
2412 : SRARI_H = 2397,
2413 : SRARI_W = 2398,
2414 : SRAR_B = 2399,
2415 : SRAR_D = 2400,
2416 : SRAR_H = 2401,
2417 : SRAR_W = 2402,
2418 : SRAV = 2403,
2419 : SRAV_MM = 2404,
2420 : SRA_B = 2405,
2421 : SRA_D = 2406,
2422 : SRA_H = 2407,
2423 : SRA_MM = 2408,
2424 : SRA_W = 2409,
2425 : SRL = 2410,
2426 : SRL16_MM = 2411,
2427 : SRL16_MMR6 = 2412,
2428 : SRLI_B = 2413,
2429 : SRLI_D = 2414,
2430 : SRLI_H = 2415,
2431 : SRLI_W = 2416,
2432 : SRLRI_B = 2417,
2433 : SRLRI_D = 2418,
2434 : SRLRI_H = 2419,
2435 : SRLRI_W = 2420,
2436 : SRLR_B = 2421,
2437 : SRLR_D = 2422,
2438 : SRLR_H = 2423,
2439 : SRLR_W = 2424,
2440 : SRLV = 2425,
2441 : SRLV_MM = 2426,
2442 : SRL_B = 2427,
2443 : SRL_D = 2428,
2444 : SRL_H = 2429,
2445 : SRL_MM = 2430,
2446 : SRL_W = 2431,
2447 : SSNOP = 2432,
2448 : SSNOP_MM = 2433,
2449 : SSNOP_MMR6 = 2434,
2450 : ST_B = 2435,
2451 : ST_D = 2436,
2452 : ST_H = 2437,
2453 : ST_W = 2438,
2454 : SUB = 2439,
2455 : SUBQH_PH = 2440,
2456 : SUBQH_PH_MMR2 = 2441,
2457 : SUBQH_R_PH = 2442,
2458 : SUBQH_R_PH_MMR2 = 2443,
2459 : SUBQH_R_W = 2444,
2460 : SUBQH_R_W_MMR2 = 2445,
2461 : SUBQH_W = 2446,
2462 : SUBQH_W_MMR2 = 2447,
2463 : SUBQ_PH = 2448,
2464 : SUBQ_PH_MM = 2449,
2465 : SUBQ_S_PH = 2450,
2466 : SUBQ_S_PH_MM = 2451,
2467 : SUBQ_S_W = 2452,
2468 : SUBQ_S_W_MM = 2453,
2469 : SUBSUS_U_B = 2454,
2470 : SUBSUS_U_D = 2455,
2471 : SUBSUS_U_H = 2456,
2472 : SUBSUS_U_W = 2457,
2473 : SUBSUU_S_B = 2458,
2474 : SUBSUU_S_D = 2459,
2475 : SUBSUU_S_H = 2460,
2476 : SUBSUU_S_W = 2461,
2477 : SUBS_S_B = 2462,
2478 : SUBS_S_D = 2463,
2479 : SUBS_S_H = 2464,
2480 : SUBS_S_W = 2465,
2481 : SUBS_U_B = 2466,
2482 : SUBS_U_D = 2467,
2483 : SUBS_U_H = 2468,
2484 : SUBS_U_W = 2469,
2485 : SUBU16_MM = 2470,
2486 : SUBU16_MMR6 = 2471,
2487 : SUBUH_QB = 2472,
2488 : SUBUH_QB_MMR2 = 2473,
2489 : SUBUH_R_QB = 2474,
2490 : SUBUH_R_QB_MMR2 = 2475,
2491 : SUBU_MMR6 = 2476,
2492 : SUBU_PH = 2477,
2493 : SUBU_PH_MMR2 = 2478,
2494 : SUBU_QB = 2479,
2495 : SUBU_QB_MM = 2480,
2496 : SUBU_S_PH = 2481,
2497 : SUBU_S_PH_MMR2 = 2482,
2498 : SUBU_S_QB = 2483,
2499 : SUBU_S_QB_MM = 2484,
2500 : SUBVI_B = 2485,
2501 : SUBVI_D = 2486,
2502 : SUBVI_H = 2487,
2503 : SUBVI_W = 2488,
2504 : SUBV_B = 2489,
2505 : SUBV_D = 2490,
2506 : SUBV_H = 2491,
2507 : SUBV_W = 2492,
2508 : SUB_MM = 2493,
2509 : SUB_MMR6 = 2494,
2510 : SUBu = 2495,
2511 : SUBu_MM = 2496,
2512 : SUXC1 = 2497,
2513 : SUXC164 = 2498,
2514 : SUXC1_MM = 2499,
2515 : SW = 2500,
2516 : SW16_MM = 2501,
2517 : SW16_MMR6 = 2502,
2518 : SW64 = 2503,
2519 : SWC1 = 2504,
2520 : SWC1_MM = 2505,
2521 : SWC2 = 2506,
2522 : SWC2_MMR6 = 2507,
2523 : SWC2_R6 = 2508,
2524 : SWC3 = 2509,
2525 : SWDSP = 2510,
2526 : SWDSP_MM = 2511,
2527 : SWE = 2512,
2528 : SWE_MM = 2513,
2529 : SWL = 2514,
2530 : SWL64 = 2515,
2531 : SWLE = 2516,
2532 : SWLE_MM = 2517,
2533 : SWL_MM = 2518,
2534 : SWM16_MM = 2519,
2535 : SWM16_MMR6 = 2520,
2536 : SWM32_MM = 2521,
2537 : SWP_MM = 2522,
2538 : SWR = 2523,
2539 : SWR64 = 2524,
2540 : SWRE = 2525,
2541 : SWRE_MM = 2526,
2542 : SWR_MM = 2527,
2543 : SWSP_MM = 2528,
2544 : SWSP_MMR6 = 2529,
2545 : SWXC1 = 2530,
2546 : SWXC1_MM = 2531,
2547 : SW_MM = 2532,
2548 : SW_MMR6 = 2533,
2549 : SYNC = 2534,
2550 : SYNCI = 2535,
2551 : SYNCI_MM = 2536,
2552 : SYNCI_MMR6 = 2537,
2553 : SYNC_MM = 2538,
2554 : SYNC_MMR6 = 2539,
2555 : SYSCALL = 2540,
2556 : SYSCALL_MM = 2541,
2557 : Save16 = 2542,
2558 : SaveX16 = 2543,
2559 : SbRxRyOffMemX16 = 2544,
2560 : SebRx16 = 2545,
2561 : SehRx16 = 2546,
2562 : ShRxRyOffMemX16 = 2547,
2563 : SllX16 = 2548,
2564 : SllvRxRy16 = 2549,
2565 : SltRxRy16 = 2550,
2566 : SltiRxImm16 = 2551,
2567 : SltiRxImmX16 = 2552,
2568 : SltiuRxImm16 = 2553,
2569 : SltiuRxImmX16 = 2554,
2570 : SltuRxRy16 = 2555,
2571 : SraX16 = 2556,
2572 : SravRxRy16 = 2557,
2573 : SrlX16 = 2558,
2574 : SrlvRxRy16 = 2559,
2575 : SubuRxRyRz16 = 2560,
2576 : SwRxRyOffMemX16 = 2561,
2577 : SwRxSpImmX16 = 2562,
2578 : TEQ = 2563,
2579 : TEQI = 2564,
2580 : TEQI_MM = 2565,
2581 : TEQ_MM = 2566,
2582 : TGE = 2567,
2583 : TGEI = 2568,
2584 : TGEIU = 2569,
2585 : TGEIU_MM = 2570,
2586 : TGEI_MM = 2571,
2587 : TGEU = 2572,
2588 : TGEU_MM = 2573,
2589 : TGE_MM = 2574,
2590 : TLBGINV = 2575,
2591 : TLBGINVF = 2576,
2592 : TLBGINVF_MM = 2577,
2593 : TLBGINV_MM = 2578,
2594 : TLBGP = 2579,
2595 : TLBGP_MM = 2580,
2596 : TLBGR = 2581,
2597 : TLBGR_MM = 2582,
2598 : TLBGWI = 2583,
2599 : TLBGWI_MM = 2584,
2600 : TLBGWR = 2585,
2601 : TLBGWR_MM = 2586,
2602 : TLBINV = 2587,
2603 : TLBINVF = 2588,
2604 : TLBINVF_MMR6 = 2589,
2605 : TLBINV_MMR6 = 2590,
2606 : TLBP = 2591,
2607 : TLBP_MM = 2592,
2608 : TLBR = 2593,
2609 : TLBR_MM = 2594,
2610 : TLBWI = 2595,
2611 : TLBWI_MM = 2596,
2612 : TLBWR = 2597,
2613 : TLBWR_MM = 2598,
2614 : TLT = 2599,
2615 : TLTI = 2600,
2616 : TLTIU_MM = 2601,
2617 : TLTI_MM = 2602,
2618 : TLTU = 2603,
2619 : TLTU_MM = 2604,
2620 : TLT_MM = 2605,
2621 : TNE = 2606,
2622 : TNEI = 2607,
2623 : TNEI_MM = 2608,
2624 : TNE_MM = 2609,
2625 : TRUNC_L_D64 = 2610,
2626 : TRUNC_L_D_MMR6 = 2611,
2627 : TRUNC_L_S = 2612,
2628 : TRUNC_L_S_MMR6 = 2613,
2629 : TRUNC_W_D32 = 2614,
2630 : TRUNC_W_D64 = 2615,
2631 : TRUNC_W_D_MMR6 = 2616,
2632 : TRUNC_W_MM = 2617,
2633 : TRUNC_W_S = 2618,
2634 : TRUNC_W_S_MM = 2619,
2635 : TRUNC_W_S_MMR6 = 2620,
2636 : TTLTIU = 2621,
2637 : UDIV = 2622,
2638 : UDIV_MM = 2623,
2639 : V3MULU = 2624,
2640 : VMM0 = 2625,
2641 : VMULU = 2626,
2642 : VSHF_B = 2627,
2643 : VSHF_D = 2628,
2644 : VSHF_H = 2629,
2645 : VSHF_W = 2630,
2646 : WAIT = 2631,
2647 : WAIT_MM = 2632,
2648 : WAIT_MMR6 = 2633,
2649 : WRDSP = 2634,
2650 : WRDSP_MM = 2635,
2651 : WRPGPR_MMR6 = 2636,
2652 : WSBH = 2637,
2653 : WSBH_MM = 2638,
2654 : WSBH_MMR6 = 2639,
2655 : XOR = 2640,
2656 : XOR16_MM = 2641,
2657 : XOR16_MMR6 = 2642,
2658 : XOR64 = 2643,
2659 : XORI_B = 2644,
2660 : XORI_MMR6 = 2645,
2661 : XOR_MM = 2646,
2662 : XOR_MMR6 = 2647,
2663 : XOR_V = 2648,
2664 : XORi = 2649,
2665 : XORi64 = 2650,
2666 : XORi_MM = 2651,
2667 : XorRxRxRy16 = 2652,
2668 : YIELD = 2653,
2669 : INSTRUCTION_LIST_END = 2654
2670 : };
2671 :
2672 : } // end Mips namespace
2673 : } // end llvm namespace
2674 : #endif // GET_INSTRINFO_ENUM
2675 :
2676 : #ifdef GET_INSTRINFO_SCHED_ENUM
2677 : #undef GET_INSTRINFO_SCHED_ENUM
2678 : namespace llvm {
2679 :
2680 : namespace Mips {
2681 : namespace Sched {
2682 : enum {
2683 : NoInstrModel = 0,
2684 : IIPseudo = 1,
2685 : II_B = 2,
2686 : II_BCCZAL = 3,
2687 : II_MTC1 = 4,
2688 : II_MFC1 = 5,
2689 : II_JALR = 6,
2690 : II_CVT = 7,
2691 : II_DMULT = 8,
2692 : II_DMULTU = 9,
2693 : II_DDIV = 10,
2694 : II_DDIVU = 11,
2695 : II_IndirectBranchPseudo = 12,
2696 : II_MADD = 13,
2697 : II_MADDU = 14,
2698 : II_MFHI_MFLO = 15,
2699 : II_MSUB = 16,
2700 : II_MSUBU = 17,
2701 : II_MTHI_MTLO = 18,
2702 : II_MULT = 19,
2703 : II_MULTU = 20,
2704 : II_ReturnPseudo = 21,
2705 : II_DIV = 22,
2706 : II_DIVU = 23,
2707 : II_J = 24,
2708 : II_JR = 25,
2709 : II_TRAP = 26,
2710 : II_ADD = 27,
2711 : II_ADDIUPC = 28,
2712 : II_ADDIU = 29,
2713 : II_ADDU = 30,
2714 : II_ADDI = 31,
2715 : II_ALIGN = 32,
2716 : II_ALUIPC = 33,
2717 : II_AND = 34,
2718 : II_ANDI = 35,
2719 : II_AUI = 36,
2720 : II_AUIPC = 37,
2721 : IIM16Alu = 38,
2722 : II_BADDU = 39,
2723 : II_BC = 40,
2724 : II_BALC = 41,
2725 : II_BBIT = 42,
2726 : II_BC1CCZ = 43,
2727 : II_BC1F = 44,
2728 : II_BC1FL = 45,
2729 : II_BC1T = 46,
2730 : II_BC1TL = 47,
2731 : II_BC2CCZ = 48,
2732 : II_BCC = 49,
2733 : II_BCCC = 50,
2734 : II_BCCZ = 51,
2735 : II_BCCZC = 52,
2736 : II_BCCZALS = 53,
2737 : II_BITSWAP = 54,
2738 : II_BREAK = 55,
2739 : II_CACHE = 56,
2740 : II_CACHEE = 57,
2741 : II_CEIL = 58,
2742 : II_CFC1 = 59,
2743 : II_CFC2 = 60,
2744 : II_INS = 61,
2745 : II_CLASS_D = 62,
2746 : II_CLASS_S = 63,
2747 : II_CLO = 64,
2748 : II_CLZ = 65,
2749 : II_CMP_CC_D = 66,
2750 : II_CMP_CC_S = 67,
2751 : II_CRC32B = 68,
2752 : II_CRC32CB = 69,
2753 : II_CRC32CD = 70,
2754 : II_CRC32CH = 71,
2755 : II_CRC32CW = 72,
2756 : II_CRC32D = 73,
2757 : II_CRC32H = 74,
2758 : II_CRC32W = 75,
2759 : II_CTC1 = 76,
2760 : II_CTC2 = 77,
2761 : II_C_CC_D = 78,
2762 : II_C_CC_S = 79,
2763 : II_DADD = 80,
2764 : II_DADDI = 81,
2765 : II_DADDIU = 82,
2766 : II_DADDU = 83,
2767 : II_DAHI = 84,
2768 : II_DALIGN = 85,
2769 : II_DATI = 86,
2770 : II_DAUI = 87,
2771 : II_DBITSWAP = 88,
2772 : II_DCLO = 89,
2773 : II_DCLZ = 90,
2774 : II_DERET = 91,
2775 : II_EXT = 92,
2776 : II_DI = 93,
2777 : II_DLSA = 94,
2778 : II_DMFC0 = 95,
2779 : II_DMFC1 = 96,
2780 : II_DMFC2 = 97,
2781 : II_DMFGC0 = 98,
2782 : II_DMOD = 99,
2783 : II_DMODU = 100,
2784 : II_DMT = 101,
2785 : II_DMTC0 = 102,
2786 : II_DMTC1 = 103,
2787 : II_DMTC2 = 104,
2788 : II_DMTGC0 = 105,
2789 : II_DMUH = 106,
2790 : II_DMUHU = 107,
2791 : II_DMUL = 108,
2792 : II_POP = 109,
2793 : II_DROTR = 110,
2794 : II_DROTR32 = 111,
2795 : II_DROTRV = 112,
2796 : II_DSBH = 113,
2797 : II_DSHD = 114,
2798 : II_DSLL = 115,
2799 : II_DSLL32 = 116,
2800 : II_DSLLV = 117,
2801 : II_DSRA = 118,
2802 : II_DSRA32 = 119,
2803 : II_DSRAV = 120,
2804 : II_DSRL = 121,
2805 : II_DSRL32 = 122,
2806 : II_DSRLV = 123,
2807 : II_DSUB = 124,
2808 : II_DSUBU = 125,
2809 : II_DVP = 126,
2810 : II_DVPE = 127,
2811 : II_EHB = 128,
2812 : II_EI = 129,
2813 : II_EMT = 130,
2814 : II_ERET = 131,
2815 : II_ERETNC = 132,
2816 : II_EVP = 133,
2817 : II_EVPE = 134,
2818 : II_ABS = 135,
2819 : II_SQRT_D = 136,
2820 : II_ADD_D = 137,
2821 : II_ADD_S = 138,
2822 : II_DIV_D = 139,
2823 : II_DIV_S = 140,
2824 : II_FLOOR = 141,
2825 : II_MOV_D = 142,
2826 : II_MOV_S = 143,
2827 : II_MUL_D = 144,
2828 : II_MUL_S = 145,
2829 : II_NEG = 146,
2830 : II_FORK = 147,
2831 : II_SQRT_S = 148,
2832 : II_SUB_D = 149,
2833 : II_SUB_S = 150,
2834 : II_GINVI = 151,
2835 : II_GINVT = 152,
2836 : II_HYPCALL = 153,
2837 : II_JAL = 154,
2838 : II_JALR_HB = 155,
2839 : II_JALRC = 156,
2840 : II_JALRS = 157,
2841 : II_JALS = 158,
2842 : II_JIALC = 159,
2843 : II_JIC = 160,
2844 : II_JRADDIUSP = 161,
2845 : II_JRC = 162,
2846 : II_JR_HB = 163,
2847 : II_LB = 164,
2848 : II_LBE = 165,
2849 : II_LBU = 166,
2850 : II_LBUE = 167,
2851 : II_LD = 168,
2852 : II_LDC1 = 169,
2853 : II_LDC2 = 170,
2854 : II_LDC3 = 171,
2855 : II_LDL = 172,
2856 : II_LDPC = 173,
2857 : II_LDR = 174,
2858 : II_LDXC1 = 175,
2859 : II_LH = 176,
2860 : II_LHE = 177,
2861 : II_LHU = 178,
2862 : II_LHUE = 179,
2863 : II_LI = 180,
2864 : II_LL = 181,
2865 : II_LLD = 182,
2866 : II_LLE = 183,
2867 : II_LSA = 184,
2868 : II_LUI = 185,
2869 : II_LUXC1 = 186,
2870 : II_LW = 187,
2871 : II_LWC1 = 188,
2872 : II_LWC2 = 189,
2873 : II_LWC3 = 190,
2874 : II_LWE = 191,
2875 : II_LWL = 192,
2876 : II_LWLE = 193,
2877 : II_LWM = 194,
2878 : II_LWPC = 195,
2879 : II_LWP = 196,
2880 : II_LWR = 197,
2881 : II_LWRE = 198,
2882 : II_LWUPC = 199,
2883 : II_LWU = 200,
2884 : II_LWXC1 = 201,
2885 : II_LWXS = 202,
2886 : II_MADDF_D = 203,
2887 : II_MADDF_S = 204,
2888 : II_MADD_D = 205,
2889 : II_MADD_S = 206,
2890 : II_MAX_D = 207,
2891 : II_MAXA_D = 208,
2892 : II_MAX_S = 209,
2893 : II_MAXA_S = 210,
2894 : II_MFC0 = 211,
2895 : II_MFC2 = 212,
2896 : II_MFGC0 = 213,
2897 : II_MFHC0 = 214,
2898 : II_MFHC1 = 215,
2899 : II_MFHGC0 = 216,
2900 : II_MFTR = 217,
2901 : II_MIN_S = 218,
2902 : II_MINA_D = 219,
2903 : II_MIN_D = 220,
2904 : II_MINA_S = 221,
2905 : II_MOD = 222,
2906 : II_MODU = 223,
2907 : II_MOVE = 224,
2908 : II_MOVF_D = 225,
2909 : II_MOVF = 226,
2910 : II_MOVF_S = 227,
2911 : II_MOVN_D = 228,
2912 : II_MOVN = 229,
2913 : II_MOVN_S = 230,
2914 : II_MOVT_D = 231,
2915 : II_MOVT = 232,
2916 : II_MOVT_S = 233,
2917 : II_MOVZ_D = 234,
2918 : II_MOVZ = 235,
2919 : II_MOVZ_S = 236,
2920 : II_MSUBF_D = 237,
2921 : II_MSUBF_S = 238,
2922 : II_MSUB_D = 239,
2923 : II_MSUB_S = 240,
2924 : II_MTC0 = 241,
2925 : II_MTC2 = 242,
2926 : II_MTGC0 = 243,
2927 : II_MTHC0 = 244,
2928 : II_MTHC1 = 245,
2929 : II_MTHGC0 = 246,
2930 : II_MTTR = 247,
2931 : II_MUH = 248,
2932 : II_MUHU = 249,
2933 : II_MUL = 250,
2934 : II_MULU = 251,
2935 : II_NMADD_D = 252,
2936 : II_NMADD_S = 253,
2937 : II_NMSUB_D = 254,
2938 : II_NMSUB_S = 255,
2939 : II_NOR = 256,
2940 : II_NOT = 257,
2941 : II_OR = 258,
2942 : II_ORI = 259,
2943 : II_PAUSE = 260,
2944 : II_PREF = 261,
2945 : II_PREFE = 262,
2946 : II_RDHWR = 263,
2947 : II_RDPGPR = 264,
2948 : II_RECIP_D = 265,
2949 : II_RECIP_S = 266,
2950 : II_RINT_D = 267,
2951 : II_RINT_S = 268,
2952 : II_ROTR = 269,
2953 : II_ROTRV = 270,
2954 : II_ROUND = 271,
2955 : II_RSQRT_D = 272,
2956 : II_RSQRT_S = 273,
2957 : II_RESTORE = 274,
2958 : II_SB = 275,
2959 : II_SBE = 276,
2960 : II_SC = 277,
2961 : II_SCD = 278,
2962 : II_SCE = 279,
2963 : II_SD = 280,
2964 : II_SDBBP = 281,
2965 : II_SDC1 = 282,
2966 : II_SDC2 = 283,
2967 : II_SDC3 = 284,
2968 : II_SDL = 285,
2969 : II_SDR = 286,
2970 : II_SDXC1 = 287,
2971 : II_SEB = 288,
2972 : II_SEH = 289,
2973 : II_SELCCZ = 290,
2974 : II_SELCCZ_D = 291,
2975 : II_SELCCZ_S = 292,
2976 : II_SEL_D = 293,
2977 : II_SEL_S = 294,
2978 : II_SEQ_SNE = 295,
2979 : II_SEQI_SNEI = 296,
2980 : II_SH = 297,
2981 : II_SHE = 298,
2982 : II_SLL = 299,
2983 : II_SLLV = 300,
2984 : II_SLT_SLTU = 301,
2985 : II_SLTI_SLTIU = 302,
2986 : II_SRA = 303,
2987 : II_SRAV = 304,
2988 : II_SRL = 305,
2989 : II_SRLV = 306,
2990 : II_SSNOP = 307,
2991 : II_SUB = 308,
2992 : II_SUBU = 309,
2993 : II_SUXC1 = 310,
2994 : II_SW = 311,
2995 : II_SWC1 = 312,
2996 : II_SWC2 = 313,
2997 : II_SWC3 = 314,
2998 : II_SWE = 315,
2999 : II_SWL = 316,
3000 : II_SWLE = 317,
3001 : II_SWM = 318,
3002 : II_SWP = 319,
3003 : II_SWR = 320,
3004 : II_SWRE = 321,
3005 : II_SWXC1 = 322,
3006 : II_SYNC = 323,
3007 : II_SYNCI = 324,
3008 : II_SYSCALL = 325,
3009 : II_SAVE = 326,
3010 : II_TEQ = 327,
3011 : II_TEQI = 328,
3012 : II_TGE = 329,
3013 : II_TGEI = 330,
3014 : II_TGEIU = 331,
3015 : II_TGEU = 332,
3016 : II_TLBGINV = 333,
3017 : II_TLBGINVF = 334,
3018 : II_TLBGP = 335,
3019 : II_TLBGR = 336,
3020 : II_TLBGWI = 337,
3021 : II_TLBGWR = 338,
3022 : II_TLBINV = 339,
3023 : II_TLBINVF = 340,
3024 : II_TLBP = 341,
3025 : II_TLBR = 342,
3026 : II_TLBWI = 343,
3027 : II_TLBWR = 344,
3028 : II_TLT = 345,
3029 : II_TLTI = 346,
3030 : II_TTLTIU = 347,
3031 : II_TLTU = 348,
3032 : II_TNE = 349,
3033 : II_TNEI = 350,
3034 : II_TRUNC = 351,
3035 : II_WAIT = 352,
3036 : II_WRPGPR = 353,
3037 : II_WSBH = 354,
3038 : II_XOR = 355,
3039 : II_XORI = 356,
3040 : II_YIELD = 357,
3041 : AND = 358,
3042 : LUi = 359,
3043 : NOR = 360,
3044 : OR = 361,
3045 : SLTi_SLTiu = 362,
3046 : SUB = 363,
3047 : SUBu = 364,
3048 : XOR = 365,
3049 : B = 366,
3050 : BAL = 367,
3051 : BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 368,
3052 : BEQ_BEQL_BNE_BNEL = 369,
3053 : BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 370,
3054 : BREAK = 371,
3055 : DERET = 372,
3056 : ERET = 373,
3057 : ERETNC = 374,
3058 : J_TAILCALL = 375,
3059 : JR_TAILCALLREG_TAILCALLREGHB = 376,
3060 : JR_HB = 377,
3061 : PseudoIndirectBranch_PseudoIndirectHazardBranch = 378,
3062 : PseudoReturn = 379,
3063 : SDBBP = 380,
3064 : SSNOP = 381,
3065 : SYSCALL = 382,
3066 : TEQ = 383,
3067 : TEQI = 384,
3068 : TGE = 385,
3069 : TGEI = 386,
3070 : TGEIU = 387,
3071 : TGEU = 388,
3072 : TLT = 389,
3073 : TLTI = 390,
3074 : TLTU = 391,
3075 : TNE = 392,
3076 : TNEI = 393,
3077 : TRAP = 394,
3078 : TTLTIU = 395,
3079 : WAIT = 396,
3080 : PAUSE = 397,
3081 : JAL = 398,
3082 : JALR_JALRHBPseudo_JALRPseudo = 399,
3083 : JALR_HB = 400,
3084 : JALX = 401,
3085 : TLBINV = 402,
3086 : TLBINVF = 403,
3087 : TLBP = 404,
3088 : TLBR = 405,
3089 : TLBWI = 406,
3090 : TLBWR = 407,
3091 : MFC0 = 408,
3092 : MTC0 = 409,
3093 : MFC2 = 410,
3094 : MTC2 = 411,
3095 : LB = 412,
3096 : LBu = 413,
3097 : LH = 414,
3098 : LHu = 415,
3099 : LW = 416,
3100 : LL = 417,
3101 : LWC2 = 418,
3102 : LWC3 = 419,
3103 : LDC2 = 420,
3104 : LDC3 = 421,
3105 : LBE = 422,
3106 : LBuE = 423,
3107 : LHE = 424,
3108 : LHuE = 425,
3109 : LWE = 426,
3110 : LLE = 427,
3111 : LWPC = 428,
3112 : LWL = 429,
3113 : LWR = 430,
3114 : LWLE = 431,
3115 : LWRE = 432,
3116 : SB = 433,
3117 : SH = 434,
3118 : SW = 435,
3119 : SWC2 = 436,
3120 : SWC3 = 437,
3121 : SDC2 = 438,
3122 : SDC3 = 439,
3123 : SC = 440,
3124 : SBE = 441,
3125 : SHE = 442,
3126 : SWE = 443,
3127 : SCE = 444,
3128 : SWL = 445,
3129 : SWR = 446,
3130 : SWLE = 447,
3131 : SWRE = 448,
3132 : PREF = 449,
3133 : PREFE = 450,
3134 : CACHE = 451,
3135 : CACHEE = 452,
3136 : SYNC = 453,
3137 : SYNCI = 454,
3138 : CLO = 455,
3139 : CLZ = 456,
3140 : DI = 457,
3141 : EI = 458,
3142 : MFHI_MFLO_PseudoMFHI_PseudoMFLO = 459,
3143 : EHB = 460,
3144 : RDHWR = 461,
3145 : WSBH = 462,
3146 : MOVN_I_I = 463,
3147 : MOVZ_I_I = 464,
3148 : DIV_PseudoSDIV_SDIV = 465,
3149 : DIVU_PseudoUDIV_UDIV = 466,
3150 : MUL = 467,
3151 : MULT_PseudoMULT = 468,
3152 : MULTu_PseudoMULTu = 469,
3153 : MADD_PseudoMADD = 470,
3154 : MADDU_PseudoMADDU = 471,
3155 : MSUB_PseudoMSUB = 472,
3156 : MSUBU_PseudoMSUBU = 473,
3157 : MTHI_MTLO_PseudoMTLOHI = 474,
3158 : EXT = 475,
3159 : INS = 476,
3160 : ADD = 477,
3161 : ADDi = 478,
3162 : ADDiu = 479,
3163 : ANDi = 480,
3164 : ORi = 481,
3165 : ROTR = 482,
3166 : SEB = 483,
3167 : SEH = 484,
3168 : SLT_SLTu = 485,
3169 : SLL = 486,
3170 : SRA = 487,
3171 : SRL = 488,
3172 : XORi = 489,
3173 : ADDu = 490,
3174 : SLLV = 491,
3175 : SRAV = 492,
3176 : SRLV = 493,
3177 : LSA = 494,
3178 : COPY = 495,
3179 : VSHF_B_VSHF_D_VSHF_H_VSHF_W = 496,
3180 : BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 497,
3181 : BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 498,
3182 : INSERT_B_INSERT_D_INSERT_H_INSERT_W = 499,
3183 : SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 500,
3184 : BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 501,
3185 : BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 502,
3186 : BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 503,
3187 : BSELI_B_BSEL_V = 504,
3188 : BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 505,
3189 : PCNT_B_PCNT_D_PCNT_H_PCNT_W = 506,
3190 : SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 507,
3191 : BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 508,
3192 : CFCMSA_CTCMSA = 509,
3193 : FABS_S_FABS_D32_FABS_D64 = 510,
3194 : MOVF_D32_MOVF_D64 = 511,
3195 : MOVF_S = 512,
3196 : MOVT_D32_MOVT_D64 = 513,
3197 : MOVT_S = 514,
3198 : FMOV_D32_FMOV_D64 = 515,
3199 : FMOV_S = 516,
3200 : FNEG_S_FNEG_D32_FNEG_D64 = 517,
3201 : ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 518,
3202 : ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 519,
3203 : ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 520,
3204 : ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 521,
3205 : AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 522,
3206 : SHF_B_SHF_H_SHF_W = 523,
3207 : FILL_B_FILL_D_FILL_H_FILL_W = 524,
3208 : SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 525,
3209 : MOVE_V = 526,
3210 : LDI_B_LDI_D_LDI_H_LDI_W = 527,
3211 : AND_V_NOR_V_OR_V_XOR_V = 528,
3212 : ANDI_B_NORI_B_ORI_B_XORI_B = 529,
3213 : FEXP2_D_FEXP2_W = 530,
3214 : CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 531,
3215 : CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 532,
3216 : CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 533,
3217 : CMP_UN_D = 534,
3218 : CMP_UN_S = 535,
3219 : CMP_UEQ_D = 536,
3220 : CMP_UEQ_S = 537,
3221 : CMP_EQ_D = 538,
3222 : CMP_EQ_S = 539,
3223 : CMP_LT_D = 540,
3224 : CMP_LT_S = 541,
3225 : CMP_ULT_D = 542,
3226 : CMP_ULT_S = 543,
3227 : CMP_LE_D = 544,
3228 : CMP_LE_S = 545,
3229 : CMP_ULE_D = 546,
3230 : CMP_ULE_S = 547,
3231 : FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 548,
3232 : FSUEQ_D_FSUEQ_W = 549,
3233 : FSULE_D_FSULE_W = 550,
3234 : FSULT_D_FSULT_W = 551,
3235 : FSUNE_D_FSUNE_W = 552,
3236 : FSUN_D_FSUN_W = 553,
3237 : FCAF_D_FCAF_W = 554,
3238 : FCEQ_D_FCEQ_W = 555,
3239 : FCLE_D_FCLE_W = 556,
3240 : FCLT_D_FCLT_W = 557,
3241 : FCNE_D_FCNE_W = 558,
3242 : FCOR_D_FCOR_W = 559,
3243 : FCUEQ_D_FCUEQ_W = 560,
3244 : FCULE_D_FCULE_W = 561,
3245 : FCULT_D_FCULT_W = 562,
3246 : FCUNE_D_FCUNE_W = 563,
3247 : FCUN_D_FCUN_W = 564,
3248 : FABS_D_FABS_W = 565,
3249 : FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 566,
3250 : FFQL_D_FFQL_W = 567,
3251 : FFQR_D_FFQR_W = 568,
3252 : FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 569,
3253 : FRINT_D_FRINT_W = 570,
3254 : FTQ_H_FTQ_W = 571,
3255 : FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 572,
3256 : FEXDO_H_FEXDO_W = 573,
3257 : FEXUPL_D_FEXUPL_W = 574,
3258 : FEXUPR_D_FEXUPR_W = 575,
3259 : FCLASS_D_FCLASS_W = 576,
3260 : FMAX_A_D_FMAX_A_W = 577,
3261 : FMAX_D_FMAX_W = 578,
3262 : FMIN_A_D_FMIN_A_W = 579,
3263 : FMIN_D_FMIN_W = 580,
3264 : FLOG2_D_FLOG2_W = 581,
3265 : ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 582,
3266 : ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 583,
3267 : INSVE_B_INSVE_D_INSVE_H_INSVE_W = 584,
3268 : SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 585,
3269 : SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 586,
3270 : SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 587,
3271 : SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 588,
3272 : SUBV_B_SUBV_D_SUBV_H_SUBV_W = 589,
3273 : MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 590,
3274 : DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 591,
3275 : HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 592,
3276 : HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 593,
3277 : MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 594,
3278 : MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 595,
3279 : MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 596,
3280 : MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 597,
3281 : SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 598,
3282 : SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 599,
3283 : SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 600,
3284 : SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 601,
3285 : SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 602,
3286 : PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 603,
3287 : NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 604,
3288 : FADD_D32_FADD_D64 = 605,
3289 : FADD_S = 606,
3290 : FMUL_D32_FMUL_D64 = 607,
3291 : FMUL_S = 608,
3292 : FSUB_D32_FSUB_D64 = 609,
3293 : FSUB_S = 610,
3294 : TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 611,
3295 : CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 612,
3296 : C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 613,
3297 : C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 614,
3298 : FCMP_D32_FCMP_D64 = 615,
3299 : FCMP_S32 = 616,
3300 : PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 617,
3301 : FDIV_S = 618,
3302 : FDIV_D32_FDIV_D64 = 619,
3303 : FSQRT_S = 620,
3304 : FSQRT_D32_FSQRT_D64 = 621,
3305 : FRCP_D_FRCP_W = 622,
3306 : FRSQRT_D_FRSQRT_W = 623,
3307 : RECIP_D32_RECIP_D64 = 624,
3308 : RSQRT_D32_RSQRT_D64 = 625,
3309 : RECIP_S = 626,
3310 : RSQRT_S = 627,
3311 : FMADD_D_FMADD_W = 628,
3312 : FMSUB_D_FMSUB_W = 629,
3313 : FDIV_W = 630,
3314 : FDIV_D = 631,
3315 : FSQRT_W = 632,
3316 : FSQRT_D = 633,
3317 : FMUL_D_FMUL_W = 634,
3318 : FADD_D_FADD_W = 635,
3319 : FSUB_D_FSUB_W = 636,
3320 : DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 637,
3321 : DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 638,
3322 : DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 639,
3323 : MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 640,
3324 : MADDV_B_MADDV_D_MADDV_H_MADDV_W = 641,
3325 : MULV_B_MULV_D_MULV_H_MULV_W = 642,
3326 : MADDR_Q_H_MADDR_Q_W = 643,
3327 : MADD_Q_H_MADD_Q_W = 644,
3328 : MSUBR_Q_H_MSUBR_Q_W = 645,
3329 : MSUB_Q_H_MSUB_Q_W = 646,
3330 : MULR_Q_H_MULR_Q_W = 647,
3331 : MUL_Q_H_MUL_Q_W = 648,
3332 : MADD_D32_MADD_D64 = 649,
3333 : MADD_S = 650,
3334 : MSUB_D32_MSUB_D64 = 651,
3335 : MSUB_S = 652,
3336 : NMADD_D32_NMADD_D64 = 653,
3337 : NMADD_S = 654,
3338 : NMSUB_D32_NMSUB_D64 = 655,
3339 : NMSUB_S = 656,
3340 : CTC1 = 657,
3341 : MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 658,
3342 : MTHC1_D32_MTHC1_D64 = 659,
3343 : COPY_U_B_COPY_U_H_COPY_U_W = 660,
3344 : COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 661,
3345 : BC1F = 662,
3346 : BC1FL = 663,
3347 : BC1T = 664,
3348 : BC1TL = 665,
3349 : CFC1 = 666,
3350 : MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 667,
3351 : MFHC1_D32_MFHC1_D64 = 668,
3352 : MOVF_I = 669,
3353 : MOVT_I = 670,
3354 : SDC1 = 671,
3355 : SDXC1 = 672,
3356 : SUXC1 = 673,
3357 : SWC1 = 674,
3358 : SWXC1 = 675,
3359 : ST_B_ST_D_ST_H_ST_W = 676,
3360 : MOVN_I_D32_MOVN_I_D64 = 677,
3361 : MOVN_I_S = 678,
3362 : MOVZ_I_D32_MOVZ_I_D64 = 679,
3363 : MOVZ_I_S = 680,
3364 : LDC1 = 681,
3365 : LDXC1 = 682,
3366 : LWC1 = 683,
3367 : LWXC1 = 684,
3368 : LUXC1 = 685,
3369 : LD_B_LD_D_LD_H_LD_W = 686,
3370 : CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 687,
3371 : FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 688,
3372 : ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 689,
3373 : ROTRV = 690,
3374 : EXTRV_RS_W = 691,
3375 : EXTRV_R_W = 692,
3376 : EXTRV_S_H = 693,
3377 : EXTRV_W = 694,
3378 : EXTR_RS_W = 695,
3379 : EXTR_R_W = 696,
3380 : EXTR_S_H = 697,
3381 : EXTR_W = 698,
3382 : INSV = 699,
3383 : MTHLIP = 700,
3384 : MTHI_DSP = 701,
3385 : MTLO_DSP = 702,
3386 : ABSQ_S_PH = 703,
3387 : ABSQ_S_W = 704,
3388 : ADDQ_PH = 705,
3389 : ADDQ_S_PH = 706,
3390 : ADDQ_S_W = 707,
3391 : ADDSC = 708,
3392 : ADDU_QB = 709,
3393 : ADDU_S_QB = 710,
3394 : ADDWC = 711,
3395 : BITREV = 712,
3396 : BPOSGE32 = 713,
3397 : CMPGU_EQ_QB = 714,
3398 : CMPGU_LE_QB = 715,
3399 : CMPGU_LT_QB = 716,
3400 : CMPU_EQ_QB = 717,
3401 : CMPU_LE_QB = 718,
3402 : CMPU_LT_QB = 719,
3403 : CMP_EQ_PH = 720,
3404 : CMP_LE_PH = 721,
3405 : CMP_LT_PH = 722,
3406 : DPAQ_SA_L_W = 723,
3407 : DPAQ_S_W_PH = 724,
3408 : DPAU_H_QBL = 725,
3409 : DPAU_H_QBR = 726,
3410 : DPSQ_SA_L_W = 727,
3411 : DPSQ_S_W_PH = 728,
3412 : DPSU_H_QBL = 729,
3413 : DPSU_H_QBR = 730,
3414 : EXTPDPV = 731,
3415 : EXTPDP = 732,
3416 : EXTPV = 733,
3417 : EXTP = 734,
3418 : LBUX = 735,
3419 : LHX = 736,
3420 : LWX = 737,
3421 : MADDU_DSP = 738,
3422 : MADD_DSP = 739,
3423 : MAQ_SA_W_PHL = 740,
3424 : MAQ_SA_W_PHR = 741,
3425 : MAQ_S_W_PHL = 742,
3426 : MAQ_S_W_PHR = 743,
3427 : MFHI_DSP = 744,
3428 : MFLO_DSP = 745,
3429 : MODSUB = 746,
3430 : MSUBU_DSP = 747,
3431 : MSUB_DSP = 748,
3432 : MULEQ_S_W_PHL = 749,
3433 : MULEQ_S_W_PHR = 750,
3434 : MULEU_S_PH_QBL = 751,
3435 : MULEU_S_PH_QBR = 752,
3436 : MULQ_RS_PH = 753,
3437 : MULSAQ_S_W_PH = 754,
3438 : MULTU_DSP = 755,
3439 : MULT_DSP = 756,
3440 : PACKRL_PH = 757,
3441 : PICK_PH = 758,
3442 : PICK_QB = 759,
3443 : PRECEQU_PH_QBLA = 760,
3444 : PRECEQU_PH_QBL = 761,
3445 : PRECEQU_PH_QBRA = 762,
3446 : PRECEQU_PH_QBR = 763,
3447 : PRECEQ_W_PHL = 764,
3448 : PRECEQ_W_PHR = 765,
3449 : PRECEU_PH_QBLA = 766,
3450 : PRECEU_PH_QBL = 767,
3451 : PRECEU_PH_QBRA = 768,
3452 : PRECEU_PH_QBR = 769,
3453 : PRECRQU_S_QB_PH = 770,
3454 : PRECRQ_PH_W = 771,
3455 : PRECRQ_QB_PH = 772,
3456 : PRECRQ_RS_PH_W = 773,
3457 : RADDU_W_QB = 774,
3458 : RDDSP = 775,
3459 : REPLV_PH = 776,
3460 : REPLV_QB = 777,
3461 : REPL_PH = 778,
3462 : REPL_QB = 779,
3463 : SHILOV = 780,
3464 : SHILO = 781,
3465 : SHLLV_PH = 782,
3466 : SHLLV_QB = 783,
3467 : SHLLV_S_PH = 784,
3468 : SHLLV_S_W = 785,
3469 : SHLL_PH = 786,
3470 : SHLL_QB = 787,
3471 : SHLL_S_PH = 788,
3472 : SHLL_S_W = 789,
3473 : SHRAV_PH = 790,
3474 : SHRAV_R_PH = 791,
3475 : SHRAV_R_W = 792,
3476 : SHRA_PH = 793,
3477 : SHRA_R_PH = 794,
3478 : SHRA_R_W = 795,
3479 : SHRLV_QB = 796,
3480 : SHRL_QB = 797,
3481 : SUBQ_PH = 798,
3482 : SUBQ_S_PH = 799,
3483 : SUBQ_S_W = 800,
3484 : SUBU_QB = 801,
3485 : SUBU_S_QB = 802,
3486 : WRDSP = 803,
3487 : ABSQ_S_QB = 804,
3488 : ADDQH_PH = 805,
3489 : ADDQH_R_PH = 806,
3490 : ADDQH_R_W = 807,
3491 : ADDQH_W = 808,
3492 : ADDUH_QB = 809,
3493 : ADDUH_R_QB = 810,
3494 : ADDU_PH = 811,
3495 : ADDU_S_PH = 812,
3496 : APPEND = 813,
3497 : BALIGN = 814,
3498 : CMPGDU_EQ_QB = 815,
3499 : CMPGDU_LE_QB = 816,
3500 : CMPGDU_LT_QB = 817,
3501 : DPA_W_PH = 818,
3502 : DPAQX_SA_W_PH = 819,
3503 : DPAQX_S_W_PH = 820,
3504 : DPAX_W_PH = 821,
3505 : DPS_W_PH = 822,
3506 : DPSQX_S_W_PH = 823,
3507 : DPSQX_SA_W_PH = 824,
3508 : DPSX_W_PH = 825,
3509 : MUL_PH = 826,
3510 : MUL_S_PH = 827,
3511 : MULQ_RS_W = 828,
3512 : MULQ_S_PH = 829,
3513 : MULQ_S_W = 830,
3514 : MULSA_W_PH = 831,
3515 : PRECR_QB_PH = 832,
3516 : PRECR_SRA_PH_W = 833,
3517 : PRECR_SRA_R_PH_W = 834,
3518 : PREPEND = 835,
3519 : SHRA_QB = 836,
3520 : SHRA_R_QB = 837,
3521 : SHRAV_QB = 838,
3522 : SHRAV_R_QB = 839,
3523 : SHRL_PH = 840,
3524 : SHRLV_PH = 841,
3525 : SUBQH_PH = 842,
3526 : SUBQH_R_PH = 843,
3527 : SUBQH_W = 844,
3528 : SUBQH_R_W = 845,
3529 : SUBU_PH = 846,
3530 : SUBU_S_PH = 847,
3531 : SUBUH_QB = 848,
3532 : SUBUH_R_QB = 849,
3533 : ABSQ_S_PH_MM = 850,
3534 : ABSQ_S_W_MM = 851,
3535 : ADDQ_PH_MM = 852,
3536 : ADDQ_S_PH_MM = 853,
3537 : ADDQ_S_W_MM = 854,
3538 : ADDSC_MM = 855,
3539 : ADDU_QB_MM = 856,
3540 : ADDU_S_QB_MM = 857,
3541 : ADDWC_MM = 858,
3542 : BITREV_MM = 859,
3543 : BPOSGE32_MM = 860,
3544 : CMPGU_EQ_QB_MM = 861,
3545 : CMPGU_LE_QB_MM = 862,
3546 : CMPGU_LT_QB_MM = 863,
3547 : CMPU_EQ_QB_MM = 864,
3548 : CMPU_LE_QB_MM = 865,
3549 : CMPU_LT_QB_MM = 866,
3550 : CMP_EQ_PH_MM = 867,
3551 : CMP_LE_PH_MM = 868,
3552 : CMP_LT_PH_MM = 869,
3553 : DPAQ_SA_L_W_MM = 870,
3554 : DPAQ_S_W_PH_MM = 871,
3555 : DPAU_H_QBL_MM = 872,
3556 : DPAU_H_QBR_MM = 873,
3557 : DPSQ_SA_L_W_MM = 874,
3558 : DPSQ_S_W_PH_MM = 875,
3559 : DPSU_H_QBL_MM = 876,
3560 : DPSU_H_QBR_MM = 877,
3561 : EXTPDPV_MM = 878,
3562 : EXTPDP_MM = 879,
3563 : EXTPV_MM = 880,
3564 : EXTP_MM = 881,
3565 : EXTRV_RS_W_MM = 882,
3566 : EXTRV_R_W_MM = 883,
3567 : EXTRV_S_H_MM = 884,
3568 : EXTRV_W_MM = 885,
3569 : EXTR_RS_W_MM = 886,
3570 : EXTR_R_W_MM = 887,
3571 : EXTR_S_H_MM = 888,
3572 : EXTR_W_MM = 889,
3573 : INSV_MM = 890,
3574 : LBUX_MM = 891,
3575 : LHX_MM = 892,
3576 : LWX_MM = 893,
3577 : MADDU_DSP_MM = 894,
3578 : MADD_DSP_MM = 895,
3579 : MAQ_SA_W_PHL_MM = 896,
3580 : MAQ_SA_W_PHR_MM = 897,
3581 : MAQ_S_W_PHL_MM = 898,
3582 : MAQ_S_W_PHR_MM = 899,
3583 : MFHI_DSP_MM = 900,
3584 : MFLO_DSP_MM = 901,
3585 : MODSUB_MM = 902,
3586 : MOVEP_MM = 903,
3587 : MOVEP_MMR6 = 904,
3588 : MOVN_I_MM = 905,
3589 : MOVZ_I_MM = 906,
3590 : MSUBU_DSP_MM = 907,
3591 : MSUB_DSP_MM = 908,
3592 : MTHI_DSP_MM = 909,
3593 : MTHLIP_MM = 910,
3594 : MTLO_DSP_MM = 911,
3595 : MULEQ_S_W_PHL_MM = 912,
3596 : MULEQ_S_W_PHR_MM = 913,
3597 : MULEU_S_PH_QBL_MM = 914,
3598 : MULEU_S_PH_QBR_MM = 915,
3599 : MULQ_RS_PH_MM = 916,
3600 : MULSAQ_S_W_PH_MM = 917,
3601 : MULTU_DSP_MM = 918,
3602 : MULT_DSP_MM = 919,
3603 : PACKRL_PH_MM = 920,
3604 : PICK_PH_MM = 921,
3605 : PICK_QB_MM = 922,
3606 : PRECEQU_PH_QBLA_MM = 923,
3607 : PRECEQU_PH_QBL_MM = 924,
3608 : PRECEQU_PH_QBRA_MM = 925,
3609 : PRECEQU_PH_QBR_MM = 926,
3610 : PRECEQ_W_PHL_MM = 927,
3611 : PRECEQ_W_PHR_MM = 928,
3612 : PRECEU_PH_QBLA_MM = 929,
3613 : PRECEU_PH_QBL_MM = 930,
3614 : PRECEU_PH_QBRA_MM = 931,
3615 : PRECEU_PH_QBR_MM = 932,
3616 : PRECRQU_S_QB_PH_MM = 933,
3617 : PRECRQ_PH_W_MM = 934,
3618 : PRECRQ_QB_PH_MM = 935,
3619 : PRECRQ_RS_PH_W_MM = 936,
3620 : RADDU_W_QB_MM = 937,
3621 : RDDSP_MM = 938,
3622 : REPLV_PH_MM = 939,
3623 : REPLV_QB_MM = 940,
3624 : REPL_PH_MM = 941,
3625 : REPL_QB_MM = 942,
3626 : SHILOV_MM = 943,
3627 : SHILO_MM = 944,
3628 : SHLLV_PH_MM = 945,
3629 : SHLLV_QB_MM = 946,
3630 : SHLLV_S_PH_MM = 947,
3631 : SHLLV_S_W_MM = 948,
3632 : SHLL_PH_MM = 949,
3633 : SHLL_QB_MM = 950,
3634 : SHLL_S_PH_MM = 951,
3635 : SHLL_S_W_MM = 952,
3636 : SHRAV_PH_MM = 953,
3637 : SHRAV_R_PH_MM = 954,
3638 : SHRAV_R_W_MM = 955,
3639 : SHRA_PH_MM = 956,
3640 : SHRA_R_PH_MM = 957,
3641 : SHRA_R_W_MM = 958,
3642 : SHRLV_QB_MM = 959,
3643 : SHRL_QB_MM = 960,
3644 : SUBQ_PH_MM = 961,
3645 : SUBQ_S_PH_MM = 962,
3646 : SUBQ_S_W_MM = 963,
3647 : SUBU_QB_MM = 964,
3648 : SUBU_S_QB_MM = 965,
3649 : WRDSP_MM = 966,
3650 : ABSQ_S_QB_MMR2 = 967,
3651 : ADDQH_PH_MMR2 = 968,
3652 : ADDQH_R_PH_MMR2 = 969,
3653 : ADDQH_R_W_MMR2 = 970,
3654 : ADDQH_W_MMR2 = 971,
3655 : ADDUH_QB_MMR2 = 972,
3656 : ADDUH_R_QB_MMR2 = 973,
3657 : ADDU_PH_MMR2 = 974,
3658 : ADDU_S_PH_MMR2 = 975,
3659 : APPEND_MMR2 = 976,
3660 : BALIGN_MMR2 = 977,
3661 : CMPGDU_EQ_QB_MMR2 = 978,
3662 : CMPGDU_LE_QB_MMR2 = 979,
3663 : CMPGDU_LT_QB_MMR2 = 980,
3664 : DPA_W_PH_MMR2 = 981,
3665 : DPAQX_SA_W_PH_MMR2 = 982,
3666 : DPAQX_S_W_PH_MMR2 = 983,
3667 : DPAX_W_PH_MMR2 = 984,
3668 : DPS_W_PH_MMR2 = 985,
3669 : DPSQX_S_W_PH_MMR2 = 986,
3670 : DPSQX_SA_W_PH_MMR2 = 987,
3671 : DPSX_W_PH_MMR2 = 988,
3672 : MUL_PH_MMR2 = 989,
3673 : MUL_S_PH_MMR2 = 990,
3674 : MULQ_RS_W_MMR2 = 991,
3675 : MULQ_S_PH_MMR2 = 992,
3676 : MULQ_S_W_MMR2 = 993,
3677 : MULSA_W_PH_MMR2 = 994,
3678 : PRECR_QB_PH_MMR2 = 995,
3679 : PRECR_SRA_PH_W_MMR2 = 996,
3680 : PRECR_SRA_R_PH_W_MMR2 = 997,
3681 : PREPEND_MMR2 = 998,
3682 : SHRA_QB_MMR2 = 999,
3683 : SHRA_R_QB_MMR2 = 1000,
3684 : SHRAV_QB_MMR2 = 1001,
3685 : SHRAV_R_QB_MMR2 = 1002,
3686 : SHRL_PH_MMR2 = 1003,
3687 : SHRLV_PH_MMR2 = 1004,
3688 : SUBQH_PH_MMR2 = 1005,
3689 : SUBQH_R_PH_MMR2 = 1006,
3690 : SUBQH_W_MMR2 = 1007,
3691 : SUBQH_R_W_MMR2 = 1008,
3692 : SUBU_PH_MMR2 = 1009,
3693 : SUBU_S_PH_MMR2 = 1010,
3694 : SUBUH_QB_MMR2 = 1011,
3695 : SUBUH_R_QB_MMR2 = 1012,
3696 : BPOSGE32C_MMR3 = 1013,
3697 : SCHED_LIST_END = 1014
3698 : };
3699 : } // end Sched namespace
3700 : } // end Mips namespace
3701 : } // end llvm namespace
3702 : #endif // GET_INSTRINFO_SCHED_ENUM
3703 :
3704 : #ifdef GET_INSTRINFO_MC_DESC
3705 : #undef GET_INSTRINFO_MC_DESC
3706 : namespace llvm {
3707 :
3708 : static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
3709 : static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 };
3710 : static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 };
3711 : static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 };
3712 : static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 };
3713 : static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 };
3714 : static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
3715 : static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 };
3716 : static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 };
3717 : static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 };
3718 : static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
3719 : static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 };
3720 : static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 };
3721 : static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 };
3722 : static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
3723 : static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 };
3724 : static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 };
3725 : static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
3726 : static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 };
3727 : static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 };
3728 : static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
3729 : static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
3730 : static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
3731 : static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
3732 : static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
3733 : static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
3734 : static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3735 : static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
3736 : static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
3737 : static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
3738 : static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
3739 : static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
3740 : static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
3741 : static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3742 :
3743 : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3744 : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3745 : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3746 : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3747 : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3748 : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3749 : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3750 : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3751 : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3752 : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3753 : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3754 : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3755 : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3756 : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3757 : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3758 : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3759 : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3760 : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3761 : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3762 : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3763 : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3764 : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3765 : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3766 : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3767 : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3768 : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3769 : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3770 : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3771 : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3772 : static const MCOperandInfo OperandInfo31[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3773 : static const MCOperandInfo OperandInfo32[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3774 : static const MCOperandInfo OperandInfo33[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3775 : static const MCOperandInfo OperandInfo34[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3776 : static const MCOperandInfo OperandInfo35[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3777 : static const MCOperandInfo OperandInfo36[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3778 : static const MCOperandInfo OperandInfo37[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3779 : static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3780 : static const MCOperandInfo OperandInfo39[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3781 : static const MCOperandInfo OperandInfo40[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3782 : static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3783 : static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3784 : static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3785 : static const MCOperandInfo OperandInfo44[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3786 : static const MCOperandInfo OperandInfo45[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3787 : static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3788 : static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3789 : static const MCOperandInfo OperandInfo48[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3790 : static const MCOperandInfo OperandInfo49[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3791 : static const MCOperandInfo OperandInfo50[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3792 : static const MCOperandInfo OperandInfo51[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3793 : static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3794 : static const MCOperandInfo OperandInfo53[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3795 : static const MCOperandInfo OperandInfo54[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3796 : static const MCOperandInfo OperandInfo55[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3797 : static const MCOperandInfo OperandInfo56[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3798 : static const MCOperandInfo OperandInfo57[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3799 : static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3800 : static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3801 : static const MCOperandInfo OperandInfo60[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3802 : static const MCOperandInfo OperandInfo61[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3803 : static const MCOperandInfo OperandInfo62[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3804 : static const MCOperandInfo OperandInfo63[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3805 : static const MCOperandInfo OperandInfo64[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3806 : static const MCOperandInfo OperandInfo65[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3807 : static const MCOperandInfo OperandInfo66[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3808 : static const MCOperandInfo OperandInfo67[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3809 : static const MCOperandInfo OperandInfo68[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3810 : static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3811 : static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3812 : static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3813 : static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3814 : static const MCOperandInfo OperandInfo73[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3815 : static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3816 : static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3817 : static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3818 : static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3819 : static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3820 : static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3821 : static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3822 : static const MCOperandInfo OperandInfo81[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3823 : static const MCOperandInfo OperandInfo82[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3824 : static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3825 : static const MCOperandInfo OperandInfo84[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3826 : static const MCOperandInfo OperandInfo85[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3827 : static const MCOperandInfo OperandInfo86[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3828 : static const MCOperandInfo OperandInfo87[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3829 : static const MCOperandInfo OperandInfo88[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3830 : static const MCOperandInfo OperandInfo89[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3831 : static const MCOperandInfo OperandInfo90[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3832 : static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3833 : static const MCOperandInfo OperandInfo92[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3834 : static const MCOperandInfo OperandInfo93[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3835 : static const MCOperandInfo OperandInfo94[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3836 : static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3837 : static const MCOperandInfo OperandInfo96[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3838 : static const MCOperandInfo OperandInfo97[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3839 : static const MCOperandInfo OperandInfo98[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3840 : static const MCOperandInfo OperandInfo99[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3841 : static const MCOperandInfo OperandInfo100[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3842 : static const MCOperandInfo OperandInfo101[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3843 : static const MCOperandInfo OperandInfo102[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3844 : static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3845 : static const MCOperandInfo OperandInfo104[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3846 : static const MCOperandInfo OperandInfo105[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3847 : static const MCOperandInfo OperandInfo106[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3848 : static const MCOperandInfo OperandInfo107[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3849 : static const MCOperandInfo OperandInfo108[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3850 : static const MCOperandInfo OperandInfo109[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3851 : static const MCOperandInfo OperandInfo110[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3852 : static const MCOperandInfo OperandInfo111[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3853 : static const MCOperandInfo OperandInfo112[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3854 : static const MCOperandInfo OperandInfo113[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3855 : static const MCOperandInfo OperandInfo114[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3856 : static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3857 : static const MCOperandInfo OperandInfo116[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3858 : static const MCOperandInfo OperandInfo117[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3859 : static const MCOperandInfo OperandInfo118[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3860 : static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3861 : static const MCOperandInfo OperandInfo120[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3862 : static const MCOperandInfo OperandInfo121[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3863 : static const MCOperandInfo OperandInfo122[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3864 : static const MCOperandInfo OperandInfo123[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3865 : static const MCOperandInfo OperandInfo124[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3866 : static const MCOperandInfo OperandInfo125[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3867 : static const MCOperandInfo OperandInfo126[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3868 : static const MCOperandInfo OperandInfo127[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3869 : static const MCOperandInfo OperandInfo128[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3870 : static const MCOperandInfo OperandInfo129[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3871 : static const MCOperandInfo OperandInfo130[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3872 : static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3873 : static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3874 : static const MCOperandInfo OperandInfo133[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3875 : static const MCOperandInfo OperandInfo134[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3876 : static const MCOperandInfo OperandInfo135[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3877 : static const MCOperandInfo OperandInfo136[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3878 : static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3879 : static const MCOperandInfo OperandInfo138[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3880 : static const MCOperandInfo OperandInfo139[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3881 : static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3882 : static const MCOperandInfo OperandInfo141[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3883 : static const MCOperandInfo OperandInfo142[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3884 : static const MCOperandInfo OperandInfo143[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3885 : static const MCOperandInfo OperandInfo144[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3886 : static const MCOperandInfo OperandInfo145[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3887 : static const MCOperandInfo OperandInfo146[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3888 : static const MCOperandInfo OperandInfo147[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3889 : static const MCOperandInfo OperandInfo148[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3890 : static const MCOperandInfo OperandInfo149[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3891 : static const MCOperandInfo OperandInfo150[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3892 : static const MCOperandInfo OperandInfo151[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3893 : static const MCOperandInfo OperandInfo152[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3894 : static const MCOperandInfo OperandInfo153[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3895 : static const MCOperandInfo OperandInfo154[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3896 : static const MCOperandInfo OperandInfo155[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3897 : static const MCOperandInfo OperandInfo156[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3898 : static const MCOperandInfo OperandInfo157[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3899 : static const MCOperandInfo OperandInfo158[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3900 : static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3901 : static const MCOperandInfo OperandInfo160[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3902 : static const MCOperandInfo OperandInfo161[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3903 : static const MCOperandInfo OperandInfo162[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3904 : static const MCOperandInfo OperandInfo163[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3905 : static const MCOperandInfo OperandInfo164[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3906 : static const MCOperandInfo OperandInfo165[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3907 : static const MCOperandInfo OperandInfo166[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3908 : static const MCOperandInfo OperandInfo167[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3909 : static const MCOperandInfo OperandInfo168[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3910 : static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3911 : static const MCOperandInfo OperandInfo170[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3912 : static const MCOperandInfo OperandInfo171[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3913 : static const MCOperandInfo OperandInfo172[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3914 : static const MCOperandInfo OperandInfo173[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3915 : static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3916 : static const MCOperandInfo OperandInfo175[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3917 : static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3918 : static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3919 : static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3920 : static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3921 : static const MCOperandInfo OperandInfo180[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3922 : static const MCOperandInfo OperandInfo181[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3923 : static const MCOperandInfo OperandInfo182[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3924 : static const MCOperandInfo OperandInfo183[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3925 : static const MCOperandInfo OperandInfo184[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3926 : static const MCOperandInfo OperandInfo185[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3927 : static const MCOperandInfo OperandInfo186[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3928 : static const MCOperandInfo OperandInfo187[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3929 : static const MCOperandInfo OperandInfo188[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3930 : static const MCOperandInfo OperandInfo189[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3931 : static const MCOperandInfo OperandInfo190[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3932 : static const MCOperandInfo OperandInfo191[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3933 : static const MCOperandInfo OperandInfo192[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3934 : static const MCOperandInfo OperandInfo193[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3935 : static const MCOperandInfo OperandInfo194[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3936 : static const MCOperandInfo OperandInfo195[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3937 : static const MCOperandInfo OperandInfo196[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3938 : static const MCOperandInfo OperandInfo197[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3939 : static const MCOperandInfo OperandInfo198[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3940 : static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3941 : static const MCOperandInfo OperandInfo200[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3942 : static const MCOperandInfo OperandInfo201[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3943 : static const MCOperandInfo OperandInfo202[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3944 : static const MCOperandInfo OperandInfo203[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3945 : static const MCOperandInfo OperandInfo204[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3946 : static const MCOperandInfo OperandInfo205[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3947 : static const MCOperandInfo OperandInfo206[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3948 : static const MCOperandInfo OperandInfo207[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3949 : static const MCOperandInfo OperandInfo208[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3950 : static const MCOperandInfo OperandInfo209[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3951 : static const MCOperandInfo OperandInfo210[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3952 : static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3953 : static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3954 : static const MCOperandInfo OperandInfo213[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3955 : static const MCOperandInfo OperandInfo214[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3956 : static const MCOperandInfo OperandInfo215[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3957 : static const MCOperandInfo OperandInfo216[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3958 : static const MCOperandInfo OperandInfo217[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3959 : static const MCOperandInfo OperandInfo218[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3960 : static const MCOperandInfo OperandInfo219[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3961 : static const MCOperandInfo OperandInfo220[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3962 : static const MCOperandInfo OperandInfo221[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3963 : static const MCOperandInfo OperandInfo222[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3964 : static const MCOperandInfo OperandInfo223[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3965 : static const MCOperandInfo OperandInfo224[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3966 : static const MCOperandInfo OperandInfo225[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3967 : static const MCOperandInfo OperandInfo226[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3968 : static const MCOperandInfo OperandInfo227[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3969 : static const MCOperandInfo OperandInfo228[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3970 : static const MCOperandInfo OperandInfo229[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3971 : static const MCOperandInfo OperandInfo230[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3972 : static const MCOperandInfo OperandInfo231[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3973 : static const MCOperandInfo OperandInfo232[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3974 : static const MCOperandInfo OperandInfo233[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3975 : static const MCOperandInfo OperandInfo234[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3976 : static const MCOperandInfo OperandInfo235[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3977 : static const MCOperandInfo OperandInfo236[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3978 : static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3979 : static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3980 : static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3981 : static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3982 : static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3983 : static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3984 : static const MCOperandInfo OperandInfo243[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3985 : static const MCOperandInfo OperandInfo244[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3986 : static const MCOperandInfo OperandInfo245[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3987 : static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3988 : static const MCOperandInfo OperandInfo247[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3989 : static const MCOperandInfo OperandInfo248[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3990 : static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3991 : static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3992 : static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3993 : static const MCOperandInfo OperandInfo252[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3994 : static const MCOperandInfo OperandInfo253[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3995 : static const MCOperandInfo OperandInfo254[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3996 : static const MCOperandInfo OperandInfo255[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3997 : static const MCOperandInfo OperandInfo256[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3998 : static const MCOperandInfo OperandInfo257[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3999 : static const MCOperandInfo OperandInfo258[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4000 : static const MCOperandInfo OperandInfo259[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4001 : static const MCOperandInfo OperandInfo260[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4002 : static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4003 : static const MCOperandInfo OperandInfo262[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4004 : static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4005 : static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4006 : static const MCOperandInfo OperandInfo265[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4007 : static const MCOperandInfo OperandInfo266[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4008 : static const MCOperandInfo OperandInfo267[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4009 : static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4010 : static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4011 : static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4012 : static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4013 : static const MCOperandInfo OperandInfo272[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4014 : static const MCOperandInfo OperandInfo273[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4015 : static const MCOperandInfo OperandInfo274[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4016 : static const MCOperandInfo OperandInfo275[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4017 : static const MCOperandInfo OperandInfo276[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4018 : static const MCOperandInfo OperandInfo277[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4019 : static const MCOperandInfo OperandInfo278[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4020 : static const MCOperandInfo OperandInfo279[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4021 : static const MCOperandInfo OperandInfo280[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4022 : static const MCOperandInfo OperandInfo281[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4023 : static const MCOperandInfo OperandInfo282[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4024 : static const MCOperandInfo OperandInfo283[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4025 : static const MCOperandInfo OperandInfo284[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4026 : static const MCOperandInfo OperandInfo285[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4027 : static const MCOperandInfo OperandInfo286[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4028 : static const MCOperandInfo OperandInfo287[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4029 : static const MCOperandInfo OperandInfo288[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4030 : static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4031 : static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4032 : static const MCOperandInfo OperandInfo291[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4033 : static const MCOperandInfo OperandInfo292[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4034 : static const MCOperandInfo OperandInfo293[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4035 : static const MCOperandInfo OperandInfo294[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4036 : static const MCOperandInfo OperandInfo295[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4037 : static const MCOperandInfo OperandInfo296[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4038 : static const MCOperandInfo OperandInfo297[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4039 : static const MCOperandInfo OperandInfo298[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4040 : static const MCOperandInfo OperandInfo299[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4041 : static const MCOperandInfo OperandInfo300[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4042 : static const MCOperandInfo OperandInfo301[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4043 : static const MCOperandInfo OperandInfo302[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4044 : static const MCOperandInfo OperandInfo303[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4045 : static const MCOperandInfo OperandInfo304[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4046 : static const MCOperandInfo OperandInfo305[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4047 : static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4048 : static const MCOperandInfo OperandInfo307[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4049 : static const MCOperandInfo OperandInfo308[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4050 : static const MCOperandInfo OperandInfo309[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4051 : static const MCOperandInfo OperandInfo310[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4052 : static const MCOperandInfo OperandInfo311[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4053 : static const MCOperandInfo OperandInfo312[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4054 : static const MCOperandInfo OperandInfo313[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4055 : static const MCOperandInfo OperandInfo314[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4056 : static const MCOperandInfo OperandInfo315[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4057 : static const MCOperandInfo OperandInfo316[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4058 : static const MCOperandInfo OperandInfo317[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4059 : static const MCOperandInfo OperandInfo318[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4060 : static const MCOperandInfo OperandInfo319[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4061 : static const MCOperandInfo OperandInfo320[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4062 : static const MCOperandInfo OperandInfo321[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4063 : static const MCOperandInfo OperandInfo322[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4064 : static const MCOperandInfo OperandInfo323[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4065 : static const MCOperandInfo OperandInfo324[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4066 : static const MCOperandInfo OperandInfo325[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4067 : static const MCOperandInfo OperandInfo326[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4068 : static const MCOperandInfo OperandInfo327[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4069 : static const MCOperandInfo OperandInfo328[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4070 : static const MCOperandInfo OperandInfo329[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4071 : static const MCOperandInfo OperandInfo330[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4072 : static const MCOperandInfo OperandInfo331[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4073 : static const MCOperandInfo OperandInfo332[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4074 : static const MCOperandInfo OperandInfo333[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4075 : static const MCOperandInfo OperandInfo334[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4076 : static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4077 : static const MCOperandInfo OperandInfo336[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4078 : static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4079 : static const MCOperandInfo OperandInfo338[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4080 : static const MCOperandInfo OperandInfo339[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4081 : static const MCOperandInfo OperandInfo340[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4082 : static const MCOperandInfo OperandInfo341[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4083 : static const MCOperandInfo OperandInfo342[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4084 : static const MCOperandInfo OperandInfo343[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4085 :
4086 : extern const MCInstrDesc MipsInsts[] = {
4087 : { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
4088 : { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
4089 : { 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
4090 : { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = EH_LABEL
4091 : { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = GC_LABEL
4092 : { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = ANNOTATION_LABEL
4093 : { 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #6 = KILL
4094 : { 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = EXTRACT_SUBREG
4095 : { 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = INSERT_SUBREG
4096 : { 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #9 = IMPLICIT_DEF
4097 : { 10, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #10 = SUBREG_TO_REG
4098 : { 11, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #11 = COPY_TO_REGCLASS
4099 : { 12, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #12 = DBG_VALUE
4100 : { 13, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #13 = DBG_LABEL
4101 : { 14, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #14 = REG_SEQUENCE
4102 : { 15, 2, 1, 0, 495, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = COPY
4103 : { 16, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #16 = BUNDLE
4104 : { 17, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #17 = LIFETIME_START
4105 : { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_END
4106 : { 19, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #19 = STACKMAP
4107 : { 20, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #20 = FENTRY_CALL
4108 : { 21, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #21 = PATCHPOINT
4109 : { 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #22 = LOAD_STACK_GUARD
4110 : { 23, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #23 = STATEPOINT
4111 : { 24, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #24 = LOCAL_ESCAPE
4112 : { 25, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #25 = FAULTING_OP
4113 : { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = PATCHABLE_OP
4114 : { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_FUNCTION_ENTER
4115 : { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_RET
4116 : { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_FUNCTION_EXIT
4117 : { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_TAIL_CALL
4118 : { 31, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #31 = PATCHABLE_EVENT_CALL
4119 : { 32, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
4120 : { 33, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #33 = ICALL_BRANCH_FUNNEL
4121 : { 34, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #34 = G_ADD
4122 : { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_SUB
4123 : { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_MUL
4124 : { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_SDIV
4125 : { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_UDIV
4126 : { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_SREM
4127 : { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_UREM
4128 : { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_AND
4129 : { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_OR
4130 : { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_XOR
4131 : { 44, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_IMPLICIT_DEF
4132 : { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_PHI
4133 : { 46, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_FRAME_INDEX
4134 : { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_GLOBAL_VALUE
4135 : { 48, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_EXTRACT
4136 : { 49, 2, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_UNMERGE_VALUES
4137 : { 50, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_INSERT
4138 : { 51, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #51 = G_MERGE_VALUES
4139 : { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_PTRTOINT
4140 : { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_INTTOPTR
4141 : { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BITCAST
4142 : { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #55 = G_INTRINSIC_TRUNC
4143 : { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #56 = G_INTRINSIC_ROUND
4144 : { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_LOAD
4145 : { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_SEXTLOAD
4146 : { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #59 = G_ZEXTLOAD
4147 : { 60, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #60 = G_STORE
4148 : { 61, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4149 : { 62, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #62 = G_ATOMIC_CMPXCHG
4150 : { 63, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #63 = G_ATOMICRMW_XCHG
4151 : { 64, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #64 = G_ATOMICRMW_ADD
4152 : { 65, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #65 = G_ATOMICRMW_SUB
4153 : { 66, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #66 = G_ATOMICRMW_AND
4154 : { 67, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #67 = G_ATOMICRMW_NAND
4155 : { 68, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #68 = G_ATOMICRMW_OR
4156 : { 69, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMICRMW_XOR
4157 : { 70, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #70 = G_ATOMICRMW_MAX
4158 : { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_MIN
4159 : { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_UMAX
4160 : { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_UMIN
4161 : { 74, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #74 = G_BRCOND
4162 : { 75, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #75 = G_BRINDIRECT
4163 : { 76, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #76 = G_INTRINSIC
4164 : { 77, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
4165 : { 78, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #78 = G_ANYEXT
4166 : { 79, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #79 = G_TRUNC
4167 : { 80, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #80 = G_CONSTANT
4168 : { 81, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #81 = G_FCONSTANT
4169 : { 82, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #82 = G_VASTART
4170 : { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #83 = G_VAARG
4171 : { 84, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #84 = G_SEXT
4172 : { 85, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #85 = G_ZEXT
4173 : { 86, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #86 = G_SHL
4174 : { 87, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #87 = G_LSHR
4175 : { 88, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #88 = G_ASHR
4176 : { 89, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #89 = G_ICMP
4177 : { 90, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #90 = G_FCMP
4178 : { 91, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #91 = G_SELECT
4179 : { 92, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #92 = G_UADDO
4180 : { 93, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #93 = G_UADDE
4181 : { 94, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #94 = G_USUBO
4182 : { 95, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #95 = G_USUBE
4183 : { 96, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #96 = G_SADDO
4184 : { 97, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #97 = G_SADDE
4185 : { 98, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #98 = G_SSUBO
4186 : { 99, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #99 = G_SSUBE
4187 : { 100, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #100 = G_UMULO
4188 : { 101, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #101 = G_SMULO
4189 : { 102, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #102 = G_UMULH
4190 : { 103, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #103 = G_SMULH
4191 : { 104, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #104 = G_FADD
4192 : { 105, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #105 = G_FSUB
4193 : { 106, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #106 = G_FMUL
4194 : { 107, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #107 = G_FMA
4195 : { 108, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #108 = G_FDIV
4196 : { 109, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #109 = G_FREM
4197 : { 110, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #110 = G_FPOW
4198 : { 111, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #111 = G_FEXP
4199 : { 112, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #112 = G_FEXP2
4200 : { 113, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #113 = G_FLOG
4201 : { 114, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #114 = G_FLOG2
4202 : { 115, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #115 = G_FNEG
4203 : { 116, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #116 = G_FPEXT
4204 : { 117, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #117 = G_FPTRUNC
4205 : { 118, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #118 = G_FPTOSI
4206 : { 119, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #119 = G_FPTOUI
4207 : { 120, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #120 = G_SITOFP
4208 : { 121, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #121 = G_UITOFP
4209 : { 122, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #122 = G_FABS
4210 : { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #123 = G_GEP
4211 : { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #124 = G_PTR_MASK
4212 : { 125, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #125 = G_BR
4213 : { 126, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #126 = G_INSERT_VECTOR_ELT
4214 : { 127, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #127 = G_EXTRACT_VECTOR_ELT
4215 : { 128, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #128 = G_SHUFFLE_VECTOR
4216 : { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_CTTZ
4217 : { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #130 = G_CTTZ_ZERO_UNDEF
4218 : { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #131 = G_CTLZ
4219 : { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #132 = G_CTLZ_ZERO_UNDEF
4220 : { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #133 = G_CTPOP
4221 : { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #134 = G_BSWAP
4222 : { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_ADDRSPACE_CAST
4223 : { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #136 = G_BLOCK_ADDR
4224 : { 137, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #137 = ABSMacro
4225 : { 138, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #138 = ADJCALLSTACKDOWN
4226 : { 139, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #139 = ADJCALLSTACKUP
4227 : { 140, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #140 = AND_V_D_PSEUDO
4228 : { 141, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #141 = AND_V_H_PSEUDO
4229 : { 142, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #142 = AND_V_W_PSEUDO
4230 : { 143, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #143 = ATOMIC_CMP_SWAP_I16
4231 : { 144, 7, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #144 = ATOMIC_CMP_SWAP_I16_POSTRA
4232 : { 145, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #145 = ATOMIC_CMP_SWAP_I32
4233 : { 146, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #146 = ATOMIC_CMP_SWAP_I32_POSTRA
4234 : { 147, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #147 = ATOMIC_CMP_SWAP_I64
4235 : { 148, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #148 = ATOMIC_CMP_SWAP_I64_POSTRA
4236 : { 149, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #149 = ATOMIC_CMP_SWAP_I8
4237 : { 150, 7, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #150 = ATOMIC_CMP_SWAP_I8_POSTRA
4238 : { 151, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #151 = ATOMIC_LOAD_ADD_I16
4239 : { 152, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #152 = ATOMIC_LOAD_ADD_I16_POSTRA
4240 : { 153, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #153 = ATOMIC_LOAD_ADD_I32
4241 : { 154, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #154 = ATOMIC_LOAD_ADD_I32_POSTRA
4242 : { 155, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #155 = ATOMIC_LOAD_ADD_I64
4243 : { 156, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #156 = ATOMIC_LOAD_ADD_I64_POSTRA
4244 : { 157, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #157 = ATOMIC_LOAD_ADD_I8
4245 : { 158, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #158 = ATOMIC_LOAD_ADD_I8_POSTRA
4246 : { 159, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #159 = ATOMIC_LOAD_AND_I16
4247 : { 160, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #160 = ATOMIC_LOAD_AND_I16_POSTRA
4248 : { 161, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #161 = ATOMIC_LOAD_AND_I32
4249 : { 162, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #162 = ATOMIC_LOAD_AND_I32_POSTRA
4250 : { 163, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #163 = ATOMIC_LOAD_AND_I64
4251 : { 164, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #164 = ATOMIC_LOAD_AND_I64_POSTRA
4252 : { 165, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #165 = ATOMIC_LOAD_AND_I8
4253 : { 166, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #166 = ATOMIC_LOAD_AND_I8_POSTRA
4254 : { 167, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #167 = ATOMIC_LOAD_NAND_I16
4255 : { 168, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #168 = ATOMIC_LOAD_NAND_I16_POSTRA
4256 : { 169, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #169 = ATOMIC_LOAD_NAND_I32
4257 : { 170, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #170 = ATOMIC_LOAD_NAND_I32_POSTRA
4258 : { 171, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #171 = ATOMIC_LOAD_NAND_I64
4259 : { 172, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #172 = ATOMIC_LOAD_NAND_I64_POSTRA
4260 : { 173, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #173 = ATOMIC_LOAD_NAND_I8
4261 : { 174, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #174 = ATOMIC_LOAD_NAND_I8_POSTRA
4262 : { 175, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #175 = ATOMIC_LOAD_OR_I16
4263 : { 176, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #176 = ATOMIC_LOAD_OR_I16_POSTRA
4264 : { 177, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = ATOMIC_LOAD_OR_I32
4265 : { 178, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = ATOMIC_LOAD_OR_I32_POSTRA
4266 : { 179, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #179 = ATOMIC_LOAD_OR_I64
4267 : { 180, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #180 = ATOMIC_LOAD_OR_I64_POSTRA
4268 : { 181, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #181 = ATOMIC_LOAD_OR_I8
4269 : { 182, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #182 = ATOMIC_LOAD_OR_I8_POSTRA
4270 : { 183, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #183 = ATOMIC_LOAD_SUB_I16
4271 : { 184, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #184 = ATOMIC_LOAD_SUB_I16_POSTRA
4272 : { 185, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #185 = ATOMIC_LOAD_SUB_I32
4273 : { 186, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #186 = ATOMIC_LOAD_SUB_I32_POSTRA
4274 : { 187, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #187 = ATOMIC_LOAD_SUB_I64
4275 : { 188, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #188 = ATOMIC_LOAD_SUB_I64_POSTRA
4276 : { 189, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #189 = ATOMIC_LOAD_SUB_I8
4277 : { 190, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #190 = ATOMIC_LOAD_SUB_I8_POSTRA
4278 : { 191, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #191 = ATOMIC_LOAD_XOR_I16
4279 : { 192, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #192 = ATOMIC_LOAD_XOR_I16_POSTRA
4280 : { 193, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #193 = ATOMIC_LOAD_XOR_I32
4281 : { 194, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #194 = ATOMIC_LOAD_XOR_I32_POSTRA
4282 : { 195, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #195 = ATOMIC_LOAD_XOR_I64
4283 : { 196, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #196 = ATOMIC_LOAD_XOR_I64_POSTRA
4284 : { 197, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #197 = ATOMIC_LOAD_XOR_I8
4285 : { 198, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #198 = ATOMIC_LOAD_XOR_I8_POSTRA
4286 : { 199, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #199 = ATOMIC_SWAP_I16
4287 : { 200, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #200 = ATOMIC_SWAP_I16_POSTRA
4288 : { 201, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #201 = ATOMIC_SWAP_I32
4289 : { 202, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #202 = ATOMIC_SWAP_I32_POSTRA
4290 : { 203, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #203 = ATOMIC_SWAP_I64
4291 : { 204, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #204 = ATOMIC_SWAP_I64_POSTRA
4292 : { 205, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #205 = ATOMIC_SWAP_I8
4293 : { 206, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #206 = ATOMIC_SWAP_I8_POSTRA
4294 : { 207, 1, 0, 4, 366, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #207 = B
4295 : { 208, 1, 0, 4, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #208 = BAL_BR
4296 : { 209, 1, 0, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #209 = BAL_BR_MM
4297 : { 210, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #210 = BEQLImmMacro
4298 : { 211, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #211 = BGE
4299 : { 212, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #212 = BGEImmMacro
4300 : { 213, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #213 = BGEL
4301 : { 214, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #214 = BGELImmMacro
4302 : { 215, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #215 = BGEU
4303 : { 216, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #216 = BGEUImmMacro
4304 : { 217, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #217 = BGEUL
4305 : { 218, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #218 = BGEULImmMacro
4306 : { 219, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #219 = BGT
4307 : { 220, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #220 = BGTImmMacro
4308 : { 221, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #221 = BGTL
4309 : { 222, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #222 = BGTLImmMacro
4310 : { 223, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = BGTU
4311 : { 224, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #224 = BGTUImmMacro
4312 : { 225, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #225 = BGTUL
4313 : { 226, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #226 = BGTULImmMacro
4314 : { 227, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #227 = BLE
4315 : { 228, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #228 = BLEImmMacro
4316 : { 229, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #229 = BLEL
4317 : { 230, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #230 = BLELImmMacro
4318 : { 231, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #231 = BLEU
4319 : { 232, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #232 = BLEUImmMacro
4320 : { 233, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #233 = BLEUL
4321 : { 234, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #234 = BLEULImmMacro
4322 : { 235, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #235 = BLT
4323 : { 236, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #236 = BLTImmMacro
4324 : { 237, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #237 = BLTL
4325 : { 238, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #238 = BLTLImmMacro
4326 : { 239, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #239 = BLTU
4327 : { 240, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #240 = BLTUImmMacro
4328 : { 241, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #241 = BLTUL
4329 : { 242, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #242 = BLTULImmMacro
4330 : { 243, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #243 = BNELImmMacro
4331 : { 244, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #244 = BPOSGE32_PSEUDO
4332 : { 245, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #245 = BSEL_D_PSEUDO
4333 : { 246, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #246 = BSEL_FD_PSEUDO
4334 : { 247, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #247 = BSEL_FW_PSEUDO
4335 : { 248, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #248 = BSEL_H_PSEUDO
4336 : { 249, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #249 = BSEL_W_PSEUDO
4337 : { 250, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #250 = B_MM
4338 : { 251, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #251 = B_MMR6_Pseudo
4339 : { 252, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #252 = B_MM_Pseudo
4340 : { 253, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #253 = BeqImm
4341 : { 254, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #254 = BneImm
4342 : { 255, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #255 = BteqzT8CmpX16
4343 : { 256, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #256 = BteqzT8CmpiX16
4344 : { 257, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #257 = BteqzT8SltX16
4345 : { 258, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #258 = BteqzT8SltiX16
4346 : { 259, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #259 = BteqzT8SltiuX16
4347 : { 260, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #260 = BteqzT8SltuX16
4348 : { 261, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #261 = BtnezT8CmpX16
4349 : { 262, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #262 = BtnezT8CmpiX16
4350 : { 263, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #263 = BtnezT8SltX16
4351 : { 264, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #264 = BtnezT8SltiX16
4352 : { 265, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #265 = BtnezT8SltiuX16
4353 : { 266, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #266 = BtnezT8SltuX16
4354 : { 267, 3, 1, 4, 658, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #267 = BuildPairF64
4355 : { 268, 3, 1, 4, 658, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #268 = BuildPairF64_64
4356 : { 269, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #269 = CFTC1
4357 : { 270, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #270 = CONSTPOOL_ENTRY
4358 : { 271, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #271 = COPY_FD_PSEUDO
4359 : { 272, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #272 = COPY_FW_PSEUDO
4360 : { 273, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #273 = CTTC1
4361 : { 274, 1, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #274 = Constant32
4362 : { 275, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #275 = DMULImmMacro
4363 : { 276, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #276 = DMULMacro
4364 : { 277, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #277 = DMULOMacro
4365 : { 278, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #278 = DMULOUMacro
4366 : { 279, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #279 = DROL
4367 : { 280, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #280 = DROLImm
4368 : { 281, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #281 = DROR
4369 : { 282, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #282 = DRORImm
4370 : { 283, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #283 = DSDivIMacro
4371 : { 284, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #284 = DSDivMacro
4372 : { 285, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #285 = DSRemIMacro
4373 : { 286, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #286 = DSRemMacro
4374 : { 287, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #287 = DUDivIMacro
4375 : { 288, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #288 = DUDivMacro
4376 : { 289, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #289 = DURemIMacro
4377 : { 290, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #290 = DURemMacro
4378 : { 291, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #291 = ERet
4379 : { 292, 3, 1, 4, 667, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #292 = ExtractElementF64
4380 : { 293, 3, 1, 4, 667, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #293 = ExtractElementF64_64
4381 : { 294, 2, 1, 4, 565, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #294 = FABS_D
4382 : { 295, 2, 1, 4, 565, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #295 = FABS_W
4383 : { 296, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #296 = FEXP2_D_1_PSEUDO
4384 : { 297, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #297 = FEXP2_W_1_PSEUDO
4385 : { 298, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #298 = FILL_FD_PSEUDO
4386 : { 299, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #299 = FILL_FW_PSEUDO
4387 : { 300, 4, 2, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #300 = GotPrologue16
4388 : { 301, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #301 = INSERT_B_VIDX64_PSEUDO
4389 : { 302, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #302 = INSERT_B_VIDX_PSEUDO
4390 : { 303, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #303 = INSERT_D_VIDX64_PSEUDO
4391 : { 304, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #304 = INSERT_D_VIDX_PSEUDO
4392 : { 305, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #305 = INSERT_FD_PSEUDO
4393 : { 306, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #306 = INSERT_FD_VIDX64_PSEUDO
4394 : { 307, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #307 = INSERT_FD_VIDX_PSEUDO
4395 : { 308, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #308 = INSERT_FW_PSEUDO
4396 : { 309, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #309 = INSERT_FW_VIDX64_PSEUDO
4397 : { 310, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #310 = INSERT_FW_VIDX_PSEUDO
4398 : { 311, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #311 = INSERT_H_VIDX64_PSEUDO
4399 : { 312, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #312 = INSERT_H_VIDX_PSEUDO
4400 : { 313, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #313 = INSERT_W_VIDX64_PSEUDO
4401 : { 314, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #314 = INSERT_W_VIDX_PSEUDO
4402 : { 315, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr }, // Inst #315 = JALR64Pseudo
4403 : { 316, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr }, // Inst #316 = JALRHB64Pseudo
4404 : { 317, 1, 0, 4, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #317 = JALRHBPseudo
4405 : { 318, 1, 0, 4, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #318 = JALRPseudo
4406 : { 319, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #319 = JalOneReg
4407 : { 320, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #320 = JalTwoReg
4408 : { 321, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #321 = LDMacro
4409 : { 322, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #322 = LD_F16
4410 : { 323, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #323 = LOAD_ACC128
4411 : { 324, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #324 = LOAD_ACC64
4412 : { 325, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #325 = LOAD_ACC64DSP
4413 : { 326, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #326 = LOAD_CCOND_DSP
4414 : { 327, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #327 = LONG_BRANCH_ADDiu
4415 : { 328, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #328 = LONG_BRANCH_DADDiu
4416 : { 329, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #329 = LONG_BRANCH_LUi
4417 : { 330, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #330 = LWM_MM
4418 : { 331, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #331 = LoadAddrImm32
4419 : { 332, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #332 = LoadAddrImm64
4420 : { 333, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #333 = LoadAddrReg32
4421 : { 334, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #334 = LoadAddrReg64
4422 : { 335, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #335 = LoadImm32
4423 : { 336, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #336 = LoadImm64
4424 : { 337, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #337 = LoadImmDoubleFGR
4425 : { 338, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #338 = LoadImmDoubleFGR_32
4426 : { 339, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #339 = LoadImmDoubleGPR
4427 : { 340, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #340 = LoadImmSingleFGR
4428 : { 341, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #341 = LoadImmSingleGPR
4429 : { 342, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #342 = LwConstant32
4430 : { 343, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #343 = MFTACX
4431 : { 344, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #344 = MFTC0
4432 : { 345, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #345 = MFTC1
4433 : { 346, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #346 = MFTDSP
4434 : { 347, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #347 = MFTGPR
4435 : { 348, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #348 = MFTHC1
4436 : { 349, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #349 = MFTHI
4437 : { 350, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #350 = MFTLO
4438 : { 351, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #351 = MIPSeh_return32
4439 : { 352, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #352 = MIPSeh_return64
4440 : { 353, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #353 = MSA_FP_EXTEND_D_PSEUDO
4441 : { 354, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #354 = MSA_FP_EXTEND_W_PSEUDO
4442 : { 355, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #355 = MSA_FP_ROUND_D_PSEUDO
4443 : { 356, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #356 = MSA_FP_ROUND_W_PSEUDO
4444 : { 357, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #357 = MTTACX
4445 : { 358, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #358 = MTTC0
4446 : { 359, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #359 = MTTC1
4447 : { 360, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #360 = MTTDSP
4448 : { 361, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #361 = MTTGPR
4449 : { 362, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #362 = MTTHC1
4450 : { 363, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #363 = MTTHI
4451 : { 364, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #364 = MTTLO
4452 : { 365, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #365 = MULImmMacro
4453 : { 366, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #366 = MULOMacro
4454 : { 367, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #367 = MULOUMacro
4455 : { 368, 2, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #368 = MultRxRy16
4456 : { 369, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr }, // Inst #369 = MultRxRyRz16
4457 : { 370, 2, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #370 = MultuRxRy16
4458 : { 371, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr }, // Inst #371 = MultuRxRyRz16
4459 : { 372, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #372 = NOP
4460 : { 373, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #373 = NORImm
4461 : { 374, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #374 = NORImm64
4462 : { 375, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #375 = NOR_V_D_PSEUDO
4463 : { 376, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #376 = NOR_V_H_PSEUDO
4464 : { 377, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #377 = NOR_V_W_PSEUDO
4465 : { 378, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #378 = OR_V_D_PSEUDO
4466 : { 379, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #379 = OR_V_H_PSEUDO
4467 : { 380, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #380 = OR_V_W_PSEUDO
4468 : { 381, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #381 = PseudoCMPU_EQ_QB
4469 : { 382, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #382 = PseudoCMPU_LE_QB
4470 : { 383, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #383 = PseudoCMPU_LT_QB
4471 : { 384, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #384 = PseudoCMP_EQ_PH
4472 : { 385, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #385 = PseudoCMP_LE_PH
4473 : { 386, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #386 = PseudoCMP_LT_PH
4474 : { 387, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #387 = PseudoCVT_D32_W
4475 : { 388, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #388 = PseudoCVT_D64_L
4476 : { 389, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #389 = PseudoCVT_D64_W
4477 : { 390, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #390 = PseudoCVT_S_L
4478 : { 391, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #391 = PseudoCVT_S_W
4479 : { 392, 3, 1, 4, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #392 = PseudoDMULT
4480 : { 393, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #393 = PseudoDMULTu
4481 : { 394, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #394 = PseudoDSDIV
4482 : { 395, 3, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #395 = PseudoDUDIV
4483 : { 396, 1, 0, 4, 378, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #396 = PseudoIndirectBranch
4484 : { 397, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #397 = PseudoIndirectBranch64
4485 : { 398, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #398 = PseudoIndirectBranch64R6
4486 : { 399, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #399 = PseudoIndirectBranchR6
4487 : { 400, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #400 = PseudoIndirectBranch_MM
4488 : { 401, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #401 = PseudoIndirectBranch_MMR6
4489 : { 402, 1, 0, 4, 378, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #402 = PseudoIndirectHazardBranch
4490 : { 403, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #403 = PseudoIndirectHazardBranch64
4491 : { 404, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #404 = PseudoIndrectHazardBranch64R6
4492 : { 405, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #405 = PseudoIndrectHazardBranchR6
4493 : { 406, 4, 1, 4, 470, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #406 = PseudoMADD
4494 : { 407, 4, 1, 4, 471, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #407 = PseudoMADDU
4495 : { 408, 4, 1, 4, 14, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #408 = PseudoMADDU_MM
4496 : { 409, 4, 1, 4, 13, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #409 = PseudoMADD_MM
4497 : { 410, 2, 1, 4, 459, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #410 = PseudoMFHI
4498 : { 411, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #411 = PseudoMFHI64
4499 : { 412, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #412 = PseudoMFHI_MM
4500 : { 413, 2, 1, 4, 459, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #413 = PseudoMFLO
4501 : { 414, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #414 = PseudoMFLO64
4502 : { 415, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #415 = PseudoMFLO_MM
4503 : { 416, 4, 1, 4, 472, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #416 = PseudoMSUB
4504 : { 417, 4, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #417 = PseudoMSUBU
4505 : { 418, 4, 1, 4, 17, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #418 = PseudoMSUBU_MM
4506 : { 419, 4, 1, 4, 16, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #419 = PseudoMSUB_MM
4507 : { 420, 3, 1, 4, 474, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #420 = PseudoMTLOHI
4508 : { 421, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #421 = PseudoMTLOHI64
4509 : { 422, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #422 = PseudoMTLOHI_DSP
4510 : { 423, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #423 = PseudoMTLOHI_MM
4511 : { 424, 3, 1, 4, 468, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #424 = PseudoMULT
4512 : { 425, 3, 1, 4, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #425 = PseudoMULT_MM
4513 : { 426, 3, 1, 4, 469, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #426 = PseudoMULTu
4514 : { 427, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #427 = PseudoMULTu_MM
4515 : { 428, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #428 = PseudoPICK_PH
4516 : { 429, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #429 = PseudoPICK_QB
4517 : { 430, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #430 = PseudoReturn
4518 : { 431, 1, 0, 4, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #431 = PseudoReturn64
4519 : { 432, 3, 1, 4, 465, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #432 = PseudoSDIV
4520 : { 433, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #433 = PseudoSELECTFP_F_D32
4521 : { 434, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #434 = PseudoSELECTFP_F_D64
4522 : { 435, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #435 = PseudoSELECTFP_F_I
4523 : { 436, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #436 = PseudoSELECTFP_F_I64
4524 : { 437, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #437 = PseudoSELECTFP_F_S
4525 : { 438, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #438 = PseudoSELECTFP_T_D32
4526 : { 439, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #439 = PseudoSELECTFP_T_D64
4527 : { 440, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #440 = PseudoSELECTFP_T_I
4528 : { 441, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #441 = PseudoSELECTFP_T_I64
4529 : { 442, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #442 = PseudoSELECTFP_T_S
4530 : { 443, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #443 = PseudoSELECT_D32
4531 : { 444, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #444 = PseudoSELECT_D64
4532 : { 445, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #445 = PseudoSELECT_I
4533 : { 446, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #446 = PseudoSELECT_I64
4534 : { 447, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #447 = PseudoSELECT_S
4535 : { 448, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #448 = PseudoTRUNC_W_D
4536 : { 449, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #449 = PseudoTRUNC_W_D32
4537 : { 450, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #450 = PseudoTRUNC_W_S
4538 : { 451, 3, 1, 4, 466, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #451 = PseudoUDIV
4539 : { 452, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #452 = ROL
4540 : { 453, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #453 = ROLImm
4541 : { 454, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #454 = ROR
4542 : { 455, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #455 = RORImm
4543 : { 456, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #456 = RetRA
4544 : { 457, 0, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #457 = RetRA16
4545 : { 458, 3, 1, 4, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #458 = SDIV_MM_Pseudo
4546 : { 459, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #459 = SDMacro
4547 : { 460, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #460 = SDivIMacro
4548 : { 461, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #461 = SDivMacro
4549 : { 462, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #462 = SEQIMacro
4550 : { 463, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #463 = SEQMacro
4551 : { 464, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #464 = SLTImm64
4552 : { 465, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #465 = SLTUImm64
4553 : { 466, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #466 = SNZ_B_PSEUDO
4554 : { 467, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #467 = SNZ_D_PSEUDO
4555 : { 468, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #468 = SNZ_H_PSEUDO
4556 : { 469, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #469 = SNZ_V_PSEUDO
4557 : { 470, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #470 = SNZ_W_PSEUDO
4558 : { 471, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #471 = SRemIMacro
4559 : { 472, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #472 = SRemMacro
4560 : { 473, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #473 = STORE_ACC128
4561 : { 474, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #474 = STORE_ACC64
4562 : { 475, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #475 = STORE_ACC64DSP
4563 : { 476, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #476 = STORE_CCOND_DSP
4564 : { 477, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #477 = ST_F16
4565 : { 478, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #478 = SWM_MM
4566 : { 479, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #479 = SZ_B_PSEUDO
4567 : { 480, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #480 = SZ_D_PSEUDO
4568 : { 481, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #481 = SZ_H_PSEUDO
4569 : { 482, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #482 = SZ_V_PSEUDO
4570 : { 483, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #483 = SZ_W_PSEUDO
4571 : { 484, 4, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #484 = SelBeqZ
4572 : { 485, 4, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #485 = SelBneZ
4573 : { 486, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #486 = SelTBteqZCmp
4574 : { 487, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #487 = SelTBteqZCmpi
4575 : { 488, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #488 = SelTBteqZSlt
4576 : { 489, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #489 = SelTBteqZSlti
4577 : { 490, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #490 = SelTBteqZSltiu
4578 : { 491, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #491 = SelTBteqZSltu
4579 : { 492, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #492 = SelTBtneZCmp
4580 : { 493, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #493 = SelTBtneZCmpi
4581 : { 494, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #494 = SelTBtneZSlt
4582 : { 495, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #495 = SelTBtneZSlti
4583 : { 496, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #496 = SelTBtneZSltiu
4584 : { 497, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #497 = SelTBtneZSltu
4585 : { 498, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #498 = SltCCRxRy16
4586 : { 499, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #499 = SltiCCRxImmX16
4587 : { 500, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #500 = SltiuCCRxImmX16
4588 : { 501, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #501 = SltuCCRxRy16
4589 : { 502, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo112, -1 ,nullptr }, // Inst #502 = SltuRxRyRz16
4590 : { 503, 1, 0, 4, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #503 = TAILCALL
4591 : { 504, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #504 = TAILCALL64R6REG
4592 : { 505, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #505 = TAILCALLHB64R6REG
4593 : { 506, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #506 = TAILCALLHBR6REG
4594 : { 507, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #507 = TAILCALLR6REG
4595 : { 508, 1, 0, 4, 376, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #508 = TAILCALLREG
4596 : { 509, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #509 = TAILCALLREG64
4597 : { 510, 1, 0, 4, 376, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #510 = TAILCALLREGHB
4598 : { 511, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #511 = TAILCALLREGHB64
4599 : { 512, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #512 = TAILCALLREG_MM
4600 : { 513, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #513 = TAILCALLREG_MMR6
4601 : { 514, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #514 = TAILCALL_MM
4602 : { 515, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #515 = TAILCALL_MMR6
4603 : { 516, 0, 0, 4, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #516 = TRAP
4604 : { 517, 0, 0, 4, 26, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #517 = TRAP_MM
4605 : { 518, 3, 1, 4, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #518 = UDIV_MM_Pseudo
4606 : { 519, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #519 = UDivIMacro
4607 : { 520, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #520 = UDivMacro
4608 : { 521, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #521 = URemIMacro
4609 : { 522, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #522 = URemMacro
4610 : { 523, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #523 = Ulh
4611 : { 524, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #524 = Ulhu
4612 : { 525, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #525 = Ulw
4613 : { 526, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #526 = Ush
4614 : { 527, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #527 = Usw
4615 : { 528, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #528 = XOR_V_D_PSEUDO
4616 : { 529, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #529 = XOR_V_H_PSEUDO
4617 : { 530, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #530 = XOR_V_W_PSEUDO
4618 : { 531, 2, 1, 4, 703, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #531 = ABSQ_S_PH
4619 : { 532, 2, 1, 4, 850, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #532 = ABSQ_S_PH_MM
4620 : { 533, 2, 1, 4, 804, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #533 = ABSQ_S_QB
4621 : { 534, 2, 1, 4, 967, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #534 = ABSQ_S_QB_MMR2
4622 : { 535, 2, 1, 4, 704, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr }, // Inst #535 = ABSQ_S_W
4623 : { 536, 2, 1, 4, 851, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr }, // Inst #536 = ABSQ_S_W_MM
4624 : { 537, 3, 1, 4, 477, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #537 = ADD
4625 : { 538, 2, 1, 4, 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #538 = ADDIUPC
4626 : { 539, 2, 1, 4, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #539 = ADDIUPC_MM
4627 : { 540, 2, 1, 4, 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #540 = ADDIUPC_MMR6
4628 : { 541, 2, 1, 2, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #541 = ADDIUR1SP_MM
4629 : { 542, 3, 1, 2, 29, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #542 = ADDIUR2_MM
4630 : { 543, 3, 1, 2, 29, 0, 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #543 = ADDIUS5_MM
4631 : { 544, 1, 0, 2, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #544 = ADDIUSP_MM
4632 : { 545, 3, 1, 4, 29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #545 = ADDIU_MMR6
4633 : { 546, 3, 1, 4, 805, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #546 = ADDQH_PH
4634 : { 547, 3, 1, 4, 968, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #547 = ADDQH_PH_MMR2
4635 : { 548, 3, 1, 4, 806, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #548 = ADDQH_R_PH
4636 : { 549, 3, 1, 4, 969, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #549 = ADDQH_R_PH_MMR2
4637 : { 550, 3, 1, 4, 807, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #550 = ADDQH_R_W
4638 : { 551, 3, 1, 4, 970, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #551 = ADDQH_R_W_MMR2
4639 : { 552, 3, 1, 4, 808, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #552 = ADDQH_W
4640 : { 553, 3, 1, 4, 971, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #553 = ADDQH_W_MMR2
4641 : { 554, 3, 1, 4, 705, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #554 = ADDQ_PH
4642 : { 555, 3, 1, 4, 852, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #555 = ADDQ_PH_MM
4643 : { 556, 3, 1, 4, 706, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #556 = ADDQ_S_PH
4644 : { 557, 3, 1, 4, 853, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #557 = ADDQ_S_PH_MM
4645 : { 558, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #558 = ADDQ_S_W
4646 : { 559, 3, 1, 4, 854, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #559 = ADDQ_S_W_MM
4647 : { 560, 3, 1, 4, 708, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr }, // Inst #560 = ADDSC
4648 : { 561, 3, 1, 4, 855, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr }, // Inst #561 = ADDSC_MM
4649 : { 562, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #562 = ADDS_A_B
4650 : { 563, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #563 = ADDS_A_D
4651 : { 564, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #564 = ADDS_A_H
4652 : { 565, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #565 = ADDS_A_W
4653 : { 566, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #566 = ADDS_S_B
4654 : { 567, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #567 = ADDS_S_D
4655 : { 568, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #568 = ADDS_S_H
4656 : { 569, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #569 = ADDS_S_W
4657 : { 570, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #570 = ADDS_U_B
4658 : { 571, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #571 = ADDS_U_D
4659 : { 572, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #572 = ADDS_U_H
4660 : { 573, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #573 = ADDS_U_W
4661 : { 574, 3, 1, 2, 30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #574 = ADDU16_MM
4662 : { 575, 3, 1, 2, 30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #575 = ADDU16_MMR6
4663 : { 576, 3, 1, 4, 809, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #576 = ADDUH_QB
4664 : { 577, 3, 1, 4, 972, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #577 = ADDUH_QB_MMR2
4665 : { 578, 3, 1, 4, 810, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #578 = ADDUH_R_QB
4666 : { 579, 3, 1, 4, 973, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #579 = ADDUH_R_QB_MMR2
4667 : { 580, 3, 1, 4, 30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #580 = ADDU_MMR6
4668 : { 581, 3, 1, 4, 811, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #581 = ADDU_PH
4669 : { 582, 3, 1, 4, 974, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #582 = ADDU_PH_MMR2
4670 : { 583, 3, 1, 4, 709, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #583 = ADDU_QB
4671 : { 584, 3, 1, 4, 856, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #584 = ADDU_QB_MM
4672 : { 585, 3, 1, 4, 812, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #585 = ADDU_S_PH
4673 : { 586, 3, 1, 4, 975, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #586 = ADDU_S_PH_MMR2
4674 : { 587, 3, 1, 4, 710, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #587 = ADDU_S_QB
4675 : { 588, 3, 1, 4, 857, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #588 = ADDU_S_QB_MM
4676 : { 589, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #589 = ADDVI_B
4677 : { 590, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #590 = ADDVI_D
4678 : { 591, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #591 = ADDVI_H
4679 : { 592, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #592 = ADDVI_W
4680 : { 593, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #593 = ADDV_B
4681 : { 594, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #594 = ADDV_D
4682 : { 595, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #595 = ADDV_H
4683 : { 596, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #596 = ADDV_W
4684 : { 597, 3, 1, 4, 711, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #597 = ADDWC
4685 : { 598, 3, 1, 4, 858, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #598 = ADDWC_MM
4686 : { 599, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #599 = ADD_A_B
4687 : { 600, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #600 = ADD_A_D
4688 : { 601, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #601 = ADD_A_H
4689 : { 602, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #602 = ADD_A_W
4690 : { 603, 3, 1, 4, 27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #603 = ADD_MM
4691 : { 604, 3, 1, 4, 27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #604 = ADD_MMR6
4692 : { 605, 3, 1, 4, 478, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #605 = ADDi
4693 : { 606, 3, 1, 4, 31, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #606 = ADDi_MM
4694 : { 607, 3, 1, 4, 479, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #607 = ADDiu
4695 : { 608, 3, 1, 4, 29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #608 = ADDiu_MM
4696 : { 609, 3, 1, 4, 490, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #609 = ADDu
4697 : { 610, 3, 1, 4, 30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #610 = ADDu_MM
4698 : { 611, 4, 1, 4, 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #611 = ALIGN
4699 : { 612, 4, 1, 4, 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #612 = ALIGN_MMR6
4700 : { 613, 2, 1, 4, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #613 = ALUIPC
4701 : { 614, 2, 1, 4, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #614 = ALUIPC_MMR6
4702 : { 615, 3, 1, 4, 358, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #615 = AND
4703 : { 616, 3, 1, 2, 34, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #616 = AND16_MM
4704 : { 617, 3, 1, 2, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #617 = AND16_MMR6
4705 : { 618, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #618 = AND64
4706 : { 619, 3, 1, 2, 34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #619 = ANDI16_MM
4707 : { 620, 3, 1, 2, 34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #620 = ANDI16_MMR6
4708 : { 621, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #621 = ANDI_B
4709 : { 622, 3, 1, 4, 35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #622 = ANDI_MMR6
4710 : { 623, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #623 = AND_MM
4711 : { 624, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #624 = AND_MMR6
4712 : { 625, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #625 = AND_V
4713 : { 626, 3, 1, 4, 480, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #626 = ANDi
4714 : { 627, 3, 1, 4, 34, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #627 = ANDi64
4715 : { 628, 3, 1, 4, 35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #628 = ANDi_MM
4716 : { 629, 4, 1, 4, 813, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #629 = APPEND
4717 : { 630, 4, 1, 4, 976, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #630 = APPEND_MMR2
4718 : { 631, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #631 = ASUB_S_B
4719 : { 632, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #632 = ASUB_S_D
4720 : { 633, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #633 = ASUB_S_H
4721 : { 634, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #634 = ASUB_S_W
4722 : { 635, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #635 = ASUB_U_B
4723 : { 636, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #636 = ASUB_U_D
4724 : { 637, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #637 = ASUB_U_H
4725 : { 638, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #638 = ASUB_U_W
4726 : { 639, 3, 1, 4, 36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #639 = AUI
4727 : { 640, 2, 1, 4, 37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #640 = AUIPC
4728 : { 641, 2, 1, 4, 37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #641 = AUIPC_MMR6
4729 : { 642, 3, 1, 4, 36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #642 = AUI_MMR6
4730 : { 643, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #643 = AVER_S_B
4731 : { 644, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #644 = AVER_S_D
4732 : { 645, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #645 = AVER_S_H
4733 : { 646, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #646 = AVER_S_W
4734 : { 647, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #647 = AVER_U_B
4735 : { 648, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #648 = AVER_U_D
4736 : { 649, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #649 = AVER_U_H
4737 : { 650, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #650 = AVER_U_W
4738 : { 651, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #651 = AVE_S_B
4739 : { 652, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #652 = AVE_S_D
4740 : { 653, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #653 = AVE_S_H
4741 : { 654, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #654 = AVE_S_W
4742 : { 655, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #655 = AVE_U_B
4743 : { 656, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #656 = AVE_U_D
4744 : { 657, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #657 = AVE_U_H
4745 : { 658, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #658 = AVE_U_W
4746 : { 659, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #659 = AddiuRxImmX16
4747 : { 660, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #660 = AddiuRxPcImmX16
4748 : { 661, 3, 1, 2, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #661 = AddiuRxRxImm16
4749 : { 662, 3, 1, 4, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #662 = AddiuRxRxImmX16
4750 : { 663, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #663 = AddiuRxRyOffMemX16
4751 : { 664, 1, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #664 = AddiuSpImm16
4752 : { 665, 1, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #665 = AddiuSpImmX16
4753 : { 666, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #666 = AdduRxRyRz16
4754 : { 667, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #667 = AndRxRxRy16
4755 : { 668, 1, 0, 2, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #668 = B16_MM
4756 : { 669, 3, 1, 4, 39, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #669 = BADDu
4757 : { 670, 1, 0, 4, 367, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #670 = BAL
4758 : { 671, 1, 0, 4, 41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #671 = BALC
4759 : { 672, 1, 0, 4, 41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #672 = BALC_MMR6
4760 : { 673, 4, 1, 4, 814, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #673 = BALIGN
4761 : { 674, 4, 1, 4, 977, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #674 = BALIGN_MMR2
4762 : { 675, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #675 = BBIT0
4763 : { 676, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #676 = BBIT032
4764 : { 677, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #677 = BBIT1
4765 : { 678, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #678 = BBIT132
4766 : { 679, 1, 0, 4, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #679 = BC
4767 : { 680, 1, 0, 2, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #680 = BC16_MMR6
4768 : { 681, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #681 = BC1EQZ
4769 : { 682, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #682 = BC1EQZC_MMR6
4770 : { 683, 2, 0, 4, 662, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #683 = BC1F
4771 : { 684, 2, 0, 4, 663, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #684 = BC1FL
4772 : { 685, 2, 0, 4, 44, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #685 = BC1F_MM
4773 : { 686, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #686 = BC1NEZ
4774 : { 687, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #687 = BC1NEZC_MMR6
4775 : { 688, 2, 0, 4, 664, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #688 = BC1T
4776 : { 689, 2, 0, 4, 665, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #689 = BC1TL
4777 : { 690, 2, 0, 4, 46, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #690 = BC1T_MM
4778 : { 691, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #691 = BC2EQZ
4779 : { 692, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr }, // Inst #692 = BC2EQZC_MMR6
4780 : { 693, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #693 = BC2NEZ
4781 : { 694, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr }, // Inst #694 = BC2NEZC_MMR6
4782 : { 695, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #695 = BCLRI_B
4783 : { 696, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #696 = BCLRI_D
4784 : { 697, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #697 = BCLRI_H
4785 : { 698, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #698 = BCLRI_W
4786 : { 699, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #699 = BCLR_B
4787 : { 700, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #700 = BCLR_D
4788 : { 701, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #701 = BCLR_H
4789 : { 702, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #702 = BCLR_W
4790 : { 703, 1, 0, 4, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #703 = BC_MMR6
4791 : { 704, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #704 = BEQ
4792 : { 705, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #705 = BEQ64
4793 : { 706, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #706 = BEQC
4794 : { 707, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #707 = BEQC64
4795 : { 708, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #708 = BEQC_MMR6
4796 : { 709, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #709 = BEQL
4797 : { 710, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #710 = BEQZ16_MM
4798 : { 711, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #711 = BEQZALC
4799 : { 712, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #712 = BEQZALC_MMR6
4800 : { 713, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #713 = BEQZC
4801 : { 714, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #714 = BEQZC16_MMR6
4802 : { 715, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #715 = BEQZC64
4803 : { 716, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #716 = BEQZC_MM
4804 : { 717, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #717 = BEQZC_MMR6
4805 : { 718, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #718 = BEQ_MM
4806 : { 719, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #719 = BGEC
4807 : { 720, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #720 = BGEC64
4808 : { 721, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #721 = BGEC_MMR6
4809 : { 722, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #722 = BGEUC
4810 : { 723, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #723 = BGEUC64
4811 : { 724, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #724 = BGEUC_MMR6
4812 : { 725, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #725 = BGEZ
4813 : { 726, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #726 = BGEZ64
4814 : { 727, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #727 = BGEZAL
4815 : { 728, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #728 = BGEZALC
4816 : { 729, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #729 = BGEZALC_MMR6
4817 : { 730, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #730 = BGEZALL
4818 : { 731, 2, 0, 4, 53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #731 = BGEZALS_MM
4819 : { 732, 2, 0, 4, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #732 = BGEZAL_MM
4820 : { 733, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #733 = BGEZC
4821 : { 734, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #734 = BGEZC64
4822 : { 735, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #735 = BGEZC_MMR6
4823 : { 736, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #736 = BGEZL
4824 : { 737, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #737 = BGEZ_MM
4825 : { 738, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #738 = BGTZ
4826 : { 739, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #739 = BGTZ64
4827 : { 740, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #740 = BGTZALC
4828 : { 741, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #741 = BGTZALC_MMR6
4829 : { 742, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #742 = BGTZC
4830 : { 743, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #743 = BGTZC64
4831 : { 744, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #744 = BGTZC_MMR6
4832 : { 745, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #745 = BGTZL
4833 : { 746, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #746 = BGTZ_MM
4834 : { 747, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #747 = BINSLI_B
4835 : { 748, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #748 = BINSLI_D
4836 : { 749, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #749 = BINSLI_H
4837 : { 750, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #750 = BINSLI_W
4838 : { 751, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #751 = BINSL_B
4839 : { 752, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #752 = BINSL_D
4840 : { 753, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #753 = BINSL_H
4841 : { 754, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #754 = BINSL_W
4842 : { 755, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #755 = BINSRI_B
4843 : { 756, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #756 = BINSRI_D
4844 : { 757, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #757 = BINSRI_H
4845 : { 758, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #758 = BINSRI_W
4846 : { 759, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #759 = BINSR_B
4847 : { 760, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #760 = BINSR_D
4848 : { 761, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #761 = BINSR_H
4849 : { 762, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #762 = BINSR_W
4850 : { 763, 2, 1, 4, 712, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #763 = BITREV
4851 : { 764, 2, 1, 4, 859, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #764 = BITREV_MM
4852 : { 765, 2, 1, 4, 54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #765 = BITSWAP
4853 : { 766, 2, 1, 4, 54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #766 = BITSWAP_MMR6
4854 : { 767, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #767 = BLEZ
4855 : { 768, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #768 = BLEZ64
4856 : { 769, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #769 = BLEZALC
4857 : { 770, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #770 = BLEZALC_MMR6
4858 : { 771, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #771 = BLEZC
4859 : { 772, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #772 = BLEZC64
4860 : { 773, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #773 = BLEZC_MMR6
4861 : { 774, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #774 = BLEZL
4862 : { 775, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #775 = BLEZ_MM
4863 : { 776, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #776 = BLTC
4864 : { 777, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #777 = BLTC64
4865 : { 778, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #778 = BLTC_MMR6
4866 : { 779, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #779 = BLTUC
4867 : { 780, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #780 = BLTUC64
4868 : { 781, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #781 = BLTUC_MMR6
4869 : { 782, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #782 = BLTZ
4870 : { 783, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #783 = BLTZ64
4871 : { 784, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #784 = BLTZAL
4872 : { 785, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #785 = BLTZALC
4873 : { 786, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #786 = BLTZALC_MMR6
4874 : { 787, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #787 = BLTZALL
4875 : { 788, 2, 0, 4, 53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #788 = BLTZALS_MM
4876 : { 789, 2, 0, 4, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #789 = BLTZAL_MM
4877 : { 790, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #790 = BLTZC
4878 : { 791, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #791 = BLTZC64
4879 : { 792, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #792 = BLTZC_MMR6
4880 : { 793, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #793 = BLTZL
4881 : { 794, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #794 = BLTZ_MM
4882 : { 795, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #795 = BMNZI_B
4883 : { 796, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #796 = BMNZ_V
4884 : { 797, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #797 = BMZI_B
4885 : { 798, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #798 = BMZ_V
4886 : { 799, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #799 = BNE
4887 : { 800, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #800 = BNE64
4888 : { 801, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #801 = BNEC
4889 : { 802, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #802 = BNEC64
4890 : { 803, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #803 = BNEC_MMR6
4891 : { 804, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #804 = BNEGI_B
4892 : { 805, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #805 = BNEGI_D
4893 : { 806, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #806 = BNEGI_H
4894 : { 807, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #807 = BNEGI_W
4895 : { 808, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #808 = BNEG_B
4896 : { 809, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #809 = BNEG_D
4897 : { 810, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #810 = BNEG_H
4898 : { 811, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #811 = BNEG_W
4899 : { 812, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #812 = BNEL
4900 : { 813, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #813 = BNEZ16_MM
4901 : { 814, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #814 = BNEZALC
4902 : { 815, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #815 = BNEZALC_MMR6
4903 : { 816, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #816 = BNEZC
4904 : { 817, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #817 = BNEZC16_MMR6
4905 : { 818, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #818 = BNEZC64
4906 : { 819, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #819 = BNEZC_MM
4907 : { 820, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #820 = BNEZC_MMR6
4908 : { 821, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #821 = BNE_MM
4909 : { 822, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #822 = BNVC
4910 : { 823, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #823 = BNVC_MMR6
4911 : { 824, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #824 = BNZ_B
4912 : { 825, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #825 = BNZ_D
4913 : { 826, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #826 = BNZ_H
4914 : { 827, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #827 = BNZ_V
4915 : { 828, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #828 = BNZ_W
4916 : { 829, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #829 = BOVC
4917 : { 830, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #830 = BOVC_MMR6
4918 : { 831, 1, 0, 4, 713, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #831 = BPOSGE32
4919 : { 832, 1, 0, 4, 1013, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #832 = BPOSGE32C_MMR3
4920 : { 833, 1, 0, 4, 860, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #833 = BPOSGE32_MM
4921 : { 834, 2, 0, 4, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #834 = BREAK
4922 : { 835, 1, 0, 2, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #835 = BREAK16_MM
4923 : { 836, 1, 0, 2, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #836 = BREAK16_MMR6
4924 : { 837, 2, 0, 4, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #837 = BREAK_MM
4925 : { 838, 2, 0, 4, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #838 = BREAK_MMR6
4926 : { 839, 4, 1, 4, 504, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #839 = BSELI_B
4927 : { 840, 4, 1, 4, 504, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #840 = BSEL_V
4928 : { 841, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #841 = BSETI_B
4929 : { 842, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #842 = BSETI_D
4930 : { 843, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #843 = BSETI_H
4931 : { 844, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #844 = BSETI_W
4932 : { 845, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #845 = BSET_B
4933 : { 846, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #846 = BSET_D
4934 : { 847, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #847 = BSET_H
4935 : { 848, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #848 = BSET_W
4936 : { 849, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #849 = BZ_B
4937 : { 850, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #850 = BZ_D
4938 : { 851, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #851 = BZ_H
4939 : { 852, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #852 = BZ_V
4940 : { 853, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #853 = BZ_W
4941 : { 854, 2, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #854 = BeqzRxImm16
4942 : { 855, 2, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #855 = BeqzRxImmX16
4943 : { 856, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #856 = Bimm16
4944 : { 857, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #857 = BimmX16
4945 : { 858, 2, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #858 = BnezRxImm16
4946 : { 859, 2, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #859 = BnezRxImmX16
4947 : { 860, 0, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #860 = Break16
4948 : { 861, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #861 = Bteqz16
4949 : { 862, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #862 = BteqzX16
4950 : { 863, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #863 = Btnez16
4951 : { 864, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #864 = BtnezX16
4952 : { 865, 3, 0, 4, 451, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #865 = CACHE
4953 : { 866, 3, 0, 4, 452, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #866 = CACHEE
4954 : { 867, 3, 0, 4, 57, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #867 = CACHEE_MM
4955 : { 868, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #868 = CACHE_MM
4956 : { 869, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #869 = CACHE_MMR6
4957 : { 870, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #870 = CACHE_R6
4958 : { 871, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #871 = CEIL_L_D64
4959 : { 872, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #872 = CEIL_L_D_MMR6
4960 : { 873, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #873 = CEIL_L_S
4961 : { 874, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #874 = CEIL_L_S_MMR6
4962 : { 875, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #875 = CEIL_W_D32
4963 : { 876, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #876 = CEIL_W_D64
4964 : { 877, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #877 = CEIL_W_D_MMR6
4965 : { 878, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #878 = CEIL_W_MM
4966 : { 879, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #879 = CEIL_W_S
4967 : { 880, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #880 = CEIL_W_S_MM
4968 : { 881, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #881 = CEIL_W_S_MMR6
4969 : { 882, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #882 = CEQI_B
4970 : { 883, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #883 = CEQI_D
4971 : { 884, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #884 = CEQI_H
4972 : { 885, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #885 = CEQI_W
4973 : { 886, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #886 = CEQ_B
4974 : { 887, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #887 = CEQ_D
4975 : { 888, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #888 = CEQ_H
4976 : { 889, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #889 = CEQ_W
4977 : { 890, 2, 1, 4, 666, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #890 = CFC1
4978 : { 891, 2, 1, 4, 59, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #891 = CFC1_MM
4979 : { 892, 2, 1, 4, 60, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #892 = CFC2_MM
4980 : { 893, 2, 1, 4, 509, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #893 = CFCMSA
4981 : { 894, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #894 = CINS
4982 : { 895, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #895 = CINS32
4983 : { 896, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #896 = CINS64_32
4984 : { 897, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #897 = CINS_i32
4985 : { 898, 2, 1, 4, 62, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #898 = CLASS_D
4986 : { 899, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #899 = CLASS_D_MMR6
4987 : { 900, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #900 = CLASS_S
4988 : { 901, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #901 = CLASS_S_MMR6
4989 : { 902, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #902 = CLEI_S_B
4990 : { 903, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #903 = CLEI_S_D
4991 : { 904, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #904 = CLEI_S_H
4992 : { 905, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #905 = CLEI_S_W
4993 : { 906, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #906 = CLEI_U_B
4994 : { 907, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #907 = CLEI_U_D
4995 : { 908, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #908 = CLEI_U_H
4996 : { 909, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #909 = CLEI_U_W
4997 : { 910, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #910 = CLE_S_B
4998 : { 911, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #911 = CLE_S_D
4999 : { 912, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #912 = CLE_S_H
5000 : { 913, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #913 = CLE_S_W
5001 : { 914, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #914 = CLE_U_B
5002 : { 915, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #915 = CLE_U_D
5003 : { 916, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #916 = CLE_U_H
5004 : { 917, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #917 = CLE_U_W
5005 : { 918, 2, 1, 4, 455, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #918 = CLO
5006 : { 919, 2, 1, 4, 64, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #919 = CLO_MM
5007 : { 920, 2, 1, 4, 64, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #920 = CLO_MMR6
5008 : { 921, 2, 1, 4, 64, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #921 = CLO_R6
5009 : { 922, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #922 = CLTI_S_B
5010 : { 923, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #923 = CLTI_S_D
5011 : { 924, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #924 = CLTI_S_H
5012 : { 925, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #925 = CLTI_S_W
5013 : { 926, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #926 = CLTI_U_B
5014 : { 927, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #927 = CLTI_U_D
5015 : { 928, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #928 = CLTI_U_H
5016 : { 929, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #929 = CLTI_U_W
5017 : { 930, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #930 = CLT_S_B
5018 : { 931, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #931 = CLT_S_D
5019 : { 932, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #932 = CLT_S_H
5020 : { 933, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #933 = CLT_S_W
5021 : { 934, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #934 = CLT_U_B
5022 : { 935, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #935 = CLT_U_D
5023 : { 936, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #936 = CLT_U_H
5024 : { 937, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #937 = CLT_U_W
5025 : { 938, 2, 1, 4, 456, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #938 = CLZ
5026 : { 939, 2, 1, 4, 65, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #939 = CLZ_MM
5027 : { 940, 2, 1, 4, 65, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #940 = CLZ_MMR6
5028 : { 941, 2, 1, 4, 65, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #941 = CLZ_R6
5029 : { 942, 3, 1, 4, 815, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #942 = CMPGDU_EQ_QB
5030 : { 943, 3, 1, 4, 978, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #943 = CMPGDU_EQ_QB_MMR2
5031 : { 944, 3, 1, 4, 816, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #944 = CMPGDU_LE_QB
5032 : { 945, 3, 1, 4, 979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #945 = CMPGDU_LE_QB_MMR2
5033 : { 946, 3, 1, 4, 817, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #946 = CMPGDU_LT_QB
5034 : { 947, 3, 1, 4, 980, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #947 = CMPGDU_LT_QB_MMR2
5035 : { 948, 3, 1, 4, 714, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #948 = CMPGU_EQ_QB
5036 : { 949, 3, 1, 4, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #949 = CMPGU_EQ_QB_MM
5037 : { 950, 3, 1, 4, 715, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #950 = CMPGU_LE_QB
5038 : { 951, 3, 1, 4, 862, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #951 = CMPGU_LE_QB_MM
5039 : { 952, 3, 1, 4, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #952 = CMPGU_LT_QB
5040 : { 953, 3, 1, 4, 863, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #953 = CMPGU_LT_QB_MM
5041 : { 954, 2, 0, 4, 717, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #954 = CMPU_EQ_QB
5042 : { 955, 2, 0, 4, 864, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #955 = CMPU_EQ_QB_MM
5043 : { 956, 2, 0, 4, 718, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #956 = CMPU_LE_QB
5044 : { 957, 2, 0, 4, 865, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #957 = CMPU_LE_QB_MM
5045 : { 958, 2, 0, 4, 719, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #958 = CMPU_LT_QB
5046 : { 959, 2, 0, 4, 866, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #959 = CMPU_LT_QB_MM
5047 : { 960, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #960 = CMP_AF_D_MMR6
5048 : { 961, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #961 = CMP_AF_S_MMR6
5049 : { 962, 3, 1, 4, 538, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #962 = CMP_EQ_D
5050 : { 963, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #963 = CMP_EQ_D_MMR6
5051 : { 964, 2, 0, 4, 720, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #964 = CMP_EQ_PH
5052 : { 965, 2, 0, 4, 867, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #965 = CMP_EQ_PH_MM
5053 : { 966, 3, 1, 4, 539, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #966 = CMP_EQ_S
5054 : { 967, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #967 = CMP_EQ_S_MMR6
5055 : { 968, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #968 = CMP_F_D
5056 : { 969, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #969 = CMP_F_S
5057 : { 970, 3, 1, 4, 544, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #970 = CMP_LE_D
5058 : { 971, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #971 = CMP_LE_D_MMR6
5059 : { 972, 2, 0, 4, 721, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #972 = CMP_LE_PH
5060 : { 973, 2, 0, 4, 868, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #973 = CMP_LE_PH_MM
5061 : { 974, 3, 1, 4, 545, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #974 = CMP_LE_S
5062 : { 975, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #975 = CMP_LE_S_MMR6
5063 : { 976, 3, 1, 4, 540, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #976 = CMP_LT_D
5064 : { 977, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #977 = CMP_LT_D_MMR6
5065 : { 978, 2, 0, 4, 722, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #978 = CMP_LT_PH
5066 : { 979, 2, 0, 4, 869, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #979 = CMP_LT_PH_MM
5067 : { 980, 3, 1, 4, 541, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #980 = CMP_LT_S
5068 : { 981, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #981 = CMP_LT_S_MMR6
5069 : { 982, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #982 = CMP_SAF_D
5070 : { 983, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #983 = CMP_SAF_D_MMR6
5071 : { 984, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #984 = CMP_SAF_S
5072 : { 985, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #985 = CMP_SAF_S_MMR6
5073 : { 986, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #986 = CMP_SEQ_D
5074 : { 987, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #987 = CMP_SEQ_D_MMR6
5075 : { 988, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #988 = CMP_SEQ_S
5076 : { 989, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #989 = CMP_SEQ_S_MMR6
5077 : { 990, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #990 = CMP_SLE_D
5078 : { 991, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #991 = CMP_SLE_D_MMR6
5079 : { 992, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #992 = CMP_SLE_S
5080 : { 993, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #993 = CMP_SLE_S_MMR6
5081 : { 994, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #994 = CMP_SLT_D
5082 : { 995, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #995 = CMP_SLT_D_MMR6
5083 : { 996, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #996 = CMP_SLT_S
5084 : { 997, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #997 = CMP_SLT_S_MMR6
5085 : { 998, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #998 = CMP_SUEQ_D
5086 : { 999, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #999 = CMP_SUEQ_D_MMR6
5087 : { 1000, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1000 = CMP_SUEQ_S
5088 : { 1001, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1001 = CMP_SUEQ_S_MMR6
5089 : { 1002, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1002 = CMP_SULE_D
5090 : { 1003, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1003 = CMP_SULE_D_MMR6
5091 : { 1004, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1004 = CMP_SULE_S
5092 : { 1005, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1005 = CMP_SULE_S_MMR6
5093 : { 1006, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1006 = CMP_SULT_D
5094 : { 1007, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1007 = CMP_SULT_D_MMR6
5095 : { 1008, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1008 = CMP_SULT_S
5096 : { 1009, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1009 = CMP_SULT_S_MMR6
5097 : { 1010, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1010 = CMP_SUN_D
5098 : { 1011, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1011 = CMP_SUN_D_MMR6
5099 : { 1012, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1012 = CMP_SUN_S
5100 : { 1013, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1013 = CMP_SUN_S_MMR6
5101 : { 1014, 3, 1, 4, 536, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1014 = CMP_UEQ_D
5102 : { 1015, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1015 = CMP_UEQ_D_MMR6
5103 : { 1016, 3, 1, 4, 537, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1016 = CMP_UEQ_S
5104 : { 1017, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1017 = CMP_UEQ_S_MMR6
5105 : { 1018, 3, 1, 4, 546, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1018 = CMP_ULE_D
5106 : { 1019, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1019 = CMP_ULE_D_MMR6
5107 : { 1020, 3, 1, 4, 547, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1020 = CMP_ULE_S
5108 : { 1021, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1021 = CMP_ULE_S_MMR6
5109 : { 1022, 3, 1, 4, 542, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1022 = CMP_ULT_D
5110 : { 1023, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1023 = CMP_ULT_D_MMR6
5111 : { 1024, 3, 1, 4, 543, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1024 = CMP_ULT_S
5112 : { 1025, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1025 = CMP_ULT_S_MMR6
5113 : { 1026, 3, 1, 4, 534, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1026 = CMP_UN_D
5114 : { 1027, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1027 = CMP_UN_D_MMR6
5115 : { 1028, 3, 1, 4, 535, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1028 = CMP_UN_S
5116 : { 1029, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1029 = CMP_UN_S_MMR6
5117 : { 1030, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1030 = COPY_S_B
5118 : { 1031, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1031 = COPY_S_D
5119 : { 1032, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1032 = COPY_S_H
5120 : { 1033, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1033 = COPY_S_W
5121 : { 1034, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1034 = COPY_U_B
5122 : { 1035, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1035 = COPY_U_H
5123 : { 1036, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1036 = COPY_U_W
5124 : { 1037, 3, 1, 4, 68, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1037 = CRC32B
5125 : { 1038, 3, 1, 4, 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1038 = CRC32CB
5126 : { 1039, 3, 1, 4, 70, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1039 = CRC32CD
5127 : { 1040, 3, 1, 4, 71, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1040 = CRC32CH
5128 : { 1041, 3, 1, 4, 72, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1041 = CRC32CW
5129 : { 1042, 3, 1, 4, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1042 = CRC32D
5130 : { 1043, 3, 1, 4, 74, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1043 = CRC32H
5131 : { 1044, 3, 1, 4, 75, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1044 = CRC32W
5132 : { 1045, 2, 1, 4, 657, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1045 = CTC1
5133 : { 1046, 2, 1, 4, 76, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1046 = CTC1_MM
5134 : { 1047, 2, 1, 4, 77, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1047 = CTC2_MM
5135 : { 1048, 2, 0, 4, 509, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1048 = CTCMSA
5136 : { 1049, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1049 = CVT_D32_S
5137 : { 1050, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1050 = CVT_D32_S_MM
5138 : { 1051, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1051 = CVT_D32_W
5139 : { 1052, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1052 = CVT_D32_W_MM
5140 : { 1053, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1053 = CVT_D64_L
5141 : { 1054, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1054 = CVT_D64_S
5142 : { 1055, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1055 = CVT_D64_S_MM
5143 : { 1056, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1056 = CVT_D64_W
5144 : { 1057, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1057 = CVT_D64_W_MM
5145 : { 1058, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1058 = CVT_D_L_MMR6
5146 : { 1059, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1059 = CVT_L_D64
5147 : { 1060, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1060 = CVT_L_D64_MM
5148 : { 1061, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1061 = CVT_L_D_MMR6
5149 : { 1062, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1062 = CVT_L_S
5150 : { 1063, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1063 = CVT_L_S_MM
5151 : { 1064, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1064 = CVT_L_S_MMR6
5152 : { 1065, 3, 1, 4, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1065 = CVT_PS_S64
5153 : { 1066, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1066 = CVT_S_D32
5154 : { 1067, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1067 = CVT_S_D32_MM
5155 : { 1068, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1068 = CVT_S_D64
5156 : { 1069, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1069 = CVT_S_D64_MM
5157 : { 1070, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1070 = CVT_S_L
5158 : { 1071, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1071 = CVT_S_L_MMR6
5159 : { 1072, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1072 = CVT_S_PL64
5160 : { 1073, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1073 = CVT_S_PU64
5161 : { 1074, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1074 = CVT_S_W
5162 : { 1075, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1075 = CVT_S_W_MM
5163 : { 1076, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1076 = CVT_S_W_MMR6
5164 : { 1077, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1077 = CVT_W_D32
5165 : { 1078, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1078 = CVT_W_D32_MM
5166 : { 1079, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1079 = CVT_W_D64
5167 : { 1080, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1080 = CVT_W_D64_MM
5168 : { 1081, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1081 = CVT_W_S
5169 : { 1082, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1082 = CVT_W_S_MM
5170 : { 1083, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1083 = CVT_W_S_MMR6
5171 : { 1084, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1084 = C_EQ_D32
5172 : { 1085, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1085 = C_EQ_D32_MM
5173 : { 1086, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1086 = C_EQ_D64
5174 : { 1087, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1087 = C_EQ_D64_MM
5175 : { 1088, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1088 = C_EQ_S
5176 : { 1089, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1089 = C_EQ_S_MM
5177 : { 1090, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1090 = C_F_D32
5178 : { 1091, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1091 = C_F_D32_MM
5179 : { 1092, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1092 = C_F_D64
5180 : { 1093, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1093 = C_F_D64_MM
5181 : { 1094, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1094 = C_F_S
5182 : { 1095, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1095 = C_F_S_MM
5183 : { 1096, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1096 = C_LE_D32
5184 : { 1097, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1097 = C_LE_D32_MM
5185 : { 1098, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1098 = C_LE_D64
5186 : { 1099, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1099 = C_LE_D64_MM
5187 : { 1100, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1100 = C_LE_S
5188 : { 1101, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1101 = C_LE_S_MM
5189 : { 1102, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1102 = C_LT_D32
5190 : { 1103, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1103 = C_LT_D32_MM
5191 : { 1104, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1104 = C_LT_D64
5192 : { 1105, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1105 = C_LT_D64_MM
5193 : { 1106, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1106 = C_LT_S
5194 : { 1107, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1107 = C_LT_S_MM
5195 : { 1108, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1108 = C_NGE_D32
5196 : { 1109, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1109 = C_NGE_D32_MM
5197 : { 1110, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1110 = C_NGE_D64
5198 : { 1111, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1111 = C_NGE_D64_MM
5199 : { 1112, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1112 = C_NGE_S
5200 : { 1113, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1113 = C_NGE_S_MM
5201 : { 1114, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1114 = C_NGLE_D32
5202 : { 1115, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1115 = C_NGLE_D32_MM
5203 : { 1116, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1116 = C_NGLE_D64
5204 : { 1117, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1117 = C_NGLE_D64_MM
5205 : { 1118, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1118 = C_NGLE_S
5206 : { 1119, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1119 = C_NGLE_S_MM
5207 : { 1120, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1120 = C_NGL_D32
5208 : { 1121, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1121 = C_NGL_D32_MM
5209 : { 1122, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1122 = C_NGL_D64
5210 : { 1123, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1123 = C_NGL_D64_MM
5211 : { 1124, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1124 = C_NGL_S
5212 : { 1125, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1125 = C_NGL_S_MM
5213 : { 1126, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1126 = C_NGT_D32
5214 : { 1127, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1127 = C_NGT_D32_MM
5215 : { 1128, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1128 = C_NGT_D64
5216 : { 1129, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1129 = C_NGT_D64_MM
5217 : { 1130, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1130 = C_NGT_S
5218 : { 1131, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1131 = C_NGT_S_MM
5219 : { 1132, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1132 = C_OLE_D32
5220 : { 1133, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1133 = C_OLE_D32_MM
5221 : { 1134, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1134 = C_OLE_D64
5222 : { 1135, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1135 = C_OLE_D64_MM
5223 : { 1136, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1136 = C_OLE_S
5224 : { 1137, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1137 = C_OLE_S_MM
5225 : { 1138, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1138 = C_OLT_D32
5226 : { 1139, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1139 = C_OLT_D32_MM
5227 : { 1140, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1140 = C_OLT_D64
5228 : { 1141, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1141 = C_OLT_D64_MM
5229 : { 1142, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1142 = C_OLT_S
5230 : { 1143, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1143 = C_OLT_S_MM
5231 : { 1144, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1144 = C_SEQ_D32
5232 : { 1145, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1145 = C_SEQ_D32_MM
5233 : { 1146, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1146 = C_SEQ_D64
5234 : { 1147, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1147 = C_SEQ_D64_MM
5235 : { 1148, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1148 = C_SEQ_S
5236 : { 1149, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1149 = C_SEQ_S_MM
5237 : { 1150, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1150 = C_SF_D32
5238 : { 1151, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1151 = C_SF_D32_MM
5239 : { 1152, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1152 = C_SF_D64
5240 : { 1153, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1153 = C_SF_D64_MM
5241 : { 1154, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1154 = C_SF_S
5242 : { 1155, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1155 = C_SF_S_MM
5243 : { 1156, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1156 = C_UEQ_D32
5244 : { 1157, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1157 = C_UEQ_D32_MM
5245 : { 1158, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1158 = C_UEQ_D64
5246 : { 1159, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1159 = C_UEQ_D64_MM
5247 : { 1160, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1160 = C_UEQ_S
5248 : { 1161, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1161 = C_UEQ_S_MM
5249 : { 1162, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1162 = C_ULE_D32
5250 : { 1163, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1163 = C_ULE_D32_MM
5251 : { 1164, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1164 = C_ULE_D64
5252 : { 1165, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1165 = C_ULE_D64_MM
5253 : { 1166, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1166 = C_ULE_S
5254 : { 1167, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1167 = C_ULE_S_MM
5255 : { 1168, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1168 = C_ULT_D32
5256 : { 1169, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1169 = C_ULT_D32_MM
5257 : { 1170, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1170 = C_ULT_D64
5258 : { 1171, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1171 = C_ULT_D64_MM
5259 : { 1172, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1172 = C_ULT_S
5260 : { 1173, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1173 = C_ULT_S_MM
5261 : { 1174, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1174 = C_UN_D32
5262 : { 1175, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1175 = C_UN_D32_MM
5263 : { 1176, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1176 = C_UN_D64
5264 : { 1177, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1177 = C_UN_D64_MM
5265 : { 1178, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1178 = C_UN_S
5266 : { 1179, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1179 = C_UN_S_MM
5267 : { 1180, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #1180 = CmpRxRy16
5268 : { 1181, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #1181 = CmpiRxImm16
5269 : { 1182, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #1182 = CmpiRxImmX16
5270 : { 1183, 3, 1, 4, 80, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1183 = DADD
5271 : { 1184, 3, 1, 4, 81, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1184 = DADDi
5272 : { 1185, 3, 1, 4, 82, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1185 = DADDiu
5273 : { 1186, 3, 1, 4, 83, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1186 = DADDu
5274 : { 1187, 3, 1, 4, 84, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1187 = DAHI
5275 : { 1188, 4, 1, 4, 85, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1188 = DALIGN
5276 : { 1189, 3, 1, 4, 86, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1189 = DATI
5277 : { 1190, 3, 1, 4, 87, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1190 = DAUI
5278 : { 1191, 2, 1, 4, 88, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1191 = DBITSWAP
5279 : { 1192, 2, 1, 4, 89, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1192 = DCLO
5280 : { 1193, 2, 1, 4, 89, 0, 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1193 = DCLO_R6
5281 : { 1194, 2, 1, 4, 90, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1194 = DCLZ
5282 : { 1195, 2, 1, 4, 90, 0, 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1195 = DCLZ_R6
5283 : { 1196, 3, 1, 4, 10, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1196 = DDIV
5284 : { 1197, 3, 1, 4, 11, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1197 = DDIVU
5285 : { 1198, 0, 0, 4, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1198 = DERET
5286 : { 1199, 0, 0, 4, 91, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1199 = DERET_MM
5287 : { 1200, 0, 0, 4, 91, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1200 = DERET_MMR6
5288 : { 1201, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1201 = DEXT
5289 : { 1202, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1202 = DEXT64_32
5290 : { 1203, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1203 = DEXTM
5291 : { 1204, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1204 = DEXTU
5292 : { 1205, 1, 1, 4, 457, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1205 = DI
5293 : { 1206, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1206 = DINS
5294 : { 1207, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1207 = DINSM
5295 : { 1208, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1208 = DINSU
5296 : { 1209, 3, 1, 4, 465, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1209 = DIV
5297 : { 1210, 3, 1, 4, 466, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1210 = DIVU
5298 : { 1211, 3, 1, 4, 23, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1211 = DIVU_MMR6
5299 : { 1212, 3, 1, 4, 22, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1212 = DIV_MMR6
5300 : { 1213, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1213 = DIV_S_B
5301 : { 1214, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1214 = DIV_S_D
5302 : { 1215, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1215 = DIV_S_H
5303 : { 1216, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1216 = DIV_S_W
5304 : { 1217, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1217 = DIV_U_B
5305 : { 1218, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1218 = DIV_U_D
5306 : { 1219, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1219 = DIV_U_H
5307 : { 1220, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1220 = DIV_U_W
5308 : { 1221, 1, 1, 4, 93, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1221 = DI_MM
5309 : { 1222, 1, 1, 4, 93, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1222 = DI_MMR6
5310 : { 1223, 4, 1, 4, 94, 0, 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1223 = DLSA
5311 : { 1224, 4, 1, 4, 94, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1224 = DLSA_R6
5312 : { 1225, 3, 1, 4, 95, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1225 = DMFC0
5313 : { 1226, 2, 1, 4, 96, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1226 = DMFC1
5314 : { 1227, 3, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1227 = DMFC2
5315 : { 1228, 2, 2, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1228 = DMFC2_OCTEON
5316 : { 1229, 3, 1, 4, 98, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1229 = DMFGC0
5317 : { 1230, 3, 1, 4, 99, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1230 = DMOD
5318 : { 1231, 3, 1, 4, 100, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1231 = DMODU
5319 : { 1232, 1, 1, 4, 101, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1232 = DMT
5320 : { 1233, 3, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1233 = DMTC0
5321 : { 1234, 2, 1, 4, 103, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1234 = DMTC1
5322 : { 1235, 3, 1, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1235 = DMTC2
5323 : { 1236, 2, 2, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1236 = DMTC2_OCTEON
5324 : { 1237, 3, 1, 4, 105, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1237 = DMTGC0
5325 : { 1238, 3, 1, 4, 106, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1238 = DMUH
5326 : { 1239, 3, 1, 4, 107, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1239 = DMUHU
5327 : { 1240, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList11, OperandInfo57, -1 ,nullptr }, // Inst #1240 = DMUL
5328 : { 1241, 2, 0, 4, 8, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1241 = DMULT
5329 : { 1242, 2, 0, 4, 9, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1242 = DMULTu
5330 : { 1243, 3, 1, 4, 108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1243 = DMULU
5331 : { 1244, 3, 1, 4, 108, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1244 = DMUL_R6
5332 : { 1245, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1245 = DOTP_S_D
5333 : { 1246, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1246 = DOTP_S_H
5334 : { 1247, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1247 = DOTP_S_W
5335 : { 1248, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1248 = DOTP_U_D
5336 : { 1249, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1249 = DOTP_U_H
5337 : { 1250, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1250 = DOTP_U_W
5338 : { 1251, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1251 = DPADD_S_D
5339 : { 1252, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1252 = DPADD_S_H
5340 : { 1253, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1253 = DPADD_S_W
5341 : { 1254, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1254 = DPADD_U_D
5342 : { 1255, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1255 = DPADD_U_H
5343 : { 1256, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1256 = DPADD_U_W
5344 : { 1257, 4, 1, 4, 819, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1257 = DPAQX_SA_W_PH
5345 : { 1258, 4, 1, 4, 982, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1258 = DPAQX_SA_W_PH_MMR2
5346 : { 1259, 4, 1, 4, 820, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1259 = DPAQX_S_W_PH
5347 : { 1260, 4, 1, 4, 983, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1260 = DPAQX_S_W_PH_MMR2
5348 : { 1261, 4, 1, 4, 723, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1261 = DPAQ_SA_L_W
5349 : { 1262, 4, 1, 4, 870, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1262 = DPAQ_SA_L_W_MM
5350 : { 1263, 4, 1, 4, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1263 = DPAQ_S_W_PH
5351 : { 1264, 4, 1, 4, 871, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1264 = DPAQ_S_W_PH_MM
5352 : { 1265, 4, 1, 4, 725, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1265 = DPAU_H_QBL
5353 : { 1266, 4, 1, 4, 872, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1266 = DPAU_H_QBL_MM
5354 : { 1267, 4, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1267 = DPAU_H_QBR
5355 : { 1268, 4, 1, 4, 873, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1268 = DPAU_H_QBR_MM
5356 : { 1269, 4, 1, 4, 821, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1269 = DPAX_W_PH
5357 : { 1270, 4, 1, 4, 984, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1270 = DPAX_W_PH_MMR2
5358 : { 1271, 4, 1, 4, 818, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1271 = DPA_W_PH
5359 : { 1272, 4, 1, 4, 981, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1272 = DPA_W_PH_MMR2
5360 : { 1273, 2, 1, 4, 109, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1273 = DPOP
5361 : { 1274, 4, 1, 4, 824, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1274 = DPSQX_SA_W_PH
5362 : { 1275, 4, 1, 4, 987, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1275 = DPSQX_SA_W_PH_MMR2
5363 : { 1276, 4, 1, 4, 823, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1276 = DPSQX_S_W_PH
5364 : { 1277, 4, 1, 4, 986, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1277 = DPSQX_S_W_PH_MMR2
5365 : { 1278, 4, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1278 = DPSQ_SA_L_W
5366 : { 1279, 4, 1, 4, 874, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1279 = DPSQ_SA_L_W_MM
5367 : { 1280, 4, 1, 4, 728, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1280 = DPSQ_S_W_PH
5368 : { 1281, 4, 1, 4, 875, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1281 = DPSQ_S_W_PH_MM
5369 : { 1282, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1282 = DPSUB_S_D
5370 : { 1283, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1283 = DPSUB_S_H
5371 : { 1284, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1284 = DPSUB_S_W
5372 : { 1285, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1285 = DPSUB_U_D
5373 : { 1286, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1286 = DPSUB_U_H
5374 : { 1287, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1287 = DPSUB_U_W
5375 : { 1288, 4, 1, 4, 729, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1288 = DPSU_H_QBL
5376 : { 1289, 4, 1, 4, 876, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1289 = DPSU_H_QBL_MM
5377 : { 1290, 4, 1, 4, 730, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1290 = DPSU_H_QBR
5378 : { 1291, 4, 1, 4, 877, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1291 = DPSU_H_QBR_MM
5379 : { 1292, 4, 1, 4, 825, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1292 = DPSX_W_PH
5380 : { 1293, 4, 1, 4, 988, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1293 = DPSX_W_PH_MMR2
5381 : { 1294, 4, 1, 4, 822, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1294 = DPS_W_PH
5382 : { 1295, 4, 1, 4, 985, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1295 = DPS_W_PH_MMR2
5383 : { 1296, 3, 1, 4, 110, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1296 = DROTR
5384 : { 1297, 3, 1, 4, 111, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1297 = DROTR32
5385 : { 1298, 3, 1, 4, 112, 0, 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1298 = DROTRV
5386 : { 1299, 2, 1, 4, 113, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1299 = DSBH
5387 : { 1300, 2, 0, 4, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1300 = DSDIV
5388 : { 1301, 2, 1, 4, 114, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1301 = DSHD
5389 : { 1302, 3, 1, 4, 115, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1302 = DSLL
5390 : { 1303, 3, 1, 4, 116, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1303 = DSLL32
5391 : { 1304, 2, 1, 4, 115, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1304 = DSLL64_32
5392 : { 1305, 3, 1, 4, 117, 0, 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1305 = DSLLV
5393 : { 1306, 3, 1, 4, 118, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1306 = DSRA
5394 : { 1307, 3, 1, 4, 119, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1307 = DSRA32
5395 : { 1308, 3, 1, 4, 120, 0, 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1308 = DSRAV
5396 : { 1309, 3, 1, 4, 121, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1309 = DSRL
5397 : { 1310, 3, 1, 4, 122, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1310 = DSRL32
5398 : { 1311, 3, 1, 4, 123, 0, 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1311 = DSRLV
5399 : { 1312, 3, 1, 4, 124, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1312 = DSUB
5400 : { 1313, 3, 1, 4, 125, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1313 = DSUBu
5401 : { 1314, 2, 0, 4, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1314 = DUDIV
5402 : { 1315, 1, 1, 4, 126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1315 = DVP
5403 : { 1316, 1, 1, 4, 127, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1316 = DVPE
5404 : { 1317, 1, 1, 4, 126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1317 = DVP_MMR6
5405 : { 1318, 2, 0, 2, 38, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #1318 = DivRxRy16
5406 : { 1319, 2, 0, 2, 38, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #1319 = DivuRxRy16
5407 : { 1320, 0, 0, 4, 460, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1320 = EHB
5408 : { 1321, 0, 0, 4, 128, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1321 = EHB_MM
5409 : { 1322, 0, 0, 4, 128, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1322 = EHB_MMR6
5410 : { 1323, 1, 1, 4, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1323 = EI
5411 : { 1324, 1, 1, 4, 129, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1324 = EI_MM
5412 : { 1325, 1, 1, 4, 129, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1325 = EI_MMR6
5413 : { 1326, 1, 1, 4, 130, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1326 = EMT
5414 : { 1327, 0, 0, 4, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1327 = ERET
5415 : { 1328, 0, 0, 4, 374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1328 = ERETNC
5416 : { 1329, 0, 0, 4, 132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1329 = ERETNC_MMR6
5417 : { 1330, 0, 0, 4, 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1330 = ERET_MM
5418 : { 1331, 0, 0, 4, 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1331 = ERET_MMR6
5419 : { 1332, 1, 1, 4, 133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1332 = EVP
5420 : { 1333, 1, 1, 4, 134, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1333 = EVPE
5421 : { 1334, 1, 1, 4, 133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1334 = EVP_MMR6
5422 : { 1335, 4, 1, 4, 475, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1335 = EXT
5423 : { 1336, 3, 1, 4, 734, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo226, -1 ,nullptr }, // Inst #1336 = EXTP
5424 : { 1337, 3, 1, 4, 732, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo226, -1 ,nullptr }, // Inst #1337 = EXTPDP
5425 : { 1338, 3, 1, 4, 731, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo227, -1 ,nullptr }, // Inst #1338 = EXTPDPV
5426 : { 1339, 3, 1, 4, 878, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo227, -1 ,nullptr }, // Inst #1339 = EXTPDPV_MM
5427 : { 1340, 3, 1, 4, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo226, -1 ,nullptr }, // Inst #1340 = EXTPDP_MM
5428 : { 1341, 3, 1, 4, 733, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo227, -1 ,nullptr }, // Inst #1341 = EXTPV
5429 : { 1342, 3, 1, 4, 880, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo227, -1 ,nullptr }, // Inst #1342 = EXTPV_MM
5430 : { 1343, 3, 1, 4, 881, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo226, -1 ,nullptr }, // Inst #1343 = EXTP_MM
5431 : { 1344, 3, 1, 4, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1344 = EXTRV_RS_W
5432 : { 1345, 3, 1, 4, 882, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1345 = EXTRV_RS_W_MM
5433 : { 1346, 3, 1, 4, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1346 = EXTRV_R_W
5434 : { 1347, 3, 1, 4, 883, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1347 = EXTRV_R_W_MM
5435 : { 1348, 3, 1, 4, 693, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1348 = EXTRV_S_H
5436 : { 1349, 3, 1, 4, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1349 = EXTRV_S_H_MM
5437 : { 1350, 3, 1, 4, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1350 = EXTRV_W
5438 : { 1351, 3, 1, 4, 885, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo227, -1 ,nullptr }, // Inst #1351 = EXTRV_W_MM
5439 : { 1352, 3, 1, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1352 = EXTR_RS_W
5440 : { 1353, 3, 1, 4, 886, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1353 = EXTR_RS_W_MM
5441 : { 1354, 3, 1, 4, 696, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1354 = EXTR_R_W
5442 : { 1355, 3, 1, 4, 887, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1355 = EXTR_R_W_MM
5443 : { 1356, 3, 1, 4, 697, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1356 = EXTR_S_H
5444 : { 1357, 3, 1, 4, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1357 = EXTR_S_H_MM
5445 : { 1358, 3, 1, 4, 698, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1358 = EXTR_W
5446 : { 1359, 3, 1, 4, 889, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1359 = EXTR_W_MM
5447 : { 1360, 4, 1, 4, 92, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1360 = EXTS
5448 : { 1361, 4, 1, 4, 92, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1361 = EXTS32
5449 : { 1362, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1362 = EXT_MM
5450 : { 1363, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1363 = EXT_MMR6
5451 : { 1364, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1364 = FABS_D32
5452 : { 1365, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1365 = FABS_D32_MM
5453 : { 1366, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1366 = FABS_D64
5454 : { 1367, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1367 = FABS_D64_MM
5455 : { 1368, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1368 = FABS_S
5456 : { 1369, 2, 1, 4, 135, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1369 = FABS_S_MM
5457 : { 1370, 3, 1, 4, 635, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1370 = FADD_D
5458 : { 1371, 3, 1, 4, 605, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1371 = FADD_D32
5459 : { 1372, 3, 1, 4, 137, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1372 = FADD_D32_MM
5460 : { 1373, 3, 1, 4, 605, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1373 = FADD_D64
5461 : { 1374, 3, 1, 4, 137, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1374 = FADD_D64_MM
5462 : { 1375, 3, 1, 4, 606, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1375 = FADD_S
5463 : { 1376, 3, 1, 4, 138, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1376 = FADD_S_MM
5464 : { 1377, 3, 1, 4, 138, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1377 = FADD_S_MMR6
5465 : { 1378, 3, 1, 4, 635, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1378 = FADD_W
5466 : { 1379, 3, 1, 4, 554, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1379 = FCAF_D
5467 : { 1380, 3, 1, 4, 554, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1380 = FCAF_W
5468 : { 1381, 3, 1, 4, 555, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1381 = FCEQ_D
5469 : { 1382, 3, 1, 4, 555, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1382 = FCEQ_W
5470 : { 1383, 2, 1, 4, 576, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1383 = FCLASS_D
5471 : { 1384, 2, 1, 4, 576, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1384 = FCLASS_W
5472 : { 1385, 3, 1, 4, 556, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1385 = FCLE_D
5473 : { 1386, 3, 1, 4, 556, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1386 = FCLE_W
5474 : { 1387, 3, 1, 4, 557, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1387 = FCLT_D
5475 : { 1388, 3, 1, 4, 557, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1388 = FCLT_W
5476 : { 1389, 3, 0, 4, 615, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo232, -1 ,nullptr }, // Inst #1389 = FCMP_D32
5477 : { 1390, 3, 0, 4, 78, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo232, -1 ,nullptr }, // Inst #1390 = FCMP_D32_MM
5478 : { 1391, 3, 0, 4, 615, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo233, -1 ,nullptr }, // Inst #1391 = FCMP_D64
5479 : { 1392, 3, 0, 4, 616, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo234, -1 ,nullptr }, // Inst #1392 = FCMP_S32
5480 : { 1393, 3, 0, 4, 79, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo234, -1 ,nullptr }, // Inst #1393 = FCMP_S32_MM
5481 : { 1394, 3, 1, 4, 558, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1394 = FCNE_D
5482 : { 1395, 3, 1, 4, 558, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1395 = FCNE_W
5483 : { 1396, 3, 1, 4, 559, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1396 = FCOR_D
5484 : { 1397, 3, 1, 4, 559, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1397 = FCOR_W
5485 : { 1398, 3, 1, 4, 560, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1398 = FCUEQ_D
5486 : { 1399, 3, 1, 4, 560, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1399 = FCUEQ_W
5487 : { 1400, 3, 1, 4, 561, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1400 = FCULE_D
5488 : { 1401, 3, 1, 4, 561, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1401 = FCULE_W
5489 : { 1402, 3, 1, 4, 562, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1402 = FCULT_D
5490 : { 1403, 3, 1, 4, 562, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1403 = FCULT_W
5491 : { 1404, 3, 1, 4, 563, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1404 = FCUNE_D
5492 : { 1405, 3, 1, 4, 563, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1405 = FCUNE_W
5493 : { 1406, 3, 1, 4, 564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1406 = FCUN_D
5494 : { 1407, 3, 1, 4, 564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1407 = FCUN_W
5495 : { 1408, 3, 1, 4, 631, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1408 = FDIV_D
5496 : { 1409, 3, 1, 4, 619, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1409 = FDIV_D32
5497 : { 1410, 3, 1, 4, 139, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1410 = FDIV_D32_MM
5498 : { 1411, 3, 1, 4, 619, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1411 = FDIV_D64
5499 : { 1412, 3, 1, 4, 139, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1412 = FDIV_D64_MM
5500 : { 1413, 3, 1, 4, 618, 0, 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1413 = FDIV_S
5501 : { 1414, 3, 1, 4, 140, 0, 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1414 = FDIV_S_MM
5502 : { 1415, 3, 1, 4, 140, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1415 = FDIV_S_MMR6
5503 : { 1416, 3, 1, 4, 630, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1416 = FDIV_W
5504 : { 1417, 3, 1, 4, 573, 0, 0x6ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1417 = FEXDO_H
5505 : { 1418, 3, 1, 4, 573, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1418 = FEXDO_W
5506 : { 1419, 3, 1, 4, 530, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1419 = FEXP2_D
5507 : { 1420, 3, 1, 4, 530, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1420 = FEXP2_W
5508 : { 1421, 2, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1421 = FEXUPL_D
5509 : { 1422, 2, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1422 = FEXUPL_W
5510 : { 1423, 2, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1423 = FEXUPR_D
5511 : { 1424, 2, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1424 = FEXUPR_W
5512 : { 1425, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1425 = FFINT_S_D
5513 : { 1426, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1426 = FFINT_S_W
5514 : { 1427, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1427 = FFINT_U_D
5515 : { 1428, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1428 = FFINT_U_W
5516 : { 1429, 2, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1429 = FFQL_D
5517 : { 1430, 2, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1430 = FFQL_W
5518 : { 1431, 2, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1431 = FFQR_D
5519 : { 1432, 2, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1432 = FFQR_W
5520 : { 1433, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1433 = FILL_B
5521 : { 1434, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1434 = FILL_D
5522 : { 1435, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1435 = FILL_H
5523 : { 1436, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1436 = FILL_W
5524 : { 1437, 2, 1, 4, 581, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1437 = FLOG2_D
5525 : { 1438, 2, 1, 4, 581, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1438 = FLOG2_W
5526 : { 1439, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1439 = FLOOR_L_D64
5527 : { 1440, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1440 = FLOOR_L_D_MMR6
5528 : { 1441, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1441 = FLOOR_L_S
5529 : { 1442, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1442 = FLOOR_L_S_MMR6
5530 : { 1443, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1443 = FLOOR_W_D32
5531 : { 1444, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1444 = FLOOR_W_D64
5532 : { 1445, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1445 = FLOOR_W_D_MMR6
5533 : { 1446, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1446 = FLOOR_W_MM
5534 : { 1447, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1447 = FLOOR_W_S
5535 : { 1448, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1448 = FLOOR_W_S_MM
5536 : { 1449, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1449 = FLOOR_W_S_MMR6
5537 : { 1450, 4, 1, 4, 628, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1450 = FMADD_D
5538 : { 1451, 4, 1, 4, 628, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1451 = FMADD_W
5539 : { 1452, 3, 1, 4, 577, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1452 = FMAX_A_D
5540 : { 1453, 3, 1, 4, 577, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1453 = FMAX_A_W
5541 : { 1454, 3, 1, 4, 578, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1454 = FMAX_D
5542 : { 1455, 3, 1, 4, 578, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1455 = FMAX_W
5543 : { 1456, 3, 1, 4, 579, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1456 = FMIN_A_D
5544 : { 1457, 3, 1, 4, 579, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1457 = FMIN_A_W
5545 : { 1458, 3, 1, 4, 580, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1458 = FMIN_D
5546 : { 1459, 3, 1, 4, 580, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1459 = FMIN_W
5547 : { 1460, 2, 1, 4, 515, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1460 = FMOV_D32
5548 : { 1461, 2, 1, 4, 142, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1461 = FMOV_D32_MM
5549 : { 1462, 2, 1, 4, 515, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1462 = FMOV_D64
5550 : { 1463, 2, 1, 4, 142, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1463 = FMOV_D64_MM
5551 : { 1464, 2, 1, 4, 516, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1464 = FMOV_S
5552 : { 1465, 2, 1, 4, 143, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1465 = FMOV_S_MM
5553 : { 1466, 2, 1, 4, 143, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1466 = FMOV_S_MMR6
5554 : { 1467, 4, 1, 4, 629, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1467 = FMSUB_D
5555 : { 1468, 4, 1, 4, 629, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1468 = FMSUB_W
5556 : { 1469, 3, 1, 4, 634, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1469 = FMUL_D
5557 : { 1470, 3, 1, 4, 607, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1470 = FMUL_D32
5558 : { 1471, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1471 = FMUL_D32_MM
5559 : { 1472, 3, 1, 4, 607, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1472 = FMUL_D64
5560 : { 1473, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1473 = FMUL_D64_MM
5561 : { 1474, 3, 1, 4, 608, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1474 = FMUL_S
5562 : { 1475, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1475 = FMUL_S_MM
5563 : { 1476, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1476 = FMUL_S_MMR6
5564 : { 1477, 3, 1, 4, 634, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1477 = FMUL_W
5565 : { 1478, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1478 = FNEG_D32
5566 : { 1479, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1479 = FNEG_D32_MM
5567 : { 1480, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1480 = FNEG_D64
5568 : { 1481, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1481 = FNEG_D64_MM
5569 : { 1482, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1482 = FNEG_S
5570 : { 1483, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1483 = FNEG_S_MM
5571 : { 1484, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1484 = FNEG_S_MMR6
5572 : { 1485, 3, 2, 4, 147, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1485 = FORK
5573 : { 1486, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1486 = FRCP_D
5574 : { 1487, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1487 = FRCP_W
5575 : { 1488, 2, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1488 = FRINT_D
5576 : { 1489, 2, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1489 = FRINT_W
5577 : { 1490, 2, 1, 4, 623, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1490 = FRSQRT_D
5578 : { 1491, 2, 1, 4, 623, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1491 = FRSQRT_W
5579 : { 1492, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1492 = FSAF_D
5580 : { 1493, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1493 = FSAF_W
5581 : { 1494, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1494 = FSEQ_D
5582 : { 1495, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1495 = FSEQ_W
5583 : { 1496, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1496 = FSLE_D
5584 : { 1497, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1497 = FSLE_W
5585 : { 1498, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1498 = FSLT_D
5586 : { 1499, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1499 = FSLT_W
5587 : { 1500, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1500 = FSNE_D
5588 : { 1501, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1501 = FSNE_W
5589 : { 1502, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1502 = FSOR_D
5590 : { 1503, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1503 = FSOR_W
5591 : { 1504, 2, 1, 4, 633, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1504 = FSQRT_D
5592 : { 1505, 2, 1, 4, 621, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1505 = FSQRT_D32
5593 : { 1506, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1506 = FSQRT_D32_MM
5594 : { 1507, 2, 1, 4, 621, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1507 = FSQRT_D64
5595 : { 1508, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1508 = FSQRT_D64_MM
5596 : { 1509, 2, 1, 4, 620, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1509 = FSQRT_S
5597 : { 1510, 2, 1, 4, 148, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1510 = FSQRT_S_MM
5598 : { 1511, 2, 1, 4, 632, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1511 = FSQRT_W
5599 : { 1512, 3, 1, 4, 636, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1512 = FSUB_D
5600 : { 1513, 3, 1, 4, 609, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1513 = FSUB_D32
5601 : { 1514, 3, 1, 4, 149, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1514 = FSUB_D32_MM
5602 : { 1515, 3, 1, 4, 609, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1515 = FSUB_D64
5603 : { 1516, 3, 1, 4, 149, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1516 = FSUB_D64_MM
5604 : { 1517, 3, 1, 4, 610, 0, 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1517 = FSUB_S
5605 : { 1518, 3, 1, 4, 150, 0, 0x4ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1518 = FSUB_S_MM
5606 : { 1519, 3, 1, 4, 150, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1519 = FSUB_S_MMR6
5607 : { 1520, 3, 1, 4, 636, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1520 = FSUB_W
5608 : { 1521, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1521 = FSUEQ_D
5609 : { 1522, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1522 = FSUEQ_W
5610 : { 1523, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1523 = FSULE_D
5611 : { 1524, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1524 = FSULE_W
5612 : { 1525, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1525 = FSULT_D
5613 : { 1526, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1526 = FSULT_W
5614 : { 1527, 3, 1, 4, 552, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1527 = FSUNE_D
5615 : { 1528, 3, 1, 4, 552, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1528 = FSUNE_W
5616 : { 1529, 3, 1, 4, 553, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1529 = FSUN_D
5617 : { 1530, 3, 1, 4, 553, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1530 = FSUN_W
5618 : { 1531, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1531 = FTINT_S_D
5619 : { 1532, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1532 = FTINT_S_W
5620 : { 1533, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1533 = FTINT_U_D
5621 : { 1534, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1534 = FTINT_U_W
5622 : { 1535, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1535 = FTQ_H
5623 : { 1536, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1536 = FTQ_W
5624 : { 1537, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1537 = FTRUNC_S_D
5625 : { 1538, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1538 = FTRUNC_S_W
5626 : { 1539, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1539 = FTRUNC_U_D
5627 : { 1540, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1540 = FTRUNC_U_W
5628 : { 1541, 1, 0, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1541 = GINVI
5629 : { 1542, 1, 0, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1542 = GINVI_MMR6
5630 : { 1543, 2, 0, 4, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1543 = GINVT
5631 : { 1544, 2, 0, 4, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1544 = GINVT_MMR6
5632 : { 1545, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1545 = HADD_S_D
5633 : { 1546, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1546 = HADD_S_H
5634 : { 1547, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1547 = HADD_S_W
5635 : { 1548, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1548 = HADD_U_D
5636 : { 1549, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1549 = HADD_U_H
5637 : { 1550, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1550 = HADD_U_W
5638 : { 1551, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1551 = HSUB_S_D
5639 : { 1552, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1552 = HSUB_S_H
5640 : { 1553, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1553 = HSUB_S_W
5641 : { 1554, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1554 = HSUB_U_D
5642 : { 1555, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1555 = HSUB_U_H
5643 : { 1556, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1556 = HSUB_U_W
5644 : { 1557, 1, 0, 4, 153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1557 = HYPCALL
5645 : { 1558, 1, 0, 4, 153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1558 = HYPCALL_MM
5646 : { 1559, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1559 = ILVEV_B
5647 : { 1560, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1560 = ILVEV_D
5648 : { 1561, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1561 = ILVEV_H
5649 : { 1562, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1562 = ILVEV_W
5650 : { 1563, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1563 = ILVL_B
5651 : { 1564, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1564 = ILVL_D
5652 : { 1565, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1565 = ILVL_H
5653 : { 1566, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1566 = ILVL_W
5654 : { 1567, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1567 = ILVOD_B
5655 : { 1568, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1568 = ILVOD_D
5656 : { 1569, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1569 = ILVOD_H
5657 : { 1570, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1570 = ILVOD_W
5658 : { 1571, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1571 = ILVR_B
5659 : { 1572, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1572 = ILVR_D
5660 : { 1573, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1573 = ILVR_H
5661 : { 1574, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1574 = ILVR_W
5662 : { 1575, 5, 1, 4, 476, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1575 = INS
5663 : { 1576, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1576 = INSERT_B
5664 : { 1577, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1577 = INSERT_D
5665 : { 1578, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1578 = INSERT_H
5666 : { 1579, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1579 = INSERT_W
5667 : { 1580, 3, 1, 4, 699, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1580 = INSV
5668 : { 1581, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1581 = INSVE_B
5669 : { 1582, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1582 = INSVE_D
5670 : { 1583, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1583 = INSVE_H
5671 : { 1584, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1584 = INSVE_W
5672 : { 1585, 3, 1, 4, 890, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1585 = INSV_MM
5673 : { 1586, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1586 = INS_MM
5674 : { 1587, 5, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1587 = INS_MMR6
5675 : { 1588, 1, 0, 4, 375, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1588 = J
5676 : { 1589, 1, 0, 4, 398, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1589 = JAL
5677 : { 1590, 2, 1, 4, 399, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1590 = JALR
5678 : { 1591, 1, 0, 2, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1591 = JALR16_MM
5679 : { 1592, 2, 1, 4, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1592 = JALR64
5680 : { 1593, 1, 0, 2, 6, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1593 = JALRC16_MMR6
5681 : { 1594, 2, 1, 4, 155, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1594 = JALRC_HB_MMR6
5682 : { 1595, 2, 1, 4, 156, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1595 = JALRC_MMR6
5683 : { 1596, 1, 0, 2, 157, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1596 = JALRS16_MM
5684 : { 1597, 2, 1, 4, 157, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1597 = JALRS_MM
5685 : { 1598, 2, 1, 4, 400, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1598 = JALR_HB
5686 : { 1599, 2, 1, 4, 155, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1599 = JALR_HB64
5687 : { 1600, 2, 1, 4, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1600 = JALR_MM
5688 : { 1601, 1, 0, 4, 158, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1601 = JALS_MM
5689 : { 1602, 1, 0, 4, 401, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1602 = JALX
5690 : { 1603, 1, 0, 4, 154, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1603 = JALX_MM
5691 : { 1604, 1, 0, 4, 154, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1604 = JAL_MM
5692 : { 1605, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo95, -1 ,nullptr }, // Inst #1605 = JIALC
5693 : { 1606, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo93, -1 ,nullptr }, // Inst #1606 = JIALC64
5694 : { 1607, 2, 0, 4, 159, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo95, -1 ,nullptr }, // Inst #1607 = JIALC_MMR6
5695 : { 1608, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #1608 = JIC
5696 : { 1609, 2, 0, 4, 160, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr }, // Inst #1609 = JIC64
5697 : { 1610, 2, 0, 4, 160, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #1610 = JIC_MMR6
5698 : { 1611, 1, 0, 4, 376, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1611 = JR
5699 : { 1612, 1, 0, 2, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1612 = JR16_MM
5700 : { 1613, 1, 0, 4, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1613 = JR64
5701 : { 1614, 1, 0, 2, 161, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1614 = JRADDIUSP
5702 : { 1615, 1, 0, 2, 162, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1615 = JRC16_MM
5703 : { 1616, 1, 0, 2, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1616 = JRC16_MMR6
5704 : { 1617, 1, 0, 2, 161, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1617 = JRCADDIUSP_MMR6
5705 : { 1618, 1, 0, 4, 377, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1618 = JR_HB
5706 : { 1619, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1619 = JR_HB64
5707 : { 1620, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1620 = JR_HB64_R6
5708 : { 1621, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1621 = JR_HB_R6
5709 : { 1622, 1, 0, 4, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1622 = JR_MM
5710 : { 1623, 1, 0, 4, 24, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1623 = J_MM
5711 : { 1624, 1, 0, 6, 38, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1624 = Jal16
5712 : { 1625, 1, 0, 6, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1625 = JalB16
5713 : { 1626, 0, 0, 2, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1626 = JrRa16
5714 : { 1627, 0, 0, 2, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1627 = JrcRa16
5715 : { 1628, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1628 = JrcRx16
5716 : { 1629, 1, 0, 2, 156, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo253, -1 ,nullptr }, // Inst #1629 = JumpLinkReg16
5717 : { 1630, 3, 1, 4, 412, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1630 = LB
5718 : { 1631, 3, 1, 4, 164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1631 = LB64
5719 : { 1632, 3, 1, 4, 422, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1632 = LBE
5720 : { 1633, 3, 1, 4, 165, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1633 = LBE_MM
5721 : { 1634, 3, 1, 2, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1634 = LBU16_MM
5722 : { 1635, 3, 1, 4, 735, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1635 = LBUX
5723 : { 1636, 3, 1, 4, 891, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1636 = LBUX_MM
5724 : { 1637, 3, 1, 4, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1637 = LBU_MMR6
5725 : { 1638, 3, 1, 4, 164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1638 = LB_MM
5726 : { 1639, 3, 1, 4, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1639 = LB_MMR6
5727 : { 1640, 3, 1, 4, 413, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1640 = LBu
5728 : { 1641, 3, 1, 4, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1641 = LBu64
5729 : { 1642, 3, 1, 4, 423, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1642 = LBuE
5730 : { 1643, 3, 1, 4, 167, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1643 = LBuE_MM
5731 : { 1644, 3, 1, 4, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1644 = LBu_MM
5732 : { 1645, 3, 1, 4, 168, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1645 = LD
5733 : { 1646, 3, 1, 4, 681, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1646 = LDC1
5734 : { 1647, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1647 = LDC164
5735 : { 1648, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1648 = LDC1_D64_MMR6
5736 : { 1649, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1649 = LDC1_MM
5737 : { 1650, 3, 1, 4, 420, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1650 = LDC2
5738 : { 1651, 3, 1, 4, 170, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1651 = LDC2_MMR6
5739 : { 1652, 3, 1, 4, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1652 = LDC2_R6
5740 : { 1653, 3, 1, 4, 421, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1653 = LDC3
5741 : { 1654, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1654 = LDI_B
5742 : { 1655, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1655 = LDI_D
5743 : { 1656, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1656 = LDI_H
5744 : { 1657, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1657 = LDI_W
5745 : { 1658, 4, 1, 4, 172, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1658 = LDL
5746 : { 1659, 2, 1, 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1659 = LDPC
5747 : { 1660, 4, 1, 4, 174, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1660 = LDR
5748 : { 1661, 3, 1, 4, 682, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1661 = LDXC1
5749 : { 1662, 3, 1, 4, 175, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1662 = LDXC164
5750 : { 1663, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1663 = LD_B
5751 : { 1664, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1664 = LD_D
5752 : { 1665, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #1665 = LD_H
5753 : { 1666, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1666 = LD_W
5754 : { 1667, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1667 = LEA_ADDiu
5755 : { 1668, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1668 = LEA_ADDiu64
5756 : { 1669, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1669 = LEA_ADDiu_MM
5757 : { 1670, 3, 1, 4, 414, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1670 = LH
5758 : { 1671, 3, 1, 4, 176, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1671 = LH64
5759 : { 1672, 3, 1, 4, 424, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1672 = LHE
5760 : { 1673, 3, 1, 4, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1673 = LHE_MM
5761 : { 1674, 3, 1, 2, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1674 = LHU16_MM
5762 : { 1675, 3, 1, 4, 736, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1675 = LHX
5763 : { 1676, 3, 1, 4, 892, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1676 = LHX_MM
5764 : { 1677, 3, 1, 4, 176, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1677 = LH_MM
5765 : { 1678, 3, 1, 4, 415, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1678 = LHu
5766 : { 1679, 3, 1, 4, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1679 = LHu64
5767 : { 1680, 3, 1, 4, 425, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1680 = LHuE
5768 : { 1681, 3, 1, 4, 179, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1681 = LHuE_MM
5769 : { 1682, 3, 1, 4, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1682 = LHu_MM
5770 : { 1683, 2, 1, 2, 180, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1683 = LI16_MM
5771 : { 1684, 2, 1, 2, 180, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1684 = LI16_MMR6
5772 : { 1685, 3, 1, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1685 = LL
5773 : { 1686, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1686 = LL64
5774 : { 1687, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1687 = LL64_R6
5775 : { 1688, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1688 = LLD
5776 : { 1689, 3, 1, 4, 182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1689 = LLD_R6
5777 : { 1690, 3, 1, 4, 427, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1690 = LLE
5778 : { 1691, 3, 1, 4, 183, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1691 = LLE_MM
5779 : { 1692, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1692 = LL_MM
5780 : { 1693, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1693 = LL_MMR6
5781 : { 1694, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1694 = LL_R6
5782 : { 1695, 4, 1, 4, 494, 0, 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1695 = LSA
5783 : { 1696, 4, 1, 4, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1696 = LSA_MMR6
5784 : { 1697, 4, 1, 4, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1697 = LSA_R6
5785 : { 1698, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1698 = LUI_MMR6
5786 : { 1699, 3, 1, 4, 685, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1699 = LUXC1
5787 : { 1700, 3, 1, 4, 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1700 = LUXC164
5788 : { 1701, 3, 1, 4, 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1701 = LUXC1_MM
5789 : { 1702, 2, 1, 4, 359, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1702 = LUi
5790 : { 1703, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1703 = LUi64
5791 : { 1704, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1704 = LUi_MM
5792 : { 1705, 3, 1, 4, 416, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1705 = LW
5793 : { 1706, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1706 = LW16_MM
5794 : { 1707, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1707 = LW64
5795 : { 1708, 3, 1, 4, 683, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1708 = LWC1
5796 : { 1709, 3, 1, 4, 188, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1709 = LWC1_MM
5797 : { 1710, 3, 1, 4, 418, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1710 = LWC2
5798 : { 1711, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1711 = LWC2_MMR6
5799 : { 1712, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1712 = LWC2_R6
5800 : { 1713, 3, 1, 4, 419, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1713 = LWC3
5801 : { 1714, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #1714 = LWDSP
5802 : { 1715, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #1715 = LWDSP_MM
5803 : { 1716, 3, 1, 4, 426, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1716 = LWE
5804 : { 1717, 3, 1, 4, 191, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1717 = LWE_MM
5805 : { 1718, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1718 = LWGP_MM
5806 : { 1719, 4, 1, 4, 429, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1719 = LWL
5807 : { 1720, 4, 1, 4, 192, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1720 = LWL64
5808 : { 1721, 4, 1, 4, 431, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1721 = LWLE
5809 : { 1722, 4, 1, 4, 193, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1722 = LWLE_MM
5810 : { 1723, 4, 1, 4, 192, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1723 = LWL_MM
5811 : { 1724, 3, 1, 2, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1724 = LWM16_MM
5812 : { 1725, 3, 1, 2, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1725 = LWM16_MMR6
5813 : { 1726, 3, 1, 4, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1726 = LWM32_MM
5814 : { 1727, 2, 1, 4, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1727 = LWPC
5815 : { 1728, 2, 1, 4, 195, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1728 = LWPC_MMR6
5816 : { 1729, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #1729 = LWP_MM
5817 : { 1730, 4, 1, 4, 430, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1730 = LWR
5818 : { 1731, 4, 1, 4, 197, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1731 = LWR64
5819 : { 1732, 4, 1, 4, 432, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1732 = LWRE
5820 : { 1733, 4, 1, 4, 198, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1733 = LWRE_MM
5821 : { 1734, 4, 1, 4, 197, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1734 = LWR_MM
5822 : { 1735, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #1735 = LWSP_MM
5823 : { 1736, 2, 1, 4, 199, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1736 = LWUPC
5824 : { 1737, 3, 1, 4, 200, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1737 = LWU_MM
5825 : { 1738, 3, 1, 4, 737, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1738 = LWX
5826 : { 1739, 3, 1, 4, 684, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1739 = LWXC1
5827 : { 1740, 3, 1, 4, 201, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1740 = LWXC1_MM
5828 : { 1741, 3, 1, 4, 202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1741 = LWXS_MM
5829 : { 1742, 3, 1, 4, 893, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1742 = LWX_MM
5830 : { 1743, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1743 = LW_MM
5831 : { 1744, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1744 = LW_MMR6
5832 : { 1745, 3, 1, 4, 200, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1745 = LWu
5833 : { 1746, 3, 1, 4, 164, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1746 = LbRxRyOffMemX16
5834 : { 1747, 3, 1, 4, 166, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1747 = LbuRxRyOffMemX16
5835 : { 1748, 3, 1, 4, 176, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1748 = LhRxRyOffMemX16
5836 : { 1749, 3, 1, 4, 178, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1749 = LhuRxRyOffMemX16
5837 : { 1750, 2, 1, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1750 = LiRxImm16
5838 : { 1751, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1751 = LiRxImmAlignX16
5839 : { 1752, 2, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1752 = LiRxImmX16
5840 : { 1753, 3, 1, 2, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1753 = LwRxPcTcp16
5841 : { 1754, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1754 = LwRxPcTcpX16
5842 : { 1755, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1755 = LwRxRyOffMemX16
5843 : { 1756, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1756 = LwRxSpImmX16
5844 : { 1757, 2, 0, 4, 470, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1757 = MADD
5845 : { 1758, 4, 1, 4, 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1758 = MADDF_D
5846 : { 1759, 4, 1, 4, 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1759 = MADDF_D_MMR6
5847 : { 1760, 4, 1, 4, 204, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1760 = MADDF_S
5848 : { 1761, 4, 1, 4, 204, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1761 = MADDF_S_MMR6
5849 : { 1762, 4, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1762 = MADDR_Q_H
5850 : { 1763, 4, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1763 = MADDR_Q_W
5851 : { 1764, 2, 0, 4, 471, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1764 = MADDU
5852 : { 1765, 4, 1, 4, 738, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1765 = MADDU_DSP
5853 : { 1766, 4, 1, 4, 894, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1766 = MADDU_DSP_MM
5854 : { 1767, 2, 0, 4, 14, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1767 = MADDU_MM
5855 : { 1768, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1768 = MADDV_B
5856 : { 1769, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1769 = MADDV_D
5857 : { 1770, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1770 = MADDV_H
5858 : { 1771, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1771 = MADDV_W
5859 : { 1772, 4, 1, 4, 649, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1772 = MADD_D32
5860 : { 1773, 4, 1, 4, 205, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1773 = MADD_D32_MM
5861 : { 1774, 4, 1, 4, 649, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1774 = MADD_D64
5862 : { 1775, 4, 1, 4, 739, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1775 = MADD_DSP
5863 : { 1776, 4, 1, 4, 895, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1776 = MADD_DSP_MM
5864 : { 1777, 2, 0, 4, 13, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1777 = MADD_MM
5865 : { 1778, 4, 1, 4, 644, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1778 = MADD_Q_H
5866 : { 1779, 4, 1, 4, 644, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1779 = MADD_Q_W
5867 : { 1780, 4, 1, 4, 650, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1780 = MADD_S
5868 : { 1781, 4, 1, 4, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1781 = MADD_S_MM
5869 : { 1782, 4, 1, 4, 740, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1782 = MAQ_SA_W_PHL
5870 : { 1783, 4, 1, 4, 896, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1783 = MAQ_SA_W_PHL_MM
5871 : { 1784, 4, 1, 4, 741, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1784 = MAQ_SA_W_PHR
5872 : { 1785, 4, 1, 4, 897, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1785 = MAQ_SA_W_PHR_MM
5873 : { 1786, 4, 1, 4, 742, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1786 = MAQ_S_W_PHL
5874 : { 1787, 4, 1, 4, 898, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1787 = MAQ_S_W_PHL_MM
5875 : { 1788, 4, 1, 4, 743, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1788 = MAQ_S_W_PHR
5876 : { 1789, 4, 1, 4, 899, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #1789 = MAQ_S_W_PHR_MM
5877 : { 1790, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1790 = MAXA_D
5878 : { 1791, 3, 1, 4, 208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1791 = MAXA_D_MMR6
5879 : { 1792, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1792 = MAXA_S
5880 : { 1793, 3, 1, 4, 210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1793 = MAXA_S_MMR6
5881 : { 1794, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1794 = MAXI_S_B
5882 : { 1795, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1795 = MAXI_S_D
5883 : { 1796, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1796 = MAXI_S_H
5884 : { 1797, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1797 = MAXI_S_W
5885 : { 1798, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1798 = MAXI_U_B
5886 : { 1799, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1799 = MAXI_U_D
5887 : { 1800, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1800 = MAXI_U_H
5888 : { 1801, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1801 = MAXI_U_W
5889 : { 1802, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1802 = MAX_A_B
5890 : { 1803, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1803 = MAX_A_D
5891 : { 1804, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1804 = MAX_A_H
5892 : { 1805, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1805 = MAX_A_W
5893 : { 1806, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1806 = MAX_D
5894 : { 1807, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1807 = MAX_D_MMR6
5895 : { 1808, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1808 = MAX_S
5896 : { 1809, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1809 = MAX_S_B
5897 : { 1810, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1810 = MAX_S_D
5898 : { 1811, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1811 = MAX_S_H
5899 : { 1812, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1812 = MAX_S_MMR6
5900 : { 1813, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1813 = MAX_S_W
5901 : { 1814, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1814 = MAX_U_B
5902 : { 1815, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1815 = MAX_U_D
5903 : { 1816, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1816 = MAX_U_H
5904 : { 1817, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1817 = MAX_U_W
5905 : { 1818, 3, 1, 4, 408, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1818 = MFC0
5906 : { 1819, 3, 1, 4, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1819 = MFC0_MMR6
5907 : { 1820, 2, 1, 4, 667, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1820 = MFC1
5908 : { 1821, 2, 1, 4, 667, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1821 = MFC1_D64
5909 : { 1822, 2, 1, 4, 5, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1822 = MFC1_MM
5910 : { 1823, 2, 1, 4, 5, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1823 = MFC1_MMR6
5911 : { 1824, 3, 1, 4, 410, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1824 = MFC2
5912 : { 1825, 2, 1, 4, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1825 = MFC2_MMR6
5913 : { 1826, 3, 1, 4, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1826 = MFGC0
5914 : { 1827, 3, 1, 4, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1827 = MFGC0_MM
5915 : { 1828, 3, 1, 4, 214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1828 = MFHC0_MMR6
5916 : { 1829, 2, 1, 4, 668, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1829 = MFHC1_D32
5917 : { 1830, 2, 1, 4, 215, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1830 = MFHC1_D32_MM
5918 : { 1831, 2, 1, 4, 668, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1831 = MFHC1_D64
5919 : { 1832, 2, 1, 4, 215, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1832 = MFHC1_D64_MM
5920 : { 1833, 2, 1, 4, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1833 = MFHC2_MMR6
5921 : { 1834, 3, 1, 4, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1834 = MFHGC0
5922 : { 1835, 3, 1, 4, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1835 = MFHGC0_MM
5923 : { 1836, 1, 1, 4, 459, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1836 = MFHI
5924 : { 1837, 1, 1, 2, 15, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1837 = MFHI16_MM
5925 : { 1838, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1838 = MFHI64
5926 : { 1839, 2, 1, 4, 744, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1839 = MFHI_DSP
5927 : { 1840, 2, 1, 4, 900, 0, 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1840 = MFHI_DSP_MM
5928 : { 1841, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1841 = MFHI_MM
5929 : { 1842, 1, 1, 4, 459, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1842 = MFLO
5930 : { 1843, 1, 1, 2, 15, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1843 = MFLO16_MM
5931 : { 1844, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1844 = MFLO64
5932 : { 1845, 2, 1, 4, 745, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1845 = MFLO_DSP
5933 : { 1846, 2, 1, 4, 901, 0, 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1846 = MFLO_DSP_MM
5934 : { 1847, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1847 = MFLO_MM
5935 : { 1848, 5, 1, 4, 217, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1848 = MFTR
5936 : { 1849, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1849 = MINA_D
5937 : { 1850, 3, 1, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1850 = MINA_D_MMR6
5938 : { 1851, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1851 = MINA_S
5939 : { 1852, 3, 1, 4, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1852 = MINA_S_MMR6
5940 : { 1853, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1853 = MINI_S_B
5941 : { 1854, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1854 = MINI_S_D
5942 : { 1855, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1855 = MINI_S_H
5943 : { 1856, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1856 = MINI_S_W
5944 : { 1857, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1857 = MINI_U_B
5945 : { 1858, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1858 = MINI_U_D
5946 : { 1859, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1859 = MINI_U_H
5947 : { 1860, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1860 = MINI_U_W
5948 : { 1861, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1861 = MIN_A_B
5949 : { 1862, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1862 = MIN_A_D
5950 : { 1863, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1863 = MIN_A_H
5951 : { 1864, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1864 = MIN_A_W
5952 : { 1865, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1865 = MIN_D
5953 : { 1866, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1866 = MIN_D_MMR6
5954 : { 1867, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1867 = MIN_S
5955 : { 1868, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1868 = MIN_S_B
5956 : { 1869, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1869 = MIN_S_D
5957 : { 1870, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1870 = MIN_S_H
5958 : { 1871, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1871 = MIN_S_MMR6
5959 : { 1872, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1872 = MIN_S_W
5960 : { 1873, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1873 = MIN_U_B
5961 : { 1874, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1874 = MIN_U_D
5962 : { 1875, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1875 = MIN_U_H
5963 : { 1876, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1876 = MIN_U_W
5964 : { 1877, 3, 1, 4, 222, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1877 = MOD
5965 : { 1878, 3, 1, 4, 746, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1878 = MODSUB
5966 : { 1879, 3, 1, 4, 902, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1879 = MODSUB_MM
5967 : { 1880, 3, 1, 4, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1880 = MODU
5968 : { 1881, 3, 1, 4, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1881 = MODU_MMR6
5969 : { 1882, 3, 1, 4, 222, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1882 = MOD_MMR6
5970 : { 1883, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1883 = MOD_S_B
5971 : { 1884, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1884 = MOD_S_D
5972 : { 1885, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1885 = MOD_S_H
5973 : { 1886, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1886 = MOD_S_W
5974 : { 1887, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1887 = MOD_U_B
5975 : { 1888, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1888 = MOD_U_D
5976 : { 1889, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1889 = MOD_U_H
5977 : { 1890, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1890 = MOD_U_W
5978 : { 1891, 2, 1, 2, 224, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1891 = MOVE16_MM
5979 : { 1892, 2, 1, 2, 224, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1892 = MOVE16_MMR6
5980 : { 1893, 4, 2, 2, 903, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1893 = MOVEP_MM
5981 : { 1894, 4, 2, 2, 904, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1894 = MOVEP_MMR6
5982 : { 1895, 2, 1, 4, 526, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1895 = MOVE_V
5983 : { 1896, 4, 1, 4, 511, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1896 = MOVF_D32
5984 : { 1897, 4, 1, 4, 225, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1897 = MOVF_D32_MM
5985 : { 1898, 4, 1, 4, 511, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1898 = MOVF_D64
5986 : { 1899, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1899 = MOVF_I
5987 : { 1900, 4, 1, 4, 226, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1900 = MOVF_I64
5988 : { 1901, 4, 1, 4, 226, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1901 = MOVF_I_MM
5989 : { 1902, 4, 1, 4, 512, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1902 = MOVF_S
5990 : { 1903, 4, 1, 4, 227, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1903 = MOVF_S_MM
5991 : { 1904, 4, 1, 4, 228, 0, 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1904 = MOVN_I64_D64
5992 : { 1905, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1905 = MOVN_I64_I
5993 : { 1906, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1906 = MOVN_I64_I64
5994 : { 1907, 4, 1, 4, 230, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1907 = MOVN_I64_S
5995 : { 1908, 4, 1, 4, 677, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1908 = MOVN_I_D32
5996 : { 1909, 4, 1, 4, 228, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1909 = MOVN_I_D32_MM
5997 : { 1910, 4, 1, 4, 677, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1910 = MOVN_I_D64
5998 : { 1911, 4, 1, 4, 463, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1911 = MOVN_I_I
5999 : { 1912, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1912 = MOVN_I_I64
6000 : { 1913, 4, 1, 4, 905, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1913 = MOVN_I_MM
6001 : { 1914, 4, 1, 4, 678, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1914 = MOVN_I_S
6002 : { 1915, 4, 1, 4, 230, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1915 = MOVN_I_S_MM
6003 : { 1916, 4, 1, 4, 513, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1916 = MOVT_D32
6004 : { 1917, 4, 1, 4, 231, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1917 = MOVT_D32_MM
6005 : { 1918, 4, 1, 4, 513, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1918 = MOVT_D64
6006 : { 1919, 4, 1, 4, 670, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1919 = MOVT_I
6007 : { 1920, 4, 1, 4, 232, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1920 = MOVT_I64
6008 : { 1921, 4, 1, 4, 232, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1921 = MOVT_I_MM
6009 : { 1922, 4, 1, 4, 514, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1922 = MOVT_S
6010 : { 1923, 4, 1, 4, 233, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1923 = MOVT_S_MM
6011 : { 1924, 4, 1, 4, 234, 0, 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1924 = MOVZ_I64_D64
6012 : { 1925, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1925 = MOVZ_I64_I
6013 : { 1926, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1926 = MOVZ_I64_I64
6014 : { 1927, 4, 1, 4, 236, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1927 = MOVZ_I64_S
6015 : { 1928, 4, 1, 4, 679, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1928 = MOVZ_I_D32
6016 : { 1929, 4, 1, 4, 234, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1929 = MOVZ_I_D32_MM
6017 : { 1930, 4, 1, 4, 679, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1930 = MOVZ_I_D64
6018 : { 1931, 4, 1, 4, 464, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1931 = MOVZ_I_I
6019 : { 1932, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1932 = MOVZ_I_I64
6020 : { 1933, 4, 1, 4, 906, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1933 = MOVZ_I_MM
6021 : { 1934, 4, 1, 4, 680, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1934 = MOVZ_I_S
6022 : { 1935, 4, 1, 4, 236, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1935 = MOVZ_I_S_MM
6023 : { 1936, 2, 0, 4, 472, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1936 = MSUB
6024 : { 1937, 4, 1, 4, 237, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1937 = MSUBF_D
6025 : { 1938, 4, 1, 4, 237, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1938 = MSUBF_D_MMR6
6026 : { 1939, 4, 1, 4, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1939 = MSUBF_S
6027 : { 1940, 4, 1, 4, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1940 = MSUBF_S_MMR6
6028 : { 1941, 4, 1, 4, 645, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1941 = MSUBR_Q_H
6029 : { 1942, 4, 1, 4, 645, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1942 = MSUBR_Q_W
6030 : { 1943, 2, 0, 4, 473, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1943 = MSUBU
6031 : { 1944, 4, 1, 4, 747, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1944 = MSUBU_DSP
6032 : { 1945, 4, 1, 4, 907, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1945 = MSUBU_DSP_MM
6033 : { 1946, 2, 0, 4, 17, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1946 = MSUBU_MM
6034 : { 1947, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1947 = MSUBV_B
6035 : { 1948, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1948 = MSUBV_D
6036 : { 1949, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1949 = MSUBV_H
6037 : { 1950, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1950 = MSUBV_W
6038 : { 1951, 4, 1, 4, 651, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1951 = MSUB_D32
6039 : { 1952, 4, 1, 4, 239, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1952 = MSUB_D32_MM
6040 : { 1953, 4, 1, 4, 651, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1953 = MSUB_D64
6041 : { 1954, 4, 1, 4, 748, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1954 = MSUB_DSP
6042 : { 1955, 4, 1, 4, 908, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1955 = MSUB_DSP_MM
6043 : { 1956, 2, 0, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1956 = MSUB_MM
6044 : { 1957, 4, 1, 4, 646, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1957 = MSUB_Q_H
6045 : { 1958, 4, 1, 4, 646, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1958 = MSUB_Q_W
6046 : { 1959, 4, 1, 4, 652, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1959 = MSUB_S
6047 : { 1960, 4, 1, 4, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1960 = MSUB_S_MM
6048 : { 1961, 3, 1, 4, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1961 = MTC0
6049 : { 1962, 3, 1, 4, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1962 = MTC0_MMR6
6050 : { 1963, 2, 1, 4, 658, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1963 = MTC1
6051 : { 1964, 2, 1, 4, 658, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1964 = MTC1_D64
6052 : { 1965, 2, 1, 4, 4, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1965 = MTC1_D64_MM
6053 : { 1966, 2, 1, 4, 4, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1966 = MTC1_MM
6054 : { 1967, 2, 1, 4, 4, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1967 = MTC1_MMR6
6055 : { 1968, 3, 1, 4, 411, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #1968 = MTC2
6056 : { 1969, 2, 1, 4, 242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1969 = MTC2_MMR6
6057 : { 1970, 3, 1, 4, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1970 = MTGC0
6058 : { 1971, 3, 1, 4, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1971 = MTGC0_MM
6059 : { 1972, 3, 1, 4, 244, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1972 = MTHC0_MMR6
6060 : { 1973, 3, 1, 4, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1973 = MTHC1_D32
6061 : { 1974, 3, 1, 4, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1974 = MTHC1_D32_MM
6062 : { 1975, 3, 1, 4, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1975 = MTHC1_D64
6063 : { 1976, 3, 1, 4, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1976 = MTHC1_D64_MM
6064 : { 1977, 2, 1, 4, 242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1977 = MTHC2_MMR6
6065 : { 1978, 3, 1, 4, 246, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1978 = MTHGC0
6066 : { 1979, 3, 1, 4, 246, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1979 = MTHGC0_MM
6067 : { 1980, 1, 0, 4, 474, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo44, -1 ,nullptr }, // Inst #1980 = MTHI
6068 : { 1981, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo81, -1 ,nullptr }, // Inst #1981 = MTHI64
6069 : { 1982, 2, 1, 4, 701, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #1982 = MTHI_DSP
6070 : { 1983, 2, 1, 4, 909, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #1983 = MTHI_DSP_MM
6071 : { 1984, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo44, -1 ,nullptr }, // Inst #1984 = MTHI_MM
6072 : { 1985, 3, 1, 4, 700, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo311, -1 ,nullptr }, // Inst #1985 = MTHLIP
6073 : { 1986, 3, 1, 4, 910, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo311, -1 ,nullptr }, // Inst #1986 = MTHLIP_MM
6074 : { 1987, 1, 0, 4, 474, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo44, -1 ,nullptr }, // Inst #1987 = MTLO
6075 : { 1988, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo81, -1 ,nullptr }, // Inst #1988 = MTLO64
6076 : { 1989, 2, 1, 4, 702, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #1989 = MTLO_DSP
6077 : { 1990, 2, 1, 4, 911, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #1990 = MTLO_DSP_MM
6078 : { 1991, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo44, -1 ,nullptr }, // Inst #1991 = MTLO_MM
6079 : { 1992, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo81, -1 ,nullptr }, // Inst #1992 = MTM0
6080 : { 1993, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo81, -1 ,nullptr }, // Inst #1993 = MTM1
6081 : { 1994, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo81, -1 ,nullptr }, // Inst #1994 = MTM2
6082 : { 1995, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo81, -1 ,nullptr }, // Inst #1995 = MTP0
6083 : { 1996, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo81, -1 ,nullptr }, // Inst #1996 = MTP1
6084 : { 1997, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo81, -1 ,nullptr }, // Inst #1997 = MTP2
6085 : { 1998, 5, 1, 4, 247, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1998 = MTTR
6086 : { 1999, 3, 1, 4, 248, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1999 = MUH
6087 : { 2000, 3, 1, 4, 249, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2000 = MUHU
6088 : { 2001, 3, 1, 4, 249, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2001 = MUHU_MMR6
6089 : { 2002, 3, 1, 4, 248, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2002 = MUH_MMR6
6090 : { 2003, 3, 1, 4, 467, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo58, -1 ,nullptr }, // Inst #2003 = MUL
6091 : { 2004, 3, 1, 4, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #2004 = MULEQ_S_W_PHL
6092 : { 2005, 3, 1, 4, 912, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #2005 = MULEQ_S_W_PHL_MM
6093 : { 2006, 3, 1, 4, 750, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #2006 = MULEQ_S_W_PHR
6094 : { 2007, 3, 1, 4, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #2007 = MULEQ_S_W_PHR_MM
6095 : { 2008, 3, 1, 4, 751, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2008 = MULEU_S_PH_QBL
6096 : { 2009, 3, 1, 4, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2009 = MULEU_S_PH_QBL_MM
6097 : { 2010, 3, 1, 4, 752, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2010 = MULEU_S_PH_QBR
6098 : { 2011, 3, 1, 4, 915, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2011 = MULEU_S_PH_QBR_MM
6099 : { 2012, 3, 1, 4, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2012 = MULQ_RS_PH
6100 : { 2013, 3, 1, 4, 916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2013 = MULQ_RS_PH_MM
6101 : { 2014, 3, 1, 4, 828, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #2014 = MULQ_RS_W
6102 : { 2015, 3, 1, 4, 991, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #2015 = MULQ_RS_W_MMR2
6103 : { 2016, 3, 1, 4, 829, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2016 = MULQ_S_PH
6104 : { 2017, 3, 1, 4, 992, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2017 = MULQ_S_PH_MMR2
6105 : { 2018, 3, 1, 4, 830, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #2018 = MULQ_S_W
6106 : { 2019, 3, 1, 4, 993, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #2019 = MULQ_S_W_MMR2
6107 : { 2020, 3, 1, 4, 647, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2020 = MULR_Q_H
6108 : { 2021, 3, 1, 4, 647, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2021 = MULR_Q_W
6109 : { 2022, 4, 1, 4, 754, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #2022 = MULSAQ_S_W_PH
6110 : { 2023, 4, 1, 4, 917, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo223, -1 ,nullptr }, // Inst #2023 = MULSAQ_S_W_PH_MM
6111 : { 2024, 4, 1, 4, 831, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #2024 = MULSA_W_PH
6112 : { 2025, 4, 1, 4, 994, 0, 0x6ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #2025 = MULSA_W_PH_MMR2
6113 : { 2026, 2, 0, 4, 468, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2026 = MULT
6114 : { 2027, 3, 1, 4, 755, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2027 = MULTU_DSP
6115 : { 2028, 3, 1, 4, 918, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2028 = MULTU_DSP_MM
6116 : { 2029, 3, 1, 4, 756, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2029 = MULT_DSP
6117 : { 2030, 3, 1, 4, 919, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2030 = MULT_DSP_MM
6118 : { 2031, 2, 0, 4, 19, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2031 = MULT_MM
6119 : { 2032, 2, 0, 4, 469, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2032 = MULTu
6120 : { 2033, 2, 0, 4, 20, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2033 = MULTu_MM
6121 : { 2034, 3, 1, 4, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2034 = MULU
6122 : { 2035, 3, 1, 4, 251, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2035 = MULU_MMR6
6123 : { 2036, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2036 = MULV_B
6124 : { 2037, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2037 = MULV_D
6125 : { 2038, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2038 = MULV_H
6126 : { 2039, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2039 = MULV_W
6127 : { 2040, 3, 1, 4, 250, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo58, -1 ,nullptr }, // Inst #2040 = MUL_MM
6128 : { 2041, 3, 1, 4, 250, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2041 = MUL_MMR6
6129 : { 2042, 3, 1, 4, 826, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2042 = MUL_PH
6130 : { 2043, 3, 1, 4, 989, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2043 = MUL_PH_MMR2
6131 : { 2044, 3, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2044 = MUL_Q_H
6132 : { 2045, 3, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2045 = MUL_Q_W
6133 : { 2046, 3, 1, 4, 250, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2046 = MUL_R6
6134 : { 2047, 3, 1, 4, 827, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2047 = MUL_S_PH
6135 : { 2048, 3, 1, 4, 990, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2048 = MUL_S_PH_MMR2
6136 : { 2049, 1, 1, 2, 38, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2049 = Mfhi16
6137 : { 2050, 1, 1, 2, 38, 0, 0x0ULL, ImplicitList23, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2050 = Mflo16
6138 : { 2051, 2, 1, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2051 = Move32R16
6139 : { 2052, 2, 1, 2, 38, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2052 = MoveR3216
6140 : { 2053, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2053 = NLOC_B
6141 : { 2054, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2054 = NLOC_D
6142 : { 2055, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2055 = NLOC_H
6143 : { 2056, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2056 = NLOC_W
6144 : { 2057, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2057 = NLZC_B
6145 : { 2058, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2058 = NLZC_D
6146 : { 2059, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2059 = NLZC_H
6147 : { 2060, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2060 = NLZC_W
6148 : { 2061, 4, 1, 4, 653, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2061 = NMADD_D32
6149 : { 2062, 4, 1, 4, 252, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2062 = NMADD_D32_MM
6150 : { 2063, 4, 1, 4, 653, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2063 = NMADD_D64
6151 : { 2064, 4, 1, 4, 654, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2064 = NMADD_S
6152 : { 2065, 4, 1, 4, 253, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2065 = NMADD_S_MM
6153 : { 2066, 4, 1, 4, 655, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2066 = NMSUB_D32
6154 : { 2067, 4, 1, 4, 254, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2067 = NMSUB_D32_MM
6155 : { 2068, 4, 1, 4, 655, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2068 = NMSUB_D64
6156 : { 2069, 4, 1, 4, 656, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2069 = NMSUB_S
6157 : { 2070, 4, 1, 4, 255, 0, 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2070 = NMSUB_S_MM
6158 : { 2071, 3, 1, 4, 360, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2071 = NOR
6159 : { 2072, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2072 = NOR64
6160 : { 2073, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2073 = NORI_B
6161 : { 2074, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2074 = NOR_MM
6162 : { 2075, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2075 = NOR_MMR6
6163 : { 2076, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2076 = NOR_V
6164 : { 2077, 2, 1, 2, 257, 0, 0x0ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2077 = NOT16_MM
6165 : { 2078, 2, 1, 2, 257, 0, 0x0ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2078 = NOT16_MMR6
6166 : { 2079, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2079 = NegRxRy16
6167 : { 2080, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2080 = NotRxRy16
6168 : { 2081, 3, 1, 4, 361, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2081 = OR
6169 : { 2082, 3, 1, 2, 258, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2082 = OR16_MM
6170 : { 2083, 3, 1, 2, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2083 = OR16_MMR6
6171 : { 2084, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2084 = OR64
6172 : { 2085, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2085 = ORI_B
6173 : { 2086, 3, 1, 4, 259, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2086 = ORI_MMR6
6174 : { 2087, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2087 = OR_MM
6175 : { 2088, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2088 = OR_MMR6
6176 : { 2089, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2089 = OR_V
6177 : { 2090, 3, 1, 4, 481, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2090 = ORi
6178 : { 2091, 3, 1, 4, 258, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2091 = ORi64
6179 : { 2092, 3, 1, 4, 259, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2092 = ORi_MM
6180 : { 2093, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2093 = OrRxRxRy16
6181 : { 2094, 3, 1, 4, 757, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2094 = PACKRL_PH
6182 : { 2095, 3, 1, 4, 920, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2095 = PACKRL_PH_MM
6183 : { 2096, 0, 0, 4, 397, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2096 = PAUSE
6184 : { 2097, 0, 0, 4, 260, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2097 = PAUSE_MM
6185 : { 2098, 0, 0, 4, 260, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2098 = PAUSE_MMR6
6186 : { 2099, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2099 = PCKEV_B
6187 : { 2100, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2100 = PCKEV_D
6188 : { 2101, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2101 = PCKEV_H
6189 : { 2102, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2102 = PCKEV_W
6190 : { 2103, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2103 = PCKOD_B
6191 : { 2104, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2104 = PCKOD_D
6192 : { 2105, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2105 = PCKOD_H
6193 : { 2106, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2106 = PCKOD_W
6194 : { 2107, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2107 = PCNT_B
6195 : { 2108, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2108 = PCNT_D
6196 : { 2109, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2109 = PCNT_H
6197 : { 2110, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2110 = PCNT_W
6198 : { 2111, 3, 1, 4, 758, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2111 = PICK_PH
6199 : { 2112, 3, 1, 4, 921, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2112 = PICK_PH_MM
6200 : { 2113, 3, 1, 4, 759, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2113 = PICK_QB
6201 : { 2114, 3, 1, 4, 922, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2114 = PICK_QB_MM
6202 : { 2115, 3, 1, 4, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2115 = PLL_PS64
6203 : { 2116, 3, 1, 4, 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2116 = PLU_PS64
6204 : { 2117, 2, 1, 4, 109, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2117 = POP
6205 : { 2118, 2, 1, 4, 761, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2118 = PRECEQU_PH_QBL
6206 : { 2119, 2, 1, 4, 760, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2119 = PRECEQU_PH_QBLA
6207 : { 2120, 2, 1, 4, 923, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2120 = PRECEQU_PH_QBLA_MM
6208 : { 2121, 2, 1, 4, 924, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2121 = PRECEQU_PH_QBL_MM
6209 : { 2122, 2, 1, 4, 763, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2122 = PRECEQU_PH_QBR
6210 : { 2123, 2, 1, 4, 762, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2123 = PRECEQU_PH_QBRA
6211 : { 2124, 2, 1, 4, 925, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2124 = PRECEQU_PH_QBRA_MM
6212 : { 2125, 2, 1, 4, 926, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2125 = PRECEQU_PH_QBR_MM
6213 : { 2126, 2, 1, 4, 764, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2126 = PRECEQ_W_PHL
6214 : { 2127, 2, 1, 4, 927, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2127 = PRECEQ_W_PHL_MM
6215 : { 2128, 2, 1, 4, 765, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2128 = PRECEQ_W_PHR
6216 : { 2129, 2, 1, 4, 928, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2129 = PRECEQ_W_PHR_MM
6217 : { 2130, 2, 1, 4, 767, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2130 = PRECEU_PH_QBL
6218 : { 2131, 2, 1, 4, 766, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2131 = PRECEU_PH_QBLA
6219 : { 2132, 2, 1, 4, 929, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2132 = PRECEU_PH_QBLA_MM
6220 : { 2133, 2, 1, 4, 930, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2133 = PRECEU_PH_QBL_MM
6221 : { 2134, 2, 1, 4, 769, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2134 = PRECEU_PH_QBR
6222 : { 2135, 2, 1, 4, 768, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2135 = PRECEU_PH_QBRA
6223 : { 2136, 2, 1, 4, 931, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2136 = PRECEU_PH_QBRA_MM
6224 : { 2137, 2, 1, 4, 932, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2137 = PRECEU_PH_QBR_MM
6225 : { 2138, 3, 1, 4, 770, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo150, -1 ,nullptr }, // Inst #2138 = PRECRQU_S_QB_PH
6226 : { 2139, 3, 1, 4, 933, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo150, -1 ,nullptr }, // Inst #2139 = PRECRQU_S_QB_PH_MM
6227 : { 2140, 3, 1, 4, 771, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2140 = PRECRQ_PH_W
6228 : { 2141, 3, 1, 4, 934, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2141 = PRECRQ_PH_W_MM
6229 : { 2142, 3, 1, 4, 772, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2142 = PRECRQ_QB_PH
6230 : { 2143, 3, 1, 4, 935, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2143 = PRECRQ_QB_PH_MM
6231 : { 2144, 3, 1, 4, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo318, -1 ,nullptr }, // Inst #2144 = PRECRQ_RS_PH_W
6232 : { 2145, 3, 1, 4, 936, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo318, -1 ,nullptr }, // Inst #2145 = PRECRQ_RS_PH_W_MM
6233 : { 2146, 3, 1, 4, 832, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2146 = PRECR_QB_PH
6234 : { 2147, 3, 1, 4, 995, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2147 = PRECR_QB_PH_MMR2
6235 : { 2148, 4, 1, 4, 833, 0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2148 = PRECR_SRA_PH_W
6236 : { 2149, 4, 1, 4, 996, 0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2149 = PRECR_SRA_PH_W_MMR2
6237 : { 2150, 4, 1, 4, 834, 0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2150 = PRECR_SRA_R_PH_W
6238 : { 2151, 4, 1, 4, 997, 0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2151 = PRECR_SRA_R_PH_W_MMR2
6239 : { 2152, 3, 0, 4, 449, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2152 = PREF
6240 : { 2153, 3, 0, 4, 450, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2153 = PREFE
6241 : { 2154, 3, 0, 4, 262, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2154 = PREFE_MM
6242 : { 2155, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2155 = PREFX_MM
6243 : { 2156, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2156 = PREF_MM
6244 : { 2157, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2157 = PREF_MMR6
6245 : { 2158, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2158 = PREF_R6
6246 : { 2159, 4, 1, 4, 835, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2159 = PREPEND
6247 : { 2160, 4, 1, 4, 998, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2160 = PREPEND_MMR2
6248 : { 2161, 2, 1, 4, 774, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2161 = RADDU_W_QB
6249 : { 2162, 2, 1, 4, 937, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2162 = RADDU_W_QB_MM
6250 : { 2163, 2, 1, 4, 775, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2163 = RDDSP
6251 : { 2164, 2, 1, 4, 938, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2164 = RDDSP_MM
6252 : { 2165, 3, 1, 4, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2165 = RDHWR
6253 : { 2166, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2166 = RDHWR64
6254 : { 2167, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2167 = RDHWR_MM
6255 : { 2168, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2168 = RDHWR_MMR6
6256 : { 2169, 2, 1, 4, 264, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2169 = RDPGPR_MMR6
6257 : { 2170, 2, 1, 4, 624, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #2170 = RECIP_D32
6258 : { 2171, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #2171 = RECIP_D32_MM
6259 : { 2172, 2, 1, 4, 624, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2172 = RECIP_D64
6260 : { 2173, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2173 = RECIP_D64_MM
6261 : { 2174, 2, 1, 4, 626, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2174 = RECIP_S
6262 : { 2175, 2, 1, 4, 266, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2175 = RECIP_S_MM
6263 : { 2176, 2, 1, 4, 776, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2176 = REPLV_PH
6264 : { 2177, 2, 1, 4, 939, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2177 = REPLV_PH_MM
6265 : { 2178, 2, 1, 4, 777, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2178 = REPLV_QB
6266 : { 2179, 2, 1, 4, 940, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2179 = REPLV_QB_MM
6267 : { 2180, 2, 1, 4, 778, 0, 0x6ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2180 = REPL_PH
6268 : { 2181, 2, 1, 4, 941, 0, 0x6ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2181 = REPL_PH_MM
6269 : { 2182, 2, 1, 4, 779, 0, 0x6ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2182 = REPL_QB
6270 : { 2183, 2, 1, 4, 942, 0, 0x6ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2183 = REPL_QB_MM
6271 : { 2184, 2, 1, 4, 267, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2184 = RINT_D
6272 : { 2185, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2185 = RINT_D_MMR6
6273 : { 2186, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2186 = RINT_S
6274 : { 2187, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2187 = RINT_S_MMR6
6275 : { 2188, 3, 1, 4, 482, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2188 = ROTR
6276 : { 2189, 3, 1, 4, 690, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2189 = ROTRV
6277 : { 2190, 3, 1, 4, 270, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2190 = ROTRV_MM
6278 : { 2191, 3, 1, 4, 269, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2191 = ROTR_MM
6279 : { 2192, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2192 = ROUND_L_D64
6280 : { 2193, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2193 = ROUND_L_D_MMR6
6281 : { 2194, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2194 = ROUND_L_S
6282 : { 2195, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2195 = ROUND_L_S_MMR6
6283 : { 2196, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2196 = ROUND_W_D32
6284 : { 2197, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2197 = ROUND_W_D64
6285 : { 2198, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2198 = ROUND_W_D_MMR6
6286 : { 2199, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2199 = ROUND_W_MM
6287 : { 2200, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2200 = ROUND_W_S
6288 : { 2201, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2201 = ROUND_W_S_MM
6289 : { 2202, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2202 = ROUND_W_S_MMR6
6290 : { 2203, 2, 1, 4, 625, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #2203 = RSQRT_D32
6291 : { 2204, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #2204 = RSQRT_D32_MM
6292 : { 2205, 2, 1, 4, 625, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2205 = RSQRT_D64
6293 : { 2206, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2206 = RSQRT_D64_MM
6294 : { 2207, 2, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2207 = RSQRT_S
6295 : { 2208, 2, 1, 4, 266, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2208 = RSQRT_S_MM
6296 : { 2209, 0, 0, 2, 274, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2209 = Restore16
6297 : { 2210, 0, 0, 2, 274, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2210 = RestoreX16
6298 : { 2211, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2211 = SAT_S_B
6299 : { 2212, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2212 = SAT_S_D
6300 : { 2213, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2213 = SAT_S_H
6301 : { 2214, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2214 = SAT_S_W
6302 : { 2215, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2215 = SAT_U_B
6303 : { 2216, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2216 = SAT_U_D
6304 : { 2217, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2217 = SAT_U_H
6305 : { 2218, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2218 = SAT_U_W
6306 : { 2219, 3, 0, 4, 433, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2219 = SB
6307 : { 2220, 3, 0, 2, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2220 = SB16_MM
6308 : { 2221, 3, 0, 2, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2221 = SB16_MMR6
6309 : { 2222, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2222 = SB64
6310 : { 2223, 3, 0, 4, 441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2223 = SBE
6311 : { 2224, 3, 0, 4, 276, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2224 = SBE_MM
6312 : { 2225, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2225 = SB_MM
6313 : { 2226, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2226 = SB_MMR6
6314 : { 2227, 4, 1, 4, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2227 = SC
6315 : { 2228, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2228 = SC64
6316 : { 2229, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2229 = SC64_R6
6317 : { 2230, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2230 = SCD
6318 : { 2231, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2231 = SCD_R6
6319 : { 2232, 4, 1, 4, 444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2232 = SCE
6320 : { 2233, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2233 = SCE_MM
6321 : { 2234, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2234 = SC_MM
6322 : { 2235, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2235 = SC_MMR6
6323 : { 2236, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2236 = SC_R6
6324 : { 2237, 3, 0, 4, 280, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2237 = SD
6325 : { 2238, 1, 0, 4, 380, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2238 = SDBBP
6326 : { 2239, 1, 0, 2, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2239 = SDBBP16_MM
6327 : { 2240, 1, 0, 2, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2240 = SDBBP16_MMR6
6328 : { 2241, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2241 = SDBBP_MM
6329 : { 2242, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2242 = SDBBP_MMR6
6330 : { 2243, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2243 = SDBBP_R6
6331 : { 2244, 3, 0, 4, 671, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2244 = SDC1
6332 : { 2245, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2245 = SDC164
6333 : { 2246, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2246 = SDC1_D64_MMR6
6334 : { 2247, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2247 = SDC1_MM
6335 : { 2248, 3, 0, 4, 438, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2248 = SDC2
6336 : { 2249, 3, 0, 4, 283, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2249 = SDC2_MMR6
6337 : { 2250, 3, 0, 4, 283, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2250 = SDC2_R6
6338 : { 2251, 3, 0, 4, 439, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2251 = SDC3
6339 : { 2252, 2, 0, 4, 465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2252 = SDIV
6340 : { 2253, 2, 0, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2253 = SDIV_MM
6341 : { 2254, 3, 0, 4, 285, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2254 = SDL
6342 : { 2255, 3, 0, 4, 286, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2255 = SDR
6343 : { 2256, 3, 0, 4, 672, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2256 = SDXC1
6344 : { 2257, 3, 0, 4, 287, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2257 = SDXC164
6345 : { 2258, 2, 1, 4, 483, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2258 = SEB
6346 : { 2259, 2, 1, 4, 288, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2259 = SEB64
6347 : { 2260, 2, 1, 4, 288, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2260 = SEB_MM
6348 : { 2261, 2, 1, 4, 484, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2261 = SEH
6349 : { 2262, 2, 1, 4, 289, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2262 = SEH64
6350 : { 2263, 2, 1, 4, 289, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2263 = SEH_MM
6351 : { 2264, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2264 = SELEQZ
6352 : { 2265, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2265 = SELEQZ64
6353 : { 2266, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2266 = SELEQZ_D
6354 : { 2267, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2267 = SELEQZ_D_MMR6
6355 : { 2268, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2268 = SELEQZ_MMR6
6356 : { 2269, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2269 = SELEQZ_S
6357 : { 2270, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2270 = SELEQZ_S_MMR6
6358 : { 2271, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2271 = SELNEZ
6359 : { 2272, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2272 = SELNEZ64
6360 : { 2273, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2273 = SELNEZ_D
6361 : { 2274, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2274 = SELNEZ_D_MMR6
6362 : { 2275, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2275 = SELNEZ_MMR6
6363 : { 2276, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2276 = SELNEZ_S
6364 : { 2277, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2277 = SELNEZ_S_MMR6
6365 : { 2278, 4, 1, 4, 293, 0, 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2278 = SEL_D
6366 : { 2279, 4, 1, 4, 293, 0, 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2279 = SEL_D_MMR6
6367 : { 2280, 4, 1, 4, 294, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2280 = SEL_S
6368 : { 2281, 4, 1, 4, 294, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2281 = SEL_S_MMR6
6369 : { 2282, 3, 1, 4, 295, 0, 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2282 = SEQ
6370 : { 2283, 3, 1, 4, 296, 0, 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2283 = SEQi
6371 : { 2284, 3, 0, 4, 434, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2284 = SH
6372 : { 2285, 3, 0, 2, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2285 = SH16_MM
6373 : { 2286, 3, 0, 2, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2286 = SH16_MMR6
6374 : { 2287, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2287 = SH64
6375 : { 2288, 3, 0, 4, 442, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2288 = SHE
6376 : { 2289, 3, 0, 4, 298, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2289 = SHE_MM
6377 : { 2290, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2290 = SHF_B
6378 : { 2291, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2291 = SHF_H
6379 : { 2292, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2292 = SHF_W
6380 : { 2293, 3, 1, 4, 781, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2293 = SHILO
6381 : { 2294, 3, 1, 4, 780, 0, 0x6ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2294 = SHILOV
6382 : { 2295, 3, 1, 4, 943, 0, 0x6ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2295 = SHILOV_MM
6383 : { 2296, 3, 1, 4, 944, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2296 = SHILO_MM
6384 : { 2297, 3, 1, 4, 782, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2297 = SHLLV_PH
6385 : { 2298, 3, 1, 4, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2298 = SHLLV_PH_MM
6386 : { 2299, 3, 1, 4, 783, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2299 = SHLLV_QB
6387 : { 2300, 3, 1, 4, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2300 = SHLLV_QB_MM
6388 : { 2301, 3, 1, 4, 784, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2301 = SHLLV_S_PH
6389 : { 2302, 3, 1, 4, 947, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2302 = SHLLV_S_PH_MM
6390 : { 2303, 3, 1, 4, 785, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo58, -1 ,nullptr }, // Inst #2303 = SHLLV_S_W
6391 : { 2304, 3, 1, 4, 948, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo58, -1 ,nullptr }, // Inst #2304 = SHLLV_S_W_MM
6392 : { 2305, 3, 1, 4, 786, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2305 = SHLL_PH
6393 : { 2306, 3, 1, 4, 949, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2306 = SHLL_PH_MM
6394 : { 2307, 3, 1, 4, 787, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2307 = SHLL_QB
6395 : { 2308, 3, 1, 4, 950, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2308 = SHLL_QB_MM
6396 : { 2309, 3, 1, 4, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2309 = SHLL_S_PH
6397 : { 2310, 3, 1, 4, 951, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo331, -1 ,nullptr }, // Inst #2310 = SHLL_S_PH_MM
6398 : { 2311, 3, 1, 4, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo59, -1 ,nullptr }, // Inst #2311 = SHLL_S_W
6399 : { 2312, 3, 1, 4, 952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo59, -1 ,nullptr }, // Inst #2312 = SHLL_S_W_MM
6400 : { 2313, 3, 1, 4, 790, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2313 = SHRAV_PH
6401 : { 2314, 3, 1, 4, 953, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2314 = SHRAV_PH_MM
6402 : { 2315, 3, 1, 4, 838, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2315 = SHRAV_QB
6403 : { 2316, 3, 1, 4, 1001, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2316 = SHRAV_QB_MMR2
6404 : { 2317, 3, 1, 4, 791, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2317 = SHRAV_R_PH
6405 : { 2318, 3, 1, 4, 954, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2318 = SHRAV_R_PH_MM
6406 : { 2319, 3, 1, 4, 839, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2319 = SHRAV_R_QB
6407 : { 2320, 3, 1, 4, 1002, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2320 = SHRAV_R_QB_MMR2
6408 : { 2321, 3, 1, 4, 792, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2321 = SHRAV_R_W
6409 : { 2322, 3, 1, 4, 955, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2322 = SHRAV_R_W_MM
6410 : { 2323, 3, 1, 4, 793, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2323 = SHRA_PH
6411 : { 2324, 3, 1, 4, 956, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2324 = SHRA_PH_MM
6412 : { 2325, 3, 1, 4, 836, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2325 = SHRA_QB
6413 : { 2326, 3, 1, 4, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2326 = SHRA_QB_MMR2
6414 : { 2327, 3, 1, 4, 794, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2327 = SHRA_R_PH
6415 : { 2328, 3, 1, 4, 957, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2328 = SHRA_R_PH_MM
6416 : { 2329, 3, 1, 4, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2329 = SHRA_R_QB
6417 : { 2330, 3, 1, 4, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2330 = SHRA_R_QB_MMR2
6418 : { 2331, 3, 1, 4, 795, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2331 = SHRA_R_W
6419 : { 2332, 3, 1, 4, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2332 = SHRA_R_W_MM
6420 : { 2333, 3, 1, 4, 841, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2333 = SHRLV_PH
6421 : { 2334, 3, 1, 4, 1004, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2334 = SHRLV_PH_MMR2
6422 : { 2335, 3, 1, 4, 796, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2335 = SHRLV_QB
6423 : { 2336, 3, 1, 4, 959, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2336 = SHRLV_QB_MM
6424 : { 2337, 3, 1, 4, 840, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2337 = SHRL_PH
6425 : { 2338, 3, 1, 4, 1003, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2338 = SHRL_PH_MMR2
6426 : { 2339, 3, 1, 4, 797, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2339 = SHRL_QB
6427 : { 2340, 3, 1, 4, 960, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2340 = SHRL_QB_MM
6428 : { 2341, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2341 = SH_MM
6429 : { 2342, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2342 = SH_MMR6
6430 : { 2343, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2343 = SLDI_B
6431 : { 2344, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #2344 = SLDI_D
6432 : { 2345, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #2345 = SLDI_H
6433 : { 2346, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #2346 = SLDI_W
6434 : { 2347, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2347 = SLD_B
6435 : { 2348, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2348 = SLD_D
6436 : { 2349, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2349 = SLD_H
6437 : { 2350, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2350 = SLD_W
6438 : { 2351, 3, 1, 4, 486, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2351 = SLL
6439 : { 2352, 3, 1, 2, 299, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2352 = SLL16_MM
6440 : { 2353, 3, 1, 2, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2353 = SLL16_MMR6
6441 : { 2354, 2, 1, 4, 299, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #2354 = SLL64_32
6442 : { 2355, 2, 1, 4, 299, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2355 = SLL64_64
6443 : { 2356, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2356 = SLLI_B
6444 : { 2357, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2357 = SLLI_D
6445 : { 2358, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2358 = SLLI_H
6446 : { 2359, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2359 = SLLI_W
6447 : { 2360, 3, 1, 4, 491, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2360 = SLLV
6448 : { 2361, 3, 1, 4, 300, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2361 = SLLV_MM
6449 : { 2362, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2362 = SLL_B
6450 : { 2363, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2363 = SLL_D
6451 : { 2364, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2364 = SLL_H
6452 : { 2365, 3, 1, 4, 299, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2365 = SLL_MM
6453 : { 2366, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2366 = SLL_MMR6
6454 : { 2367, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2367 = SLL_W
6455 : { 2368, 3, 1, 4, 485, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2368 = SLT
6456 : { 2369, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2369 = SLT64
6457 : { 2370, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2370 = SLT_MM
6458 : { 2371, 3, 1, 4, 362, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2371 = SLTi
6459 : { 2372, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2372 = SLTi64
6460 : { 2373, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2373 = SLTi_MM
6461 : { 2374, 3, 1, 4, 362, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2374 = SLTiu
6462 : { 2375, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2375 = SLTiu64
6463 : { 2376, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2376 = SLTiu_MM
6464 : { 2377, 3, 1, 4, 485, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2377 = SLTu
6465 : { 2378, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2378 = SLTu64
6466 : { 2379, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2379 = SLTu_MM
6467 : { 2380, 3, 1, 4, 295, 0, 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2380 = SNE
6468 : { 2381, 3, 1, 4, 296, 0, 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2381 = SNEi
6469 : { 2382, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2382 = SPLATI_B
6470 : { 2383, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2383 = SPLATI_D
6471 : { 2384, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2384 = SPLATI_H
6472 : { 2385, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2385 = SPLATI_W
6473 : { 2386, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2386 = SPLAT_B
6474 : { 2387, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2387 = SPLAT_D
6475 : { 2388, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2388 = SPLAT_H
6476 : { 2389, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2389 = SPLAT_W
6477 : { 2390, 3, 1, 4, 487, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2390 = SRA
6478 : { 2391, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2391 = SRAI_B
6479 : { 2392, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2392 = SRAI_D
6480 : { 2393, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2393 = SRAI_H
6481 : { 2394, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2394 = SRAI_W
6482 : { 2395, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2395 = SRARI_B
6483 : { 2396, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2396 = SRARI_D
6484 : { 2397, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2397 = SRARI_H
6485 : { 2398, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2398 = SRARI_W
6486 : { 2399, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2399 = SRAR_B
6487 : { 2400, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2400 = SRAR_D
6488 : { 2401, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2401 = SRAR_H
6489 : { 2402, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2402 = SRAR_W
6490 : { 2403, 3, 1, 4, 492, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2403 = SRAV
6491 : { 2404, 3, 1, 4, 304, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2404 = SRAV_MM
6492 : { 2405, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2405 = SRA_B
6493 : { 2406, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2406 = SRA_D
6494 : { 2407, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2407 = SRA_H
6495 : { 2408, 3, 1, 4, 303, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2408 = SRA_MM
6496 : { 2409, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2409 = SRA_W
6497 : { 2410, 3, 1, 4, 488, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2410 = SRL
6498 : { 2411, 3, 1, 2, 305, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2411 = SRL16_MM
6499 : { 2412, 3, 1, 2, 305, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2412 = SRL16_MMR6
6500 : { 2413, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2413 = SRLI_B
6501 : { 2414, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2414 = SRLI_D
6502 : { 2415, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2415 = SRLI_H
6503 : { 2416, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2416 = SRLI_W
6504 : { 2417, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2417 = SRLRI_B
6505 : { 2418, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2418 = SRLRI_D
6506 : { 2419, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2419 = SRLRI_H
6507 : { 2420, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2420 = SRLRI_W
6508 : { 2421, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2421 = SRLR_B
6509 : { 2422, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2422 = SRLR_D
6510 : { 2423, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2423 = SRLR_H
6511 : { 2424, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2424 = SRLR_W
6512 : { 2425, 3, 1, 4, 493, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2425 = SRLV
6513 : { 2426, 3, 1, 4, 306, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2426 = SRLV_MM
6514 : { 2427, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2427 = SRL_B
6515 : { 2428, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2428 = SRL_D
6516 : { 2429, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2429 = SRL_H
6517 : { 2430, 3, 1, 4, 305, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2430 = SRL_MM
6518 : { 2431, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2431 = SRL_W
6519 : { 2432, 0, 0, 4, 381, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2432 = SSNOP
6520 : { 2433, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2433 = SSNOP_MM
6521 : { 2434, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2434 = SSNOP_MMR6
6522 : { 2435, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2435 = ST_B
6523 : { 2436, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2436 = ST_D
6524 : { 2437, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2437 = ST_H
6525 : { 2438, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2438 = ST_W
6526 : { 2439, 3, 1, 4, 363, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2439 = SUB
6527 : { 2440, 3, 1, 4, 842, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2440 = SUBQH_PH
6528 : { 2441, 3, 1, 4, 1005, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2441 = SUBQH_PH_MMR2
6529 : { 2442, 3, 1, 4, 843, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2442 = SUBQH_R_PH
6530 : { 2443, 3, 1, 4, 1006, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2443 = SUBQH_R_PH_MMR2
6531 : { 2444, 3, 1, 4, 845, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2444 = SUBQH_R_W
6532 : { 2445, 3, 1, 4, 1008, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2445 = SUBQH_R_W_MMR2
6533 : { 2446, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2446 = SUBQH_W
6534 : { 2447, 3, 1, 4, 1007, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2447 = SUBQH_W_MMR2
6535 : { 2448, 3, 1, 4, 798, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2448 = SUBQ_PH
6536 : { 2449, 3, 1, 4, 961, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2449 = SUBQ_PH_MM
6537 : { 2450, 3, 1, 4, 799, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2450 = SUBQ_S_PH
6538 : { 2451, 3, 1, 4, 962, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2451 = SUBQ_S_PH_MM
6539 : { 2452, 3, 1, 4, 800, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #2452 = SUBQ_S_W
6540 : { 2453, 3, 1, 4, 963, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #2453 = SUBQ_S_W_MM
6541 : { 2454, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2454 = SUBSUS_U_B
6542 : { 2455, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2455 = SUBSUS_U_D
6543 : { 2456, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2456 = SUBSUS_U_H
6544 : { 2457, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2457 = SUBSUS_U_W
6545 : { 2458, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2458 = SUBSUU_S_B
6546 : { 2459, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2459 = SUBSUU_S_D
6547 : { 2460, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2460 = SUBSUU_S_H
6548 : { 2461, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2461 = SUBSUU_S_W
6549 : { 2462, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2462 = SUBS_S_B
6550 : { 2463, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2463 = SUBS_S_D
6551 : { 2464, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2464 = SUBS_S_H
6552 : { 2465, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2465 = SUBS_S_W
6553 : { 2466, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2466 = SUBS_U_B
6554 : { 2467, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2467 = SUBS_U_D
6555 : { 2468, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2468 = SUBS_U_H
6556 : { 2469, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2469 = SUBS_U_W
6557 : { 2470, 3, 1, 2, 309, 0, 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #2470 = SUBU16_MM
6558 : { 2471, 3, 1, 2, 309, 0, 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #2471 = SUBU16_MMR6
6559 : { 2472, 3, 1, 4, 848, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2472 = SUBUH_QB
6560 : { 2473, 3, 1, 4, 1011, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2473 = SUBUH_QB_MMR2
6561 : { 2474, 3, 1, 4, 849, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2474 = SUBUH_R_QB
6562 : { 2475, 3, 1, 4, 1012, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2475 = SUBUH_R_QB_MMR2
6563 : { 2476, 3, 1, 4, 309, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2476 = SUBU_MMR6
6564 : { 2477, 3, 1, 4, 846, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2477 = SUBU_PH
6565 : { 2478, 3, 1, 4, 1009, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2478 = SUBU_PH_MMR2
6566 : { 2479, 3, 1, 4, 801, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2479 = SUBU_QB
6567 : { 2480, 3, 1, 4, 964, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2480 = SUBU_QB_MM
6568 : { 2481, 3, 1, 4, 847, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2481 = SUBU_S_PH
6569 : { 2482, 3, 1, 4, 1010, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2482 = SUBU_S_PH_MMR2
6570 : { 2483, 3, 1, 4, 802, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2483 = SUBU_S_QB
6571 : { 2484, 3, 1, 4, 965, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2484 = SUBU_S_QB_MM
6572 : { 2485, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2485 = SUBVI_B
6573 : { 2486, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2486 = SUBVI_D
6574 : { 2487, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2487 = SUBVI_H
6575 : { 2488, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2488 = SUBVI_W
6576 : { 2489, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2489 = SUBV_B
6577 : { 2490, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2490 = SUBV_D
6578 : { 2491, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2491 = SUBV_H
6579 : { 2492, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2492 = SUBV_W
6580 : { 2493, 3, 1, 4, 308, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2493 = SUB_MM
6581 : { 2494, 3, 1, 4, 308, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2494 = SUB_MMR6
6582 : { 2495, 3, 1, 4, 364, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2495 = SUBu
6583 : { 2496, 3, 1, 4, 309, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2496 = SUBu_MM
6584 : { 2497, 3, 0, 4, 673, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2497 = SUXC1
6585 : { 2498, 3, 0, 4, 310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2498 = SUXC164
6586 : { 2499, 3, 0, 4, 310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2499 = SUXC1_MM
6587 : { 2500, 3, 0, 4, 435, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2500 = SW
6588 : { 2501, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2501 = SW16_MM
6589 : { 2502, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2502 = SW16_MMR6
6590 : { 2503, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2503 = SW64
6591 : { 2504, 3, 0, 4, 674, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2504 = SWC1
6592 : { 2505, 3, 0, 4, 312, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2505 = SWC1_MM
6593 : { 2506, 3, 0, 4, 436, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2506 = SWC2
6594 : { 2507, 3, 0, 4, 313, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2507 = SWC2_MMR6
6595 : { 2508, 3, 0, 4, 313, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2508 = SWC2_R6
6596 : { 2509, 3, 0, 4, 437, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2509 = SWC3
6597 : { 2510, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2510 = SWDSP
6598 : { 2511, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2511 = SWDSP_MM
6599 : { 2512, 3, 0, 4, 443, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2512 = SWE
6600 : { 2513, 3, 0, 4, 315, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2513 = SWE_MM
6601 : { 2514, 3, 0, 4, 445, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2514 = SWL
6602 : { 2515, 3, 0, 4, 316, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2515 = SWL64
6603 : { 2516, 3, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2516 = SWLE
6604 : { 2517, 3, 0, 4, 317, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2517 = SWLE_MM
6605 : { 2518, 3, 0, 4, 316, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2518 = SWL_MM
6606 : { 2519, 3, 0, 2, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2519 = SWM16_MM
6607 : { 2520, 3, 0, 2, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2520 = SWM16_MMR6
6608 : { 2521, 3, 0, 4, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2521 = SWM32_MM
6609 : { 2522, 4, 0, 4, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2522 = SWP_MM
6610 : { 2523, 3, 0, 4, 446, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2523 = SWR
6611 : { 2524, 3, 0, 4, 320, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2524 = SWR64
6612 : { 2525, 3, 0, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2525 = SWRE
6613 : { 2526, 3, 0, 4, 321, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2526 = SWRE_MM
6614 : { 2527, 3, 0, 4, 320, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2527 = SWR_MM
6615 : { 2528, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2528 = SWSP_MM
6616 : { 2529, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2529 = SWSP_MMR6
6617 : { 2530, 3, 0, 4, 675, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2530 = SWXC1
6618 : { 2531, 3, 0, 4, 322, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2531 = SWXC1_MM
6619 : { 2532, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2532 = SW_MM
6620 : { 2533, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2533 = SW_MMR6
6621 : { 2534, 1, 0, 4, 453, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2534 = SYNC
6622 : { 2535, 2, 0, 4, 454, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2535 = SYNCI
6623 : { 2536, 2, 0, 4, 324, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2536 = SYNCI_MM
6624 : { 2537, 2, 0, 4, 324, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2537 = SYNCI_MMR6
6625 : { 2538, 1, 0, 4, 323, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2538 = SYNC_MM
6626 : { 2539, 1, 0, 4, 323, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2539 = SYNC_MMR6
6627 : { 2540, 1, 0, 4, 382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2540 = SYSCALL
6628 : { 2541, 1, 0, 4, 325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2541 = SYSCALL_MM
6629 : { 2542, 0, 0, 2, 326, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2542 = Save16
6630 : { 2543, 0, 0, 2, 326, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2543 = SaveX16
6631 : { 2544, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2544 = SbRxRyOffMemX16
6632 : { 2545, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2545 = SebRx16
6633 : { 2546, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2546 = SehRx16
6634 : { 2547, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2547 = ShRxRyOffMemX16
6635 : { 2548, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2548 = SllX16
6636 : { 2549, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2549 = SllvRxRy16
6637 : { 2550, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #2550 = SltRxRy16
6638 : { 2551, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2551 = SltiRxImm16
6639 : { 2552, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2552 = SltiRxImmX16
6640 : { 2553, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2553 = SltiuRxImm16
6641 : { 2554, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2554 = SltiuRxImmX16
6642 : { 2555, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #2555 = SltuRxRy16
6643 : { 2556, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2556 = SraX16
6644 : { 2557, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2557 = SravRxRy16
6645 : { 2558, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2558 = SrlX16
6646 : { 2559, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2559 = SrlvRxRy16
6647 : { 2560, 3, 1, 2, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #2560 = SubuRxRyRz16
6648 : { 2561, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2561 = SwRxRyOffMemX16
6649 : { 2562, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #2562 = SwRxSpImmX16
6650 : { 2563, 3, 0, 4, 383, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2563 = TEQ
6651 : { 2564, 2, 0, 4, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2564 = TEQI
6652 : { 2565, 2, 0, 4, 328, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2565 = TEQI_MM
6653 : { 2566, 3, 0, 4, 327, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2566 = TEQ_MM
6654 : { 2567, 3, 0, 4, 385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2567 = TGE
6655 : { 2568, 2, 0, 4, 386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2568 = TGEI
6656 : { 2569, 2, 0, 4, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2569 = TGEIU
6657 : { 2570, 2, 0, 4, 331, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2570 = TGEIU_MM
6658 : { 2571, 2, 0, 4, 330, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2571 = TGEI_MM
6659 : { 2572, 3, 0, 4, 388, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2572 = TGEU
6660 : { 2573, 3, 0, 4, 332, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2573 = TGEU_MM
6661 : { 2574, 3, 0, 4, 329, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2574 = TGE_MM
6662 : { 2575, 0, 0, 4, 333, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2575 = TLBGINV
6663 : { 2576, 0, 0, 4, 334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2576 = TLBGINVF
6664 : { 2577, 0, 0, 4, 334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2577 = TLBGINVF_MM
6665 : { 2578, 0, 0, 4, 333, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2578 = TLBGINV_MM
6666 : { 2579, 0, 0, 4, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2579 = TLBGP
6667 : { 2580, 0, 0, 4, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2580 = TLBGP_MM
6668 : { 2581, 0, 0, 4, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2581 = TLBGR
6669 : { 2582, 0, 0, 4, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2582 = TLBGR_MM
6670 : { 2583, 0, 0, 4, 337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2583 = TLBGWI
6671 : { 2584, 0, 0, 4, 337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2584 = TLBGWI_MM
6672 : { 2585, 0, 0, 4, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2585 = TLBGWR
6673 : { 2586, 0, 0, 4, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2586 = TLBGWR_MM
6674 : { 2587, 0, 0, 4, 402, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2587 = TLBINV
6675 : { 2588, 0, 0, 4, 403, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2588 = TLBINVF
6676 : { 2589, 0, 0, 4, 340, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2589 = TLBINVF_MMR6
6677 : { 2590, 0, 0, 4, 339, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2590 = TLBINV_MMR6
6678 : { 2591, 0, 0, 4, 404, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2591 = TLBP
6679 : { 2592, 0, 0, 4, 341, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2592 = TLBP_MM
6680 : { 2593, 0, 0, 4, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2593 = TLBR
6681 : { 2594, 0, 0, 4, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2594 = TLBR_MM
6682 : { 2595, 0, 0, 4, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2595 = TLBWI
6683 : { 2596, 0, 0, 4, 343, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2596 = TLBWI_MM
6684 : { 2597, 0, 0, 4, 407, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2597 = TLBWR
6685 : { 2598, 0, 0, 4, 344, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2598 = TLBWR_MM
6686 : { 2599, 3, 0, 4, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2599 = TLT
6687 : { 2600, 2, 0, 4, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2600 = TLTI
6688 : { 2601, 2, 0, 4, 347, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2601 = TLTIU_MM
6689 : { 2602, 2, 0, 4, 346, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2602 = TLTI_MM
6690 : { 2603, 3, 0, 4, 391, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2603 = TLTU
6691 : { 2604, 3, 0, 4, 348, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2604 = TLTU_MM
6692 : { 2605, 3, 0, 4, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2605 = TLT_MM
6693 : { 2606, 3, 0, 4, 392, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2606 = TNE
6694 : { 2607, 2, 0, 4, 393, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2607 = TNEI
6695 : { 2608, 2, 0, 4, 350, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2608 = TNEI_MM
6696 : { 2609, 3, 0, 4, 349, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2609 = TNE_MM
6697 : { 2610, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2610 = TRUNC_L_D64
6698 : { 2611, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2611 = TRUNC_L_D_MMR6
6699 : { 2612, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2612 = TRUNC_L_S
6700 : { 2613, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2613 = TRUNC_L_S_MMR6
6701 : { 2614, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2614 = TRUNC_W_D32
6702 : { 2615, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2615 = TRUNC_W_D64
6703 : { 2616, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2616 = TRUNC_W_D_MMR6
6704 : { 2617, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2617 = TRUNC_W_MM
6705 : { 2618, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2618 = TRUNC_W_S
6706 : { 2619, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2619 = TRUNC_W_S_MM
6707 : { 2620, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2620 = TRUNC_W_S_MMR6
6708 : { 2621, 2, 0, 4, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2621 = TTLTIU
6709 : { 2622, 2, 0, 4, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2622 = UDIV
6710 : { 2623, 2, 0, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2623 = UDIV_MM
6711 : { 2624, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo57, -1 ,nullptr }, // Inst #2624 = V3MULU
6712 : { 2625, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo57, -1 ,nullptr }, // Inst #2625 = VMM0
6713 : { 2626, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo57, -1 ,nullptr }, // Inst #2626 = VMULU
6714 : { 2627, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2627 = VSHF_B
6715 : { 2628, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #2628 = VSHF_D
6716 : { 2629, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2629 = VSHF_H
6717 : { 2630, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #2630 = VSHF_W
6718 : { 2631, 0, 0, 4, 396, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2631 = WAIT
6719 : { 2632, 1, 0, 4, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2632 = WAIT_MM
6720 : { 2633, 1, 0, 4, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2633 = WAIT_MMR6
6721 : { 2634, 2, 0, 4, 803, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2634 = WRDSP
6722 : { 2635, 2, 0, 4, 966, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2635 = WRDSP_MM
6723 : { 2636, 2, 1, 4, 353, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2636 = WRPGPR_MMR6
6724 : { 2637, 2, 1, 4, 462, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2637 = WSBH
6725 : { 2638, 2, 1, 4, 354, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2638 = WSBH_MM
6726 : { 2639, 2, 1, 4, 354, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2639 = WSBH_MMR6
6727 : { 2640, 3, 1, 4, 365, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2640 = XOR
6728 : { 2641, 3, 1, 2, 355, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2641 = XOR16_MM
6729 : { 2642, 3, 1, 2, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2642 = XOR16_MMR6
6730 : { 2643, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2643 = XOR64
6731 : { 2644, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2644 = XORI_B
6732 : { 2645, 3, 1, 4, 356, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2645 = XORI_MMR6
6733 : { 2646, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2646 = XOR_MM
6734 : { 2647, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2647 = XOR_MMR6
6735 : { 2648, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2648 = XOR_V
6736 : { 2649, 3, 1, 4, 489, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2649 = XORi
6737 : { 2650, 3, 1, 4, 355, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2650 = XORi64
6738 : { 2651, 3, 1, 4, 356, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2651 = XORi_MM
6739 : { 2652, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2652 = XorRxRxRy16
6740 : { 2653, 2, 1, 4, 357, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2653 = YIELD
6741 : };
6742 :
6743 : extern const char MipsInstrNameData[] = {
6744 : /* 0 */ 'D', 'M', 'F', 'C', '0', 0,
6745 : /* 6 */ 'D', 'M', 'F', 'G', 'C', '0', 0,
6746 : /* 13 */ 'M', 'F', 'H', 'G', 'C', '0', 0,
6747 : /* 20 */ 'M', 'T', 'H', 'G', 'C', '0', 0,
6748 : /* 27 */ 'D', 'M', 'T', 'G', 'C', '0', 0,
6749 : /* 34 */ 'M', 'F', 'T', 'C', '0', 0,
6750 : /* 40 */ 'D', 'M', 'T', 'C', '0', 0,
6751 : /* 46 */ 'M', 'T', 'T', 'C', '0', 0,
6752 : /* 52 */ 'V', 'M', 'M', '0', 0,
6753 : /* 57 */ 'M', 'T', 'M', '0', 0,
6754 : /* 62 */ 'M', 'T', 'P', '0', 0,
6755 : /* 67 */ 'B', 'B', 'I', 'T', '0', 0,
6756 : /* 73 */ 'L', 'D', 'C', '1', 0,
6757 : /* 78 */ 'S', 'D', 'C', '1', 0,
6758 : /* 83 */ 'C', 'F', 'C', '1', 0,
6759 : /* 88 */ 'D', 'M', 'F', 'C', '1', 0,
6760 : /* 94 */ 'M', 'F', 'T', 'H', 'C', '1', 0,
6761 : /* 101 */ 'M', 'T', 'T', 'H', 'C', '1', 0,
6762 : /* 108 */ 'C', 'T', 'C', '1', 0,
6763 : /* 113 */ 'C', 'F', 'T', 'C', '1', 0,
6764 : /* 119 */ 'M', 'F', 'T', 'C', '1', 0,
6765 : /* 125 */ 'D', 'M', 'T', 'C', '1', 0,
6766 : /* 131 */ 'C', 'T', 'T', 'C', '1', 0,
6767 : /* 137 */ 'M', 'T', 'T', 'C', '1', 0,
6768 : /* 143 */ 'L', 'W', 'C', '1', 0,
6769 : /* 148 */ 'S', 'W', 'C', '1', 0,
6770 : /* 153 */ 'L', 'D', 'X', 'C', '1', 0,
6771 : /* 159 */ 'S', 'D', 'X', 'C', '1', 0,
6772 : /* 165 */ 'L', 'U', 'X', 'C', '1', 0,
6773 : /* 171 */ 'S', 'U', 'X', 'C', '1', 0,
6774 : /* 177 */ 'L', 'W', 'X', 'C', '1', 0,
6775 : /* 183 */ 'S', 'W', 'X', 'C', '1', 0,
6776 : /* 189 */ 'M', 'T', 'M', '1', 0,
6777 : /* 194 */ 'M', 'T', 'P', '1', 0,
6778 : /* 199 */ 'B', 'B', 'I', 'T', '1', 0,
6779 : /* 205 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0,
6780 : /* 213 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0,
6781 : /* 221 */ 'D', 'S', 'R', 'A', '3', '2', 0,
6782 : /* 228 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0,
6783 : /* 238 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0,
6784 : /* 248 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
6785 : /* 257 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
6786 : /* 267 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
6787 : /* 276 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
6788 : /* 286 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0,
6789 : /* 296 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0,
6790 : /* 307 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0,
6791 : /* 317 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0,
6792 : /* 327 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0,
6793 : /* 336 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0,
6794 : /* 345 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0,
6795 : /* 354 */ 'C', '_', 'F', '_', 'D', '3', '2', 0,
6796 : /* 362 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0,
6797 : /* 383 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0,
6798 : /* 392 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0,
6799 : /* 403 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0,
6800 : /* 414 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0,
6801 : /* 424 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0,
6802 : /* 433 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0,
6803 : /* 442 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0,
6804 : /* 452 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0,
6805 : /* 461 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0,
6806 : /* 471 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0,
6807 : /* 481 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0,
6808 : /* 490 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0,
6809 : /* 499 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0,
6810 : /* 509 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0,
6811 : /* 526 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0,
6812 : /* 536 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0,
6813 : /* 546 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0,
6814 : /* 556 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0,
6815 : /* 565 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
6816 : /* 575 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
6817 : /* 585 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0,
6818 : /* 594 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0,
6819 : /* 615 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0,
6820 : /* 624 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0,
6821 : /* 633 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0,
6822 : /* 651 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0,
6823 : /* 663 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0,
6824 : /* 674 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0,
6825 : /* 686 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0,
6826 : /* 696 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0,
6827 : /* 705 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
6828 : /* 725 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
6829 : /* 745 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
6830 : /* 766 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
6831 : /* 786 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
6832 : /* 802 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
6833 : /* 822 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
6834 : /* 842 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0,
6835 : /* 861 */ 'D', 'S', 'L', 'L', '3', '2', 0,
6836 : /* 868 */ 'D', 'S', 'R', 'L', '3', '2', 0,
6837 : /* 875 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0,
6838 : /* 883 */ 'C', 'I', 'N', 'S', '3', '2', 0,
6839 : /* 890 */ 'E', 'X', 'T', 'S', '3', '2', 0,
6840 : /* 897 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0,
6841 : /* 906 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0,
6842 : /* 916 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0,
6843 : /* 926 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0,
6844 : /* 936 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0,
6845 : /* 956 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0,
6846 : /* 970 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0,
6847 : /* 979 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0,
6848 : /* 989 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0,
6849 : /* 1003 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0,
6850 : /* 1019 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0,
6851 : /* 1032 */ 'L', 'D', 'C', '2', 0,
6852 : /* 1037 */ 'S', 'D', 'C', '2', 0,
6853 : /* 1042 */ 'D', 'M', 'F', 'C', '2', 0,
6854 : /* 1048 */ 'D', 'M', 'T', 'C', '2', 0,
6855 : /* 1054 */ 'L', 'W', 'C', '2', 0,
6856 : /* 1059 */ 'S', 'W', 'C', '2', 0,
6857 : /* 1064 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
6858 : /* 1072 */ 'M', 'T', 'M', '2', 0,
6859 : /* 1077 */ 'M', 'T', 'P', '2', 0,
6860 : /* 1082 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
6861 : /* 1090 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6862 : /* 1103 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6863 : /* 1121 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6864 : /* 1135 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6865 : /* 1149 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6866 : /* 1167 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6867 : /* 1182 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6868 : /* 1198 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6869 : /* 1214 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6870 : /* 1230 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6871 : /* 1245 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6872 : /* 1263 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
6873 : /* 1277 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
6874 : /* 1290 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
6875 : /* 1302 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6876 : /* 1319 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6877 : /* 1333 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6878 : /* 1347 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6879 : /* 1360 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6880 : /* 1372 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6881 : /* 1388 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6882 : /* 1404 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6883 : /* 1418 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6884 : /* 1433 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6885 : /* 1448 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6886 : /* 1463 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6887 : /* 1476 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6888 : /* 1489 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6889 : /* 1503 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6890 : /* 1517 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6891 : /* 1533 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6892 : /* 1552 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6893 : /* 1571 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6894 : /* 1585 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6895 : /* 1603 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6896 : /* 1621 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6897 : /* 1636 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
6898 : /* 1651 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0,
6899 : /* 1663 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6900 : /* 1683 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6901 : /* 1705 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6902 : /* 1718 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6903 : /* 1731 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6904 : /* 1746 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6905 : /* 1761 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6906 : /* 1776 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
6907 : /* 1790 */ 'L', 'D', 'C', '3', 0,
6908 : /* 1795 */ 'S', 'D', 'C', '3', 0,
6909 : /* 1800 */ 'L', 'W', 'C', '3', 0,
6910 : /* 1805 */ 'S', 'W', 'C', '3', 0,
6911 : /* 1810 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0,
6912 : /* 1825 */ 'L', 'D', 'C', '1', '6', '4', 0,
6913 : /* 1832 */ 'S', 'D', 'C', '1', '6', '4', 0,
6914 : /* 1839 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0,
6915 : /* 1847 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0,
6916 : /* 1855 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0,
6917 : /* 1863 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0,
6918 : /* 1871 */ 'S', 'E', 'B', '6', '4', 0,
6919 : /* 1877 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0,
6920 : /* 1893 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0,
6921 : /* 1901 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0,
6922 : /* 1911 */ 'L', 'B', '6', '4', 0,
6923 : /* 1916 */ 'S', 'B', '6', '4', 0,
6924 : /* 1921 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0,
6925 : /* 1932 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0,
6926 : /* 1944 */ 'B', 'G', 'E', 'C', '6', '4', 0,
6927 : /* 1951 */ 'B', 'N', 'E', 'C', '6', '4', 0,
6928 : /* 1958 */ 'J', 'I', 'C', '6', '4', 0,
6929 : /* 1964 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0,
6930 : /* 1972 */ 'B', 'E', 'Q', 'C', '6', '4', 0,
6931 : /* 1979 */ 'S', 'C', '6', '4', 0,
6932 : /* 1984 */ 'B', 'L', 'T', 'C', '6', '4', 0,
6933 : /* 1991 */ 'B', 'G', 'E', 'U', 'C', '6', '4', 0,
6934 : /* 1999 */ 'B', 'L', 'T', 'U', 'C', '6', '4', 0,
6935 : /* 2007 */ 'B', 'G', 'E', 'Z', 'C', '6', '4', 0,
6936 : /* 2015 */ 'B', 'L', 'E', 'Z', 'C', '6', '4', 0,
6937 : /* 2023 */ 'B', 'N', 'E', 'Z', 'C', '6', '4', 0,
6938 : /* 2031 */ 'B', 'E', 'Q', 'Z', 'C', '6', '4', 0,
6939 : /* 2039 */ 'B', 'G', 'T', 'Z', 'C', '6', '4', 0,
6940 : /* 2047 */ 'B', 'L', 'T', 'Z', 'C', '6', '4', 0,
6941 : /* 2055 */ 'A', 'N', 'D', '6', '4', 0,
6942 : /* 2061 */ 'M', 'F', 'C', '1', '_', 'D', '6', '4', 0,
6943 : /* 2070 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', 0,
6944 : /* 2080 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', 0,
6945 : /* 2090 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', 0,
6946 : /* 2099 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
6947 : /* 2112 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
6948 : /* 2125 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
6949 : /* 2134 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
6950 : /* 2144 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
6951 : /* 2153 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
6952 : /* 2163 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', 0,
6953 : /* 2173 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', 0,
6954 : /* 2184 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', 0,
6955 : /* 2194 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', 0,
6956 : /* 2204 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', 0,
6957 : /* 2213 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', 0,
6958 : /* 2222 */ 'M', 'O', 'V', 'F', '_', 'D', '6', '4', 0,
6959 : /* 2231 */ 'C', '_', 'F', '_', 'D', '6', '4', 0,
6960 : /* 2239 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '6', '4', 0,
6961 : /* 2260 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', 0,
6962 : /* 2269 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '6', '4', 0,
6963 : /* 2280 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '6', '4', 0,
6964 : /* 2291 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', 0,
6965 : /* 2301 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', 0,
6966 : /* 2310 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '6', '4', 0,
6967 : /* 2322 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '6', '4', 0,
6968 : /* 2334 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '6', '4', 0,
6969 : /* 2345 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '6', '4', 0,
6970 : /* 2357 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', 0,
6971 : /* 2367 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', 0,
6972 : /* 2376 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', 0,
6973 : /* 2386 */ 'F', 'C', 'M', 'P', '_', 'D', '6', '4', 0,
6974 : /* 2395 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', 0,
6975 : /* 2405 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', 0,
6976 : /* 2415 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', 0,
6977 : /* 2424 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', 0,
6978 : /* 2433 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', 0,
6979 : /* 2443 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '6', '4', 0,
6980 : /* 2460 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', 0,
6981 : /* 2470 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', 0,
6982 : /* 2480 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', 0,
6983 : /* 2490 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', 0,
6984 : /* 2499 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
6985 : /* 2509 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
6986 : /* 2519 */ 'M', 'O', 'V', 'T', '_', 'D', '6', '4', 0,
6987 : /* 2528 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '6', '4', 0,
6988 : /* 2549 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', 0,
6989 : /* 2558 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', 0,
6990 : /* 2567 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '6', '4', 0,
6991 : /* 2579 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '6', '4', 0,
6992 : /* 2591 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '6', '4', 0,
6993 : /* 2602 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '6', '4', 0,
6994 : /* 2614 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', 0,
6995 : /* 2624 */ 'B', 'N', 'E', '6', '4', 0,
6996 : /* 2630 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 0,
6997 : /* 2643 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', 0,
6998 : /* 2661 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '6', '4', 0,
6999 : /* 2675 */ 'S', 'E', 'H', '6', '4', 0,
7000 : /* 2681 */ 'L', 'H', '6', '4', 0,
7001 : /* 2686 */ 'S', 'H', '6', '4', 0,
7002 : /* 2691 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '6', '4', 0,
7003 : /* 2704 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '6', '4', 0,
7004 : /* 2719 */ 'M', 'T', 'H', 'I', '6', '4', 0,
7005 : /* 2726 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
7006 : /* 2739 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
7007 : /* 2752 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
7008 : /* 2772 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
7009 : /* 2792 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
7010 : /* 2813 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
7011 : /* 2833 */ 'M', 'O', 'V', 'F', '_', 'I', '6', '4', 0,
7012 : /* 2842 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', '6', '4', 0,
7013 : /* 2863 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', '6', '4', 0,
7014 : /* 2874 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', '6', '4', 0,
7015 : /* 2885 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
7016 : /* 2901 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
7017 : /* 2921 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
7018 : /* 2941 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0,
7019 : /* 2960 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0,
7020 : /* 2977 */ 'M', 'O', 'V', 'T', '_', 'I', '6', '4', 0,
7021 : /* 2986 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', '6', '4', 0,
7022 : /* 3007 */ 'L', 'L', '6', '4', 0,
7023 : /* 3012 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'L', '6', '4', 0,
7024 : /* 3023 */ 'L', 'W', 'L', '6', '4', 0,
7025 : /* 3029 */ 'S', 'W', 'L', '6', '4', 0,
7026 : /* 3035 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '6', '4', 0,
7027 : /* 3048 */ 'M', 'T', 'L', 'O', '6', '4', 0,
7028 : /* 3055 */ 'B', 'E', 'Q', '6', '4', 0,
7029 : /* 3061 */ 'J', 'R', '6', '4', 0,
7030 : /* 3066 */ 'J', 'A', 'L', 'R', '6', '4', 0,
7031 : /* 3073 */ 'N', 'O', 'R', '6', '4', 0,
7032 : /* 3079 */ 'X', 'O', 'R', '6', '4', 0,
7033 : /* 3085 */ 'R', 'D', 'H', 'W', 'R', '6', '4', 0,
7034 : /* 3093 */ 'L', 'W', 'R', '6', '4', 0,
7035 : /* 3099 */ 'S', 'W', 'R', '6', '4', 0,
7036 : /* 3105 */ 'P', 'L', 'L', '_', 'P', 'S', '6', '4', 0,
7037 : /* 3114 */ 'P', 'L', 'U', '_', 'P', 'S', '6', '4', 0,
7038 : /* 3123 */ 'C', 'V', 'T', '_', 'P', 'S', '_', 'S', '6', '4', 0,
7039 : /* 3134 */ 'S', 'L', 'T', '6', '4', 0,
7040 : /* 3140 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'U', '6', '4', 0,
7041 : /* 3151 */ 'L', 'W', '6', '4', 0,
7042 : /* 3156 */ 'S', 'W', '6', '4', 0,
7043 : /* 3161 */ 'B', 'G', 'E', 'Z', '6', '4', 0,
7044 : /* 3168 */ 'B', 'L', 'E', 'Z', '6', '4', 0,
7045 : /* 3175 */ 'S', 'E', 'L', 'N', 'E', 'Z', '6', '4', 0,
7046 : /* 3184 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '6', '4', 0,
7047 : /* 3193 */ 'B', 'G', 'T', 'Z', '6', '4', 0,
7048 : /* 3200 */ 'B', 'L', 'T', 'Z', '6', '4', 0,
7049 : /* 3207 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', '_', '6', '4', 0,
7050 : /* 3223 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', '_', '6', '4', 0,
7051 : /* 3244 */ 'S', 'L', 'L', '6', '4', '_', '6', '4', 0,
7052 : /* 3253 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '6', '4', 0,
7053 : /* 3267 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
7054 : /* 3296 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
7055 : /* 3319 */ 'A', 'N', 'D', 'i', '6', '4', 0,
7056 : /* 3326 */ 'X', 'O', 'R', 'i', '6', '4', 0,
7057 : /* 3333 */ 'S', 'L', 'T', 'i', '6', '4', 0,
7058 : /* 3340 */ 'L', 'U', 'i', '6', '4', 0,
7059 : /* 3346 */ 'N', 'O', 'R', 'I', 'm', 'm', '6', '4', 0,
7060 : /* 3355 */ 'S', 'L', 'T', 'I', 'm', 'm', '6', '4', 0,
7061 : /* 3364 */ 'S', 'L', 'T', 'U', 'I', 'm', 'm', '6', '4', 0,
7062 : /* 3374 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '6', '4', 0,
7063 : /* 3384 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '6', '4', 0,
7064 : /* 3398 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
7065 : /* 3413 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
7066 : /* 3429 */ 'L', 'B', 'u', '6', '4', 0,
7067 : /* 3435 */ 'L', 'H', 'u', '6', '4', 0,
7068 : /* 3441 */ 'S', 'L', 'T', 'u', '6', '4', 0,
7069 : /* 3448 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '6', '4', 0,
7070 : /* 3460 */ 'S', 'L', 'T', 'i', 'u', '6', '4', 0,
7071 : /* 3468 */ 'M', 'o', 'v', 'e', 'R', '3', '2', '1', '6', 0,
7072 : /* 3478 */ 'R', 'e', 't', 'R', 'A', '1', '6', 0,
7073 : /* 3486 */ 'J', 'a', 'l', 'B', '1', '6', 0,
7074 : /* 3493 */ 'L', 'D', '_', 'F', '1', '6', 0,
7075 : /* 3500 */ 'S', 'T', '_', 'F', '1', '6', 0,
7076 : /* 3507 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0,
7077 : /* 3527 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0,
7078 : /* 3547 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
7079 : /* 3568 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
7080 : /* 3588 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
7081 : /* 3604 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
7082 : /* 3624 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0,
7083 : /* 3644 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0,
7084 : /* 3663 */ 'M', 'o', 'v', 'e', '3', '2', 'R', '1', '6', 0,
7085 : /* 3673 */ 'S', 'r', 'a', 'X', '1', '6', 0,
7086 : /* 3680 */ 'R', 'e', 's', 't', 'o', 'r', 'e', 'X', '1', '6', 0,
7087 : /* 3691 */ 'S', 'a', 'v', 'e', 'X', '1', '6', 0,
7088 : /* 3699 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
7089 : /* 3714 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
7090 : /* 3729 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
7091 : /* 3744 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
7092 : /* 3759 */ 'S', 'l', 'l', 'X', '1', '6', 0,
7093 : /* 3766 */ 'S', 'r', 'l', 'X', '1', '6', 0,
7094 : /* 3773 */ 'L', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7095 : /* 3789 */ 'S', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7096 : /* 3805 */ 'L', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7097 : /* 3821 */ 'S', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7098 : /* 3837 */ 'L', 'b', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7099 : /* 3854 */ 'L', 'h', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7100 : /* 3871 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7101 : /* 3890 */ 'L', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7102 : /* 3906 */ 'S', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
7103 : /* 3922 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'P', 'c', 'I', 'm', 'm', 'X', '1', '6', 0,
7104 : /* 3938 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
7105 : /* 3952 */ 'L', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
7106 : /* 3965 */ 'S', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
7107 : /* 3978 */ 'S', 'l', 't', 'i', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
7108 : /* 3993 */ 'S', 'l', 't', 'i', 'u', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
7109 : /* 4009 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
7110 : /* 4020 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
7111 : /* 4033 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
|
