LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenRegisterBank.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 3 3 100.0 %
Date: 2018-10-20 13:21:21 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Register Bank Source Fragments                                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_REGBANK_DECLARATIONS
      10             : #undef GET_REGBANK_DECLARATIONS
      11             : namespace llvm {
      12             : namespace Mips {
      13             : enum {
      14             :   GPRBRegBankID,
      15             :   NumRegisterBanks,
      16             : };
      17             : } // end namespace Mips
      18             : } // end namespace llvm
      19             : #endif // GET_REGBANK_DECLARATIONS
      20             : 
      21             : #ifdef GET_TARGET_REGBANK_CLASS
      22             : #undef GET_TARGET_REGBANK_CLASS
      23             : private:
      24             :   static RegisterBank *RegBanks[];
      25             : 
      26             : protected:
      27             :   MipsGenRegisterBankInfo();
      28             : 
      29             : #endif // GET_TARGET_REGBANK_CLASS
      30             : 
      31             : #ifdef GET_TARGET_REGBANK_IMPL
      32             : #undef GET_TARGET_REGBANK_IMPL
      33             : namespace llvm {
      34             : namespace Mips {
      35             : const uint32_t GPRBRegBankCoverageData[] = {
      36             :     // 0-31
      37             :     (1u << (Mips::GPR32RegClassID - 0)) |
      38             :     (1u << (Mips::GPR32NONZERORegClassID - 0)) |
      39             :     (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
      40             :     (1u << (Mips::CPU16RegsRegClassID - 0)) |
      41             :     (1u << (Mips::GPRMM16RegClassID - 0)) |
      42             :     (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
      43             :     (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
      44             :     (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
      45             :     (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
      46             :     (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
      47             :     (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
      48             :     (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
      49             :     0,
      50             :     // 32-63
      51             :     (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 32)) |
      52             :     (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 32)) |
      53             :     (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 32)) |
      54             :     (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
      55             :     (1u << (Mips::CPUSPRegRegClassID - 32)) |
      56             :     (1u << (Mips::SP32RegClassID - 32)) |
      57             :     (1u << (Mips::CPURARegRegClassID - 32)) |
      58             :     (1u << (Mips::GP32RegClassID - 32)) |
      59             :     (1u << (Mips::GPR32ZERORegClassID - 32)) |
      60             :     0,
      61             :     // 64-95
      62             :     0,
      63             : };
      64             : 
      65             : RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 81);
      66             : } // end namespace Mips
      67             : 
      68             : RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
      69             :     &Mips::GPRBRegBank,
      70             : };
      71             : 
      72       10307 : MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
      73       10307 :     : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
      74             :   // Assert that RegBank indices match their ID's
      75             : #ifndef NDEBUG
      76             :   unsigned Index = 0;
      77             :   for (const auto &RB : RegBanks)
      78             :     assert(Index++ == RB->getID() && "Index != ID");
      79             : #endif // NDEBUG
      80       10307 : }
      81             : } // end namespace llvm
      82             : #endif // GET_TARGET_REGBANK_IMPL

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