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1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : namespace NVPTX {
15 : enum {
16 : PTX32 = 0,
17 : PTX40 = 1,
18 : PTX41 = 2,
19 : PTX42 = 3,
20 : PTX43 = 4,
21 : PTX50 = 5,
22 : PTX60 = 6,
23 : PTX61 = 7,
24 : PTX63 = 8,
25 : SM20 = 9,
26 : SM21 = 10,
27 : SM30 = 11,
28 : SM32 = 12,
29 : SM35 = 13,
30 : SM37 = 14,
31 : SM50 = 15,
32 : SM52 = 16,
33 : SM53 = 17,
34 : SM60 = 18,
35 : SM61 = 19,
36 : SM62 = 20,
37 : SM70 = 21,
38 : SM72 = 22,
39 : SM75 = 23,
40 : };
41 : } // end namespace NVPTX
42 : } // end namespace llvm
43 :
44 : #endif // GET_SUBTARGETINFO_ENUM
45 :
46 :
47 : #ifdef GET_SUBTARGETINFO_MC_DESC
48 : #undef GET_SUBTARGETINFO_MC_DESC
49 :
50 : namespace llvm {
51 : // Sorted (by key) array of values for CPU features.
52 : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
53 : { "ptx32", "Use PTX version 3.2", { NVPTX::PTX32 }, { } },
54 : { "ptx40", "Use PTX version 4.0", { NVPTX::PTX40 }, { } },
55 : { "ptx41", "Use PTX version 4.1", { NVPTX::PTX41 }, { } },
56 : { "ptx42", "Use PTX version 4.2", { NVPTX::PTX42 }, { } },
57 : { "ptx43", "Use PTX version 4.3", { NVPTX::PTX43 }, { } },
58 : { "ptx50", "Use PTX version 5.0", { NVPTX::PTX50 }, { } },
59 : { "ptx60", "Use PTX version 6.0", { NVPTX::PTX60 }, { } },
60 : { "ptx61", "Use PTX version 6.1", { NVPTX::PTX61 }, { } },
61 : { "ptx63", "Use PTX version 6.3", { NVPTX::PTX63 }, { } },
62 : { "sm_20", "Target SM 2.0", { NVPTX::SM20 }, { } },
63 : { "sm_21", "Target SM 2.1", { NVPTX::SM21 }, { } },
64 : { "sm_30", "Target SM 3.0", { NVPTX::SM30 }, { } },
65 : { "sm_32", "Target SM 3.2", { NVPTX::SM32 }, { } },
66 : { "sm_35", "Target SM 3.5", { NVPTX::SM35 }, { } },
67 : { "sm_37", "Target SM 3.7", { NVPTX::SM37 }, { } },
68 : { "sm_50", "Target SM 5.0", { NVPTX::SM50 }, { } },
69 : { "sm_52", "Target SM 5.2", { NVPTX::SM52 }, { } },
70 : { "sm_53", "Target SM 5.3", { NVPTX::SM53 }, { } },
71 : { "sm_60", "Target SM 6.0", { NVPTX::SM60 }, { } },
72 : { "sm_61", "Target SM 6.1", { NVPTX::SM61 }, { } },
73 : { "sm_62", "Target SM 6.2", { NVPTX::SM62 }, { } },
74 : { "sm_70", "Target SM 7.0", { NVPTX::SM70 }, { } },
75 : { "sm_72", "Target SM 7.2", { NVPTX::SM72 }, { } },
76 : { "sm_75", "Target SM 7.5", { NVPTX::SM75 }, { } },
77 : };
78 :
79 : // Sorted (by key) array of values for CPU subtype.
80 : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[] = {
81 : { "sm_20", "Select the sm_20 processor", { NVPTX::SM20 }, { } },
82 : { "sm_21", "Select the sm_21 processor", { NVPTX::SM21 }, { } },
83 : { "sm_30", "Select the sm_30 processor", { NVPTX::SM30 }, { } },
84 : { "sm_32", "Select the sm_32 processor", { NVPTX::SM32, NVPTX::PTX40 }, { } },
85 : { "sm_35", "Select the sm_35 processor", { NVPTX::SM35 }, { } },
86 : { "sm_37", "Select the sm_37 processor", { NVPTX::SM37, NVPTX::PTX41 }, { } },
87 : { "sm_50", "Select the sm_50 processor", { NVPTX::SM50, NVPTX::PTX40 }, { } },
88 : { "sm_52", "Select the sm_52 processor", { NVPTX::SM52, NVPTX::PTX41 }, { } },
89 : { "sm_53", "Select the sm_53 processor", { NVPTX::SM53, NVPTX::PTX42 }, { } },
90 : { "sm_60", "Select the sm_60 processor", { NVPTX::SM60, NVPTX::PTX50 }, { } },
91 : { "sm_61", "Select the sm_61 processor", { NVPTX::SM61, NVPTX::PTX50 }, { } },
92 : { "sm_62", "Select the sm_62 processor", { NVPTX::SM62, NVPTX::PTX50 }, { } },
93 : { "sm_70", "Select the sm_70 processor", { NVPTX::SM70, NVPTX::PTX60 }, { } },
94 : { "sm_72", "Select the sm_72 processor", { NVPTX::SM72, NVPTX::PTX61 }, { } },
95 : { "sm_75", "Select the sm_75 processor", { NVPTX::SM75, NVPTX::PTX63 }, { } },
96 : };
97 :
98 : #ifdef DBGFIELD
99 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
100 : #endif
101 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
102 : #define DBGFIELD(x) x,
103 : #else
104 : #define DBGFIELD(x)
105 : #endif
106 :
107 : // ===============================================================
108 : // Data tables for the new per-operand machine model.
109 :
110 : // {ProcResourceIdx, Cycles}
111 : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
112 : { 0, 0}, // Invalid
113 : }; // NVPTXWriteProcResTable
114 :
115 : // {Cycles, WriteResourceID}
116 : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
117 : { 0, 0}, // Invalid
118 : }; // NVPTXWriteLatencyTable
119 :
120 : // {UseIdx, WriteResourceID, Cycles}
121 : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
122 : {0, 0, 0}, // Invalid
123 : }; // NVPTXReadAdvanceTable
124 :
125 : static const llvm::MCSchedModel NoSchedModel = {
126 : MCSchedModel::DefaultIssueWidth,
127 : MCSchedModel::DefaultMicroOpBufferSize,
128 : MCSchedModel::DefaultLoopMicroOpBufferSize,
129 : MCSchedModel::DefaultLoadLatency,
130 : MCSchedModel::DefaultHighLatency,
131 : MCSchedModel::DefaultMispredictPenalty,
132 : false, // PostRAScheduler
133 : false, // CompleteModel
134 : 0, // Processor ID
135 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
136 : nullptr, // No Itinerary
137 : nullptr // No extra processor descriptor
138 : };
139 :
140 : // Sorted (by key) array of itineraries for CPU subtype.
141 : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[] = {
142 : { "sm_20", (const void *)&NoSchedModel },
143 : { "sm_21", (const void *)&NoSchedModel },
144 : { "sm_30", (const void *)&NoSchedModel },
145 : { "sm_32", (const void *)&NoSchedModel },
146 : { "sm_35", (const void *)&NoSchedModel },
147 : { "sm_37", (const void *)&NoSchedModel },
148 : { "sm_50", (const void *)&NoSchedModel },
149 : { "sm_52", (const void *)&NoSchedModel },
150 : { "sm_53", (const void *)&NoSchedModel },
151 : { "sm_60", (const void *)&NoSchedModel },
152 : { "sm_61", (const void *)&NoSchedModel },
153 : { "sm_62", (const void *)&NoSchedModel },
154 : { "sm_70", (const void *)&NoSchedModel },
155 : { "sm_72", (const void *)&NoSchedModel },
156 : { "sm_75", (const void *)&NoSchedModel },
157 : };
158 :
159 : #undef DBGFIELD
160 : namespace NVPTX_MC {
161 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
162 : const MCInst *MI, unsigned CPUID) {
163 : // Don't know how to resolve this scheduling class.
164 0 : return 0;
165 : }
166 : } // end of namespace NVPTX_MC
167 :
168 : struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
169 : NVPTXGenMCSubtargetInfo(const Triple &TT,
170 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
171 : ArrayRef<SubtargetFeatureKV> PD,
172 : const SubtargetInfoKV *ProcSched,
173 : const MCWriteProcResEntry *WPR,
174 : const MCWriteLatencyEntry *WL,
175 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
176 411 : const unsigned *OC, const unsigned *FP) :
177 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
178 411 : WPR, WL, RA, IS, OC, FP) { }
179 :
180 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
181 : const MCInst *MI, unsigned CPUID) const override {
182 0 : return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
183 : }
184 : };
185 :
186 411 : static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
187 : return new NVPTXGenMCSubtargetInfo(TT, CPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV,
188 : NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
189 411 : nullptr, nullptr, nullptr);
190 : }
191 :
192 : } // end namespace llvm
193 :
194 : #endif // GET_SUBTARGETINFO_MC_DESC
195 :
196 :
197 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
198 : #undef GET_SUBTARGETINFO_TARGET_DESC
199 :
200 : #include "llvm/Support/Debug.h"
201 : #include "llvm/Support/raw_ostream.h"
202 :
203 : // ParseSubtargetFeatures - Parses features string setting specified
204 : // subtarget options.
205 655 : void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
206 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
207 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
208 655 : InitMCProcessorInfo(CPU, FS);
209 : const FeatureBitset& Bits = getFeatureBits();
210 655 : if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
211 655 : if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
212 655 : if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
213 655 : if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
214 655 : if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
215 655 : if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
216 655 : if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
217 655 : if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
218 655 : if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
219 655 : if (Bits[NVPTX::SM20] && SmVersion < 20) SmVersion = 20;
220 655 : if (Bits[NVPTX::SM21] && SmVersion < 21) SmVersion = 21;
221 655 : if (Bits[NVPTX::SM30] && SmVersion < 30) SmVersion = 30;
222 655 : if (Bits[NVPTX::SM32] && SmVersion < 32) SmVersion = 32;
223 655 : if (Bits[NVPTX::SM35] && SmVersion < 35) SmVersion = 35;
224 655 : if (Bits[NVPTX::SM37] && SmVersion < 37) SmVersion = 37;
225 655 : if (Bits[NVPTX::SM50] && SmVersion < 50) SmVersion = 50;
226 655 : if (Bits[NVPTX::SM52] && SmVersion < 52) SmVersion = 52;
227 655 : if (Bits[NVPTX::SM53] && SmVersion < 53) SmVersion = 53;
228 655 : if (Bits[NVPTX::SM60] && SmVersion < 60) SmVersion = 60;
229 655 : if (Bits[NVPTX::SM61] && SmVersion < 61) SmVersion = 61;
230 655 : if (Bits[NVPTX::SM62] && SmVersion < 62) SmVersion = 62;
231 655 : if (Bits[NVPTX::SM70] && SmVersion < 70) SmVersion = 70;
232 655 : if (Bits[NVPTX::SM72] && SmVersion < 72) SmVersion = 72;
233 655 : if (Bits[NVPTX::SM75] && SmVersion < 75) SmVersion = 75;
234 655 : }
235 : #endif // GET_SUBTARGETINFO_TARGET_DESC
236 :
237 :
238 : #ifdef GET_SUBTARGETINFO_HEADER
239 : #undef GET_SUBTARGETINFO_HEADER
240 :
241 : namespace llvm {
242 : class DFAPacketizer;
243 : namespace NVPTX_MC {
244 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
245 : }
246 :
247 : struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
248 : explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
249 : public:
250 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
251 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
252 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
253 : };
254 : } // end namespace llvm
255 :
256 : #endif // GET_SUBTARGETINFO_HEADER
257 :
258 :
259 : #ifdef GET_SUBTARGETINFO_CTOR
260 : #undef GET_SUBTARGETINFO_CTOR
261 :
262 : #include "llvm/CodeGen/TargetSchedule.h"
263 :
264 : namespace llvm {
265 : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
266 : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[];
267 : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[];
268 : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
269 : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
270 : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
271 655 : NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
272 : : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(NVPTXFeatureKV, 24), makeArrayRef(NVPTXSubTypeKV, 15),
273 : NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
274 655 : nullptr, nullptr, nullptr) {}
275 :
276 0 : unsigned NVPTXGenSubtargetInfo
277 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
278 0 : report_fatal_error("Expected a variant SchedClass");
279 : } // NVPTXGenSubtargetInfo::resolveSchedClass
280 :
281 0 : unsigned NVPTXGenSubtargetInfo
282 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
283 0 : return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
284 : } // NVPTXGenSubtargetInfo::resolveVariantSchedClass
285 :
286 : } // end namespace llvm
287 :
288 : #endif // GET_SUBTARGETINFO_CTOR
289 :
290 :
291 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
292 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
293 :
294 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
295 :
296 :
297 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
298 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
299 :
300 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
301 :
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