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1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : namespace WebAssembly {
15 : enum {
16 : FeatureAtomics = 0,
17 : FeatureExceptionHandling = 1,
18 : FeatureNontrappingFPToInt = 2,
19 : FeatureSIMD128 = 3,
20 : FeatureSignExt = 4,
21 : };
22 : } // end namespace WebAssembly
23 : } // end namespace llvm
24 :
25 : #endif // GET_SUBTARGETINFO_ENUM
26 :
27 :
28 : #ifdef GET_SUBTARGETINFO_MC_DESC
29 : #undef GET_SUBTARGETINFO_MC_DESC
30 :
31 : namespace llvm {
32 : // Sorted (by key) array of values for CPU features.
33 : extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[] = {
34 : { "atomics", "Enable Atomics", { WebAssembly::FeatureAtomics }, { } },
35 : { "exception-handling", "Enable Wasm exception handling", { WebAssembly::FeatureExceptionHandling }, { } },
36 : { "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", { WebAssembly::FeatureNontrappingFPToInt }, { } },
37 : { "sign-ext", "Enable sign extension operators", { WebAssembly::FeatureSignExt }, { } },
38 : { "simd128", "Enable 128-bit SIMD", { WebAssembly::FeatureSIMD128 }, { } },
39 : };
40 :
41 : // Sorted (by key) array of values for CPU subtype.
42 : extern const llvm::SubtargetFeatureKV WebAssemblySubTypeKV[] = {
43 : { "bleeding-edge", "Select the bleeding-edge processor", { WebAssembly::FeatureSIMD128, WebAssembly::FeatureAtomics }, { } },
44 : { "generic", "Select the generic processor", { }, { } },
45 : { "mvp", "Select the mvp processor", { }, { } },
46 : };
47 :
48 : #ifdef DBGFIELD
49 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
50 : #endif
51 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
52 : #define DBGFIELD(x) x,
53 : #else
54 : #define DBGFIELD(x)
55 : #endif
56 :
57 : // ===============================================================
58 : // Data tables for the new per-operand machine model.
59 :
60 : // {ProcResourceIdx, Cycles}
61 : extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
62 : { 0, 0}, // Invalid
63 : }; // WebAssemblyWriteProcResTable
64 :
65 : // {Cycles, WriteResourceID}
66 : extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
67 : { 0, 0}, // Invalid
68 : }; // WebAssemblyWriteLatencyTable
69 :
70 : // {UseIdx, WriteResourceID, Cycles}
71 : extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
72 : {0, 0, 0}, // Invalid
73 : }; // WebAssemblyReadAdvanceTable
74 :
75 : static const llvm::MCSchedModel NoSchedModel = {
76 : MCSchedModel::DefaultIssueWidth,
77 : MCSchedModel::DefaultMicroOpBufferSize,
78 : MCSchedModel::DefaultLoopMicroOpBufferSize,
79 : MCSchedModel::DefaultLoadLatency,
80 : MCSchedModel::DefaultHighLatency,
81 : MCSchedModel::DefaultMispredictPenalty,
82 : false, // PostRAScheduler
83 : false, // CompleteModel
84 : 0, // Processor ID
85 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
86 : nullptr, // No Itinerary
87 : nullptr // No extra processor descriptor
88 : };
89 :
90 : // Sorted (by key) array of itineraries for CPU subtype.
91 : extern const llvm::SubtargetInfoKV WebAssemblyProcSchedKV[] = {
92 : { "bleeding-edge", (const void *)&NoSchedModel },
93 : { "generic", (const void *)&NoSchedModel },
94 : { "mvp", (const void *)&NoSchedModel },
95 : };
96 :
97 : #undef DBGFIELD
98 : namespace WebAssembly_MC {
99 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
100 : const MCInst *MI, unsigned CPUID) {
101 : // Don't know how to resolve this scheduling class.
102 0 : return 0;
103 : }
104 : } // end of namespace WebAssembly_MC
105 :
106 : struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
107 : WebAssemblyGenMCSubtargetInfo(const Triple &TT,
108 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
109 : ArrayRef<SubtargetFeatureKV> PD,
110 : const SubtargetInfoKV *ProcSched,
111 : const MCWriteProcResEntry *WPR,
112 : const MCWriteLatencyEntry *WL,
113 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
114 356 : const unsigned *OC, const unsigned *FP) :
115 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
116 356 : WPR, WL, RA, IS, OC, FP) { }
117 :
118 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
119 : const MCInst *MI, unsigned CPUID) const override {
120 0 : return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
121 : }
122 : };
123 :
124 356 : static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
125 : return new WebAssemblyGenMCSubtargetInfo(TT, CPU, FS, WebAssemblyFeatureKV, WebAssemblySubTypeKV,
126 : WebAssemblyProcSchedKV, WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
127 356 : nullptr, nullptr, nullptr);
128 : }
129 :
130 : } // end namespace llvm
131 :
132 : #endif // GET_SUBTARGETINFO_MC_DESC
133 :
134 :
135 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
136 : #undef GET_SUBTARGETINFO_TARGET_DESC
137 :
138 : #include "llvm/Support/Debug.h"
139 : #include "llvm/Support/raw_ostream.h"
140 :
141 : // ParseSubtargetFeatures - Parses features string setting specified
142 : // subtarget options.
143 293 : void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
144 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
145 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
146 293 : InitMCProcessorInfo(CPU, FS);
147 : const FeatureBitset& Bits = getFeatureBits();
148 293 : if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
149 293 : if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
150 293 : if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
151 293 : if (Bits[WebAssembly::FeatureSIMD128]) HasSIMD128 = true;
152 293 : if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
153 293 : }
154 : #endif // GET_SUBTARGETINFO_TARGET_DESC
155 :
156 :
157 : #ifdef GET_SUBTARGETINFO_HEADER
158 : #undef GET_SUBTARGETINFO_HEADER
159 :
160 : namespace llvm {
161 : class DFAPacketizer;
162 : namespace WebAssembly_MC {
163 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
164 : }
165 :
166 : struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
167 : explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
168 : public:
169 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
170 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
171 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
172 : };
173 : } // end namespace llvm
174 :
175 : #endif // GET_SUBTARGETINFO_HEADER
176 :
177 :
178 : #ifdef GET_SUBTARGETINFO_CTOR
179 : #undef GET_SUBTARGETINFO_CTOR
180 :
181 : #include "llvm/CodeGen/TargetSchedule.h"
182 :
183 : namespace llvm {
184 : extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[];
185 : extern const llvm::SubtargetFeatureKV WebAssemblySubTypeKV[];
186 : extern const llvm::SubtargetInfoKV WebAssemblyProcSchedKV[];
187 : extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
188 : extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
189 : extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
190 293 : WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
191 : : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(WebAssemblyFeatureKV, 5), makeArrayRef(WebAssemblySubTypeKV, 3),
192 : WebAssemblyProcSchedKV, WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
193 293 : nullptr, nullptr, nullptr) {}
194 :
195 0 : unsigned WebAssemblyGenSubtargetInfo
196 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
197 0 : report_fatal_error("Expected a variant SchedClass");
198 : } // WebAssemblyGenSubtargetInfo::resolveSchedClass
199 :
200 0 : unsigned WebAssemblyGenSubtargetInfo
201 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
202 0 : return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
203 : } // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
204 :
205 : } // end namespace llvm
206 :
207 : #endif // GET_SUBTARGETINFO_CTOR
208 :
209 :
210 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
211 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
212 :
213 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
214 :
215 :
216 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
217 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
218 :
219 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
220 :
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