Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Calling Convention Implementation Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10 : MVT LocVT, CCValAssign::LocInfo LocInfo,
11 : ISD::ArgFlagsTy ArgFlags, CCState &State);
12 : static bool CC_X86(unsigned ValNo, MVT ValVT,
13 : MVT LocVT, CCValAssign::LocInfo LocInfo,
14 : ISD::ArgFlagsTy ArgFlags, CCState &State);
15 : static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16 : MVT LocVT, CCValAssign::LocInfo LocInfo,
17 : ISD::ArgFlagsTy ArgFlags, CCState &State);
18 : static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19 : MVT LocVT, CCValAssign::LocInfo LocInfo,
20 : ISD::ArgFlagsTy ArgFlags, CCState &State);
21 : static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22 : MVT LocVT, CCValAssign::LocInfo LocInfo,
23 : ISD::ArgFlagsTy ArgFlags, CCState &State);
24 : static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
25 : MVT LocVT, CCValAssign::LocInfo LocInfo,
26 : ISD::ArgFlagsTy ArgFlags, CCState &State);
27 : static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
28 : MVT LocVT, CCValAssign::LocInfo LocInfo,
29 : ISD::ArgFlagsTy ArgFlags, CCState &State);
30 : static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
31 : MVT LocVT, CCValAssign::LocInfo LocInfo,
32 : ISD::ArgFlagsTy ArgFlags, CCState &State);
33 : static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
34 : MVT LocVT, CCValAssign::LocInfo LocInfo,
35 : ISD::ArgFlagsTy ArgFlags, CCState &State);
36 : static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
37 : MVT LocVT, CCValAssign::LocInfo LocInfo,
38 : ISD::ArgFlagsTy ArgFlags, CCState &State);
39 : static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
40 : MVT LocVT, CCValAssign::LocInfo LocInfo,
41 : ISD::ArgFlagsTy ArgFlags, CCState &State);
42 : static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
43 : MVT LocVT, CCValAssign::LocInfo LocInfo,
44 : ISD::ArgFlagsTy ArgFlags, CCState &State);
45 : static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
46 : MVT LocVT, CCValAssign::LocInfo LocInfo,
47 : ISD::ArgFlagsTy ArgFlags, CCState &State);
48 : static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
49 : MVT LocVT, CCValAssign::LocInfo LocInfo,
50 : ISD::ArgFlagsTy ArgFlags, CCState &State);
51 : static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
52 : MVT LocVT, CCValAssign::LocInfo LocInfo,
53 : ISD::ArgFlagsTy ArgFlags, CCState &State);
54 : static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
55 : MVT LocVT, CCValAssign::LocInfo LocInfo,
56 : ISD::ArgFlagsTy ArgFlags, CCState &State);
57 : static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
58 : MVT LocVT, CCValAssign::LocInfo LocInfo,
59 : ISD::ArgFlagsTy ArgFlags, CCState &State);
60 : static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
61 : MVT LocVT, CCValAssign::LocInfo LocInfo,
62 : ISD::ArgFlagsTy ArgFlags, CCState &State);
63 : static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
64 : MVT LocVT, CCValAssign::LocInfo LocInfo,
65 : ISD::ArgFlagsTy ArgFlags, CCState &State);
66 : static bool CC_X86_64(unsigned ValNo, MVT ValVT,
67 : MVT LocVT, CCValAssign::LocInfo LocInfo,
68 : ISD::ArgFlagsTy ArgFlags, CCState &State);
69 : static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
70 : MVT LocVT, CCValAssign::LocInfo LocInfo,
71 : ISD::ArgFlagsTy ArgFlags, CCState &State);
72 : static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
73 : MVT LocVT, CCValAssign::LocInfo LocInfo,
74 : ISD::ArgFlagsTy ArgFlags, CCState &State);
75 : static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
76 : MVT LocVT, CCValAssign::LocInfo LocInfo,
77 : ISD::ArgFlagsTy ArgFlags, CCState &State);
78 : static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
79 : MVT LocVT, CCValAssign::LocInfo LocInfo,
80 : ISD::ArgFlagsTy ArgFlags, CCState &State);
81 : static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
82 : MVT LocVT, CCValAssign::LocInfo LocInfo,
83 : ISD::ArgFlagsTy ArgFlags, CCState &State);
84 : static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
85 : MVT LocVT, CCValAssign::LocInfo LocInfo,
86 : ISD::ArgFlagsTy ArgFlags, CCState &State);
87 : static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
88 : MVT LocVT, CCValAssign::LocInfo LocInfo,
89 : ISD::ArgFlagsTy ArgFlags, CCState &State);
90 : static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
91 : MVT LocVT, CCValAssign::LocInfo LocInfo,
92 : ISD::ArgFlagsTy ArgFlags, CCState &State);
93 : static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
94 : MVT LocVT, CCValAssign::LocInfo LocInfo,
95 : ISD::ArgFlagsTy ArgFlags, CCState &State);
96 : static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
97 : MVT LocVT, CCValAssign::LocInfo LocInfo,
98 : ISD::ArgFlagsTy ArgFlags, CCState &State);
99 : static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
100 : MVT LocVT, CCValAssign::LocInfo LocInfo,
101 : ISD::ArgFlagsTy ArgFlags, CCState &State);
102 : static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
103 : MVT LocVT, CCValAssign::LocInfo LocInfo,
104 : ISD::ArgFlagsTy ArgFlags, CCState &State);
105 : static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
106 : MVT LocVT, CCValAssign::LocInfo LocInfo,
107 : ISD::ArgFlagsTy ArgFlags, CCState &State);
108 : static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
109 : MVT LocVT, CCValAssign::LocInfo LocInfo,
110 : ISD::ArgFlagsTy ArgFlags, CCState &State);
111 : static bool RetCC_X86(unsigned ValNo, MVT ValVT,
112 : MVT LocVT, CCValAssign::LocInfo LocInfo,
113 : ISD::ArgFlagsTy ArgFlags, CCState &State);
114 : static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
115 : MVT LocVT, CCValAssign::LocInfo LocInfo,
116 : ISD::ArgFlagsTy ArgFlags, CCState &State);
117 : static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
118 : MVT LocVT, CCValAssign::LocInfo LocInfo,
119 : ISD::ArgFlagsTy ArgFlags, CCState &State);
120 : static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
121 : MVT LocVT, CCValAssign::LocInfo LocInfo,
122 : ISD::ArgFlagsTy ArgFlags, CCState &State);
123 : static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
124 : MVT LocVT, CCValAssign::LocInfo LocInfo,
125 : ISD::ArgFlagsTy ArgFlags, CCState &State);
126 : static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
127 : MVT LocVT, CCValAssign::LocInfo LocInfo,
128 : ISD::ArgFlagsTy ArgFlags, CCState &State);
129 : static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
130 : MVT LocVT, CCValAssign::LocInfo LocInfo,
131 : ISD::ArgFlagsTy ArgFlags, CCState &State);
132 : static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
133 : MVT LocVT, CCValAssign::LocInfo LocInfo,
134 : ISD::ArgFlagsTy ArgFlags, CCState &State);
135 : static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
136 : MVT LocVT, CCValAssign::LocInfo LocInfo,
137 : ISD::ArgFlagsTy ArgFlags, CCState &State);
138 : static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
139 : MVT LocVT, CCValAssign::LocInfo LocInfo,
140 : ISD::ArgFlagsTy ArgFlags, CCState &State);
141 : static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
142 : MVT LocVT, CCValAssign::LocInfo LocInfo,
143 : ISD::ArgFlagsTy ArgFlags, CCState &State);
144 : static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
145 : MVT LocVT, CCValAssign::LocInfo LocInfo,
146 : ISD::ArgFlagsTy ArgFlags, CCState &State);
147 : static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
148 : MVT LocVT, CCValAssign::LocInfo LocInfo,
149 : ISD::ArgFlagsTy ArgFlags, CCState &State);
150 : static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
151 : MVT LocVT, CCValAssign::LocInfo LocInfo,
152 : ISD::ArgFlagsTy ArgFlags, CCState &State);
153 : static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
154 : MVT LocVT, CCValAssign::LocInfo LocInfo,
155 : ISD::ArgFlagsTy ArgFlags, CCState &State);
156 : static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
157 : MVT LocVT, CCValAssign::LocInfo LocInfo,
158 : ISD::ArgFlagsTy ArgFlags, CCState &State);
159 : static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
160 : MVT LocVT, CCValAssign::LocInfo LocInfo,
161 : ISD::ArgFlagsTy ArgFlags, CCState &State);
162 : static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
163 : MVT LocVT, CCValAssign::LocInfo LocInfo,
164 : ISD::ArgFlagsTy ArgFlags, CCState &State);
165 : static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
166 : MVT LocVT, CCValAssign::LocInfo LocInfo,
167 : ISD::ArgFlagsTy ArgFlags, CCState &State);
168 :
169 :
170 238 : static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
171 : MVT LocVT, CCValAssign::LocInfo LocInfo,
172 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
173 :
174 238 : if (LocVT == MVT::i32) {
175 22 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
176 : static const MCPhysReg RegList1[] = {
177 : X86::ECX, X86::EDX, X86::R8D, X86::R9D
178 : };
179 2 : if (unsigned Reg = State.AllocateReg(RegList1)) {
180 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181 2 : return false;
182 : }
183 : }
184 : }
185 :
186 236 : if (LocVT == MVT::i64) {
187 16 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
188 : static const MCPhysReg RegList2[] = {
189 : X86::RCX, X86::RDX, X86::R8, X86::R9
190 : };
191 8 : if (unsigned Reg = State.AllocateReg(RegList2)) {
192 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193 8 : return false;
194 : }
195 : }
196 : }
197 :
198 228 : if (LocVT == MVT::i32) {
199 20 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
200 : static const MCPhysReg RegList3[] = {
201 : X86::EDI, X86::ESI, X86::EDX, X86::ECX
202 : };
203 2 : if (unsigned Reg = State.AllocateReg(RegList3)) {
204 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205 2 : return false;
206 : }
207 : }
208 : }
209 :
210 226 : if (LocVT == MVT::i64) {
211 8 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
212 : static const MCPhysReg RegList4[] = {
213 : X86::RDI, X86::RSI, X86::RDX, X86::RCX
214 : };
215 8 : if (unsigned Reg = State.AllocateReg(RegList4)) {
216 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217 8 : return false;
218 : }
219 : }
220 : }
221 :
222 218 : if (LocVT == MVT::i32) {
223 18 : unsigned Offset5 = State.AllocateStack(4, 4);
224 18 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225 18 : return false;
226 : }
227 :
228 200 : if (LocVT == MVT::f32 ||
229 200 : LocVT == MVT::f64 ||
230 200 : LocVT == MVT::v4i32 ||
231 200 : LocVT == MVT::v2i64 ||
232 328 : LocVT == MVT::v4f32 ||
233 : LocVT == MVT::v2f64) {
234 : static const MCPhysReg RegList6[] = {
235 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236 : };
237 72 : if (unsigned Reg = State.AllocateReg(RegList6)) {
238 60 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239 60 : return false;
240 : }
241 : }
242 :
243 108 : if (LocVT == MVT::v8f32 ||
244 108 : LocVT == MVT::v4f64 ||
245 248 : LocVT == MVT::v8i32 ||
246 : LocVT == MVT::v4i64) {
247 : static const MCPhysReg RegList7[] = {
248 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249 : };
250 32 : if (unsigned Reg = State.AllocateReg(RegList7)) {
251 32 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252 32 : return false;
253 : }
254 : }
255 :
256 52 : if (LocVT == MVT::v16f32 ||
257 52 : LocVT == MVT::v8f64 ||
258 144 : LocVT == MVT::v16i32 ||
259 : LocVT == MVT::v8i64) {
260 : static const MCPhysReg RegList8[] = {
261 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262 : };
263 72 : if (unsigned Reg = State.AllocateReg(RegList8)) {
264 72 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265 72 : return false;
266 : }
267 : }
268 :
269 36 : if (LocVT == MVT::v16i1 ||
270 : LocVT == MVT::v8i1) {
271 : if (unsigned Reg = State.AllocateReg(X86::K1)) {
272 24 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273 24 : return false;
274 : }
275 : }
276 :
277 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
278 4 : if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279 : return false;
280 : }
281 :
282 8 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
283 4 : if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284 : return false;
285 : }
286 :
287 4 : if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
288 4 : return false;
289 :
290 : return true; // CC didn't match.
291 : }
292 :
293 :
294 4371290 : static bool CC_X86(unsigned ValNo, MVT ValVT,
295 : MVT LocVT, CCValAssign::LocInfo LocInfo,
296 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
297 :
298 4371290 : if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299 238 : if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300 : return false;
301 : }
302 :
303 4371052 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304 4239117 : if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305 : return false;
306 : }
307 :
308 133790 : if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309 133790 : return false;
310 :
311 : return true; // CC didn't match.
312 : }
313 :
314 :
315 133790 : static bool CC_X86_32(unsigned ValNo, MVT ValVT,
316 : MVT LocVT, CCValAssign::LocInfo LocInfo,
317 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
318 :
319 133790 : if (State.getCallingConv() == CallingConv::X86_INTR) {
320 16 : if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321 : return false;
322 : }
323 :
324 267548 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325 126 : if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326 : return false;
327 : }
328 :
329 133648 : if (State.getCallingConv() == CallingConv::X86_FastCall) {
330 204 : if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331 : return false;
332 : }
333 :
334 133450 : if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335 244 : if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336 : return false;
337 : }
338 :
339 133206 : if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340 448 : if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341 : return false;
342 : }
343 :
344 132758 : if (State.getCallingConv() == CallingConv::Fast) {
345 1164 : if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346 : return false;
347 : }
348 :
349 131594 : if (State.getCallingConv() == CallingConv::GHC) {
350 20 : if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351 : return false;
352 : }
353 :
354 131574 : if (State.getCallingConv() == CallingConv::HiPE) {
355 42 : if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356 : return false;
357 : }
358 :
359 131532 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
360 200 : if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361 : return false;
362 : }
363 :
364 131332 : if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365 131332 : return false;
366 :
367 : return true; // CC didn't match.
368 : }
369 :
370 :
371 131336 : static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
372 : MVT LocVT, CCValAssign::LocInfo LocInfo,
373 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
374 :
375 131334 : if (LocVT == MVT::i1 ||
376 123467 : LocVT == MVT::i8 ||
377 252908 : LocVT == MVT::i16 ||
378 : LocVT == MVT::v1i1) {
379 : LocVT = MVT::i32;
380 9769 : if (ArgFlags.isSExt())
381 : LocInfo = CCValAssign::SExt;
382 9629 : else if (ArgFlags.isZExt())
383 : LocInfo = CCValAssign::ZExt;
384 : else
385 : LocInfo = CCValAssign::AExt;
386 : }
387 :
388 131336 : if (ArgFlags.isNest()) {
389 : if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391 8 : return false;
392 : }
393 : }
394 :
395 131328 : if (!State.isVarArg()) {
396 129846 : if (ArgFlags.isInReg()) {
397 290 : if (LocVT == MVT::i32) {
398 : static const MCPhysReg RegList1[] = {
399 : X86::EAX, X86::EDX, X86::ECX
400 : };
401 266 : if (unsigned Reg = State.AllocateReg(RegList1)) {
402 257 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403 257 : return false;
404 : }
405 : }
406 : }
407 : }
408 :
409 131071 : if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410 131071 : return false;
411 :
412 : return true; // CC didn't match.
413 : }
414 :
415 :
416 131738 : static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
417 : MVT LocVT, CCValAssign::LocInfo LocInfo,
418 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
419 :
420 131738 : if (ArgFlags.isByVal()) {
421 790 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422 790 : return false;
423 : }
424 :
425 130948 : if (!State.isVarArg()) {
426 129461 : if (ArgFlags.isInReg()) {
427 62 : if (LocVT == MVT::f32 ||
428 : LocVT == MVT::f64) {
429 16 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430 : static const MCPhysReg RegList1[] = {
431 : X86::XMM0, X86::XMM1, X86::XMM2
432 : };
433 0 : if (unsigned Reg = State.AllocateReg(RegList1)) {
434 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435 0 : return false;
436 : }
437 : }
438 : }
439 : }
440 : }
441 :
442 130948 : if (!State.isVarArg()) {
443 129461 : if (LocVT == MVT::x86mmx) {
444 : static const MCPhysReg RegList2[] = {
445 : X86::MM0, X86::MM1, X86::MM2
446 : };
447 1867 : if (unsigned Reg = State.AllocateReg(RegList2)) {
448 1867 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449 1867 : return false;
450 : }
451 : }
452 : }
453 :
454 129081 : if (LocVT == MVT::i32 ||
455 : LocVT == MVT::f32) {
456 109658 : unsigned Offset3 = State.AllocateStack(4, 4);
457 109658 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458 109658 : return false;
459 : }
460 :
461 19423 : if (LocVT == MVT::f64) {
462 621 : unsigned Offset4 = State.AllocateStack(8, 4);
463 621 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464 621 : return false;
465 : }
466 :
467 18802 : if (LocVT == MVT::f80) {
468 176 : unsigned Offset5 = State.AllocateStack(
469 352 : State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470 176 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471 176 : return false;
472 : }
473 :
474 18626 : if (LocVT == MVT::v2i1) {
475 : LocVT = MVT::v2i64;
476 22 : if (ArgFlags.isSExt())
477 : LocInfo = CCValAssign::SExt;
478 22 : else if (ArgFlags.isZExt())
479 : LocInfo = CCValAssign::ZExt;
480 : else
481 : LocInfo = CCValAssign::AExt;
482 : }
483 :
484 18626 : if (LocVT == MVT::v4i1) {
485 : LocVT = MVT::v4i32;
486 21 : if (ArgFlags.isSExt())
487 : LocInfo = CCValAssign::SExt;
488 21 : else if (ArgFlags.isZExt())
489 : LocInfo = CCValAssign::ZExt;
490 : else
491 : LocInfo = CCValAssign::AExt;
492 : }
493 :
494 18626 : if (LocVT == MVT::v8i1) {
495 : LocVT = MVT::v8i16;
496 17 : if (ArgFlags.isSExt())
497 : LocInfo = CCValAssign::SExt;
498 17 : else if (ArgFlags.isZExt())
499 : LocInfo = CCValAssign::ZExt;
500 : else
501 : LocInfo = CCValAssign::AExt;
502 : }
503 :
504 18626 : if (LocVT == MVT::v16i1) {
505 : LocVT = MVT::v16i8;
506 30 : if (ArgFlags.isSExt())
507 : LocInfo = CCValAssign::SExt;
508 30 : else if (ArgFlags.isZExt())
509 : LocInfo = CCValAssign::ZExt;
510 : else
511 : LocInfo = CCValAssign::AExt;
512 : }
513 :
514 18626 : if (LocVT == MVT::v32i1) {
515 : LocVT = MVT::v32i8;
516 5 : if (ArgFlags.isSExt())
517 : LocInfo = CCValAssign::SExt;
518 5 : else if (ArgFlags.isZExt())
519 : LocInfo = CCValAssign::ZExt;
520 : else
521 : LocInfo = CCValAssign::AExt;
522 : }
523 :
524 18626 : if (LocVT == MVT::v64i1) {
525 : LocVT = MVT::v64i8;
526 1 : if (ArgFlags.isSExt())
527 : LocInfo = CCValAssign::SExt;
528 1 : else if (ArgFlags.isZExt())
529 : LocInfo = CCValAssign::ZExt;
530 : else
531 : LocInfo = CCValAssign::AExt;
532 : }
533 :
534 18626 : if (LocVT == MVT::x86mmx) {
535 0 : unsigned Offset6 = State.AllocateStack(8, 4);
536 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537 0 : return false;
538 : }
539 :
540 18626 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541 4358 : if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542 : return false;
543 : }
544 :
545 14268 : if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546 14262 : return false;
547 :
548 : return true; // CC didn't match.
549 : }
550 :
551 :
552 1164 : static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
553 : MVT LocVT, CCValAssign::LocInfo LocInfo,
554 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
555 :
556 1164 : if (ArgFlags.isByVal()) {
557 39 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558 39 : return false;
559 : }
560 :
561 1125 : if (LocVT == MVT::i1 ||
562 1049 : LocVT == MVT::i8 ||
563 2173 : LocVT == MVT::i16 ||
564 : LocVT == MVT::v1i1) {
565 : LocVT = MVT::i32;
566 77 : if (ArgFlags.isSExt())
567 : LocInfo = CCValAssign::SExt;
568 62 : else if (ArgFlags.isZExt())
569 : LocInfo = CCValAssign::ZExt;
570 : else
571 : LocInfo = CCValAssign::AExt;
572 : }
573 :
574 1125 : if (ArgFlags.isNest()) {
575 : if (unsigned Reg = State.AllocateReg(X86::EAX)) {
576 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577 0 : return false;
578 : }
579 : }
580 :
581 1125 : if (LocVT == MVT::i32) {
582 : static const MCPhysReg RegList1[] = {
583 : X86::ECX, X86::EDX
584 : };
585 1098 : if (unsigned Reg = State.AllocateReg(RegList1)) {
586 728 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587 728 : return false;
588 : }
589 : }
590 :
591 397 : if (!State.isVarArg()) {
592 397 : if (LocVT == MVT::f32 ||
593 : LocVT == MVT::f64) {
594 36 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
595 : static const MCPhysReg RegList2[] = {
596 : X86::XMM0, X86::XMM1, X86::XMM2
597 : };
598 8 : if (unsigned Reg = State.AllocateReg(RegList2)) {
599 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600 6 : return false;
601 : }
602 : }
603 : }
604 : }
605 :
606 391 : if (LocVT == MVT::f64) {
607 9 : unsigned Offset3 = State.AllocateStack(8, 8);
608 9 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609 9 : return false;
610 : }
611 :
612 382 : if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
613 382 : return false;
614 :
615 : return true; // CC didn't match.
616 : }
617 :
618 :
619 264 : static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
620 : MVT LocVT, CCValAssign::LocInfo LocInfo,
621 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
622 :
623 264 : if (LocVT == MVT::i1) {
624 : LocVT = MVT::i8;
625 0 : if (ArgFlags.isSExt())
626 : LocInfo = CCValAssign::SExt;
627 0 : else if (ArgFlags.isZExt())
628 : LocInfo = CCValAssign::ZExt;
629 : else
630 : LocInfo = CCValAssign::AExt;
631 : }
632 :
633 264 : if (ArgFlags.isNest()) {
634 : if (unsigned Reg = State.AllocateReg(X86::EAX)) {
635 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636 0 : return false;
637 : }
638 : }
639 :
640 264 : if (ArgFlags.isInReg()) {
641 197 : if (LocVT == MVT::i8) {
642 : static const MCPhysReg RegList1[] = {
643 : X86::CL, X86::DL
644 : };
645 4 : if (unsigned Reg = State.AllocateReg(RegList1)) {
646 4 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
647 4 : return false;
648 : }
649 : }
650 : }
651 :
652 260 : if (ArgFlags.isInReg()) {
653 193 : if (LocVT == MVT::i16) {
654 : static const MCPhysReg RegList2[] = {
655 : X86::CX, X86::DX
656 : };
657 0 : if (unsigned Reg = State.AllocateReg(RegList2)) {
658 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
659 0 : return false;
660 : }
661 : }
662 : }
663 :
664 260 : if (ArgFlags.isInReg()) {
665 193 : if (LocVT == MVT::i32) {
666 : static const MCPhysReg RegList3[] = {
667 : X86::ECX, X86::EDX
668 : };
669 178 : if (unsigned Reg = State.AllocateReg(RegList3)) {
670 172 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
671 172 : return false;
672 : }
673 : }
674 : }
675 :
676 88 : if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
677 82 : return false;
678 :
679 : return true; // CC didn't match.
680 : }
681 :
682 :
683 20 : static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
684 : MVT LocVT, CCValAssign::LocInfo LocInfo,
685 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
686 :
687 20 : if (LocVT == MVT::i8 ||
688 : LocVT == MVT::i16) {
689 : LocVT = MVT::i32;
690 0 : if (ArgFlags.isSExt())
691 : LocInfo = CCValAssign::SExt;
692 0 : else if (ArgFlags.isZExt())
693 : LocInfo = CCValAssign::ZExt;
694 : else
695 : LocInfo = CCValAssign::AExt;
696 : }
697 :
698 20 : if (LocVT == MVT::i32) {
699 : static const MCPhysReg RegList1[] = {
700 : X86::EBX, X86::EBP, X86::EDI, X86::ESI
701 : };
702 20 : if (unsigned Reg = State.AllocateReg(RegList1)) {
703 20 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
704 20 : return false;
705 : }
706 : }
707 :
708 : return true; // CC didn't match.
709 : }
710 :
711 :
712 42 : static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
713 : MVT LocVT, CCValAssign::LocInfo LocInfo,
714 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
715 :
716 42 : if (LocVT == MVT::i8 ||
717 : LocVT == MVT::i16) {
718 : LocVT = MVT::i32;
719 0 : if (ArgFlags.isSExt())
720 : LocInfo = CCValAssign::SExt;
721 0 : else if (ArgFlags.isZExt())
722 : LocInfo = CCValAssign::ZExt;
723 : else
724 : LocInfo = CCValAssign::AExt;
725 : }
726 :
727 42 : if (LocVT == MVT::i32) {
728 : static const MCPhysReg RegList1[] = {
729 : X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
730 : };
731 42 : if (unsigned Reg = State.AllocateReg(RegList1)) {
732 41 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
733 41 : return false;
734 : }
735 : }
736 :
737 1 : if (LocVT == MVT::i32 ||
738 : LocVT == MVT::f32) {
739 1 : unsigned Offset2 = State.AllocateStack(4, 4);
740 1 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
741 1 : return false;
742 : }
743 :
744 : return true; // CC didn't match.
745 : }
746 :
747 :
748 0 : static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
749 : MVT LocVT, CCValAssign::LocInfo LocInfo,
750 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
751 :
752 0 : unsigned Offset1 = State.AllocateStack(4, 4);
753 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754 : return false;
755 :
756 : return true; // CC didn't match.
757 : }
758 :
759 :
760 126 : static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
761 : MVT LocVT, CCValAssign::LocInfo LocInfo,
762 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
763 :
764 126 : if (ArgFlags.isByVal()) {
765 1 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
766 1 : return false;
767 : }
768 :
769 125 : if (LocVT == MVT::i1 ||
770 113 : LocVT == MVT::i8 ||
771 231 : LocVT == MVT::i16 ||
772 : LocVT == MVT::v1i1) {
773 19 : LocVT = MVT::i32;
774 19 : if (ArgFlags.isSExt())
775 0 : LocInfo = CCValAssign::SExt;
776 19 : else if (ArgFlags.isZExt())
777 3 : LocInfo = CCValAssign::ZExt;
778 : else
779 16 : LocInfo = CCValAssign::AExt;
780 : }
781 :
782 125 : if (!State.isVarArg()) {
783 124 : if (LocVT == MVT::i32) {
784 123 : if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
785 : return false;
786 : }
787 : }
788 :
789 5 : if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
790 5 : return false;
791 :
792 : return true; // CC didn't match.
793 : }
794 :
795 :
796 200 : static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
797 : MVT LocVT, CCValAssign::LocInfo LocInfo,
798 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
799 :
800 200 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
801 0 : if (ArgFlags.isByVal()) {
802 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
803 0 : return false;
804 : }
805 : }
806 :
807 200 : if (ArgFlags.isByVal()) {
808 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
809 0 : return false;
810 : }
811 :
812 200 : if (LocVT == MVT::i1 ||
813 189 : LocVT == MVT::i8 ||
814 385 : LocVT == MVT::i16 ||
815 : LocVT == MVT::v1i1) {
816 15 : LocVT = MVT::i32;
817 15 : if (ArgFlags.isSExt())
818 2 : LocInfo = CCValAssign::SExt;
819 13 : else if (ArgFlags.isZExt())
820 0 : LocInfo = CCValAssign::ZExt;
821 : else
822 13 : LocInfo = CCValAssign::AExt;
823 : }
824 :
825 194 : if (LocVT == MVT::v8i1 ||
826 388 : LocVT == MVT::v16i1 ||
827 : LocVT == MVT::v32i1) {
828 18 : LocVT = MVT::i32;
829 18 : if (ArgFlags.isSExt())
830 0 : LocInfo = CCValAssign::SExt;
831 18 : else if (ArgFlags.isZExt())
832 0 : LocInfo = CCValAssign::ZExt;
833 : else
834 18 : LocInfo = CCValAssign::AExt;
835 : }
836 :
837 200 : if (LocVT == MVT::i32) {
838 : static const MCPhysReg RegList1[] = {
839 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
840 : };
841 86 : if (unsigned Reg = State.AllocateReg(RegList1)) {
842 142 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
843 71 : return false;
844 : }
845 : }
846 :
847 129 : if (LocVT == MVT::i64) {
848 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
849 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
850 0 : return false;
851 : }
852 : }
853 :
854 129 : if (LocVT == MVT::v64i1) {
855 26 : LocVT = MVT::i64;
856 26 : if (ArgFlags.isSExt())
857 0 : LocInfo = CCValAssign::SExt;
858 26 : else if (ArgFlags.isZExt())
859 0 : LocInfo = CCValAssign::ZExt;
860 : else
861 26 : LocInfo = CCValAssign::AExt;
862 : }
863 :
864 129 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
865 0 : if (LocVT == MVT::i64) {
866 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
867 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868 0 : return false;
869 : }
870 : }
871 : }
872 :
873 129 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
874 129 : if (LocVT == MVT::i64) {
875 26 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
876 : return false;
877 : }
878 : }
879 :
880 120 : if (LocVT == MVT::f32 ||
881 240 : LocVT == MVT::f64 ||
882 : LocVT == MVT::f128) {
883 20 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
884 : static const MCPhysReg RegList2[] = {
885 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
886 : };
887 10 : if (unsigned Reg = State.AllocateReg(RegList2)) {
888 20 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
889 10 : return false;
890 : }
891 : }
892 : }
893 :
894 115 : if (LocVT == MVT::f80) {
895 : if (unsigned Reg = State.AllocateReg(X86::FP0)) {
896 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
897 3 : return false;
898 : }
899 : }
900 :
901 112 : if (LocVT == MVT::v16i8 ||
902 112 : LocVT == MVT::v8i16 ||
903 107 : LocVT == MVT::v4i32 ||
904 107 : LocVT == MVT::v2i64 ||
905 183 : LocVT == MVT::v4f32 ||
906 : LocVT == MVT::v2f64) {
907 82 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
908 : static const MCPhysReg RegList3[] = {
909 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
910 : };
911 41 : if (unsigned Reg = State.AllocateReg(RegList3)) {
912 42 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
913 21 : return false;
914 : }
915 : }
916 : }
917 :
918 91 : if (LocVT == MVT::v32i8 ||
919 91 : LocVT == MVT::v16i16 ||
920 86 : LocVT == MVT::v8i32 ||
921 86 : LocVT == MVT::v4i64 ||
922 177 : LocVT == MVT::v8f32 ||
923 : LocVT == MVT::v4f64) {
924 10 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
925 : static const MCPhysReg RegList4[] = {
926 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
927 : };
928 5 : if (unsigned Reg = State.AllocateReg(RegList4)) {
929 10 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
930 5 : return false;
931 : }
932 : }
933 : }
934 :
935 86 : if (LocVT == MVT::v64i8 ||
936 86 : LocVT == MVT::v32i16 ||
937 81 : LocVT == MVT::v16i32 ||
938 81 : LocVT == MVT::v8i64 ||
939 143 : LocVT == MVT::v16f32 ||
940 : LocVT == MVT::v8f64) {
941 58 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
942 : static const MCPhysReg RegList5[] = {
943 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
944 : };
945 29 : if (unsigned Reg = State.AllocateReg(RegList5)) {
946 38 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
947 19 : return false;
948 : }
949 : }
950 : }
951 :
952 67 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
953 0 : if (LocVT == MVT::i32 ||
954 0 : LocVT == MVT::i64 ||
955 0 : LocVT == MVT::f32 ||
956 : LocVT == MVT::f64) {
957 0 : unsigned Offset6 = State.AllocateStack(8, 8);
958 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
959 0 : return false;
960 : }
961 : }
962 :
963 67 : if (LocVT == MVT::i32 ||
964 : LocVT == MVT::f32) {
965 15 : unsigned Offset7 = State.AllocateStack(4, 4);
966 30 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
967 15 : return false;
968 : }
969 :
970 52 : if (LocVT == MVT::i64 ||
971 : LocVT == MVT::f64) {
972 22 : unsigned Offset8 = State.AllocateStack(8, 4);
973 44 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
974 22 : return false;
975 : }
976 :
977 30 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
978 0 : if (LocVT == MVT::x86mmx) {
979 0 : unsigned Offset9 = State.AllocateStack(8, 8);
980 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
981 0 : return false;
982 : }
983 : }
984 :
985 30 : if (LocVT == MVT::x86mmx) {
986 0 : unsigned Offset10 = State.AllocateStack(8, 4);
987 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
988 0 : return false;
989 : }
990 :
991 30 : if (LocVT == MVT::f80 ||
992 : LocVT == MVT::f128) {
993 0 : unsigned Offset11 = State.AllocateStack(
994 0 : State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
995 0 : State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
996 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
997 0 : return false;
998 : }
999 :
1000 30 : if (LocVT == MVT::v16i8 ||
1001 30 : LocVT == MVT::v8i16 ||
1002 30 : LocVT == MVT::v4i32 ||
1003 30 : LocVT == MVT::v2i64 ||
1004 40 : LocVT == MVT::v4f32 ||
1005 : LocVT == MVT::v2f64) {
1006 20 : unsigned Offset12 = State.AllocateStack(16, 16);
1007 40 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
1008 20 : return false;
1009 : }
1010 :
1011 10 : if (LocVT == MVT::v32i8 ||
1012 10 : LocVT == MVT::v16i16 ||
1013 10 : LocVT == MVT::v8i32 ||
1014 10 : LocVT == MVT::v4i64 ||
1015 20 : LocVT == MVT::v8f32 ||
1016 : LocVT == MVT::v4f64) {
1017 0 : unsigned Offset13 = State.AllocateStack(32, 32);
1018 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1019 0 : return false;
1020 : }
1021 :
1022 10 : if (LocVT == MVT::v16i32 ||
1023 10 : LocVT == MVT::v8i64 ||
1024 10 : LocVT == MVT::v16f32 ||
1025 : LocVT == MVT::v8f64) {
1026 10 : unsigned Offset14 = State.AllocateStack(64, 64);
1027 20 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1028 10 : return false;
1029 : }
1030 :
1031 : return true; // CC didn't match.
1032 : }
1033 :
1034 :
1035 448 : static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1036 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1037 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038 :
1039 448 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1040 40 : if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1041 : return false;
1042 : }
1043 :
1044 408 : if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1045 408 : return false;
1046 :
1047 : return true; // CC didn't match.
1048 : }
1049 :
1050 :
1051 424 : static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1052 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1053 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054 :
1055 424 : if (LocVT == MVT::i32) {
1056 : if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1057 232 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1058 232 : return false;
1059 : }
1060 : }
1061 :
1062 192 : if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1063 192 : return false;
1064 :
1065 : return true; // CC didn't match.
1066 : }
1067 :
1068 :
1069 40 : static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1070 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1071 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1072 :
1073 40 : if (LocVT == MVT::i1 ||
1074 40 : LocVT == MVT::i8 ||
1075 80 : LocVT == MVT::i16 ||
1076 : LocVT == MVT::v1i1) {
1077 : LocVT = MVT::i32;
1078 0 : if (ArgFlags.isSExt())
1079 : LocInfo = CCValAssign::SExt;
1080 0 : else if (ArgFlags.isZExt())
1081 : LocInfo = CCValAssign::ZExt;
1082 : else
1083 : LocInfo = CCValAssign::AExt;
1084 : }
1085 :
1086 40 : if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1087 40 : return false;
1088 :
1089 : return true; // CC didn't match.
1090 : }
1091 :
1092 :
1093 408 : static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1094 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1095 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1096 :
1097 408 : if (LocVT == MVT::i1 ||
1098 407 : LocVT == MVT::i8 ||
1099 815 : LocVT == MVT::i16 ||
1100 : LocVT == MVT::v1i1) {
1101 : LocVT = MVT::i32;
1102 1 : if (ArgFlags.isSExt())
1103 : LocInfo = CCValAssign::SExt;
1104 1 : else if (ArgFlags.isZExt())
1105 : LocInfo = CCValAssign::ZExt;
1106 : else
1107 : LocInfo = CCValAssign::AExt;
1108 : }
1109 :
1110 408 : if (ArgFlags.isSRet()) {
1111 24 : unsigned Offset1 = State.AllocateStack(4, 4);
1112 24 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1113 24 : return false;
1114 : }
1115 :
1116 384 : if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1117 384 : return false;
1118 :
1119 : return true; // CC didn't match.
1120 : }
1121 :
1122 :
1123 0 : static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1124 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1125 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126 :
1127 0 : if (LocVT == MVT::v16i8 ||
1128 0 : LocVT == MVT::v8i16 ||
1129 0 : LocVT == MVT::v4i32 ||
1130 0 : LocVT == MVT::v2i64 ||
1131 0 : LocVT == MVT::v4f32 ||
1132 : LocVT == MVT::v2f64) {
1133 0 : unsigned Offset1 = State.AllocateStack(16, 16);
1134 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135 0 : return false;
1136 : }
1137 :
1138 0 : if (LocVT == MVT::v32i8 ||
1139 0 : LocVT == MVT::v16i16 ||
1140 0 : LocVT == MVT::v8i32 ||
1141 0 : LocVT == MVT::v4i64 ||
1142 0 : LocVT == MVT::v8f32 ||
1143 : LocVT == MVT::v4f64) {
1144 0 : unsigned Offset2 = State.AllocateStack(32, 32);
1145 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146 0 : return false;
1147 : }
1148 :
1149 0 : if (LocVT == MVT::v64i8 ||
1150 0 : LocVT == MVT::v32i16 ||
1151 0 : LocVT == MVT::v16i32 ||
1152 0 : LocVT == MVT::v8i64 ||
1153 0 : LocVT == MVT::v16f32 ||
1154 : LocVT == MVT::v8f64) {
1155 0 : unsigned Offset3 = State.AllocateStack(64, 64);
1156 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157 0 : return false;
1158 : }
1159 :
1160 : return true; // CC didn't match.
1161 : }
1162 :
1163 :
1164 0 : static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1165 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1166 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1167 :
1168 0 : if (!State.isVarArg()) {
1169 0 : if (LocVT == MVT::v16i8 ||
1170 0 : LocVT == MVT::v8i16 ||
1171 0 : LocVT == MVT::v4i32 ||
1172 0 : LocVT == MVT::v2i64 ||
1173 0 : LocVT == MVT::v4f32 ||
1174 : LocVT == MVT::v2f64) {
1175 : static const MCPhysReg RegList1[] = {
1176 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1177 : };
1178 0 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1179 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1180 0 : return false;
1181 : }
1182 : }
1183 : }
1184 :
1185 0 : if (!State.isVarArg()) {
1186 0 : if (LocVT == MVT::v32i8 ||
1187 0 : LocVT == MVT::v16i16 ||
1188 0 : LocVT == MVT::v8i32 ||
1189 0 : LocVT == MVT::v4i64 ||
1190 0 : LocVT == MVT::v8f32 ||
1191 : LocVT == MVT::v4f64) {
1192 0 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1193 : static const MCPhysReg RegList2[] = {
1194 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1195 : };
1196 0 : if (unsigned Reg = State.AllocateReg(RegList2)) {
1197 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1198 0 : return false;
1199 : }
1200 : }
1201 : }
1202 : }
1203 :
1204 0 : if (!State.isVarArg()) {
1205 0 : if (LocVT == MVT::v64i8 ||
1206 0 : LocVT == MVT::v32i16 ||
1207 0 : LocVT == MVT::v16i32 ||
1208 0 : LocVT == MVT::v8i64 ||
1209 0 : LocVT == MVT::v16f32 ||
1210 : LocVT == MVT::v8f64) {
1211 : static const MCPhysReg RegList3[] = {
1212 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1213 : };
1214 0 : if (unsigned Reg = State.AllocateReg(RegList3)) {
1215 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1216 0 : return false;
1217 : }
1218 : }
1219 : }
1220 :
1221 0 : if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1222 0 : return false;
1223 :
1224 : return true; // CC didn't match.
1225 : }
1226 :
1227 :
1228 0 : static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1229 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1230 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1231 :
1232 0 : if (!State.isVarArg()) {
1233 0 : if (LocVT == MVT::v16i8 ||
1234 0 : LocVT == MVT::v8i16 ||
1235 0 : LocVT == MVT::v4i32 ||
1236 0 : LocVT == MVT::v2i64 ||
1237 0 : LocVT == MVT::v4f32 ||
1238 : LocVT == MVT::v2f64) {
1239 : static const MCPhysReg RegList1[] = {
1240 : X86::XMM0, X86::XMM1, X86::XMM2
1241 : };
1242 0 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1243 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1244 0 : return false;
1245 : }
1246 : }
1247 : }
1248 :
1249 0 : if (!State.isVarArg()) {
1250 0 : if (LocVT == MVT::v32i8 ||
1251 0 : LocVT == MVT::v16i16 ||
1252 0 : LocVT == MVT::v8i32 ||
1253 0 : LocVT == MVT::v4i64 ||
1254 0 : LocVT == MVT::v8f32 ||
1255 : LocVT == MVT::v4f64) {
1256 0 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1257 : static const MCPhysReg RegList2[] = {
1258 : X86::YMM0, X86::YMM1, X86::YMM2
1259 : };
1260 0 : if (unsigned Reg = State.AllocateReg(RegList2)) {
1261 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1262 0 : return false;
1263 : }
1264 : }
1265 : }
1266 : }
1267 :
1268 0 : if (!State.isVarArg()) {
1269 0 : if (LocVT == MVT::v64i8 ||
1270 0 : LocVT == MVT::v32i16 ||
1271 0 : LocVT == MVT::v16i32 ||
1272 0 : LocVT == MVT::v8i64 ||
1273 0 : LocVT == MVT::v16f32 ||
1274 : LocVT == MVT::v8f64) {
1275 : static const MCPhysReg RegList3[] = {
1276 : X86::ZMM0, X86::ZMM1, X86::ZMM2
1277 : };
1278 0 : if (unsigned Reg = State.AllocateReg(RegList3)) {
1279 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1280 0 : return false;
1281 : }
1282 : }
1283 : }
1284 :
1285 0 : if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1286 0 : return false;
1287 :
1288 : return true; // CC didn't match.
1289 : }
1290 :
1291 :
1292 4239117 : static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1293 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1294 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295 :
1296 4239117 : if (State.getCallingConv() == CallingConv::GHC) {
1297 62 : if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298 : return false;
1299 : }
1300 :
1301 4239055 : if (State.getCallingConv() == CallingConv::HiPE) {
1302 42 : if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303 : return false;
1304 : }
1305 :
1306 4239013 : if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307 69 : if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308 : return false;
1309 : }
1310 :
1311 4238944 : if (State.getCallingConv() == CallingConv::AnyReg) {
1312 : if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313 : return false;
1314 : }
1315 :
1316 4238944 : if (State.getCallingConv() == CallingConv::Win64) {
1317 55 : if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318 : return false;
1319 : }
1320 :
1321 4238889 : if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322 22 : if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323 : return false;
1324 : }
1325 :
1326 4238867 : if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327 152 : if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328 : return false;
1329 : }
1330 :
1331 4238715 : if (State.getCallingConv() == CallingConv::HHVM) {
1332 112 : if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333 : return false;
1334 : }
1335 :
1336 4238603 : if (State.getCallingConv() == CallingConv::HHVM_C) {
1337 25 : if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338 : return false;
1339 : }
1340 :
1341 4238578 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342 380 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343 195 : if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344 : return false;
1345 : }
1346 : }
1347 :
1348 4238383 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349 185 : if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350 : return false;
1351 : }
1352 :
1353 4238198 : if (State.getCallingConv() == CallingConv::X86_INTR) {
1354 20 : if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355 : return false;
1356 : }
1357 :
1358 4238178 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359 2861 : if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360 : return false;
1361 : }
1362 :
1363 4235326 : if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364 4233471 : return false;
1365 :
1366 : return true; // CC didn't match.
1367 : }
1368 :
1369 :
1370 0 : static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1371 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1372 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1373 :
1374 : if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1375 : return false;
1376 :
1377 : return true; // CC didn't match.
1378 : }
1379 :
1380 :
1381 4235372 : static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1382 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1383 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384 :
1385 4235372 : if (ArgFlags.isByVal()) {
1386 3185 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387 3185 : return false;
1388 : }
1389 :
1390 4232181 : if (LocVT == MVT::i1 ||
1391 4156761 : LocVT == MVT::i8 ||
1392 8383837 : LocVT == MVT::i16 ||
1393 : LocVT == MVT::v1i1) {
1394 : LocVT = MVT::i32;
1395 80551 : if (ArgFlags.isSExt())
1396 : LocInfo = CCValAssign::SExt;
1397 59125 : else if (ArgFlags.isZExt())
1398 : LocInfo = CCValAssign::ZExt;
1399 : else
1400 : LocInfo = CCValAssign::AExt;
1401 : }
1402 :
1403 4232187 : if (ArgFlags.isNest()) {
1404 25 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405 : if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407 2 : return false;
1408 : }
1409 : }
1410 : }
1411 :
1412 4232185 : if (ArgFlags.isNest()) {
1413 : if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414 23 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415 23 : return false;
1416 : }
1417 : }
1418 :
1419 4232162 : if (ArgFlags.isSwiftSelf()) {
1420 40 : if (LocVT == MVT::i64) {
1421 : if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422 40 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423 40 : return false;
1424 : }
1425 : }
1426 : }
1427 :
1428 4232122 : if (ArgFlags.isSwiftError()) {
1429 74 : if (LocVT == MVT::i64) {
1430 : if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431 74 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432 74 : return false;
1433 : }
1434 : }
1435 : }
1436 :
1437 4232048 : if (State.getCallingConv() == CallingConv::Swift) {
1438 134 : if (ArgFlags.isSRet()) {
1439 6 : if (LocVT == MVT::i64) {
1440 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442 6 : return false;
1443 : }
1444 : }
1445 : }
1446 : }
1447 :
1448 4232042 : if (LocVT == MVT::i32) {
1449 : static const MCPhysReg RegList1[] = {
1450 : X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451 : };
1452 376457 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1453 344045 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454 344045 : return false;
1455 : }
1456 : }
1457 :
1458 3887997 : if (LocVT == MVT::i64) {
1459 : static const MCPhysReg RegList2[] = {
1460 : X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461 : };
1462 3733786 : if (unsigned Reg = State.AllocateReg(RegList2)) {
1463 3678889 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464 3678889 : return false;
1465 : }
1466 : }
1467 :
1468 209108 : if (LocVT == MVT::x86mmx) {
1469 1855 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470 24 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471 : LocVT = MVT::v2i64;
1472 12 : if (ArgFlags.isSExt())
1473 : LocInfo = CCValAssign::SExt;
1474 12 : else if (ArgFlags.isZExt())
1475 : LocInfo = CCValAssign::ZExt;
1476 : else
1477 : LocInfo = CCValAssign::AExt;
1478 : }
1479 : }
1480 : }
1481 :
1482 209108 : if (LocVT == MVT::v2i1) {
1483 : LocVT = MVT::v2i64;
1484 121 : if (ArgFlags.isSExt())
1485 : LocInfo = CCValAssign::SExt;
1486 121 : else if (ArgFlags.isZExt())
1487 : LocInfo = CCValAssign::ZExt;
1488 : else
1489 : LocInfo = CCValAssign::AExt;
1490 : }
1491 :
1492 209108 : if (LocVT == MVT::v4i1) {
1493 : LocVT = MVT::v4i32;
1494 149 : if (ArgFlags.isSExt())
1495 : LocInfo = CCValAssign::SExt;
1496 149 : else if (ArgFlags.isZExt())
1497 : LocInfo = CCValAssign::ZExt;
1498 : else
1499 : LocInfo = CCValAssign::AExt;
1500 : }
1501 :
1502 209108 : if (LocVT == MVT::v8i1) {
1503 : LocVT = MVT::v8i16;
1504 152 : if (ArgFlags.isSExt())
1505 : LocInfo = CCValAssign::SExt;
1506 152 : else if (ArgFlags.isZExt())
1507 : LocInfo = CCValAssign::ZExt;
1508 : else
1509 : LocInfo = CCValAssign::AExt;
1510 : }
1511 :
1512 209108 : if (LocVT == MVT::v16i1) {
1513 : LocVT = MVT::v16i8;
1514 188 : if (ArgFlags.isSExt())
1515 : LocInfo = CCValAssign::SExt;
1516 188 : else if (ArgFlags.isZExt())
1517 : LocInfo = CCValAssign::ZExt;
1518 : else
1519 : LocInfo = CCValAssign::AExt;
1520 : }
1521 :
1522 209108 : if (LocVT == MVT::v32i1) {
1523 : LocVT = MVT::v32i8;
1524 36 : if (ArgFlags.isSExt())
1525 : LocInfo = CCValAssign::SExt;
1526 36 : else if (ArgFlags.isZExt())
1527 : LocInfo = CCValAssign::ZExt;
1528 : else
1529 : LocInfo = CCValAssign::AExt;
1530 : }
1531 :
1532 209108 : if (LocVT == MVT::v64i1) {
1533 : LocVT = MVT::v64i8;
1534 9 : if (ArgFlags.isSExt())
1535 : LocInfo = CCValAssign::SExt;
1536 9 : else if (ArgFlags.isZExt())
1537 : LocInfo = CCValAssign::ZExt;
1538 : else
1539 : LocInfo = CCValAssign::AExt;
1540 : }
1541 :
1542 204061 : if (LocVT == MVT::f32 ||
1543 195999 : LocVT == MVT::f64 ||
1544 195463 : LocVT == MVT::f128 ||
1545 188182 : LocVT == MVT::v16i8 ||
1546 179159 : LocVT == MVT::v8i16 ||
1547 168426 : LocVT == MVT::v4i32 ||
1548 157293 : LocVT == MVT::v2i64 ||
1549 355560 : LocVT == MVT::v4f32 ||
1550 : LocVT == MVT::v2f64) {
1551 140252 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552 : static const MCPhysReg RegList3[] = {
1553 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554 : };
1555 70120 : if (unsigned Reg = State.AllocateReg(RegList3)) {
1556 68229 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557 68229 : return false;
1558 : }
1559 : }
1560 : }
1561 :
1562 140879 : if (!State.isVarArg()) {
1563 135063 : if (LocVT == MVT::v32i8 ||
1564 129427 : LocVT == MVT::v16i16 ||
1565 124104 : LocVT == MVT::v8i32 ||
1566 118473 : LocVT == MVT::v4i64 ||
1567 252511 : LocVT == MVT::v8f32 ||
1568 : LocVT == MVT::v4f64) {
1569 63432 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570 : static const MCPhysReg RegList4[] = {
1571 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572 : };
1573 31716 : if (unsigned Reg = State.AllocateReg(RegList4)) {
1574 31588 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575 31588 : return false;
1576 : }
1577 : }
1578 : }
1579 : }
1580 :
1581 109291 : if (!State.isVarArg()) {
1582 107276 : if (LocVT == MVT::v64i8 ||
1583 106077 : LocVT == MVT::v32i16 ||
1584 103195 : LocVT == MVT::v16i32 ||
1585 99380 : LocVT == MVT::v8i64 ||
1586 204360 : LocVT == MVT::v16f32 ||
1587 : LocVT == MVT::v8f64) {
1588 29218 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589 : static const MCPhysReg RegList5[] = {
1590 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591 : };
1592 14609 : if (unsigned Reg = State.AllocateReg(RegList5)) {
1593 14597 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594 14597 : return false;
1595 : }
1596 : }
1597 : }
1598 : }
1599 :
1600 62282 : if (LocVT == MVT::i32 ||
1601 7385 : LocVT == MVT::i64 ||
1602 102025 : LocVT == MVT::f32 ||
1603 : LocVT == MVT::f64) {
1604 87365 : unsigned Offset6 = State.AllocateStack(8, 8);
1605 87365 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606 87365 : return false;
1607 : }
1608 :
1609 7329 : if (LocVT == MVT::f80 ||
1610 : LocVT == MVT::f128) {
1611 7248 : unsigned Offset7 = State.AllocateStack(
1612 3624 : State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
1613 7248 : State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614 3624 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615 3624 : return false;
1616 : }
1617 :
1618 3603 : if (LocVT == MVT::v16i8 ||
1619 3539 : LocVT == MVT::v8i16 ||
1620 3467 : LocVT == MVT::v4i32 ||
1621 2131 : LocVT == MVT::v2i64 ||
1622 5789 : LocVT == MVT::v4f32 ||
1623 : LocVT == MVT::v2f64) {
1624 1721 : unsigned Offset8 = State.AllocateStack(16, 16);
1625 1721 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626 1721 : return false;
1627 : }
1628 :
1629 1912 : if (LocVT == MVT::v32i8 ||
1630 1912 : LocVT == MVT::v16i16 ||
1631 1912 : LocVT == MVT::v8i32 ||
1632 1876 : LocVT == MVT::v4i64 ||
1633 3855 : LocVT == MVT::v8f32 ||
1634 : LocVT == MVT::v4f64) {
1635 129 : unsigned Offset9 = State.AllocateStack(32, 32);
1636 129 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637 129 : return false;
1638 : }
1639 :
1640 1855 : if (LocVT == MVT::v16i32 ||
1641 1855 : LocVT == MVT::v8i64 ||
1642 3710 : LocVT == MVT::v16f32 ||
1643 : LocVT == MVT::v8f64) {
1644 0 : unsigned Offset10 = State.AllocateStack(64, 64);
1645 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646 0 : return false;
1647 : }
1648 :
1649 : return true; // CC didn't match.
1650 : }
1651 :
1652 :
1653 62 : static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1654 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1655 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1656 :
1657 62 : if (LocVT == MVT::i8 ||
1658 124 : LocVT == MVT::i16 ||
1659 : LocVT == MVT::i32) {
1660 : LocVT = MVT::i64;
1661 0 : if (ArgFlags.isSExt())
1662 : LocInfo = CCValAssign::SExt;
1663 0 : else if (ArgFlags.isZExt())
1664 : LocInfo = CCValAssign::ZExt;
1665 : else
1666 : LocInfo = CCValAssign::AExt;
1667 : }
1668 :
1669 62 : if (LocVT == MVT::i64) {
1670 : static const MCPhysReg RegList1[] = {
1671 : X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1672 : };
1673 56 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1674 56 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1675 56 : return false;
1676 : }
1677 : }
1678 :
1679 2 : if (LocVT == MVT::f32 ||
1680 0 : LocVT == MVT::f64 ||
1681 0 : LocVT == MVT::v16i8 ||
1682 0 : LocVT == MVT::v8i16 ||
1683 0 : LocVT == MVT::v4i32 ||
1684 0 : LocVT == MVT::v2i64 ||
1685 6 : LocVT == MVT::v4f32 ||
1686 : LocVT == MVT::v2f64) {
1687 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1688 : static const MCPhysReg RegList2[] = {
1689 : X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1690 : };
1691 6 : if (unsigned Reg = State.AllocateReg(RegList2)) {
1692 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1693 6 : return false;
1694 : }
1695 : }
1696 : }
1697 :
1698 0 : if (LocVT == MVT::v32i8 ||
1699 0 : LocVT == MVT::v16i16 ||
1700 0 : LocVT == MVT::v8i32 ||
1701 0 : LocVT == MVT::v4i64 ||
1702 0 : LocVT == MVT::v8f32 ||
1703 : LocVT == MVT::v4f64) {
1704 0 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1705 : static const MCPhysReg RegList3[] = {
1706 : X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1707 : };
1708 0 : if (unsigned Reg = State.AllocateReg(RegList3)) {
1709 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1710 0 : return false;
1711 : }
1712 : }
1713 : }
1714 :
1715 0 : if (LocVT == MVT::v64i8 ||
1716 0 : LocVT == MVT::v32i16 ||
1717 0 : LocVT == MVT::v16i32 ||
1718 0 : LocVT == MVT::v8i64 ||
1719 0 : LocVT == MVT::v16f32 ||
1720 : LocVT == MVT::v8f64) {
1721 0 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1722 : static const MCPhysReg RegList4[] = {
1723 : X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1724 : };
1725 0 : if (unsigned Reg = State.AllocateReg(RegList4)) {
1726 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1727 0 : return false;
1728 : }
1729 : }
1730 : }
1731 :
1732 : return true; // CC didn't match.
1733 : }
1734 :
1735 :
1736 0 : static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1737 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1738 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1739 :
1740 0 : if (LocVT == MVT::i64) {
1741 : static const MCPhysReg RegList1[] = {
1742 : X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1743 : };
1744 0 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1745 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1746 0 : return false;
1747 : }
1748 : }
1749 :
1750 : return true; // CC didn't match.
1751 : }
1752 :
1753 :
1754 25 : static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1755 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1756 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1757 :
1758 25 : if (LocVT == MVT::i64) {
1759 : if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1760 5 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1761 5 : return false;
1762 : }
1763 : }
1764 :
1765 20 : if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1766 20 : return false;
1767 :
1768 : return true; // CC didn't match.
1769 : }
1770 :
1771 :
1772 42 : static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1773 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1774 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1775 :
1776 42 : if (LocVT == MVT::i8 ||
1777 84 : LocVT == MVT::i16 ||
1778 : LocVT == MVT::i32) {
1779 : LocVT = MVT::i64;
1780 6 : if (ArgFlags.isSExt())
1781 : LocInfo = CCValAssign::SExt;
1782 6 : else if (ArgFlags.isZExt())
1783 : LocInfo = CCValAssign::ZExt;
1784 : else
1785 : LocInfo = CCValAssign::AExt;
1786 : }
1787 :
1788 42 : if (LocVT == MVT::i64) {
1789 : static const MCPhysReg RegList1[] = {
1790 : X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1791 : };
1792 42 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1793 41 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1794 41 : return false;
1795 : }
1796 : }
1797 :
1798 1 : if (LocVT == MVT::i32 ||
1799 0 : LocVT == MVT::i64 ||
1800 1 : LocVT == MVT::f32 ||
1801 : LocVT == MVT::f64) {
1802 1 : unsigned Offset2 = State.AllocateStack(8, 8);
1803 1 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1804 1 : return false;
1805 : }
1806 :
1807 : return true; // CC didn't match.
1808 : }
1809 :
1810 :
1811 0 : static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
1812 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1813 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1814 :
1815 0 : unsigned Offset1 = State.AllocateStack(8, 8);
1816 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1817 : return false;
1818 :
1819 : return true; // CC didn't match.
1820 : }
1821 :
1822 :
1823 69 : static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1824 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1825 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1826 :
1827 69 : if (LocVT == MVT::i8 ||
1828 : LocVT == MVT::i16) {
1829 : LocVT = MVT::i32;
1830 0 : if (ArgFlags.isSExt())
1831 : LocInfo = CCValAssign::SExt;
1832 0 : else if (ArgFlags.isZExt())
1833 : LocInfo = CCValAssign::ZExt;
1834 : else
1835 : LocInfo = CCValAssign::AExt;
1836 : }
1837 :
1838 69 : if (LocVT == MVT::i32) {
1839 : if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1840 4 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1841 4 : return false;
1842 : }
1843 : }
1844 :
1845 65 : if (LocVT == MVT::i64) {
1846 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1847 9 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1848 9 : return false;
1849 : }
1850 : }
1851 :
1852 56 : if (LocVT == MVT::i32 ||
1853 : LocVT == MVT::f32) {
1854 22 : unsigned Offset1 = State.AllocateStack(4, 4);
1855 22 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1856 22 : return false;
1857 : }
1858 :
1859 34 : if (LocVT == MVT::i64 ||
1860 : LocVT == MVT::f64) {
1861 34 : unsigned Offset2 = State.AllocateStack(8, 8);
1862 34 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1863 34 : return false;
1864 : }
1865 :
1866 : return true; // CC didn't match.
1867 : }
1868 :
1869 :
1870 185 : static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
1871 : MVT LocVT, CCValAssign::LocInfo LocInfo,
1872 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
1873 :
1874 185 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1875 185 : if (ArgFlags.isByVal()) {
1876 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1877 0 : return false;
1878 : }
1879 : }
1880 :
1881 185 : if (ArgFlags.isByVal()) {
1882 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
1883 0 : return false;
1884 : }
1885 :
1886 185 : if (LocVT == MVT::i1 ||
1887 174 : LocVT == MVT::i8 ||
1888 355 : LocVT == MVT::i16 ||
1889 : LocVT == MVT::v1i1) {
1890 15 : LocVT = MVT::i32;
1891 15 : if (ArgFlags.isSExt())
1892 2 : LocInfo = CCValAssign::SExt;
1893 13 : else if (ArgFlags.isZExt())
1894 0 : LocInfo = CCValAssign::ZExt;
1895 : else
1896 13 : LocInfo = CCValAssign::AExt;
1897 : }
1898 :
1899 179 : if (LocVT == MVT::v8i1 ||
1900 358 : LocVT == MVT::v16i1 ||
1901 : LocVT == MVT::v32i1) {
1902 18 : LocVT = MVT::i32;
1903 18 : if (ArgFlags.isSExt())
1904 0 : LocInfo = CCValAssign::SExt;
1905 18 : else if (ArgFlags.isZExt())
1906 0 : LocInfo = CCValAssign::ZExt;
1907 : else
1908 18 : LocInfo = CCValAssign::AExt;
1909 : }
1910 :
1911 185 : if (LocVT == MVT::i32) {
1912 : static const MCPhysReg RegList1[] = {
1913 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1914 : };
1915 62 : if (unsigned Reg = State.AllocateReg(RegList1)) {
1916 120 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1917 60 : return false;
1918 : }
1919 : }
1920 :
1921 125 : if (LocVT == MVT::i64) {
1922 : static const MCPhysReg RegList2[] = {
1923 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1924 : };
1925 9 : if (unsigned Reg = State.AllocateReg(RegList2)) {
1926 18 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1927 9 : return false;
1928 : }
1929 : }
1930 :
1931 116 : if (LocVT == MVT::v64i1) {
1932 26 : LocVT = MVT::i64;
1933 26 : if (ArgFlags.isSExt())
1934 0 : LocInfo = CCValAssign::SExt;
1935 26 : else if (ArgFlags.isZExt())
1936 0 : LocInfo = CCValAssign::ZExt;
1937 : else
1938 26 : LocInfo = CCValAssign::AExt;
1939 : }
1940 :
1941 116 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1942 116 : if (LocVT == MVT::i64) {
1943 : static const MCPhysReg RegList3[] = {
1944 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1945 : };
1946 26 : if (unsigned Reg = State.AllocateReg(RegList3)) {
1947 44 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1948 22 : return false;
1949 : }
1950 : }
1951 : }
1952 :
1953 94 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
1954 0 : if (LocVT == MVT::i64) {
1955 0 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1956 : return false;
1957 : }
1958 : }
1959 :
1960 89 : if (LocVT == MVT::f32 ||
1961 178 : LocVT == MVT::f64 ||
1962 : LocVT == MVT::f128) {
1963 20 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1964 : static const MCPhysReg RegList4[] = {
1965 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1966 : };
1967 10 : if (unsigned Reg = State.AllocateReg(RegList4)) {
1968 20 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1969 10 : return false;
1970 : }
1971 : }
1972 : }
1973 :
1974 84 : if (LocVT == MVT::f80) {
1975 : if (unsigned Reg = State.AllocateReg(X86::FP0)) {
1976 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1977 3 : return false;
1978 : }
1979 : }
1980 :
1981 81 : if (LocVT == MVT::v16i8 ||
1982 81 : LocVT == MVT::v8i16 ||
1983 76 : LocVT == MVT::v4i32 ||
1984 76 : LocVT == MVT::v2i64 ||
1985 121 : LocVT == MVT::v4f32 ||
1986 : LocVT == MVT::v2f64) {
1987 82 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1988 : static const MCPhysReg RegList5[] = {
1989 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1990 : };
1991 41 : if (unsigned Reg = State.AllocateReg(RegList5)) {
1992 66 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1993 33 : return false;
1994 : }
1995 : }
1996 : }
1997 :
1998 48 : if (LocVT == MVT::v32i8 ||
1999 48 : LocVT == MVT::v16i16 ||
2000 43 : LocVT == MVT::v8i32 ||
2001 43 : LocVT == MVT::v4i64 ||
2002 91 : LocVT == MVT::v8f32 ||
2003 : LocVT == MVT::v4f64) {
2004 10 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2005 : static const MCPhysReg RegList6[] = {
2006 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2007 : };
2008 5 : if (unsigned Reg = State.AllocateReg(RegList6)) {
2009 10 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2010 5 : return false;
2011 : }
2012 : }
2013 : }
2014 :
2015 43 : if (LocVT == MVT::v64i8 ||
2016 43 : LocVT == MVT::v32i16 ||
2017 38 : LocVT == MVT::v16i32 ||
2018 38 : LocVT == MVT::v8i64 ||
2019 57 : LocVT == MVT::v16f32 ||
2020 : LocVT == MVT::v8f64) {
2021 58 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2022 : static const MCPhysReg RegList7[] = {
2023 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2024 : };
2025 29 : if (unsigned Reg = State.AllocateReg(RegList7)) {
2026 54 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2027 27 : return false;
2028 : }
2029 : }
2030 : }
2031 :
2032 16 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2033 14 : if (LocVT == MVT::i32 ||
2034 10 : LocVT == MVT::i64 ||
2035 26 : LocVT == MVT::f32 ||
2036 : LocVT == MVT::f64) {
2037 6 : unsigned Offset8 = State.AllocateStack(8, 8);
2038 12 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2039 6 : return false;
2040 : }
2041 : }
2042 :
2043 10 : if (LocVT == MVT::i32 ||
2044 : LocVT == MVT::f32) {
2045 0 : unsigned Offset9 = State.AllocateStack(4, 4);
2046 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2047 0 : return false;
2048 : }
2049 :
2050 10 : if (LocVT == MVT::i64 ||
2051 : LocVT == MVT::f64) {
2052 0 : unsigned Offset10 = State.AllocateStack(8, 4);
2053 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2054 0 : return false;
2055 : }
2056 :
2057 10 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2058 10 : if (LocVT == MVT::x86mmx) {
2059 0 : unsigned Offset11 = State.AllocateStack(8, 8);
2060 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2061 0 : return false;
2062 : }
2063 : }
2064 :
2065 10 : if (LocVT == MVT::x86mmx) {
2066 0 : unsigned Offset12 = State.AllocateStack(8, 4);
2067 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2068 0 : return false;
2069 : }
2070 :
2071 10 : if (LocVT == MVT::f80 ||
2072 : LocVT == MVT::f128) {
2073 0 : unsigned Offset13 = State.AllocateStack(
2074 0 : State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
2075 0 : State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2076 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2077 0 : return false;
2078 : }
2079 :
2080 10 : if (LocVT == MVT::v16i8 ||
2081 10 : LocVT == MVT::v8i16 ||
2082 10 : LocVT == MVT::v4i32 ||
2083 10 : LocVT == MVT::v2i64 ||
2084 12 : LocVT == MVT::v4f32 ||
2085 : LocVT == MVT::v2f64) {
2086 8 : unsigned Offset14 = State.AllocateStack(16, 16);
2087 16 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2088 8 : return false;
2089 : }
2090 :
2091 2 : if (LocVT == MVT::v32i8 ||
2092 2 : LocVT == MVT::v16i16 ||
2093 2 : LocVT == MVT::v8i32 ||
2094 2 : LocVT == MVT::v4i64 ||
2095 4 : LocVT == MVT::v8f32 ||
2096 : LocVT == MVT::v4f64) {
2097 0 : unsigned Offset15 = State.AllocateStack(32, 32);
2098 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2099 0 : return false;
2100 : }
2101 :
2102 2 : if (LocVT == MVT::v16i32 ||
2103 2 : LocVT == MVT::v8i64 ||
2104 2 : LocVT == MVT::v16f32 ||
2105 : LocVT == MVT::v8f64) {
2106 2 : unsigned Offset16 = State.AllocateStack(64, 64);
2107 4 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2108 2 : return false;
2109 : }
2110 :
2111 : return true; // CC didn't match.
2112 : }
2113 :
2114 :
2115 244 : static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2116 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2117 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2118 :
2119 244 : if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2120 : return false;
2121 :
2122 60 : if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2123 60 : return false;
2124 :
2125 : return true; // CC didn't match.
2126 : }
2127 :
2128 :
2129 2937 : static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2130 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2131 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2132 :
2133 2937 : if (ArgFlags.isByVal()) {
2134 : LocVT = MVT::i64;
2135 : LocInfo = CCValAssign::Indirect;
2136 : }
2137 :
2138 2937 : if (LocVT == MVT::i1 ||
2139 : LocVT == MVT::v1i1) {
2140 : LocVT = MVT::i8;
2141 0 : if (ArgFlags.isSExt())
2142 : LocInfo = CCValAssign::SExt;
2143 0 : else if (ArgFlags.isZExt())
2144 : LocInfo = CCValAssign::ZExt;
2145 : else
2146 : LocInfo = CCValAssign::AExt;
2147 : }
2148 :
2149 2937 : if (ArgFlags.isNest()) {
2150 : if (unsigned Reg = State.AllocateReg(X86::R10)) {
2151 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2152 2 : return false;
2153 : }
2154 : }
2155 :
2156 2935 : if (ArgFlags.isSwiftError()) {
2157 2 : if (LocVT == MVT::i64) {
2158 : if (unsigned Reg = State.AllocateReg(X86::R12)) {
2159 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2160 2 : return false;
2161 : }
2162 : }
2163 : }
2164 :
2165 2932 : if (LocVT == MVT::v16i8 ||
2166 2930 : LocVT == MVT::v8i16 ||
2167 2922 : LocVT == MVT::v4i32 ||
2168 2922 : LocVT == MVT::v2i64 ||
2169 5531 : LocVT == MVT::v4f32 ||
2170 : LocVT == MVT::v2f64) {
2171 : LocVT = MVT::i64;
2172 : LocInfo = CCValAssign::Indirect;
2173 : }
2174 :
2175 2933 : if (LocVT == MVT::v32i8 ||
2176 2933 : LocVT == MVT::v16i16 ||
2177 2931 : LocVT == MVT::v8i32 ||
2178 2931 : LocVT == MVT::v4i64 ||
2179 5694 : LocVT == MVT::v8f32 ||
2180 : LocVT == MVT::v4f64) {
2181 : LocVT = MVT::i64;
2182 : LocInfo = CCValAssign::Indirect;
2183 : }
2184 :
2185 2933 : if (LocVT == MVT::v16i32 ||
2186 2919 : LocVT == MVT::v16f32 ||
2187 5852 : LocVT == MVT::v8f64 ||
2188 : LocVT == MVT::v8i64) {
2189 : LocVT = MVT::i64;
2190 : LocInfo = CCValAssign::Indirect;
2191 : }
2192 :
2193 2933 : if (LocVT == MVT::f80) {
2194 : LocVT = MVT::i64;
2195 : LocInfo = CCValAssign::Indirect;
2196 : }
2197 :
2198 2933 : if (LocVT == MVT::x86mmx) {
2199 : LocVT = MVT::i64;
2200 : LocInfo = CCValAssign::BCvt;
2201 : }
2202 :
2203 2933 : if (LocVT == MVT::i8) {
2204 : static const MCPhysReg RegList1[] = {
2205 : X86::CL, X86::DL, X86::R8B, X86::R9B
2206 : };
2207 : static const MCPhysReg RegList2[] = {
2208 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2209 : };
2210 40 : if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
2211 36 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2212 36 : return false;
2213 : }
2214 : }
2215 :
2216 2897 : if (LocVT == MVT::i16) {
2217 : static const MCPhysReg RegList3[] = {
2218 : X86::CX, X86::DX, X86::R8W, X86::R9W
2219 : };
2220 : static const MCPhysReg RegList4[] = {
2221 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2222 : };
2223 70 : if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
2224 50 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2225 50 : return false;
2226 : }
2227 : }
2228 :
2229 2847 : if (LocVT == MVT::i32) {
2230 : static const MCPhysReg RegList5[] = {
2231 : X86::ECX, X86::EDX, X86::R8D, X86::R9D
2232 : };
2233 : static const MCPhysReg RegList6[] = {
2234 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2235 : };
2236 663 : if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
2237 578 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2238 578 : return false;
2239 : }
2240 : }
2241 :
2242 2269 : if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2243 14 : if (ArgFlags.isSRet()) {
2244 0 : if (LocVT == MVT::i64) {
2245 : static const MCPhysReg RegList7[] = {
2246 : X86::RDX, X86::R8, X86::R9
2247 : };
2248 : static const MCPhysReg RegList8[] = {
2249 : X86::XMM1, X86::XMM2, X86::XMM3
2250 : };
2251 0 : if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
2252 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2253 0 : return false;
2254 : }
2255 : }
2256 : }
2257 : }
2258 :
2259 2269 : if (LocVT == MVT::i64) {
2260 : static const MCPhysReg RegList9[] = {
2261 : X86::RCX, X86::RDX, X86::R8, X86::R9
2262 : };
2263 : static const MCPhysReg RegList10[] = {
2264 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2265 : };
2266 2024 : if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
2267 1933 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2268 1933 : return false;
2269 : }
2270 : }
2271 :
2272 265 : if (LocVT == MVT::f32 ||
2273 209 : LocVT == MVT::f64 ||
2274 209 : LocVT == MVT::v16i8 ||
2275 209 : LocVT == MVT::v8i16 ||
2276 209 : LocVT == MVT::v4i32 ||
2277 209 : LocVT == MVT::v2i64 ||
2278 545 : LocVT == MVT::v4f32 ||
2279 : LocVT == MVT::v2f64) {
2280 : static const MCPhysReg RegList11[] = {
2281 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2282 : };
2283 : static const MCPhysReg RegList12[] = {
2284 : X86::RCX, X86::RDX, X86::R8, X86::R9
2285 : };
2286 127 : if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
2287 104 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2288 104 : return false;
2289 : }
2290 : }
2291 :
2292 228 : if (LocVT == MVT::i8 ||
2293 208 : LocVT == MVT::i16 ||
2294 123 : LocVT == MVT::i32 ||
2295 32 : LocVT == MVT::i64 ||
2296 248 : LocVT == MVT::f32 ||
2297 : LocVT == MVT::f64) {
2298 223 : unsigned Offset13 = State.AllocateStack(8, 8);
2299 223 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2300 223 : return false;
2301 : }
2302 :
2303 : return true; // CC didn't match.
2304 : }
2305 :
2306 :
2307 195 : static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2308 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2309 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2310 :
2311 195 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2312 195 : if (ArgFlags.isByVal()) {
2313 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
2314 0 : return false;
2315 : }
2316 : }
2317 :
2318 195 : if (ArgFlags.isByVal()) {
2319 0 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
2320 0 : return false;
2321 : }
2322 :
2323 195 : if (LocVT == MVT::i1 ||
2324 184 : LocVT == MVT::i8 ||
2325 375 : LocVT == MVT::i16 ||
2326 : LocVT == MVT::v1i1) {
2327 15 : LocVT = MVT::i32;
2328 15 : if (ArgFlags.isSExt())
2329 2 : LocInfo = CCValAssign::SExt;
2330 13 : else if (ArgFlags.isZExt())
2331 0 : LocInfo = CCValAssign::ZExt;
2332 : else
2333 13 : LocInfo = CCValAssign::AExt;
2334 : }
2335 :
2336 189 : if (LocVT == MVT::v8i1 ||
2337 378 : LocVT == MVT::v16i1 ||
2338 : LocVT == MVT::v32i1) {
2339 18 : LocVT = MVT::i32;
2340 18 : if (ArgFlags.isSExt())
2341 0 : LocInfo = CCValAssign::SExt;
2342 18 : else if (ArgFlags.isZExt())
2343 0 : LocInfo = CCValAssign::ZExt;
2344 : else
2345 18 : LocInfo = CCValAssign::AExt;
2346 : }
2347 :
2348 195 : if (LocVT == MVT::i32) {
2349 : static const MCPhysReg RegList1[] = {
2350 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2351 : };
2352 72 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2353 144 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2354 72 : return false;
2355 : }
2356 : }
2357 :
2358 123 : if (LocVT == MVT::i64) {
2359 : static const MCPhysReg RegList2[] = {
2360 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2361 : };
2362 9 : if (unsigned Reg = State.AllocateReg(RegList2)) {
2363 18 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2364 9 : return false;
2365 : }
2366 : }
2367 :
2368 114 : if (LocVT == MVT::v64i1) {
2369 26 : LocVT = MVT::i64;
2370 26 : if (ArgFlags.isSExt())
2371 0 : LocInfo = CCValAssign::SExt;
2372 26 : else if (ArgFlags.isZExt())
2373 0 : LocInfo = CCValAssign::ZExt;
2374 : else
2375 26 : LocInfo = CCValAssign::AExt;
2376 : }
2377 :
2378 114 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2379 114 : if (LocVT == MVT::i64) {
2380 : static const MCPhysReg RegList3[] = {
2381 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2382 : };
2383 26 : if (unsigned Reg = State.AllocateReg(RegList3)) {
2384 48 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2385 24 : return false;
2386 : }
2387 : }
2388 : }
2389 :
2390 90 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2391 0 : if (LocVT == MVT::i64) {
2392 0 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2393 : return false;
2394 : }
2395 : }
2396 :
2397 85 : if (LocVT == MVT::f32 ||
2398 170 : LocVT == MVT::f64 ||
2399 : LocVT == MVT::f128) {
2400 20 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2401 : static const MCPhysReg RegList4[] = {
2402 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2403 : };
2404 10 : if (unsigned Reg = State.AllocateReg(RegList4)) {
2405 20 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2406 10 : return false;
2407 : }
2408 : }
2409 : }
2410 :
2411 80 : if (LocVT == MVT::f80) {
2412 : if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2413 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2414 3 : return false;
2415 : }
2416 : }
2417 :
2418 77 : if (LocVT == MVT::v16i8 ||
2419 77 : LocVT == MVT::v8i16 ||
2420 72 : LocVT == MVT::v4i32 ||
2421 72 : LocVT == MVT::v2i64 ||
2422 113 : LocVT == MVT::v4f32 ||
2423 : LocVT == MVT::v2f64) {
2424 82 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2425 : static const MCPhysReg RegList5[] = {
2426 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2427 : };
2428 41 : if (unsigned Reg = State.AllocateReg(RegList5)) {
2429 66 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2430 33 : return false;
2431 : }
2432 : }
2433 : }
2434 :
2435 44 : if (LocVT == MVT::v32i8 ||
2436 44 : LocVT == MVT::v16i16 ||
2437 39 : LocVT == MVT::v8i32 ||
2438 39 : LocVT == MVT::v4i64 ||
2439 83 : LocVT == MVT::v8f32 ||
2440 : LocVT == MVT::v4f64) {
2441 10 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2442 : static const MCPhysReg RegList6[] = {
2443 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2444 : };
2445 5 : if (unsigned Reg = State.AllocateReg(RegList6)) {
2446 10 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2447 5 : return false;
2448 : }
2449 : }
2450 : }
2451 :
2452 39 : if (LocVT == MVT::v64i8 ||
2453 39 : LocVT == MVT::v32i16 ||
2454 34 : LocVT == MVT::v16i32 ||
2455 34 : LocVT == MVT::v8i64 ||
2456 49 : LocVT == MVT::v16f32 ||
2457 : LocVT == MVT::v8f64) {
2458 58 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2459 : static const MCPhysReg RegList7[] = {
2460 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2461 : };
2462 29 : if (unsigned Reg = State.AllocateReg(RegList7)) {
2463 54 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2464 27 : return false;
2465 : }
2466 : }
2467 : }
2468 :
2469 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2470 12 : if (LocVT == MVT::i32 ||
2471 10 : LocVT == MVT::i64 ||
2472 22 : LocVT == MVT::f32 ||
2473 : LocVT == MVT::f64) {
2474 2 : unsigned Offset8 = State.AllocateStack(8, 8);
2475 4 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2476 2 : return false;
2477 : }
2478 : }
2479 :
2480 10 : if (LocVT == MVT::i32 ||
2481 : LocVT == MVT::f32) {
2482 0 : unsigned Offset9 = State.AllocateStack(4, 4);
2483 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2484 0 : return false;
2485 : }
2486 :
2487 10 : if (LocVT == MVT::i64 ||
2488 : LocVT == MVT::f64) {
2489 0 : unsigned Offset10 = State.AllocateStack(8, 4);
2490 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2491 0 : return false;
2492 : }
2493 :
2494 10 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2495 10 : if (LocVT == MVT::x86mmx) {
2496 0 : unsigned Offset11 = State.AllocateStack(8, 8);
2497 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2498 0 : return false;
2499 : }
2500 : }
2501 :
2502 10 : if (LocVT == MVT::x86mmx) {
2503 0 : unsigned Offset12 = State.AllocateStack(8, 4);
2504 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2505 0 : return false;
2506 : }
2507 :
2508 10 : if (LocVT == MVT::f80 ||
2509 : LocVT == MVT::f128) {
2510 0 : unsigned Offset13 = State.AllocateStack(
2511 0 : State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
2512 0 : State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2513 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2514 0 : return false;
2515 : }
2516 :
2517 10 : if (LocVT == MVT::v16i8 ||
2518 10 : LocVT == MVT::v8i16 ||
2519 10 : LocVT == MVT::v4i32 ||
2520 10 : LocVT == MVT::v2i64 ||
2521 12 : LocVT == MVT::v4f32 ||
2522 : LocVT == MVT::v2f64) {
2523 8 : unsigned Offset14 = State.AllocateStack(16, 16);
2524 16 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2525 8 : return false;
2526 : }
2527 :
2528 2 : if (LocVT == MVT::v32i8 ||
2529 2 : LocVT == MVT::v16i16 ||
2530 2 : LocVT == MVT::v8i32 ||
2531 2 : LocVT == MVT::v4i64 ||
2532 4 : LocVT == MVT::v8f32 ||
2533 : LocVT == MVT::v4f64) {
2534 0 : unsigned Offset15 = State.AllocateStack(32, 32);
2535 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2536 0 : return false;
2537 : }
2538 :
2539 2 : if (LocVT == MVT::v16i32 ||
2540 2 : LocVT == MVT::v8i64 ||
2541 2 : LocVT == MVT::v16f32 ||
2542 : LocVT == MVT::v8f64) {
2543 2 : unsigned Offset16 = State.AllocateStack(64, 64);
2544 4 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2545 2 : return false;
2546 : }
2547 :
2548 : return true; // CC didn't match.
2549 : }
2550 :
2551 :
2552 152 : static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
2553 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2554 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2555 :
2556 152 : if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2557 : return false;
2558 :
2559 17 : if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2560 17 : return false;
2561 :
2562 : return true; // CC didn't match.
2563 : }
2564 :
2565 :
2566 240 : static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
2567 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2568 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2569 :
2570 240 : if (LocVT == MVT::f32 ||
2571 240 : LocVT == MVT::f64 ||
2572 240 : LocVT == MVT::v4i32 ||
2573 240 : LocVT == MVT::v2i64 ||
2574 392 : LocVT == MVT::v4f32 ||
2575 : LocVT == MVT::v2f64) {
2576 : static const MCPhysReg RegList1[] = {
2577 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2578 : };
2579 88 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2580 88 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2581 88 : return false;
2582 : }
2583 : }
2584 :
2585 104 : if (LocVT == MVT::v8f32 ||
2586 104 : LocVT == MVT::v4f64 ||
2587 256 : LocVT == MVT::v8i32 ||
2588 : LocVT == MVT::v4i64) {
2589 : static const MCPhysReg RegList2[] = {
2590 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2591 : };
2592 48 : if (unsigned Reg = State.AllocateReg(RegList2)) {
2593 48 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2594 48 : return false;
2595 : }
2596 : }
2597 :
2598 8 : if (LocVT == MVT::v16f32 ||
2599 8 : LocVT == MVT::v8f64 ||
2600 112 : LocVT == MVT::v16i32 ||
2601 : LocVT == MVT::v8i64) {
2602 : static const MCPhysReg RegList3[] = {
2603 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2604 : };
2605 96 : if (unsigned Reg = State.AllocateReg(RegList3)) {
2606 96 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2607 96 : return false;
2608 : }
2609 : }
2610 :
2611 8 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2612 8 : return false;
2613 :
2614 : return true; // CC didn't match.
2615 : }
2616 :
2617 :
2618 1762349 : static bool RetCC_X86(unsigned ValNo, MVT ValVT,
2619 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2620 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2621 :
2622 1762349 : if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
2623 240 : if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2624 : return false;
2625 : }
2626 :
2627 1762109 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2628 1704108 : if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2629 : return false;
2630 : }
2631 :
2632 58277 : if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2633 57746 : return false;
2634 :
2635 : return true; // CC didn't match.
2636 : }
2637 :
2638 :
2639 1740717 : static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
2640 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2641 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2642 :
2643 1740717 : if (LocVT == MVT::v1i1) {
2644 : LocVT = MVT::i8;
2645 6 : if (ArgFlags.isSExt())
2646 : LocInfo = CCValAssign::SExt;
2647 6 : else if (ArgFlags.isZExt())
2648 : LocInfo = CCValAssign::ZExt;
2649 : else
2650 : LocInfo = CCValAssign::AExt;
2651 : }
2652 :
2653 1740717 : if (LocVT == MVT::i1) {
2654 : LocVT = MVT::i8;
2655 12 : if (ArgFlags.isSExt())
2656 : LocInfo = CCValAssign::SExt;
2657 12 : else if (ArgFlags.isZExt())
2658 : LocInfo = CCValAssign::ZExt;
2659 : else
2660 : LocInfo = CCValAssign::AExt;
2661 : }
2662 :
2663 1740717 : if (LocVT == MVT::i8) {
2664 : static const MCPhysReg RegList1[] = {
2665 : X86::AL, X86::DL, X86::CL
2666 : };
2667 97794 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2668 97682 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2669 97682 : return false;
2670 : }
2671 : }
2672 :
2673 1643035 : if (LocVT == MVT::i16) {
2674 : static const MCPhysReg RegList2[] = {
2675 : X86::AX, X86::DX, X86::CX
2676 : };
2677 5053 : if (unsigned Reg = State.AllocateReg(RegList2)) {
2678 5015 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2679 5015 : return false;
2680 : }
2681 : }
2682 :
2683 1638020 : if (LocVT == MVT::i32) {
2684 : static const MCPhysReg RegList3[] = {
2685 : X86::EAX, X86::EDX, X86::ECX
2686 : };
2687 285597 : if (unsigned Reg = State.AllocateReg(RegList3)) {
2688 285323 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2689 285323 : return false;
2690 : }
2691 : }
2692 :
2693 1352697 : if (LocVT == MVT::i64) {
2694 : static const MCPhysReg RegList4[] = {
2695 : X86::RAX, X86::RDX, X86::RCX
2696 : };
2697 1219069 : if (unsigned Reg = State.AllocateReg(RegList4)) {
2698 1218927 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2699 1218927 : return false;
2700 : }
2701 : }
2702 :
2703 133770 : if (LocVT == MVT::v2i1) {
2704 : LocVT = MVT::v2i64;
2705 28 : if (ArgFlags.isSExt())
2706 : LocInfo = CCValAssign::SExt;
2707 28 : else if (ArgFlags.isZExt())
2708 : LocInfo = CCValAssign::ZExt;
2709 : else
2710 : LocInfo = CCValAssign::AExt;
2711 : }
2712 :
2713 133770 : if (LocVT == MVT::v4i1) {
2714 : LocVT = MVT::v4i32;
2715 83 : if (ArgFlags.isSExt())
2716 : LocInfo = CCValAssign::SExt;
2717 83 : else if (ArgFlags.isZExt())
2718 : LocInfo = CCValAssign::ZExt;
2719 : else
2720 : LocInfo = CCValAssign::AExt;
2721 : }
2722 :
2723 133770 : if (LocVT == MVT::v8i1) {
2724 : LocVT = MVT::v8i16;
2725 116 : if (ArgFlags.isSExt())
2726 : LocInfo = CCValAssign::SExt;
2727 116 : else if (ArgFlags.isZExt())
2728 : LocInfo = CCValAssign::ZExt;
2729 : else
2730 : LocInfo = CCValAssign::AExt;
2731 : }
2732 :
2733 133770 : if (LocVT == MVT::v16i1) {
2734 : LocVT = MVT::v16i8;
2735 156 : if (ArgFlags.isSExt())
2736 : LocInfo = CCValAssign::SExt;
2737 156 : else if (ArgFlags.isZExt())
2738 : LocInfo = CCValAssign::ZExt;
2739 : else
2740 : LocInfo = CCValAssign::AExt;
2741 : }
2742 :
2743 133770 : if (LocVT == MVT::v32i1) {
2744 : LocVT = MVT::v32i8;
2745 30 : if (ArgFlags.isSExt())
2746 : LocInfo = CCValAssign::SExt;
2747 30 : else if (ArgFlags.isZExt())
2748 : LocInfo = CCValAssign::ZExt;
2749 : else
2750 : LocInfo = CCValAssign::AExt;
2751 : }
2752 :
2753 133770 : if (LocVT == MVT::v64i1) {
2754 : LocVT = MVT::v64i8;
2755 20 : if (ArgFlags.isSExt())
2756 : LocInfo = CCValAssign::SExt;
2757 20 : else if (ArgFlags.isZExt())
2758 : LocInfo = CCValAssign::ZExt;
2759 : else
2760 : LocInfo = CCValAssign::AExt;
2761 : }
2762 :
2763 124518 : if (LocVT == MVT::v16i8 ||
2764 112425 : LocVT == MVT::v8i16 ||
2765 97605 : LocVT == MVT::v4i32 ||
2766 85345 : LocVT == MVT::v2i64 ||
2767 203773 : LocVT == MVT::v4f32 ||
2768 : LocVT == MVT::v2f64) {
2769 : static const MCPhysReg RegList5[] = {
2770 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2771 : };
2772 73299 : if (unsigned Reg = State.AllocateReg(RegList5)) {
2773 73225 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2774 73225 : return false;
2775 : }
2776 : }
2777 :
2778 54431 : if (LocVT == MVT::v32i8 ||
2779 47002 : LocVT == MVT::v16i16 ||
2780 40306 : LocVT == MVT::v8i32 ||
2781 33678 : LocVT == MVT::v4i64 ||
2782 86700 : LocVT == MVT::v8f32 ||
2783 : LocVT == MVT::v4f64) {
2784 : static const MCPhysReg RegList6[] = {
2785 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2786 : };
2787 40558 : if (unsigned Reg = State.AllocateReg(RegList6)) {
2788 40548 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2789 40548 : return false;
2790 : }
2791 : }
2792 :
2793 18917 : if (LocVT == MVT::v64i8 ||
2794 17216 : LocVT == MVT::v32i16 ||
2795 14392 : LocVT == MVT::v16i32 ||
2796 10703 : LocVT == MVT::v8i64 ||
2797 26460 : LocVT == MVT::v16f32 ||
2798 : LocVT == MVT::v8f64) {
2799 : static const MCPhysReg RegList7[] = {
2800 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2801 : };
2802 17754 : if (unsigned Reg = State.AllocateReg(RegList7)) {
2803 17752 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2804 17752 : return false;
2805 : }
2806 : }
2807 :
2808 2245 : if (LocVT == MVT::x86mmx) {
2809 : if (unsigned Reg = State.AllocateReg(X86::MM0)) {
2810 6 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2811 6 : return false;
2812 : }
2813 : }
2814 :
2815 2239 : if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
2816 2188 : if (LocVT == MVT::f80) {
2817 : static const MCPhysReg RegList8[] = {
2818 : X86::FP0, X86::FP1
2819 : };
2820 1384 : if (unsigned Reg = State.AllocateReg(RegList8)) {
2821 1384 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2822 1384 : return false;
2823 : }
2824 : }
2825 : }
2826 :
2827 : return true; // CC didn't match.
2828 : }
2829 :
2830 :
2831 58277 : static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
2832 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2833 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2834 :
2835 58277 : if (State.getCallingConv() == CallingConv::Fast) {
2836 302 : if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2837 : return false;
2838 : }
2839 :
2840 57995 : if (State.getCallingConv() == CallingConv::HiPE) {
2841 30 : if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2842 : return false;
2843 : }
2844 :
2845 57965 : if (State.getCallingConv() == CallingConv::X86_VectorCall) {
2846 84 : if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2847 : return false;
2848 : }
2849 :
2850 57885 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
2851 178 : if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2852 : return false;
2853 : }
2854 :
2855 57707 : if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2856 57176 : return false;
2857 :
2858 : return true; // CC didn't match.
2859 : }
2860 :
2861 :
2862 57707 : static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
2863 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2864 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2865 :
2866 57707 : if (ArgFlags.isInReg()) {
2867 48 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2868 8 : if (LocVT == MVT::f32 ||
2869 : LocVT == MVT::f64) {
2870 : static const MCPhysReg RegList1[] = {
2871 : X86::XMM0, X86::XMM1, X86::XMM2
2872 : };
2873 8 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2874 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2875 8 : return false;
2876 : }
2877 : }
2878 : }
2879 : }
2880 :
2881 57699 : if (LocVT == MVT::f32 ||
2882 : LocVT == MVT::f64) {
2883 : static const MCPhysReg RegList2[] = {
2884 : X86::FP0, X86::FP1
2885 : };
2886 1837 : if (unsigned Reg = State.AllocateReg(RegList2)) {
2887 1749 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2888 1749 : return false;
2889 : }
2890 : }
2891 :
2892 55950 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2893 55419 : return false;
2894 :
2895 : return true; // CC didn't match.
2896 : }
2897 :
2898 :
2899 302 : static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
2900 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2901 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2902 :
2903 302 : if (LocVT == MVT::f32) {
2904 4 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2905 : static const MCPhysReg RegList1[] = {
2906 : X86::XMM0, X86::XMM1, X86::XMM2
2907 : };
2908 2 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2909 2 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2910 2 : return false;
2911 : }
2912 : }
2913 : }
2914 :
2915 300 : if (LocVT == MVT::f64) {
2916 50 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2917 : static const MCPhysReg RegList2[] = {
2918 : X86::XMM0, X86::XMM1, X86::XMM2
2919 : };
2920 17 : if (unsigned Reg = State.AllocateReg(RegList2)) {
2921 11 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2922 11 : return false;
2923 : }
2924 : }
2925 : }
2926 :
2927 289 : if (LocVT == MVT::i8) {
2928 : static const MCPhysReg RegList3[] = {
2929 : X86::AL, X86::DL, X86::CL
2930 : };
2931 15 : if (unsigned Reg = State.AllocateReg(RegList3)) {
2932 15 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2933 15 : return false;
2934 : }
2935 : }
2936 :
2937 274 : if (LocVT == MVT::i16) {
2938 : static const MCPhysReg RegList4[] = {
2939 : X86::AX, X86::DX, X86::CX
2940 : };
2941 0 : if (unsigned Reg = State.AllocateReg(RegList4)) {
2942 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2943 0 : return false;
2944 : }
2945 : }
2946 :
2947 274 : if (LocVT == MVT::i32) {
2948 : static const MCPhysReg RegList5[] = {
2949 : X86::EAX, X86::EDX, X86::ECX
2950 : };
2951 255 : if (unsigned Reg = State.AllocateReg(RegList5)) {
2952 250 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2953 250 : return false;
2954 : }
2955 : }
2956 :
2957 24 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2958 4 : return false;
2959 :
2960 : return true; // CC didn't match.
2961 : }
2962 :
2963 :
2964 30 : static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
2965 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2966 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2967 :
2968 30 : if (LocVT == MVT::i8 ||
2969 : LocVT == MVT::i16) {
2970 : LocVT = MVT::i32;
2971 0 : if (ArgFlags.isSExt())
2972 : LocInfo = CCValAssign::SExt;
2973 0 : else if (ArgFlags.isZExt())
2974 : LocInfo = CCValAssign::ZExt;
2975 : else
2976 : LocInfo = CCValAssign::AExt;
2977 : }
2978 :
2979 30 : if (LocVT == MVT::i32) {
2980 : static const MCPhysReg RegList1[] = {
2981 : X86::ESI, X86::EBP, X86::EAX, X86::EDX
2982 : };
2983 30 : if (unsigned Reg = State.AllocateReg(RegList1)) {
2984 30 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2985 30 : return false;
2986 : }
2987 : }
2988 :
2989 : return true; // CC didn't match.
2990 : }
2991 :
2992 :
2993 178 : static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
2994 : MVT LocVT, CCValAssign::LocInfo LocInfo,
2995 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
2996 :
2997 178 : if (LocVT == MVT::i1 ||
2998 356 : LocVT == MVT::v1i1 ||
2999 : LocVT == MVT::v8i1) {
3000 4 : LocVT = MVT::i8;
3001 4 : if (ArgFlags.isSExt())
3002 0 : LocInfo = CCValAssign::SExt;
3003 4 : else if (ArgFlags.isZExt())
3004 0 : LocInfo = CCValAssign::ZExt;
3005 : else
3006 4 : LocInfo = CCValAssign::AExt;
3007 : }
3008 :
3009 178 : if (LocVT == MVT::v16i1) {
3010 4 : LocVT = MVT::i16;
3011 4 : if (ArgFlags.isSExt())
3012 0 : LocInfo = CCValAssign::SExt;
3013 4 : else if (ArgFlags.isZExt())
3014 0 : LocInfo = CCValAssign::ZExt;
3015 : else
3016 4 : LocInfo = CCValAssign::AExt;
3017 : }
3018 :
3019 178 : if (LocVT == MVT::v32i1) {
3020 4 : LocVT = MVT::i32;
3021 4 : if (ArgFlags.isSExt())
3022 0 : LocInfo = CCValAssign::SExt;
3023 4 : else if (ArgFlags.isZExt())
3024 0 : LocInfo = CCValAssign::ZExt;
3025 : else
3026 4 : LocInfo = CCValAssign::AExt;
3027 : }
3028 :
3029 178 : if (LocVT == MVT::i8) {
3030 : static const MCPhysReg RegList1[] = {
3031 : X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3032 : };
3033 28 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3034 56 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3035 28 : return false;
3036 : }
3037 : }
3038 :
3039 150 : if (LocVT == MVT::i16) {
3040 : static const MCPhysReg RegList2[] = {
3041 : X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3042 : };
3043 14 : if (unsigned Reg = State.AllocateReg(RegList2)) {
3044 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3045 14 : return false;
3046 : }
3047 : }
3048 :
3049 136 : if (LocVT == MVT::i32) {
3050 : static const MCPhysReg RegList3[] = {
3051 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3052 : };
3053 60 : if (unsigned Reg = State.AllocateReg(RegList3)) {
3054 120 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3055 60 : return false;
3056 : }
3057 : }
3058 :
3059 76 : if (LocVT == MVT::i64) {
3060 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3061 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3062 0 : return false;
3063 : }
3064 : }
3065 :
3066 76 : if (LocVT == MVT::v64i1) {
3067 4 : LocVT = MVT::i64;
3068 4 : if (ArgFlags.isSExt())
3069 0 : LocInfo = CCValAssign::SExt;
3070 4 : else if (ArgFlags.isZExt())
3071 0 : LocInfo = CCValAssign::ZExt;
3072 : else
3073 4 : LocInfo = CCValAssign::AExt;
3074 : }
3075 :
3076 76 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3077 0 : if (LocVT == MVT::i64) {
3078 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3079 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3080 0 : return false;
3081 : }
3082 : }
3083 : }
3084 :
3085 76 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3086 76 : if (LocVT == MVT::i64) {
3087 4 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3088 : return false;
3089 : }
3090 : }
3091 :
3092 72 : if (LocVT == MVT::f80) {
3093 : static const MCPhysReg RegList4[] = {
3094 : X86::FP0, X86::FP1
3095 : };
3096 6 : if (unsigned Reg = State.AllocateReg(RegList4)) {
3097 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3098 6 : return false;
3099 : }
3100 : }
3101 :
3102 58 : if (LocVT == MVT::f32 ||
3103 116 : LocVT == MVT::f64 ||
3104 : LocVT == MVT::f128) {
3105 32 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3106 : static const MCPhysReg RegList5[] = {
3107 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3108 : };
3109 16 : if (unsigned Reg = State.AllocateReg(RegList5)) {
3110 32 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3111 16 : return false;
3112 : }
3113 : }
3114 : }
3115 :
3116 50 : if (LocVT == MVT::v16i8 ||
3117 50 : LocVT == MVT::v8i16 ||
3118 44 : LocVT == MVT::v4i32 ||
3119 44 : LocVT == MVT::v2i64 ||
3120 70 : LocVT == MVT::v4f32 ||
3121 : LocVT == MVT::v2f64) {
3122 60 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3123 : static const MCPhysReg RegList6[] = {
3124 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3125 : };
3126 30 : if (unsigned Reg = State.AllocateReg(RegList6)) {
3127 60 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3128 30 : return false;
3129 : }
3130 : }
3131 : }
3132 :
3133 20 : if (LocVT == MVT::v32i8 ||
3134 20 : LocVT == MVT::v16i16 ||
3135 14 : LocVT == MVT::v8i32 ||
3136 14 : LocVT == MVT::v4i64 ||
3137 34 : LocVT == MVT::v8f32 ||
3138 : LocVT == MVT::v4f64) {
3139 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3140 : static const MCPhysReg RegList7[] = {
3141 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3142 : };
3143 6 : if (unsigned Reg = State.AllocateReg(RegList7)) {
3144 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3145 6 : return false;
3146 : }
3147 : }
3148 : }
3149 :
3150 14 : if (LocVT == MVT::v64i8 ||
3151 14 : LocVT == MVT::v32i16 ||
3152 8 : LocVT == MVT::v16i32 ||
3153 8 : LocVT == MVT::v8i64 ||
3154 14 : LocVT == MVT::v16f32 ||
3155 : LocVT == MVT::v8f64) {
3156 28 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3157 : static const MCPhysReg RegList8[] = {
3158 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3159 : };
3160 14 : if (unsigned Reg = State.AllocateReg(RegList8)) {
3161 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3162 14 : return false;
3163 : }
3164 : }
3165 : }
3166 :
3167 : return true; // CC didn't match.
3168 : }
3169 :
3170 :
3171 84 : static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3172 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3173 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3174 :
3175 84 : if (LocVT == MVT::f32 ||
3176 140 : LocVT == MVT::f64 ||
3177 : LocVT == MVT::f128) {
3178 : static const MCPhysReg RegList1[] = {
3179 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3180 : };
3181 28 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3182 24 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3183 24 : return false;
3184 : }
3185 : }
3186 :
3187 60 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3188 56 : return false;
3189 :
3190 : return true; // CC didn't match.
3191 : }
3192 :
3193 :
3194 1704108 : static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3195 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3196 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3197 :
3198 1704108 : if (State.getCallingConv() == CallingConv::HiPE) {
3199 28 : if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3200 : return false;
3201 : }
3202 :
3203 1704080 : if (State.getCallingConv() == CallingConv::WebKit_JS) {
3204 20 : if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3205 : return false;
3206 : }
3207 :
3208 1704060 : if (State.getCallingConv() == CallingConv::AnyReg) {
3209 : if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3210 : return false;
3211 : }
3212 :
3213 1704060 : if (State.getCallingConv() == CallingConv::Swift) {
3214 411 : if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3215 : return false;
3216 : }
3217 :
3218 1703654 : if (State.getCallingConv() == CallingConv::Win64) {
3219 1 : if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3220 34 : return false;
3221 : }
3222 :
3223 1703620 : if (State.getCallingConv() == CallingConv::X86_64_SysV) {
3224 8 : if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3225 : return false;
3226 : }
3227 :
3228 1703612 : if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3229 60 : if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3230 : return false;
3231 : }
3232 :
3233 1703554 : if (State.getCallingConv() == CallingConv::HHVM) {
3234 70 : if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3235 : return false;
3236 : }
3237 :
3238 1703484 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
3239 324 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3240 166 : if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3241 : return false;
3242 : }
3243 : }
3244 :
3245 1703318 : if (State.getCallingConv() == CallingConv::X86_RegCall) {
3246 158 : if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3247 : return false;
3248 : }
3249 :
3250 1703160 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3251 16 : if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3252 2615 : return false;
3253 : }
3254 :
3255 1700545 : if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3256 1700269 : return false;
3257 :
3258 : return true; // CC didn't match.
3259 : }
3260 :
3261 :
3262 0 : static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
3263 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3264 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3265 :
3266 : if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3267 : return false;
3268 :
3269 : return true; // CC didn't match.
3270 : }
3271 :
3272 :
3273 1703255 : static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
3274 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3275 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3276 :
3277 1703255 : if (LocVT == MVT::f32) {
3278 : static const MCPhysReg RegList1[] = {
3279 : X86::XMM0, X86::XMM1
3280 : };
3281 8092 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3282 8092 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3283 8092 : return false;
3284 : }
3285 : }
3286 :
3287 1695163 : if (LocVT == MVT::f64) {
3288 : static const MCPhysReg RegList2[] = {
3289 : X86::XMM0, X86::XMM1
3290 : };
3291 10045 : if (unsigned Reg = State.AllocateReg(RegList2)) {
3292 9991 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3293 9991 : return false;
3294 : }
3295 : }
3296 :
3297 1685172 : if (LocVT == MVT::f128) {
3298 : static const MCPhysReg RegList3[] = {
3299 : X86::XMM0, X86::XMM1
3300 : };
3301 308 : if (unsigned Reg = State.AllocateReg(RegList3)) {
3302 308 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3303 308 : return false;
3304 : }
3305 : }
3306 :
3307 1684864 : if (LocVT == MVT::x86mmx) {
3308 : static const MCPhysReg RegList4[] = {
3309 : X86::XMM0, X86::XMM1
3310 : };
3311 204 : if (unsigned Reg = State.AllocateReg(RegList4)) {
3312 204 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3313 204 : return false;
3314 : }
3315 : }
3316 :
3317 1684660 : if (ArgFlags.isSwiftError()) {
3318 26 : if (LocVT == MVT::i64) {
3319 : if (unsigned Reg = State.AllocateReg(X86::R12)) {
3320 26 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3321 26 : return false;
3322 : }
3323 : }
3324 : }
3325 :
3326 1684634 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3327 1684339 : return false;
3328 :
3329 : return true; // CC didn't match.
3330 : }
3331 :
3332 :
3333 70 : static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
3334 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3335 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3336 :
3337 70 : if (LocVT == MVT::i8 ||
3338 140 : LocVT == MVT::i16 ||
3339 : LocVT == MVT::i32) {
3340 : LocVT = MVT::i64;
3341 0 : if (ArgFlags.isSExt())
3342 : LocInfo = CCValAssign::SExt;
3343 0 : else if (ArgFlags.isZExt())
3344 : LocInfo = CCValAssign::ZExt;
3345 : else
3346 : LocInfo = CCValAssign::AExt;
3347 : }
3348 :
3349 70 : if (LocVT == MVT::i64) {
3350 : static const MCPhysReg RegList1[] = {
3351 : X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3352 : };
3353 70 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3354 70 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3355 70 : return false;
3356 : }
3357 : }
3358 :
3359 : return true; // CC didn't match.
3360 : }
3361 :
3362 :
3363 28 : static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
3364 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3365 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3366 :
3367 28 : if (LocVT == MVT::i8 ||
3368 56 : LocVT == MVT::i16 ||
3369 : LocVT == MVT::i32) {
3370 : LocVT = MVT::i64;
3371 10 : if (ArgFlags.isSExt())
3372 : LocInfo = CCValAssign::SExt;
3373 10 : else if (ArgFlags.isZExt())
3374 : LocInfo = CCValAssign::ZExt;
3375 : else
3376 : LocInfo = CCValAssign::AExt;
3377 : }
3378 :
3379 28 : if (LocVT == MVT::i64) {
3380 : static const MCPhysReg RegList1[] = {
3381 : X86::R15, X86::RBP, X86::RAX, X86::RDX
3382 : };
3383 28 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3384 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3385 28 : return false;
3386 : }
3387 : }
3388 :
3389 : return true; // CC didn't match.
3390 : }
3391 :
3392 :
3393 411 : static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
3394 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3395 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3396 :
3397 411 : if (ArgFlags.isSwiftError()) {
3398 54 : if (LocVT == MVT::i64) {
3399 : if (unsigned Reg = State.AllocateReg(X86::R12)) {
3400 54 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3401 54 : return false;
3402 : }
3403 : }
3404 : }
3405 :
3406 357 : if (LocVT == MVT::v1i1) {
3407 : LocVT = MVT::i8;
3408 0 : if (ArgFlags.isSExt())
3409 : LocInfo = CCValAssign::SExt;
3410 0 : else if (ArgFlags.isZExt())
3411 : LocInfo = CCValAssign::ZExt;
3412 : else
3413 : LocInfo = CCValAssign::AExt;
3414 : }
3415 :
3416 357 : if (LocVT == MVT::i1) {
3417 : LocVT = MVT::i8;
3418 0 : if (ArgFlags.isSExt())
3419 : LocInfo = CCValAssign::SExt;
3420 0 : else if (ArgFlags.isZExt())
3421 : LocInfo = CCValAssign::ZExt;
3422 : else
3423 : LocInfo = CCValAssign::AExt;
3424 : }
3425 :
3426 357 : if (LocVT == MVT::i8) {
3427 : static const MCPhysReg RegList1[] = {
3428 : X86::AL, X86::DL, X86::CL, X86::R8B
3429 : };
3430 38 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3431 38 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3432 38 : return false;
3433 : }
3434 : }
3435 :
3436 319 : if (LocVT == MVT::i16) {
3437 : static const MCPhysReg RegList2[] = {
3438 : X86::AX, X86::DX, X86::CX, X86::R8W
3439 : };
3440 4 : if (unsigned Reg = State.AllocateReg(RegList2)) {
3441 4 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3442 4 : return false;
3443 : }
3444 : }
3445 :
3446 315 : if (LocVT == MVT::i32) {
3447 : static const MCPhysReg RegList3[] = {
3448 : X86::EAX, X86::EDX, X86::ECX, X86::R8D
3449 : };
3450 69 : if (unsigned Reg = State.AllocateReg(RegList3)) {
3451 64 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3452 64 : return false;
3453 : }
3454 : }
3455 :
3456 251 : if (LocVT == MVT::i64) {
3457 : static const MCPhysReg RegList4[] = {
3458 : X86::RAX, X86::RDX, X86::RCX, X86::R8
3459 : };
3460 100 : if (unsigned Reg = State.AllocateReg(RegList4)) {
3461 100 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3462 100 : return false;
3463 : }
3464 : }
3465 :
3466 151 : if (LocVT == MVT::f32) {
3467 : static const MCPhysReg RegList5[] = {
3468 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3469 : };
3470 54 : if (unsigned Reg = State.AllocateReg(RegList5)) {
3471 54 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3472 54 : return false;
3473 : }
3474 : }
3475 :
3476 97 : if (LocVT == MVT::f64) {
3477 : static const MCPhysReg RegList6[] = {
3478 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3479 : };
3480 56 : if (unsigned Reg = State.AllocateReg(RegList6)) {
3481 56 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3482 56 : return false;
3483 : }
3484 : }
3485 :
3486 41 : if (LocVT == MVT::f128) {
3487 : static const MCPhysReg RegList7[] = {
3488 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3489 : };
3490 0 : if (unsigned Reg = State.AllocateReg(RegList7)) {
3491 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3492 0 : return false;
3493 : }
3494 : }
3495 :
3496 41 : if (LocVT == MVT::x86mmx) {
3497 : static const MCPhysReg RegList8[] = {
3498 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3499 : };
3500 0 : if (unsigned Reg = State.AllocateReg(RegList8)) {
3501 0 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3502 0 : return false;
3503 : }
3504 : }
3505 :
3506 41 : if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3507 36 : return false;
3508 :
3509 : return true; // CC didn't match.
3510 : }
3511 :
3512 :
3513 60 : static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
3514 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3515 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3516 :
3517 60 : if (LocVT == MVT::f32 ||
3518 94 : LocVT == MVT::f64 ||
3519 : LocVT == MVT::f128) {
3520 : static const MCPhysReg RegList1[] = {
3521 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3522 : };
3523 26 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3524 24 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3525 24 : return false;
3526 : }
3527 : }
3528 :
3529 2 : if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3530 34 : return false;
3531 :
3532 : return true; // CC didn't match.
3533 : }
3534 :
3535 :
3536 20 : static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
3537 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3538 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3539 :
3540 20 : if (LocVT == MVT::i8 ||
3541 40 : LocVT == MVT::i16 ||
3542 : LocVT == MVT::i32) {
3543 : LocVT = MVT::i64;
3544 8 : if (ArgFlags.isSExt())
3545 : LocInfo = CCValAssign::SExt;
3546 8 : else if (ArgFlags.isZExt())
3547 : LocInfo = CCValAssign::ZExt;
3548 : else
3549 : LocInfo = CCValAssign::AExt;
3550 : }
3551 :
3552 20 : if (LocVT == MVT::i64) {
3553 : if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3554 20 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3555 20 : return false;
3556 : }
3557 : }
3558 :
3559 : return true; // CC didn't match.
3560 : }
3561 :
3562 :
3563 158 : static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
3564 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3565 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3566 :
3567 158 : if (LocVT == MVT::i1 ||
3568 316 : LocVT == MVT::v1i1 ||
3569 : LocVT == MVT::v8i1) {
3570 4 : LocVT = MVT::i8;
3571 4 : if (ArgFlags.isSExt())
3572 0 : LocInfo = CCValAssign::SExt;
3573 4 : else if (ArgFlags.isZExt())
3574 0 : LocInfo = CCValAssign::ZExt;
3575 : else
3576 4 : LocInfo = CCValAssign::AExt;
3577 : }
3578 :
3579 158 : if (LocVT == MVT::v16i1) {
3580 4 : LocVT = MVT::i16;
3581 4 : if (ArgFlags.isSExt())
3582 0 : LocInfo = CCValAssign::SExt;
3583 4 : else if (ArgFlags.isZExt())
3584 0 : LocInfo = CCValAssign::ZExt;
3585 : else
3586 4 : LocInfo = CCValAssign::AExt;
3587 : }
3588 :
3589 158 : if (LocVT == MVT::v32i1) {
3590 4 : LocVT = MVT::i32;
3591 4 : if (ArgFlags.isSExt())
3592 0 : LocInfo = CCValAssign::SExt;
3593 4 : else if (ArgFlags.isZExt())
3594 0 : LocInfo = CCValAssign::ZExt;
3595 : else
3596 4 : LocInfo = CCValAssign::AExt;
3597 : }
3598 :
3599 158 : if (LocVT == MVT::i8) {
3600 : static const MCPhysReg RegList1[] = {
3601 : X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3602 : };
3603 28 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3604 56 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3605 28 : return false;
3606 : }
3607 : }
3608 :
3609 130 : if (LocVT == MVT::i16) {
3610 : static const MCPhysReg RegList2[] = {
3611 : X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3612 : };
3613 14 : if (unsigned Reg = State.AllocateReg(RegList2)) {
3614 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3615 14 : return false;
3616 : }
3617 : }
3618 :
3619 116 : if (LocVT == MVT::i32) {
3620 : static const MCPhysReg RegList3[] = {
3621 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3622 : };
3623 22 : if (unsigned Reg = State.AllocateReg(RegList3)) {
3624 44 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3625 22 : return false;
3626 : }
3627 : }
3628 :
3629 94 : if (LocVT == MVT::i64) {
3630 : static const MCPhysReg RegList4[] = {
3631 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3632 : };
3633 18 : if (unsigned Reg = State.AllocateReg(RegList4)) {
3634 36 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3635 18 : return false;
3636 : }
3637 : }
3638 :
3639 76 : if (LocVT == MVT::v64i1) {
3640 4 : LocVT = MVT::i64;
3641 4 : if (ArgFlags.isSExt())
3642 0 : LocInfo = CCValAssign::SExt;
3643 4 : else if (ArgFlags.isZExt())
3644 0 : LocInfo = CCValAssign::ZExt;
3645 : else
3646 4 : LocInfo = CCValAssign::AExt;
3647 : }
3648 :
3649 76 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3650 76 : if (LocVT == MVT::i64) {
3651 : static const MCPhysReg RegList5[] = {
3652 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3653 : };
3654 4 : if (unsigned Reg = State.AllocateReg(RegList5)) {
3655 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3656 4 : return false;
3657 : }
3658 : }
3659 : }
3660 :
3661 72 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3662 0 : if (LocVT == MVT::i64) {
3663 0 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3664 : return false;
3665 : }
3666 : }
3667 :
3668 72 : if (LocVT == MVT::f80) {
3669 : static const MCPhysReg RegList6[] = {
3670 : X86::FP0, X86::FP1
3671 : };
3672 6 : if (unsigned Reg = State.AllocateReg(RegList6)) {
3673 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3674 6 : return false;
3675 : }
3676 : }
3677 :
3678 58 : if (LocVT == MVT::f32 ||
3679 116 : LocVT == MVT::f64 ||
3680 : LocVT == MVT::f128) {
3681 32 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3682 : static const MCPhysReg RegList7[] = {
3683 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3684 : };
3685 16 : if (unsigned Reg = State.AllocateReg(RegList7)) {
3686 32 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3687 16 : return false;
3688 : }
3689 : }
3690 : }
3691 :
3692 50 : if (LocVT == MVT::v16i8 ||
3693 50 : LocVT == MVT::v8i16 ||
3694 44 : LocVT == MVT::v4i32 ||
3695 44 : LocVT == MVT::v2i64 ||
3696 70 : LocVT == MVT::v4f32 ||
3697 : LocVT == MVT::v2f64) {
3698 60 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3699 : static const MCPhysReg RegList8[] = {
3700 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3701 : };
3702 30 : if (unsigned Reg = State.AllocateReg(RegList8)) {
3703 60 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3704 30 : return false;
3705 : }
3706 : }
3707 : }
3708 :
3709 20 : if (LocVT == MVT::v32i8 ||
3710 20 : LocVT == MVT::v16i16 ||
3711 14 : LocVT == MVT::v8i32 ||
3712 14 : LocVT == MVT::v4i64 ||
3713 34 : LocVT == MVT::v8f32 ||
3714 : LocVT == MVT::v4f64) {
3715 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3716 : static const MCPhysReg RegList9[] = {
3717 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3718 : };
3719 6 : if (unsigned Reg = State.AllocateReg(RegList9)) {
3720 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3721 6 : return false;
3722 : }
3723 : }
3724 : }
3725 :
3726 14 : if (LocVT == MVT::v64i8 ||
3727 14 : LocVT == MVT::v32i16 ||
3728 8 : LocVT == MVT::v16i32 ||
3729 8 : LocVT == MVT::v8i64 ||
3730 14 : LocVT == MVT::v16f32 ||
3731 : LocVT == MVT::v8f64) {
3732 28 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3733 : static const MCPhysReg RegList10[] = {
3734 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3735 : };
3736 14 : if (unsigned Reg = State.AllocateReg(RegList10)) {
3737 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3738 14 : return false;
3739 : }
3740 : }
3741 : }
3742 :
3743 : return true; // CC didn't match.
3744 : }
3745 :
3746 :
3747 : static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
3748 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3749 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3750 :
3751 2702 : if (LocVT == MVT::x86mmx) {
3752 : LocVT = MVT::i64;
3753 : LocInfo = CCValAssign::BCvt;
3754 : }
3755 :
3756 2702 : if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3757 : return false;
3758 :
3759 : return true; // CC didn't match.
3760 : }
3761 :
3762 :
3763 166 : static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
3764 : MVT LocVT, CCValAssign::LocInfo LocInfo,
3765 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
3766 :
3767 166 : if (LocVT == MVT::i1 ||
3768 332 : LocVT == MVT::v1i1 ||
3769 : LocVT == MVT::v8i1) {
3770 4 : LocVT = MVT::i8;
3771 4 : if (ArgFlags.isSExt())
3772 0 : LocInfo = CCValAssign::SExt;
3773 4 : else if (ArgFlags.isZExt())
3774 0 : LocInfo = CCValAssign::ZExt;
3775 : else
3776 4 : LocInfo = CCValAssign::AExt;
3777 : }
3778 :
3779 166 : if (LocVT == MVT::v16i1) {
3780 4 : LocVT = MVT::i16;
3781 4 : if (ArgFlags.isSExt())
3782 0 : LocInfo = CCValAssign::SExt;
3783 4 : else if (ArgFlags.isZExt())
3784 0 : LocInfo = CCValAssign::ZExt;
3785 : else
3786 4 : LocInfo = CCValAssign::AExt;
3787 : }
3788 :
3789 166 : if (LocVT == MVT::v32i1) {
3790 4 : LocVT = MVT::i32;
3791 4 : if (ArgFlags.isSExt())
3792 0 : LocInfo = CCValAssign::SExt;
3793 4 : else if (ArgFlags.isZExt())
3794 0 : LocInfo = CCValAssign::ZExt;
3795 : else
3796 4 : LocInfo = CCValAssign::AExt;
3797 : }
3798 :
3799 166 : if (LocVT == MVT::i8) {
3800 : static const MCPhysReg RegList1[] = {
3801 : X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
3802 : };
3803 28 : if (unsigned Reg = State.AllocateReg(RegList1)) {
3804 56 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3805 28 : return false;
3806 : }
3807 : }
3808 :
3809 138 : if (LocVT == MVT::i16) {
3810 : static const MCPhysReg RegList2[] = {
3811 : X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
3812 : };
3813 14 : if (unsigned Reg = State.AllocateReg(RegList2)) {
3814 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3815 14 : return false;
3816 : }
3817 : }
3818 :
3819 124 : if (LocVT == MVT::i32) {
3820 : static const MCPhysReg RegList3[] = {
3821 : X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
3822 : };
3823 30 : if (unsigned Reg = State.AllocateReg(RegList3)) {
3824 60 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3825 30 : return false;
3826 : }
3827 : }
3828 :
3829 94 : if (LocVT == MVT::i64) {
3830 : static const MCPhysReg RegList4[] = {
3831 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3832 : };
3833 18 : if (unsigned Reg = State.AllocateReg(RegList4)) {
3834 36 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3835 18 : return false;
3836 : }
3837 : }
3838 :
3839 76 : if (LocVT == MVT::v64i1) {
3840 4 : LocVT = MVT::i64;
3841 4 : if (ArgFlags.isSExt())
3842 0 : LocInfo = CCValAssign::SExt;
3843 4 : else if (ArgFlags.isZExt())
3844 0 : LocInfo = CCValAssign::ZExt;
3845 : else
3846 4 : LocInfo = CCValAssign::AExt;
3847 : }
3848 :
3849 76 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3850 76 : if (LocVT == MVT::i64) {
3851 : static const MCPhysReg RegList5[] = {
3852 : X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3853 : };
3854 4 : if (unsigned Reg = State.AllocateReg(RegList5)) {
3855 8 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3856 4 : return false;
3857 : }
3858 : }
3859 : }
3860 :
3861 72 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3862 0 : if (LocVT == MVT::i64) {
3863 0 : if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3864 : return false;
3865 : }
3866 : }
3867 :
3868 72 : if (LocVT == MVT::f80) {
3869 : static const MCPhysReg RegList6[] = {
3870 : X86::FP0, X86::FP1
3871 : };
3872 6 : if (unsigned Reg = State.AllocateReg(RegList6)) {
3873 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3874 6 : return false;
3875 : }
3876 : }
3877 :
3878 58 : if (LocVT == MVT::f32 ||
3879 116 : LocVT == MVT::f64 ||
3880 : LocVT == MVT::f128) {
3881 32 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3882 : static const MCPhysReg RegList7[] = {
3883 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3884 : };
3885 16 : if (unsigned Reg = State.AllocateReg(RegList7)) {
3886 32 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3887 16 : return false;
3888 : }
3889 : }
3890 : }
3891 :
3892 50 : if (LocVT == MVT::v16i8 ||
3893 50 : LocVT == MVT::v8i16 ||
3894 44 : LocVT == MVT::v4i32 ||
3895 44 : LocVT == MVT::v2i64 ||
3896 70 : LocVT == MVT::v4f32 ||
3897 : LocVT == MVT::v2f64) {
3898 60 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3899 : static const MCPhysReg RegList8[] = {
3900 : X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3901 : };
3902 30 : if (unsigned Reg = State.AllocateReg(RegList8)) {
3903 60 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3904 30 : return false;
3905 : }
3906 : }
3907 : }
3908 :
3909 20 : if (LocVT == MVT::v32i8 ||
3910 20 : LocVT == MVT::v16i16 ||
3911 14 : LocVT == MVT::v8i32 ||
3912 14 : LocVT == MVT::v4i64 ||
3913 34 : LocVT == MVT::v8f32 ||
3914 : LocVT == MVT::v4f64) {
3915 12 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3916 : static const MCPhysReg RegList9[] = {
3917 : X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3918 : };
3919 6 : if (unsigned Reg = State.AllocateReg(RegList9)) {
3920 12 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3921 6 : return false;
3922 : }
3923 : }
3924 : }
3925 :
3926 14 : if (LocVT == MVT::v64i8 ||
3927 14 : LocVT == MVT::v32i16 ||
3928 8 : LocVT == MVT::v16i32 ||
3929 8 : LocVT == MVT::v8i64 ||
3930 14 : LocVT == MVT::v16f32 ||
3931 : LocVT == MVT::v8f64) {
3932 28 : if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3933 : static const MCPhysReg RegList10[] = {
3934 : X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3935 : };
3936 14 : if (unsigned Reg = State.AllocateReg(RegList10)) {
3937 28 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3938 14 : return false;
3939 : }
3940 : }
3941 : }
3942 :
3943 : return true; // CC didn't match.
3944 : }
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