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1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : } // end namespace llvm
15 :
16 : #endif // GET_SUBTARGETINFO_ENUM
17 :
18 :
19 : #ifdef GET_SUBTARGETINFO_MC_DESC
20 : #undef GET_SUBTARGETINFO_MC_DESC
21 :
22 : namespace llvm {
23 :
24 : // Sorted (by key) array of values for CPU subtype.
25 : extern const llvm::SubtargetFeatureKV XCoreSubTypeKV[] = {
26 : { "generic", "Select the generic processor", { }, { } },
27 : { "xs1b-generic", "Select the xs1b-generic processor", { }, { } },
28 : };
29 :
30 : #ifdef DBGFIELD
31 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
32 : #endif
33 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
34 : #define DBGFIELD(x) x,
35 : #else
36 : #define DBGFIELD(x)
37 : #endif
38 :
39 : // ===============================================================
40 : // Data tables for the new per-operand machine model.
41 :
42 : // {ProcResourceIdx, Cycles}
43 : extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
44 : { 0, 0}, // Invalid
45 : }; // XCoreWriteProcResTable
46 :
47 : // {Cycles, WriteResourceID}
48 : extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
49 : { 0, 0}, // Invalid
50 : }; // XCoreWriteLatencyTable
51 :
52 : // {UseIdx, WriteResourceID, Cycles}
53 : extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
54 : {0, 0, 0}, // Invalid
55 : }; // XCoreReadAdvanceTable
56 :
57 : static const llvm::MCSchedModel NoSchedModel = {
58 : MCSchedModel::DefaultIssueWidth,
59 : MCSchedModel::DefaultMicroOpBufferSize,
60 : MCSchedModel::DefaultLoopMicroOpBufferSize,
61 : MCSchedModel::DefaultLoadLatency,
62 : MCSchedModel::DefaultHighLatency,
63 : MCSchedModel::DefaultMispredictPenalty,
64 : false, // PostRAScheduler
65 : false, // CompleteModel
66 : 0, // Processor ID
67 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
68 : nullptr, // No Itinerary
69 : nullptr // No extra processor descriptor
70 : };
71 :
72 : // Sorted (by key) array of itineraries for CPU subtype.
73 : extern const llvm::SubtargetInfoKV XCoreProcSchedKV[] = {
74 : { "generic", (const void *)&NoSchedModel },
75 : { "xs1b-generic", (const void *)&NoSchedModel },
76 : };
77 :
78 : #undef DBGFIELD
79 : namespace XCore_MC {
80 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
81 : const MCInst *MI, unsigned CPUID) {
82 : // Don't know how to resolve this scheduling class.
83 0 : return 0;
84 : }
85 : } // end of namespace XCore_MC
86 :
87 : struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
88 : XCoreGenMCSubtargetInfo(const Triple &TT,
89 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
90 : ArrayRef<SubtargetFeatureKV> PD,
91 : const SubtargetInfoKV *ProcSched,
92 : const MCWriteProcResEntry *WPR,
93 : const MCWriteLatencyEntry *WL,
94 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
95 81 : const unsigned *OC, const unsigned *FP) :
96 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
97 81 : WPR, WL, RA, IS, OC, FP) { }
98 :
99 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
100 : const MCInst *MI, unsigned CPUID) const override {
101 0 : return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
102 : }
103 : };
104 :
105 81 : static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
106 : return new XCoreGenMCSubtargetInfo(TT, CPU, FS, None, XCoreSubTypeKV,
107 : XCoreProcSchedKV, XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
108 81 : nullptr, nullptr, nullptr);
109 : }
110 :
111 : } // end namespace llvm
112 :
113 : #endif // GET_SUBTARGETINFO_MC_DESC
114 :
115 :
116 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
117 : #undef GET_SUBTARGETINFO_TARGET_DESC
118 :
119 : #include "llvm/Support/Debug.h"
120 : #include "llvm/Support/raw_ostream.h"
121 :
122 : // ParseSubtargetFeatures - Parses features string setting specified
123 : // subtarget options.
124 0 : void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
125 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
126 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
127 0 : }
128 : #endif // GET_SUBTARGETINFO_TARGET_DESC
129 :
130 :
131 : #ifdef GET_SUBTARGETINFO_HEADER
132 : #undef GET_SUBTARGETINFO_HEADER
133 :
134 : namespace llvm {
135 : class DFAPacketizer;
136 : namespace XCore_MC {
137 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
138 : }
139 :
140 : struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
141 : explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
142 : public:
143 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
144 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
145 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
146 : };
147 : } // end namespace llvm
148 :
149 : #endif // GET_SUBTARGETINFO_HEADER
150 :
151 :
152 : #ifdef GET_SUBTARGETINFO_CTOR
153 : #undef GET_SUBTARGETINFO_CTOR
154 :
155 : #include "llvm/CodeGen/TargetSchedule.h"
156 :
157 : namespace llvm {
158 : extern const llvm::SubtargetFeatureKV XCoreFeatureKV[];
159 : extern const llvm::SubtargetFeatureKV XCoreSubTypeKV[];
160 : extern const llvm::SubtargetInfoKV XCoreProcSchedKV[];
161 : extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
162 : extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
163 : extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
164 80 : XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
165 : : TargetSubtargetInfo(TT, CPU, FS, None, makeArrayRef(XCoreSubTypeKV, 2),
166 : XCoreProcSchedKV, XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
167 160 : nullptr, nullptr, nullptr) {}
168 :
169 0 : unsigned XCoreGenSubtargetInfo
170 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
171 0 : report_fatal_error("Expected a variant SchedClass");
172 : } // XCoreGenSubtargetInfo::resolveSchedClass
173 :
174 0 : unsigned XCoreGenSubtargetInfo
175 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
176 0 : return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
177 : } // XCoreGenSubtargetInfo::resolveVariantSchedClass
178 :
179 : } // end namespace llvm
180 :
181 : #endif // GET_SUBTARGETINFO_CTOR
182 :
183 :
184 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
185 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
186 :
187 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
188 :
189 :
190 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
191 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
192 :
193 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
194 :
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