Line data Source code
1 : //=== llvm/CodeGen/ISDOpcodes.h  CodeGen opcodes * C++ *===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //======//
9 : //
10 : // This file declares codegen opcodes and related utilities.
11 : //
12 : //======//
13 :
14 : #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 : #define LLVM_CODEGEN_ISDOPCODES_H
16 :
17 : namespace llvm {
18 :
19 : /// ISD namespace  This namespace contains an enum which represents all of the
20 : /// SelectionDAG node types and value types.
21 : ///
22 : namespace ISD {
23 :
24 : //======//
25 : /// ISD::NodeType enum  This enum defines the targetindependent operators
26 : /// for a SelectionDAG.
27 : ///
28 : /// Targets may also define targetdependent operator codes for SDNodes. For
29 : /// example, on x86, these are the enum values in the X86ISD namespace.
30 : /// Targets should aim to use targetindependent operators to model their
31 : /// instruction sets as much as possible, and only use targetdependent
32 : /// operators when they have special requirements.
33 : ///
34 : /// Finally, during and after selection proper, SNodes may use special
35 : /// operator codes that correspond directly with MachineInstr opcodes. These
36 : /// are used to represent selected instructions. See the isMachineOpcode()
37 : /// and getMachineOpcode() member functions of SDNode.
38 : ///
39 : enum NodeType {
40 : /// DELETED_NODE  This is an illegal value that is used to catch
41 : /// errors. This opcode is not a legal opcode for any node.
42 : DELETED_NODE,
43 :
44 : /// EntryToken  This is the marker used to indicate the start of a region.
45 : EntryToken,
46 :
47 : /// TokenFactor  This node takes multiple tokens as input and produces a
48 : /// single token result. This is used to represent the fact that the operand
49 : /// operators are independent of each other.
50 : TokenFactor,
51 :
52 : /// AssertSext, AssertZext  These nodes record if a register contains a
53 : /// value that has already been zero or sign extended from a narrower type.
54 : /// These nodes take two operands. The first is the node that has already
55 : /// been extended, and the second is a value type node indicating the width
56 : /// of the extension
57 : AssertSext, AssertZext,
58 :
59 : /// Various leaf nodes.
60 : BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
61 : Constant, ConstantFP,
62 : GlobalAddress, GlobalTLSAddress, FrameIndex,
63 : JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
64 :
65 : /// The address of the GOT
66 : GLOBAL_OFFSET_TABLE,
67 :
68 : /// FRAMEADDR, RETURNADDR  These nodes represent llvm.frameaddress and
69 : /// llvm.returnaddress on the DAG. These nodes take one operand, the index
70 : /// of the frame or return address to return. An index of zero corresponds
71 : /// to the current function's frame or return address, an index of one to
72 : /// the parent's frame or return address, and so on.
73 : FRAMEADDR, RETURNADDR, ADDROFRETURNADDR,
74 :
75 : /// LOCAL_RECOVER  Represents the llvm.localrecover intrinsic.
76 : /// Materializes the offset from the local object pointer of another
77 : /// function to a particular local object passed to llvm.localescape. The
78 : /// operand is the MCSymbol label used to represent this offset, since
79 : /// typically the offset is not known until after code generation of the
80 : /// parent.
81 : LOCAL_RECOVER,
82 :
83 : /// READ_REGISTER, WRITE_REGISTER  This node represents llvm.register on
84 : /// the DAG, which implements the named register global variables extension.
85 : READ_REGISTER,
86 : WRITE_REGISTER,
87 :
88 : /// FRAME_TO_ARGS_OFFSET  This node represents offset from frame pointer to
89 : /// first (possible) onstack argument. This is needed for correct stack
90 : /// adjustment during unwind.
91 : FRAME_TO_ARGS_OFFSET,
92 :
93 : /// EH_DWARF_CFA  This node represents the pointer to the DWARF Canonical
94 : /// Frame Address (CFA), generally the value of the stack pointer at the
95 : /// call site in the previous frame.
96 : EH_DWARF_CFA,
97 :
98 : /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)  This node represents
99 : /// 'eh_return' gcc dwarf builtin, which is used to return from
100 : /// exception. The general meaning is: adjust stack by OFFSET and pass
101 : /// execution to HANDLER. Many platformrelated details also :)
102 : EH_RETURN,
103 :
104 : /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
105 : /// This corresponds to the eh.sjlj.setjmp intrinsic.
106 : /// It takes an input chain and a pointer to the jump buffer as inputs
107 : /// and returns an outchain.
108 : EH_SJLJ_SETJMP,
109 :
110 : /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
111 : /// This corresponds to the eh.sjlj.longjmp intrinsic.
112 : /// It takes an input chain and a pointer to the jump buffer as inputs
113 : /// and returns an outchain.
114 : EH_SJLJ_LONGJMP,
115 :
116 : /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
117 : /// The target initializes the dispatch table here.
118 : EH_SJLJ_SETUP_DISPATCH,
119 :
120 : /// TargetConstant*  Like Constant*, but the DAG does not do any folding,
121 : /// simplification, or lowering of the constant. They are used for constants
122 : /// which are known to fit in the immediate fields of their users, or for
123 : /// carrying magic numbers which are not values which need to be
124 : /// materialized in registers.
125 : TargetConstant,
126 : TargetConstantFP,
127 :
128 : /// TargetGlobalAddress  Like GlobalAddress, but the DAG does no folding or
129 : /// anything else with this node, and this is valid in the targetspecific
130 : /// dag, turning into a GlobalAddress operand.
131 : TargetGlobalAddress,
132 : TargetGlobalTLSAddress,
133 : TargetFrameIndex,
134 : TargetJumpTable,
135 : TargetConstantPool,
136 : TargetExternalSymbol,
137 : TargetBlockAddress,
138 :
139 : MCSymbol,
140 :
141 : /// TargetIndex  Like a constant pool entry, but with completely
142 : /// targetdependent semantics. Holds target flags, a 32bit index, and a
143 : /// 64bit index. Targets can use this however they like.
144 : TargetIndex,
145 :
146 : /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
147 : /// This node represents a target intrinsic function with no side effects.
148 : /// The first operand is the ID number of the intrinsic from the
149 : /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
150 : /// node returns the result of the intrinsic.
151 : INTRINSIC_WO_CHAIN,
152 :
153 : /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
154 : /// This node represents a target intrinsic function with side effects that
155 : /// returns a result. The first operand is a chain pointer. The second is
156 : /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
157 : /// operands to the intrinsic follow. The node has two results, the result
158 : /// of the intrinsic and an output chain.
159 : INTRINSIC_W_CHAIN,
160 :
161 : /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
162 : /// This node represents a target intrinsic function with side effects that
163 : /// does not return a result. The first operand is a chain pointer. The
164 : /// second is the ID number of the intrinsic from the llvm::Intrinsic
165 : /// namespace. The operands to the intrinsic follow.
166 : INTRINSIC_VOID,
167 :
168 : /// CopyToReg  This node has three operands: a chain, a register number to
169 : /// set to this value, and a value.
170 : CopyToReg,
171 :
172 : /// CopyFromReg  This node indicates that the input value is a virtual or
173 : /// physical register that is defined outside of the scope of this
174 : /// SelectionDAG. The register is available from the RegisterSDNode object.
175 : CopyFromReg,
176 :
177 : /// UNDEF  An undefined node.
178 : UNDEF,
179 :
180 : /// EXTRACT_ELEMENT  This is used to get the lower or upper (determined by
181 : /// a Constant, which is required to be operand #1) half of the integer or
182 : /// float value specified as operand #0. This is only for use before
183 : /// legalization, for values that will be broken into multiple registers.
184 : EXTRACT_ELEMENT,
185 :
186 : /// BUILD_PAIR  This is the opposite of EXTRACT_ELEMENT in some ways.
187 : /// Given two values of the same integer value type, this produces a value
188 : /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
189 : /// legalization. The lower part of the composite value should be in
190 : /// element 0 and the upper part should be in element 1.
191 : BUILD_PAIR,
192 :
193 : /// MERGE_VALUES  This node takes multiple discrete operands and returns
194 : /// them all as its individual results. This nodes has exactly the same
195 : /// number of inputs and outputs. This node is useful for some pieces of the
196 : /// code generator that want to think about a single node with multiple
197 : /// results, not multiple nodes.
198 : MERGE_VALUES,
199 :
200 : /// Simple integer binary arithmetic operators.
201 : ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
202 :
203 : /// SMUL_LOHI/UMUL_LOHI  Multiply two integers of type iN, producing
204 : /// a signed/unsigned value of type i[2*N], and return the full value as
205 : /// two results, each of type iN.
206 : SMUL_LOHI, UMUL_LOHI,
207 :
208 : /// SDIVREM/UDIVREM  Divide two integers and produce both a quotient and
209 : /// remainder result.
210 : SDIVREM, UDIVREM,
211 :
212 : /// CARRY_FALSE  This node is used when folding other nodes,
213 : /// like ADDC/SUBC, which indicate the carry result is always false.
214 : CARRY_FALSE,
215 :
216 : /// Carrysetting nodes for multiple precision addition and subtraction.
217 : /// These nodes take two operands of the same value type, and produce two
218 : /// results. The first result is the normal add or sub result, the second
219 : /// result is the carry flag result.
220 : /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
221 : /// They are kept around for now to provide a smooth transition path
222 : /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
223 : ADDC, SUBC,
224 :
225 : /// Carryusing nodes for multiple precision addition and subtraction. These
226 : /// nodes take three operands: The first two are the normal lhs and rhs to
227 : /// the add or sub, and the third is the input carry flag. These nodes
228 : /// produce two results; the normal result of the add or sub, and the output
229 : /// carry flag. These nodes both read and write a carry flag to allow them
230 : /// to them to be chained together for add and sub of arbitrarily large
231 : /// values.
232 : ADDE, SUBE,
233 :
234 : /// Carryusing nodes for multiple precision addition and subtraction.
235 : /// These nodes take three operands: The first two are the normal lhs and
236 : /// rhs to the add or sub, and the third is a boolean indicating if there
237 : /// is an incoming carry. These nodes produce two results: the normal
238 : /// result of the add or sub, and the output carry so they can be chained
239 : /// together. The use of this opcode is preferable to adde/sube if the
240 : /// target supports it, as the carry is a regular value rather than a
241 : /// glue, which allows further optimisation.
242 : ADDCARRY, SUBCARRY,
243 :
244 : /// RESULT, BOOL = [SU]ADDO(LHS, RHS)  Overflowaware nodes for addition.
245 : /// These nodes take two operands: the normal LHS and RHS to the add. They
246 : /// produce two results: the normal result of the add, and a boolean that
247 : /// indicates if an overflow occurred (*not* a flag, because it may be store
248 : /// to memory, etc.). If the type of the boolean is not i1 then the high
249 : /// bits conform to getBooleanContents.
250 : /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
251 : SADDO, UADDO,
252 :
253 : /// Same for subtraction.
254 : SSUBO, USUBO,
255 :
256 : /// Same for multiplication.
257 : SMULO, UMULO,
258 :
259 : /// RESULT = SADDSAT(LHS, RHS)  Perform signed saturation addition on 2
260 : /// integers with the same bit width (W). If the true value of LHS + RHS
261 : /// exceeds the largest signed value that can be represented by W bits, the
262 : /// resulting value is this maximum value. Otherwise, if this value is less
263 : /// than the smallest signed value that can be represented by W bits, the
264 : /// resulting value is this minimum value.
265 : SADDSAT,
266 :
267 : /// Simple binary floating point operators.
268 : FADD, FSUB, FMUL, FDIV, FREM,
269 :
270 : /// Constrained versions of the binary floating point operators.
271 : /// These will be lowered to the simple operators before final selection.
272 : /// They are used to limit optimizations while the DAG is being
273 : /// optimized.
274 : STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
275 : STRICT_FMA,
276 :
277 : /// Constrained versions of libmequivalent floating point intrinsics.
278 : /// These will be lowered to the equivalent nonconstrained pseudoop
279 : /// (or expanded to the equivalent library call) before final selection.
280 : /// They are used to limit optimizations while the DAG is being optimized.
281 : STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
282 : STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
283 : STRICT_FRINT, STRICT_FNEARBYINT,
284 :
285 : /// FMA  Perform a * b + c with no intermediate rounding step.
286 : FMA,
287 :
288 : /// FMAD  Perform a * b + c, while getting the same result as the
289 : /// separately rounded operations.
290 : FMAD,
291 :
292 : /// FCOPYSIGN(X, Y)  Return the value of X with the sign of Y. NOTE: This
293 : /// DAG node does not require that X and Y have the same type, just that
294 : /// they are both floating point. X and the result must have the same type.
295 : /// FCOPYSIGN(f32, f64) is allowed.
296 : FCOPYSIGN,
297 :
298 : /// INT = FGETSIGN(FP)  Return the sign bit of the specified floating point
299 : /// value as an integer 0/1 value.
300 : FGETSIGN,
301 :
302 : /// Returns platform specific canonical encoding of a floating point number.
303 : FCANONICALIZE,
304 :
305 : /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...)  Return a vector with the
306 : /// specified, possibly variable, elements. The number of elements is
307 : /// required to be a power of two. The types of the operands must all be
308 : /// the same and must match the vector element type, except that integer
309 : /// types are allowed to be larger than the element type, in which case
310 : /// the operands are implicitly truncated.
311 : BUILD_VECTOR,
312 :
313 : /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX)  Returns VECTOR with the element
314 : /// at IDX replaced with VAL. If the type of VAL is larger than the vector
315 : /// element type then VAL is truncated before replacement.
316 : INSERT_VECTOR_ELT,
317 :
318 : /// EXTRACT_VECTOR_ELT(VECTOR, IDX)  Returns a single element from VECTOR
319 : /// identified by the (potentially variable) element number IDX. If the
320 : /// return type is an integer type larger than the element type of the
321 : /// vector, the result is extended to the width of the return type. In
322 : /// that case, the high bits are undefined.
323 : EXTRACT_VECTOR_ELT,
324 :
325 : /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...)  Given a number of values of
326 : /// vector type with the same length and element type, this produces a
327 : /// concatenated vector result value, with length equal to the sum of the
328 : /// lengths of the input vectors.
329 : CONCAT_VECTORS,
330 :
331 : /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX)  Returns a vector
332 : /// with VECTOR2 inserted into VECTOR1 at the (potentially
333 : /// variable) element number IDX, which must be a multiple of the
334 : /// VECTOR2 vector length. The elements of VECTOR1 starting at
335 : /// IDX are overwritten with VECTOR2. Elements IDX through
336 : /// vector_length(VECTOR2) must be valid VECTOR1 indices.
337 : INSERT_SUBVECTOR,
338 :
339 : /// EXTRACT_SUBVECTOR(VECTOR, IDX)  Returns a subvector from VECTOR (an
340 : /// vector value) starting with the element number IDX, which must be a
341 : /// constant multiple of the result vector length.
342 : EXTRACT_SUBVECTOR,
343 :
344 : /// VECTOR_SHUFFLE(VEC1, VEC2)  Returns a vector, of the same type as
345 : /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
346 : /// values that indicate which value (or undef) each result element will
347 : /// get. These constant ints are accessible through the
348 : /// ShuffleVectorSDNode class. This is quite similar to the Altivec
349 : /// 'vperm' instruction, except that the indices must be constants and are
350 : /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
351 : VECTOR_SHUFFLE,
352 :
353 : /// SCALAR_TO_VECTOR(VAL)  This represents the operation of loading a
354 : /// scalar value into element 0 of the resultant vector type. The top
355 : /// elements 1 to N1 of the Nelement vector are undefined. The type
356 : /// of the operand must match the vector element type, except when they
357 : /// are integer types. In this case the operand is allowed to be wider
358 : /// than the vector element type, and is implicitly truncated to it.
359 : SCALAR_TO_VECTOR,
360 :
361 : /// MULHU/MULHS  Multiply high  Multiply two integers of type iN,
362 : /// producing an unsigned/signed value of type i[2*N], then return the top
363 : /// part.
364 : MULHU, MULHS,
365 :
366 : /// [US]{MIN/MAX}  Binary minimum or maximum or signed or unsigned
367 : /// integers.
368 : SMIN, SMAX, UMIN, UMAX,
369 :
370 : /// Bitwise operators  logical and, logical or, logical xor.
371 : AND, OR, XOR,
372 :
373 : /// ABS  Determine the unsigned absolute value of a signed integer value of
374 : /// the same bitwidth.
375 : /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
376 : /// is performed.
377 : ABS,
378 :
379 : /// Shift and rotation operations. After legalization, the type of the
380 : /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
381 : /// the shift amount can be any type, but care must be taken to ensure it is
382 : /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
383 : /// legalization, types like i1024 can occur and i8 doesn't have enough bits
384 : /// to represent the shift amount.
385 : /// When the 1st operand is a vector, the shift amount must be in the same
386 : /// type. (TLI.getShiftAmountTy() will return the same type when the input
387 : /// type is a vector.)
388 : /// For rotates, the shift amount is treated as an unsigned amount modulo
389 : /// the element size of the first operand.
390 : SHL, SRA, SRL, ROTL, ROTR,
391 :
392 : /// Byte Swap and Counting operators.
393 : BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
394 :
395 : /// Bit counting operators with an undefined result for zero inputs.
396 : CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
397 :
398 : /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
399 : /// i1 then the high bits must conform to getBooleanContents.
400 : SELECT,
401 :
402 : /// Select with a vector condition (op #0) and two vector operands (ops #1
403 : /// and #2), returning a vector result. All vectors have the same length.
404 : /// Much like the scalar select and setcc, each bit in the condition selects
405 : /// whether the corresponding result element is taken from op #1 or op #2.
406 : /// At first, the VSELECT condition is of vXi1 type. Later, targets may
407 : /// change the condition type in order to match the VSELECT node using a
408 : /// pattern. The condition follows the BooleanContent format of the target.
409 : VSELECT,
410 :
411 : /// Select with condition operator  This selects between a true value and
412 : /// a false value (ops #2 and #3) based on the boolean result of comparing
413 : /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
414 : /// condition code in op #4, a CondCodeSDNode.
415 : SELECT_CC,
416 :
417 : /// SetCC operator  This evaluates to a true value iff the condition is
418 : /// true. If the result value type is not i1 then the high bits conform
419 : /// to getBooleanContents. The operands to this are the left and right
420 : /// operands to compare (ops #0, and #1) and the condition code to compare
421 : /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
422 : /// then the result type must also be a vector type.
423 : SETCC,
424 :
425 : /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
426 : /// op #2 is a boolean indicating if there is an incoming carry. This
427 : /// operator checks the result of "LHS  RHS  Carry", and can be used to
428 : /// compare two wide integers:
429 : /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
430 : /// Only valid for integers.
431 : SETCCCARRY,
432 :
433 : /// SHL_PARTS/SRA_PARTS/SRL_PARTS  These operators are used for expanded
434 : /// integer shift operations. The operation ordering is:
435 : /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
436 : SHL_PARTS, SRA_PARTS, SRL_PARTS,
437 :
438 : /// Conversion operators. These are all single input single output
439 : /// operations. For all of these, the result type must be strictly
440 : /// wider or narrower (depending on the operation) than the source
441 : /// type.
442 :
443 : /// SIGN_EXTEND  Used for integer types, replicating the sign bit
444 : /// into new bits.
445 : SIGN_EXTEND,
446 :
447 : /// ZERO_EXTEND  Used for integer types, zeroing the new bits.
448 : ZERO_EXTEND,
449 :
450 : /// ANY_EXTEND  Used for integer types. The high bits are undefined.
451 : ANY_EXTEND,
452 :
453 : /// TRUNCATE  Completely drop the high bits.
454 : TRUNCATE,
455 :
456 : /// [SU]INT_TO_FP  These operators convert integers (whose interpreted sign
457 : /// depends on the first letter) to floating point.
458 : SINT_TO_FP,
459 : UINT_TO_FP,
460 :
461 : /// SIGN_EXTEND_INREG  This operator atomically performs a SHL/SRA pair to
462 : /// sign extend a small value in a large integer register (e.g. sign
463 : /// extending the low 8 bits of a 32bit register to fill the top 24 bits
464 : /// with the 7th bit). The size of the smaller type is indicated by the 1th
465 : /// operand, a ValueType node.
466 : SIGN_EXTEND_INREG,
467 :
468 : /// ANY_EXTEND_VECTOR_INREG(Vector)  This operator represents an
469 : /// inregister anyextension of the low lanes of an integer vector. The
470 : /// result type must have fewer elements than the operand type, and those
471 : /// elements must be larger integer types such that the total size of the
472 : /// operand type and the result type match. Each of the low operand
473 : /// elements is anyextended into the corresponding, wider result
474 : /// elements with the high bits becoming undef.
475 : ANY_EXTEND_VECTOR_INREG,
476 :
477 : /// SIGN_EXTEND_VECTOR_INREG(Vector)  This operator represents an
478 : /// inregister signextension of the low lanes of an integer vector. The
479 : /// result type must have fewer elements than the operand type, and those
480 : /// elements must be larger integer types such that the total size of the
481 : /// operand type and the result type match. Each of the low operand
482 : /// elements is signextended into the corresponding, wider result
483 : /// elements.
484 : // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
485 : // scalars, but it also doesn't handle vectors well. Either it should be
486 : // restricted to scalars or this node (and its handling) should be merged
487 : // into it.
488 : SIGN_EXTEND_VECTOR_INREG,
489 :
490 : /// ZERO_EXTEND_VECTOR_INREG(Vector)  This operator represents an
491 : /// inregister zeroextension of the low lanes of an integer vector. The
492 : /// result type must have fewer elements than the operand type, and those
493 : /// elements must be larger integer types such that the total size of the
494 : /// operand type and the result type match. Each of the low operand
495 : /// elements is zeroextended into the corresponding, wider result
496 : /// elements.
497 : ZERO_EXTEND_VECTOR_INREG,
498 :
499 : /// FP_TO_[US]INT  Convert a floating point value to a signed or unsigned
500 : /// integer. These have the same semantics as fptosi and fptoui in IR. If
501 : /// the FP value cannot fit in the integer type, the results are undefined.
502 : FP_TO_SINT,
503 : FP_TO_UINT,
504 :
505 : /// X = FP_ROUND(Y, TRUNC)  Rounding 'Y' from a larger floating point type
506 : /// down to the precision of the destination VT. TRUNC is a flag, which is
507 : /// always an integer that is zero or one. If TRUNC is 0, this is a
508 : /// normal rounding, if it is 1, this FP_ROUND is known to not change the
509 : /// value of Y.
510 : ///
511 : /// The TRUNC = 1 case is used in cases where we know that the value will
512 : /// not be modified by the node, because Y is not using any of the extra
513 : /// precision of source type. This allows certain transformations like
514 : /// FP_EXTEND(FP_ROUND(X,1)) > X which are not safe for
515 : /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
516 : FP_ROUND,
517 :
518 : /// FLT_ROUNDS_  Returns current rounding mode:
519 : /// 1 Undefined
520 : /// 0 Round to 0
521 : /// 1 Round to nearest
522 : /// 2 Round to +inf
523 : /// 3 Round to inf
524 : FLT_ROUNDS_,
525 :
526 : /// X = FP_ROUND_INREG(Y, VT)  This operator takes an FP register, and
527 : /// rounds it to a floating point value. It then promotes it and returns it
528 : /// in a register of the same size. This operation effectively just
529 : /// discards excess precision. The type to round down to is specified by
530 : /// the VT operand, a VTSDNode.
531 : FP_ROUND_INREG,
532 :
533 : /// X = FP_EXTEND(Y)  Extend a smaller FP type into a larger FP type.
534 : FP_EXTEND,
535 :
536 : /// BITCAST  This operator converts between integer, vector and FP
537 : /// values, as if the value was stored to memory with one type and loaded
538 : /// from the same address with the other type (or equivalently for vector
539 : /// format conversions, etc). The source and result are required to have
540 : /// the same bit size (e.g. f32 <> i32). This can also be used for
541 : /// inttoint or fptofp conversions, but that is a noop, deleted by
542 : /// getNode().
543 : ///
544 : /// This operator is subtly different from the bitcast instruction from
545 : /// LLVMIR since this node may change the bits in the register. For
546 : /// example, this occurs on bigendian NEON and bigendian MSA where the
547 : /// layout of the bits in the register depends on the vector type and this
548 : /// operator acts as a shuffle operation for some vector type combinations.
549 : BITCAST,
550 :
551 : /// ADDRSPACECAST  This operator converts between pointers of different
552 : /// address spaces.
553 : ADDRSPACECAST,
554 :
555 : /// FP16_TO_FP, FP_TO_FP16  These operators are used to perform promotions
556 : /// and truncation for halfprecision (16 bit) floating numbers. These nodes
557 : /// form a semisoftened interface for dealing with f16 (as an i16), which
558 : /// is often a storageonly type but has native conversions.
559 : FP16_TO_FP, FP_TO_FP16,
560 :
561 : /// Perform various unary floatingpoint operations inspired by libm.
562 : FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW,
563 : FLOG, FLOG2, FLOG10, FEXP, FEXP2,
564 : FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
565 : /// FMINNUM/FMAXNUM  Perform floatingpoint minimum or maximum on two
566 : /// values.
567 : /// In the case where a single input is NaN, the nonNaN input is returned.
568 : ///
569 : /// The return value of (FMINNUM 0.0, 0.0) could be either 0.0 or 0.0.
570 : FMINNUM, FMAXNUM,
571 : /// FMINNAN/FMAXNAN  NaNpropagating minimum/maximum that also treat 0.0
572 : /// as less than 0.0. While FMINNUM/FMAXNUM follow IEEE 7542008 semantics,
573 : /// FMINNAN/FMAXNAN follow IEEE 7542018 draft semantics.
574 : FMINNAN, FMAXNAN,
575 :
576 : /// FSINCOS  Compute both fsin and fcos as a single operation.
577 : FSINCOS,
578 :
579 : /// LOAD and STORE have token chains as their first operand, then the same
580 : /// operands as an LLVM load/store instruction, then an offset node that
581 : /// is added / subtracted from the base pointer to form the address (for
582 : /// indexed memory ops).
583 : LOAD, STORE,
584 :
585 : /// DYNAMIC_STACKALLOC  Allocate some number of bytes on the stack aligned
586 : /// to a specified boundary. This node always has two return values: a new
587 : /// stack pointer value and a chain. The first operand is the token chain,
588 : /// the second is the number of bytes to allocate, and the third is the
589 : /// alignment boundary. The size is guaranteed to be a multiple of the
590 : /// stack alignment, and the alignment is guaranteed to be bigger than the
591 : /// stack alignment (if required) or 0 to get standard stack alignment.
592 : DYNAMIC_STACKALLOC,
593 :
594 : /// Control flow instructions. These all have token chains.
595 :
596 : /// BR  Unconditional branch. The first operand is the chain
597 : /// operand, the second is the MBB to branch to.
598 : BR,
599 :
600 : /// BRIND  Indirect branch. The first operand is the chain, the second
601 : /// is the value to branch to, which must be of the same type as the
602 : /// target's pointer type.
603 : BRIND,
604 :
605 : /// BR_JT  Jumptable branch. The first operand is the chain, the second
606 : /// is the jumptable index, the last one is the jumptable entry index.
607 : BR_JT,
608 :
609 : /// BRCOND  Conditional branch. The first operand is the chain, the
610 : /// second is the condition, the third is the block to branch to if the
611 : /// condition is true. If the type of the condition is not i1, then the
612 : /// high bits must conform to getBooleanContents.
613 : BRCOND,
614 :
615 : /// BR_CC  Conditional branch. The behavior is like that of SELECT_CC, in
616 : /// that the condition is represented as condition code, and two nodes to
617 : /// compare, rather than as a combined SetCC node. The operands in order
618 : /// are chain, cc, lhs, rhs, block to branch to if condition is true.
619 : BR_CC,
620 :
621 : /// INLINEASM  Represents an inline asm block. This node always has two
622 : /// return values: a chain and a flag result. The inputs are as follows:
623 : /// Operand #0 : Input chain.
624 : /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
625 : /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
626 : /// Operand #3 : HasSideEffect, IsAlignStack bits.
627 : /// After this, it is followed by a list of operands with this format:
628 : /// ConstantSDNode: Flags that encode whether it is a mem or not, the
629 : /// of operands that follow, etc. See InlineAsm.h.
630 : /// ... however many operands ...
631 : /// Operand #last: Optional, an incoming flag.
632 : ///
633 : /// The variable width operands are required to represent target addressing
634 : /// modes as a single "operand", even though they may have multiple
635 : /// SDOperands.
636 : INLINEASM,
637 :
638 : /// EH_LABEL  Represents a label in mid basic block used to track
639 : /// locations needed for debug and exception handling tables. These nodes
640 : /// take a chain as input and return a chain.
641 : EH_LABEL,
642 :
643 : /// ANNOTATION_LABEL  Represents a mid basic block label used by
644 : /// annotations. This should remain within the basic block and be ordered
645 : /// with respect to other call instructions, but loads and stores may float
646 : /// past it.
647 : ANNOTATION_LABEL,
648 :
649 : /// CATCHPAD  Represents a catchpad instruction.
650 : CATCHPAD,
651 :
652 : /// CATCHRET  Represents a return from a catch block funclet. Used for
653 : /// MSVC compatible exception handling. Takes a chain operand and a
654 : /// destination basic block operand.
655 : CATCHRET,
656 :
657 : /// CLEANUPRET  Represents a return from a cleanup block funclet. Used for
658 : /// MSVC compatible exception handling. Takes only a chain operand.
659 : CLEANUPRET,
660 :
661 : /// STACKSAVE  STACKSAVE has one operand, an input chain. It produces a
662 : /// value, the same type as the pointer type for the system, and an output
663 : /// chain.
664 : STACKSAVE,
665 :
666 : /// STACKRESTORE has two operands, an input chain and a pointer to restore
667 : /// to it returns an output chain.
668 : STACKRESTORE,
669 :
670 : /// CALLSEQ_START/CALLSEQ_END  These operators mark the beginning and end
671 : /// of a call sequence, and carry arbitrary information that target might
672 : /// want to know. The first operand is a chain, the rest are specified by
673 : /// the target and not touched by the DAG optimizers.
674 : /// Targets that may use stack to pass call arguments define additional
675 : /// operands:
676 : ///  size of the call frame part that must be set up within the
677 : /// CALLSEQ_START..CALLSEQ_END pair,
678 : ///  part of the call frame prepared prior to CALLSEQ_START.
679 : /// Both these parameters must be constants, their sum is the total call
680 : /// frame size.
681 : /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
682 : CALLSEQ_START, // Beginning of a call sequence
683 : CALLSEQ_END, // End of a call sequence
684 :
685 : /// VAARG  VAARG has four operands: an input chain, a pointer, a SRCVALUE,
686 : /// and the alignment. It returns a pair of values: the vaarg value and a
687 : /// new chain.
688 : VAARG,
689 :
690 : /// VACOPY  VACOPY has 5 operands: an input chain, a destination pointer,
691 : /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
692 : /// source.
693 : VACOPY,
694 :
695 : /// VAEND, VASTART  VAEND and VASTART have three operands: an input chain,
696 : /// pointer, and a SRCVALUE.
697 : VAEND, VASTART,
698 :
699 : /// SRCVALUE  This is a node type that holds a Value* that is used to
700 : /// make reference to a value in the LLVM IR.
701 : SRCVALUE,
702 :
703 : /// MDNODE_SDNODE  This is a node that holdes an MDNode*, which is used to
704 : /// reference metadata in the IR.
705 : MDNODE_SDNODE,
706 :
707 : /// PCMARKER  This corresponds to the pcmarker intrinsic.
708 : PCMARKER,
709 :
710 : /// READCYCLECOUNTER  This corresponds to the readcyclecounter intrinsic.
711 : /// It produces a chain and one i64 value. The only operand is a chain.
712 : /// If i64 is not legal, the result will be expanded into smaller values.
713 : /// Still, it returns an i64, so targets should set legality for i64.
714 : /// The result is the content of the architecturespecific cycle
715 : /// counterlike register (or other high accuracy low latency clock source).
716 : READCYCLECOUNTER,
717 :
718 : /// HANDLENODE node  Used as a handle for various purposes.
719 : HANDLENODE,
720 :
721 : /// INIT_TRAMPOLINE  This corresponds to the init_trampoline intrinsic. It
722 : /// takes as input a token chain, the pointer to the trampoline, the pointer
723 : /// to the nested function, the pointer to pass for the 'nest' parameter, a
724 : /// SRCVALUE for the trampoline and another for the nested function
725 : /// (allowing targets to access the original Function*).
726 : /// It produces a token chain as output.
727 : INIT_TRAMPOLINE,
728 :
729 : /// ADJUST_TRAMPOLINE  This corresponds to the adjust_trampoline intrinsic.
730 : /// It takes a pointer to the trampoline and produces a (possibly) new
731 : /// pointer to the same trampoline with platformspecific adjustments
732 : /// applied. The pointer it returns points to an executable block of code.
733 : ADJUST_TRAMPOLINE,
734 :
735 : /// TRAP  Trapping instruction
736 : TRAP,
737 :
738 : /// DEBUGTRAP  Trap intended to get the attention of a debugger.
739 : DEBUGTRAP,
740 :
741 : /// PREFETCH  This corresponds to a prefetch intrinsic. The first operand
742 : /// is the chain. The other operands are the address to prefetch,
743 : /// read / write specifier, locality specifier and instruction / data cache
744 : /// specifier.
745 : PREFETCH,
746 :
747 : /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
748 : /// This corresponds to the fence instruction. It takes an input chain, and
749 : /// two integer constants: an AtomicOrdering and a SynchronizationScope.
750 : ATOMIC_FENCE,
751 :
752 : /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
753 : /// This corresponds to "load atomic" instruction.
754 : ATOMIC_LOAD,
755 :
756 : /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
757 : /// This corresponds to "store atomic" instruction.
758 : ATOMIC_STORE,
759 :
760 : /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
761 : /// For doubleword atomic operations:
762 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
763 : /// swapLo, swapHi)
764 : /// This corresponds to the cmpxchg instruction.
765 : ATOMIC_CMP_SWAP,
766 :
767 : /// Val, Success, OUTCHAIN
768 : /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
769 : /// N.b. this is still a strong cmpxchg operation, so
770 : /// Success == "Val == cmp".
771 : ATOMIC_CMP_SWAP_WITH_SUCCESS,
772 :
773 : /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
774 : /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
775 : /// For doubleword atomic operations:
776 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
777 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
778 : /// These correspond to the atomicrmw instruction.
779 : ATOMIC_SWAP,
780 : ATOMIC_LOAD_ADD,
781 : ATOMIC_LOAD_SUB,
782 : ATOMIC_LOAD_AND,
783 : ATOMIC_LOAD_CLR,
784 : ATOMIC_LOAD_OR,
785 : ATOMIC_LOAD_XOR,
786 : ATOMIC_LOAD_NAND,
787 : ATOMIC_LOAD_MIN,
788 : ATOMIC_LOAD_MAX,
789 : ATOMIC_LOAD_UMIN,
790 : ATOMIC_LOAD_UMAX,
791 :
792 : // Masked load and store  consecutive vector load and store operations
793 : // with additional mask operand that prevents memory accesses to the
794 : // maskedoff lanes.
795 : //
796 : // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
797 : // OutChain = MSTORE(Value, BasePtr, Mask)
798 : MLOAD, MSTORE,
799 :
800 : // Masked gather and scatter  load and store operations for a vector of
801 : // random addresses with additional mask operand that prevents memory
802 : // accesses to the maskedoff lanes.
803 : //
804 : // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
805 : // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
806 : //
807 : // The Index operand can have more vector elements than the other operands
808 : // due to type legalization. The extra elements are ignored.
809 : MGATHER, MSCATTER,
810 :
811 : /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
812 : /// is the chain and the second operand is the alloca pointer.
813 : LIFETIME_START, LIFETIME_END,
814 :
815 : /// GC_TRANSITION_START/GC_TRANSITION_END  These operators mark the
816 : /// beginning and end of GC transition sequence, and carry arbitrary
817 : /// information that target might need for lowering. The first operand is
818 : /// a chain, the rest are specified by the target and not touched by the DAG
819 : /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
820 : /// nested.
821 : GC_TRANSITION_START,
822 : GC_TRANSITION_END,
823 :
824 : /// GET_DYNAMIC_AREA_OFFSET  get offset from native SP to the address of
825 : /// the most recent dynamic alloca. For most targets that would be 0, but
826 : /// for some others (e.g. PowerPC, PowerPC64) that would be compiletime
827 : /// known nonzero constant. The only operand here is the chain.
828 : GET_DYNAMIC_AREA_OFFSET,
829 :
830 : /// Generic reduction nodes. These nodes represent horizontal vector
831 : /// reduction operations, producing a scalar result.
832 : /// The STRICT variants perform reductions in sequential order. The first
833 : /// operand is an initial scalar accumulator value, and the second operand
834 : /// is the vector to reduce.
835 : VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
836 : /// These reductions are nonstrict, and have a single vector operand.
837 : VECREDUCE_FADD, VECREDUCE_FMUL,
838 : VECREDUCE_ADD, VECREDUCE_MUL,
839 : VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
840 : VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
841 : /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
842 : VECREDUCE_FMAX, VECREDUCE_FMIN,
843 :
844 : /// BUILTIN_OP_END  This must be the last enum value in this list.
845 : /// The targetspecific preisel opcode values start here.
846 : BUILTIN_OP_END
847 : };
848 :
849 : /// FIRST_TARGET_MEMORY_OPCODE  Targetspecific preisel operations
850 : /// which do not reference a specific memory location should be less than
851 : /// this value. Those that do must not be less than this value, and can
852 : /// be used with SelectionDAG::getMemIntrinsicNode.
853 : static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400;
854 :
855 : //======//
856 : /// MemIndexedMode enum  This enum defines the load / store indexed
857 : /// addressing modes.
858 : ///
859 : /// UNINDEXED "Normal" load / store. The effective address is already
860 : /// computed and is available in the base pointer. The offset
861 : /// operand is always undefined. In addition to producing a
862 : /// chain, an unindexed load produces one value (result of the
863 : /// load); an unindexed store does not produce a value.
864 : ///
865 : /// PRE_INC Similar to the unindexed mode where the effective address is
866 : /// PRE_DEC the value of the base pointer add / subtract the offset.
867 : /// It considers the computation as being folded into the load /
868 : /// store operation (i.e. the load / store does the address
869 : /// computation as well as performing the memory transaction).
870 : /// The base operand is always undefined. In addition to
871 : /// producing a chain, preindexed load produces two values
872 : /// (result of the load and the result of the address
873 : /// computation); a preindexed store produces one value (result
874 : /// of the address computation).
875 : ///
876 : /// POST_INC The effective address is the value of the base pointer. The
877 : /// POST_DEC value of the offset operand is then added to / subtracted
878 : /// from the base after memory transaction. In addition to
879 : /// producing a chain, postindexed load produces two values
880 : /// (the result of the load and the result of the base +/ offset
881 : /// computation); a postindexed store produces one value (the
882 : /// the result of the base +/ offset computation).
883 : enum MemIndexedMode {
884 : UNINDEXED = 0,
885 : PRE_INC,
886 : PRE_DEC,
887 : POST_INC,
888 : POST_DEC
889 : };
890 :
891 : static const int LAST_INDEXED_MODE = POST_DEC + 1;
892 :
893 : //======//
894 : /// LoadExtType enum  This enum defines the three variants of LOADEXT
895 : /// (load with extension).
896 : ///
897 : /// SEXTLOAD loads the integer operand and sign extends it to a larger
898 : /// integer result type.
899 : /// ZEXTLOAD loads the integer operand and zero extends it to a larger
900 : /// integer result type.
901 : /// EXTLOAD is used for two things: floating point extending loads and
902 : /// integer extending loads [the top bits are undefined].
903 : enum LoadExtType {
904 : NON_EXTLOAD = 0,
905 : EXTLOAD,
906 : SEXTLOAD,
907 : ZEXTLOAD
908 : };
909 :
910 : static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
911 :
912 : NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
913 :
914 : //======//
915 : /// ISD::CondCode enum  These are ordered carefully to make the bitfields
916 : /// below work out, when considering SETFALSE (something that never exists
917 : /// dynamically) as 0. "U" > Unsigned (for integer operands) or Unordered
918 : /// (for floating point), "L" > Less than, "G" > Greater than, "E" > Equal
919 : /// to. If the "N" column is 1, the result of the comparison is undefined if
920 : /// the input is a NAN.
921 : ///
922 : /// All of these (except for the 'always folded ops') should be handled for
923 : /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
924 : /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
925 : ///
926 : /// Note that these are laid out in a specific order to allow bittwiddling
927 : /// to transform conditions.
928 : enum CondCode {
929 : // Opcode N U L G E Intuitive operation
930 : SETFALSE, // 0 0 0 0 Always false (always folded)
931 : SETOEQ, // 0 0 0 1 True if ordered and equal
932 : SETOGT, // 0 0 1 0 True if ordered and greater than
933 : SETOGE, // 0 0 1 1 True if ordered and greater than or equal
934 : SETOLT, // 0 1 0 0 True if ordered and less than
935 : SETOLE, // 0 1 0 1 True if ordered and less than or equal
936 : SETONE, // 0 1 1 0 True if ordered and operands are unequal
937 : SETO, // 0 1 1 1 True if ordered (no nans)
938 : SETUO, // 1 0 0 0 True if unordered: isnan(X)  isnan(Y)
939 : SETUEQ, // 1 0 0 1 True if unordered or equal
940 : SETUGT, // 1 0 1 0 True if unordered or greater than
941 : SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
942 : SETULT, // 1 1 0 0 True if unordered or less than
943 : SETULE, // 1 1 0 1 True if unordered, less than, or equal
944 : SETUNE, // 1 1 1 0 True if unordered or not equal
945 : SETTRUE, // 1 1 1 1 Always true (always folded)
946 : // Don't care operations: undefined if the input is a nan.
947 : SETFALSE2, // 1 X 0 0 0 Always false (always folded)
948 : SETEQ, // 1 X 0 0 1 True if equal
949 : SETGT, // 1 X 0 1 0 True if greater than
950 : SETGE, // 1 X 0 1 1 True if greater than or equal
951 : SETLT, // 1 X 1 0 0 True if less than
952 : SETLE, // 1 X 1 0 1 True if less than or equal
953 : SETNE, // 1 X 1 1 0 True if not equal
954 : SETTRUE2, // 1 X 1 1 1 Always true (always folded)
955 :
956 : SETCC_INVALID // Marker value.
957 : };
958 :
959 : /// Return true if this is a setcc instruction that performs a signed
960 : /// comparison when used with integer operands.
961 : inline bool isSignedIntSetCC(CondCode Code) {
962 387303 : return Code == SETGT  Code == SETGE  Code == SETLT  Code == SETLE;
963 : }
964 :
965 : /// Return true if this is a setcc instruction that performs an unsigned
966 : /// comparison when used with integer operands.
967 : inline bool isUnsignedIntSetCC(CondCode Code) {
968 5683 : return Code == SETUGT  Code == SETUGE  Code == SETULT  Code == SETULE;
969 : }
970 :
971 : /// Return true if the specified condition returns true if the two operands to
972 : /// the condition are equal. Note that if one of the two operands is a NaN,
973 : /// this value is meaningless.
974 : inline bool isTrueWhenEqual(CondCode Cond) {
975 1044 : return ((int)Cond & 1) != 0;
976 : }
977 :
978 : /// This function returns 0 if the condition is always false if an operand is
979 : /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
980 : /// the condition is undefined if the operand is a NaN.
981 : inline unsigned getUnorderedFlavor(CondCode Cond) {
982 936 : return ((int)Cond >> 3) & 3;
983 : }
984 :
985 : /// Return the operation corresponding to !(X op Y), where 'op' is a valid
986 : /// SetCC operation.
987 : CondCode getSetCCInverse(CondCode Operation, bool isInteger);
988 :
989 : /// Return the operation corresponding to (Y op X) when given the operation
990 : /// for (X op Y).
991 : CondCode getSetCCSwappedOperands(CondCode Operation);
992 :
993 : /// Return the result of a logical OR between different comparisons of
994 : /// identical values: ((X op1 Y)  (X op2 Y)). This function returns
995 : /// SETCC_INVALID if it is not possible to represent the resultant comparison.
996 : CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
997 :
998 : /// Return the result of a logical AND between different comparisons of
999 : /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1000 : /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1001 : CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
1002 :
1003 : } // end llvm::ISD namespace
1004 :
1005 : } // end llvm namespace
1006 :
1007 : #endif
