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1 : //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains the declaration of the MachineOperand class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
15 : #define LLVM_CODEGEN_MACHINEOPERAND_H
16 :
17 : #include "llvm/ADT/DenseMap.h"
18 : #include "llvm/IR/Intrinsics.h"
19 : #include "llvm/Support/DataTypes.h"
20 : #include "llvm/Support/LowLevelTypeImpl.h"
21 : #include <cassert>
22 :
23 : namespace llvm {
24 :
25 : class BlockAddress;
26 : class ConstantFP;
27 : class ConstantInt;
28 : class GlobalValue;
29 : class MachineBasicBlock;
30 : class MachineInstr;
31 : class MachineRegisterInfo;
32 : class MCCFIInstruction;
33 : class MDNode;
34 : class ModuleSlotTracker;
35 : class TargetMachine;
36 : class TargetIntrinsicInfo;
37 : class TargetRegisterInfo;
38 : class hash_code;
39 : class raw_ostream;
40 : class MCSymbol;
41 :
42 : /// MachineOperand class - Representation of each machine instruction operand.
43 : ///
44 : /// This class isn't a POD type because it has a private constructor, but its
45 : /// destructor must be trivial. Functions like MachineInstr::addOperand(),
46 : /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47 : /// not having to call the MachineOperand destructor.
48 : ///
49 : class MachineOperand {
50 : public:
51 : enum MachineOperandType : unsigned char {
52 : MO_Register, ///< Register operand.
53 : MO_Immediate, ///< Immediate operand
54 : MO_CImmediate, ///< Immediate >64bit operand
55 : MO_FPImmediate, ///< Floating-point immediate operand
56 : MO_MachineBasicBlock, ///< MachineBasicBlock reference
57 : MO_FrameIndex, ///< Abstract Stack Frame Index
58 : MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59 : MO_TargetIndex, ///< Target-dependent index+offset operand.
60 : MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
61 : MO_ExternalSymbol, ///< Name of external global symbol
62 : MO_GlobalAddress, ///< Address of a global value
63 : MO_BlockAddress, ///< Address of a basic block
64 : MO_RegisterMask, ///< Mask of preserved registers.
65 : MO_RegisterLiveOut, ///< Mask of live-out registers.
66 : MO_Metadata, ///< Metadata reference (for debug info)
67 : MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
68 : MO_CFIIndex, ///< MCCFIInstruction index.
69 : MO_IntrinsicID, ///< Intrinsic ID for ISel
70 : MO_Predicate, ///< Generic predicate for ISel
71 : MO_Last = MO_Predicate,
72 : };
73 :
74 : private:
75 : /// OpKind - Specify what kind of operand this is. This discriminates the
76 : /// union.
77 : unsigned OpKind : 8;
78 :
79 : /// Subregister number for MO_Register. A value of 0 indicates the
80 : /// MO_Register has no subReg.
81 : ///
82 : /// For all other kinds of operands, this field holds target-specific flags.
83 : unsigned SubReg_TargetFlags : 12;
84 :
85 : /// TiedTo - Non-zero when this register operand is tied to another register
86 : /// operand. The encoding of this field is described in the block comment
87 : /// before MachineInstr::tieOperands().
88 : unsigned TiedTo : 4;
89 :
90 : /// IsDef - True if this is a def, false if this is a use of the register.
91 : /// This is only valid on register operands.
92 : ///
93 : unsigned IsDef : 1;
94 :
95 : /// IsImp - True if this is an implicit def or use, false if it is explicit.
96 : /// This is only valid on register opderands.
97 : ///
98 : unsigned IsImp : 1;
99 :
100 : /// IsDeadOrKill
101 : /// For uses: IsKill - True if this instruction is the last use of the
102 : /// register on this path through the function.
103 : /// For defs: IsDead - True if this register is never used by a subsequent
104 : /// instruction.
105 : /// This is only valid on register operands.
106 : unsigned IsDeadOrKill : 1;
107 :
108 : /// See isRenamable().
109 : unsigned IsRenamable : 1;
110 :
111 : /// IsUndef - True if this register operand reads an "undef" value, i.e. the
112 : /// read value doesn't matter. This flag can be set on both use and def
113 : /// operands. On a sub-register def operand, it refers to the part of the
114 : /// register that isn't written. On a full-register def operand, it is a
115 : /// noop. See readsReg().
116 : ///
117 : /// This is only valid on registers.
118 : ///
119 : /// Note that an instruction may have multiple <undef> operands referring to
120 : /// the same register. In that case, the instruction may depend on those
121 : /// operands reading the same dont-care value. For example:
122 : ///
123 : /// %1 = XOR undef %2, undef %2
124 : ///
125 : /// Any register can be used for %2, and its value doesn't matter, but
126 : /// the two operands must be the same register.
127 : ///
128 : unsigned IsUndef : 1;
129 :
130 : /// IsInternalRead - True if this operand reads a value that was defined
131 : /// inside the same instruction or bundle. This flag can be set on both use
132 : /// and def operands. On a sub-register def operand, it refers to the part
133 : /// of the register that isn't written. On a full-register def operand, it
134 : /// is a noop.
135 : ///
136 : /// When this flag is set, the instruction bundle must contain at least one
137 : /// other def of the register. If multiple instructions in the bundle define
138 : /// the register, the meaning is target-defined.
139 : unsigned IsInternalRead : 1;
140 :
141 : /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
142 : /// by the MachineInstr before all input registers are read. This is used to
143 : /// model the GCC inline asm '&' constraint modifier.
144 : unsigned IsEarlyClobber : 1;
145 :
146 : /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
147 : /// not a real instruction. Such uses should be ignored during codegen.
148 : unsigned IsDebug : 1;
149 :
150 : /// SmallContents - This really should be part of the Contents union, but
151 : /// lives out here so we can get a better packed struct.
152 : /// MO_Register: Register number.
153 : /// OffsetedInfo: Low bits of offset.
154 : union {
155 : unsigned RegNo; // For MO_Register.
156 : unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
157 : } SmallContents;
158 :
159 : /// ParentMI - This is the instruction that this operand is embedded into.
160 : /// This is valid for all operand types, when the operand is in an instr.
161 : MachineInstr *ParentMI;
162 :
163 : /// Contents union - This contains the payload for the various operand types.
164 : union {
165 : MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
166 : const ConstantFP *CFP; // For MO_FPImmediate.
167 : const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
168 : int64_t ImmVal; // For MO_Immediate.
169 : const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
170 : const MDNode *MD; // For MO_Metadata.
171 : MCSymbol *Sym; // For MO_MCSymbol.
172 : unsigned CFIIndex; // For MO_CFI.
173 : Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
174 : unsigned Pred; // For MO_Predicate
175 :
176 : struct { // For MO_Register.
177 : // Register number is in SmallContents.RegNo.
178 : MachineOperand *Prev; // Access list for register. See MRI.
179 : MachineOperand *Next;
180 : } Reg;
181 :
182 : /// OffsetedInfo - This struct contains the offset and an object identifier.
183 : /// this represent the object as with an optional offset from it.
184 : struct {
185 : union {
186 : int Index; // For MO_*Index - The index itself.
187 : const char *SymbolName; // For MO_ExternalSymbol.
188 : const GlobalValue *GV; // For MO_GlobalAddress.
189 : const BlockAddress *BA; // For MO_BlockAddress.
190 : } Val;
191 : // Low bits of offset are in SmallContents.OffsetLo.
192 : int OffsetHi; // An offset from the object, high 32 bits.
193 : } OffsetedInfo;
194 : } Contents;
195 :
196 : explicit MachineOperand(MachineOperandType K)
197 241700088 : : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
198 : // Assert that the layout is what we expect. It's easy to grow this object.
199 : static_assert(alignof(MachineOperand) <= alignof(int64_t),
200 : "MachineOperand shouldn't be more than 8 byte aligned");
201 : static_assert(sizeof(Contents) <= 2 * sizeof(void *),
202 : "Contents should be at most two pointers");
203 : static_assert(sizeof(MachineOperand) <=
204 : alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
205 : 3 * sizeof(void *)),
206 : "MachineOperand too big. Should be Kind, SmallContents, "
207 : "ParentMI, and Contents");
208 : }
209 :
210 : public:
211 : /// getType - Returns the MachineOperandType for this operand.
212 : ///
213 336062025 : MachineOperandType getType() const { return (MachineOperandType)OpKind; }
214 :
215 : unsigned getTargetFlags() const {
216 66344878 : return isReg() ? 0 : SubReg_TargetFlags;
217 : }
218 : void setTargetFlags(unsigned F) {
219 : assert(!isReg() && "Register operands can't have target flags");
220 8305073 : SubReg_TargetFlags = F;
221 : assert(SubReg_TargetFlags == F && "Target flags out of range");
222 : }
223 : void addTargetFlag(unsigned F) {
224 : assert(!isReg() && "Register operands can't have target flags");
225 1 : SubReg_TargetFlags |= F;
226 : assert((SubReg_TargetFlags & F) && "Target flags out of range");
227 : }
228 :
229 :
230 : /// getParent - Return the instruction that this operand belongs to.
231 : ///
232 0 : MachineInstr *getParent() { return ParentMI; }
233 0 : const MachineInstr *getParent() const { return ParentMI; }
234 :
235 : /// clearParent - Reset the parent pointer.
236 : ///
237 : /// The MachineOperand copy constructor also copies ParentMI, expecting the
238 : /// original to be deleted. If a MachineOperand is ever stored outside a
239 : /// MachineInstr, the parent pointer must be cleared.
240 : ///
241 : /// Never call clearParent() on an operand in a MachineInstr.
242 : ///
243 101120 : void clearParent() { ParentMI = nullptr; }
244 :
245 : /// Print a subreg index operand.
246 : /// MO_Immediate operands can also be subreg idices. If it's the case, the
247 : /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
248 : /// called to check this.
249 : static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
250 : const TargetRegisterInfo *TRI);
251 :
252 : /// Print operand target flags.
253 : static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
254 :
255 : /// Print a MCSymbol as an operand.
256 : static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
257 :
258 : /// Print a stack object reference.
259 : static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
260 : bool IsFixed, StringRef Name);
261 :
262 : /// Print the offset with explicit +/- signs.
263 : static void printOperandOffset(raw_ostream &OS, int64_t Offset);
264 :
265 : /// Print an IRSlotNumber.
266 : static void printIRSlotNumber(raw_ostream &OS, int Slot);
267 :
268 : /// Print the MachineOperand to \p os.
269 : /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
270 : /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
271 : /// function will try to pick it up from the parent.
272 : void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
273 : const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
274 :
275 : /// More complex way of printing a MachineOperand.
276 : /// \param TypeToPrint specifies the generic type to be printed on uses and
277 : /// defs. It can be determined using MachineInstr::getTypeToPrint.
278 : /// \param PrintDef - whether we want to print `def` on an operand which
279 : /// isDef. Sometimes, if the operand is printed before '=', we don't print
280 : /// `def`.
281 : /// \param IsStandalone - whether we want a verbose output of the MO. This
282 : /// prints extra information that can be easily inferred when printing the
283 : /// whole function, but not when printing only a fragment of it.
284 : /// \param ShouldPrintRegisterTies - whether we want to print register ties.
285 : /// Sometimes they are easily determined by the instruction's descriptor
286 : /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
287 : /// \param TiedOperandIdx - if we need to print register ties this needs to
288 : /// provide the index of the tied register. If not, it will be ignored.
289 : /// \param TRI - provide more target-specific information to the printer.
290 : /// Unlike the previous function, this one will not try and get the
291 : /// information from it's parent.
292 : /// \param IntrinsicInfo - same as \p TRI.
293 : void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
294 : bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
295 : unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
296 : const TargetIntrinsicInfo *IntrinsicInfo) const;
297 :
298 : /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
299 : /// type to be printed the same way the full version of print(...) does it.
300 : void print(raw_ostream &os, LLT TypeToPrint,
301 : const TargetRegisterInfo *TRI = nullptr,
302 : const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
303 :
304 : void dump() const;
305 :
306 : //===--------------------------------------------------------------------===//
307 : // Accessors that tell you what kind of MachineOperand you're looking at.
308 : //===--------------------------------------------------------------------===//
309 :
310 : /// isReg - Tests if this is a MO_Register operand.
311 2377225176 : bool isReg() const { return OpKind == MO_Register; }
312 : /// isImm - Tests if this is a MO_Immediate operand.
313 34589101 : bool isImm() const { return OpKind == MO_Immediate; }
314 : /// isCImm - Test if this is a MO_CImmediate operand.
315 490 : bool isCImm() const { return OpKind == MO_CImmediate; }
316 : /// isFPImm - Tests if this is a MO_FPImmediate operand.
317 40731748 : bool isFPImm() const { return OpKind == MO_FPImmediate; }
318 : /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
319 722647 : bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
320 : /// isFI - Tests if this is a MO_FrameIndex operand.
321 45945435 : bool isFI() const { return OpKind == MO_FrameIndex; }
322 : /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
323 850014 : bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
324 : /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
325 2 : bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
326 : /// isJTI - Tests if this is a MO_JumpTableIndex operand.
327 11363572 : bool isJTI() const { return OpKind == MO_JumpTableIndex; }
328 : /// isGlobal - Tests if this is a MO_GlobalAddress operand.
329 18489219 : bool isGlobal() const { return OpKind == MO_GlobalAddress; }
330 : /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
331 403052 : bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
332 : /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
333 0 : bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
334 : /// isRegMask - Tests if this is a MO_RegisterMask operand.
335 328701414 : bool isRegMask() const { return OpKind == MO_RegisterMask; }
336 : /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
337 : bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
338 : /// isMetadata - Tests if this is a MO_Metadata operand.
339 306570 : bool isMetadata() const { return OpKind == MO_Metadata; }
340 0 : bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
341 : bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
342 564 : bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
343 : bool isPredicate() const { return OpKind == MO_Predicate; }
344 : //===--------------------------------------------------------------------===//
345 : // Accessors for Register Operands
346 : //===--------------------------------------------------------------------===//
347 :
348 : /// getReg - Returns the register number.
349 0 : unsigned getReg() const {
350 : assert(isReg() && "This is not a register operand!");
351 0 : return SmallContents.RegNo;
352 : }
353 :
354 : unsigned getSubReg() const {
355 : assert(isReg() && "Wrong MachineOperand accessor");
356 193288663 : return SubReg_TargetFlags;
357 : }
358 :
359 : bool isUse() const {
360 : assert(isReg() && "Wrong MachineOperand accessor");
361 663767097 : return !IsDef;
362 : }
363 :
364 : bool isDef() const {
365 : assert(isReg() && "Wrong MachineOperand accessor");
366 874939981 : return IsDef;
367 : }
368 :
369 : bool isImplicit() const {
370 : assert(isReg() && "Wrong MachineOperand accessor");
371 491106077 : return IsImp;
372 : }
373 :
374 : bool isDead() const {
375 : assert(isReg() && "Wrong MachineOperand accessor");
376 103101446 : return IsDeadOrKill & IsDef;
377 : }
378 :
379 : bool isKill() const {
380 : assert(isReg() && "Wrong MachineOperand accessor");
381 107047877 : return IsDeadOrKill & !IsDef;
382 : }
383 :
384 : bool isUndef() const {
385 : assert(isReg() && "Wrong MachineOperand accessor");
386 106995216 : return IsUndef;
387 : }
388 :
389 : /// isRenamable - Returns true if this register may be renamed, i.e. it does
390 : /// not generate a value that is somehow read in a way that is not represented
391 : /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
392 : /// valid on physical register operands. Virtual registers are assumed to
393 : /// always be renamable regardless of the value of this field.
394 : ///
395 : /// Operands that are renamable can freely be changed to any other register
396 : /// that is a member of the register class returned by
397 : /// MI->getRegClassConstraint().
398 : ///
399 : /// isRenamable can return false for several different reasons:
400 : ///
401 : /// - ABI constraints (since liveness is not always precisely modeled). We
402 : /// conservatively handle these cases by setting all physical register
403 : /// operands that didn’t start out as virtual regs to not be renamable.
404 : /// Also any physical register operands created after register allocation or
405 : /// whose register is changed after register allocation will not be
406 : /// renamable. This state is tracked in the MachineOperand::IsRenamable
407 : /// bit.
408 : ///
409 : /// - Opcode/target constraints: for opcodes that have complex register class
410 : /// requirements (e.g. that depend on other operands/instructions), we set
411 : /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
412 : /// description. Operands belonging to instructions with opcodes that are
413 : /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
414 : /// isRenamable(). Additionally, the AllowRegisterRenaming target property
415 : /// prevents any operands from being marked renamable for targets that don't
416 : /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
417 : /// values.
418 : bool isRenamable() const;
419 :
420 : bool isInternalRead() const {
421 : assert(isReg() && "Wrong MachineOperand accessor");
422 71832704 : return IsInternalRead;
423 : }
424 :
425 : bool isEarlyClobber() const {
426 : assert(isReg() && "Wrong MachineOperand accessor");
427 96602012 : return IsEarlyClobber;
428 : }
429 :
430 : bool isTied() const {
431 : assert(isReg() && "Wrong MachineOperand accessor");
432 222541008 : return TiedTo;
433 : }
434 :
435 : bool isDebug() const {
436 : assert(isReg() && "Wrong MachineOperand accessor");
437 62081638 : return IsDebug;
438 : }
439 :
440 : /// readsReg - Returns true if this operand reads the previous value of its
441 : /// register. A use operand with the <undef> flag set doesn't read its
442 : /// register. A sub-register def implicitly reads the other parts of the
443 : /// register being redefined unless the <undef> flag is set.
444 : ///
445 : /// This refers to reading the register value from before the current
446 : /// instruction or bundle. Internal bundle reads are not included.
447 : bool readsReg() const {
448 : assert(isReg() && "Wrong MachineOperand accessor");
449 128779326 : return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
450 : }
451 :
452 : //===--------------------------------------------------------------------===//
453 : // Mutators for Register Operands
454 : //===--------------------------------------------------------------------===//
455 :
456 : /// Change the register this operand corresponds to.
457 : ///
458 : void setReg(unsigned Reg);
459 :
460 : void setSubReg(unsigned subReg) {
461 : assert(isReg() && "Wrong MachineOperand mutator");
462 123105468 : SubReg_TargetFlags = subReg;
463 : assert(SubReg_TargetFlags == subReg && "SubReg out of range");
464 : }
465 :
466 : /// substVirtReg - Substitute the current register with the virtual
467 : /// subregister Reg:SubReg. Take any existing SubReg index into account,
468 : /// using TargetRegisterInfo to compose the subreg indices if necessary.
469 : /// Reg must be a virtual register, SubIdx can be 0.
470 : ///
471 : void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
472 :
473 : /// substPhysReg - Substitute the current register with the physical register
474 : /// Reg, taking any existing SubReg into account. For instance,
475 : /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
476 : ///
477 : void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
478 :
479 88957 : void setIsUse(bool Val = true) { setIsDef(!Val); }
480 :
481 : /// Change a def to a use, or a use to a def.
482 : void setIsDef(bool Val = true);
483 :
484 : void setImplicit(bool Val = true) {
485 : assert(isReg() && "Wrong MachineOperand mutator");
486 1517 : IsImp = Val;
487 : }
488 :
489 : void setIsKill(bool Val = true) {
490 : assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
491 : assert((!Val || !isDebug()) && "Marking a debug operation as kill");
492 49202335 : IsDeadOrKill = Val;
493 : }
494 :
495 : void setIsDead(bool Val = true) {
496 : assert(isReg() && IsDef && "Wrong MachineOperand mutator");
497 9425312 : IsDeadOrKill = Val;
498 : }
499 :
500 : void setIsUndef(bool Val = true) {
501 : assert(isReg() && "Wrong MachineOperand mutator");
502 1905522 : IsUndef = Val;
503 : }
504 :
505 : void setIsRenamable(bool Val = true);
506 :
507 : void setIsInternalRead(bool Val = true) {
508 : assert(isReg() && "Wrong MachineOperand mutator");
509 1246818 : IsInternalRead = Val;
510 : }
511 :
512 : void setIsEarlyClobber(bool Val = true) {
513 : assert(isReg() && IsDef && "Wrong MachineOperand mutator");
514 6455 : IsEarlyClobber = Val;
515 : }
516 :
517 : void setIsDebug(bool Val = true) {
518 : assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
519 548 : IsDebug = Val;
520 : }
521 :
522 : //===--------------------------------------------------------------------===//
523 : // Accessors for various operand types.
524 : //===--------------------------------------------------------------------===//
525 :
526 0 : int64_t getImm() const {
527 : assert(isImm() && "Wrong MachineOperand accessor");
528 0 : return Contents.ImmVal;
529 : }
530 :
531 0 : const ConstantInt *getCImm() const {
532 : assert(isCImm() && "Wrong MachineOperand accessor");
533 0 : return Contents.CI;
534 : }
535 :
536 0 : const ConstantFP *getFPImm() const {
537 : assert(isFPImm() && "Wrong MachineOperand accessor");
538 0 : return Contents.CFP;
539 : }
540 :
541 0 : MachineBasicBlock *getMBB() const {
542 : assert(isMBB() && "Wrong MachineOperand accessor");
543 0 : return Contents.MBB;
544 : }
545 :
546 0 : int getIndex() const {
547 : assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
548 : "Wrong MachineOperand accessor");
549 0 : return Contents.OffsetedInfo.Val.Index;
550 : }
551 :
552 0 : const GlobalValue *getGlobal() const {
553 : assert(isGlobal() && "Wrong MachineOperand accessor");
554 0 : return Contents.OffsetedInfo.Val.GV;
555 : }
556 :
557 0 : const BlockAddress *getBlockAddress() const {
558 : assert(isBlockAddress() && "Wrong MachineOperand accessor");
559 0 : return Contents.OffsetedInfo.Val.BA;
560 : }
561 :
562 0 : MCSymbol *getMCSymbol() const {
563 : assert(isMCSymbol() && "Wrong MachineOperand accessor");
564 0 : return Contents.Sym;
565 : }
566 :
567 0 : unsigned getCFIIndex() const {
568 : assert(isCFIIndex() && "Wrong MachineOperand accessor");
569 0 : return Contents.CFIIndex;
570 : }
571 :
572 0 : Intrinsic::ID getIntrinsicID() const {
573 : assert(isIntrinsicID() && "Wrong MachineOperand accessor");
574 0 : return Contents.IntrinsicID;
575 : }
576 :
577 0 : unsigned getPredicate() const {
578 : assert(isPredicate() && "Wrong MachineOperand accessor");
579 0 : return Contents.Pred;
580 : }
581 :
582 : /// Return the offset from the symbol in this operand. This always returns 0
583 : /// for ExternalSymbol operands.
584 0 : int64_t getOffset() const {
585 : assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
586 : isTargetIndex() || isBlockAddress()) &&
587 : "Wrong MachineOperand accessor");
588 8565432 : return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
589 8564802 : SmallContents.OffsetLo;
590 : }
591 :
592 0 : const char *getSymbolName() const {
593 : assert(isSymbol() && "Wrong MachineOperand accessor");
594 0 : return Contents.OffsetedInfo.Val.SymbolName;
595 : }
596 :
597 : /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
598 : /// It is sometimes necessary to detach the register mask pointer from its
599 : /// machine operand. This static method can be used for such detached bit
600 : /// mask pointers.
601 : static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
602 : // See TargetRegisterInfo.h.
603 : assert(PhysReg < (1u << 30) && "Not a physical register");
604 40999881 : return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
605 : }
606 :
607 : /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
608 : bool clobbersPhysReg(unsigned PhysReg) const {
609 39031234 : return clobbersPhysReg(getRegMask(), PhysReg);
610 : }
611 :
612 : /// getRegMask - Returns a bit mask of registers preserved by this RegMask
613 : /// operand.
614 0 : const uint32_t *getRegMask() const {
615 : assert(isRegMask() && "Wrong MachineOperand accessor");
616 0 : return Contents.RegMask;
617 : }
618 :
619 : /// Returns number of elements needed for a regmask array.
620 : static unsigned getRegMaskSize(unsigned NumRegs) {
621 19784 : return (NumRegs + 31) / 32;
622 : }
623 :
624 : /// getRegLiveOut - Returns a bit mask of live-out registers.
625 0 : const uint32_t *getRegLiveOut() const {
626 : assert(isRegLiveOut() && "Wrong MachineOperand accessor");
627 0 : return Contents.RegMask;
628 : }
629 :
630 0 : const MDNode *getMetadata() const {
631 : assert(isMetadata() && "Wrong MachineOperand accessor");
632 0 : return Contents.MD;
633 : }
634 :
635 : //===--------------------------------------------------------------------===//
636 : // Mutators for various operand types.
637 : //===--------------------------------------------------------------------===//
638 :
639 0 : void setImm(int64_t immVal) {
640 : assert(isImm() && "Wrong MachineOperand mutator");
641 59643242 : Contents.ImmVal = immVal;
642 0 : }
643 :
644 0 : void setCImm(const ConstantInt *CI) {
645 : assert(isCImm() && "Wrong MachineOperand mutator");
646 56 : Contents.CI = CI;
647 0 : }
648 :
649 0 : void setFPImm(const ConstantFP *CFP) {
650 : assert(isFPImm() && "Wrong MachineOperand mutator");
651 1 : Contents.CFP = CFP;
652 0 : }
653 :
654 0 : void setOffset(int64_t Offset) {
655 : assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
656 : isTargetIndex() || isBlockAddress()) &&
657 : "Wrong MachineOperand mutator");
658 5034748 : SmallContents.OffsetLo = unsigned(Offset);
659 5034743 : Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
660 0 : }
661 :
662 0 : void setIndex(int Idx) {
663 : assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
664 : "Wrong MachineOperand mutator");
665 19501907 : Contents.OffsetedInfo.Val.Index = Idx;
666 0 : }
667 :
668 0 : void setMetadata(const MDNode *MD) {
669 : assert(isMetadata() && "Wrong MachineOperand mutator");
670 2 : Contents.MD = MD;
671 0 : }
672 :
673 0 : void setMBB(MachineBasicBlock *MBB) {
674 : assert(isMBB() && "Wrong MachineOperand mutator");
675 3365314 : Contents.MBB = MBB;
676 0 : }
677 :
678 : /// Sets value of register mask operand referencing Mask. The
679 : /// operand does not take ownership of the memory referenced by Mask, it must
680 : /// remain valid for the lifetime of the operand. See CreateRegMask().
681 : /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
682 0 : void setRegMask(const uint32_t *RegMaskPtr) {
683 : assert(isRegMask() && "Wrong MachineOperand mutator");
684 0 : Contents.RegMask = RegMaskPtr;
685 0 : }
686 :
687 : //===--------------------------------------------------------------------===//
688 : // Other methods.
689 : //===--------------------------------------------------------------------===//
690 :
691 : /// Returns true if this operand is identical to the specified operand except
692 : /// for liveness related flags (isKill, isUndef and isDead). Note that this
693 : /// should stay in sync with the hash_value overload below.
694 : bool isIdenticalTo(const MachineOperand &Other) const;
695 :
696 : /// MachineOperand hash_value overload.
697 : ///
698 : /// Note that this includes the same information in the hash that
699 : /// isIdenticalTo uses for comparison. It is thus suited for use in hash
700 : /// tables which use that function for equality comparisons only. This must
701 : /// stay exactly in sync with isIdenticalTo above.
702 : friend hash_code hash_value(const MachineOperand &MO);
703 :
704 : /// ChangeToImmediate - Replace this operand with a new immediate operand of
705 : /// the specified value. If an operand is known to be an immediate already,
706 : /// the setImm method should be used.
707 : void ChangeToImmediate(int64_t ImmVal);
708 :
709 : /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
710 : /// of the specified value. If an operand is known to be an FP immediate
711 : /// already, the setFPImm method should be used.
712 : void ChangeToFPImmediate(const ConstantFP *FPImm);
713 :
714 : /// ChangeToES - Replace this operand with a new external symbol operand.
715 : void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
716 :
717 : /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
718 : void ChangeToMCSymbol(MCSymbol *Sym);
719 :
720 : /// Replace this operand with a frame index.
721 : void ChangeToFrameIndex(int Idx);
722 :
723 : /// Replace this operand with a target index.
724 : void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
725 : unsigned char TargetFlags = 0);
726 :
727 : /// ChangeToRegister - Replace this operand with a new register operand of
728 : /// the specified value. If an operand is known to be an register already,
729 : /// the setReg method should be used.
730 : void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
731 : bool isKill = false, bool isDead = false,
732 : bool isUndef = false, bool isDebug = false);
733 :
734 : //===--------------------------------------------------------------------===//
735 : // Construction methods.
736 : //===--------------------------------------------------------------------===//
737 :
738 : static MachineOperand CreateImm(int64_t Val) {
739 : MachineOperand Op(MachineOperand::MO_Immediate);
740 : Op.setImm(Val);
741 : return Op;
742 : }
743 :
744 : static MachineOperand CreateCImm(const ConstantInt *CI) {
745 : MachineOperand Op(MachineOperand::MO_CImmediate);
746 1440 : Op.Contents.CI = CI;
747 : return Op;
748 : }
749 :
750 : static MachineOperand CreateFPImm(const ConstantFP *CFP) {
751 : MachineOperand Op(MachineOperand::MO_FPImmediate);
752 363 : Op.Contents.CFP = CFP;
753 : return Op;
754 : }
755 :
756 : static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
757 : bool isKill = false, bool isDead = false,
758 : bool isUndef = false,
759 : bool isEarlyClobber = false,
760 : unsigned SubReg = 0, bool isDebug = false,
761 : bool isInternalRead = false,
762 : bool isRenamable = false) {
763 : assert(!(isDead && !isDef) && "Dead flag on non-def");
764 : assert(!(isKill && isDef) && "Kill flag on def");
765 : MachineOperand Op(MachineOperand::MO_Register);
766 146607965 : Op.IsDef = isDef;
767 146607965 : Op.IsImp = isImp;
768 146679976 : Op.IsDeadOrKill = isKill | isDead;
769 146607965 : Op.IsRenamable = isRenamable;
770 146607965 : Op.IsUndef = isUndef;
771 146607965 : Op.IsInternalRead = isInternalRead;
772 146607965 : Op.IsEarlyClobber = isEarlyClobber;
773 146607965 : Op.TiedTo = 0;
774 146607417 : Op.IsDebug = isDebug;
775 146607965 : Op.SmallContents.RegNo = Reg;
776 146607965 : Op.Contents.Reg.Prev = nullptr;
777 146607955 : Op.Contents.Reg.Next = nullptr;
778 : Op.setSubReg(SubReg);
779 : return Op;
780 : }
781 : static MachineOperand CreateMBB(MachineBasicBlock *MBB,
782 : unsigned char TargetFlags = 0) {
783 : MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
784 : Op.setMBB(MBB);
785 : Op.setTargetFlags(TargetFlags);
786 : return Op;
787 : }
788 : static MachineOperand CreateFI(int Idx) {
789 : MachineOperand Op(MachineOperand::MO_FrameIndex);
790 : Op.setIndex(Idx);
791 : return Op;
792 : }
793 : static MachineOperand CreateCPI(unsigned Idx, int Offset,
794 : unsigned char TargetFlags = 0) {
795 : MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
796 47980 : Op.setIndex(Idx);
797 6 : Op.setOffset(Offset);
798 : Op.setTargetFlags(TargetFlags);
799 : return Op;
800 : }
801 : static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
802 : unsigned char TargetFlags = 0) {
803 : MachineOperand Op(MachineOperand::MO_TargetIndex);
804 0 : Op.setIndex(Idx);
805 : Op.setOffset(Offset);
806 : Op.setTargetFlags(TargetFlags);
807 : return Op;
808 : }
809 : static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
810 : MachineOperand Op(MachineOperand::MO_JumpTableIndex);
811 49 : Op.setIndex(Idx);
812 : Op.setTargetFlags(TargetFlags);
813 : return Op;
814 : }
815 : static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
816 : unsigned char TargetFlags = 0) {
817 : MachineOperand Op(MachineOperand::MO_GlobalAddress);
818 3564937 : Op.Contents.OffsetedInfo.Val.GV = GV;
819 : Op.setOffset(Offset);
820 : Op.setTargetFlags(TargetFlags);
821 : return Op;
822 : }
823 : static MachineOperand CreateES(const char *SymName,
824 : unsigned char TargetFlags = 0) {
825 : MachineOperand Op(MachineOperand::MO_ExternalSymbol);
826 43728 : Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
827 : Op.setOffset(0); // Offset is always 0.
828 : Op.setTargetFlags(TargetFlags);
829 : return Op;
830 : }
831 : static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
832 : unsigned char TargetFlags = 0) {
833 : MachineOperand Op(MachineOperand::MO_BlockAddress);
834 315 : Op.Contents.OffsetedInfo.Val.BA = BA;
835 : Op.setOffset(Offset);
836 : Op.setTargetFlags(TargetFlags);
837 : return Op;
838 : }
839 : /// CreateRegMask - Creates a register mask operand referencing Mask. The
840 : /// operand does not take ownership of the memory referenced by Mask, it
841 : /// must remain valid for the lifetime of the operand.
842 : ///
843 : /// A RegMask operand represents a set of non-clobbered physical registers
844 : /// on an instruction that clobbers many registers, typically a call. The
845 : /// bit mask has a bit set for each physreg that is preserved by this
846 : /// instruction, as described in the documentation for
847 : /// TargetRegisterInfo::getCallPreservedMask().
848 : ///
849 : /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
850 : ///
851 : static MachineOperand CreateRegMask(const uint32_t *Mask) {
852 : assert(Mask && "Missing register mask");
853 : MachineOperand Op(MachineOperand::MO_RegisterMask);
854 2173664 : Op.Contents.RegMask = Mask;
855 : return Op;
856 : }
857 : static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
858 : assert(Mask && "Missing live-out register mask");
859 : MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
860 179 : Op.Contents.RegMask = Mask;
861 : return Op;
862 : }
863 : static MachineOperand CreateMetadata(const MDNode *Meta) {
864 : MachineOperand Op(MachineOperand::MO_Metadata);
865 424232 : Op.Contents.MD = Meta;
866 : return Op;
867 : }
868 :
869 : static MachineOperand CreateMCSymbol(MCSymbol *Sym,
870 : unsigned char TargetFlags = 0) {
871 : MachineOperand Op(MachineOperand::MO_MCSymbol);
872 1376324 : Op.Contents.Sym = Sym;
873 : Op.setOffset(0);
874 : Op.setTargetFlags(TargetFlags);
875 : return Op;
876 : }
877 :
878 : static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
879 : MachineOperand Op(MachineOperand::MO_CFIIndex);
880 1005048 : Op.Contents.CFIIndex = CFIIndex;
881 : return Op;
882 : }
883 :
884 : static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
885 : MachineOperand Op(MachineOperand::MO_IntrinsicID);
886 26 : Op.Contents.IntrinsicID = ID;
887 : return Op;
888 : }
889 :
890 : static MachineOperand CreatePredicate(unsigned Pred) {
891 : MachineOperand Op(MachineOperand::MO_Predicate);
892 120 : Op.Contents.Pred = Pred;
893 : return Op;
894 : }
895 :
896 : friend class MachineInstr;
897 : friend class MachineRegisterInfo;
898 :
899 : private:
900 : // If this operand is currently a register operand, and if this is in a
901 : // function, deregister the operand from the register's use/def list.
902 : void removeRegFromUses();
903 :
904 : /// Artificial kinds for DenseMap usage.
905 : enum : unsigned char {
906 : MO_Empty = MO_Last + 1,
907 : MO_Tombstone,
908 : };
909 :
910 : friend struct DenseMapInfo<MachineOperand>;
911 :
912 : //===--------------------------------------------------------------------===//
913 : // Methods for handling register use/def lists.
914 : //===--------------------------------------------------------------------===//
915 :
916 : /// isOnRegUseList - Return true if this operand is on a register use/def
917 : /// list or false if not. This can only be called for register operands
918 : /// that are part of a machine instruction.
919 0 : bool isOnRegUseList() const {
920 : assert(isReg() && "Can only add reg operand to use lists");
921 0 : return Contents.Reg.Prev != nullptr;
922 : }
923 : };
924 :
925 : template <> struct DenseMapInfo<MachineOperand> {
926 : static MachineOperand getEmptyKey() {
927 : return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
928 : MachineOperand::MO_Empty));
929 : }
930 : static MachineOperand getTombstoneKey() {
931 : return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
932 : MachineOperand::MO_Tombstone));
933 : }
934 : static unsigned getHashValue(const MachineOperand &MO) {
935 96323 : return hash_value(MO);
936 : }
937 : static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
938 : if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
939 4887051 : MachineOperand::MO_Empty) ||
940 : LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
941 : MachineOperand::MO_Tombstone))
942 4611913 : return LHS.getType() == RHS.getType();
943 275138 : return LHS.isIdenticalTo(RHS);
944 : }
945 : };
946 :
947 : inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
948 : MO.print(OS);
949 : return OS;
950 : }
951 :
952 : // See friend declaration above. This additional declaration is required in
953 : // order to compile LLVM with IBM xlC compiler.
954 : hash_code hash_value(const MachineOperand &MO);
955 : } // namespace llvm
956 :
957 : #endif
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