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1 : //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : ///
10 : /// \file
11 : /// This file describes how to lower LLVM code to machine code. This has two
12 : /// main components:
13 : ///
14 : /// 1. Which ValueTypes are natively supported by the target.
15 : /// 2. Which operations are supported for supported ValueTypes.
16 : /// 3. Cost thresholds for alternative implementations of certain operations.
17 : ///
18 : /// In addition it has a few other components, like information about FP
19 : /// immediates.
20 : ///
21 : //===----------------------------------------------------------------------===//
22 :
23 : #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 : #define LLVM_CODEGEN_TARGETLOWERING_H
25 :
26 : #include "llvm/ADT/APInt.h"
27 : #include "llvm/ADT/ArrayRef.h"
28 : #include "llvm/ADT/DenseMap.h"
29 : #include "llvm/ADT/STLExtras.h"
30 : #include "llvm/ADT/SmallVector.h"
31 : #include "llvm/ADT/StringRef.h"
32 : #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
33 : #include "llvm/CodeGen/DAGCombine.h"
34 : #include "llvm/CodeGen/ISDOpcodes.h"
35 : #include "llvm/CodeGen/RuntimeLibcalls.h"
36 : #include "llvm/CodeGen/SelectionDAG.h"
37 : #include "llvm/CodeGen/SelectionDAGNodes.h"
38 : #include "llvm/CodeGen/TargetCallingConv.h"
39 : #include "llvm/CodeGen/ValueTypes.h"
40 : #include "llvm/IR/Attributes.h"
41 : #include "llvm/IR/CallSite.h"
42 : #include "llvm/IR/CallingConv.h"
43 : #include "llvm/IR/DataLayout.h"
44 : #include "llvm/IR/DerivedTypes.h"
45 : #include "llvm/IR/Function.h"
46 : #include "llvm/IR/IRBuilder.h"
47 : #include "llvm/IR/InlineAsm.h"
48 : #include "llvm/IR/Instruction.h"
49 : #include "llvm/IR/Instructions.h"
50 : #include "llvm/IR/Type.h"
51 : #include "llvm/MC/MCRegisterInfo.h"
52 : #include "llvm/Support/AtomicOrdering.h"
53 : #include "llvm/Support/Casting.h"
54 : #include "llvm/Support/ErrorHandling.h"
55 : #include "llvm/Support/MachineValueType.h"
56 : #include "llvm/Target/TargetMachine.h"
57 : #include <algorithm>
58 : #include <cassert>
59 : #include <climits>
60 : #include <cstdint>
61 : #include <iterator>
62 : #include <map>
63 : #include <string>
64 : #include <utility>
65 : #include <vector>
66 :
67 : namespace llvm {
68 :
69 : class BranchProbability;
70 : class CCState;
71 : class CCValAssign;
72 : class Constant;
73 : class FastISel;
74 : class FunctionLoweringInfo;
75 : class GlobalValue;
76 : class IntrinsicInst;
77 : struct KnownBits;
78 : class LLVMContext;
79 : class MachineBasicBlock;
80 : class MachineFunction;
81 : class MachineInstr;
82 : class MachineJumpTableInfo;
83 : class MachineLoop;
84 : class MachineRegisterInfo;
85 : class MCContext;
86 : class MCExpr;
87 : class Module;
88 : class TargetRegisterClass;
89 : class TargetLibraryInfo;
90 : class TargetRegisterInfo;
91 : class Value;
92 :
93 : namespace Sched {
94 :
95 : enum Preference {
96 : None, // No preference
97 : Source, // Follow source order.
98 : RegPressure, // Scheduling for lowest register pressure.
99 : Hybrid, // Scheduling for both latency and register pressure.
100 : ILP, // Scheduling for ILP in low register pressure mode.
101 : VLIW // Scheduling for VLIW targets.
102 : };
103 :
104 : } // end namespace Sched
105 :
106 : /// This base class for TargetLowering contains the SelectionDAG-independent
107 : /// parts that can be used from the rest of CodeGen.
108 : class TargetLoweringBase {
109 : public:
110 : /// This enum indicates whether operations are valid for a target, and if not,
111 : /// what action should be used to make them valid.
112 : enum LegalizeAction : uint8_t {
113 : Legal, // The target natively supports this operation.
114 : Promote, // This operation should be executed in a larger type.
115 : Expand, // Try to expand this to other ops, otherwise use a libcall.
116 : LibCall, // Don't try to expand this to other ops, always use a libcall.
117 : Custom // Use the LowerOperation hook to implement custom lowering.
118 : };
119 :
120 : /// This enum indicates whether a types are legal for a target, and if not,
121 : /// what action should be used to make them valid.
122 : enum LegalizeTypeAction : uint8_t {
123 : TypeLegal, // The target natively supports this type.
124 : TypePromoteInteger, // Replace this integer with a larger one.
125 : TypeExpandInteger, // Split this integer into two of half the size.
126 : TypeSoftenFloat, // Convert this float to a same size integer type,
127 : // if an operation is not supported in target HW.
128 : TypeExpandFloat, // Split this float into two of half the size.
129 : TypeScalarizeVector, // Replace this one-element vector with its element.
130 : TypeSplitVector, // Split this vector into two of half the size.
131 : TypeWidenVector, // This vector should be widened into a larger vector.
132 : TypePromoteFloat // Replace this float with a larger one.
133 : };
134 :
135 : /// LegalizeKind holds the legalization kind that needs to happen to EVT
136 : /// in order to type-legalize it.
137 : using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 :
139 : /// Enum that describes how the target represents true/false values.
140 : enum BooleanContent {
141 : UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142 : ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143 : ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144 : };
145 :
146 : /// Enum that describes what type of support for selects the target has.
147 : enum SelectSupportKind {
148 : ScalarValSelect, // The target supports scalar selects (ex: cmov).
149 : ScalarCondVectorVal, // The target supports selects with a scalar condition
150 : // and vector values (ex: cmov).
151 : VectorMaskSelect // The target supports vector selects with a vector
152 : // mask (ex: x86 blends).
153 : };
154 :
155 : /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156 : /// to, if at all. Exists because different targets have different levels of
157 : /// support for these atomic instructions, and also have different options
158 : /// w.r.t. what they should expand to.
159 : enum class AtomicExpansionKind {
160 : None, // Don't expand the instruction.
161 : LLSC, // Expand the instruction into loadlinked/storeconditional; used
162 : // by ARM/AArch64.
163 : LLOnly, // Expand the (load) instruction into just a load-linked, which has
164 : // greater atomic guarantees than a normal load.
165 : CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166 : MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167 : };
168 :
169 : /// Enum that specifies when a multiplication should be expanded.
170 : enum class MulExpansionKind {
171 : Always, // Always expand the instruction.
172 : OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173 : // or custom.
174 : };
175 :
176 : class ArgListEntry {
177 : public:
178 : Value *Val = nullptr;
179 : SDValue Node = SDValue();
180 : Type *Ty = nullptr;
181 : bool IsSExt : 1;
182 : bool IsZExt : 1;
183 : bool IsInReg : 1;
184 : bool IsSRet : 1;
185 : bool IsNest : 1;
186 : bool IsByVal : 1;
187 : bool IsInAlloca : 1;
188 : bool IsReturned : 1;
189 : bool IsSwiftSelf : 1;
190 : bool IsSwiftError : 1;
191 : uint16_t Alignment = 0;
192 :
193 : ArgListEntry()
194 3414850 : : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195 : IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196 3414850 : IsSwiftSelf(false), IsSwiftError(false) {}
197 :
198 : void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
199 : };
200 : using ArgListTy = std::vector<ArgListEntry>;
201 :
202 5561 : virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
203 5561 : ArgListTy &Args) const {};
204 :
205 : static ISD::NodeType getExtendForContent(BooleanContent Content) {
206 : switch (Content) {
207 : case UndefinedBooleanContent:
208 : // Extend by adding rubbish bits.
209 : return ISD::ANY_EXTEND;
210 : case ZeroOrOneBooleanContent:
211 : // Extend by adding zero bits.
212 : return ISD::ZERO_EXTEND;
213 : case ZeroOrNegativeOneBooleanContent:
214 : // Extend by copying the sign bit.
215 : return ISD::SIGN_EXTEND;
216 : }
217 0 : llvm_unreachable("Invalid content kind");
218 : }
219 :
220 : /// NOTE: The TargetMachine owns TLOF.
221 : explicit TargetLoweringBase(const TargetMachine &TM);
222 : TargetLoweringBase(const TargetLoweringBase &) = delete;
223 : TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
224 34779 : virtual ~TargetLoweringBase() = default;
225 :
226 : protected:
227 : /// Initialize all of the actions to default values.
228 : void initActions();
229 :
230 : public:
231 0 : const TargetMachine &getTargetMachine() const { return TM; }
232 :
233 8037 : virtual bool useSoftFloat() const { return false; }
234 :
235 : /// Return the pointer type for the given address space, defaults to
236 : /// the pointer type from the data layout.
237 : /// FIXME: The default needs to be removed once all the code is updated.
238 0 : MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239 61607175 : return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
240 : }
241 :
242 : /// Return the type for frame index, which is determined by
243 : /// the alloca address space specified through the data layout.
244 0 : MVT getFrameIndexTy(const DataLayout &DL) const {
245 0 : return getPointerTy(DL, DL.getAllocaAddrSpace());
246 : }
247 :
248 : /// Return the type for operands of fence.
249 : /// TODO: Let fence operands be of i32 type and remove this.
250 594 : virtual MVT getFenceOperandTy(const DataLayout &DL) const {
251 594 : return getPointerTy(DL);
252 : }
253 :
254 : /// EVT is not used in-tree, but is used by out-of-tree target.
255 : /// A documentation for this function would be nice...
256 : virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
257 :
258 : EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
259 : bool LegalTypes = true) const;
260 :
261 : /// Returns the type to be used for the index operand of:
262 : /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
263 : /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
264 138326 : virtual MVT getVectorIdxTy(const DataLayout &DL) const {
265 138326 : return getPointerTy(DL);
266 : }
267 :
268 10914 : virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
269 10914 : return true;
270 : }
271 :
272 : /// Return true if multiple condition registers are available.
273 0 : bool hasMultipleConditionRegisters() const {
274 0 : return HasMultipleConditionRegisters;
275 : }
276 :
277 : /// Return true if the target has BitExtract instructions.
278 0 : bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
279 :
280 : /// Return the preferred vector type legalization action.
281 : virtual TargetLoweringBase::LegalizeTypeAction
282 1553572 : getPreferredVectorAction(EVT VT) const {
283 : // The default action for one element vectors is to scalarize
284 3293672 : if (VT.getVectorNumElements() == 1)
285 248337 : return TypeScalarizeVector;
286 : // The default action for other vectors is to promote
287 : return TypePromoteInteger;
288 : }
289 :
290 : // There are two general methods for expanding a BUILD_VECTOR node:
291 : // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
292 : // them together.
293 : // 2. Build the vector on the stack and then load it.
294 : // If this function returns true, then method (1) will be used, subject to
295 : // the constraint that all of the necessary shuffles are legal (as determined
296 : // by isShuffleMaskLegal). If this function returns false, then method (2) is
297 : // always used. The vector type, and the number of defined values, are
298 : // provided.
299 : virtual bool
300 2030 : shouldExpandBuildVectorWithShuffles(EVT /* VT */,
301 : unsigned DefinedValues) const {
302 2052 : return DefinedValues < 3;
303 : }
304 :
305 : /// Return true if integer divide is usually cheaper than a sequence of
306 : /// several shifts, adds, and multiplies for this target.
307 : /// The definition of "cheaper" may depend on whether we're optimizing
308 : /// for speed or for size.
309 565 : virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
310 :
311 : /// Return true if the target can handle a standalone remainder operation.
312 0 : virtual bool hasStandaloneRem(EVT VT) const {
313 0 : return true;
314 : }
315 :
316 : /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
317 124 : virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
318 : // Default behavior is to replace SQRT(X) with X*RSQRT(X).
319 124 : return false;
320 : }
321 :
322 : /// Reciprocal estimate status values used by the functions below.
323 : enum ReciprocalEstimate : int {
324 : Unspecified = -1,
325 : Disabled = 0,
326 : Enabled = 1
327 : };
328 :
329 : /// Return a ReciprocalEstimate enum value for a square root of the given type
330 : /// based on the function's attributes. If the operation is not overridden by
331 : /// the function's attributes, "Unspecified" is returned and target defaults
332 : /// are expected to be used for instruction selection.
333 : int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
334 :
335 : /// Return a ReciprocalEstimate enum value for a division of the given type
336 : /// based on the function's attributes. If the operation is not overridden by
337 : /// the function's attributes, "Unspecified" is returned and target defaults
338 : /// are expected to be used for instruction selection.
339 : int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
340 :
341 : /// Return the refinement step count for a square root of the given type based
342 : /// on the function's attributes. If the operation is not overridden by
343 : /// the function's attributes, "Unspecified" is returned and target defaults
344 : /// are expected to be used for instruction selection.
345 : int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
346 :
347 : /// Return the refinement step count for a division of the given type based
348 : /// on the function's attributes. If the operation is not overridden by
349 : /// the function's attributes, "Unspecified" is returned and target defaults
350 : /// are expected to be used for instruction selection.
351 : int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
352 :
353 : /// Returns true if target has indicated at least one type should be bypassed.
354 : bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
355 :
356 : /// Returns map of slow types for division or remainder with corresponding
357 : /// fast types
358 : const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
359 11462 : return BypassSlowDivWidths;
360 : }
361 :
362 : /// Return true if Flow Control is an expensive operation that should be
363 : /// avoided.
364 0 : bool isJumpExpensive() const { return JumpIsExpensive; }
365 :
366 : /// Return true if selects are only cheaper than branches if the branch is
367 : /// unlikely to be predicted right.
368 0 : bool isPredictableSelectExpensive() const {
369 0 : return PredictableSelectIsExpensive;
370 : }
371 :
372 : /// If a branch or a select condition is skewed in one direction by more than
373 : /// this factor, it is very likely to be predicted correctly.
374 : virtual BranchProbability getPredictableBranchThreshold() const;
375 :
376 : /// Return true if the following transform is beneficial:
377 : /// fold (conv (load x)) -> (load (conv*)x)
378 : /// On architectures that don't natively support some vector loads
379 : /// efficiently, casting the load to a smaller vector of larger types and
380 : /// loading is more efficient, however, this can be undone by optimizations in
381 : /// dag combiner.
382 197665 : virtual bool isLoadBitCastBeneficial(EVT LoadVT,
383 : EVT BitcastVT) const {
384 : // Don't do if we could do an indexed load on the original type, but not on
385 : // the new one.
386 197665 : if (!LoadVT.isSimple() || !BitcastVT.isSimple())
387 : return true;
388 :
389 : MVT LoadMVT = LoadVT.getSimpleVT();
390 :
391 : // Don't bother doing this if it's just going to be promoted again later, as
392 : // doing so might interfere with other combines.
393 386965 : if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
394 197573 : getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
395 20429 : return false;
396 :
397 : return true;
398 : }
399 :
400 : /// Return true if the following transform is beneficial:
401 : /// (store (y (conv x)), y*)) -> (store x, (x*))
402 201231 : virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
403 : // Default to the same logic as loads.
404 201231 : return isLoadBitCastBeneficial(StoreVT, BitcastVT);
405 : }
406 :
407 : /// Return true if it is expected to be cheaper to do a store of a non-zero
408 : /// vector constant with the given size and type for the address space than to
409 : /// store the individual scalar element constants.
410 9225 : virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
411 : unsigned NumElem,
412 : unsigned AddrSpace) const {
413 9225 : return false;
414 : }
415 :
416 : /// Allow store merging after legalization in addition to before legalization.
417 : /// This may catch stores that do not exist earlier (eg, stores created from
418 : /// intrinsics).
419 71335 : virtual bool mergeStoresAfterLegalization() const { return true; }
420 :
421 : /// Returns if it's reasonable to merge stores to MemVT size.
422 7317 : virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
423 : const SelectionDAG &DAG) const {
424 7317 : return true;
425 : }
426 :
427 : /// Return true if it is cheap to speculate a call to intrinsic cttz.
428 9 : virtual bool isCheapToSpeculateCttz() const {
429 9 : return false;
430 : }
431 :
432 : /// Return true if it is cheap to speculate a call to intrinsic ctlz.
433 6 : virtual bool isCheapToSpeculateCtlz() const {
434 6 : return false;
435 : }
436 :
437 : /// Return true if ctlz instruction is fast.
438 0 : virtual bool isCtlzFast() const {
439 0 : return false;
440 : }
441 :
442 : /// Return true if it is safe to transform an integer-domain bitwise operation
443 : /// into the equivalent floating-point operation. This should be set to true
444 : /// if the target has IEEE-754-compliant fabs/fneg operations for the input
445 : /// type.
446 18602 : virtual bool hasBitPreservingFPLogic(EVT VT) const {
447 18602 : return false;
448 : }
449 :
450 : /// Return true if it is cheaper to split the store of a merged int val
451 : /// from a pair of smaller values into multiple stores.
452 57 : virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
453 57 : return false;
454 : }
455 :
456 : /// Return if the target supports combining a
457 : /// chain like:
458 : /// \code
459 : /// %andResult = and %val1, #mask
460 : /// %icmpResult = icmp %andResult, 0
461 : /// \endcode
462 : /// into a single machine instruction of a form like:
463 : /// \code
464 : /// cc = test %register, #mask
465 : /// \endcode
466 81 : virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
467 81 : return false;
468 : }
469 :
470 : /// Use bitwise logic to make pairs of compares more efficient. For example:
471 : /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
472 : /// This should be true when it takes more than one instruction to lower
473 : /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
474 : /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
475 880 : virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
476 880 : return false;
477 : }
478 :
479 : /// Return the preferred operand type if the target has a quick way to compare
480 : /// integer values of the given size. Assume that any legal integer type can
481 : /// be compared efficiently. Targets may override this to allow illegal wide
482 : /// types to return a vector type if there is support to compare that type.
483 0 : virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
484 0 : MVT VT = MVT::getIntegerVT(NumBits);
485 0 : return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
486 : }
487 :
488 : /// Return true if the target should transform:
489 : /// (X & Y) == Y ---> (~X & Y) == 0
490 : /// (X & Y) != Y ---> (~X & Y) != 0
491 : ///
492 : /// This may be profitable if the target has a bitwise and-not operation that
493 : /// sets comparison flags. A target may want to limit the transformation based
494 : /// on the type of Y or if Y is a constant.
495 : ///
496 : /// Note that the transform will not occur if Y is known to be a power-of-2
497 : /// because a mask and compare of a single bit can be handled by inverting the
498 : /// predicate, for example:
499 : /// (X & 8) == 8 ---> (X & 8) != 0
500 599 : virtual bool hasAndNotCompare(SDValue Y) const {
501 599 : return false;
502 : }
503 :
504 : /// Return true if the target has a bitwise and-not operation:
505 : /// X = ~A & B
506 : /// This can be used to simplify select or other instructions.
507 698 : virtual bool hasAndNot(SDValue X) const {
508 : // If the target has the more complex version of this operation, assume that
509 : // it has this operation too.
510 698 : return hasAndNotCompare(X);
511 : }
512 :
513 : /// There are two ways to clear extreme bits (either low or high):
514 : /// Mask: x & (-1 << y) (the instcombine canonical form)
515 : /// Shifts: x >> y << y
516 : /// Return true if the variant with 2 shifts is preferred.
517 : /// Return false if there is no preference.
518 83021 : virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
519 : // By default, let's assume that no one prefers shifts.
520 83021 : return false;
521 : }
522 :
523 : /// Should we tranform the IR-optimal check for whether given truncation
524 : /// down into KeptBits would be truncating or not:
525 : /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
526 : /// Into it's more traditional form:
527 : /// ((%x << C) a>> C) dstcond %x
528 : /// Return true if we should transform.
529 : /// Return false if there is no preference.
530 31 : virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
531 : unsigned KeptBits) const {
532 : // By default, let's assume that no one prefers shifts.
533 31 : return false;
534 : }
535 :
536 : /// Return true if the target wants to use the optimization that
537 : /// turns ext(promotableInst1(...(promotableInstN(load)))) into
538 : /// promotedInst1(...(promotedInstN(ext(load)))).
539 0 : bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
540 :
541 : /// Return true if the target can combine store(extractelement VectorTy,
542 : /// Idx).
543 : /// \p Cost[out] gives the cost of that transformation when this is true.
544 29939 : virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
545 : unsigned &Cost) const {
546 29939 : return false;
547 : }
548 :
549 : /// Return true if inserting a scalar into a variable element of an undef
550 : /// vector is more efficiently handled by splatting the scalar instead.
551 28 : virtual bool shouldSplatInsEltVarIndex(EVT) const {
552 28 : return false;
553 : }
554 :
555 : /// Return true if target supports floating point exceptions.
556 0 : bool hasFloatingPointExceptions() const {
557 0 : return HasFloatingPointExceptions;
558 : }
559 :
560 : /// Return true if target always beneficiates from combining into FMA for a
561 : /// given value type. This must typically return false on targets where FMA
562 : /// takes more cycles to execute than FADD.
563 4532 : virtual bool enableAggressiveFMAFusion(EVT VT) const {
564 4532 : return false;
565 : }
566 :
567 : /// Return the ValueType of the result of SETCC operations.
568 : virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
569 : EVT VT) const;
570 :
571 : /// Return the ValueType for comparison libcalls. Comparions libcalls include
572 : /// floating point comparion calls, and Ordered/Unordered check calls on
573 : /// floating point numbers.
574 : virtual
575 : MVT::SimpleValueType getCmpLibcallReturnType() const;
576 :
577 : /// For targets without i1 registers, this gives the nature of the high-bits
578 : /// of boolean values held in types wider than i1.
579 : ///
580 : /// "Boolean values" are special true/false values produced by nodes like
581 : /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
582 : /// Not to be confused with general values promoted from i1. Some cpus
583 : /// distinguish between vectors of boolean and scalars; the isVec parameter
584 : /// selects between the two kinds. For example on X86 a scalar boolean should
585 : /// be zero extended from i1, while the elements of a vector of booleans
586 : /// should be sign extended from i1.
587 : ///
588 : /// Some cpus also treat floating point types the same way as they treat
589 : /// vectors instead of the way they treat scalars.
590 : BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
591 686923 : if (isVec)
592 250684 : return BooleanVectorContents;
593 439519 : return isFloat ? BooleanFloatContents : BooleanContents;
594 : }
595 :
596 684895 : BooleanContent getBooleanContents(EVT Type) const {
597 684895 : return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
598 : }
599 :
600 : /// Return target scheduling preference.
601 0 : Sched::Preference getSchedulingPreference() const {
602 0 : return SchedPreferenceInfo;
603 : }
604 :
605 : /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
606 : /// for different nodes. This function returns the preference (or none) for
607 : /// the given node.
608 16050136 : virtual Sched::Preference getSchedulingPreference(SDNode *) const {
609 16050136 : return Sched::None;
610 : }
611 :
612 : /// Return the register class that should be used for the specified value
613 : /// type.
614 37263461 : virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
615 37482134 : const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
616 : assert(RC && "This value type is not natively supported!");
617 37263461 : return RC;
618 : }
619 :
620 : /// Return the 'representative' register class for the specified value
621 : /// type.
622 : ///
623 : /// The 'representative' register class is the largest legal super-reg
624 : /// register class for the register class of the value type. For example, on
625 : /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
626 : /// register class is GR64 on x86_64.
627 413240 : virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
628 830141 : const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
629 413240 : return RC;
630 : }
631 :
632 : /// Return the cost of the 'representative' register class for the specified
633 : /// value type.
634 489351 : virtual uint8_t getRepRegClassCostFor(MVT VT) const {
635 489351 : return RepRegClassCostForVT[VT.SimpleTy];
636 : }
637 :
638 : /// Return true if the target has native support for the specified value type.
639 : /// This means that it has a register that directly holds it without
640 : /// promotions or expansions.
641 0 : bool isTypeLegal(EVT VT) const {
642 : assert(!VT.isSimple() ||
643 : (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
644 408185344 : return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
645 : }
646 :
647 : class ValueTypeActionImpl {
648 : /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
649 : /// that indicates how instruction selection should deal with the type.
650 : LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
651 :
652 : public:
653 41320 : ValueTypeActionImpl() {
654 41320 : std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
655 : TypeLegal);
656 : }
657 :
658 : LegalizeTypeAction getTypeAction(MVT VT) const {
659 101326042 : return ValueTypeActions[VT.SimpleTy];
660 : }
661 :
662 : void setTypeAction(MVT VT, LegalizeTypeAction Action) {
663 3967513 : ValueTypeActions[VT.SimpleTy] = Action;
664 : }
665 : };
666 :
667 : const ValueTypeActionImpl &getValueTypeActions() const {
668 : return ValueTypeActions;
669 : }
670 :
671 : /// Return how we should legalize values of this type, either it is already
672 : /// legal (return 'Legal') or we need to promote it to a larger type (return
673 : /// 'Promote'), or we need to expand it into multiple registers of smaller
674 : /// integer type (return 'Expand'). 'Custom' is not an option.
675 : LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
676 98871058 : return getTypeConversion(Context, VT).first;
677 : }
678 : LegalizeTypeAction getTypeAction(MVT VT) const {
679 : return ValueTypeActions.getTypeAction(VT);
680 : }
681 :
682 : /// For types supported by the target, this is an identity function. For
683 : /// types that must be promoted to larger types, this returns the larger type
684 : /// to promote to. For integer types that are larger than the largest integer
685 : /// register, this contains one step in the expansion to get to the smaller
686 : /// register. For illegal floating point types, this returns the integer type
687 : /// to transform to.
688 : EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
689 1184675 : return getTypeConversion(Context, VT).second;
690 : }
691 :
692 : /// For types supported by the target, this is an identity function. For
693 : /// types that must be expanded (i.e. integer types that are larger than the
694 : /// largest integer register or illegal floating point types), this returns
695 : /// the largest legal type it will be expanded to.
696 115000 : EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
697 : assert(!VT.isVector());
698 : while (true) {
699 116466 : switch (getTypeAction(Context, VT)) {
700 115000 : case TypeLegal:
701 115000 : return VT;
702 1466 : case TypeExpandInteger:
703 1466 : VT = getTypeToTransformTo(Context, VT);
704 : break;
705 0 : default:
706 0 : llvm_unreachable("Type is not legal nor is it to be expanded!");
707 : }
708 : }
709 : }
710 :
711 : /// Vector types are broken down into some number of legal first class types.
712 : /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
713 : /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
714 : /// turns into 4 EVT::i32 values with both PPC and X86.
715 : ///
716 : /// This method returns the number of registers needed, and the VT for each
717 : /// register. It also returns the VT and quantity of the intermediate values
718 : /// before they are promoted/expanded.
719 : unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
720 : EVT &IntermediateVT,
721 : unsigned &NumIntermediates,
722 : MVT &RegisterVT) const;
723 :
724 : /// Certain targets such as MIPS require that some types such as vectors are
725 : /// always broken down into scalars in some contexts. This occurs even if the
726 : /// vector type is legal.
727 12433 : virtual unsigned getVectorTypeBreakdownForCallingConv(
728 : LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
729 : unsigned &NumIntermediates, MVT &RegisterVT) const {
730 12653 : return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
731 12433 : RegisterVT);
732 : }
733 :
734 : struct IntrinsicInfo {
735 : unsigned opc = 0; // target opcode
736 : EVT memVT; // memory VT
737 :
738 : // value representing memory location
739 : PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
740 :
741 : int offset = 0; // offset off of ptrVal
742 : unsigned size = 0; // the size of the memory location
743 : // (taken from memVT if zero)
744 : unsigned align = 1; // alignment
745 :
746 : MachineMemOperand::Flags flags = MachineMemOperand::MONone;
747 : IntrinsicInfo() = default;
748 : };
749 :
750 : /// Given an intrinsic, checks if on the target the intrinsic will need to map
751 : /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
752 : /// true and store the intrinsic information into the IntrinsicInfo that was
753 : /// passed to the function.
754 3916 : virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
755 : MachineFunction &,
756 : unsigned /*Intrinsic*/) const {
757 3916 : return false;
758 : }
759 :
760 : /// Returns true if the target can instruction select the specified FP
761 : /// immediate natively. If false, the legalizer will materialize the FP
762 : /// immediate as a load from a constant pool.
763 75 : virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
764 75 : return false;
765 : }
766 :
767 : /// Targets can use this to indicate that they only support *some*
768 : /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
769 : /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
770 : /// legal.
771 645 : virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
772 645 : return true;
773 : }
774 :
775 : /// Returns true if the operation can trap for the value type.
776 : ///
777 : /// VT must be a legal type. By default, we optimistically assume most
778 : /// operations don't trap except for integer divide and remainder.
779 : virtual bool canOpTrap(unsigned Op, EVT VT) const;
780 :
781 : /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
782 : /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
783 : /// constant pool entry.
784 1129 : virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
785 : EVT /*VT*/) const {
786 1129 : return false;
787 : }
788 :
789 : /// Return how this operation should be treated: either it is legal, needs to
790 : /// be promoted to a larger size, needs to be expanded to some other code
791 : /// sequence, or the target has a custom expander for it.
792 0 : LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
793 65811160 : if (VT.isExtended()) return Expand;
794 : // If a target-specific SDNode requires legalization, require the target
795 : // to provide custom legalization for it.
796 8347823 : if (Op >= array_lengthof(OpActions[0])) return Custom;
797 82333161 : return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
798 : }
799 :
800 : LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
801 : unsigned EqOpc;
802 : switch (Op) {
803 0 : default: llvm_unreachable("Unexpected FP pseudo-opcode");
804 : case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
805 : case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
806 : case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
807 : case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
808 : case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
809 : case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
810 : case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
811 : case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
812 : case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
813 : case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
814 : case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
815 : case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
816 : case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
817 : case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
818 : case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
819 : case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
820 : case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
821 : case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
822 : }
823 :
824 : auto Action = getOperationAction(EqOpc, VT);
825 :
826 : // We don't currently handle Custom or Promote for strict FP pseudo-ops.
827 : // For now, we just expand for those cases.
828 770 : if (Action != Legal)
829 : Action = Expand;
830 :
831 : return Action;
832 : }
833 :
834 : /// Return true if the specified operation is legal on this target or can be
835 : /// made legal with custom lowering. This is used to help guide high-level
836 : /// lowering decisions.
837 267457 : bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
838 2945992 : return (VT == MVT::Other || isTypeLegal(VT)) &&
839 1978508 : (getOperationAction(Op, VT) == Legal ||
840 267457 : getOperationAction(Op, VT) == Custom);
841 : }
842 :
843 : /// Return true if the specified operation is legal on this target or can be
844 : /// made legal using promotion. This is used to help guide high-level lowering
845 : /// decisions.
846 208950 : bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
847 208940 : return (VT == MVT::Other || isTypeLegal(VT)) &&
848 5587 : (getOperationAction(Op, VT) == Legal ||
849 208950 : getOperationAction(Op, VT) == Promote);
850 : }
851 :
852 : /// Return true if the specified operation is legal on this target or can be
853 : /// made legal with custom lowering or using promotion. This is used to help
854 : /// guide high-level lowering decisions.
855 77910 : bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
856 74350 : return (VT == MVT::Other || isTypeLegal(VT)) &&
857 45454 : (getOperationAction(Op, VT) == Legal ||
858 34307 : getOperationAction(Op, VT) == Custom ||
859 77910 : getOperationAction(Op, VT) == Promote);
860 : }
861 :
862 : /// Return true if the operation uses custom lowering, regardless of whether
863 : /// the type is legal or not.
864 0 : bool isOperationCustom(unsigned Op, EVT VT) const {
865 0 : return getOperationAction(Op, VT) == Custom;
866 : }
867 :
868 : /// Return true if lowering to a jump table is allowed.
869 19406 : virtual bool areJTsAllowed(const Function *Fn) const {
870 38810 : if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
871 2 : return false;
872 :
873 : return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
874 : isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
875 : }
876 :
877 : /// Check whether the range [Low,High] fits in a machine word.
878 14514 : bool rangeFitsInWord(const APInt &Low, const APInt &High,
879 : const DataLayout &DL) const {
880 : // FIXME: Using the pointer type doesn't seem ideal.
881 14514 : uint64_t BW = DL.getIndexSizeInBits(0u);
882 14514 : uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
883 14514 : return Range <= BW;
884 : }
885 :
886 : /// Return true if lowering to a jump table is suitable for a set of case
887 : /// clusters which may contain \p NumCases cases, \p Range range of values.
888 : /// FIXME: This function check the maximum table size and density, but the
889 : /// minimum size is not checked. It would be nice if the minimum size is
890 : /// also combined within this function. Currently, the minimum size check is
891 : /// performed in findJumpTable() in SelectionDAGBuiler and
892 : /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
893 11300 : virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
894 : uint64_t Range) const {
895 11300 : const bool OptForSize = SI->getParent()->getParent()->optForSize();
896 11300 : const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
897 : const unsigned MaxJumpTableSize =
898 11248 : OptForSize || getMaximumJumpTableSize() == 0
899 11761 : ? UINT_MAX
900 461 : : getMaximumJumpTableSize();
901 : // Check whether a range of clusters is dense enough for a jump table.
902 11300 : if (Range <= MaxJumpTableSize &&
903 11089 : (NumCases * 100 >= Range * MinDensity)) {
904 8969 : return true;
905 : }
906 : return false;
907 : }
908 :
909 : /// Return true if lowering to a bit test is suitable for a set of case
910 : /// clusters which contains \p NumDests unique destinations, \p Low and
911 : /// \p High as its lowest and highest case values, and expects \p NumCmps
912 : /// case value comparisons. Check if the number of destinations, comparison
913 : /// metric, and range are all suitable.
914 12215 : bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
915 : const APInt &Low, const APInt &High,
916 : const DataLayout &DL) const {
917 : // FIXME: I don't think NumCmps is the correct metric: a single case and a
918 : // range of cases both require only one branch to lower. Just looking at the
919 : // number of clusters and destinations should be enough to decide whether to
920 : // build bit tests.
921 :
922 : // To lower a range with bit tests, the range must fit the bitwidth of a
923 : // machine word.
924 12215 : if (!rangeFitsInWord(Low, High, DL))
925 : return false;
926 :
927 : // Decide whether it's profitable to lower this range with bit tests. Each
928 : // destination requires a bit test and branch, and there is an overall range
929 : // check branch. For a small number of clusters, separate comparisons might
930 : // be cheaper, and for many destinations, splitting the range might be
931 : // better.
932 11334 : return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
933 10861 : (NumDests == 3 && NumCmps >= 6);
934 : }
935 :
936 : /// Return true if the specified operation is illegal on this target or
937 : /// unlikely to be made legal with custom lowering. This is used to help guide
938 : /// high-level lowering decisions.
939 0 : bool isOperationExpand(unsigned Op, EVT VT) const {
940 17049 : return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
941 : }
942 :
943 : /// Return true if the specified operation is legal on this target.
944 : bool isOperationLegal(unsigned Op, EVT VT) const {
945 2178752 : return (VT == MVT::Other || isTypeLegal(VT)) &&
946 : getOperationAction(Op, VT) == Legal;
947 : }
948 :
949 : /// Return how this load with extension should be treated: either it is legal,
950 : /// needs to be promoted to a larger size, needs to be expanded to some other
951 : /// code sequence, or the target has a custom expander for it.
952 0 : LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
953 : EVT MemVT) const {
954 244299 : if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
955 241501 : unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
956 241100 : unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
957 : assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
958 : MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
959 137334 : unsigned Shift = 4 * ExtType;
960 240018 : return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
961 : }
962 :
963 : /// Return true if the specified load with extension is legal on this target.
964 0 : bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
965 80432 : return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
966 : }
967 :
968 : /// Return true if the specified load with extension is legal or custom
969 : /// on this target.
970 0 : bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
971 2473 : return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
972 0 : getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
973 : }
974 :
975 : /// Return how this store with truncation should be treated: either it is
976 : /// legal, needs to be promoted to a larger size, needs to be expanded to some
977 : /// other code sequence, or the target has a custom expander for it.
978 0 : LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
979 164784 : if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
980 86136 : unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
981 86136 : unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
982 : assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
983 : "Table isn't big enough!");
984 30700 : return TruncStoreActions[ValI][MemI];
985 : }
986 :
987 : /// Return true if the specified store with truncation is legal on this
988 : /// target.
989 0 : bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
990 52302 : return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
991 : }
992 :
993 : /// Return true if the specified store with truncation has solution on this
994 : /// target.
995 0 : bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
996 2039 : return isTypeLegal(ValVT) &&
997 1095 : (getTruncStoreAction(ValVT, MemVT) == Legal ||
998 0 : getTruncStoreAction(ValVT, MemVT) == Custom);
999 : }
1000 :
1001 : /// Return how the indexed load should be treated: either it is legal, needs
1002 : /// to be promoted to a larger size, needs to be expanded to some other code
1003 : /// sequence, or the target has a custom expander for it.
1004 : LegalizeAction
1005 : getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1006 : assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1007 : "Table isn't big enough!");
1008 10335630 : unsigned Ty = (unsigned)VT.SimpleTy;
1009 10335630 : return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1010 : }
1011 :
1012 : /// Return true if the specified indexed load is legal on this target.
1013 0 : bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1014 10335630 : return VT.isSimple() &&
1015 10289378 : (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1016 0 : getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1017 : }
1018 :
1019 : /// Return how the indexed store should be treated: either it is legal, needs
1020 : /// to be promoted to a larger size, needs to be expanded to some other code
1021 : /// sequence, or the target has a custom expander for it.
1022 : LegalizeAction
1023 : getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1024 : assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1025 : "Table isn't big enough!");
1026 11717407 : unsigned Ty = (unsigned)VT.SimpleTy;
1027 11717407 : return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1028 : }
1029 :
1030 : /// Return true if the specified indexed load is legal on this target.
1031 0 : bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1032 11717407 : return VT.isSimple() &&
1033 11684902 : (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1034 0 : getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1035 : }
1036 :
1037 : /// Return how the condition code should be treated: either it is legal, needs
1038 : /// to be expanded to some other code sequence, or the target has a custom
1039 : /// expander for it.
1040 : LegalizeAction
1041 : getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1042 : assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1043 : ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1044 : "Table isn't big enough!");
1045 : // See setCondCodeAction for how this is encoded.
1046 95477 : uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1047 95735 : uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1048 94067 : LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1049 : assert(Action != Promote && "Can't promote condition code!");
1050 : return Action;
1051 : }
1052 :
1053 : /// Return true if the specified condition code is legal on this target.
1054 : bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1055 : return getCondCodeAction(CC, VT) == Legal;
1056 : }
1057 :
1058 : /// Return true if the specified condition code is legal or custom on this
1059 : /// target.
1060 : bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1061 1668 : return getCondCodeAction(CC, VT) == Legal ||
1062 : getCondCodeAction(CC, VT) == Custom;
1063 : }
1064 :
1065 : /// If the action for this operation is to promote, this method returns the
1066 : /// ValueType to promote to.
1067 290595 : MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1068 : assert(getOperationAction(Op, VT) == Promote &&
1069 : "This operation isn't promoted!");
1070 :
1071 : // See if this has an explicit type specified.
1072 : std::map<std::pair<unsigned, MVT::SimpleValueType>,
1073 : MVT::SimpleValueType>::const_iterator PTTI =
1074 290595 : PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1075 290595 : if (PTTI != PromoteToType.end()) return PTTI->second;
1076 :
1077 : assert((VT.isInteger() || VT.isFloatingPoint()) &&
1078 : "Cannot autopromote this type, add it with AddPromotedToType.");
1079 :
1080 : MVT NVT = VT;
1081 : do {
1082 2048 : NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1083 : assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1084 : "Didn't find type to promote to!");
1085 2042 : } while (!isTypeLegal(NVT) ||
1086 : getOperationAction(Op, NVT) == Promote);
1087 1976 : return NVT;
1088 : }
1089 :
1090 : /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1091 : /// operations except for the pointer size. If AllowUnknown is true, this
1092 : /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1093 : /// otherwise it will assert.
1094 67510572 : EVT getValueType(const DataLayout &DL, Type *Ty,
1095 : bool AllowUnknown = false) const {
1096 : // Lower scalar pointers to native pointer types.
1097 : if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1098 45916906 : return getPointerTy(DL, PTy->getAddressSpace());
1099 :
1100 21593666 : if (Ty->isVectorTy()) {
1101 : VectorType *VTy = cast<VectorType>(Ty);
1102 1904403 : Type *Elm = VTy->getElementType();
1103 : // Lower vectors of pointers to native pointer types.
1104 : if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1105 : EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1106 20266 : Elm = PointerTy.getTypeForEVT(Ty->getContext());
1107 : }
1108 :
1109 : return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1110 1904403 : VTy->getNumElements());
1111 : }
1112 19689263 : return EVT::getEVT(Ty, AllowUnknown);
1113 : }
1114 :
1115 : /// Return the MVT corresponding to this LLVM type. See getValueType.
1116 : MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1117 : bool AllowUnknown = false) const {
1118 411658 : return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1119 : }
1120 :
1121 : /// Return the desired alignment for ByVal or InAlloca aggregate function
1122 : /// arguments in the caller parameter area. This is the actual alignment, not
1123 : /// its logarithm.
1124 : virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1125 :
1126 : /// Return the type of registers that this ValueType will eventually require.
1127 : MVT getRegisterType(MVT VT) const {
1128 : assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1129 354 : return RegisterTypeForVT[VT.SimpleTy];
1130 : }
1131 :
1132 : /// Return the type of registers that this ValueType will eventually require.
1133 17657415 : MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1134 17657415 : if (VT.isSimple()) {
1135 : assert((unsigned)VT.getSimpleVT().SimpleTy <
1136 : array_lengthof(RegisterTypeForVT));
1137 17644278 : return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1138 : }
1139 13137 : if (VT.isVector()) {
1140 3390 : EVT VT1;
1141 3390 : MVT RegisterVT;
1142 : unsigned NumIntermediates;
1143 3390 : (void)getVectorTypeBreakdown(Context, VT, VT1,
1144 : NumIntermediates, RegisterVT);
1145 3390 : return RegisterVT;
1146 : }
1147 9747 : if (VT.isInteger()) {
1148 9747 : return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1149 : }
1150 0 : llvm_unreachable("Unsupported extended type!");
1151 : }
1152 :
1153 : /// Return the number of registers that this ValueType will eventually
1154 : /// require.
1155 : ///
1156 : /// This is one for any types promoted to live in larger registers, but may be
1157 : /// more than one for types (like i64) that are split into pieces. For types
1158 : /// like i140, which are first promoted then expanded, it is the number of
1159 : /// registers needed to hold all the bits of the original type. For an i140
1160 : /// on a 32 bit machine this means 5 registers.
1161 18194194 : unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1162 18194194 : if (VT.isSimple()) {
1163 : assert((unsigned)VT.getSimpleVT().SimpleTy <
1164 : array_lengthof(NumRegistersForVT));
1165 18187161 : return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1166 : }
1167 7033 : if (VT.isVector()) {
1168 3459 : EVT VT1;
1169 3459 : MVT VT2;
1170 : unsigned NumIntermediates;
1171 3459 : return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1172 : }
1173 3574 : if (VT.isInteger()) {
1174 3574 : unsigned BitWidth = VT.getSizeInBits();
1175 3574 : unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1176 3574 : return (BitWidth + RegWidth - 1) / RegWidth;
1177 : }
1178 0 : llvm_unreachable("Unsupported extended type!");
1179 : }
1180 :
1181 : /// Certain combinations of ABIs, Targets and features require that types
1182 : /// are legal for some operations and not for other operations.
1183 : /// For MIPS all vector types must be passed through the integer register set.
1184 290920 : virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1185 : CallingConv::ID CC, EVT VT) const {
1186 4876823 : return getRegisterType(Context, VT);
1187 : }
1188 :
1189 : /// Certain targets require unusual breakdowns of certain types. For MIPS,
1190 : /// this occurs when a vector type is used, as vector are passed through the
1191 : /// integer register set.
1192 290920 : virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1193 : CallingConv::ID CC,
1194 : EVT VT) const {
1195 4876657 : return getNumRegisters(Context, VT);
1196 : }
1197 :
1198 : /// Certain targets have context senstive alignment requirements, where one
1199 : /// type has the alignment requirement of another type.
1200 2522766 : virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1201 : DataLayout DL) const {
1202 2522766 : return DL.getABITypeAlignment(ArgTy);
1203 : }
1204 :
1205 : /// If true, then instruction selection should seek to shrink the FP constant
1206 : /// of the specified type to a smaller type in order to save space and / or
1207 : /// reduce runtime.
1208 292 : virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1209 :
1210 : // Return true if it is profitable to reduce the given load node to a smaller
1211 : // type.
1212 : //
1213 : // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1214 1013 : virtual bool shouldReduceLoadWidth(SDNode *Load,
1215 : ISD::LoadExtType ExtTy,
1216 : EVT NewVT) const {
1217 1013 : return true;
1218 : }
1219 :
1220 : /// When splitting a value of the specified type into parts, does the Lo
1221 : /// or Hi part come first? This usually follows the endianness, except
1222 : /// for ppcf128, where the Hi part always comes first.
1223 0 : bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1224 420747 : return DL.isBigEndian() || VT == MVT::ppcf128;
1225 : }
1226 :
1227 : /// If true, the target has custom DAG combine transformations that it can
1228 : /// perform for the specified node.
1229 : bool hasTargetDAGCombine(ISD::NodeType NT) const {
1230 : assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1231 80949613 : return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1232 : }
1233 :
1234 0 : unsigned getGatherAllAliasesMaxDepth() const {
1235 0 : return GatherAllAliasesMaxDepth;
1236 : }
1237 :
1238 : /// Returns the size of the platform's va_list object.
1239 0 : virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1240 0 : return getPointerTy(DL).getSizeInBits();
1241 : }
1242 :
1243 : /// Get maximum # of store operations permitted for llvm.memset
1244 : ///
1245 : /// This function returns the maximum number of store operations permitted
1246 : /// to replace a call to llvm.memset. The value is set by the target at the
1247 : /// performance threshold for such a replacement. If OptSize is true,
1248 : /// return the limit for functions that have OptSize attribute.
1249 : unsigned getMaxStoresPerMemset(bool OptSize) const {
1250 155690 : return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1251 : }
1252 :
1253 : /// Get maximum # of store operations permitted for llvm.memcpy
1254 : ///
1255 : /// This function returns the maximum number of store operations permitted
1256 : /// to replace a call to llvm.memcpy. The value is set by the target at the
1257 : /// performance threshold for such a replacement. If OptSize is true,
1258 : /// return the limit for functions that have OptSize attribute.
1259 : unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1260 101552 : return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1261 : }
1262 :
1263 : /// \brief Get maximum # of store operations to be glued together
1264 : ///
1265 : /// This function returns the maximum number of store operations permitted
1266 : /// to glue together during lowering of llvm.memcpy. The value is set by
1267 : // the target at the performance threshold for such a replacement.
1268 101185 : virtual unsigned getMaxGluedStoresPerMemcpy() const {
1269 101185 : return MaxGluedStoresPerMemcpy;
1270 : }
1271 :
1272 : /// Get maximum # of load operations permitted for memcmp
1273 : ///
1274 : /// This function returns the maximum number of load operations permitted
1275 : /// to replace a call to memcmp. The value is set by the target at the
1276 : /// performance threshold for such a replacement. If OptSize is true,
1277 : /// return the limit for functions that have OptSize attribute.
1278 : unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1279 395 : return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1280 : }
1281 :
1282 : /// For memcmp expansion when the memcmp result is only compared equal or
1283 : /// not-equal to 0, allow up to this number of load pairs per block. As an
1284 : /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1285 : /// a0 = load2bytes &a[0]
1286 : /// b0 = load2bytes &b[0]
1287 : /// a2 = load1byte &a[2]
1288 : /// b2 = load1byte &b[2]
1289 : /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1290 22 : virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1291 22 : return 1;
1292 : }
1293 :
1294 : /// Get maximum # of store operations permitted for llvm.memmove
1295 : ///
1296 : /// This function returns the maximum number of store operations permitted
1297 : /// to replace a call to llvm.memmove. The value is set by the target at the
1298 : /// performance threshold for such a replacement. If OptSize is true,
1299 : /// return the limit for functions that have OptSize attribute.
1300 : unsigned getMaxStoresPerMemmove(bool OptSize) const {
1301 84 : return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1302 : }
1303 :
1304 : /// Determine if the target supports unaligned memory accesses.
1305 : ///
1306 : /// This function returns true if the target allows unaligned memory accesses
1307 : /// of the specified type in the given address space. If true, it also returns
1308 : /// whether the unaligned memory access is "fast" in the last argument by
1309 : /// reference. This is used, for example, in situations where an array
1310 : /// copy/move/set is converted to a sequence of store operations. Its use
1311 : /// helps to ensure that such replacements don't generate code that causes an
1312 : /// alignment error (trap) on the target machine.
1313 1204 : virtual bool allowsMisalignedMemoryAccesses(EVT,
1314 : unsigned AddrSpace = 0,
1315 : unsigned Align = 1,
1316 : bool * /*Fast*/ = nullptr) const {
1317 1204 : return false;
1318 : }
1319 :
1320 : /// Return true if the target supports a memory access of this type for the
1321 : /// given address space and alignment. If the access is allowed, the optional
1322 : /// final parameter returns if the access is also fast (as defined by the
1323 : /// target).
1324 : bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1325 : unsigned AddrSpace = 0, unsigned Alignment = 1,
1326 : bool *Fast = nullptr) const;
1327 :
1328 : /// Returns the target specific optimal type for load and store operations as
1329 : /// a result of memset, memcpy, and memmove lowering.
1330 : ///
1331 : /// If DstAlign is zero that means it's safe to destination alignment can
1332 : /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1333 : /// a need to check it against alignment requirement, probably because the
1334 : /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1335 : /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1336 : /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1337 : /// does not need to be loaded. It returns EVT::Other if the type should be
1338 : /// determined using generic target-independent logic.
1339 149 : virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1340 : unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1341 : bool /*IsMemset*/,
1342 : bool /*ZeroMemset*/,
1343 : bool /*MemcpyStrSrc*/,
1344 : MachineFunction &/*MF*/) const {
1345 149 : return MVT::Other;
1346 : }
1347 :
1348 : /// Returns true if it's safe to use load / store of the specified type to
1349 : /// expand memcpy / memset inline.
1350 : ///
1351 : /// This is mostly true for all types except for some special cases. For
1352 : /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1353 : /// fstpl which also does type conversion. Note the specified type doesn't
1354 : /// have to be legal as the hook is used before type legalization.
1355 435 : virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1356 :
1357 : /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1358 0 : bool usesUnderscoreSetJmp() const {
1359 0 : return UseUnderscoreSetJmp;
1360 : }
1361 :
1362 : /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1363 0 : bool usesUnderscoreLongJmp() const {
1364 0 : return UseUnderscoreLongJmp;
1365 : }
1366 :
1367 : /// Return lower limit for number of blocks in a jump table.
1368 : virtual unsigned getMinimumJumpTableEntries() const;
1369 :
1370 : /// Return lower limit of the density in a jump table.
1371 : unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1372 :
1373 : /// Return upper limit for number of entries in a jump table.
1374 : /// Zero if no limit.
1375 : unsigned getMaximumJumpTableSize() const;
1376 :
1377 3124 : virtual bool isJumpTableRelative() const {
1378 3130 : return TM.isPositionIndependent();
1379 : }
1380 :
1381 : /// If a physical register, this specifies the register that
1382 : /// llvm.savestack/llvm.restorestack should save and restore.
1383 0 : unsigned getStackPointerRegisterToSaveRestore() const {
1384 0 : return StackPointerRegisterToSaveRestore;
1385 : }
1386 :
1387 : /// If a physical register, this returns the register that receives the
1388 : /// exception address on entry to an EH pad.
1389 : virtual unsigned
1390 0 : getExceptionPointerRegister(const Constant *PersonalityFn) const {
1391 : // 0 is guaranteed to be the NoRegister value on all targets
1392 0 : return 0;
1393 : }
1394 :
1395 : /// If a physical register, this returns the register that receives the
1396 : /// exception typeid on entry to a landing pad.
1397 : virtual unsigned
1398 0 : getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1399 : // 0 is guaranteed to be the NoRegister value on all targets
1400 0 : return 0;
1401 : }
1402 :
1403 0 : virtual bool needsFixedCatchObjects() const {
1404 0 : report_fatal_error("Funclet EH is not implemented for this target");
1405 : }
1406 :
1407 : /// Returns the target's jmp_buf size in bytes (if never set, the default is
1408 : /// 200)
1409 0 : unsigned getJumpBufSize() const {
1410 0 : return JumpBufSize;
1411 : }
1412 :
1413 : /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1414 : /// is 0)
1415 0 : unsigned getJumpBufAlignment() const {
1416 0 : return JumpBufAlignment;
1417 : }
1418 :
1419 : /// Return the minimum stack alignment of an argument.
1420 0 : unsigned getMinStackArgumentAlignment() const {
1421 0 : return MinStackArgumentAlignment;
1422 : }
1423 :
1424 : /// Return the minimum function alignment.
1425 0 : unsigned getMinFunctionAlignment() const {
1426 0 : return MinFunctionAlignment;
1427 : }
1428 :
1429 : /// Return the preferred function alignment.
1430 0 : unsigned getPrefFunctionAlignment() const {
1431 0 : return PrefFunctionAlignment;
1432 : }
1433 :
1434 : /// Return the preferred loop alignment.
1435 36734 : virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1436 37606 : return PrefLoopAlignment;
1437 : }
1438 :
1439 : /// Should loops be aligned even when the function is marked OptSize (but not
1440 : /// MinSize).
1441 147 : virtual bool alignLoopsWithOptSize() const {
1442 147 : return false;
1443 : }
1444 :
1445 : /// If the target has a standard location for the stack protector guard,
1446 : /// returns the address of that location. Otherwise, returns nullptr.
1447 : /// DEPRECATED: please override useLoadStackGuardNode and customize
1448 : /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1449 : virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1450 :
1451 : /// Inserts necessary declarations for SSP (stack protection) purpose.
1452 : /// Should be used only when getIRStackGuard returns nullptr.
1453 : virtual void insertSSPDeclarations(Module &M) const;
1454 :
1455 : /// Return the variable that's previously inserted by insertSSPDeclarations,
1456 : /// if any, otherwise return nullptr. Should be used only when
1457 : /// getIRStackGuard returns nullptr.
1458 : virtual Value *getSDagStackGuard(const Module &M) const;
1459 :
1460 : /// If this function returns true, stack protection checks should XOR the
1461 : /// frame pointer (or whichever pointer is used to address locals) into the
1462 : /// stack guard value before checking it. getIRStackGuard must return nullptr
1463 : /// if this returns true.
1464 197 : virtual bool useStackGuardXorFP() const { return false; }
1465 :
1466 : /// If the target has a standard stack protection check function that
1467 : /// performs validation and error handling, returns the function. Otherwise,
1468 : /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1469 : /// Should be used only when getIRStackGuard returns nullptr.
1470 : virtual Value *getSSPStackGuardCheck(const Module &M) const;
1471 :
1472 : protected:
1473 : Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1474 : bool UseTLS) const;
1475 :
1476 : public:
1477 : /// Returns the target-specific address of the unsafe stack pointer.
1478 : virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1479 :
1480 : /// Returns the name of the symbol used to emit stack probes or the empty
1481 : /// string if not applicable.
1482 0 : virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1483 0 : return "";
1484 : }
1485 :
1486 : /// Returns true if a cast between SrcAS and DestAS is a noop.
1487 465 : virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1488 465 : return false;
1489 : }
1490 :
1491 : /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1492 : /// are happy to sink it into basic blocks.
1493 200 : virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1494 200 : return isNoopAddrSpaceCast(SrcAS, DestAS);
1495 : }
1496 :
1497 : /// Return true if the pointer arguments to CI should be aligned by aligning
1498 : /// the object whose address is being passed. If so then MinSize is set to the
1499 : /// minimum size the object must be to be aligned and PrefAlign is set to the
1500 : /// preferred alignment.
1501 655820 : virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1502 : unsigned & /*PrefAlign*/) const {
1503 655820 : return false;
1504 : }
1505 :
1506 : //===--------------------------------------------------------------------===//
1507 : /// \name Helpers for TargetTransformInfo implementations
1508 : /// @{
1509 :
1510 : /// Get the ISD node that corresponds to the Instruction class opcode.
1511 : int InstructionOpcodeToISD(unsigned Opcode) const;
1512 :
1513 : /// Estimate the cost of type-legalization and the legalized type.
1514 : std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1515 : Type *Ty) const;
1516 :
1517 : /// @}
1518 :
1519 : //===--------------------------------------------------------------------===//
1520 : /// \name Helpers for atomic expansion.
1521 : /// @{
1522 :
1523 : /// Returns the maximum atomic operation size (in bits) supported by
1524 : /// the backend. Atomic operations greater than this size (as well
1525 : /// as ones that are not naturally aligned), will be expanded by
1526 : /// AtomicExpandPass into an __atomic_* library call.
1527 0 : unsigned getMaxAtomicSizeInBitsSupported() const {
1528 0 : return MaxAtomicSizeInBitsSupported;
1529 : }
1530 :
1531 : /// Returns the size of the smallest cmpxchg or ll/sc instruction
1532 : /// the backend supports. Any smaller operations are widened in
1533 : /// AtomicExpandPass.
1534 : ///
1535 : /// Note that *unlike* operations above the maximum size, atomic ops
1536 : /// are still natively supported below the minimum; they just
1537 : /// require a more complex expansion.
1538 0 : unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1539 :
1540 : /// Whether the target supports unaligned atomic operations.
1541 0 : bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1542 :
1543 : /// Whether AtomicExpandPass should automatically insert fences and reduce
1544 : /// ordering for this atomic. This should be true for most architectures with
1545 : /// weak memory ordering. Defaults to false.
1546 21866 : virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1547 21866 : return false;
1548 : }
1549 :
1550 : /// Perform a load-linked operation on Addr, returning a "Value *" with the
1551 : /// corresponding pointee type. This may entail some non-trivial operations to
1552 : /// truncate or reconstruct types that will be illegal in the backend. See
1553 : /// ARMISelLowering for an example implementation.
1554 0 : virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1555 : AtomicOrdering Ord) const {
1556 0 : llvm_unreachable("Load linked unimplemented on this target");
1557 : }
1558 :
1559 : /// Perform a store-conditional operation to Addr. Return the status of the
1560 : /// store. This should be 0 if the store succeeded, non-zero otherwise.
1561 0 : virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1562 : Value *Addr, AtomicOrdering Ord) const {
1563 0 : llvm_unreachable("Store conditional unimplemented on this target");
1564 : }
1565 :
1566 : /// Perform a masked atomicrmw using a target-specific intrinsic. This
1567 : /// represents the core LL/SC loop which will be lowered at a late stage by
1568 : /// the backend.
1569 0 : virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1570 : AtomicRMWInst *AI,
1571 : Value *AlignedAddr, Value *Incr,
1572 : Value *Mask, Value *ShiftAmt,
1573 : AtomicOrdering Ord) const {
1574 0 : llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1575 : }
1576 :
1577 : /// Perform a masked cmpxchg using a target-specific intrinsic. This
1578 : /// represents the core LL/SC loop which will be lowered at a late stage by
1579 : /// the backend.
1580 0 : virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1581 : IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1582 : Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1583 0 : llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1584 : }
1585 :
1586 : /// Inserts in the IR a target-specific intrinsic specifying a fence.
1587 : /// It is called by AtomicExpandPass before expanding an
1588 : /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1589 : /// if shouldInsertFencesForAtomic returns true.
1590 : ///
1591 : /// Inst is the original atomic instruction, prior to other expansions that
1592 : /// may be performed.
1593 : ///
1594 : /// This function should either return a nullptr, or a pointer to an IR-level
1595 : /// Instruction*. Even complex fence sequences can be represented by a
1596 : /// single Instruction* through an intrinsic to be lowered later.
1597 : /// Backends should override this method to produce target-specific intrinsic
1598 : /// for their fences.
1599 : /// FIXME: Please note that the default implementation here in terms of
1600 : /// IR-level fences exists for historical/compatibility reasons and is
1601 : /// *unsound* ! Fences cannot, in general, be used to restore sequential
1602 : /// consistency. For example, consider the following example:
1603 : /// atomic<int> x = y = 0;
1604 : /// int r1, r2, r3, r4;
1605 : /// Thread 0:
1606 : /// x.store(1);
1607 : /// Thread 1:
1608 : /// y.store(1);
1609 : /// Thread 2:
1610 : /// r1 = x.load();
1611 : /// r2 = y.load();
1612 : /// Thread 3:
1613 : /// r3 = y.load();
1614 : /// r4 = x.load();
1615 : /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1616 : /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1617 : /// IR-level fences can prevent it.
1618 : /// @{
1619 127 : virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1620 : AtomicOrdering Ord) const {
1621 127 : if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1622 94 : return Builder.CreateFence(Ord);
1623 : else
1624 33 : return nullptr;
1625 : }
1626 :
1627 127 : virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1628 : Instruction *Inst,
1629 : AtomicOrdering Ord) const {
1630 127 : if (isAcquireOrStronger(Ord))
1631 104 : return Builder.CreateFence(Ord);
1632 : else
1633 : return nullptr;
1634 : }
1635 : /// @}
1636 :
1637 : // Emits code that executes when the comparison result in the ll/sc
1638 : // expansion of a cmpxchg instruction is such that the store-conditional will
1639 : // not execute. This makes it possible to balance out the load-linked with
1640 : // a dedicated instruction, if desired.
1641 : // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1642 : // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1643 3 : virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1644 :
1645 : /// Returns true if the given (atomic) store should be expanded by the
1646 : /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1647 271 : virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1648 271 : return false;
1649 : }
1650 :
1651 : /// Returns true if arguments should be sign-extended in lib calls.
1652 26729 : virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1653 26729 : return IsSigned;
1654 : }
1655 :
1656 : /// Returns how the given (atomic) load should be expanded by the
1657 : /// IR-level AtomicExpand pass.
1658 301 : virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1659 301 : return AtomicExpansionKind::None;
1660 : }
1661 :
1662 : /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1663 : /// AtomicExpand pass.
1664 : virtual AtomicExpansionKind
1665 4577 : shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1666 4577 : return AtomicExpansionKind::None;
1667 : }
1668 :
1669 : /// Returns how the IR-level AtomicExpand pass should expand the given
1670 : /// AtomicRMW, if at all. Default is to never expand.
1671 786 : virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1672 786 : return AtomicExpansionKind::None;
1673 : }
1674 :
1675 : /// On some platforms, an AtomicRMW that never actually modifies the value
1676 : /// (such as fetch_add of 0) can be turned into a fence followed by an
1677 : /// atomic load. This may sound useless, but it makes it possible for the
1678 : /// processor to keep the cacheline shared, dramatically improving
1679 : /// performance. And such idempotent RMWs are useful for implementing some
1680 : /// kinds of locks, see for example (justification + benchmarks):
1681 : /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1682 : /// This method tries doing that transformation, returning the atomic load if
1683 : /// it succeeds, and nullptr otherwise.
1684 : /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1685 : /// another round of expansion.
1686 : virtual LoadInst *
1687 0 : lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1688 0 : return nullptr;
1689 : }
1690 :
1691 : /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1692 : /// SIGN_EXTEND, or ANY_EXTEND).
1693 5742 : virtual ISD::NodeType getExtendForAtomicOps() const {
1694 5742 : return ISD::ZERO_EXTEND;
1695 : }
1696 :
1697 : /// @}
1698 :
1699 : /// Returns true if we should normalize
1700 : /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1701 : /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1702 : /// that it saves us from materializing N0 and N1 in an integer register.
1703 : /// Targets that are able to perform and/or on flags should return false here.
1704 21577 : virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1705 : EVT VT) const {
1706 : // If a target has multiple condition registers, then it likely has logical
1707 : // operations on those registers.
1708 21577 : if (hasMultipleConditionRegisters())
1709 : return false;
1710 : // Only do the transform if the value won't be split into multiple
1711 : // registers.
1712 8809 : LegalizeTypeAction Action = getTypeAction(Context, VT);
1713 8809 : return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1714 : Action != TypeSplitVector;
1715 : }
1716 :
1717 : /// Return true if a select of constants (select Cond, C1, C2) should be
1718 : /// transformed into simple math ops with the condition value. For example:
1719 : /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1720 2324 : virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1721 2324 : return false;
1722 : }
1723 :
1724 : /// Return true if it is profitable to transform an integer
1725 : /// multiplication-by-constant into simpler operations like shifts and adds.
1726 : /// This may be true if the target does not directly support the
1727 : /// multiplication operation for the specified type or the sequence of simpler
1728 : /// ops is faster than the multiply.
1729 1665 : virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1730 1665 : return false;
1731 : }
1732 :
1733 : //===--------------------------------------------------------------------===//
1734 : // TargetLowering Configuration Methods - These methods should be invoked by
1735 : // the derived class constructor to configure this object for the target.
1736 : //
1737 : protected:
1738 : /// Specify how the target extends the result of integer and floating point
1739 : /// boolean values from i1 to a wider type. See getBooleanContents.
1740 0 : void setBooleanContents(BooleanContent Ty) {
1741 41316 : BooleanContents = Ty;
1742 41316 : BooleanFloatContents = Ty;
1743 0 : }
1744 :
1745 : /// Specify how the target extends the result of integer and floating point
1746 : /// boolean values from i1 to a wider type. See getBooleanContents.
1747 0 : void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1748 0 : BooleanContents = IntTy;
1749 1345 : BooleanFloatContents = FloatTy;
1750 0 : }
1751 :
1752 : /// Specify how the target extends the result of a vector boolean value from a
1753 : /// vector of i1 to a wider type. See getBooleanContents.
1754 0 : void setBooleanVectorContents(BooleanContent Ty) {
1755 40331 : BooleanVectorContents = Ty;
1756 0 : }
1757 :
1758 : /// Specify the target scheduling preference.
1759 0 : void setSchedulingPreference(Sched::Preference Pref) {
1760 33203 : SchedPreferenceInfo = Pref;
1761 0 : }
1762 :
1763 : /// Indicate whether this target prefers to use _setjmp to implement
1764 : /// llvm.setjmp or the version without _. Defaults to false.
1765 : void setUseUnderscoreSetJmp(bool Val) {
1766 17920 : UseUnderscoreSetJmp = Val;
1767 : }
1768 :
1769 : /// Indicate whether this target prefers to use _longjmp to implement
1770 : /// llvm.longjmp or the version without _. Defaults to false.
1771 : void setUseUnderscoreLongJmp(bool Val) {
1772 17920 : UseUnderscoreLongJmp = Val;
1773 : }
1774 :
1775 : /// Indicate the minimum number of blocks to generate jump tables.
1776 : void setMinimumJumpTableEntries(unsigned Val);
1777 :
1778 : /// Indicate the maximum number of entries in jump tables.
1779 : /// Set to zero to generate unlimited jump tables.
1780 : void setMaximumJumpTableSize(unsigned);
1781 :
1782 : /// If set to a physical register, this specifies the register that
1783 : /// llvm.savestack/llvm.restorestack should save and restore.
1784 0 : void setStackPointerRegisterToSaveRestore(unsigned R) {
1785 37878 : StackPointerRegisterToSaveRestore = R;
1786 0 : }
1787 :
1788 : /// Tells the code generator that the target has multiple (allocatable)
1789 : /// condition registers that can be used to store the results of comparisons
1790 : /// for use by selects and conditional branches. With multiple condition
1791 : /// registers, the code generator will not aggressively sink comparisons into
1792 : /// the blocks of their users.
1793 : void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1794 4205 : HasMultipleConditionRegisters = hasManyRegs;
1795 : }
1796 :
1797 : /// Tells the code generator that the target has BitExtract instructions.
1798 : /// The code generator will aggressively sink "shift"s into the blocks of
1799 : /// their users if the users will generate "and" instructions which can be
1800 : /// combined with "shift" to BitExtract instructions.
1801 : void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1802 4323 : HasExtractBitsInsn = hasExtractInsn;
1803 : }
1804 :
1805 : /// Tells the code generator not to expand logic operations on comparison
1806 : /// predicates into separate sequences that increase the amount of flow
1807 : /// control.
1808 : void setJumpIsExpensive(bool isExpensive = true);
1809 :
1810 : /// Tells the code generator that this target supports floating point
1811 : /// exceptions and cares about preserving floating point exception behavior.
1812 : void setHasFloatingPointExceptions(bool FPExceptions = true) {
1813 2785 : HasFloatingPointExceptions = FPExceptions;
1814 : }
1815 :
1816 : /// Tells the code generator which bitwidths to bypass.
1817 : void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1818 1205 : BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1819 : }
1820 :
1821 : /// Add the specified register class as an available regclass for the
1822 : /// specified value type. This indicates the selector can handle values of
1823 : /// that class natively.
1824 : void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1825 : assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1826 233241 : RegClassForVT[VT.SimpleTy] = RC;
1827 : }
1828 :
1829 : /// Return the largest legal super-reg register class of the register class
1830 : /// for the specified type and its associated "cost".
1831 : virtual std::pair<const TargetRegisterClass *, uint8_t>
1832 : findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1833 :
1834 : /// Once all of the register classes are added, this allows us to compute
1835 : /// derived properties we expose.
1836 : void computeRegisterProperties(const TargetRegisterInfo *TRI);
1837 :
1838 : /// Indicate that the specified operation does not work with the specified
1839 : /// type and indicate what to do about it. Note that VT may refer to either
1840 : /// the type of a result or that of an operand of Op.
1841 : void setOperationAction(unsigned Op, MVT VT,
1842 : LegalizeAction Action) {
1843 : assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1844 44993341 : OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1845 : }
1846 :
1847 : /// Indicate that the specified load with extension does not work with the
1848 : /// specified type and indicate what to do about it.
1849 : void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1850 : LegalizeAction Action) {
1851 : assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1852 : MemVT.isValid() && "Table isn't big enough!");
1853 : assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1854 22188 : unsigned Shift = 4 * ExtType;
1855 627929693 : LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1856 62857719 : LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1857 : }
1858 :
1859 : /// Indicate that the specified truncating store does not work with the
1860 : /// specified type and indicate what to do about it.
1861 : void setTruncStoreAction(MVT ValVT, MVT MemVT,
1862 : LegalizeAction Action) {
1863 : assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1864 241039304 : TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1865 : }
1866 :
1867 : /// Indicate that the specified indexed load does or does not work with the
1868 : /// specified type and indicate what to do abort it.
1869 : ///
1870 : /// NOTE: All indexed mode loads are initialized to Expand in
1871 : /// TargetLowering.cpp
1872 : void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1873 : LegalizeAction Action) {
1874 : assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1875 : (unsigned)Action < 0xf && "Table isn't big enough!");
1876 : // Load action are kept in the upper half.
1877 18890003 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1878 116728 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1879 : }
1880 :
1881 : /// Indicate that the specified indexed store does or does not work with the
1882 : /// specified type and indicate what to do about it.
1883 : ///
1884 : /// NOTE: All indexed mode stores are initialized to Expand in
1885 : /// TargetLowering.cpp
1886 : void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1887 : LegalizeAction Action) {
1888 : assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1889 : (unsigned)Action < 0xf && "Table isn't big enough!");
1890 : // Store action are kept in the lower half.
1891 116664 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1892 18799974 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1893 : }
1894 :
1895 : /// Indicate that the specified condition code is or isn't supported on the
1896 : /// target and indicate what to do about it.
1897 : void setCondCodeAction(ISD::CondCode CC, MVT VT,
1898 : LegalizeAction Action) {
1899 : assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1900 : "Table isn't big enough!");
1901 : assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1902 : /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1903 : /// value and the upper 29 bits index into the second dimension of the array
1904 : /// to select what 32-bit value to use.
1905 94113 : uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1906 345793 : CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1907 112510 : CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1908 : }
1909 :
1910 : /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1911 : /// to trying a larger integer/fp until it can find one that works. If that
1912 : /// default is insufficient, this method can be used by the target to override
1913 : /// the default.
1914 : void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1915 348788 : PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1916 : }
1917 :
1918 : /// Convenience method to set an operation to Promote and specify the type
1919 : /// in a single call.
1920 : void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1921 : setOperationAction(Opc, OrigVT, Promote);
1922 : AddPromotedToType(Opc, OrigVT, DestVT);
1923 : }
1924 :
1925 : /// Targets should invoke this method for each target independent node that
1926 : /// they want to provide a custom DAG combiner for by implementing the
1927 : /// PerformDAGCombine virtual method.
1928 : void setTargetDAGCombine(ISD::NodeType NT) {
1929 : assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1930 55138 : TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1931 : }
1932 :
1933 : /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1934 : void setJumpBufSize(unsigned Size) {
1935 : JumpBufSize = Size;
1936 : }
1937 :
1938 : /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1939 : /// 0
1940 : void setJumpBufAlignment(unsigned Align) {
1941 : JumpBufAlignment = Align;
1942 : }
1943 :
1944 : /// Set the target's minimum function alignment (in log2(bytes))
1945 0 : void setMinFunctionAlignment(unsigned Align) {
1946 21302 : MinFunctionAlignment = Align;
1947 0 : }
1948 :
1949 : /// Set the target's preferred function alignment. This should be set if
1950 : /// there is a performance benefit to higher-than-minimum alignment (in
1951 : /// log2(bytes))
1952 0 : void setPrefFunctionAlignment(unsigned Align) {
1953 20042 : PrefFunctionAlignment = Align;
1954 0 : }
1955 :
1956 : /// Set the target's preferred loop alignment. Default alignment is zero, it
1957 : /// means the target does not care about loop alignment. The alignment is
1958 : /// specified in log2(bytes). The target may also override
1959 : /// getPrefLoopAlignment to provide per-loop values.
1960 0 : void setPrefLoopAlignment(unsigned Align) {
1961 24970 : PrefLoopAlignment = Align;
1962 0 : }
1963 :
1964 : /// Set the minimum stack alignment of an argument (in log2(bytes)).
1965 0 : void setMinStackArgumentAlignment(unsigned Align) {
1966 17005 : MinStackArgumentAlignment = Align;
1967 0 : }
1968 :
1969 : /// Set the maximum atomic operation size supported by the
1970 : /// backend. Atomic operations greater than this size (as well as
1971 : /// ones that are not naturally aligned), will be expanded by
1972 : /// AtomicExpandPass into an __atomic_* library call.
1973 0 : void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1974 1704 : MaxAtomicSizeInBitsSupported = SizeInBits;
1975 0 : }
1976 :
1977 : /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1978 0 : void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1979 1411 : MinCmpXchgSizeInBits = SizeInBits;
1980 0 : }
1981 :
1982 : /// Sets whether unaligned atomic operations are supported.
1983 : void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1984 119 : SupportsUnalignedAtomics = UnalignedSupported;
1985 : }
1986 :
1987 : public:
1988 : //===--------------------------------------------------------------------===//
1989 : // Addressing mode description hooks (used by LSR etc).
1990 : //
1991 :
1992 : /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1993 : /// instructions reading the address. This allows as much computation as
1994 : /// possible to be done in the address mode for that operand. This hook lets
1995 : /// targets also pass back when this should be done on intrinsics which
1996 : /// load/store.
1997 468699 : virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1998 : SmallVectorImpl<Value*> &/*Ops*/,
1999 : Type *&/*AccessTy*/) const {
2000 468699 : return false;
2001 : }
2002 :
2003 : /// This represents an addressing mode of:
2004 : /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2005 : /// If BaseGV is null, there is no BaseGV.
2006 : /// If BaseOffs is zero, there is no base offset.
2007 : /// If HasBaseReg is false, there is no base register.
2008 : /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2009 : /// no scale.
2010 : struct AddrMode {
2011 : GlobalValue *BaseGV = nullptr;
2012 : int64_t BaseOffs = 0;
2013 : bool HasBaseReg = false;
2014 : int64_t Scale = 0;
2015 : AddrMode() = default;
2016 : };
2017 :
2018 : /// Return true if the addressing mode represented by AM is legal for this
2019 : /// target, for a load/store of the specified type.
2020 : ///
2021 : /// The type may be VoidTy, in which case only return true if the addressing
2022 : /// mode is legal for a load/store of any legal type. TODO: Handle
2023 : /// pre/postinc as well.
2024 : ///
2025 : /// If the address space cannot be determined, it will be -1.
2026 : ///
2027 : /// TODO: Remove default argument
2028 : virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2029 : Type *Ty, unsigned AddrSpace,
2030 : Instruction *I = nullptr) const;
2031 :
2032 : /// Return the cost of the scaling factor used in the addressing mode
2033 : /// represented by AM for this target, for a load/store of the specified type.
2034 : ///
2035 : /// If the AM is supported, the return value must be >= 0.
2036 : /// If the AM is not supported, it returns a negative value.
2037 : /// TODO: Handle pre/postinc as well.
2038 : /// TODO: Remove default argument
2039 7566 : virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2040 : Type *Ty, unsigned AS = 0) const {
2041 : // Default: assume that any scaling factor used in a legal AM is free.
2042 7566 : if (isLegalAddressingMode(DL, AM, Ty, AS))
2043 7566 : return 0;
2044 : return -1;
2045 : }
2046 :
2047 : /// Return true if the specified immediate is legal icmp immediate, that is
2048 : /// the target has icmp instructions which can compare a register against the
2049 : /// immediate without having to materialize the immediate into a register.
2050 36705 : virtual bool isLegalICmpImmediate(int64_t) const {
2051 36705 : return true;
2052 : }
2053 :
2054 : /// Return true if the specified immediate is legal add immediate, that is the
2055 : /// target has add instructions which can add a register with the immediate
2056 : /// without having to materialize the immediate into a register.
2057 1593 : virtual bool isLegalAddImmediate(int64_t) const {
2058 1593 : return true;
2059 : }
2060 :
2061 : /// Return true if it's significantly cheaper to shift a vector by a uniform
2062 : /// scalar than by an amount which will vary across each lane. On x86, for
2063 : /// example, there is a "psllw" instruction for the former case, but no simple
2064 : /// instruction for a general "a << b" operation on vectors.
2065 7127 : virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2066 7127 : return false;
2067 : }
2068 :
2069 : /// Returns true if the opcode is a commutative binary operation.
2070 105058847 : virtual bool isCommutativeBinOp(unsigned Opcode) const {
2071 : // FIXME: This should get its info from the td file.
2072 105058847 : switch (Opcode) {
2073 : case ISD::ADD:
2074 : case ISD::SMIN:
2075 : case ISD::SMAX:
2076 : case ISD::UMIN:
2077 : case ISD::UMAX:
2078 : case ISD::MUL:
2079 : case ISD::MULHU:
2080 : case ISD::MULHS:
2081 : case ISD::SMUL_LOHI:
2082 : case ISD::UMUL_LOHI:
2083 : case ISD::FADD:
2084 : case ISD::FMUL:
2085 : case ISD::AND:
2086 : case ISD::OR:
2087 : case ISD::XOR:
2088 : case ISD::SADDO:
2089 : case ISD::UADDO:
2090 : case ISD::ADDC:
2091 : case ISD::ADDE:
2092 : case ISD::FMINNUM:
2093 : case ISD::FMAXNUM:
2094 : case ISD::FMINNAN:
2095 : case ISD::FMAXNAN:
2096 : return true;
2097 91629879 : default: return false;
2098 : }
2099 : }
2100 :
2101 : /// Return true if it's free to truncate a value of type FromTy to type
2102 : /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2103 : /// by referencing its sub-register AX.
2104 : /// Targets must return false when FromTy <= ToTy.
2105 229 : virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2106 229 : return false;
2107 : }
2108 :
2109 : /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2110 : /// whether a call is in tail position. Typically this means that both results
2111 : /// would be assigned to the same register or stack slot, but it could mean
2112 : /// the target performs adequate checks of its own before proceeding with the
2113 : /// tail call. Targets must return false when FromTy <= ToTy.
2114 2 : virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2115 2 : return false;
2116 : }
2117 :
2118 13375 : virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2119 13375 : return false;
2120 : }
2121 :
2122 5806 : virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2123 :
2124 : /// Return true if the extension represented by \p I is free.
2125 : /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2126 : /// this method can use the context provided by \p I to decide
2127 : /// whether or not \p I is free.
2128 : /// This method extends the behavior of the is[Z|FP]ExtFree family.
2129 : /// In other words, if is[Z|FP]Free returns true, then this method
2130 : /// returns true as well. The converse is not true.
2131 : /// The target can perform the adequate checks by overriding isExtFreeImpl.
2132 : /// \pre \p I must be a sign, zero, or fp extension.
2133 45258 : bool isExtFree(const Instruction *I) const {
2134 45258 : switch (I->getOpcode()) {
2135 50 : case Instruction::FPExt:
2136 50 : if (isFPExtFree(EVT::getEVT(I->getType()),
2137 50 : EVT::getEVT(I->getOperand(0)->getType())))
2138 : return true;
2139 : break;
2140 31562 : case Instruction::ZExt:
2141 63124 : if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2142 : return true;
2143 : break;
2144 : case Instruction::SExt:
2145 : break;
2146 0 : default:
2147 0 : llvm_unreachable("Instruction is not an extension");
2148 : }
2149 37659 : return isExtFreeImpl(I);
2150 : }
2151 :
2152 : /// Return true if \p Load and \p Ext can form an ExtLoad.
2153 : /// For example, in AArch64
2154 : /// %L = load i8, i8* %ptr
2155 : /// %E = zext i8 %L to i32
2156 : /// can be lowered into one load instruction
2157 : /// ldrb w0, [x0]
2158 12466 : bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2159 : const DataLayout &DL) const {
2160 12466 : EVT VT = getValueType(DL, Ext->getType());
2161 12466 : EVT LoadVT = getValueType(DL, Load->getType());
2162 :
2163 : // If the load has other users and the truncate is not free, the ext
2164 : // probably isn't free.
2165 16400 : if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2166 3934 : !isTruncateFree(Ext->getType(), Load->getType()))
2167 : return false;
2168 :
2169 : // Check whether the target supports casts folded into loads.
2170 : unsigned LType;
2171 12466 : if (isa<ZExtInst>(Ext))
2172 : LType = ISD::ZEXTLOAD;
2173 : else {
2174 : assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2175 : LType = ISD::SEXTLOAD;
2176 : }
2177 :
2178 12466 : return isLoadExtLegal(LType, VT, LoadVT);
2179 : }
2180 :
2181 : /// Return true if any actual instruction that defines a value of type FromTy
2182 : /// implicitly zero-extends the value to ToTy in the result register.
2183 : ///
2184 : /// The function should return true when it is likely that the truncate can
2185 : /// be freely folded with an instruction defining a value of FromTy. If
2186 : /// the defining instruction is unknown (because you're looking at a
2187 : /// function argument, PHI, etc.) then the target may require an
2188 : /// explicit truncate, which is not necessarily free, but this function
2189 : /// does not deal with those cases.
2190 : /// Targets must return false when FromTy >= ToTy.
2191 338 : virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2192 338 : return false;
2193 : }
2194 :
2195 16819 : virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2196 16819 : return false;
2197 : }
2198 :
2199 : /// Return true if the target supplies and combines to a paired load
2200 : /// two loaded values of type LoadedType next to each other in memory.
2201 : /// RequiredAlignment gives the minimal alignment constraints that must be met
2202 : /// to be able to select this paired load.
2203 : ///
2204 : /// This information is *not* used to generate actual paired loads, but it is
2205 : /// used to generate a sequence of loads that is easier to combine into a
2206 : /// paired load.
2207 : /// For instance, something like this:
2208 : /// a = load i64* addr
2209 : /// b = trunc i64 a to i32
2210 : /// c = lshr i64 a, 32
2211 : /// d = trunc i64 c to i32
2212 : /// will be optimized into:
2213 : /// b = load i32* addr1
2214 : /// d = load i32* addr2
2215 : /// Where addr1 = addr2 +/- sizeof(i32).
2216 : ///
2217 : /// In other words, unless the target performs a post-isel load combining,
2218 : /// this information should not be provided because it will generate more
2219 : /// loads.
2220 7637 : virtual bool hasPairedLoad(EVT /*LoadedType*/,
2221 : unsigned & /*RequiredAlignment*/) const {
2222 7637 : return false;
2223 : }
2224 :
2225 : /// Return true if the target has a vector blend instruction.
2226 9664 : virtual bool hasVectorBlend() const { return false; }
2227 :
2228 : /// Get the maximum supported factor for interleaved memory accesses.
2229 : /// Default to be the minimum interleave factor: 2.
2230 0 : virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2231 :
2232 : /// Lower an interleaved load to target specific intrinsics. Return
2233 : /// true on success.
2234 : ///
2235 : /// \p LI is the vector load instruction.
2236 : /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2237 : /// \p Indices is the corresponding indices for each shufflevector.
2238 : /// \p Factor is the interleave factor.
2239 0 : virtual bool lowerInterleavedLoad(LoadInst *LI,
2240 : ArrayRef<ShuffleVectorInst *> Shuffles,
2241 : ArrayRef<unsigned> Indices,
2242 : unsigned Factor) const {
2243 0 : return false;
2244 : }
2245 :
2246 : /// Lower an interleaved store to target specific intrinsics. Return
2247 : /// true on success.
2248 : ///
2249 : /// \p SI is the vector store instruction.
2250 : /// \p SVI is the shufflevector to RE-interleave the stored vector.
2251 : /// \p Factor is the interleave factor.
2252 0 : virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2253 : unsigned Factor) const {
2254 0 : return false;
2255 : }
2256 :
2257 : /// Return true if zero-extending the specific node Val to type VT2 is free
2258 : /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2259 : /// because it's folded such as X86 zero-extending loads).
2260 11559 : virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2261 29356 : return isZExtFree(Val.getValueType(), VT2);
2262 : }
2263 :
2264 : /// Return true if an fpext operation is free (for instance, because
2265 : /// single-precision floating-point numbers are implicitly extended to
2266 : /// double-precision).
2267 357 : virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2268 : assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2269 : "invalid fpext types");
2270 357 : return false;
2271 : }
2272 :
2273 : /// Return true if an fpext operation input to an \p Opcode operation is free
2274 : /// (for instance, because half-precision floating-point numbers are
2275 : /// implicitly extended to float-precision) for an FMA instruction.
2276 44 : virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2277 : assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2278 : "invalid fpext types");
2279 44 : return isFPExtFree(DestVT, SrcVT);
2280 : }
2281 :
2282 : /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2283 : /// extend node) is profitable.
2284 3457 : virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2285 :
2286 : /// Return true if an fneg operation is free to the point where it is never
2287 : /// worthwhile to replace it with a bitwise operation.
2288 2314 : virtual bool isFNegFree(EVT VT) const {
2289 : assert(VT.isFloatingPoint());
2290 2314 : return false;
2291 : }
2292 :
2293 : /// Return true if an fabs operation is free to the point where it is never
2294 : /// worthwhile to replace it with a bitwise operation.
2295 3239 : virtual bool isFAbsFree(EVT VT) const {
2296 : assert(VT.isFloatingPoint());
2297 3239 : return false;
2298 : }
2299 :
2300 : /// Return true if an FMA operation is faster than a pair of fmul and fadd
2301 : /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2302 : /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2303 : ///
2304 : /// NOTE: This may be called before legalization on types for which FMAs are
2305 : /// not legal, but should return true if those types will eventually legalize
2306 : /// to types that support FMAs. After legalization, it will only be called on
2307 : /// types that support FMAs (via Legal or Custom actions)
2308 4977 : virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2309 4977 : return false;
2310 : }
2311 :
2312 : /// Return true if it's profitable to narrow operations of type VT1 to
2313 : /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2314 : /// i32 to i16.
2315 274 : virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2316 274 : return false;
2317 : }
2318 :
2319 : /// Return true if it is beneficial to convert a load of a constant to
2320 : /// just the constant itself.
2321 : /// On some targets it might be more efficient to use a combination of
2322 : /// arithmetic instructions to materialize the constant instead of loading it
2323 : /// from a constant pool.
2324 12 : virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2325 : Type *Ty) const {
2326 12 : return false;
2327 : }
2328 :
2329 : /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2330 : /// from this source type with this index. This is needed because
2331 : /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2332 : /// the first element, and only the target knows which lowering is cheap.
2333 59 : virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2334 : unsigned Index) const {
2335 59 : return false;
2336 : }
2337 :
2338 : // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2339 : // even if the vector itself has multiple uses.
2340 701 : virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2341 701 : return false;
2342 : }
2343 :
2344 : // Return true if CodeGenPrepare should consider splitting large offset of a
2345 : // GEP to make the GEP fit into the addressing mode and can be sunk into the
2346 : // same blocks of its users.
2347 3268 : virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2348 :
2349 : //===--------------------------------------------------------------------===//
2350 : // Runtime Library hooks
2351 : //
2352 :
2353 : /// Rename the default libcall routine name for the specified libcall.
2354 : void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2355 1715369 : LibcallRoutineNames[Call] = Name;
2356 : }
2357 :
2358 : /// Get the libcall routine name for the specified libcall.
2359 : const char *getLibcallName(RTLIB::Libcall Call) const {
2360 60913 : return LibcallRoutineNames[Call];
2361 : }
2362 :
2363 : /// Override the default CondCode to be used to test the result of the
2364 : /// comparison libcall against zero.
2365 : void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2366 60160 : CmpLibcallCCs[Call] = CC;
2367 : }
2368 :
2369 : /// Get the CondCode that's to be used to test the result of the comparison
2370 : /// libcall against zero.
2371 : ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2372 347 : return CmpLibcallCCs[Call];
2373 : }
2374 :
2375 : /// Set the CallingConv that should be used for the specified libcall.
2376 : void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2377 21671365 : LibcallCallingConvs[Call] = CC;
2378 : }
2379 :
2380 : /// Get the CallingConv that should be used for the specified libcall.
2381 : CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2382 52164 : return LibcallCallingConvs[Call];
2383 : }
2384 :
2385 : /// Execute target specific actions to finalize target lowering.
2386 : /// This is used to set extra flags in MachineFrameInformation and freezing
2387 : /// the set of reserved registers.
2388 : /// The default implementation just freezes the set of reserved registers.
2389 : virtual void finalizeLowering(MachineFunction &MF) const;
2390 :
2391 : private:
2392 : const TargetMachine &TM;
2393 :
2394 : /// Tells the code generator that the target has multiple (allocatable)
2395 : /// condition registers that can be used to store the results of comparisons
2396 : /// for use by selects and conditional branches. With multiple condition
2397 : /// registers, the code generator will not aggressively sink comparisons into
2398 : /// the blocks of their users.
2399 : bool HasMultipleConditionRegisters;
2400 :
2401 : /// Tells the code generator that the target has BitExtract instructions.
2402 : /// The code generator will aggressively sink "shift"s into the blocks of
2403 : /// their users if the users will generate "and" instructions which can be
2404 : /// combined with "shift" to BitExtract instructions.
2405 : bool HasExtractBitsInsn;
2406 :
2407 : /// Tells the code generator to bypass slow divide or remainder
2408 : /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2409 : /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2410 : /// div/rem when the operands are positive and less than 256.
2411 : DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2412 :
2413 : /// Tells the code generator that it shouldn't generate extra flow control
2414 : /// instructions and should attempt to combine flow control instructions via
2415 : /// predication.
2416 : bool JumpIsExpensive;
2417 :
2418 : /// Whether the target supports or cares about preserving floating point
2419 : /// exception behavior.
2420 : bool HasFloatingPointExceptions;
2421 :
2422 : /// This target prefers to use _setjmp to implement llvm.setjmp.
2423 : ///
2424 : /// Defaults to false.
2425 : bool UseUnderscoreSetJmp;
2426 :
2427 : /// This target prefers to use _longjmp to implement llvm.longjmp.
2428 : ///
2429 : /// Defaults to false.
2430 : bool UseUnderscoreLongJmp;
2431 :
2432 : /// Information about the contents of the high-bits in boolean values held in
2433 : /// a type wider than i1. See getBooleanContents.
2434 : BooleanContent BooleanContents;
2435 :
2436 : /// Information about the contents of the high-bits in boolean values held in
2437 : /// a type wider than i1. See getBooleanContents.
2438 : BooleanContent BooleanFloatContents;
2439 :
2440 : /// Information about the contents of the high-bits in boolean vector values
2441 : /// when the element type is wider than i1. See getBooleanContents.
2442 : BooleanContent BooleanVectorContents;
2443 :
2444 : /// The target scheduling preference: shortest possible total cycles or lowest
2445 : /// register usage.
2446 : Sched::Preference SchedPreferenceInfo;
2447 :
2448 : /// The size, in bytes, of the target's jmp_buf buffers
2449 : unsigned JumpBufSize;
2450 :
2451 : /// The alignment, in bytes, of the target's jmp_buf buffers
2452 : unsigned JumpBufAlignment;
2453 :
2454 : /// The minimum alignment that any argument on the stack needs to have.
2455 : unsigned MinStackArgumentAlignment;
2456 :
2457 : /// The minimum function alignment (used when optimizing for size, and to
2458 : /// prevent explicitly provided alignment from leading to incorrect code).
2459 : unsigned MinFunctionAlignment;
2460 :
2461 : /// The preferred function alignment (used when alignment unspecified and
2462 : /// optimizing for speed).
2463 : unsigned PrefFunctionAlignment;
2464 :
2465 : /// The preferred loop alignment.
2466 : unsigned PrefLoopAlignment;
2467 :
2468 : /// Size in bits of the maximum atomics size the backend supports.
2469 : /// Accesses larger than this will be expanded by AtomicExpandPass.
2470 : unsigned MaxAtomicSizeInBitsSupported;
2471 :
2472 : /// Size in bits of the minimum cmpxchg or ll/sc operation the
2473 : /// backend supports.
2474 : unsigned MinCmpXchgSizeInBits;
2475 :
2476 : /// This indicates if the target supports unaligned atomic operations.
2477 : bool SupportsUnalignedAtomics;
2478 :
2479 : /// If set to a physical register, this specifies the register that
2480 : /// llvm.savestack/llvm.restorestack should save and restore.
2481 : unsigned StackPointerRegisterToSaveRestore;
2482 :
2483 : /// This indicates the default register class to use for each ValueType the
2484 : /// target supports natively.
2485 : const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2486 : unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2487 : MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2488 :
2489 : /// This indicates the "representative" register class to use for each
2490 : /// ValueType the target supports natively. This information is used by the
2491 : /// scheduler to track register pressure. By default, the representative
2492 : /// register class is the largest legal super-reg register class of the
2493 : /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2494 : /// representative class would be GR32.
2495 : const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2496 :
2497 : /// This indicates the "cost" of the "representative" register class for each
2498 : /// ValueType. The cost is used by the scheduler to approximate register
2499 : /// pressure.
2500 : uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2501 :
2502 : /// For any value types we are promoting or expanding, this contains the value
2503 : /// type that we are changing to. For Expanded types, this contains one step
2504 : /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2505 : /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2506 : /// the same type (e.g. i32 -> i32).
2507 : MVT TransformToType[MVT::LAST_VALUETYPE];
2508 :
2509 : /// For each operation and each value type, keep a LegalizeAction that
2510 : /// indicates how instruction selection should deal with the operation. Most
2511 : /// operations are Legal (aka, supported natively by the target), but
2512 : /// operations that are not should be described. Note that operations on
2513 : /// non-legal value types are not described here.
2514 : LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2515 :
2516 : /// For each load extension type and each value type, keep a LegalizeAction
2517 : /// that indicates how instruction selection should deal with a load of a
2518 : /// specific value type and extension type. Uses 4-bits to store the action
2519 : /// for each of the 4 load ext types.
2520 : uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2521 :
2522 : /// For each value type pair keep a LegalizeAction that indicates whether a
2523 : /// truncating store of a specific value type and truncating type is legal.
2524 : LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2525 :
2526 : /// For each indexed mode and each value type, keep a pair of LegalizeAction
2527 : /// that indicates how instruction selection should deal with the load /
2528 : /// store.
2529 : ///
2530 : /// The first dimension is the value_type for the reference. The second
2531 : /// dimension represents the various modes for load store.
2532 : uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2533 :
2534 : /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2535 : /// indicates how instruction selection should deal with the condition code.
2536 : ///
2537 : /// Because each CC action takes up 4 bits, we need to have the array size be
2538 : /// large enough to fit all of the value types. This can be done by rounding
2539 : /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2540 : uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2541 :
2542 : protected:
2543 : ValueTypeActionImpl ValueTypeActions;
2544 :
2545 : private:
2546 : LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2547 :
2548 : /// Targets can specify ISD nodes that they would like PerformDAGCombine
2549 : /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2550 : /// array.
2551 : unsigned char
2552 : TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2553 :
2554 : /// For operations that must be promoted to a specific type, this holds the
2555 : /// destination type. This map should be sparse, so don't hold it as an
2556 : /// array.
2557 : ///
2558 : /// Targets add entries to this map with AddPromotedToType(..), clients access
2559 : /// this with getTypeToPromoteTo(..).
2560 : std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2561 : PromoteToType;
2562 :
2563 : /// Stores the name each libcall.
2564 : const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2565 :
2566 : /// The ISD::CondCode that should be used to test the result of each of the
2567 : /// comparison libcall against zero.
2568 : ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2569 :
2570 : /// Stores the CallingConv that should be used for each libcall.
2571 : CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2572 :
2573 : /// Set default libcall names and calling conventions.
2574 : void InitLibcalls(const Triple &TT);
2575 :
2576 : protected:
2577 : /// Return true if the extension represented by \p I is free.
2578 : /// \pre \p I is a sign, zero, or fp extension and
2579 : /// is[Z|FP]ExtFree of the related types is not true.
2580 37188 : virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2581 :
2582 : /// Depth that GatherAllAliases should should continue looking for chain
2583 : /// dependencies when trying to find a more preferable chain. As an
2584 : /// approximation, this should be more than the number of consecutive stores
2585 : /// expected to be merged.
2586 : unsigned GatherAllAliasesMaxDepth;
2587 :
2588 : /// Specify maximum number of store instructions per memset call.
2589 : ///
2590 : /// When lowering \@llvm.memset this field specifies the maximum number of
2591 : /// store operations that may be substituted for the call to memset. Targets
2592 : /// must set this value based on the cost threshold for that target. Targets
2593 : /// should assume that the memset will be done using as many of the largest
2594 : /// store operations first, followed by smaller ones, if necessary, per
2595 : /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2596 : /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2597 : /// store. This only applies to setting a constant array of a constant size.
2598 : unsigned MaxStoresPerMemset;
2599 :
2600 : /// Maximum number of stores operations that may be substituted for the call
2601 : /// to memset, used for functions with OptSize attribute.
2602 : unsigned MaxStoresPerMemsetOptSize;
2603 :
2604 : /// Specify maximum bytes of store instructions per memcpy call.
2605 : ///
2606 : /// When lowering \@llvm.memcpy this field specifies the maximum number of
2607 : /// store operations that may be substituted for a call to memcpy. Targets
2608 : /// must set this value based on the cost threshold for that target. Targets
2609 : /// should assume that the memcpy will be done using as many of the largest
2610 : /// store operations first, followed by smaller ones, if necessary, per
2611 : /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2612 : /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2613 : /// and one 1-byte store. This only applies to copying a constant array of
2614 : /// constant size.
2615 : unsigned MaxStoresPerMemcpy;
2616 :
2617 :
2618 : /// \brief Specify max number of store instructions to glue in inlined memcpy.
2619 : ///
2620 : /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2621 : /// of store instructions to keep together. This helps in pairing and
2622 : // vectorization later on.
2623 : unsigned MaxGluedStoresPerMemcpy = 0;
2624 :
2625 : /// Maximum number of store operations that may be substituted for a call to
2626 : /// memcpy, used for functions with OptSize attribute.
2627 : unsigned MaxStoresPerMemcpyOptSize;
2628 : unsigned MaxLoadsPerMemcmp;
2629 : unsigned MaxLoadsPerMemcmpOptSize;
2630 :
2631 : /// Specify maximum bytes of store instructions per memmove call.
2632 : ///
2633 : /// When lowering \@llvm.memmove this field specifies the maximum number of
2634 : /// store instructions that may be substituted for a call to memmove. Targets
2635 : /// must set this value based on the cost threshold for that target. Targets
2636 : /// should assume that the memmove will be done using as many of the largest
2637 : /// store operations first, followed by smaller ones, if necessary, per
2638 : /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2639 : /// with 8-bit alignment would result in nine 1-byte stores. This only
2640 : /// applies to copying a constant array of constant size.
2641 : unsigned MaxStoresPerMemmove;
2642 :
2643 : /// Maximum number of store instructions that may be substituted for a call to
2644 : /// memmove, used for functions with OptSize attribute.
2645 : unsigned MaxStoresPerMemmoveOptSize;
2646 :
2647 : /// Tells the code generator that select is more expensive than a branch if
2648 : /// the branch is usually predicted right.
2649 : bool PredictableSelectIsExpensive;
2650 :
2651 : /// \see enableExtLdPromotion.
2652 : bool EnableExtLdPromotion;
2653 :
2654 : /// Return true if the value types that can be represented by the specified
2655 : /// register class are all legal.
2656 : bool isLegalRC(const TargetRegisterInfo &TRI,
2657 : const TargetRegisterClass &RC) const;
2658 :
2659 : /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2660 : /// sequence of memory operands that is recognized by PrologEpilogInserter.
2661 : MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2662 : MachineBasicBlock *MBB) const;
2663 :
2664 : /// Replace/modify the XRay custom event operands with target-dependent
2665 : /// details.
2666 : MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2667 : MachineBasicBlock *MBB) const;
2668 :
2669 : /// Replace/modify the XRay typed event operands with target-dependent
2670 : /// details.
2671 : MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2672 : MachineBasicBlock *MBB) const;
2673 : };
2674 :
2675 : /// This class defines information used to lower LLVM code to legal SelectionDAG
2676 : /// operators that the target instruction selector can accept natively.
2677 : ///
2678 : /// This class also defines callbacks that targets must implement to lower
2679 : /// target-specific constructs to SelectionDAG operators.
2680 2485 : class TargetLowering : public TargetLoweringBase {
2681 : public:
2682 : struct DAGCombinerInfo;
2683 :
2684 : TargetLowering(const TargetLowering &) = delete;
2685 : TargetLowering &operator=(const TargetLowering &) = delete;
2686 :
2687 : /// NOTE: The TargetMachine owns TLOF.
2688 : explicit TargetLowering(const TargetMachine &TM);
2689 :
2690 : bool isPositionIndependent() const;
2691 :
2692 47005446 : virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2693 : FunctionLoweringInfo *FLI,
2694 : LegacyDivergenceAnalysis *DA) const {
2695 47005446 : return false;
2696 : }
2697 :
2698 39897542 : virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2699 39897542 : return false;
2700 : }
2701 :
2702 : /// Returns true by value, base pointer and offset pointer and addressing mode
2703 : /// by reference if the node's address can be legally represented as
2704 : /// pre-indexed load / store address.
2705 0 : virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2706 : SDValue &/*Offset*/,
2707 : ISD::MemIndexedMode &/*AM*/,
2708 : SelectionDAG &/*DAG*/) const {
2709 0 : return false;
2710 : }
2711 :
2712 : /// Returns true by value, base pointer and offset pointer and addressing mode
2713 : /// by reference if this node can be combined with a load / store to form a
2714 : /// post-indexed load / store.
2715 0 : virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2716 : SDValue &/*Base*/,
2717 : SDValue &/*Offset*/,
2718 : ISD::MemIndexedMode &/*AM*/,
2719 : SelectionDAG &/*DAG*/) const {
2720 0 : return false;
2721 : }
2722 :
2723 : /// Return the entry encoding for a jump table in the current function. The
2724 : /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2725 : virtual unsigned getJumpTableEncoding() const;
2726 :
2727 : virtual const MCExpr *
2728 0 : LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2729 : const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2730 : MCContext &/*Ctx*/) const {
2731 0 : llvm_unreachable("Need to implement this hook if target has custom JTIs");
2732 : }
2733 :
2734 : /// Returns relocation base for the given PIC jumptable.
2735 : virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2736 : SelectionDAG &DAG) const;
2737 :
2738 : /// This returns the relocation base for the given PIC jumptable, the same as
2739 : /// getPICJumpTableRelocBase, but as an MCExpr.
2740 : virtual const MCExpr *
2741 : getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2742 : unsigned JTI, MCContext &Ctx) const;
2743 :
2744 : /// Return true if folding a constant offset with the given GlobalAddress is
2745 : /// legal. It is frequently not legal in PIC relocation models.
2746 : virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2747 :
2748 : bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2749 : SDValue &Chain) const;
2750 :
2751 : void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2752 : SDValue &NewRHS, ISD::CondCode &CCCode,
2753 : const SDLoc &DL) const;
2754 :
2755 : /// Returns a pair of (return value, chain).
2756 : /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2757 : std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2758 : EVT RetVT, ArrayRef<SDValue> Ops,
2759 : bool isSigned, const SDLoc &dl,
2760 : bool doesNotReturn = false,
2761 : bool isReturnValueUsed = true) const;
2762 :
2763 : /// Check whether parameters to a call that are passed in callee saved
2764 : /// registers are the same as from the calling function. This needs to be
2765 : /// checked for tail call eligibility.
2766 : bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2767 : const uint32_t *CallerPreservedMask,
2768 : const SmallVectorImpl<CCValAssign> &ArgLocs,
2769 : const SmallVectorImpl<SDValue> &OutVals) const;
2770 :
2771 : //===--------------------------------------------------------------------===//
2772 : // TargetLowering Optimization Methods
2773 : //
2774 :
2775 : /// A convenience struct that encapsulates a DAG, and two SDValues for
2776 : /// returning information from TargetLowering to its clients that want to
2777 : /// combine.
2778 : struct TargetLoweringOpt {
2779 : SelectionDAG &DAG;
2780 : bool LegalTys;
2781 : bool LegalOps;
2782 : SDValue Old;
2783 : SDValue New;
2784 :
2785 : explicit TargetLoweringOpt(SelectionDAG &InDAG,
2786 5401413 : bool LT, bool LO) :
2787 5401413 : DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2788 :
2789 0 : bool LegalTypes() const { return LegalTys; }
2790 0 : bool LegalOperations() const { return LegalOps; }
2791 :
2792 : bool CombineTo(SDValue O, SDValue N) {
2793 161170 : Old = O;
2794 161170 : New = N;
2795 : return true;
2796 : }
2797 : };
2798 :
2799 : /// Check to see if the specified operand of the specified instruction is a
2800 : /// constant integer. If so, check to see if there are any bits set in the
2801 : /// constant that are not demanded. If so, shrink the constant and return
2802 : /// true.
2803 : bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2804 : TargetLoweringOpt &TLO) const;
2805 :
2806 : // Target hook to do target-specific const optimization, which is called by
2807 : // ShrinkDemandedConstant. This function should return true if the target
2808 : // doesn't want ShrinkDemandedConstant to further optimize the constant.
2809 280808 : virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2810 : TargetLoweringOpt &TLO) const {
2811 280808 : return false;
2812 : }
2813 :
2814 : /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2815 : /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2816 : /// generalized for targets with other types of implicit widening casts.
2817 : bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2818 : TargetLoweringOpt &TLO) const;
2819 :
2820 : /// Helper for SimplifyDemandedBits that can simplify an operation with
2821 : /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2822 : /// then updates \p User with the simplified version. No other uses of
2823 : /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2824 : /// function behaves exactly like function SimplifyDemandedBits declared
2825 : /// below except that it also updates the DAG by calling
2826 : /// DCI.CommitTargetLoweringOpt.
2827 : bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2828 : DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2829 :
2830 : /// Look at Op. At this point, we know that only the DemandedMask bits of the
2831 : /// result of Op are ever used downstream. If we can use this information to
2832 : /// simplify Op, create a new simplified DAG node and return true, returning
2833 : /// the original and new nodes in Old and New. Otherwise, analyze the
2834 : /// expression and return a mask of KnownOne and KnownZero bits for the
2835 : /// expression (used to simplify the caller). The KnownZero/One bits may only
2836 : /// be accurate for those bits in the DemandedMask.
2837 : /// \p AssumeSingleUse When this parameter is true, this function will
2838 : /// attempt to simplify \p Op even if there are multiple uses.
2839 : /// Callers are responsible for correctly updating the DAG based on the
2840 : /// results of this function, because simply replacing replacing TLO.Old
2841 : /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2842 : /// has multiple uses.
2843 : bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2844 : KnownBits &Known,
2845 : TargetLoweringOpt &TLO,
2846 : unsigned Depth = 0,
2847 : bool AssumeSingleUse = false) const;
2848 :
2849 : /// Helper wrapper around SimplifyDemandedBits.
2850 : /// Adds Op back to the worklist upon success.
2851 : bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2852 : DAGCombinerInfo &DCI) const;
2853 :
2854 : /// Look at Vector Op. At this point, we know that only the DemandedElts
2855 : /// elements of the result of Op are ever used downstream. If we can use
2856 : /// this information to simplify Op, create a new simplified DAG node and
2857 : /// return true, storing the original and new nodes in TLO.
2858 : /// Otherwise, analyze the expression and return a mask of KnownUndef and
2859 : /// KnownZero elements for the expression (used to simplify the caller).
2860 : /// The KnownUndef/Zero elements may only be accurate for those bits
2861 : /// in the DemandedMask.
2862 : /// \p AssumeSingleUse When this parameter is true, this function will
2863 : /// attempt to simplify \p Op even if there are multiple uses.
2864 : /// Callers are responsible for correctly updating the DAG based on the
2865 : /// results of this function, because simply replacing replacing TLO.Old
2866 : /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2867 : /// has multiple uses.
2868 : bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2869 : APInt &KnownUndef, APInt &KnownZero,
2870 : TargetLoweringOpt &TLO, unsigned Depth = 0,
2871 : bool AssumeSingleUse = false) const;
2872 :
2873 : /// Helper wrapper around SimplifyDemandedVectorElts.
2874 : /// Adds Op back to the worklist upon success.
2875 : bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2876 : APInt &KnownUndef, APInt &KnownZero,
2877 : DAGCombinerInfo &DCI) const;
2878 :
2879 : /// Determine which of the bits specified in Mask are known to be either zero
2880 : /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2881 : /// argument allows us to only collect the known bits that are shared by the
2882 : /// requested vector elements.
2883 : virtual void computeKnownBitsForTargetNode(const SDValue Op,
2884 : KnownBits &Known,
2885 : const APInt &DemandedElts,
2886 : const SelectionDAG &DAG,
2887 : unsigned Depth = 0) const;
2888 :
2889 : /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2890 : /// Default implementation computes low bits based on alignment
2891 : /// information. This should preserve known bits passed into it.
2892 : virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2893 : KnownBits &Known,
2894 : const APInt &DemandedElts,
2895 : const SelectionDAG &DAG,
2896 : unsigned Depth = 0) const;
2897 :
2898 : /// This method can be implemented by targets that want to expose additional
2899 : /// information about sign bits to the DAG Combiner. The DemandedElts
2900 : /// argument allows us to only collect the minimum sign bits that are shared
2901 : /// by the requested vector elements.
2902 : virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2903 : const APInt &DemandedElts,
2904 : const SelectionDAG &DAG,
2905 : unsigned Depth = 0) const;
2906 :
2907 : /// Attempt to simplify any target nodes based on the demanded vector
2908 : /// elements, returning true on success. Otherwise, analyze the expression and
2909 : /// return a mask of KnownUndef and KnownZero elements for the expression
2910 : /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2911 : /// accurate for those bits in the DemandedMask
2912 : virtual bool SimplifyDemandedVectorEltsForTargetNode(
2913 : SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2914 : APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2915 :
2916 : /// If \p SNaN is false, \returns true if \p Op is known to never be any
2917 : /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
2918 : /// NaN.
2919 : virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
2920 : const SelectionDAG &DAG,
2921 : bool SNaN = false,
2922 : unsigned Depth = 0) const;
2923 : struct DAGCombinerInfo {
2924 : void *DC; // The DAG Combiner object.
2925 : CombineLevel Level;
2926 : bool CalledByLegalizer;
2927 :
2928 : public:
2929 : SelectionDAG &DAG;
2930 :
2931 : DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2932 25332370 : : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2933 :
2934 0 : bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2935 1697944 : bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2936 0 : bool isAfterLegalizeDAG() const {
2937 0 : return Level == AfterLegalizeDAG;
2938 : }
2939 0 : CombineLevel getDAGCombineLevel() { return Level; }
2940 0 : bool isCalledByLegalizer() const { return CalledByLegalizer; }
2941 :
2942 : void AddToWorklist(SDNode *N);
2943 : SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2944 : SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2945 : SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2946 :
2947 : void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2948 : };
2949 :
2950 : /// Return if the N is a constant or constant vector equal to the true value
2951 : /// from getBooleanContents().
2952 : bool isConstTrueVal(const SDNode *N) const;
2953 :
2954 : /// Return if the N is a constant or constant vector equal to the false value
2955 : /// from getBooleanContents().
2956 : bool isConstFalseVal(const SDNode *N) const;
2957 :
2958 : /// Return if \p N is a True value when extended to \p VT.
2959 : bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
2960 :
2961 : /// Try to simplify a setcc built with the specified operands and cc. If it is
2962 : /// unable to simplify it, return a null SDValue.
2963 : SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2964 : bool foldBooleans, DAGCombinerInfo &DCI,
2965 : const SDLoc &dl) const;
2966 :
2967 : // For targets which wrap address, unwrap for analysis.
2968 2905300 : virtual SDValue unwrapAddress(SDValue N) const { return N; }
2969 :
2970 : /// Returns true (and the GlobalValue and the offset) if the node is a
2971 : /// GlobalAddress + offset.
2972 : virtual bool
2973 : isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2974 :
2975 : /// This method will be invoked for all target nodes and for any
2976 : /// target-independent nodes that the target has registered with invoke it
2977 : /// for.
2978 : ///
2979 : /// The semantics are as follows:
2980 : /// Return Value:
2981 : /// SDValue.Val == 0 - No change was made
2982 : /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2983 : /// otherwise - N should be replaced by the returned Operand.
2984 : ///
2985 : /// In addition, methods provided by DAGCombinerInfo may be used to perform
2986 : /// more complex transformations.
2987 : ///
2988 : virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2989 :
2990 : /// Return true if it is profitable to move this shift by a constant amount
2991 : /// though its operand, adjusting any immediate operands as necessary to
2992 : /// preserve semantics. This transformation may not be desirable if it
2993 : /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
2994 : /// extraction in AArch64). By default, it returns true.
2995 : ///
2996 : /// @param N the shift node
2997 : /// @param Level the current DAGCombine legalization level.
2998 2210 : virtual bool isDesirableToCommuteWithShift(const SDNode *N,
2999 : CombineLevel Level) const {
3000 2210 : return true;
3001 : }
3002 :
3003 : // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3004 : // to a shuffle and a truncate.
3005 : // Example of such a combine:
3006 : // v4i32 build_vector((extract_elt V, 1),
3007 : // (extract_elt V, 3),
3008 : // (extract_elt V, 5),
3009 : // (extract_elt V, 7))
3010 : // -->
3011 : // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3012 0 : virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3013 : ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3014 0 : return false;
3015 : }
3016 :
3017 : /// Return true if the target has native support for the specified value type
3018 : /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3019 : /// i16 is legal, but undesirable since i16 instruction encodings are longer
3020 : /// and some i16 instructions are slow.
3021 249703 : virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3022 : // By default, assume all legal types are desirable.
3023 249703 : return isTypeLegal(VT);
3024 : }
3025 :
3026 : /// Return true if it is profitable for dag combiner to transform a floating
3027 : /// point op of specified opcode to a equivalent op of an integer
3028 : /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3029 2305 : virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3030 : EVT /*VT*/) const {
3031 2305 : return false;
3032 : }
3033 :
3034 : /// This method query the target whether it is beneficial for dag combiner to
3035 : /// promote the specified node. If true, it should return the desired
3036 : /// promotion type by reference.
3037 4254 : virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3038 4254 : return false;
3039 : }
3040 :
3041 : /// Return true if the target supports swifterror attribute. It optimizes
3042 : /// loads and stores to reading and writing a specific register.
3043 430852 : virtual bool supportSwiftError() const {
3044 430852 : return false;
3045 : }
3046 :
3047 : /// Return true if the target supports that a subset of CSRs for the given
3048 : /// machine function is handled explicitly via copies.
3049 30543 : virtual bool supportSplitCSR(MachineFunction *MF) const {
3050 30543 : return false;
3051 : }
3052 :
3053 : /// Perform necessary initialization to handle a subset of CSRs explicitly
3054 : /// via copies. This function is called at the beginning of instruction
3055 : /// selection.
3056 0 : virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3057 0 : llvm_unreachable("Not Implemented");
3058 : }
3059 :
3060 : /// Insert explicit copies in entry and exit blocks. We copy a subset of
3061 : /// CSRs to virtual registers in the entry block, and copy them back to
3062 : /// physical registers in the exit blocks. This function is called at the end
3063 : /// of instruction selection.
3064 0 : virtual void insertCopiesSplitCSR(
3065 : MachineBasicBlock *Entry,
3066 : const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3067 0 : llvm_unreachable("Not Implemented");
3068 : }
3069 :
3070 : //===--------------------------------------------------------------------===//
3071 : // Lowering methods - These methods must be implemented by targets so that
3072 : // the SelectionDAGBuilder code knows how to lower these.
3073 : //
3074 :
3075 : /// This hook must be implemented to lower the incoming (formal) arguments,
3076 : /// described by the Ins array, into the specified DAG. The implementation
3077 : /// should fill in the InVals array with legal-type argument values, and
3078 : /// return the resulting token chain value.
3079 0 : virtual SDValue LowerFormalArguments(
3080 : SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3081 : const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3082 : SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3083 0 : llvm_unreachable("Not Implemented");
3084 : }
3085 :
3086 : /// This structure contains all information that is necessary for lowering
3087 : /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3088 : /// needs to lower a call, and targets will see this struct in their LowerCall
3089 : /// implementation.
3090 : struct CallLoweringInfo {
3091 : SDValue Chain;
3092 : Type *RetTy = nullptr;
3093 : bool RetSExt : 1;
3094 : bool RetZExt : 1;
3095 : bool IsVarArg : 1;
3096 : bool IsInReg : 1;
3097 : bool DoesNotReturn : 1;
3098 : bool IsReturnValueUsed : 1;
3099 : bool IsConvergent : 1;
3100 : bool IsPatchPoint : 1;
3101 :
3102 : // IsTailCall should be modified by implementations of
3103 : // TargetLowering::LowerCall that perform tail call conversions.
3104 : bool IsTailCall = false;
3105 :
3106 : // Is Call lowering done post SelectionDAG type legalization.
3107 : bool IsPostTypeLegalization = false;
3108 :
3109 : unsigned NumFixedArgs = -1;
3110 : CallingConv::ID CallConv = CallingConv::C;
3111 : SDValue Callee;
3112 : ArgListTy Args;
3113 : SelectionDAG &DAG;
3114 : SDLoc DL;
3115 : ImmutableCallSite CS;
3116 : SmallVector<ISD::OutputArg, 32> Outs;
3117 : SmallVector<SDValue, 32> OutVals;
3118 : SmallVector<ISD::InputArg, 32> Ins;
3119 : SmallVector<SDValue, 4> InVals;
3120 :
3121 1005206 : CallLoweringInfo(SelectionDAG &DAG)
3122 1005206 : : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3123 : DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3124 3015618 : IsPatchPoint(false), DAG(DAG) {}
3125 :
3126 : CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3127 : DL = dl;
3128 : return *this;
3129 : }
3130 :
3131 : CallLoweringInfo &setChain(SDValue InChain) {
3132 1502191 : Chain = InChain;
3133 : return *this;
3134 : }
3135 :
3136 : // setCallee with target/module-specific attributes
3137 14364 : CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3138 : SDValue Target, ArgListTy &&ArgsList) {
3139 14364 : RetTy = ResultType;
3140 14364 : Callee = Target;
3141 14364 : CallConv = CC;
3142 14364 : NumFixedArgs = ArgsList.size();
3143 14364 : Args = std::move(ArgsList);
3144 :
3145 28728 : DAG.getTargetLoweringInfo().markLibCallAttributes(
3146 14364 : &(DAG.getMachineFunction()), CC, Args);
3147 14364 : return *this;
3148 : }
3149 :
3150 : CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3151 : SDValue Target, ArgListTy &&ArgsList) {
3152 577 : RetTy = ResultType;
3153 577 : Callee = Target;
3154 577 : CallConv = CC;
3155 938 : NumFixedArgs = ArgsList.size();
3156 216 : Args = std::move(ArgsList);
3157 : return *this;
3158 : }
3159 :
3160 990242 : CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3161 : SDValue Target, ArgListTy &&ArgsList,
3162 : ImmutableCallSite Call) {
3163 990242 : RetTy = ResultType;
3164 :
3165 990242 : IsInReg = Call.hasRetAttr(Attribute::InReg);
3166 990242 : DoesNotReturn =
3167 990242 : Call.doesNotReturn() ||
3168 471399 : (!Call.isInvoke() &&
3169 : isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3170 990242 : IsVarArg = FTy->isVarArg();
3171 990242 : IsReturnValueUsed = !Call.getInstruction()->use_empty();
3172 990242 : RetSExt = Call.hasRetAttr(Attribute::SExt);
3173 990242 : RetZExt = Call.hasRetAttr(Attribute::ZExt);
3174 :
3175 990242 : Callee = Target;
3176 :
3177 990242 : CallConv = Call.getCallingConv();
3178 990242 : NumFixedArgs = FTy->getNumParams();
3179 990242 : Args = std::move(ArgsList);
3180 :
3181 990242 : CS = Call;
3182 :
3183 990242 : return *this;
3184 : }
3185 :
3186 : CallLoweringInfo &setInRegister(bool Value = true) {
3187 219 : IsInReg = Value;
3188 : return *this;
3189 : }
3190 :
3191 : CallLoweringInfo &setNoReturn(bool Value = true) {
3192 3140 : DoesNotReturn = Value;
3193 : return *this;
3194 : }
3195 :
3196 : CallLoweringInfo &setVarArg(bool Value = true) {
3197 : IsVarArg = Value;
3198 : return *this;
3199 : }
3200 :
3201 : CallLoweringInfo &setTailCall(bool Value = true) {
3202 1000292 : IsTailCall = Value;
3203 : return *this;
3204 : }
3205 :
3206 : CallLoweringInfo &setDiscardResult(bool Value = true) {
3207 8474 : IsReturnValueUsed = !Value;
3208 : return *this;
3209 : }
3210 :
3211 : CallLoweringInfo &setConvergent(bool Value = true) {
3212 990242 : IsConvergent = Value;
3213 : return *this;
3214 : }
3215 :
3216 : CallLoweringInfo &setSExtResult(bool Value = true) {
3217 9012 : RetSExt = Value;
3218 : return *this;
3219 : }
3220 :
3221 : CallLoweringInfo &setZExtResult(bool Value = true) {
3222 3899 : RetZExt = Value;
3223 : return *this;
3224 : }
3225 :
3226 : CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3227 216 : IsPatchPoint = Value;
3228 : return *this;
3229 : }
3230 :
3231 : CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3232 5103 : IsPostTypeLegalization = Value;
3233 : return *this;
3234 : }
3235 :
3236 : ArgListTy &getArgs() {
3237 4178 : return Args;
3238 : }
3239 : };
3240 :
3241 : /// This function lowers an abstract call to a function into an actual call.
3242 : /// This returns a pair of operands. The first element is the return value
3243 : /// for the function (if RetTy is not VoidTy). The second element is the
3244 : /// outgoing token chain. It calls LowerCall to do the actual lowering.
3245 : std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3246 :
3247 : /// This hook must be implemented to lower calls into the specified
3248 : /// DAG. The outgoing arguments to the call are described by the Outs array,
3249 : /// and the values to be returned by the call are described by the Ins
3250 : /// array. The implementation should fill in the InVals array with legal-type
3251 : /// return values from the call, and return the resulting token chain value.
3252 : virtual SDValue
3253 0 : LowerCall(CallLoweringInfo &/*CLI*/,
3254 : SmallVectorImpl<SDValue> &/*InVals*/) const {
3255 0 : llvm_unreachable("Not Implemented");
3256 : }
3257 :
3258 : /// Target-specific cleanup for formal ByVal parameters.
3259 4182 : virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3260 :
3261 : /// This hook should be implemented to check whether the return values
3262 : /// described by the Outs array can fit into the return registers. If false
3263 : /// is returned, an sret-demotion is performed.
3264 5575 : virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3265 : MachineFunction &/*MF*/, bool /*isVarArg*/,
3266 : const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3267 : LLVMContext &/*Context*/) const
3268 : {
3269 : // Return true by default to get preexisting behavior.
3270 5575 : return true;
3271 : }
3272 :
3273 : /// This hook must be implemented to lower outgoing return values, described
3274 : /// by the Outs array, into the specified DAG. The implementation should
3275 : /// return the resulting token chain value.
3276 0 : virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3277 : bool /*isVarArg*/,
3278 : const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3279 : const SmallVectorImpl<SDValue> & /*OutVals*/,
3280 : const SDLoc & /*dl*/,
3281 : SelectionDAG & /*DAG*/) const {
3282 0 : llvm_unreachable("Not Implemented");
3283 : }
3284 :
3285 : /// Return true if result of the specified node is used by a return node
3286 : /// only. It also compute and return the input chain for the tail call.
3287 : ///
3288 : /// This is used to determine whether it is possible to codegen a libcall as
3289 : /// tail call at legalization time.
3290 621 : virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3291 621 : return false;
3292 : }
3293 :
3294 : /// Return true if the target may be able emit the call instruction as a tail
3295 : /// call. This is used by optimization passes to determine if it's profitable
3296 : /// to duplicate return instructions to enable tailcall optimization.
3297 197 : virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3298 197 : return false;
3299 : }
3300 :
3301 : /// Return the builtin name for the __builtin___clear_cache intrinsic
3302 : /// Default is to invoke the clear cache library call
3303 2 : virtual const char * getClearCacheBuiltinName() const {
3304 2 : return "__clear_cache";
3305 : }
3306 :
3307 : /// Return the register ID of the name passed in. Used by named register
3308 : /// global variables extension. There is no target-independent behaviour
3309 : /// so the default action is to bail.
3310 0 : virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3311 : SelectionDAG &DAG) const {
3312 0 : report_fatal_error("Named registers not implemented for this target");
3313 : }
3314 :
3315 : /// Return the type that should be used to zero or sign extend a
3316 : /// zeroext/signext integer return value. FIXME: Some C calling conventions
3317 : /// require the return type to be promoted, but this is not true all the time,
3318 : /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3319 : /// conventions. The frontend should handle this and include all of the
3320 : /// necessary information.
3321 1874 : virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3322 : ISD::NodeType /*ExtendKind*/) const {
3323 3748 : EVT MinVT = getRegisterType(Context, MVT::i32);
3324 1874 : return VT.bitsLT(MinVT) ? MinVT : VT;
3325 : }
3326 :
3327 : /// For some targets, an LLVM struct type must be broken down into multiple
3328 : /// simple types, but the calling convention specifies that the entire struct
3329 : /// must be passed in a block of consecutive registers.
3330 : virtual bool
3331 4452635 : functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3332 : bool isVarArg) const {
3333 4452635 : return false;
3334 : }
3335 :
3336 : /// Returns a 0 terminated array of registers that can be safely used as
3337 : /// scratch registers.
3338 0 : virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3339 0 : return nullptr;
3340 : }
3341 :
3342 : /// This callback is used to prepare for a volatile or atomic load.
3343 : /// It takes a chain node as input and returns the chain for the load itself.
3344 : ///
3345 : /// Having a callback like this is necessary for targets like SystemZ,
3346 : /// which allows a CPU to reuse the result of a previous load indefinitely,
3347 : /// even if a cache-coherent store is performed by another CPU. The default
3348 : /// implementation does nothing.
3349 17843 : virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3350 : SelectionDAG &DAG) const {
3351 17843 : return Chain;
3352 : }
3353 :
3354 : /// This callback is used to inspect load/store instructions and add
3355 : /// target-specific MachineMemOperand flags to them. The default
3356 : /// implementation does nothing.
3357 4347412 : virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3358 4347412 : return MachineMemOperand::MONone;
3359 : }
3360 :
3361 : /// This callback is invoked by the type legalizer to legalize nodes with an
3362 : /// illegal operand type but legal result types. It replaces the
3363 : /// LowerOperation callback in the type Legalizer. The reason we can not do
3364 : /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3365 : /// use this callback.
3366 : ///
3367 : /// TODO: Consider merging with ReplaceNodeResults.
3368 : ///
3369 : /// The target places new result values for the node in Results (their number
3370 : /// and types must exactly match those of the original return values of
3371 : /// the node), or leaves Results empty, which indicates that the node is not
3372 : /// to be custom lowered after all.
3373 : /// The default implementation calls LowerOperation.
3374 : virtual void LowerOperationWrapper(SDNode *N,
3375 : SmallVectorImpl<SDValue> &Results,
3376 : SelectionDAG &DAG) const;
3377 :
3378 : /// This callback is invoked for operations that are unsupported by the
3379 : /// target, which are registered to use 'custom' lowering, and whose defined
3380 : /// values are all legal. If the target has no operations that require custom
3381 : /// lowering, it need not implement this. The default implementation of this
3382 : /// aborts.
3383 : virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3384 :
3385 : /// This callback is invoked when a node result type is illegal for the
3386 : /// target, and the operation was registered to use 'custom' lowering for that
3387 : /// result type. The target places new result values for the node in Results
3388 : /// (their number and types must exactly match those of the original return
3389 : /// values of the node), or leaves Results empty, which indicates that the
3390 : /// node is not to be custom lowered after all.
3391 : ///
3392 : /// If the target has no operations that require custom lowering, it need not
3393 : /// implement this. The default implementation aborts.
3394 0 : virtual void ReplaceNodeResults(SDNode * /*N*/,
3395 : SmallVectorImpl<SDValue> &/*Results*/,
3396 : SelectionDAG &/*DAG*/) const {
3397 0 : llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3398 : }
3399 :
3400 : /// This method returns the name of a target specific DAG node.
3401 : virtual const char *getTargetNodeName(unsigned Opcode) const;
3402 :
3403 : /// This method returns a target specific FastISel object, or null if the
3404 : /// target does not support "fast" ISel.
3405 2648 : virtual FastISel *createFastISel(FunctionLoweringInfo &,
3406 : const TargetLibraryInfo *) const {
3407 2648 : return nullptr;
3408 : }
3409 :
3410 : bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3411 : SelectionDAG &DAG) const;
3412 :
3413 : //===--------------------------------------------------------------------===//
3414 : // Inline Asm Support hooks
3415 : //
3416 :
3417 : /// This hook allows the target to expand an inline asm call to be explicit
3418 : /// llvm code if it wants to. This is useful for turning simple inline asms
3419 : /// into LLVM intrinsics, which gives the compiler more information about the
3420 : /// behavior of the code.
3421 6921 : virtual bool ExpandInlineAsm(CallInst *) const {
3422 6921 : return false;
3423 : }
3424 :
3425 : enum ConstraintType {
3426 : C_Register, // Constraint represents specific register(s).
3427 : C_RegisterClass, // Constraint represents any of register(s) in class.
3428 : C_Memory, // Memory constraint.
3429 : C_Other, // Something else.
3430 : C_Unknown // Unsupported constraint.
3431 : };
3432 :
3433 : enum ConstraintWeight {
3434 : // Generic weights.
3435 : CW_Invalid = -1, // No match.
3436 : CW_Okay = 0, // Acceptable.
3437 : CW_Good = 1, // Good weight.
3438 : CW_Better = 2, // Better weight.
3439 : CW_Best = 3, // Best weight.
3440 :
3441 : // Well-known weights.
3442 : CW_SpecificReg = CW_Okay, // Specific register operands.
3443 : CW_Register = CW_Good, // Register operands.
3444 : CW_Memory = CW_Better, // Memory operands.
3445 : CW_Constant = CW_Best, // Constant operand.
3446 : CW_Default = CW_Okay // Default or don't know type.
3447 : };
3448 :
3449 : /// This contains information for each constraint that we are lowering.
3450 : struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3451 : /// This contains the actual string for the code, like "m". TargetLowering
3452 : /// picks the 'best' code from ConstraintInfo::Codes that most closely
3453 : /// matches the operand.
3454 : std::string ConstraintCode;
3455 :
3456 : /// Information about the constraint code, e.g. Register, RegisterClass,
3457 : /// Memory, Other, Unknown.
3458 : TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3459 :
3460 : /// If this is the result output operand or a clobber, this is null,
3461 : /// otherwise it is the incoming operand to the CallInst. This gets
3462 : /// modified as the asm is processed.
3463 : Value *CallOperandVal = nullptr;
3464 :
3465 : /// The ValueType for the operand value.
3466 : MVT ConstraintVT = MVT::Other;
3467 :
3468 : /// Copy constructor for copying from a ConstraintInfo.
3469 : AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3470 0 : : InlineAsm::ConstraintInfo(std::move(Info)) {}
3471 :
3472 : /// Return true of this is an input operand that is a matching constraint
3473 : /// like "4".
3474 : bool isMatchingInputConstraint() const;
3475 :
3476 : /// If this is an input matching constraint, this method returns the output
3477 : /// operand it matches.
3478 : unsigned getMatchedOperand() const;
3479 : };
3480 :
3481 : using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3482 :
3483 : /// Split up the constraint string from the inline assembly value into the
3484 : /// specific constraints and their prefixes, and also tie in the associated
3485 : /// operand values. If this returns an empty vector, and if the constraint
3486 : /// string itself isn't empty, there was an error parsing.
3487 : virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3488 : const TargetRegisterInfo *TRI,
3489 : ImmutableCallSite CS) const;
3490 :
3491 : /// Examine constraint type and operand type and determine a weight value.
3492 : /// The operand object must already have been set up with the operand type.
3493 : virtual ConstraintWeight getMultipleConstraintMatchWeight(
3494 : AsmOperandInfo &info, int maIndex) const;
3495 :
3496 : /// Examine constraint string and operand type and determine a weight value.
3497 : /// The operand object must already have been set up with the operand type.
3498 : virtual ConstraintWeight getSingleConstraintMatchWeight(
3499 : AsmOperandInfo &info, const char *constraint) const;
3500 :
3501 : /// Determines the constraint code and constraint type to use for the specific
3502 : /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3503 : /// If the actual operand being passed in is available, it can be passed in as
3504 : /// Op, otherwise an empty SDValue can be passed.
3505 : virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3506 : SDValue Op,
3507 : SelectionDAG *DAG = nullptr) const;
3508 :
3509 : /// Given a constraint, return the type of constraint it is for this target.
3510 : virtual ConstraintType getConstraintType(StringRef Constraint) const;
3511 :
3512 : /// Given a physical register constraint (e.g. {edx}), return the register
3513 : /// number and the register class for the register.
3514 : ///
3515 : /// Given a register class constraint, like 'r', if this corresponds directly
3516 : /// to an LLVM register class, return a register of 0 and the register class
3517 : /// pointer.
3518 : ///
3519 : /// This should only be used for C_Register constraints. On error, this
3520 : /// returns a register number of 0 and a null register class pointer.
3521 : virtual std::pair<unsigned, const TargetRegisterClass *>
3522 : getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3523 : StringRef Constraint, MVT VT) const;
3524 :
3525 16 : virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3526 : if (ConstraintCode == "i")
3527 : return InlineAsm::Constraint_i;
3528 : else if (ConstraintCode == "m")
3529 16 : return InlineAsm::Constraint_m;
3530 : return InlineAsm::Constraint_Unknown;
3531 : }
3532 :
3533 : /// Try to replace an X constraint, which matches anything, with another that
3534 : /// has more specific requirements based on the type of the corresponding
3535 : /// operand. This returns null if there is no replacement to make.
3536 : virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3537 :
3538 : /// Lower the specified operand into the Ops vector. If it is invalid, don't
3539 : /// add anything to Ops.
3540 : virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3541 : std::vector<SDValue> &Ops,
3542 : SelectionDAG &DAG) const;
3543 :
3544 : //===--------------------------------------------------------------------===//
3545 : // Div utility functions
3546 : //
3547 : SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3548 : SmallVectorImpl<SDNode *> &Created) const;
3549 : SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3550 : SmallVectorImpl<SDNode *> &Created) const;
3551 :
3552 : /// Targets may override this function to provide custom SDIV lowering for
3553 : /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3554 : /// assumes SDIV is expensive and replaces it with a series of other integer
3555 : /// operations.
3556 : virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3557 : SelectionDAG &DAG,
3558 : SmallVectorImpl<SDNode *> &Created) const;
3559 :
3560 : /// Indicate whether this target prefers to combine FDIVs with the same
3561 : /// divisor. If the transform should never be done, return zero. If the
3562 : /// transform should be done, return the minimum number of divisor uses
3563 : /// that must exist.
3564 52 : virtual unsigned combineRepeatedFPDivisors() const {
3565 52 : return 0;
3566 : }
3567 :
3568 : /// Hooks for building estimates in place of slower divisions and square
3569 : /// roots.
3570 :
3571 : /// Return either a square root or its reciprocal estimate value for the input
3572 : /// operand.
3573 : /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3574 : /// 'Enabled' as set by a potential default override attribute.
3575 : /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3576 : /// refinement iterations required to generate a sufficient (though not
3577 : /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3578 : /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3579 : /// algorithm implementation that uses either one or two constants.
3580 : /// The boolean Reciprocal is used to select whether the estimate is for the
3581 : /// square root of the input operand or the reciprocal of its square root.
3582 : /// A target may choose to implement its own refinement within this function.
3583 : /// If that's true, then return '0' as the number of RefinementSteps to avoid
3584 : /// any further refinement of the estimate.
3585 : /// An empty SDValue return means no estimate sequence can be created.
3586 16 : virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3587 : int Enabled, int &RefinementSteps,
3588 : bool &UseOneConstNR, bool Reciprocal) const {
3589 16 : return SDValue();
3590 : }
3591 :
3592 : /// Return a reciprocal estimate value for the input operand.
3593 : /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3594 : /// 'Enabled' as set by a potential default override attribute.
3595 : /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3596 : /// refinement iterations required to generate a sufficient (though not
3597 : /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3598 : /// A target may choose to implement its own refinement within this function.
3599 : /// If that's true, then return '0' as the number of RefinementSteps to avoid
3600 : /// any further refinement of the estimate.
3601 : /// An empty SDValue return means no estimate sequence can be created.
3602 42 : virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3603 : int Enabled, int &RefinementSteps) const {
3604 42 : return SDValue();
3605 : }
3606 :
3607 : //===--------------------------------------------------------------------===//
3608 : // Legalization utility functions
3609 : //
3610 :
3611 : /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3612 : /// respectively, each computing an n/2-bit part of the result.
3613 : /// \param Result A vector that will be filled with the parts of the result
3614 : /// in little-endian order.
3615 : /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3616 : /// if you want to control how low bits are extracted from the LHS.
3617 : /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3618 : /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3619 : /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3620 : /// \returns true if the node has been expanded, false if it has not
3621 : bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3622 : SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3623 : SelectionDAG &DAG, MulExpansionKind Kind,
3624 : SDValue LL = SDValue(), SDValue LH = SDValue(),
3625 : SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3626 :
3627 : /// Expand a MUL into two nodes. One that computes the high bits of
3628 : /// the result and one that computes the low bits.
3629 : /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3630 : /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3631 : /// if you want to control how low bits are extracted from the LHS.
3632 : /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3633 : /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3634 : /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3635 : /// \returns true if the node has been expanded. false if it has not
3636 : bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3637 : SelectionDAG &DAG, MulExpansionKind Kind,
3638 : SDValue LL = SDValue(), SDValue LH = SDValue(),
3639 : SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3640 :
3641 : /// Expand float(f32) to SINT(i64) conversion
3642 : /// \param N Node to expand
3643 : /// \param Result output after conversion
3644 : /// \returns True, if the expansion was successful, false otherwise
3645 : bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3646 :
3647 : /// Turn load of vector type into a load of the individual elements.
3648 : /// \param LD load to expand
3649 : /// \returns MERGE_VALUEs of the scalar loads with their chains.
3650 : SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3651 :
3652 : // Turn a store of a vector type into stores of the individual elements.
3653 : /// \param ST Store with a vector value type
3654 : /// \returns MERGE_VALUs of the individual store chains.
3655 : SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3656 :
3657 : /// Expands an unaligned load to 2 half-size loads for an integer, and
3658 : /// possibly more for vectors.
3659 : std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3660 : SelectionDAG &DAG) const;
3661 :
3662 : /// Expands an unaligned store to 2 half-size stores for integer values, and
3663 : /// possibly more for vectors.
3664 : SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3665 :
3666 : /// Increments memory address \p Addr according to the type of the value
3667 : /// \p DataVT that should be stored. If the data is stored in compressed
3668 : /// form, the memory address should be incremented according to the number of
3669 : /// the stored elements. This number is equal to the number of '1's bits
3670 : /// in the \p Mask.
3671 : /// \p DataVT is a vector type. \p Mask is a vector value.
3672 : /// \p DataVT and \p Mask have the same number of vector elements.
3673 : SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3674 : EVT DataVT, SelectionDAG &DAG,
3675 : bool IsCompressedMemory) const;
3676 :
3677 : /// Get a pointer to vector element \p Idx located in memory for a vector of
3678 : /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3679 : /// bounds the returned pointer is unspecified, but will be within the vector
3680 : /// bounds.
3681 : SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3682 : SDValue Index) const;
3683 :
3684 : /// Method for building the DAG expansion of ISD::SADDSAT. This method accepts
3685 : /// integers or vectors of integers as its arguments.
3686 : SDValue getExpandedSignedSaturationAddition(SDNode *Node,
3687 : SelectionDAG &DAG) const;
3688 :
3689 : //===--------------------------------------------------------------------===//
3690 : // Instruction Emitting Hooks
3691 : //
3692 :
3693 : /// This method should be implemented by targets that mark instructions with
3694 : /// the 'usesCustomInserter' flag. These instructions are special in various
3695 : /// ways, which require special support to insert. The specified MachineInstr
3696 : /// is created but not inserted into any basic blocks, and this method is
3697 : /// called to expand it into a sequence of instructions, potentially also
3698 : /// creating new basic blocks and control flow.
3699 : /// As long as the returned basic block is different (i.e., we created a new
3700 : /// one), the custom inserter is free to modify the rest of \p MBB.
3701 : virtual MachineBasicBlock *
3702 : EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3703 :
3704 : /// This method should be implemented by targets that mark instructions with
3705 : /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3706 : /// instruction selection by target hooks. e.g. To fill in optional defs for
3707 : /// ARM 's' setting instructions.
3708 : virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3709 : SDNode *Node) const;
3710 :
3711 : /// If this function returns true, SelectionDAGBuilder emits a
3712 : /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3713 12 : virtual bool useLoadStackGuardNode() const {
3714 12 : return false;
3715 : }
3716 :
3717 0 : virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3718 : const SDLoc &DL) const {
3719 0 : llvm_unreachable("not implemented for this target");
3720 : }
3721 :
3722 : /// Lower TLS global address SDNode for target independent emulated TLS model.
3723 : virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3724 : SelectionDAG &DAG) const;
3725 :
3726 : /// Expands target specific indirect branch for the case of JumpTable
3727 : /// expanasion.
3728 3154 : virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3729 : SelectionDAG &DAG) const {
3730 3154 : return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3731 : }
3732 :
3733 : // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3734 : // If we're comparing for equality to zero and isCtlzFast is true, expose the
3735 : // fact that this can be implemented as a ctlz/srl pair, so that the dag
3736 : // combiner can fold the new nodes.
3737 : SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3738 :
3739 : private:
3740 : SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3741 : ISD::CondCode Cond, DAGCombinerInfo &DCI,
3742 : const SDLoc &DL) const;
3743 :
3744 : SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3745 : SDValue N1, ISD::CondCode Cond,
3746 : DAGCombinerInfo &DCI,
3747 : const SDLoc &DL) const;
3748 : };
3749 :
3750 : /// Given an LLVM IR type and return type attributes, compute the return value
3751 : /// EVTs and flags, and optionally also the offsets, if the return value is
3752 : /// being lowered to memory.
3753 : void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
3754 : SmallVectorImpl<ISD::OutputArg> &Outs,
3755 : const TargetLowering &TLI, const DataLayout &DL);
3756 :
3757 : } // end namespace llvm
3758 :
3759 : #endif // LLVM_CODEGEN_TARGETLOWERING_H
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