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1 : //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file defines the MCInstrAnalysis class which the MCTargetDescs can
11 : // derive from to give additional information to MC.
12 : //
13 : //===----------------------------------------------------------------------===//
14 :
15 : #ifndef LLVM_MC_MCINSTRANALYSIS_H
16 : #define LLVM_MC_MCINSTRANALYSIS_H
17 :
18 : #include "llvm/MC/MCInst.h"
19 : #include "llvm/MC/MCInstrDesc.h"
20 : #include "llvm/MC/MCInstrInfo.h"
21 : #include <cstdint>
22 :
23 : namespace llvm {
24 :
25 : class MCRegisterInfo;
26 : class Triple;
27 :
28 : class MCInstrAnalysis {
29 : protected:
30 : friend class Target;
31 :
32 : const MCInstrInfo *Info;
33 :
34 : public:
35 1978 : MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
36 0 : virtual ~MCInstrAnalysis() = default;
37 :
38 0 : virtual bool isBranch(const MCInst &Inst) const {
39 0 : return Info->get(Inst.getOpcode()).isBranch();
40 : }
41 :
42 307078 : virtual bool isConditionalBranch(const MCInst &Inst) const {
43 629175 : return Info->get(Inst.getOpcode()).isConditionalBranch();
44 : }
45 :
46 312122 : virtual bool isUnconditionalBranch(const MCInst &Inst) const {
47 651358 : return Info->get(Inst.getOpcode()).isUnconditionalBranch();
48 : }
49 :
50 0 : virtual bool isIndirectBranch(const MCInst &Inst) const {
51 0 : return Info->get(Inst.getOpcode()).isIndirectBranch();
52 : }
53 :
54 3146775 : virtual bool isCall(const MCInst &Inst) const {
55 9440325 : return Info->get(Inst.getOpcode()).isCall();
56 : }
57 :
58 0 : virtual bool isReturn(const MCInst &Inst) const {
59 0 : return Info->get(Inst.getOpcode()).isReturn();
60 : }
61 :
62 0 : virtual bool isTerminator(const MCInst &Inst) const {
63 0 : return Info->get(Inst.getOpcode()).isTerminator();
64 : }
65 :
66 : /// Returns true if at least one of the register writes performed by
67 : /// \param Inst implicitly clears the upper portion of all super-registers.
68 : ///
69 : /// Example: on X86-64, a write to EAX implicitly clears the upper half of
70 : /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
71 : /// instruction implicitly clears the upper portion of the correspondent
72 : /// YMM register.
73 : ///
74 : /// This method also updates an APInt which is used as mask of register
75 : /// writes. There is one bit for every explicit/implicit write performed by
76 : /// the instruction. If a write implicitly clears its super-registers, then
77 : /// the corresponding bit is set (vic. the corresponding bit is cleared).
78 : ///
79 : /// The first bits in the APint are related to explicit writes. The remaining
80 : /// bits are related to implicit writes. The sequence of writes follows the
81 : /// machine operand sequence. For implicit writes, the sequence is defined by
82 : /// the MCInstrDesc.
83 : ///
84 : /// The assumption is that the bit-width of the APInt is correctly set by
85 : /// the caller. The default implementation conservatively assumes that none of
86 : /// the writes clears the upper portion of a super-register.
87 : virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
88 : const MCInst &Inst,
89 : APInt &Writes) const;
90 :
91 : /// Returns true if MI is a dependency breaking zero-idiom for the given
92 : /// subtarget.
93 : ///
94 : /// Mask is used to identify input operands that have their dependency
95 : /// broken. Each bit of the mask is associated with a specific input operand.
96 : /// Bits associated with explicit input operands are laid out first in the
97 : /// mask; implicit operands come after explicit operands.
98 : ///
99 : /// Dependencies are broken only for operands that have their corresponding bit
100 : /// set. Operands that have their bit cleared, or that don't have a
101 : /// corresponding bit in the mask don't have their dependency broken. Note
102 : /// that Mask may not be big enough to describe all operands. The assumption
103 : /// for operands that don't have a correspondent bit in the mask is that those
104 : /// are still data dependent.
105 : ///
106 : /// The only exception to the rule is for when Mask has all zeroes.
107 : /// A zero mask means: dependencies are broken for all explicit register
108 : /// operands.
109 2808 : virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask,
110 : unsigned CPUID) const {
111 2808 : return false;
112 : }
113 :
114 : /// Returns true if MI is a dependency breaking instruction for the
115 : /// subtarget associated with CPUID .
116 : ///
117 : /// The value computed by a dependency breaking instruction is not dependent
118 : /// on the inputs. An example of dependency breaking instruction on X86 is
119 : /// `XOR %eax, %eax`.
120 : ///
121 : /// If MI is a dependency breaking instruction for subtarget CPUID, then Mask
122 : /// can be inspected to identify independent operands.
123 : ///
124 : /// Essentially, each bit of the mask corresponds to an input operand.
125 : /// Explicit operands are laid out first in the mask; implicit operands follow
126 : /// explicit operands. Bits are set for operands that are independent.
127 : ///
128 : /// Note that the number of bits in Mask may not be equivalent to the sum of
129 : /// explicit and implicit operands in MI. Operands that don't have a
130 : /// corresponding bit in Mask are assumed "not independente".
131 : ///
132 : /// The only exception is for when Mask is all zeroes. That means: explicit
133 : /// input operands of MI are independent.
134 1404 : virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
135 : unsigned CPUID) const {
136 1404 : return isZeroIdiom(MI, Mask, CPUID);
137 : }
138 :
139 : /// Returns true if MI is a candidate for move elimination.
140 : ///
141 : /// Different subtargets may apply different constraints to optimizable
142 : /// register moves. For example, on most X86 subtargets, a candidate for move
143 : /// elimination cannot specify the same register for both source and
144 : /// destination.
145 1404 : virtual bool isOptimizableRegisterMove(const MCInst &MI,
146 : unsigned CPUID) const {
147 1404 : return false;
148 : }
149 :
150 : /// Given a branch instruction try to get the address the branch
151 : /// targets. Return true on success, and the address in Target.
152 : virtual bool
153 : evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
154 : uint64_t &Target) const;
155 :
156 : /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
157 : virtual std::vector<std::pair<uint64_t, uint64_t>>
158 0 : findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
159 : uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
160 0 : return {};
161 : }
162 : };
163 :
164 : } // end namespace llvm
165 :
166 : #endif // LLVM_MC_MCINSTRANALYSIS_H
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