Line data Source code
1 : //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains support for writing dwarf debug info into asm files.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "DwarfExpression.h"
15 : #include "llvm/ADT/APInt.h"
16 : #include "llvm/ADT/SmallBitVector.h"
17 : #include "llvm/BinaryFormat/Dwarf.h"
18 : #include "llvm/CodeGen/TargetRegisterInfo.h"
19 : #include "llvm/IR/DebugInfoMetadata.h"
20 : #include "llvm/Support/ErrorHandling.h"
21 : #include <algorithm>
22 : #include <cassert>
23 : #include <cstdint>
24 :
25 : using namespace llvm;
26 :
27 953 : void DwarfExpression::emitConstu(uint64_t Value) {
28 953 : if (Value < 32)
29 799 : emitOp(dwarf::DW_OP_lit0 + Value);
30 154 : else if (Value == std::numeric_limits<uint64_t>::max()) {
31 : // Only do this for 64-bit values as the DWARF expression stack uses
32 : // target-address-size values.
33 28 : emitOp(dwarf::DW_OP_lit0);
34 28 : emitOp(dwarf::DW_OP_not);
35 : } else {
36 126 : emitOp(dwarf::DW_OP_constu);
37 126 : emitUnsigned(Value);
38 : }
39 953 : }
40 :
41 70858 : void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
42 : assert(DwarfReg >= 0 && "invalid negative dwarf register number");
43 : assert((LocationKind == Unknown || LocationKind == Register) &&
44 : "location description already locked down");
45 70858 : LocationKind = Register;
46 70858 : if (DwarfReg < 32) {
47 70828 : emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
48 : } else {
49 30 : emitOp(dwarf::DW_OP_regx, Comment);
50 30 : emitUnsigned(DwarfReg);
51 : }
52 70858 : }
53 :
54 20211 : void DwarfExpression::addBReg(int DwarfReg, int Offset) {
55 : assert(DwarfReg >= 0 && "invalid negative dwarf register number");
56 : assert(LocationKind != Register && "location description already locked down");
57 20211 : if (DwarfReg < 32) {
58 20208 : emitOp(dwarf::DW_OP_breg0 + DwarfReg);
59 : } else {
60 3 : emitOp(dwarf::DW_OP_bregx);
61 3 : emitUnsigned(DwarfReg);
62 : }
63 20211 : emitSigned(Offset);
64 20211 : }
65 :
66 699 : void DwarfExpression::addFBReg(int Offset) {
67 699 : emitOp(dwarf::DW_OP_fbreg);
68 699 : emitSigned(Offset);
69 699 : }
70 :
71 71834 : void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
72 71834 : if (!SizeInBits)
73 : return;
74 :
75 : const unsigned SizeOfByte = 8;
76 993 : if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
77 6 : emitOp(dwarf::DW_OP_bit_piece);
78 6 : emitUnsigned(SizeInBits);
79 6 : emitUnsigned(OffsetInBits);
80 : } else {
81 987 : emitOp(dwarf::DW_OP_piece);
82 987 : unsigned ByteSize = SizeInBits / SizeOfByte;
83 987 : emitUnsigned(ByteSize);
84 : }
85 993 : this->OffsetInBits += SizeInBits;
86 : }
87 :
88 0 : void DwarfExpression::addShr(unsigned ShiftBy) {
89 0 : emitConstu(ShiftBy);
90 0 : emitOp(dwarf::DW_OP_shr);
91 0 : }
92 :
93 1 : void DwarfExpression::addAnd(unsigned Mask) {
94 1 : emitConstu(Mask);
95 1 : emitOp(dwarf::DW_OP_and);
96 1 : }
97 :
98 97715 : bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
99 : unsigned MachineReg, unsigned MaxSize) {
100 97715 : if (!TRI.isPhysicalRegister(MachineReg)) {
101 5922 : if (isFrameRegister(TRI, MachineReg)) {
102 0 : DwarfRegs.push_back({-1, 0, nullptr});
103 0 : return true;
104 : }
105 : return false;
106 : }
107 :
108 91793 : int Reg = TRI.getDwarfRegNum(MachineReg, false);
109 :
110 : // If this is a valid register number, emit it.
111 91793 : if (Reg >= 0) {
112 89155 : DwarfRegs.push_back({Reg, 0, nullptr});
113 89155 : return true;
114 : }
115 :
116 : // Walk up the super-register chain until we find a valid number.
117 : // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
118 3763 : for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
119 3724 : Reg = TRI.getDwarfRegNum(*SR, false);
120 3724 : if (Reg >= 0) {
121 2599 : unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
122 2599 : unsigned Size = TRI.getSubRegIdxSize(Idx);
123 2599 : unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
124 2599 : DwarfRegs.push_back({Reg, 0, "super-register"});
125 : // Use a DW_OP_bit_piece to describe the sub-register.
126 : setSubRegisterPiece(Size, RegOffset);
127 : return true;
128 : }
129 : }
130 :
131 : // Otherwise, attempt to find a covering set of sub-register numbers.
132 : // For example, Q0 on ARM is a composition of D0+D1.
133 : unsigned CurPos = 0;
134 : // The size of the register in bits.
135 39 : const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
136 : unsigned RegSize = TRI.getRegSizeInBits(*RC);
137 : // Keep track of the bits in the register we already emitted, so we
138 : // can avoid emitting redundant aliasing subregs. Because this is
139 : // just doing a greedy scan of all subregisters, it is possible that
140 : // this doesn't find a combination of subregisters that fully cover
141 : // the register (even though one may exist).
142 78 : SmallBitVector Coverage(RegSize, false);
143 95 : for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
144 56 : unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
145 56 : unsigned Size = TRI.getSubRegIdxSize(Idx);
146 56 : unsigned Offset = TRI.getSubRegIdxOffset(Idx);
147 56 : Reg = TRI.getDwarfRegNum(*SR, false);
148 56 : if (Reg < 0)
149 24 : continue;
150 :
151 : // Intersection between the bits we already emitted and the bits
152 : // covered by this subregister.
153 64 : SmallBitVector CurSubReg(RegSize, false);
154 32 : CurSubReg.set(Offset, Offset + Size);
155 :
156 : // If this sub-register has a DWARF number and we haven't covered
157 : // its range, emit a DWARF piece for it.
158 32 : if (CurSubReg.test(Coverage)) {
159 : // Emit a piece for any gap in the coverage.
160 28 : if (Offset > CurPos)
161 0 : DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
162 84 : DwarfRegs.push_back(
163 30 : {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
164 28 : if (Offset >= MaxSize)
165 : break;
166 :
167 : // Mark it as emitted.
168 28 : Coverage.set(Offset, Offset + Size);
169 : CurPos = Offset + Size;
170 : }
171 : }
172 : // Failed to find any DWARF encoding.
173 39 : if (CurPos == 0)
174 : return false;
175 : // Found a partial or complete DWARF encoding.
176 14 : if (CurPos < RegSize)
177 0 : DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
178 : return true;
179 : }
180 :
181 14660 : void DwarfExpression::addStackValue() {
182 14660 : if (DwarfVersion >= 4)
183 14636 : emitOp(dwarf::DW_OP_stack_value);
184 14660 : }
185 :
186 87 : void DwarfExpression::addSignedConstant(int64_t Value) {
187 : assert(LocationKind == Implicit || LocationKind == Unknown);
188 87 : LocationKind = Implicit;
189 87 : emitOp(dwarf::DW_OP_consts);
190 87 : emitSigned(Value);
191 87 : }
192 :
193 698 : void DwarfExpression::addUnsignedConstant(uint64_t Value) {
194 : assert(LocationKind == Implicit || LocationKind == Unknown);
195 698 : LocationKind = Implicit;
196 698 : emitConstu(Value);
197 698 : }
198 :
199 9 : void DwarfExpression::addUnsignedConstant(const APInt &Value) {
200 : assert(LocationKind == Implicit || LocationKind == Unknown);
201 9 : LocationKind = Implicit;
202 :
203 9 : unsigned Size = Value.getBitWidth();
204 : const uint64_t *Data = Value.getRawData();
205 :
206 : // Chop it up into 64-bit pieces, because that's the maximum that
207 : // addUnsignedConstant takes.
208 : unsigned Offset = 0;
209 15 : while (Offset < Size) {
210 12 : addUnsignedConstant(*Data++);
211 12 : if (Offset == 0 && Size <= 64)
212 : break;
213 6 : addStackValue();
214 9 : addOpPiece(std::min(Size - Offset, 64u), Offset);
215 6 : Offset += 64;
216 : }
217 9 : }
218 :
219 97715 : bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
220 : DIExpressionCursor &ExprCursor,
221 : unsigned MachineReg,
222 : unsigned FragmentOffsetInBits) {
223 97715 : auto Fragment = ExprCursor.getFragmentInfo();
224 97715 : if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
225 5947 : LocationKind = Unknown;
226 5947 : return false;
227 : }
228 :
229 : bool HasComplexExpression = false;
230 : auto Op = ExprCursor.peek();
231 91768 : if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
232 : HasComplexExpression = true;
233 :
234 : // If the register can only be described by a complex expression (i.e.,
235 : // multiple subregisters) it doesn't safely compose with another complex
236 : // expression. For example, it is not possible to apply a DW_OP_deref
237 : // operation to multiple DW_OP_pieces.
238 20569 : if (HasComplexExpression && DwarfRegs.size() > 1) {
239 : DwarfRegs.clear();
240 3 : LocationKind = Unknown;
241 3 : return false;
242 : }
243 :
244 : // Handle simple register locations.
245 91765 : if (LocationKind != Memory && !HasComplexExpression) {
246 141705 : for (auto &Reg : DwarfRegs) {
247 70858 : if (Reg.DwarfRegNo >= 0)
248 70858 : addReg(Reg.DwarfRegNo, Reg.Comment);
249 70858 : addOpPiece(Reg.Size);
250 : }
251 : DwarfRegs.clear();
252 70847 : return true;
253 : }
254 :
255 : // Don't emit locations that cannot be expressed without DW_OP_stack_value.
256 20918 : if (DwarfVersion < 4)
257 133 : if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
258 : [](DIExpression::ExprOperand Op) -> bool {
259 0 : return Op.getOp() == dwarf::DW_OP_stack_value;
260 : })) {
261 : DwarfRegs.clear();
262 8 : LocationKind = Unknown;
263 8 : return false;
264 : }
265 :
266 : assert(DwarfRegs.size() == 1);
267 20910 : auto Reg = DwarfRegs[0];
268 20910 : bool FBReg = isFrameRegister(TRI, MachineReg);
269 : int SignedOffset = 0;
270 : assert(Reg.Size == 0 && "subregister has same size as superregister");
271 :
272 : // Pattern-match combinations for which more efficient representations exist.
273 : // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
274 20910 : if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
275 19233 : SignedOffset = Op->getArg(0);
276 : ExprCursor.take();
277 : }
278 :
279 : // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
280 : // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
281 : // If Reg is a subregister we need to mask it out before subtracting.
282 20910 : if (Op && Op->getOp() == dwarf::DW_OP_constu) {
283 990 : auto N = ExprCursor.peekNext();
284 1980 : if (N && (N->getOp() == dwarf::DW_OP_plus ||
285 1942 : (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
286 952 : int Offset = Op->getArg(0);
287 952 : SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
288 : ExprCursor.consume(2);
289 : }
290 : }
291 :
292 20910 : if (FBReg)
293 699 : addFBReg(SignedOffset);
294 : else
295 20211 : addBReg(Reg.DwarfRegNo, SignedOffset);
296 : DwarfRegs.clear();
297 20910 : return true;
298 : }
299 :
300 : /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
301 1497 : static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
302 1500 : while (ExprCursor) {
303 : auto Op = ExprCursor.take();
304 940 : switch (Op->getOp()) {
305 : case dwarf::DW_OP_deref:
306 : case dwarf::DW_OP_LLVM_fragment:
307 : break;
308 937 : default:
309 : return false;
310 : }
311 : }
312 : return true;
313 : }
314 :
315 93479 : void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
316 : unsigned FragmentOffsetInBits) {
317 : // If we need to mask out a subregister, do it now, unless the next
318 : // operation would emit an OpPiece anyway.
319 : auto N = ExprCursor.peek();
320 93479 : if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
321 1 : maskSubRegister();
322 :
323 113353 : while (ExprCursor) {
324 : auto Op = ExprCursor.take();
325 20563 : switch (Op->getOp()) {
326 : case dwarf::DW_OP_LLVM_fragment: {
327 689 : unsigned SizeInBits = Op->getArg(1);
328 689 : unsigned FragmentOffset = Op->getArg(0);
329 : // The fragment offset must have already been adjusted by emitting an
330 : // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
331 : // location.
332 : assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
333 :
334 : // If addMachineReg already emitted DW_OP_piece operations to represent
335 : // a super-register by splicing together sub-registers, subtract the size
336 : // of the pieces that was already emitted.
337 689 : SizeInBits -= OffsetInBits - FragmentOffset;
338 :
339 : // If addMachineReg requested a DW_OP_bit_piece to stencil out a
340 : // sub-register that is smaller than the current fragment's size, use it.
341 689 : if (SubRegisterSizeInBits)
342 53 : SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
343 :
344 : // Emit a DW_OP_stack_value for implicit location descriptions.
345 689 : if (LocationKind == Implicit)
346 123 : addStackValue();
347 :
348 : // Emit the DW_OP_piece.
349 689 : addOpPiece(SizeInBits, SubRegisterOffsetInBits);
350 : setSubRegisterPiece(0, 0);
351 : // Reset the location description kind.
352 689 : LocationKind = Unknown;
353 : return;
354 : }
355 3884 : case dwarf::DW_OP_plus_uconst:
356 : assert(LocationKind != Register);
357 3884 : emitOp(dwarf::DW_OP_plus_uconst);
358 7768 : emitUnsigned(Op->getArg(0));
359 3884 : break;
360 237 : case dwarf::DW_OP_plus:
361 : case dwarf::DW_OP_minus:
362 : case dwarf::DW_OP_mul:
363 : case dwarf::DW_OP_div:
364 : case dwarf::DW_OP_mod:
365 : case dwarf::DW_OP_or:
366 : case dwarf::DW_OP_and:
367 : case dwarf::DW_OP_xor:
368 : case dwarf::DW_OP_shl:
369 : case dwarf::DW_OP_shr:
370 : case dwarf::DW_OP_shra:
371 : case dwarf::DW_OP_lit0:
372 : case dwarf::DW_OP_not:
373 : case dwarf::DW_OP_dup:
374 237 : emitOp(Op->getOp());
375 237 : break;
376 1606 : case dwarf::DW_OP_deref:
377 : assert(LocationKind != Register);
378 1606 : if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
379 : // Turning this into a memory location description makes the deref
380 : // implicit.
381 560 : LocationKind = Memory;
382 : else
383 1046 : emitOp(dwarf::DW_OP_deref);
384 : break;
385 : case dwarf::DW_OP_constu:
386 : assert(LocationKind != Register);
387 254 : emitConstu(Op->getArg(0));
388 254 : break;
389 13873 : case dwarf::DW_OP_stack_value:
390 13873 : LocationKind = Implicit;
391 13873 : break;
392 10 : case dwarf::DW_OP_swap:
393 : assert(LocationKind != Register);
394 10 : emitOp(dwarf::DW_OP_swap);
395 10 : break;
396 10 : case dwarf::DW_OP_xderef:
397 : assert(LocationKind != Register);
398 10 : emitOp(dwarf::DW_OP_xderef);
399 10 : break;
400 0 : default:
401 0 : llvm_unreachable("unhandled opcode found in expression");
402 : }
403 : }
404 :
405 92790 : if (LocationKind == Implicit)
406 : // Turn this into an implicit location description.
407 14531 : addStackValue();
408 : }
409 :
410 : /// add masking operations to stencil out a subregister.
411 1 : void DwarfExpression::maskSubRegister() {
412 : assert(SubRegisterSizeInBits && "no subregister was registered");
413 1 : if (SubRegisterOffsetInBits > 0)
414 0 : addShr(SubRegisterOffsetInBits);
415 1 : uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
416 1 : addAnd(Mask);
417 1 : }
418 :
419 93287 : void DwarfExpression::finalize() {
420 : assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
421 : // Emit any outstanding DW_OP_piece operations to mask out subregisters.
422 93287 : if (SubRegisterSizeInBits == 0)
423 : return;
424 : // Don't emit a DW_OP_piece for a subregister at offset 0.
425 2546 : if (SubRegisterOffsetInBits == 0)
426 : return;
427 1 : addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
428 : }
429 :
430 88715 : void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
431 177430 : if (!Expr || !Expr->isFragment())
432 88018 : return;
433 :
434 697 : uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
435 : assert(FragmentOffset >= OffsetInBits &&
436 : "overlapping or duplicate fragments");
437 697 : if (FragmentOffset > OffsetInBits)
438 280 : addOpPiece(FragmentOffset - OffsetInBits);
439 697 : OffsetInBits = FragmentOffset;
440 : }
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