Line data Source code
1 : //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file
11 : /// Analysis that tracks defined/used subregister lanes across COPY instructions
12 : /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
13 : /// INSERT_SUBREG, EXTRACT_SUBREG).
14 : /// The information is used to detect dead definitions and the usage of
15 : /// (completely) undefined values and mark the operands as such.
16 : /// This pass is necessary because the dead/undef status is not obvious anymore
17 : /// when subregisters are involved.
18 : ///
19 : /// Example:
20 : /// %0 = some definition
21 : /// %1 = IMPLICIT_DEF
22 : /// %2 = REG_SEQUENCE %0, sub0, %1, sub1
23 : /// %3 = EXTRACT_SUBREG %2, sub1
24 : /// = use %3
25 : /// The %0 definition is dead and %3 contains an undefined value.
26 : //
27 : //===----------------------------------------------------------------------===//
28 :
29 : #include <deque>
30 : #include <vector>
31 :
32 : #include "llvm/ADT/BitVector.h"
33 : #include "llvm/ADT/SetVector.h"
34 : #include "llvm/CodeGen/MachineFunctionPass.h"
35 : #include "llvm/CodeGen/MachineRegisterInfo.h"
36 : #include "llvm/CodeGen/Passes.h"
37 : #include "llvm/CodeGen/TargetRegisterInfo.h"
38 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 : #include "llvm/InitializePasses.h"
40 : #include "llvm/Pass.h"
41 : #include "llvm/PassRegistry.h"
42 : #include "llvm/Support/Debug.h"
43 : #include "llvm/Support/raw_ostream.h"
44 :
45 : using namespace llvm;
46 :
47 : #define DEBUG_TYPE "detect-dead-lanes"
48 :
49 : namespace {
50 :
51 : /// Contains a bitmask of which lanes of a given virtual register are
52 : /// defined and which ones are actually used.
53 : struct VRegInfo {
54 : LaneBitmask UsedLanes;
55 : LaneBitmask DefinedLanes;
56 : };
57 :
58 : class DetectDeadLanes : public MachineFunctionPass {
59 : public:
60 : bool runOnMachineFunction(MachineFunction &MF) override;
61 :
62 : static char ID;
63 19976 : DetectDeadLanes() : MachineFunctionPass(ID) {}
64 :
65 19827 : StringRef getPassName() const override { return "Detect Dead Lanes"; }
66 :
67 19811 : void getAnalysisUsage(AnalysisUsage &AU) const override {
68 19811 : AU.setPreservesCFG();
69 19811 : MachineFunctionPass::getAnalysisUsage(AU);
70 19811 : }
71 :
72 : private:
73 : /// Add used lane bits on the register used by operand \p MO. This translates
74 : /// the bitmask based on the operands subregister, and puts the register into
75 : /// the worklist if any new bits were added.
76 : void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
77 :
78 : /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
79 : /// COPY-like instruction determine the lanes used on the use operands
80 : /// and call addUsedLanesOnOperand() for them.
81 : void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
82 :
83 : /// Given a use regiser operand \p Use and a mask of defined lanes, check
84 : /// if the operand belongs to a lowersToCopies() instruction, transfer the
85 : /// mask to the def and put the instruction into the worklist.
86 : void transferDefinedLanesStep(const MachineOperand &Use,
87 : LaneBitmask DefinedLanes);
88 :
89 : /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
90 : /// of COPY-like instruction, determine which lanes are defined at the output
91 : /// operand \p Def.
92 : LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
93 : LaneBitmask DefinedLanes) const;
94 :
95 : /// Given a mask \p UsedLanes used from the output of instruction \p MI
96 : /// determine which lanes are used from operand \p MO of this instruction.
97 : LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
98 : const MachineOperand &MO) const;
99 :
100 : bool runOnce(MachineFunction &MF);
101 :
102 : LaneBitmask determineInitialDefinedLanes(unsigned Reg);
103 : LaneBitmask determineInitialUsedLanes(unsigned Reg);
104 :
105 : bool isUndefRegAtInput(const MachineOperand &MO,
106 : const VRegInfo &RegInfo) const;
107 :
108 : bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
109 :
110 : const MachineRegisterInfo *MRI;
111 : const TargetRegisterInfo *TRI;
112 :
113 314006 : void PutInWorklist(unsigned RegIdx) {
114 628012 : if (WorklistMembers.test(RegIdx))
115 : return;
116 : WorklistMembers.set(RegIdx);
117 241491 : Worklist.push_back(RegIdx);
118 : }
119 :
120 : VRegInfo *VRegInfos;
121 : /// Worklist containing virtreg indexes.
122 : std::deque<unsigned> Worklist;
123 : BitVector WorklistMembers;
124 : /// This bitvector is set for each vreg index where the vreg is defined
125 : /// by an instruction where lowersToCopies()==true.
126 : BitVector DefinedByCopy;
127 : };
128 :
129 : } // end anonymous namespace
130 :
131 : char DetectDeadLanes::ID = 0;
132 : char &llvm::DetectDeadLanesID = DetectDeadLanes::ID;
133 :
134 85147 : INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
135 :
136 : /// Returns true if \p MI will get lowered to a series of COPY instructions.
137 : /// We call this a COPY-like instruction.
138 : static bool lowersToCopies(const MachineInstr &MI) {
139 : // Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
140 : // isExtractSubRegLike(), isInsertSubregLike() in the future even though they
141 : // are not lowered to a COPY.
142 0 : switch (MI.getOpcode()) {
143 : case TargetOpcode::COPY:
144 : case TargetOpcode::PHI:
145 : case TargetOpcode::INSERT_SUBREG:
146 : case TargetOpcode::REG_SEQUENCE:
147 : case TargetOpcode::EXTRACT_SUBREG:
148 : return true;
149 : }
150 : return false;
151 : }
152 :
153 498925 : static bool isCrossCopy(const MachineRegisterInfo &MRI,
154 : const MachineInstr &MI,
155 : const TargetRegisterClass *DstRC,
156 : const MachineOperand &MO) {
157 : assert(lowersToCopies(MI));
158 498925 : unsigned SrcReg = MO.getReg();
159 : const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
160 498925 : if (DstRC == SrcRC)
161 : return false;
162 :
163 : unsigned SrcSubIdx = MO.getSubReg();
164 :
165 439534 : const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
166 : unsigned DstSubIdx = 0;
167 879068 : switch (MI.getOpcode()) {
168 : case TargetOpcode::INSERT_SUBREG:
169 358 : if (MI.getOperandNo(&MO) == 2)
170 322 : DstSubIdx = MI.getOperand(3).getImm();
171 : break;
172 : case TargetOpcode::REG_SEQUENCE: {
173 : unsigned OpNum = MI.getOperandNo(&MO);
174 270575 : DstSubIdx = MI.getOperand(OpNum+1).getImm();
175 270575 : break;
176 : }
177 10 : case TargetOpcode::EXTRACT_SUBREG: {
178 10 : unsigned SubReg = MI.getOperand(2).getImm();
179 : SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
180 : }
181 : }
182 :
183 : unsigned PreA, PreB; // Unused.
184 439534 : if (SrcSubIdx && DstSubIdx)
185 4349 : return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
186 4349 : PreB);
187 435185 : if (SrcSubIdx)
188 98449 : return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
189 336736 : if (DstSubIdx)
190 266548 : return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
191 70188 : return !TRI.getCommonSubClass(SrcRC, DstRC);
192 : }
193 :
194 304484 : void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
195 : LaneBitmask UsedLanes) {
196 : if (!MO.readsReg())
197 : return;
198 304464 : unsigned MOReg = MO.getReg();
199 304464 : if (!TargetRegisterInfo::isVirtualRegister(MOReg))
200 : return;
201 :
202 : unsigned MOSubReg = MO.getSubReg();
203 304464 : if (MOSubReg != 0)
204 95628 : UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
205 304464 : UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
206 :
207 : unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg);
208 304464 : VRegInfo &MORegInfo = VRegInfos[MORegIdx];
209 304464 : LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
210 : // Any change at all?
211 304464 : if ((UsedLanes & ~PrevUsedLanes).none())
212 : return;
213 :
214 : // Set UsedLanes and remember instruction for further propagation.
215 192344 : MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
216 192344 : if (DefinedByCopy.test(MORegIdx))
217 61558 : PutInWorklist(MORegIdx);
218 : }
219 :
220 241491 : void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
221 : LaneBitmask UsedLanes) {
222 799506 : for (const MachineOperand &MO : MI.uses()) {
223 558015 : if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
224 253531 : continue;
225 304484 : LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
226 304484 : addUsedLanesOnOperand(MO, UsedOnMO);
227 : }
228 241491 : }
229 :
230 0 : LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
231 : LaneBitmask UsedLanes,
232 : const MachineOperand &MO) const {
233 : unsigned OpNum = MI.getOperandNo(&MO);
234 : assert(lowersToCopies(MI) && DefinedByCopy[
235 : TargetRegisterInfo::virtReg2Index(MI.getOperand(0).getReg())]);
236 :
237 0 : switch (MI.getOpcode()) {
238 0 : case TargetOpcode::COPY:
239 : case TargetOpcode::PHI:
240 0 : return UsedLanes;
241 0 : case TargetOpcode::REG_SEQUENCE: {
242 : assert(OpNum % 2 == 1);
243 0 : unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
244 0 : return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
245 : }
246 0 : case TargetOpcode::INSERT_SUBREG: {
247 0 : unsigned SubIdx = MI.getOperand(3).getImm();
248 : LaneBitmask MO2UsedLanes =
249 0 : TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
250 0 : if (OpNum == 2)
251 0 : return MO2UsedLanes;
252 :
253 0 : const MachineOperand &Def = MI.getOperand(0);
254 0 : unsigned DefReg = Def.getReg();
255 0 : const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
256 : LaneBitmask MO1UsedLanes;
257 0 : if (RC->CoveredBySubRegs)
258 0 : MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
259 : else
260 0 : MO1UsedLanes = RC->LaneMask;
261 :
262 : assert(OpNum == 1);
263 0 : return MO1UsedLanes;
264 : }
265 0 : case TargetOpcode::EXTRACT_SUBREG: {
266 : assert(OpNum == 1);
267 0 : unsigned SubIdx = MI.getOperand(2).getImm();
268 0 : return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
269 : }
270 0 : default:
271 0 : llvm_unreachable("function must be called with COPY-like instruction");
272 : }
273 : }
274 :
275 292599 : void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
276 : LaneBitmask DefinedLanes) {
277 : if (!Use.readsReg())
278 : return;
279 : // Check whether the operand writes a vreg and is part of a COPY-like
280 : // instruction.
281 292499 : const MachineInstr &MI = *Use.getParent();
282 292499 : if (MI.getDesc().getNumDefs() != 1)
283 : return;
284 : // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
285 : // they really need to be modeled differently!
286 231074 : if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
287 : return;
288 : const MachineOperand &Def = *MI.defs().begin();
289 231074 : unsigned DefReg = Def.getReg();
290 231074 : if (!TargetRegisterInfo::isVirtualRegister(DefReg))
291 : return;
292 : unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
293 222294 : if (!DefinedByCopy.test(DefRegIdx))
294 : return;
295 :
296 : unsigned OpNum = MI.getOperandNo(&Use);
297 : DefinedLanes =
298 131213 : TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
299 131213 : DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
300 :
301 131213 : VRegInfo &RegInfo = VRegInfos[DefRegIdx];
302 131213 : LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
303 : // Any change at all?
304 131213 : if ((DefinedLanes & ~PrevDefinedLanes).none())
305 : return;
306 :
307 61426 : RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
308 61426 : PutInWorklist(DefRegIdx);
309 : }
310 :
311 0 : LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
312 : unsigned OpNum, LaneBitmask DefinedLanes) const {
313 0 : const MachineInstr &MI = *Def.getParent();
314 : // Translate DefinedLanes if necessary.
315 0 : switch (MI.getOpcode()) {
316 0 : case TargetOpcode::REG_SEQUENCE: {
317 0 : unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
318 0 : DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
319 0 : DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
320 0 : break;
321 : }
322 0 : case TargetOpcode::INSERT_SUBREG: {
323 0 : unsigned SubIdx = MI.getOperand(3).getImm();
324 0 : if (OpNum == 2) {
325 0 : DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
326 0 : DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
327 : } else {
328 : assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
329 : // Ignore lanes defined by operand 2.
330 0 : DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
331 : }
332 : break;
333 : }
334 0 : case TargetOpcode::EXTRACT_SUBREG: {
335 0 : unsigned SubIdx = MI.getOperand(2).getImm();
336 : assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
337 0 : DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
338 : break;
339 : }
340 : case TargetOpcode::COPY:
341 : case TargetOpcode::PHI:
342 : break;
343 0 : default:
344 0 : llvm_unreachable("function must be called with COPY-like instruction");
345 : }
346 :
347 : assert(Def.getSubReg() == 0 &&
348 : "Should not have subregister defs in machine SSA phase");
349 0 : DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
350 0 : return DefinedLanes;
351 : }
352 :
353 811984 : LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
354 : // Live-In or unused registers have no definition but are considered fully
355 : // defined.
356 811984 : if (!MRI->hasOneDef(Reg))
357 366455 : return LaneBitmask::getAll();
358 :
359 445529 : const MachineOperand &Def = *MRI->def_begin(Reg);
360 445529 : const MachineInstr &DefMI = *Def.getParent();
361 : if (lowersToCopies(DefMI)) {
362 : // Start optimisatically with no used or defined lanes for copy
363 : // instructions. The following dataflow analysis will add more bits.
364 : unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
365 : DefinedByCopy.set(RegIdx);
366 191022 : PutInWorklist(RegIdx);
367 :
368 191022 : if (Def.isDead())
369 22 : return LaneBitmask::getNone();
370 :
371 : // COPY/PHI can copy across unrelated register classes (example: float/int)
372 : // with incompatible subregister structure. Do not include these in the
373 : // dataflow analysis since we cannot transfer lanemasks in a meaningful way.
374 191000 : const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
375 :
376 : // Determine initially DefinedLanes.
377 : LaneBitmask DefinedLanes;
378 654535 : for (const MachineOperand &MO : DefMI.uses()) {
379 463535 : if (!MO.isReg() || !MO.readsReg())
380 : continue;
381 298222 : unsigned MOReg = MO.getReg();
382 298222 : if (!MOReg)
383 : continue;
384 :
385 : LaneBitmask MODefinedLanes;
386 298222 : if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
387 : MODefinedLanes = LaneBitmask::getAll();
388 250785 : } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
389 : MODefinedLanes = LaneBitmask::getAll();
390 : } else {
391 : assert(TargetRegisterInfo::isVirtualRegister(MOReg));
392 217136 : if (MRI->hasOneDef(MOReg)) {
393 217136 : const MachineOperand &MODef = *MRI->def_begin(MOReg);
394 217136 : const MachineInstr &MODefMI = *MODef.getParent();
395 : // Bits from copy-like operations will be added later.
396 151747 : if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
397 : continue;
398 : }
399 : unsigned MOSubReg = MO.getSubReg();
400 147656 : MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
401 147656 : MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
402 : MOSubReg, MODefinedLanes);
403 : }
404 :
405 : unsigned OpNum = DefMI.getOperandNo(&MO);
406 228742 : DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
407 : }
408 191000 : return DefinedLanes;
409 : }
410 254507 : if (DefMI.isImplicitDef() || Def.isDead())
411 12308 : return LaneBitmask::getNone();
412 :
413 : assert(Def.getSubReg() == 0 &&
414 : "Should not have subregister defs in machine SSA phase");
415 242199 : return MRI->getMaxLaneMaskForVReg(Reg);
416 : }
417 :
418 0 : LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
419 : LaneBitmask UsedLanes = LaneBitmask::getNone();
420 0 : for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
421 0 : if (!MO.readsReg())
422 0 : continue;
423 :
424 0 : const MachineInstr &UseMI = *MO.getParent();
425 0 : if (UseMI.isKill())
426 0 : continue;
427 :
428 : unsigned SubReg = MO.getSubReg();
429 : if (lowersToCopies(UseMI)) {
430 : assert(UseMI.getDesc().getNumDefs() == 1);
431 0 : const MachineOperand &Def = *UseMI.defs().begin();
432 0 : unsigned DefReg = Def.getReg();
433 : // The used lanes of COPY-like instruction operands are determined by the
434 : // following dataflow analysis.
435 0 : if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
436 : // But ignore copies across incompatible register classes.
437 : bool CrossCopy = false;
438 : if (lowersToCopies(UseMI)) {
439 0 : const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
440 0 : CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
441 : if (CrossCopy)
442 : LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
443 : }
444 :
445 0 : if (!CrossCopy)
446 0 : continue;
447 : }
448 : }
449 :
450 : // Shortcut: All lanes are used.
451 0 : if (SubReg == 0)
452 0 : return MRI->getMaxLaneMaskForVReg(Reg);
453 :
454 0 : UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
455 : }
456 0 : return UsedLanes;
457 : }
458 :
459 0 : bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
460 : const VRegInfo &RegInfo) const {
461 : unsigned SubReg = MO.getSubReg();
462 623141 : LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
463 623141 : return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
464 : }
465 :
466 612188 : bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
467 : bool *CrossCopy) const {
468 612188 : if (!MO.isUse())
469 : return false;
470 612188 : const MachineInstr &MI = *MO.getParent();
471 : if (!lowersToCopies(MI))
472 : return false;
473 254143 : const MachineOperand &Def = MI.getOperand(0);
474 254143 : unsigned DefReg = Def.getReg();
475 254143 : if (!TargetRegisterInfo::isVirtualRegister(DefReg))
476 : return false;
477 : unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
478 241151 : if (!DefinedByCopy.test(DefRegIdx))
479 : return false;
480 :
481 241151 : const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
482 241151 : LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
483 241151 : if (UsedLanes.any())
484 : return false;
485 :
486 111 : unsigned MOReg = MO.getReg();
487 111 : if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
488 111 : const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
489 111 : *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
490 : }
491 : return true;
492 : }
493 :
494 25152 : bool DetectDeadLanes::runOnce(MachineFunction &MF) {
495 : // First pass: Populate defs/uses of vregs with initial values
496 25152 : unsigned NumVirtRegs = MRI->getNumVirtRegs();
497 837136 : for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
498 : unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
499 :
500 : // Determine used/defined lanes and add copy instructions to worklist.
501 811984 : VRegInfo &Info = VRegInfos[RegIdx];
502 811984 : Info.DefinedLanes = determineInitialDefinedLanes(Reg);
503 811984 : Info.UsedLanes = determineInitialUsedLanes(Reg);
504 : }
505 :
506 : // Iterate as long as defined lanes/used lanes keep changing.
507 266643 : while (!Worklist.empty()) {
508 241491 : unsigned RegIdx = Worklist.front();
509 241491 : Worklist.pop_front();
510 : WorklistMembers.reset(RegIdx);
511 241491 : VRegInfo &Info = VRegInfos[RegIdx];
512 : unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
513 :
514 : // Transfer UsedLanes to operands of DefMI (backwards dataflow).
515 241491 : MachineOperand &Def = *MRI->def_begin(Reg);
516 241491 : const MachineInstr &MI = *Def.getParent();
517 241491 : transferUsedLanesStep(MI, Info.UsedLanes);
518 : // Transfer DefinedLanes to users of Reg (forward dataflow).
519 775581 : for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
520 292599 : transferDefinedLanesStep(MO, Info.DefinedLanes);
521 : }
522 :
523 : LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
524 : RegIdx < NumVirtRegs;
525 : ++RegIdx) {
526 : unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
527 : const VRegInfo &Info = VRegInfos[RegIdx];
528 : dbgs() << printReg(Reg, nullptr)
529 : << " Used: " << PrintLaneMask(Info.UsedLanes)
530 : << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
531 : } dbgs() << "\n";);
532 :
533 : bool Again = false;
534 : // Mark operands as dead/unused.
535 54953 : for (MachineBasicBlock &MBB : MF) {
536 557630 : for (MachineInstr &MI : MBB) {
537 3258054 : for (MachineOperand &MO : MI.operands()) {
538 2730225 : if (!MO.isReg())
539 : continue;
540 1457758 : unsigned Reg = MO.getReg();
541 1457758 : if (!TargetRegisterInfo::isVirtualRegister(Reg))
542 : continue;
543 : unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
544 1068781 : const VRegInfo &RegInfo = VRegInfos[RegIdx];
545 1068781 : if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
546 : LLVM_DEBUG(dbgs()
547 : << "Marking operand '" << MO << "' as dead in " << MI);
548 : MO.setIsDead();
549 : }
550 : if (MO.readsReg()) {
551 623141 : bool CrossCopy = false;
552 1246282 : if (isUndefRegAtInput(MO, RegInfo)) {
553 : LLVM_DEBUG(dbgs()
554 : << "Marking operand '" << MO << "' as undef in " << MI);
555 : MO.setIsUndef();
556 612188 : } else if (isUndefInput(MO, &CrossCopy)) {
557 : LLVM_DEBUG(dbgs()
558 : << "Marking operand '" << MO << "' as undef in " << MI);
559 : MO.setIsUndef();
560 111 : if (CrossCopy)
561 : Again = true;
562 : }
563 : }
564 : }
565 : }
566 : }
567 :
568 25152 : return Again;
569 : }
570 :
571 196856 : bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
572 : // Don't bother if we won't track subregister liveness later. This pass is
573 : // required for correctness if subregister liveness is enabled because the
574 : // register coalescer cannot deal with hidden dead defs. However without
575 : // subregister liveness enabled, the expected benefits of this pass are small
576 : // so we safe the compile time.
577 196856 : MRI = &MF.getRegInfo();
578 196856 : if (!MRI->subRegLivenessEnabled()) {
579 : LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
580 : return false;
581 : }
582 :
583 25150 : TRI = MRI->getTargetRegisterInfo();
584 :
585 25150 : unsigned NumVirtRegs = MRI->getNumVirtRegs();
586 837066 : VRegInfos = new VRegInfo[NumVirtRegs];
587 25150 : WorklistMembers.resize(NumVirtRegs);
588 25150 : DefinedByCopy.resize(NumVirtRegs);
589 :
590 : bool Again;
591 25152 : do {
592 25152 : Again = runOnce(MF);
593 : } while(Again);
594 :
595 : DefinedByCopy.clear();
596 : WorklistMembers.clear();
597 25150 : delete[] VRegInfos;
598 : return true;
599 : }
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