Line data    Source code

       1             : //===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the live stack slot analysis pass. It is analogous to
      11             : // live interval analysis except it's analyzing liveness of stack slots rather
      12             : // than registers.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "llvm/CodeGen/LiveStacks.h"
      17             : #include "llvm/CodeGen/LiveIntervals.h"
      18             : #include "llvm/CodeGen/Passes.h"
      19             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      20             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      21             : #include "llvm/Support/Debug.h"
      22             : #include "llvm/Support/raw_ostream.h"
      23             : using namespace llvm;
      24             : 
      25             : #define DEBUG_TYPE "livestacks"
      26             : 
      27             : char LiveStacks::ID = 0;
      28       31780 : INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
      29             :                 "Live Stack Slot Analysis", false, false)
      30       31780 : INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
      31      232034 : INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
      32             :                 "Live Stack Slot Analysis", false, false)
      33             : 
      34             : char &llvm::LiveStacksID = LiveStacks::ID;
      35             : 
      36       19760 : void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
      37             :   AU.setPreservesAll();
      38             :   AU.addPreserved<SlotIndexes>();
      39             :   AU.addRequiredTransitive<SlotIndexes>();
      40       19760 :   MachineFunctionPass::getAnalysisUsage(AU);
      41       19760 : }
      42             : 
      43      195052 : void LiveStacks::releaseMemory() {
      44             :   // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
      45      195052 :   VNInfoAllocator.Reset();
      46             :   S2IMap.clear();
      47             :   S2RCMap.clear();
      48      195052 : }
      49             : 
      50      195038 : bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
      51      195038 :   TRI = MF.getSubtarget().getRegisterInfo();
      52             :   // FIXME: No analysis is being done right now. We are relying on the
      53             :   // register allocators to provide the information.
      54      195038 :   return false;
      55             : }
      56             : 
      57             : LiveInterval &
      58       14514 : LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
      59             :   assert(Slot >= 0 && "Spill slot indice must be >= 0");
      60             :   SS2IntervalMap::iterator I = S2IMap.find(Slot);
      61       14514 :   if (I == S2IMap.end()) {
      62       14514 :     I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
      63       14514 :                        std::forward_as_tuple(
      64       29028 :                            TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
      65             :             .first;
      66       14514 :     S2RCMap.insert(std::make_pair(Slot, RC));
      67             :   } else {
      68             :     // Use the largest common subclass register class.
      69           0 :     const TargetRegisterClass *OldRC = S2RCMap[Slot];
      70           0 :     S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
      71             :   }
      72       14514 :   return I->second;
      73             : }
      74             : 
      75             : /// print - Implement the dump method.
      76           0 : void LiveStacks::print(raw_ostream &OS, const Module*) const {
      77             : 
      78           0 :   OS << "********** INTERVALS **********\n";
      79           0 :   for (const_iterator I = begin(), E = end(); I != E; ++I) {
      80           0 :     I->second.print(OS);
      81           0 :     int Slot = I->first;
      82             :     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
      83           0 :     if (RC)
      84           0 :       OS << " [" << TRI->getRegClassName(RC) << "]\n";
      85             :     else
      86           0 :       OS << " [Unknown]\n";
      87             :   }
      88           0 : }