Line data Source code
1 : //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // Implementation of the MachineRegisterInfo class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "llvm/CodeGen/MachineRegisterInfo.h"
15 : #include "llvm/ADT/iterator_range.h"
16 : #include "llvm/CodeGen/LowLevelType.h"
17 : #include "llvm/CodeGen/MachineBasicBlock.h"
18 : #include "llvm/CodeGen/MachineFunction.h"
19 : #include "llvm/CodeGen/MachineInstr.h"
20 : #include "llvm/CodeGen/MachineInstrBuilder.h"
21 : #include "llvm/CodeGen/MachineOperand.h"
22 : #include "llvm/CodeGen/TargetInstrInfo.h"
23 : #include "llvm/CodeGen/TargetRegisterInfo.h"
24 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 : #include "llvm/Config/llvm-config.h"
26 : #include "llvm/IR/Attributes.h"
27 : #include "llvm/IR/DebugLoc.h"
28 : #include "llvm/IR/Function.h"
29 : #include "llvm/MC/MCRegisterInfo.h"
30 : #include "llvm/Support/Casting.h"
31 : #include "llvm/Support/CommandLine.h"
32 : #include "llvm/Support/Compiler.h"
33 : #include "llvm/Support/ErrorHandling.h"
34 : #include "llvm/Support/raw_ostream.h"
35 : #include <cassert>
36 :
37 : using namespace llvm;
38 :
39 : static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
40 : cl::init(true), cl::desc("Enable subregister liveness tracking."));
41 :
42 : // Pin the vtable to this file.
43 0 : void MachineRegisterInfo::Delegate::anchor() {}
44 :
45 411209 : MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
46 411209 : : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47 : EnableSubRegLiveness),
48 1644836 : IsUpdatedCSRsInitialized(false) {
49 411209 : unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
50 : VRegInfo.reserve(256);
51 : RegAllocHints.reserve(256);
52 411209 : UsedPhysRegMask.resize(NumRegs);
53 156808190 : PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
54 411209 : }
55 :
56 : /// setRegClass - Set the register class of the specified virtual register.
57 : ///
58 : void
59 525668 : MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
60 : assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
61 : VRegInfo[Reg].first = RC;
62 525668 : }
63 :
64 10130 : void MachineRegisterInfo::setRegBank(unsigned Reg,
65 : const RegisterBank &RegBank) {
66 : VRegInfo[Reg].first = &RegBank;
67 10130 : }
68 :
69 : static const TargetRegisterClass *
70 21165047 : constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
71 : const TargetRegisterClass *OldRC,
72 : const TargetRegisterClass *RC, unsigned MinNumRegs) {
73 21165047 : if (OldRC == RC)
74 : return RC;
75 : const TargetRegisterClass *NewRC =
76 550458 : MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
77 550458 : if (!NewRC || NewRC == OldRC)
78 : return NewRC;
79 398762 : if (NewRC->getNumRegs() < MinNumRegs)
80 : return nullptr;
81 199255 : MRI.setRegClass(Reg, NewRC);
82 199255 : return NewRC;
83 : }
84 :
85 : const TargetRegisterClass *
86 20986145 : MachineRegisterInfo::constrainRegClass(unsigned Reg,
87 : const TargetRegisterClass *RC,
88 : unsigned MinNumRegs) {
89 20986145 : return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
90 : }
91 :
92 : bool
93 178943 : MachineRegisterInfo::constrainRegAttrs(unsigned Reg,
94 : unsigned ConstrainingReg,
95 : unsigned MinNumRegs) {
96 : auto const *OldRC = getRegClassOrNull(Reg);
97 : auto const *RC = getRegClassOrNull(ConstrainingReg);
98 : // A virtual register at any point must have either a low-level type
99 : // or a class assigned, but not both. The only exception is the internals of
100 : // GlobalISel's instruction selection pass, which is allowed to temporarily
101 : // introduce registers with types and classes both.
102 : assert((OldRC || getType(Reg).isValid()) && "Reg has neither class nor type");
103 : assert((!OldRC || !getType(Reg).isValid()) && "Reg has class and type both");
104 : assert((RC || getType(ConstrainingReg).isValid()) &&
105 : "ConstrainingReg has neither class nor type");
106 : assert((!RC || !getType(ConstrainingReg).isValid()) &&
107 : "ConstrainingReg has class and type both");
108 178943 : if (OldRC && RC)
109 178902 : return ::constrainRegClass(*this, Reg, OldRC, RC, MinNumRegs);
110 : // If one of the virtual registers is generic (used in generic machine
111 : // instructions, has a low-level type, doesn't have a class), and the other is
112 : // concrete (used in target specific instructions, doesn't have a low-level
113 : // type, has a class), we can not unify them.
114 41 : if (OldRC || RC)
115 : return false;
116 : // At this point, both registers are guaranteed to have a valid low-level
117 : // type, and they must agree.
118 : if (getType(Reg) != getType(ConstrainingReg))
119 : return false;
120 : auto const *OldRB = getRegBankOrNull(Reg);
121 : auto const *RB = getRegBankOrNull(ConstrainingReg);
122 36 : if (OldRB)
123 2 : return !RB || RB == OldRB;
124 34 : if (RB)
125 1 : setRegBank(Reg, *RB);
126 : return true;
127 : }
128 :
129 : bool
130 118459 : MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
131 118459 : const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
132 : const TargetRegisterClass *OldRC = getRegClass(Reg);
133 : const TargetRegisterClass *NewRC =
134 118459 : getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
135 :
136 : // Stop early if there is no room to grow.
137 118459 : if (NewRC == OldRC)
138 : return false;
139 :
140 : // Accumulate constraints from all uses.
141 49773 : for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
142 : // Apply the effect of the given operand to NewRC.
143 43108 : MachineInstr *MI = MO.getParent();
144 43108 : unsigned OpNo = &MO - &MI->getOperand(0);
145 43108 : NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
146 : getTargetRegisterInfo());
147 43108 : if (!NewRC || NewRC == OldRC)
148 : return false;
149 : }
150 6665 : setRegClass(Reg, NewRC);
151 6665 : return true;
152 : }
153 :
154 27048022 : unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
155 : unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
156 : VRegInfo.grow(Reg);
157 : RegAllocHints.grow(Reg);
158 27048023 : insertVRegByName(Name, Reg);
159 27048022 : return Reg;
160 : }
161 :
162 : /// createVirtualRegister - Create and return a new virtual register in the
163 : /// function with the specified register class.
164 : ///
165 : unsigned
166 27019826 : MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
167 : StringRef Name) {
168 : assert(RegClass && "Cannot create register without RegClass!");
169 : assert(RegClass->isAllocatable() &&
170 : "Virtual register RegClass must be allocatable.");
171 :
172 : // New virtual register number.
173 27019826 : unsigned Reg = createIncompleteVirtualRegister(Name);
174 : VRegInfo[Reg].first = RegClass;
175 27019826 : if (TheDelegate)
176 114650 : TheDelegate->MRI_NoteNewVirtualRegister(Reg);
177 27019826 : return Reg;
178 : }
179 :
180 15 : unsigned MachineRegisterInfo::cloneVirtualRegister(unsigned VReg,
181 : StringRef Name) {
182 15 : unsigned Reg = createIncompleteVirtualRegister(Name);
183 15 : VRegInfo[Reg].first = VRegInfo[VReg].first;
184 15 : setType(Reg, getType(VReg));
185 15 : if (TheDelegate)
186 0 : TheDelegate->MRI_NoteNewVirtualRegister(Reg);
187 15 : return Reg;
188 : }
189 :
190 25850 : void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
191 : // Check that VReg doesn't have a class.
192 : assert((getRegClassOrRegBank(VReg).isNull() ||
193 : !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) &&
194 : "Can't set the size of a non-generic virtual register");
195 : VRegToType.grow(VReg);
196 25850 : VRegToType[VReg] = Ty;
197 25850 : }
198 :
199 : unsigned
200 10913 : MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
201 : // New virtual register number.
202 10913 : unsigned Reg = createIncompleteVirtualRegister(Name);
203 : // FIXME: Should we use a dummy register class?
204 : VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
205 10913 : setType(Reg, Ty);
206 10913 : if (TheDelegate)
207 0 : TheDelegate->MRI_NoteNewVirtualRegister(Reg);
208 10913 : return Reg;
209 : }
210 :
211 5376 : void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
212 :
213 : /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
214 401942 : void MachineRegisterInfo::clearVirtRegs() {
215 : #ifndef NDEBUG
216 : for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
217 : unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
218 : if (!VRegInfo[Reg].second)
219 : continue;
220 : verifyUseList(Reg);
221 : llvm_unreachable("Remaining virtual register operands");
222 : }
223 : #endif
224 : VRegInfo.clear();
225 1058999 : for (auto &I : LiveIns)
226 657057 : I.second = 0;
227 401942 : }
228 :
229 0 : void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
230 : #ifndef NDEBUG
231 : bool Valid = true;
232 : for (MachineOperand &M : reg_operands(Reg)) {
233 : MachineOperand *MO = &M;
234 : MachineInstr *MI = MO->getParent();
235 : if (!MI) {
236 : errs() << printReg(Reg, getTargetRegisterInfo())
237 : << " use list MachineOperand " << MO
238 : << " has no parent instruction.\n";
239 : Valid = false;
240 : continue;
241 : }
242 : MachineOperand *MO0 = &MI->getOperand(0);
243 : unsigned NumOps = MI->getNumOperands();
244 : if (!(MO >= MO0 && MO < MO0+NumOps)) {
245 : errs() << printReg(Reg, getTargetRegisterInfo())
246 : << " use list MachineOperand " << MO
247 : << " doesn't belong to parent MI: " << *MI;
248 : Valid = false;
249 : }
250 : if (!MO->isReg()) {
251 : errs() << printReg(Reg, getTargetRegisterInfo())
252 : << " MachineOperand " << MO << ": " << *MO
253 : << " is not a register\n";
254 : Valid = false;
255 : }
256 : if (MO->getReg() != Reg) {
257 : errs() << printReg(Reg, getTargetRegisterInfo())
258 : << " use-list MachineOperand " << MO << ": "
259 : << *MO << " is the wrong register\n";
260 : Valid = false;
261 : }
262 : }
263 : assert(Valid && "Invalid use list");
264 : #endif
265 0 : }
266 :
267 1661447 : void MachineRegisterInfo::verifyUseLists() const {
268 : #ifndef NDEBUG
269 : for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
270 : verifyUseList(TargetRegisterInfo::index2VirtReg(i));
271 : for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
272 : verifyUseList(i);
273 : #endif
274 1661447 : }
275 :
276 : /// Add MO to the linked list of operands for its register.
277 216479261 : void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
278 : assert(!MO->isOnRegUseList() && "Already on list");
279 216479261 : MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
280 216479261 : MachineOperand *const Head = HeadRef;
281 :
282 : // Head points to the first list element.
283 : // Next is NULL on the last list element.
284 : // Prev pointers are circular, so Head->Prev == Last.
285 :
286 : // Head is NULL for an empty list.
287 216479261 : if (!Head) {
288 30752997 : MO->Contents.Reg.Prev = MO;
289 30752997 : MO->Contents.Reg.Next = nullptr;
290 30752997 : HeadRef = MO;
291 30752997 : return;
292 : }
293 : assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
294 :
295 : // Insert MO between Last and Head in the circular Prev chain.
296 185726264 : MachineOperand *Last = Head->Contents.Reg.Prev;
297 : assert(Last && "Inconsistent use list");
298 : assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
299 185726264 : Head->Contents.Reg.Prev = MO;
300 185726264 : MO->Contents.Reg.Prev = Last;
301 :
302 : // Def operands always precede uses. This allows def_iterator to stop early.
303 : // Insert def operands at the front, and use operands at the back.
304 185726264 : if (MO->isDef()) {
305 : // Insert def at the front.
306 51134122 : MO->Contents.Reg.Next = Head;
307 51134122 : HeadRef = MO;
308 : } else {
309 : // Insert use at the end.
310 134592142 : MO->Contents.Reg.Next = nullptr;
311 134592142 : Last->Contents.Reg.Next = MO;
312 : }
313 : }
314 :
315 : /// Remove MO from its use-def list.
316 105605126 : void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
317 : assert(MO->isOnRegUseList() && "Operand not on use list");
318 105605126 : MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
319 105605126 : MachineOperand *const Head = HeadRef;
320 : assert(Head && "List already empty");
321 :
322 : // Unlink this from the doubly linked list of operands.
323 105605126 : MachineOperand *Next = MO->Contents.Reg.Next;
324 105605126 : MachineOperand *Prev = MO->Contents.Reg.Prev;
325 :
326 : // Prev links are circular, next link is NULL instead of looping back to Head.
327 105605126 : if (MO == Head)
328 53877299 : HeadRef = Next;
329 : else
330 51727827 : Prev->Contents.Reg.Next = Next;
331 :
332 105605126 : (Next ? Next : Head)->Contents.Reg.Prev = Prev;
333 :
334 105605126 : MO->Contents.Reg.Prev = nullptr;
335 105605126 : MO->Contents.Reg.Next = nullptr;
336 105605126 : }
337 :
338 : /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
339 : ///
340 : /// The Dst range is assumed to be uninitialized memory. (Or it may contain
341 : /// operands that won't be destroyed, which is OK because the MO destructor is
342 : /// trivial anyway).
343 : ///
344 : /// The Src and Dst ranges may overlap.
345 20018878 : void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
346 : MachineOperand *Src,
347 : unsigned NumOps) {
348 : assert(Src != Dst && NumOps && "Noop moveOperands");
349 :
350 : // Copy backwards if Dst is within the Src range.
351 : int Stride = 1;
352 20018878 : if (Dst >= Src && Dst < Src + NumOps) {
353 : Stride = -1;
354 8848569 : Dst += NumOps - 1;
355 8848569 : Src += NumOps - 1;
356 : }
357 :
358 : // Copy one operand at a time.
359 : do {
360 55766828 : new (Dst) MachineOperand(*Src);
361 :
362 : // Dst takes Src's place in the use-def chain.
363 55766828 : if (Src->isReg()) {
364 51973725 : MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
365 51973725 : MachineOperand *Prev = Src->Contents.Reg.Prev;
366 51973725 : MachineOperand *Next = Src->Contents.Reg.Next;
367 : assert(Head && "List empty, but operand is chained");
368 : assert(Prev && "Operand was not on use-def list");
369 :
370 : // Prev links are circular, next link is NULL instead of looping back to
371 : // Head.
372 51973725 : if (Src == Head)
373 26672647 : Head = Dst;
374 : else
375 25301078 : Prev->Contents.Reg.Next = Dst;
376 :
377 : // Update Prev pointer. This also works when Src was pointing to itself
378 : // in a 1-element list. In that case Head == Dst.
379 51973725 : (Next ? Next : Head)->Contents.Reg.Prev = Dst;
380 : }
381 :
382 55766828 : Dst += Stride;
383 55766828 : Src += Stride;
384 55766828 : } while (--NumOps);
385 20018878 : }
386 :
387 : /// replaceRegWith - Replace all instances of FromReg with ToReg in the
388 : /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
389 : /// except that it also changes any definitions of the register as well.
390 : /// If ToReg is a physical register we apply the sub register to obtain the
391 : /// final/proper physical register.
392 8428587 : void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
393 : assert(FromReg != ToReg && "Cannot replace a reg with itself");
394 :
395 8428587 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
396 :
397 : // TODO: This could be more efficient by bulk changing the operands.
398 16725449 : for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
399 : MachineOperand &O = *I;
400 : ++I;
401 8296862 : if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
402 28413 : O.substPhysReg(ToReg, *TRI);
403 : } else {
404 8268449 : O.setReg(ToReg);
405 : }
406 : }
407 8428587 : }
408 :
409 : /// getVRegDef - Return the machine instr that defines the specified virtual
410 : /// register or null if none is found. This assumes that the code is in SSA
411 : /// form, so there should only be one definition.
412 9942603 : MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
413 : // Since we are in SSA form, we can use the first definition.
414 9942603 : def_instr_iterator I = def_instr_begin(Reg);
415 : assert((I.atEnd() || std::next(I) == def_instr_end()) &&
416 : "getVRegDef assumes a single definition or no definition");
417 9942603 : return !I.atEnd() ? &*I : nullptr;
418 : }
419 :
420 : /// getUniqueVRegDef - Return the unique machine instr that defines the
421 : /// specified virtual register or null if none is found. If there are
422 : /// multiple definitions or no definition, return null.
423 508702 : MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
424 508702 : if (def_empty(Reg)) return nullptr;
425 507583 : def_instr_iterator I = def_instr_begin(Reg);
426 507583 : if (std::next(I) != def_instr_end())
427 : return nullptr;
428 1006700 : return &*I;
429 : }
430 :
431 17434047 : bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
432 17434047 : use_nodbg_iterator UI = use_nodbg_begin(RegNo);
433 17434046 : if (UI == use_nodbg_end())
434 : return false;
435 : return ++UI == use_nodbg_end();
436 : }
437 :
438 : /// clearKillFlags - Iterate over all the uses of the given register and
439 : /// clear the kill flag from the MachineOperand. This function is used by
440 : /// optimization passes which extend register lifetimes and need only
441 : /// preserve conservative kill flag information.
442 2830077 : void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
443 11285455 : for (MachineOperand &MO : use_operands(Reg))
444 : MO.setIsKill(false);
445 2830077 : }
446 :
447 505651 : bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
448 1580754 : for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
449 1201991 : if (I->first == Reg || I->second == Reg)
450 : return true;
451 : return false;
452 : }
453 :
454 : /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
455 : /// corresponding live-in physical register.
456 23318 : unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
457 47580 : for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
458 46803 : if (I->second == VReg)
459 22541 : return I->first;
460 : return 0;
461 : }
462 :
463 : /// getLiveInVirtReg - If PReg is a live-in physical register, return the
464 : /// corresponding live-in physical register.
465 734925 : unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
466 1560025 : for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
467 883755 : if (I->first == PReg)
468 58655 : return I->second;
469 : return 0;
470 : }
471 :
472 : /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
473 : /// into the given entry block.
474 : void
475 405211 : MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
476 : const TargetRegisterInfo &TRI,
477 : const TargetInstrInfo &TII) {
478 : // Emit the copies into the top of the block.
479 1534311 : for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
480 1447776 : if (LiveIns[i].second) {
481 720904 : if (use_nodbg_empty(LiveIns[i].second)) {
482 : // The livein has no non-dbg uses. Drop it.
483 : //
484 : // It would be preferable to have isel avoid creating live-in
485 : // records for unused arguments in the first place, but it's
486 : // complicated by the debug info code for arguments.
487 : LiveIns.erase(LiveIns.begin() + i);
488 69841 : --i; --e;
489 : } else {
490 : // Emit a copy.
491 1302126 : BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
492 1953189 : TII.get(TargetOpcode::COPY), LiveIns[i].second)
493 1302126 : .addReg(LiveIns[i].first);
494 :
495 : // Add the register to the entry block live-in set.
496 1302126 : EntryMBB->addLiveIn(LiveIns[i].first);
497 : }
498 : } else {
499 : // Add the register to the entry block live-in set.
500 2984 : EntryMBB->addLiveIn(LiveIns[i].first);
501 : }
502 405212 : }
503 :
504 12740625 : LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
505 : // Lane masks are only defined for vregs.
506 : assert(TargetRegisterInfo::isVirtualRegister(Reg));
507 : const TargetRegisterClass &TRC = *getRegClass(Reg);
508 12740625 : return TRC.getLaneMask();
509 : }
510 :
511 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
512 : LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const {
513 : for (MachineInstr &I : use_instructions(Reg))
514 : I.dump();
515 : }
516 : #endif
517 :
518 812989 : void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
519 812989 : ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
520 : assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
521 : "Invalid ReservedRegs vector from target");
522 812989 : }
523 :
524 6978572 : bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
525 : assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
526 :
527 6978572 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
528 6978572 : if (TRI->isConstantPhysReg(PhysReg))
529 : return true;
530 :
531 : // Check if any overlapping register is modified, or allocatable so it may be
532 : // used later.
533 14684561 : for (MCRegAliasIterator AI(PhysReg, TRI, true);
534 22399142 : AI.isValid(); ++AI)
535 13608170 : if (!def_empty(*AI) || isAllocatable(*AI))
536 5893589 : return false;
537 1076391 : return true;
538 : }
539 :
540 : bool
541 383002 : MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const {
542 383002 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
543 755416 : return isConstantPhysReg(PhysReg) ||
544 372414 : TRI->isCallerPreservedPhysReg(PhysReg, *MF);
545 : }
546 :
547 : /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
548 : /// specified register as undefined which causes the DBG_VALUE to be
549 : /// deleted during LiveDebugVariables analysis.
550 257609 : void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
551 : // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
552 : MachineRegisterInfo::use_instr_iterator nextI;
553 257609 : for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
554 265898 : I != E; I = nextI) {
555 8289 : nextI = std::next(I); // I is invalidated by the setReg
556 : MachineInstr *UseMI = &*I;
557 8289 : if (UseMI->isDebugValue())
558 86 : UseMI->getOperand(0).setReg(0U);
559 : }
560 257609 : }
561 :
562 : static const Function *getCalledFunction(const MachineInstr &MI) {
563 37424 : for (const MachineOperand &MO : MI.operands()) {
564 33901 : if (!MO.isGlobal())
565 : continue;
566 2707 : const Function *Func = dyn_cast<Function>(MO.getGlobal());
567 : if (Func != nullptr)
568 : return Func;
569 : }
570 : return nullptr;
571 : }
572 :
573 75160 : static bool isNoReturnDef(const MachineOperand &MO) {
574 : // Anything which is not a noreturn function is a real def.
575 75160 : const MachineInstr &MI = *MO.getParent();
576 75160 : if (!MI.isCall())
577 : return false;
578 7041 : const MachineBasicBlock &MBB = *MI.getParent();
579 7041 : if (!MBB.succ_empty())
580 : return false;
581 6251 : const MachineFunction &MF = *MBB.getParent();
582 : // We need to keep correct unwind information even if the function will
583 : // not return, since the runtime may need it.
584 6251 : if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
585 : return false;
586 : const Function *Called = getCalledFunction(MI);
587 8911 : return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
588 : !Called->hasFnAttribute(Attribute::NoUnwind));
589 : }
590 :
591 4351365 : bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
592 : bool SkipNoReturnDef) const {
593 4351365 : if (UsedPhysRegMask.test(PhysReg))
594 : return true;
595 4348393 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
596 65830052 : for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
597 123113609 : for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
598 75156 : if (!SkipNoReturnDef && isNoReturnDef(MO))
599 : continue;
600 : return true;
601 : }
602 : }
603 4273256 : return false;
604 : }
605 :
606 7819852 : bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
607 7819852 : if (UsedPhysRegMask.test(PhysReg))
608 : return true;
609 7787847 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
610 192892224 : for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
611 185104375 : ++AliasReg) {
612 185240041 : if (!reg_nodbg_empty(*AliasReg))
613 135666 : return true;
614 : }
615 7652183 : return false;
616 : }
617 :
618 579 : void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
619 :
620 579 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
621 : assert(Reg && (Reg < TRI->getNumRegs()) &&
622 : "Trying to disable an invalid register");
623 :
624 579 : if (!IsUpdatedCSRsInitialized) {
625 132 : const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
626 1984 : for (const MCPhysReg *I = CSR; *I; ++I)
627 1852 : UpdatedCSRs.push_back(*I);
628 :
629 : // Zero value represents the end of the register list
630 : // (no more registers should be pushed).
631 132 : UpdatedCSRs.push_back(0);
632 :
633 132 : IsUpdatedCSRsInitialized = true;
634 : }
635 :
636 : // Remove the register (and its aliases from the list).
637 4475 : for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
638 7792 : UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
639 : UpdatedCSRs.end());
640 579 : }
641 :
642 3639596 : const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
643 3639596 : if (IsUpdatedCSRsInitialized)
644 1502 : return UpdatedCSRs.data();
645 :
646 3638094 : return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
647 : }
648 :
649 42 : void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
650 42 : if (IsUpdatedCSRsInitialized)
651 : UpdatedCSRs.clear();
652 :
653 1361 : for (MCPhysReg Reg : CSRs)
654 1319 : UpdatedCSRs.push_back(Reg);
655 :
656 : // Zero value represents the end of the register list
657 : // (no more registers should be pushed).
658 42 : UpdatedCSRs.push_back(0);
659 42 : IsUpdatedCSRsInitialized = true;
660 42 : }
661 :
662 1043138 : bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
663 1043138 : const TargetRegisterInfo *TRI = getTargetRegisterInfo();
664 2946730 : for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
665 : bool IsRootReserved = true;
666 : for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
667 1419234 : Super.isValid(); ++Super) {
668 : unsigned Reg = *Super;
669 1234658 : if (!isReserved(Reg)) {
670 : IsRootReserved = false;
671 : break;
672 : }
673 : }
674 1045030 : if (IsRootReserved)
675 : return true;
676 : }
677 858562 : return false;
678 : }
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