Line data Source code
1 : //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This implements the Emit routines for the SelectionDAG class, which creates
11 : // MachineInstrs based on the decisions of the SelectionDAG instruction
12 : // selection.
13 : //
14 : //===----------------------------------------------------------------------===//
15 :
16 : #include "InstrEmitter.h"
17 : #include "SDNodeDbgValue.h"
18 : #include "llvm/ADT/Statistic.h"
19 : #include "llvm/CodeGen/MachineConstantPool.h"
20 : #include "llvm/CodeGen/MachineFunction.h"
21 : #include "llvm/CodeGen/MachineInstrBuilder.h"
22 : #include "llvm/CodeGen/MachineRegisterInfo.h"
23 : #include "llvm/CodeGen/StackMaps.h"
24 : #include "llvm/CodeGen/TargetInstrInfo.h"
25 : #include "llvm/CodeGen/TargetLowering.h"
26 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 : #include "llvm/IR/DataLayout.h"
28 : #include "llvm/IR/DebugInfo.h"
29 : #include "llvm/Support/Debug.h"
30 : #include "llvm/Support/ErrorHandling.h"
31 : #include "llvm/Support/MathExtras.h"
32 : using namespace llvm;
33 :
34 : #define DEBUG_TYPE "instr-emitter"
35 :
36 : /// MinRCSize - Smallest register class we allow when constraining virtual
37 : /// registers. If satisfying all register class constraints would require
38 : /// using a smaller register class, emit a COPY to a new virtual register
39 : /// instead.
40 : const unsigned MinRCSize = 4;
41 :
42 : /// CountResults - The results of target nodes have register or immediate
43 : /// operands first, then an optional chain, and optional glue operands (which do
44 : /// not go into the resulting MachineInstr).
45 21387345 : unsigned InstrEmitter::CountResults(SDNode *Node) {
46 21387345 : unsigned N = Node->getNumValues();
47 28614134 : while (N && Node->getValueType(N - 1) == MVT::Glue)
48 : --N;
49 21387345 : if (N && Node->getValueType(N - 1) == MVT::Other)
50 : --N; // Skip over chain result.
51 21387345 : return N;
52 : }
53 :
54 : /// countOperands - The inputs to target nodes have any actual inputs first,
55 : /// followed by an optional chain operand, then an optional glue operand.
56 : /// Compute the number of actual operands that will go into the resulting
57 : /// MachineInstr.
58 : ///
59 : /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60 : /// the chain and glue. These operands may be implicit on the machine instr.
61 11388661 : static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62 : unsigned &NumImpUses) {
63 11388661 : unsigned N = Node->getNumOperands();
64 13828355 : while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
65 : --N;
66 11388661 : if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
67 : --N; // Ignore chain if it exists.
68 :
69 : // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
70 11388661 : NumImpUses = N - NumExpUses;
71 14621135 : for (unsigned I = N; I > NumExpUses; --I) {
72 6473200 : if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
73 : continue;
74 : if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
75 4463760 : if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
76 : continue;
77 4126 : NumImpUses = N - I;
78 4126 : break;
79 : }
80 :
81 11388661 : return N;
82 : }
83 :
84 : /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
85 : /// implicit physical register output.
86 2240797 : void InstrEmitter::
87 : EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
88 : unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 : unsigned VRBase = 0;
90 2240797 : if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
91 : // Just use the input register directly!
92 : SDValue Op(Node, ResNo);
93 1491612 : if (IsClone)
94 0 : VRBaseMap.erase(Op);
95 1491612 : bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
96 : (void)isNew; // Silence compiler warning.
97 : assert(isNew && "Node emitted out of order - early");
98 : return;
99 : }
100 :
101 : // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102 : // the CopyToReg'd destination register instead of creating a new vreg.
103 : bool MatchReg = true;
104 : const TargetRegisterClass *UseRC = nullptr;
105 : MVT VT = Node->getSimpleValueType(ResNo);
106 :
107 : // Stick to the preferred register classes for legal types.
108 749185 : if (TLI->isTypeLegal(VT))
109 749185 : UseRC = TLI->getRegClassFor(VT);
110 :
111 749185 : if (!IsClone && !IsCloned)
112 1762586 : for (SDNode *User : Node->uses()) {
113 : bool Match = true;
114 1754050 : if (User->getOpcode() == ISD::CopyToReg &&
115 1193880 : User->getOperand(2).getNode() == Node &&
116 557284 : User->getOperand(2).getResNo() == ResNo) {
117 555245 : unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 555245 : if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
119 : VRBase = DestReg;
120 : Match = false;
121 375251 : } else if (DestReg != SrcReg)
122 : Match = false;
123 : } else {
124 3777007 : for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125 3138372 : SDValue Op = User->getOperand(i);
126 3138372 : if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 : continue;
128 : MVT VT = Node->getSimpleValueType(Op.getResNo());
129 315730 : if (VT == MVT::Other || VT == MVT::Glue)
130 : continue;
131 : Match = false;
132 315730 : if (User->isMachineOpcode()) {
133 631448 : const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134 : const TargetRegisterClass *RC = nullptr;
135 947172 : if (i+II.getNumDefs() < II.getNumOperands()) {
136 315385 : RC = TRI->getAllocatableClass(
137 315385 : TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
138 : }
139 315724 : if (!UseRC)
140 : UseRC = RC;
141 315724 : else if (RC) {
142 : const TargetRegisterClass *ComRC =
143 313880 : TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
144 : // If multiple uses expect disjoint register classes, we emit
145 : // copies in AddRegisterOperand.
146 313880 : if (ComRC)
147 : UseRC = ComRC;
148 : }
149 : }
150 : }
151 : }
152 : MatchReg &= Match;
153 1193880 : if (VRBase)
154 : break;
155 : }
156 :
157 : const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
158 749185 : SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 :
160 : // Figure out the register class to create for the destreg.
161 749185 : if (VRBase) {
162 179994 : DstRC = MRI->getRegClass(VRBase);
163 569191 : } else if (UseRC) {
164 : assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
165 : "Incompatible phys register def and uses!");
166 : DstRC = UseRC;
167 : } else {
168 0 : DstRC = TLI->getRegClassFor(VT);
169 : }
170 :
171 : // If all uses are reading from the src physical register and copying the
172 : // register is either impossible or very expensive, then don't create a copy.
173 749185 : if (MatchReg && SrcRC->getCopyCost() < 0) {
174 : VRBase = SrcReg;
175 : } else {
176 : // Create the reg, emit the copy.
177 1049844 : VRBase = MRI->createVirtualRegister(DstRC);
178 524922 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
179 1049844 : VRBase).addReg(SrcReg);
180 : }
181 :
182 : SDValue Op(Node, ResNo);
183 749185 : if (IsClone)
184 275 : VRBaseMap.erase(Op);
185 749185 : bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
186 : (void)isNew; // Silence compiler warning.
187 : assert(isNew && "Node emitted out of order - early");
188 : }
189 :
190 : /// getDstOfCopyToRegUse - If the only use of the specified result number of
191 : /// node is a CopyToReg, return its destination register. Return 0 otherwise.
192 44727 : unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
193 : unsigned ResNo) const {
194 : if (!Node->hasOneUse())
195 : return 0;
196 :
197 : SDNode *User = *Node->use_begin();
198 21737 : if (User->getOpcode() == ISD::CopyToReg &&
199 20467 : User->getOperand(2).getNode() == Node &&
200 1270 : User->getOperand(2).getResNo() == ResNo) {
201 1270 : unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
202 1270 : if (TargetRegisterInfo::isVirtualRegister(Reg))
203 603 : return Reg;
204 : }
205 : return 0;
206 : }
207 :
208 7087697 : void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
209 : MachineInstrBuilder &MIB,
210 : const MCInstrDesc &II,
211 : bool IsClone, bool IsCloned,
212 : DenseMap<SDValue, unsigned> &VRBaseMap) {
213 : assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
214 : "IMPLICIT_DEF should have been handled as a special case elsewhere!");
215 :
216 7087697 : unsigned NumResults = CountResults(Node);
217 18859646 : for (unsigned i = 0; i < II.getNumDefs(); ++i) {
218 : // If the specific node value is only used by a CopyToReg and the dest reg
219 : // is a vreg in the same register class, use the CopyToReg'd destination
220 : // register instead of creating a new vreg.
221 : unsigned VRBase = 0;
222 : const TargetRegisterClass *RC =
223 4684252 : TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
224 : // Always let the value type influence the used register class. The
225 : // constraints on the instruction may be too lax to represent the value
226 : // type correctly. For example, a 64-bit float (X86::FR64) can't live in
227 : // the 32-bit float super-class (X86::FR32).
228 4684252 : if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
229 : const TargetRegisterClass *VTRC =
230 4676731 : TLI->getRegClassFor(Node->getSimpleValueType(i));
231 4676731 : if (RC)
232 4670394 : VTRC = TRI->getCommonSubClass(RC, VTRC);
233 4676731 : if (VTRC)
234 : RC = VTRC;
235 : }
236 :
237 4684252 : if (II.OpInfo[i].isOptionalDef()) {
238 : // Optional def must be a physical register.
239 2757 : VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
240 : assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
241 2757 : MIB.addReg(VRBase, RegState::Define);
242 : }
243 :
244 4684252 : if (!VRBase && !IsClone && !IsCloned)
245 12411525 : for (SDNode *User : Node->uses()) {
246 10246887 : if (User->getOpcode() == ISD::CopyToReg &&
247 8050167 : User->getOperand(2).getNode() == Node &&
248 2194642 : User->getOperand(2).getResNo() == i) {
249 2125434 : unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
250 2125434 : if (TargetRegisterInfo::isVirtualRegister(Reg)) {
251 324021 : const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252 324021 : if (RegRC == RC) {
253 : VRBase = Reg;
254 319895 : MIB.addReg(VRBase, RegState::Define);
255 319895 : break;
256 : }
257 : }
258 : }
259 : }
260 :
261 : // Create the result registers for this node and add the result regs to
262 : // the machine instruction.
263 4684252 : if (VRBase == 0) {
264 : assert(RC && "Isn't a register operand!");
265 8723200 : VRBase = MRI->createVirtualRegister(RC);
266 4361600 : MIB.addReg(VRBase, RegState::Define);
267 : }
268 :
269 : // If this def corresponds to a result of the SDNode insert the VRBase into
270 : // the lookup map.
271 4684252 : if (i < NumResults) {
272 : SDValue Op(Node, i);
273 4681495 : if (IsClone)
274 126 : VRBaseMap.erase(Op);
275 4681495 : bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
276 : (void)isNew; // Silence compiler warning.
277 : assert(isNew && "Node emitted out of order - early");
278 : }
279 : }
280 7087697 : }
281 :
282 : /// getVR - Return the virtual register corresponding to the specified result
283 : /// of the specified node.
284 9269624 : unsigned InstrEmitter::getVR(SDValue Op,
285 : DenseMap<SDValue, unsigned> &VRBaseMap) {
286 18539248 : if (Op.isMachineOpcode() &&
287 : Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
288 : // Add an IMPLICIT_DEF instruction before every use.
289 44727 : unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
290 : // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
291 : // does not include operand register class info.
292 44727 : if (!VReg) {
293 : const TargetRegisterClass *RC =
294 88248 : TLI->getRegClassFor(Op.getSimpleValueType());
295 88248 : VReg = MRI->createVirtualRegister(RC);
296 : }
297 44727 : BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
298 134181 : TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
299 44727 : return VReg;
300 : }
301 :
302 9224897 : DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
303 : assert(I != VRBaseMap.end() && "Node emitted out of order - late");
304 9224897 : return I->second;
305 : }
306 :
307 :
308 : /// AddRegisterOperand - Add the specified register as an operand to the
309 : /// specified machine instr. Insert register copies if the register is
310 : /// not in the required register class.
311 : void
312 4941202 : InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
313 : SDValue Op,
314 : unsigned IIOpNum,
315 : const MCInstrDesc *II,
316 : DenseMap<SDValue, unsigned> &VRBaseMap,
317 : bool IsDebug, bool IsClone, bool IsCloned) {
318 : assert(Op.getValueType() != MVT::Other &&
319 : Op.getValueType() != MVT::Glue &&
320 : "Chain and glue operands should occur at end of operand list!");
321 : // Get/emit the operand.
322 4941202 : unsigned VReg = getVR(Op, VRBaseMap);
323 :
324 4941202 : const MCInstrDesc &MCID = MIB->getDesc();
325 9882404 : bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326 4725945 : MCID.OpInfo[IIOpNum].isOptionalDef();
327 :
328 : // If the instruction requires a register in a different class, create
329 : // a new virtual register and copy the value into it, but first attempt to
330 : // shrink VReg's register class within reason. For example, if VReg == GR32
331 : // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
332 4941202 : if (II) {
333 : const TargetRegisterClass *OpRC = nullptr;
334 9563352 : if (IIOpNum < II->getNumOperands())
335 4569362 : OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
336 :
337 4569362 : if (OpRC) {
338 : const TargetRegisterClass *ConstrainedRC
339 4562876 : = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
340 4562876 : if (!ConstrainedRC) {
341 60980 : OpRC = TRI->getAllocatableClass(OpRC);
342 : assert(OpRC && "Constraints cannot be fulfilled for allocation");
343 121960 : unsigned NewVReg = MRI->createVirtualRegister(OpRC);
344 60980 : BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
345 121960 : TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
346 : VReg = NewVReg;
347 : } else {
348 : assert(ConstrainedRC->isAllocatable() &&
349 : "Constraining an allocatable VReg produced an unallocatable class?");
350 : }
351 : }
352 : }
353 :
354 : // If this value has only one use, that use is a kill. This is a
355 : // conservative approximation. InstrEmitter does trivial coalescing
356 : // with CopyFromReg nodes, so don't emit kill flags for them.
357 : // Avoid kill flags on Schedule cloned nodes, since there will be
358 : // multiple uses.
359 : // Tied operands are never killed, so we need to check that. And that
360 : // means we need to determine the index of the operand.
361 4941202 : bool isKill = Op.hasOneUse() &&
362 3159070 : Op.getNode()->getOpcode() != ISD::CopyFromReg &&
363 7393542 : !IsDebug &&
364 : !(IsClone || IsCloned);
365 : if (isKill) {
366 2452192 : unsigned Idx = MIB->getNumOperands();
367 2834093 : while (Idx > 0 &&
368 2947898 : MIB->getOperand(Idx-1).isReg() &&
369 : MIB->getOperand(Idx-1).isImplicit())
370 : --Idx;
371 2452192 : bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
372 : if (isTied)
373 : isKill = false;
374 : }
375 :
376 4941202 : MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
377 4941202 : getDebugRegState(IsDebug));
378 4941202 : }
379 :
380 : /// AddOperand - Add the specified operand to the specified machine instr. II
381 : /// specifies the instruction information for the node, and IIOpNum is the
382 : /// operand number (in the II) that we are adding.
383 45130753 : void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
384 : SDValue Op,
385 : unsigned IIOpNum,
386 : const MCInstrDesc *II,
387 : DenseMap<SDValue, unsigned> &VRBaseMap,
388 : bool IsDebug, bool IsClone, bool IsCloned) {
389 45130753 : if (Op.isMachineOpcode()) {
390 3827409 : AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
391 : IsDebug, IsClone, IsCloned);
392 : } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
393 18217967 : MIB.addImm(C->getSExtValue());
394 : } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
395 247 : MIB.addFPImm(F->getConstantFPValue());
396 : } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
397 14245938 : unsigned VReg = R->getReg();
398 : MVT OpVT = Op.getSimpleValueType();
399 : const TargetRegisterClass *OpRC =
400 28491781 : TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr;
401 : const TargetRegisterClass *IIRC =
402 14245938 : II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
403 : : nullptr;
404 :
405 14245937 : if (OpRC && IIRC && OpRC != IIRC &&
406 : TargetRegisterInfo::isVirtualRegister(VReg)) {
407 2786 : unsigned NewVReg = MRI->createVirtualRegister(IIRC);
408 1393 : BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
409 2786 : TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
410 : VReg = NewVReg;
411 : }
412 : // Turn additional physreg operands into implicit uses on non-variadic
413 : // instructions. This is used by call and return instructions passing
414 : // arguments in registers.
415 14245937 : bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
416 14245937 : MIB.addReg(VReg, getImplRegState(Imp));
417 : } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
418 1003370 : MIB.addRegMask(RM->getRegMask());
419 : } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
420 : MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
421 1909758 : TGA->getTargetFlags());
422 : } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
423 725957 : MIB.addMBB(BBNode->getBasicBlock());
424 : } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
425 4031241 : MIB.addFrameIndex(FI->getIndex());
426 : } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
427 3307 : MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
428 : } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
429 34257 : int Offset = CP->getOffset();
430 34257 : unsigned Align = CP->getAlignment();
431 34257 : Type *Type = CP->getType();
432 : // MachineConstantPool wants an explicit alignment.
433 34257 : if (Align == 0) {
434 0 : Align = MF->getDataLayout().getPrefTypeAlignment(Type);
435 0 : if (Align == 0) {
436 : // Alignment of vector types. FIXME!
437 0 : Align = MF->getDataLayout().getTypeAllocSize(Type);
438 : }
439 : }
440 :
441 : unsigned Idx;
442 34257 : MachineConstantPool *MCP = MF->getConstantPool();
443 34257 : if (CP->isMachineConstantPoolEntry())
444 252 : Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
445 : else
446 34005 : Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
447 34257 : MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
448 : } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
449 17135 : MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
450 : } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
451 61 : MIB.addSym(SymNode->getMCSymbol());
452 : } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
453 : MIB.addBlockAddress(BA->getBlockAddress(),
454 : BA->getOffset(),
455 313 : BA->getTargetFlags());
456 : } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
457 0 : MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
458 : } else {
459 : assert(Op.getValueType() != MVT::Other &&
460 : Op.getValueType() != MVT::Glue &&
461 : "Chain and glue operands should occur at end of operand list!");
462 1113793 : AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
463 : IsDebug, IsClone, IsCloned);
464 : }
465 45130753 : }
466 :
467 492276 : unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
468 : MVT VT, const DebugLoc &DL) {
469 492276 : const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
470 492276 : const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
471 :
472 : // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
473 : // within reason.
474 492276 : if (RC && RC != VRC)
475 3217 : RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
476 :
477 : // VReg has been adjusted. It can be used with SubIdx operands now.
478 492276 : if (RC)
479 : return VReg;
480 :
481 : // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
482 : // register instead.
483 8 : RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
484 : assert(RC && "No legal register class for VT supports that SubIdx");
485 16 : unsigned NewReg = MRI->createVirtualRegister(RC);
486 16 : BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
487 8 : .addReg(VReg);
488 8 : return NewReg;
489 : }
490 :
491 : /// EmitSubregNode - Generate machine code for subreg nodes.
492 : ///
493 621614 : void InstrEmitter::EmitSubregNode(SDNode *Node,
494 : DenseMap<SDValue, unsigned> &VRBaseMap,
495 : bool IsClone, bool IsCloned) {
496 : unsigned VRBase = 0;
497 621614 : unsigned Opc = Node->getMachineOpcode();
498 :
499 : // If the node is only used by a CopyToReg and the dest reg is a vreg, use
500 : // the CopyToReg'd destination register instead of creating a new vreg.
501 983648 : for (SDNode *User : Node->uses()) {
502 672377 : if (User->getOpcode() == ISD::CopyToReg &&
503 433017 : User->getOperand(2).getNode() == Node) {
504 433012 : unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
505 433012 : if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
506 : VRBase = DestReg;
507 : break;
508 : }
509 : }
510 : }
511 :
512 621614 : if (Opc == TargetOpcode::EXTRACT_SUBREG) {
513 : // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
514 : // constraints on the %dst register, COPY can target all legal register
515 : // classes.
516 984600 : unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
517 : const TargetRegisterClass *TRC =
518 984600 : TLI->getRegClassFor(Node->getSimpleValueType(0));
519 :
520 : unsigned Reg;
521 : MachineInstr *DefMI;
522 492300 : RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
523 2 : if (R && TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
524 : Reg = R->getReg();
525 : DefMI = nullptr;
526 : } else {
527 492300 : Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
528 492300 : DefMI = MRI->getVRegDef(Reg);
529 : }
530 :
531 : unsigned SrcReg, DstReg, DefSubIdx;
532 464236 : if (DefMI &&
533 464236 : TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
534 492379 : SubIdx == DefSubIdx &&
535 24 : TRC == MRI->getRegClass(SrcReg)) {
536 : // Optimize these:
537 : // r1025 = s/zext r1024, 4
538 : // r1026 = extract_subreg r1025, 4
539 : // to a copy
540 : // r1026 = copy r1024
541 24 : VRBase = MRI->createVirtualRegister(TRC);
542 48 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543 48 : TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
544 24 : MRI->clearKillFlags(SrcReg);
545 : } else {
546 : // Reg may not support a SubIdx sub-register, and we may need to
547 : // constrain its register class or issue a COPY to a compatible register
548 : // class.
549 492276 : if (TargetRegisterInfo::isVirtualRegister(Reg))
550 492276 : Reg = ConstrainForSubReg(Reg, SubIdx,
551 492276 : Node->getOperand(0).getSimpleValueType(),
552 : Node->getDebugLoc());
553 :
554 : // Create the destreg if it is missing.
555 492276 : if (VRBase == 0)
556 378800 : VRBase = MRI->createVirtualRegister(TRC);
557 :
558 : // Create the extract_subreg machine instruction.
559 : MachineInstrBuilder CopyMI =
560 492276 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
561 984552 : TII->get(TargetOpcode::COPY), VRBase);
562 492276 : if (TargetRegisterInfo::isVirtualRegister(Reg))
563 492276 : CopyMI.addReg(Reg, 0, SubIdx);
564 : else
565 0 : CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
566 : }
567 258628 : } else if (Opc == TargetOpcode::INSERT_SUBREG ||
568 129314 : Opc == TargetOpcode::SUBREG_TO_REG) {
569 129314 : SDValue N0 = Node->getOperand(0);
570 129314 : SDValue N1 = Node->getOperand(1);
571 129314 : SDValue N2 = Node->getOperand(2);
572 129314 : unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
573 :
574 : // Figure out the register class to create for the destreg. It should be
575 : // the largest legal register class supporting SubIdx sub-registers.
576 : // RegisterCoalescer will constrain it further if it decides to eliminate
577 : // the INSERT_SUBREG instruction.
578 : //
579 : // %dst = INSERT_SUBREG %src, %sub, SubIdx
580 : //
581 : // is lowered by TwoAddressInstructionPass to:
582 : //
583 : // %dst = COPY %src
584 : // %dst:SubIdx = COPY %sub
585 : //
586 : // There is no constraint on the %src register class.
587 : //
588 258628 : const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
589 129314 : SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
590 : assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
591 :
592 129314 : if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
593 243704 : VRBase = MRI->createVirtualRegister(SRC);
594 :
595 : // Create the insert_subreg or subreg_to_reg machine instruction.
596 : MachineInstrBuilder MIB =
597 258628 : BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
598 :
599 : // If creating a subreg_to_reg, then the first input operand
600 : // is an implicit value immediate, otherwise it's a register
601 129314 : if (Opc == TargetOpcode::SUBREG_TO_REG) {
602 : const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
603 204090 : MIB.addImm(SD->getZExtValue());
604 : } else
605 27269 : AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
606 : IsClone, IsCloned);
607 : // Add the subregister being inserted
608 129314 : AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
609 : IsClone, IsCloned);
610 129314 : MIB.addImm(SubIdx);
611 129314 : MBB->insert(InsertPos, MIB);
612 : } else
613 0 : llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
614 :
615 : SDValue Op(Node, 0);
616 621614 : bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
617 : (void)isNew; // Silence compiler warning.
618 : assert(isNew && "Node emitted out of order - early");
619 621614 : }
620 :
621 : /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
622 : /// COPY_TO_REGCLASS is just a normal copy, except that the destination
623 : /// register is constrained to be in a particular register class.
624 : ///
625 : void
626 47469 : InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
627 : DenseMap<SDValue, unsigned> &VRBaseMap) {
628 94938 : unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
629 :
630 : // Create the new VReg in the destination class and emit a copy.
631 94938 : unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
632 : const TargetRegisterClass *DstRC =
633 94938 : TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
634 94938 : unsigned NewVReg = MRI->createVirtualRegister(DstRC);
635 47469 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
636 94938 : NewVReg).addReg(VReg);
637 :
638 : SDValue Op(Node, 0);
639 47469 : bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
640 : (void)isNew; // Silence compiler warning.
641 : assert(isNew && "Node emitted out of order - early");
642 47469 : }
643 :
644 : /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
645 : ///
646 63467 : void InstrEmitter::EmitRegSequence(SDNode *Node,
647 : DenseMap<SDValue, unsigned> &VRBaseMap,
648 : bool IsClone, bool IsCloned) {
649 126934 : unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
650 63467 : const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
651 126934 : unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
652 63467 : const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
653 63467 : MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
654 63467 : unsigned NumOps = Node->getNumOperands();
655 : assert((NumOps & 1) == 1 &&
656 : "REG_SEQUENCE must have an odd number of operands!");
657 415161 : for (unsigned i = 1; i != NumOps; ++i) {
658 351694 : SDValue Op = Node->getOperand(i);
659 351694 : if ((i & 1) == 0) {
660 175847 : RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
661 : // Skip physical registers as they don't have a vreg to get and we'll
662 : // insert copies for them in TwoAddressInstructionPass anyway.
663 2646 : if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
664 349048 : unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
665 174524 : unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
666 174524 : const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
667 : const TargetRegisterClass *SRC =
668 174524 : TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
669 174524 : if (SRC && SRC != RC) {
670 3925 : MRI->setRegClass(NewVReg, SRC);
671 : RC = SRC;
672 : }
673 : }
674 : }
675 351694 : AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
676 : IsClone, IsCloned);
677 : }
678 :
679 63467 : MBB->insert(InsertPos, MIB);
680 : SDValue Op(Node, 0);
681 63467 : bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
682 : (void)isNew; // Silence compiler warning.
683 : assert(isNew && "Node emitted out of order - early");
684 63467 : }
685 :
686 : /// EmitDbgValue - Generate machine instruction for a dbg_value node.
687 : ///
688 : MachineInstr *
689 76232 : InstrEmitter::EmitDbgValue(SDDbgValue *SD,
690 : DenseMap<SDValue, unsigned> &VRBaseMap) {
691 76232 : MDNode *Var = SD->getVariable();
692 76232 : MDNode *Expr = SD->getExpression();
693 : DebugLoc DL = SD->getDebugLoc();
694 : assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
695 : "Expected inlined-at fields to agree");
696 :
697 76232 : if (SD->getKind() == SDDbgValue::FRAMEIX) {
698 : // Stack address; this needs to be lowered in target-dependent fashion.
699 : // EmitTargetCodeForFrameDebugValue is responsible for allocation.
700 8958 : auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
701 4479 : .addFrameIndex(SD->getFrameIx());
702 4479 : if (SD->isIndirect())
703 : // Push [fi + 0] onto the DIExpression stack.
704 : FrameMI.addImm(0);
705 : else
706 : // Push fi onto the DIExpression stack.
707 4474 : FrameMI.addReg(0);
708 4479 : return FrameMI.addMetadata(Var).addMetadata(Expr);
709 : }
710 : // Otherwise, we're going to create an instruction here.
711 71753 : const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
712 71753 : MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
713 71753 : if (SD->getKind() == SDDbgValue::SDNODE) {
714 35223 : SDNode *Node = SD->getSDNode();
715 35223 : SDValue Op = SDValue(Node, SD->getResNo());
716 : // It's possible we replaced this SDNode with other(s) and therefore
717 : // didn't generate code for it. It's better to catch these cases where
718 : // they happen and transfer the debug info, but trying to guarantee that
719 : // in all cases would be very fragile; this is a safeguard for any
720 : // that were missed.
721 35223 : DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
722 35223 : if (I==VRBaseMap.end())
723 4 : MIB.addReg(0U); // undef
724 : else
725 35219 : AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
726 : /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
727 36530 : } else if (SD->getKind() == SDDbgValue::VREG) {
728 10696 : MIB.addReg(SD->getVReg(), RegState::Debug);
729 25834 : } else if (SD->getKind() == SDDbgValue::CONST) {
730 25834 : const Value *V = SD->getConst();
731 : if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
732 8896 : if (CI->getBitWidth() > 64)
733 : MIB.addCImm(CI);
734 : else
735 : MIB.addImm(CI->getSExtValue());
736 : } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
737 : MIB.addFPImm(CF);
738 : } else {
739 : // Could be an Undef. In any case insert an Undef so we can see what we
740 : // dropped.
741 16919 : MIB.addReg(0U);
742 : }
743 : } else {
744 : // Insert an Undef so we can see what we dropped.
745 0 : MIB.addReg(0U);
746 : }
747 :
748 : // Indirect addressing is indicated by an Imm as the second parameter.
749 71753 : if (SD->isIndirect())
750 : MIB.addImm(0U);
751 : else
752 71721 : MIB.addReg(0U, RegState::Debug);
753 :
754 : MIB.addMetadata(Var);
755 : MIB.addMetadata(Expr);
756 :
757 71753 : return &*MIB;
758 : }
759 :
760 : MachineInstr *
761 1 : InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
762 1 : MDNode *Label = SD->getLabel();
763 : DebugLoc DL = SD->getDebugLoc();
764 : assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
765 : "Expected inlined-at fields to agree");
766 :
767 1 : const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
768 1 : MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
769 : MIB.addMetadata(Label);
770 :
771 1 : return &*MIB;
772 : }
773 :
774 : /// EmitMachineNode - Generate machine code for a target-specific node and
775 : /// needed dependencies.
776 : ///
777 12148378 : void InstrEmitter::
778 : EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
779 : DenseMap<SDValue, unsigned> &VRBaseMap) {
780 12148378 : unsigned Opc = Node->getMachineOpcode();
781 :
782 : // Handle subreg insert/extract specially
783 24296756 : if (Opc == TargetOpcode::EXTRACT_SUBREG ||
784 12148378 : Opc == TargetOpcode::INSERT_SUBREG ||
785 12148378 : Opc == TargetOpcode::SUBREG_TO_REG) {
786 621614 : EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
787 759717 : return;
788 : }
789 :
790 : // Handle COPY_TO_REGCLASS specially.
791 11526764 : if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
792 47469 : EmitCopyToRegClassNode(Node, VRBaseMap);
793 47469 : return;
794 : }
795 :
796 : // Handle REG_SEQUENCE specially.
797 11479295 : if (Opc == TargetOpcode::REG_SEQUENCE) {
798 63467 : EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
799 63467 : return;
800 : }
801 :
802 11415828 : if (Opc == TargetOpcode::IMPLICIT_DEF)
803 : // We want a unique VR for each IMPLICIT_DEF use.
804 : return;
805 :
806 11388661 : const MCInstrDesc &II = TII->get(Opc);
807 11388661 : unsigned NumResults = CountResults(Node);
808 11388661 : unsigned NumDefs = II.getNumDefs();
809 : const MCPhysReg *ScratchRegs = nullptr;
810 :
811 : // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
812 11388661 : if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
813 : // Stackmaps do not have arguments and do not preserve their calling
814 : // convention. However, to simplify runtime support, they clobber the same
815 : // scratch registers as AnyRegCC.
816 : unsigned CC = CallingConv::AnyReg;
817 286 : if (Opc == TargetOpcode::PATCHPOINT) {
818 146 : CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
819 : NumDefs = NumResults;
820 : }
821 286 : ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
822 : }
823 :
824 11388661 : unsigned NumImpUses = 0;
825 : unsigned NodeOperands =
826 22777322 : countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
827 11388661 : bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
828 : #ifndef NDEBUG
829 : unsigned NumMIOperands = NodeOperands + NumResults;
830 : if (II.isVariadic())
831 : assert(NumMIOperands >= II.getNumOperands() &&
832 : "Too few operands for a variadic node!");
833 : else
834 : assert(NumMIOperands >= II.getNumOperands() &&
835 : NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
836 : NumImpUses &&
837 : "#operands for dag node doesn't match .td file!");
838 : #endif
839 :
840 : // Create the new machine instruction.
841 11388661 : MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
842 :
843 : // Add result register values for things that are defined by this
844 : // instruction.
845 11388661 : if (NumResults) {
846 7087697 : CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
847 :
848 : // Transfer any IR flags from the SDNode to the MachineInstr
849 7087697 : MachineInstr *MI = MIB.getInstr();
850 7087697 : const SDNodeFlags Flags = Node->getFlags();
851 7087697 : if (Flags.hasNoSignedZeros())
852 : MI->setFlag(MachineInstr::MIFlag::FmNsz);
853 :
854 7087697 : if (Flags.hasAllowReciprocal())
855 : MI->setFlag(MachineInstr::MIFlag::FmArcp);
856 :
857 7087697 : if (Flags.hasNoNaNs())
858 : MI->setFlag(MachineInstr::MIFlag::FmNoNans);
859 :
860 7087697 : if (Flags.hasNoInfs())
861 : MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
862 :
863 7087697 : if (Flags.hasAllowContract())
864 : MI->setFlag(MachineInstr::MIFlag::FmContract);
865 :
866 7087697 : if (Flags.hasApproximateFuncs())
867 : MI->setFlag(MachineInstr::MIFlag::FmAfn);
868 :
869 7087697 : if (Flags.hasAllowReassociation())
870 : MI->setFlag(MachineInstr::MIFlag::FmReassoc);
871 :
872 7087697 : if (Flags.hasNoUnsignedWrap())
873 : MI->setFlag(MachineInstr::MIFlag::NoUWrap);
874 :
875 7087697 : if (Flags.hasNoSignedWrap())
876 : MI->setFlag(MachineInstr::MIFlag::NoSWrap);
877 :
878 7087697 : if (Flags.hasExact())
879 : MI->setFlag(MachineInstr::MIFlag::IsExact);
880 : }
881 :
882 : // Emit all of the actual operands of this instruction, adding them to the
883 : // instruction as appropriate.
884 : bool HasOptPRefs = NumDefs > NumResults;
885 : assert((!HasOptPRefs || !HasPhysRegOuts) &&
886 : "Unable to cope with optional defs and phys regs defs!");
887 11388661 : unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
888 55952772 : for (unsigned i = NumSkip; i != NodeOperands; ++i)
889 89128222 : AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
890 : VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
891 :
892 : // Add scratch registers as implicit def and early clobber
893 11388661 : if (ScratchRegs)
894 846 : for (unsigned i = 0; ScratchRegs[i]; ++i)
895 : MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
896 560 : RegState::EarlyClobber);
897 :
898 : // Set the memory reference descriptions of this instruction now that it is
899 : // part of the function.
900 11388661 : MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
901 :
902 : // Insert the instruction into position in the block. This needs to
903 : // happen before any custom inserter hook is called so that the
904 : // hook knows where in the block to insert the replacement code.
905 11388661 : MBB->insert(InsertPos, MIB);
906 :
907 : // The MachineInstr may also define physregs instead of virtregs. These
908 : // physreg values can reach other instructions in different ways:
909 : //
910 : // 1. When there is a use of a Node value beyond the explicitly defined
911 : // virtual registers, we emit a CopyFromReg for one of the implicitly
912 : // defined physregs. This only happens when HasPhysRegOuts is true.
913 : //
914 : // 2. A CopyFromReg reading a physreg may be glued to this instruction.
915 : //
916 : // 3. A glued instruction may implicitly use a physreg.
917 : //
918 : // 4. A glued instruction may use a RegisterSDNode operand.
919 : //
920 : // Collect all the used physreg defs, and make sure that any unused physreg
921 : // defs are marked as dead.
922 : SmallVector<unsigned, 8> UsedRegs;
923 :
924 : // Additional results must be physical register defs.
925 11388661 : if (HasPhysRegOuts) {
926 5706603 : for (unsigned i = NumDefs; i < NumResults; ++i) {
927 2853573 : unsigned Reg = II.getImplicitDefs()[i - NumDefs];
928 2853573 : if (!Node->hasAnyUseOfValue(i))
929 2634064 : continue;
930 : // This implicitly defined physreg has a use.
931 219509 : UsedRegs.push_back(Reg);
932 219509 : EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
933 : }
934 : }
935 :
936 : // Scan the glue chain for any used physregs.
937 22777322 : if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
938 5055126 : for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
939 3899912 : if (F->getOpcode() == ISD::CopyFromReg) {
940 1665444 : UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
941 832722 : continue;
942 1117234 : } else if (F->getOpcode() == ISD::CopyToReg) {
943 : // Skip CopyToReg nodes that are internal to the glue chain.
944 : continue;
945 : }
946 : // Collect declared implicit uses.
947 2231934 : const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
948 1115967 : UsedRegs.append(MCID.getImplicitUses(),
949 2133290 : MCID.getImplicitUses() + MCID.getNumImplicitUses());
950 : // In addition to declared implicit uses, we must also check for
951 : // direct RegisterSDNode operands.
952 5858360 : for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
953 4742393 : if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
954 159945 : unsigned Reg = R->getReg();
955 159945 : if (TargetRegisterInfo::isPhysicalRegister(Reg))
956 10116 : UsedRegs.push_back(Reg);
957 : }
958 : }
959 : }
960 :
961 : // Finally mark unused registers as dead.
962 11388661 : if (!UsedRegs.empty() || II.getImplicitDefs())
963 7794208 : MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
964 :
965 : // Run post-isel target hook to adjust this instruction if needed.
966 22777322 : if (II.hasPostISelHook())
967 42678 : TLI->AdjustInstrPostInstrSelection(*MIB, Node);
968 : }
969 :
970 : /// EmitSpecialNode - Generate machine code for a target-independent node and
971 : /// needed dependencies.
972 8161679 : void InstrEmitter::
973 : EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
974 : DenseMap<SDValue, unsigned> &VRBaseMap) {
975 16323358 : switch (Node->getOpcode()) {
976 0 : default:
977 : #ifndef NDEBUG
978 : Node->dump();
979 : #endif
980 0 : llvm_unreachable("This target-independent node should have been selected!");
981 : case ISD::EntryToken:
982 : llvm_unreachable("EntryToken should have been excluded from the schedule!");
983 : case ISD::MERGE_VALUES:
984 : case ISD::TokenFactor: // fall thru
985 : break;
986 3661433 : case ISD::CopyToReg: {
987 : unsigned SrcReg;
988 3661433 : SDValue SrcVal = Node->getOperand(2);
989 : if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
990 47303 : SrcReg = R->getReg();
991 : else
992 3614130 : SrcReg = getVR(SrcVal, VRBaseMap);
993 :
994 3661433 : unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
995 3661433 : if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
996 : break;
997 :
998 8412021 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
999 5608014 : DestReg).addReg(SrcReg);
1000 2804007 : break;
1001 : }
1002 2021288 : case ISD::CopyFromReg: {
1003 2021288 : unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1004 2021288 : EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1005 2021288 : break;
1006 : }
1007 993853 : case ISD::EH_LABEL:
1008 : case ISD::ANNOTATION_LABEL: {
1009 : unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1010 993853 : ? TargetOpcode::EH_LABEL
1011 : : TargetOpcode::ANNOTATION_LABEL;
1012 993853 : MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1013 1987706 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1014 1987706 : TII->get(Opc)).addSym(S);
1015 993853 : break;
1016 : }
1017 :
1018 56940 : case ISD::LIFETIME_START:
1019 : case ISD::LIFETIME_END: {
1020 56940 : unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1021 : TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1022 :
1023 56940 : FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1024 113880 : BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1025 56940 : .addFrameIndex(FI->getIndex());
1026 56940 : break;
1027 : }
1028 :
1029 16827 : case ISD::INLINEASM: {
1030 16827 : unsigned NumOps = Node->getNumOperands();
1031 33654 : if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1032 : --NumOps; // Ignore the glue operand.
1033 :
1034 : // Create the inline asm machine instruction.
1035 16827 : MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
1036 16827 : TII->get(TargetOpcode::INLINEASM));
1037 :
1038 : // Add the asm string as an external symbol operand.
1039 16827 : SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1040 16827 : const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1041 : MIB.addExternalSymbol(AsmStr);
1042 :
1043 : // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1044 : // bits.
1045 : int64_t ExtraInfo =
1046 : cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1047 50481 : getZExtValue();
1048 : MIB.addImm(ExtraInfo);
1049 :
1050 : // Remember to operand index of the group flags.
1051 : SmallVector<unsigned, 8> GroupIdx;
1052 :
1053 : // Remember registers that are part of early-clobber defs.
1054 : SmallVector<unsigned, 8> ECRegs;
1055 :
1056 : // Add all of the operand registers to the instruction.
1057 81161 : for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1058 : unsigned Flags =
1059 193002 : cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1060 : const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1061 :
1062 64334 : GroupIdx.push_back(MIB->getNumOperands());
1063 64334 : MIB.addImm(Flags);
1064 64334 : ++i; // Skip the ID value.
1065 :
1066 : switch (InlineAsm::getKind(Flags)) {
1067 0 : default: llvm_unreachable("Bad flags!");
1068 : case InlineAsm::Kind_RegDef:
1069 7533 : for (unsigned j = 0; j != NumVals; ++j, ++i) {
1070 7554 : unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1071 : // FIXME: Add dead flags for physical and virtual registers defined.
1072 : // For now, mark physical register defs as implicit to help fast
1073 : // regalloc. This makes inline asm look a lot like calls.
1074 : MIB.addReg(Reg, RegState::Define |
1075 3777 : getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1076 3756 : }
1077 : break;
1078 : case InlineAsm::Kind_RegDefEarlyClobber:
1079 : case InlineAsm::Kind_Clobber:
1080 98746 : for (unsigned j = 0; j != NumVals; ++j, ++i) {
1081 98754 : unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1082 : MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
1083 49377 : getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1084 49377 : ECRegs.push_back(Reg);
1085 49369 : }
1086 : break;
1087 : case InlineAsm::Kind_RegUse: // Use of register.
1088 : case InlineAsm::Kind_Imm: // Immediate.
1089 : case InlineAsm::Kind_Mem: // Addressing mode.
1090 : // The addressing mode has been selected, just add all of the
1091 : // operands to the machine instruction.
1092 34354 : for (unsigned j = 0; j != NumVals; ++j, ++i)
1093 46290 : AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1094 11209 : /*IsDebug=*/false, IsClone, IsCloned);
1095 :
1096 : // Manually set isTied bits.
1097 11209 : if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1098 : unsigned DefGroup = 0;
1099 : if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1100 638 : unsigned DefIdx = GroupIdx[DefGroup] + 1;
1101 319 : unsigned UseIdx = GroupIdx.back() + 1;
1102 651 : for (unsigned j = 0; j != NumVals; ++j)
1103 332 : MIB->tieOperands(DefIdx + j, UseIdx + j);
1104 : }
1105 : }
1106 : break;
1107 : }
1108 : }
1109 :
1110 : // GCC inline assembly allows input operands to also be early-clobber
1111 : // output operands (so long as the operand is written only after it's
1112 : // used), but this does not match the semantics of our early-clobber flag.
1113 : // If an early-clobber operand register is also an input operand register,
1114 : // then remove the early-clobber flag.
1115 66204 : for (unsigned Reg : ECRegs) {
1116 49377 : if (MIB->readsRegister(Reg, TRI)) {
1117 42 : MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
1118 : assert(MO && "No def operand for clobbered register?");
1119 : MO->setIsEarlyClobber(false);
1120 : }
1121 : }
1122 :
1123 : // Get the mdnode from the asm if it exists and add it to the instruction.
1124 16827 : SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1125 16827 : const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1126 16827 : if (MD)
1127 : MIB.addMetadata(MD);
1128 :
1129 16827 : MBB->insert(InsertPos, MIB);
1130 : break;
1131 : }
1132 : }
1133 8161679 : }
1134 :
1135 : /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1136 : /// at the given position in the given block.
1137 1269048 : InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1138 1269048 : MachineBasicBlock::iterator insertpos)
1139 2538096 : : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1140 1269048 : TII(MF->getSubtarget().getInstrInfo()),
1141 1269049 : TRI(MF->getSubtarget().getRegisterInfo()),
1142 1269050 : TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1143 1269048 : InsertPos(insertpos) {}
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