Line data Source code
1 : //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This implements the TargetLoweringBase class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "llvm/ADT/BitVector.h"
15 : #include "llvm/ADT/STLExtras.h"
16 : #include "llvm/ADT/SmallVector.h"
17 : #include "llvm/ADT/StringExtras.h"
18 : #include "llvm/ADT/StringRef.h"
19 : #include "llvm/ADT/Triple.h"
20 : #include "llvm/ADT/Twine.h"
21 : #include "llvm/CodeGen/Analysis.h"
22 : #include "llvm/CodeGen/ISDOpcodes.h"
23 : #include "llvm/CodeGen/MachineBasicBlock.h"
24 : #include "llvm/CodeGen/MachineFrameInfo.h"
25 : #include "llvm/CodeGen/MachineFunction.h"
26 : #include "llvm/CodeGen/MachineInstr.h"
27 : #include "llvm/CodeGen/MachineInstrBuilder.h"
28 : #include "llvm/CodeGen/MachineMemOperand.h"
29 : #include "llvm/CodeGen/MachineOperand.h"
30 : #include "llvm/CodeGen/MachineRegisterInfo.h"
31 : #include "llvm/CodeGen/RuntimeLibcalls.h"
32 : #include "llvm/CodeGen/StackMaps.h"
33 : #include "llvm/CodeGen/TargetLowering.h"
34 : #include "llvm/CodeGen/TargetOpcodes.h"
35 : #include "llvm/CodeGen/TargetRegisterInfo.h"
36 : #include "llvm/CodeGen/ValueTypes.h"
37 : #include "llvm/IR/Attributes.h"
38 : #include "llvm/IR/CallingConv.h"
39 : #include "llvm/IR/DataLayout.h"
40 : #include "llvm/IR/DerivedTypes.h"
41 : #include "llvm/IR/Function.h"
42 : #include "llvm/IR/GlobalValue.h"
43 : #include "llvm/IR/GlobalVariable.h"
44 : #include "llvm/IR/IRBuilder.h"
45 : #include "llvm/IR/Module.h"
46 : #include "llvm/IR/Type.h"
47 : #include "llvm/Support/BranchProbability.h"
48 : #include "llvm/Support/Casting.h"
49 : #include "llvm/Support/CommandLine.h"
50 : #include "llvm/Support/Compiler.h"
51 : #include "llvm/Support/ErrorHandling.h"
52 : #include "llvm/Support/MachineValueType.h"
53 : #include "llvm/Support/MathExtras.h"
54 : #include "llvm/Target/TargetMachine.h"
55 : #include <algorithm>
56 : #include <cassert>
57 : #include <cstddef>
58 : #include <cstdint>
59 : #include <cstring>
60 : #include <iterator>
61 : #include <string>
62 : #include <tuple>
63 : #include <utility>
64 :
65 : using namespace llvm;
66 :
67 : static cl::opt<bool> JumpIsExpensiveOverride(
68 : "jump-is-expensive", cl::init(false),
69 : cl::desc("Do not create extra branches to split comparison logic."),
70 : cl::Hidden);
71 :
72 : static cl::opt<unsigned> MinimumJumpTableEntries
73 : ("min-jump-table-entries", cl::init(4), cl::Hidden,
74 : cl::desc("Set minimum number of entries to use a jump table."));
75 :
76 : static cl::opt<unsigned> MaximumJumpTableSize
77 : ("max-jump-table-size", cl::init(0), cl::Hidden,
78 : cl::desc("Set maximum size of jump tables; zero for no limit."));
79 :
80 : /// Minimum jump table density for normal functions.
81 : static cl::opt<unsigned>
82 : JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
83 : cl::desc("Minimum density for building a jump table in "
84 : "a normal function"));
85 :
86 : /// Minimum jump table density for -Os or -Oz functions.
87 : static cl::opt<unsigned> OptsizeJumpTableDensity(
88 : "optsize-jump-table-density", cl::init(40), cl::Hidden,
89 : cl::desc("Minimum density for building a jump table in "
90 : "an optsize function"));
91 :
92 2996 : static bool darwinHasSinCos(const Triple &TT) {
93 : assert(TT.isOSDarwin() && "should be called with darwin triple");
94 : // Don't bother with 32 bit x86.
95 2996 : if (TT.getArch() == Triple::x86)
96 : return false;
97 : // Macos < 10.9 has no sincos_stret.
98 : if (TT.isMacOSX())
99 1884 : return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
100 : // iOS < 7.0 has no sincos_stret.
101 : if (TT.isiOS())
102 616 : return !TT.isOSVersionLT(7, 0);
103 : // Any other darwin such as WatchOS/TvOS is new enough.
104 : return true;
105 : }
106 :
107 : // Although this default value is arbitrary, it is not random. It is assumed
108 : // that a condition that evaluates the same way by a higher percentage than this
109 : // is best represented as control flow. Therefore, the default value N should be
110 : // set such that the win from N% correct executions is greater than the loss
111 : // from (100 - N)% mispredicted executions for the majority of intended targets.
112 : static cl::opt<int> MinPercentageForPredictableBranch(
113 : "min-predictable-branch", cl::init(99),
114 : cl::desc("Minimum percentage (0-100) that a condition must be either true "
115 : "or false to assume that the condition is predictable"),
116 : cl::Hidden);
117 :
118 41320 : void TargetLoweringBase::InitLibcalls(const Triple &TT) {
119 : #define HANDLE_LIBCALL(code, name) \
120 : setLibcallName(RTLIB::code, name);
121 : #include "llvm/IR/RuntimeLibcalls.def"
122 : #undef HANDLE_LIBCALL
123 : // Initialize calling conventions to their default.
124 19461720 : for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 : setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C);
126 :
127 : // A few names are different on particular architectures or environments.
128 : if (TT.isOSDarwin()) {
129 : // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
130 : // of the gnueabi-style __gnu_*_ieee.
131 : // FIXME: What about other targets?
132 : setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
133 : setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
134 :
135 : // Some darwins have an optimized __bzero/bzero function.
136 2996 : switch (TT.getArch()) {
137 : case Triple::x86:
138 : case Triple::x86_64:
139 1843 : if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
140 : setLibcallName(RTLIB::BZERO, "__bzero");
141 : break;
142 : case Triple::aarch64:
143 : setLibcallName(RTLIB::BZERO, "bzero");
144 : break;
145 : default:
146 : break;
147 : }
148 :
149 2996 : if (darwinHasSinCos(TT)) {
150 : setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
151 : setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
152 382 : if (TT.isWatchABI()) {
153 : setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
154 : CallingConv::ARM_AAPCS_VFP);
155 : setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
156 : CallingConv::ARM_AAPCS_VFP);
157 : }
158 : }
159 : } else {
160 : setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
161 : setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
162 : }
163 :
164 41320 : if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
165 205 : (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
166 : setLibcallName(RTLIB::SINCOS_F32, "sincosf");
167 : setLibcallName(RTLIB::SINCOS_F64, "sincos");
168 : setLibcallName(RTLIB::SINCOS_F80, "sincosl");
169 : setLibcallName(RTLIB::SINCOS_F128, "sincosl");
170 : setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
171 : }
172 :
173 41320 : if (TT.isOSOpenBSD()) {
174 : setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
175 : }
176 41320 : }
177 :
178 : /// getFPEXT - Return the FPEXT_*_* value for the given types, or
179 : /// UNKNOWN_LIBCALL if there is none.
180 139 : RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
181 : if (OpVT == MVT::f16) {
182 : if (RetVT == MVT::f32)
183 0 : return FPEXT_F16_F32;
184 : } else if (OpVT == MVT::f32) {
185 : if (RetVT == MVT::f64)
186 98 : return FPEXT_F32_F64;
187 : if (RetVT == MVT::f128)
188 15 : return FPEXT_F32_F128;
189 : if (RetVT == MVT::ppcf128)
190 0 : return FPEXT_F32_PPCF128;
191 : } else if (OpVT == MVT::f64) {
192 : if (RetVT == MVT::f128)
193 21 : return FPEXT_F64_F128;
194 : else if (RetVT == MVT::ppcf128)
195 1 : return FPEXT_F64_PPCF128;
196 : } else if (OpVT == MVT::f80) {
197 : if (RetVT == MVT::f128)
198 4 : return FPEXT_F80_F128;
199 : }
200 :
201 : return UNKNOWN_LIBCALL;
202 : }
203 :
204 : /// getFPROUND - Return the FPROUND_*_* value for the given types, or
205 : /// UNKNOWN_LIBCALL if there is none.
206 694 : RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
207 : if (RetVT == MVT::f16) {
208 : if (OpVT == MVT::f32)
209 338 : return FPROUND_F32_F16;
210 : if (OpVT == MVT::f64)
211 290 : return FPROUND_F64_F16;
212 : if (OpVT == MVT::f80)
213 3 : return FPROUND_F80_F16;
214 : if (OpVT == MVT::f128)
215 0 : return FPROUND_F128_F16;
216 : if (OpVT == MVT::ppcf128)
217 0 : return FPROUND_PPCF128_F16;
218 : } else if (RetVT == MVT::f32) {
219 : if (OpVT == MVT::f64)
220 22 : return FPROUND_F64_F32;
221 : if (OpVT == MVT::f80)
222 0 : return FPROUND_F80_F32;
223 : if (OpVT == MVT::f128)
224 14 : return FPROUND_F128_F32;
225 : if (OpVT == MVT::ppcf128)
226 1 : return FPROUND_PPCF128_F32;
227 : } else if (RetVT == MVT::f64) {
228 : if (OpVT == MVT::f80)
229 0 : return FPROUND_F80_F64;
230 : if (OpVT == MVT::f128)
231 21 : return FPROUND_F128_F64;
232 : if (OpVT == MVT::ppcf128)
233 1 : return FPROUND_PPCF128_F64;
234 : } else if (RetVT == MVT::f80) {
235 : if (OpVT == MVT::f128)
236 4 : return FPROUND_F128_F80;
237 : }
238 :
239 : return UNKNOWN_LIBCALL;
240 : }
241 :
242 : /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
243 : /// UNKNOWN_LIBCALL if there is none.
244 231 : RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
245 : if (OpVT == MVT::f32) {
246 : if (RetVT == MVT::i32)
247 31 : return FPTOSINT_F32_I32;
248 : if (RetVT == MVT::i64)
249 35 : return FPTOSINT_F32_I64;
250 : if (RetVT == MVT::i128)
251 3 : return FPTOSINT_F32_I128;
252 : } else if (OpVT == MVT::f64) {
253 : if (RetVT == MVT::i32)
254 27 : return FPTOSINT_F64_I32;
255 : if (RetVT == MVT::i64)
256 40 : return FPTOSINT_F64_I64;
257 : if (RetVT == MVT::i128)
258 0 : return FPTOSINT_F64_I128;
259 : } else if (OpVT == MVT::f80) {
260 : if (RetVT == MVT::i32)
261 0 : return FPTOSINT_F80_I32;
262 : if (RetVT == MVT::i64)
263 0 : return FPTOSINT_F80_I64;
264 : if (RetVT == MVT::i128)
265 0 : return FPTOSINT_F80_I128;
266 : } else if (OpVT == MVT::f128) {
267 : if (RetVT == MVT::i32)
268 39 : return FPTOSINT_F128_I32;
269 : if (RetVT == MVT::i64)
270 45 : return FPTOSINT_F128_I64;
271 : if (RetVT == MVT::i128)
272 3 : return FPTOSINT_F128_I128;
273 : } else if (OpVT == MVT::ppcf128) {
274 : if (RetVT == MVT::i32)
275 0 : return FPTOSINT_PPCF128_I32;
276 : if (RetVT == MVT::i64)
277 2 : return FPTOSINT_PPCF128_I64;
278 : if (RetVT == MVT::i128)
279 0 : return FPTOSINT_PPCF128_I128;
280 : }
281 : return UNKNOWN_LIBCALL;
282 : }
283 :
284 : /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
285 : /// UNKNOWN_LIBCALL if there is none.
286 184 : RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
287 : if (OpVT == MVT::f32) {
288 : if (RetVT == MVT::i32)
289 27 : return FPTOUINT_F32_I32;
290 : if (RetVT == MVT::i64)
291 34 : return FPTOUINT_F32_I64;
292 : if (RetVT == MVT::i128)
293 0 : return FPTOUINT_F32_I128;
294 : } else if (OpVT == MVT::f64) {
295 : if (RetVT == MVT::i32)
296 29 : return FPTOUINT_F64_I32;
297 : if (RetVT == MVT::i64)
298 35 : return FPTOUINT_F64_I64;
299 : if (RetVT == MVT::i128)
300 2 : return FPTOUINT_F64_I128;
301 : } else if (OpVT == MVT::f80) {
302 : if (RetVT == MVT::i32)
303 0 : return FPTOUINT_F80_I32;
304 : if (RetVT == MVT::i64)
305 0 : return FPTOUINT_F80_I64;
306 : if (RetVT == MVT::i128)
307 1 : return FPTOUINT_F80_I128;
308 : } else if (OpVT == MVT::f128) {
309 : if (RetVT == MVT::i32)
310 15 : return FPTOUINT_F128_I32;
311 : if (RetVT == MVT::i64)
312 30 : return FPTOUINT_F128_I64;
313 : if (RetVT == MVT::i128)
314 3 : return FPTOUINT_F128_I128;
315 : } else if (OpVT == MVT::ppcf128) {
316 : if (RetVT == MVT::i32)
317 0 : return FPTOUINT_PPCF128_I32;
318 : if (RetVT == MVT::i64)
319 1 : return FPTOUINT_PPCF128_I64;
320 : if (RetVT == MVT::i128)
321 1 : return FPTOUINT_PPCF128_I128;
322 : }
323 : return UNKNOWN_LIBCALL;
324 : }
325 :
326 : /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
327 : /// UNKNOWN_LIBCALL if there is none.
328 185 : RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
329 : if (OpVT == MVT::i32) {
330 : if (RetVT == MVT::f32)
331 26 : return SINTTOFP_I32_F32;
332 : if (RetVT == MVT::f64)
333 30 : return SINTTOFP_I32_F64;
334 : if (RetVT == MVT::f80)
335 0 : return SINTTOFP_I32_F80;
336 : if (RetVT == MVT::f128)
337 23 : return SINTTOFP_I32_F128;
338 : if (RetVT == MVT::ppcf128)
339 1 : return SINTTOFP_I32_PPCF128;
340 : } else if (OpVT == MVT::i64) {
341 : if (RetVT == MVT::f32)
342 38 : return SINTTOFP_I64_F32;
343 : if (RetVT == MVT::f64)
344 43 : return SINTTOFP_I64_F64;
345 : if (RetVT == MVT::f80)
346 0 : return SINTTOFP_I64_F80;
347 : if (RetVT == MVT::f128)
348 9 : return SINTTOFP_I64_F128;
349 : if (RetVT == MVT::ppcf128)
350 0 : return SINTTOFP_I64_PPCF128;
351 : } else if (OpVT == MVT::i128) {
352 : if (RetVT == MVT::f32)
353 1 : return SINTTOFP_I128_F32;
354 : if (RetVT == MVT::f64)
355 2 : return SINTTOFP_I128_F64;
356 : if (RetVT == MVT::f80)
357 0 : return SINTTOFP_I128_F80;
358 : if (RetVT == MVT::f128)
359 0 : return SINTTOFP_I128_F128;
360 : if (RetVT == MVT::ppcf128)
361 0 : return SINTTOFP_I128_PPCF128;
362 : }
363 : return UNKNOWN_LIBCALL;
364 : }
365 :
366 : /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
367 : /// UNKNOWN_LIBCALL if there is none.
368 190 : RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
369 : if (OpVT == MVT::i32) {
370 : if (RetVT == MVT::f32)
371 28 : return UINTTOFP_I32_F32;
372 : if (RetVT == MVT::f64)
373 36 : return UINTTOFP_I32_F64;
374 : if (RetVT == MVT::f80)
375 0 : return UINTTOFP_I32_F80;
376 : if (RetVT == MVT::f128)
377 18 : return UINTTOFP_I32_F128;
378 : if (RetVT == MVT::ppcf128)
379 1 : return UINTTOFP_I32_PPCF128;
380 : } else if (OpVT == MVT::i64) {
381 : if (RetVT == MVT::f32)
382 35 : return UINTTOFP_I64_F32;
383 : if (RetVT == MVT::f64)
384 34 : return UINTTOFP_I64_F64;
385 : if (RetVT == MVT::f80)
386 0 : return UINTTOFP_I64_F80;
387 : if (RetVT == MVT::f128)
388 16 : return UINTTOFP_I64_F128;
389 : if (RetVT == MVT::ppcf128)
390 0 : return UINTTOFP_I64_PPCF128;
391 : } else if (OpVT == MVT::i128) {
392 : if (RetVT == MVT::f32)
393 2 : return UINTTOFP_I128_F32;
394 : if (RetVT == MVT::f64)
395 0 : return UINTTOFP_I128_F64;
396 : if (RetVT == MVT::f80)
397 0 : return UINTTOFP_I128_F80;
398 : if (RetVT == MVT::f128)
399 2 : return UINTTOFP_I128_F128;
400 : if (RetVT == MVT::ppcf128)
401 0 : return UINTTOFP_I128_PPCF128;
402 : }
403 : return UNKNOWN_LIBCALL;
404 : }
405 :
406 536 : RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
407 : #define OP_TO_LIBCALL(Name, Enum) \
408 : case Name: \
409 : switch (VT.SimpleTy) { \
410 : default: \
411 : return UNKNOWN_LIBCALL; \
412 : case MVT::i8: \
413 : return Enum##_1; \
414 : case MVT::i16: \
415 : return Enum##_2; \
416 : case MVT::i32: \
417 : return Enum##_4; \
418 : case MVT::i64: \
419 : return Enum##_8; \
420 : case MVT::i128: \
421 : return Enum##_16; \
422 : }
423 :
424 536 : switch (Opc) {
425 27 : OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
426 37 : OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
427 209 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
428 74 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
429 48 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
430 51 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
431 47 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
432 3 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
433 6 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
434 14 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
435 6 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
436 14 : OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
437 : }
438 :
439 : #undef OP_TO_LIBCALL
440 :
441 : return UNKNOWN_LIBCALL;
442 : }
443 :
444 6 : RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
445 : switch (ElementSize) {
446 : case 1:
447 : return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
448 : case 2:
449 : return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
450 : case 4:
451 : return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
452 : case 8:
453 : return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
454 : case 16:
455 : return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
456 : default:
457 : return UNKNOWN_LIBCALL;
458 : }
459 : }
460 :
461 6 : RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
462 : switch (ElementSize) {
463 : case 1:
464 : return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
465 : case 2:
466 : return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
467 : case 4:
468 : return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
469 : case 8:
470 : return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
471 : case 16:
472 : return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
473 : default:
474 : return UNKNOWN_LIBCALL;
475 : }
476 : }
477 :
478 6 : RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
479 : switch (ElementSize) {
480 : case 1:
481 : return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
482 : case 2:
483 : return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
484 : case 4:
485 : return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
486 : case 8:
487 : return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
488 : case 16:
489 : return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
490 : default:
491 : return UNKNOWN_LIBCALL;
492 : }
493 : }
494 :
495 : /// InitCmpLibcallCCs - Set default comparison libcall CC.
496 41320 : static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
497 41320 : memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
498 41320 : CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
499 41320 : CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
500 41320 : CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
501 41320 : CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
502 41320 : CCs[RTLIB::UNE_F32] = ISD::SETNE;
503 41320 : CCs[RTLIB::UNE_F64] = ISD::SETNE;
504 41320 : CCs[RTLIB::UNE_F128] = ISD::SETNE;
505 41320 : CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
506 41320 : CCs[RTLIB::OGE_F32] = ISD::SETGE;
507 41320 : CCs[RTLIB::OGE_F64] = ISD::SETGE;
508 41320 : CCs[RTLIB::OGE_F128] = ISD::SETGE;
509 41320 : CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
510 41320 : CCs[RTLIB::OLT_F32] = ISD::SETLT;
511 41320 : CCs[RTLIB::OLT_F64] = ISD::SETLT;
512 41320 : CCs[RTLIB::OLT_F128] = ISD::SETLT;
513 41320 : CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
514 41320 : CCs[RTLIB::OLE_F32] = ISD::SETLE;
515 41320 : CCs[RTLIB::OLE_F64] = ISD::SETLE;
516 41320 : CCs[RTLIB::OLE_F128] = ISD::SETLE;
517 41320 : CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
518 41320 : CCs[RTLIB::OGT_F32] = ISD::SETGT;
519 41320 : CCs[RTLIB::OGT_F64] = ISD::SETGT;
520 41320 : CCs[RTLIB::OGT_F128] = ISD::SETGT;
521 41320 : CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
522 41320 : CCs[RTLIB::UO_F32] = ISD::SETNE;
523 41320 : CCs[RTLIB::UO_F64] = ISD::SETNE;
524 41320 : CCs[RTLIB::UO_F128] = ISD::SETNE;
525 41320 : CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
526 41320 : CCs[RTLIB::O_F32] = ISD::SETEQ;
527 41320 : CCs[RTLIB::O_F64] = ISD::SETEQ;
528 41320 : CCs[RTLIB::O_F128] = ISD::SETEQ;
529 41320 : CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
530 41320 : }
531 :
532 : /// NOTE: The TargetMachine owns TLOF.
533 41320 : TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
534 41320 : initActions();
535 :
536 : // Perform these initializations only once.
537 41320 : MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
538 41320 : MaxLoadsPerMemcmp = 8;
539 41320 : MaxGluedStoresPerMemcpy = 0;
540 41320 : MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
541 41320 : MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
542 41320 : UseUnderscoreSetJmp = false;
543 41320 : UseUnderscoreLongJmp = false;
544 41320 : HasMultipleConditionRegisters = false;
545 41320 : HasExtractBitsInsn = false;
546 41320 : JumpIsExpensive = JumpIsExpensiveOverride;
547 41320 : PredictableSelectIsExpensive = false;
548 41320 : EnableExtLdPromotion = false;
549 41320 : HasFloatingPointExceptions = true;
550 41320 : StackPointerRegisterToSaveRestore = 0;
551 41320 : BooleanContents = UndefinedBooleanContent;
552 41320 : BooleanFloatContents = UndefinedBooleanContent;
553 41320 : BooleanVectorContents = UndefinedBooleanContent;
554 41320 : SchedPreferenceInfo = Sched::ILP;
555 41320 : JumpBufSize = 0;
556 41320 : JumpBufAlignment = 0;
557 41320 : MinFunctionAlignment = 0;
558 41320 : PrefFunctionAlignment = 0;
559 41320 : PrefLoopAlignment = 0;
560 41320 : GatherAllAliasesMaxDepth = 18;
561 41320 : MinStackArgumentAlignment = 1;
562 : // TODO: the default will be switched to 0 in the next commit, along
563 : // with the Target-specific changes necessary.
564 41320 : MaxAtomicSizeInBitsSupported = 1024;
565 :
566 41320 : MinCmpXchgSizeInBits = 0;
567 41320 : SupportsUnalignedAtomics = false;
568 :
569 41320 : std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
570 :
571 82640 : InitLibcalls(TM.getTargetTriple());
572 41320 : InitCmpLibcallCCs(CmpLibcallCCs);
573 41320 : }
574 :
575 41320 : void TargetLoweringBase::initActions() {
576 : // All operations default to being supported.
577 41320 : memset(OpActions, 0, sizeof(OpActions));
578 41320 : memset(LoadExtActions, 0, sizeof(LoadExtActions));
579 41320 : memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
580 41320 : memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
581 41320 : memset(CondCodeActions, 0, sizeof(CondCodeActions));
582 41320 : std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
583 41320 : std::fill(std::begin(TargetDAGCombineArray),
584 : std::end(TargetDAGCombineArray), 0);
585 :
586 : // Set default actions for various operations.
587 4710480 : for (MVT VT : MVT::all_valuetypes()) {
588 : // Default all indexed load / store to expand.
589 18676640 : for (unsigned IM = (unsigned)ISD::PRE_INC;
590 23345800 : IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
591 : setIndexedLoadAction(IM, VT, Expand);
592 : setIndexedStoreAction(IM, VT, Expand);
593 : }
594 :
595 : // Most backends expect to see the node which just returns the value loaded.
596 : setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
597 :
598 : // These operations default to expand.
599 : setOperationAction(ISD::FGETSIGN, VT, Expand);
600 : setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
601 : setOperationAction(ISD::FMINNUM, VT, Expand);
602 : setOperationAction(ISD::FMAXNUM, VT, Expand);
603 : setOperationAction(ISD::FMINNAN, VT, Expand);
604 : setOperationAction(ISD::FMAXNAN, VT, Expand);
605 : setOperationAction(ISD::FMAD, VT, Expand);
606 : setOperationAction(ISD::SMIN, VT, Expand);
607 : setOperationAction(ISD::SMAX, VT, Expand);
608 : setOperationAction(ISD::UMIN, VT, Expand);
609 : setOperationAction(ISD::UMAX, VT, Expand);
610 : setOperationAction(ISD::ABS, VT, Expand);
611 : setOperationAction(ISD::SADDSAT, VT, Expand);
612 :
613 : // Overflow operations default to expand
614 : setOperationAction(ISD::SADDO, VT, Expand);
615 : setOperationAction(ISD::SSUBO, VT, Expand);
616 : setOperationAction(ISD::UADDO, VT, Expand);
617 : setOperationAction(ISD::USUBO, VT, Expand);
618 : setOperationAction(ISD::SMULO, VT, Expand);
619 : setOperationAction(ISD::UMULO, VT, Expand);
620 :
621 : // ADDCARRY operations default to expand
622 : setOperationAction(ISD::ADDCARRY, VT, Expand);
623 : setOperationAction(ISD::SUBCARRY, VT, Expand);
624 : setOperationAction(ISD::SETCCCARRY, VT, Expand);
625 :
626 : // ADDC/ADDE/SUBC/SUBE default to expand.
627 : setOperationAction(ISD::ADDC, VT, Expand);
628 : setOperationAction(ISD::ADDE, VT, Expand);
629 : setOperationAction(ISD::SUBC, VT, Expand);
630 : setOperationAction(ISD::SUBE, VT, Expand);
631 :
632 : // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
633 : setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
634 : setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
635 :
636 : setOperationAction(ISD::BITREVERSE, VT, Expand);
637 :
638 : // These library functions default to expand.
639 : setOperationAction(ISD::FROUND, VT, Expand);
640 : setOperationAction(ISD::FPOWI, VT, Expand);
641 :
642 : // These operations default to expand for vector types.
643 4669160 : if (VT.isVector()) {
644 : setOperationAction(ISD::FCOPYSIGN, VT, Expand);
645 : setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
646 : setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
647 : setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
648 : }
649 :
650 : // For most targets @llvm.get.dynamic.area.offset just returns 0.
651 : setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
652 : }
653 :
654 : // Most targets ignore the @llvm.prefetch intrinsic.
655 : setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
656 :
657 : // Most targets also ignore the @llvm.readcyclecounter intrinsic.
658 : setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
659 :
660 : // ConstantFP nodes default to expand. Targets can either change this to
661 : // Legal, in which case all fp constants are legal, or use isFPImmLegal()
662 : // to optimize expansions for certain constants.
663 : setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
664 : setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
665 : setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
666 : setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
667 : setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
668 :
669 : // These library functions default to expand.
670 165280 : for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
671 : setOperationAction(ISD::FCBRT, VT, Expand);
672 : setOperationAction(ISD::FLOG , VT, Expand);
673 : setOperationAction(ISD::FLOG2, VT, Expand);
674 : setOperationAction(ISD::FLOG10, VT, Expand);
675 : setOperationAction(ISD::FEXP , VT, Expand);
676 : setOperationAction(ISD::FEXP2, VT, Expand);
677 : setOperationAction(ISD::FFLOOR, VT, Expand);
678 : setOperationAction(ISD::FNEARBYINT, VT, Expand);
679 : setOperationAction(ISD::FCEIL, VT, Expand);
680 : setOperationAction(ISD::FRINT, VT, Expand);
681 : setOperationAction(ISD::FTRUNC, VT, Expand);
682 : setOperationAction(ISD::FROUND, VT, Expand);
683 : }
684 :
685 : // Default ISD::TRAP to expand (which turns it into abort).
686 : setOperationAction(ISD::TRAP, MVT::Other, Expand);
687 :
688 : // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
689 : // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
690 : setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
691 41320 : }
692 :
693 110722 : MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
694 : EVT) const {
695 110722 : return MVT::getIntegerVT(8 * DL.getPointerSize(0));
696 : }
697 :
698 388131 : EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
699 : bool LegalTypes) const {
700 : assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
701 388131 : if (LHSTy.isVector())
702 7804 : return LHSTy;
703 365642 : return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
704 760654 : : getPointerTy(DL);
705 : }
706 :
707 185 : bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
708 : assert(isTypeLegal(VT));
709 185 : switch (Op) {
710 : default:
711 : return false;
712 41 : case ISD::SDIV:
713 : case ISD::UDIV:
714 : case ISD::SREM:
715 : case ISD::UREM:
716 41 : return true;
717 : }
718 : }
719 :
720 4886 : void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
721 : // If the command-line option was specified, ignore this request.
722 4886 : if (!JumpIsExpensiveOverride.getNumOccurrences())
723 4886 : JumpIsExpensive = isExpensive;
724 4886 : }
725 :
726 : TargetLoweringBase::LegalizeKind
727 101738705 : TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
728 : // If this is a simple type, use the ComputeRegisterProp mechanism.
729 101738705 : if (VT.isSimple()) {
730 101308551 : MVT SVT = VT.getSimpleVT();
731 : assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
732 101308551 : MVT NVT = TransformToType[SVT.SimpleTy];
733 : LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
734 :
735 : assert((LA == TypeLegal || LA == TypeSoftenFloat ||
736 : ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
737 : "Promote may not follow Expand or Promote");
738 :
739 101308551 : if (LA == TypeSplitVector)
740 : return LegalizeKind(LA,
741 289740 : EVT::getVectorVT(Context, SVT.getVectorElementType(),
742 289740 : SVT.getVectorNumElements() / 2));
743 101018811 : if (LA == TypeScalarizeVector)
744 103062 : return LegalizeKind(LA, SVT.getVectorElementType());
745 : return LegalizeKind(LA, NVT);
746 : }
747 :
748 : // Handle Extended Scalar Types.
749 430154 : if (!VT.isVector()) {
750 : assert(VT.isInteger() && "Float types must be simple");
751 361889 : unsigned BitSize = VT.getSizeInBits();
752 : // First promote to a power-of-two size, then expand if necessary.
753 361889 : if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
754 191655 : EVT NVT = VT.getRoundIntegerType(Context);
755 : assert(NVT != VT && "Unable to round integer VT");
756 191655 : LegalizeKind NextStep = getTypeConversion(Context, NVT);
757 : // Avoid multi-step promotion.
758 191655 : if (NextStep.first == TypePromoteInteger)
759 23820 : return NextStep;
760 : // Return rounded integer type.
761 : return LegalizeKind(TypePromoteInteger, NVT);
762 : }
763 :
764 : return LegalizeKind(TypeExpandInteger,
765 170234 : EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
766 : }
767 :
768 : // Handle vector types.
769 : unsigned NumElts = VT.getVectorNumElements();
770 68265 : EVT EltVT = VT.getVectorElementType();
771 :
772 : // Vectors with only one element are always scalarized.
773 68265 : if (NumElts == 1)
774 : return LegalizeKind(TypeScalarizeVector, EltVT);
775 :
776 : // Try to widen vector elements until the element type is a power of two and
777 : // promote it to a legal type later on, for example:
778 : // <3 x i8> -> <4 x i8> -> <4 x i32>
779 57740 : if (EltVT.isInteger()) {
780 : // Vectors with a number of elements that is not a power of two are always
781 : // widened, for example <3 x i8> -> <4 x i8>.
782 40136 : if (!VT.isPow2VectorType()) {
783 26136 : NumElts = (unsigned)NextPowerOf2(NumElts);
784 26136 : EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
785 : return LegalizeKind(TypeWidenVector, NVT);
786 : }
787 :
788 : // Examine the element type.
789 14000 : LegalizeKind LK = getTypeConversion(Context, EltVT);
790 :
791 : // If type is to be expanded, split the vector.
792 : // <4 x i140> -> <2 x i140>
793 14000 : if (LK.first == TypeExpandInteger)
794 : return LegalizeKind(TypeSplitVector,
795 6700 : EVT::getVectorVT(Context, EltVT, NumElts / 2));
796 :
797 : // Promote the integer element types until a legal vector type is found
798 : // or until the element integer type is too big. If a legal type was not
799 : // found, fallback to the usual mechanism of widening/splitting the
800 : // vector.
801 7300 : EVT OldEltVT = EltVT;
802 : while (true) {
803 : // Increase the bitwidth of the element to the next pow-of-two
804 : // (which is greater than 8 bits).
805 18233 : EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
806 18233 : .getRoundIntegerType(Context);
807 :
808 : // Stop trying when getting a non-simple element type.
809 : // Note that vector elements may be greater than legal vector element
810 : // types. Example: X86 XMM registers hold 64bit element on 32bit
811 : // systems.
812 18233 : if (!EltVT.isSimple())
813 : break;
814 :
815 : // Build a new vector type and check if it is legal.
816 14296 : MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
817 : // Found a legal promoted vector type.
818 14296 : if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
819 : return LegalizeKind(TypePromoteInteger,
820 3363 : EVT::getVectorVT(Context, EltVT, NumElts));
821 10933 : }
822 :
823 : // Reset the type to the unexpanded type if we did not find a legal vector
824 : // type with a promoted vector element type.
825 3937 : EltVT = OldEltVT;
826 : }
827 :
828 : // Try to widen the vector until a legal type is found.
829 : // If there is no wider legal type, split the vector.
830 : while (true) {
831 : // Round up to the next power of 2.
832 24518 : NumElts = (unsigned)NextPowerOf2(NumElts);
833 :
834 : // If there is no simple vector type with this many elements then there
835 : // cannot be a larger legal vector type. Note that this assumes that
836 : // there are no skipped intermediate vector types in the simple types.
837 24518 : if (!EltVT.isSimple())
838 : break;
839 24221 : MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
840 24221 : if (LargerVector == MVT())
841 : break;
842 :
843 : // If this type is legal then widen the vector.
844 8738 : if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
845 : return LegalizeKind(TypeWidenVector, LargerVector);
846 : }
847 :
848 : // Widen odd vectors to next power of two.
849 15780 : if (!VT.isPow2VectorType()) {
850 1758 : EVT NVT = VT.getPow2VectorType(Context);
851 : return LegalizeKind(TypeWidenVector, NVT);
852 : }
853 :
854 : // Vectors with illegal element types are expanded.
855 14022 : EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
856 : return LegalizeKind(TypeSplitVector, NVT);
857 : }
858 :
859 0 : static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
860 : unsigned &NumIntermediates,
861 : MVT &RegisterVT,
862 : TargetLoweringBase *TLI) {
863 : // Figure out the right, legal destination reg to copy into.
864 : unsigned NumElts = VT.getVectorNumElements();
865 0 : MVT EltTy = VT.getVectorElementType();
866 :
867 : unsigned NumVectorRegs = 1;
868 :
869 : // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
870 : // could break down into LHS/RHS like LegalizeDAG does.
871 : if (!isPowerOf2_32(NumElts)) {
872 : NumVectorRegs = NumElts;
873 : NumElts = 1;
874 : }
875 :
876 : // Divide the input until we get to a supported size. This will always
877 : // end with a scalar if the target doesn't support vectors.
878 0 : while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
879 0 : NumElts >>= 1;
880 0 : NumVectorRegs <<= 1;
881 : }
882 :
883 0 : NumIntermediates = NumVectorRegs;
884 :
885 0 : MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
886 0 : if (!TLI->isTypeLegal(NewVT))
887 0 : NewVT = EltTy;
888 0 : IntermediateVT = NewVT;
889 :
890 0 : unsigned NewVTSize = NewVT.getSizeInBits();
891 :
892 : // Convert sizes such as i33 to i64.
893 : if (!isPowerOf2_32(NewVTSize))
894 0 : NewVTSize = NextPowerOf2(NewVTSize);
895 :
896 0 : MVT DestVT = TLI->getRegisterType(NewVT);
897 0 : RegisterVT = DestVT;
898 0 : if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
899 0 : return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
900 :
901 : // Otherwise, promotion or legal types use the same number of registers as
902 : // the vector decimated to the appropriate level.
903 : return NumVectorRegs;
904 : }
905 :
906 : /// isLegalRC - Return true if the value types that can be represented by the
907 : /// specified register class are all legal.
908 12982271 : bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
909 : const TargetRegisterClass &RC) const {
910 19258684 : for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
911 14883973 : if (isTypeLegal(*I))
912 8607560 : return true;
913 : return false;
914 : }
915 :
916 : /// Replace/modify any TargetFrameIndex operands with a targte-dependent
917 : /// sequence of memory operands that is recognized by PrologEpilogInserter.
918 : MachineBasicBlock *
919 421 : TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
920 : MachineBasicBlock *MBB) const {
921 : MachineInstr *MI = &InitialMI;
922 : MachineFunction &MF = *MI->getMF();
923 421 : MachineFrameInfo &MFI = MF.getFrameInfo();
924 :
925 : // We're handling multiple types of operands here:
926 : // PATCHPOINT MetaArgs - live-in, read only, direct
927 : // STATEPOINT Deopt Spill - live-through, read only, indirect
928 : // STATEPOINT Deopt Alloca - live-through, read only, direct
929 : // (We're currently conservative and mark the deopt slots read/write in
930 : // practice.)
931 : // STATEPOINT GC Spill - live-through, read/write, indirect
932 : // STATEPOINT GC Alloca - live-through, read/write, direct
933 : // The live-in vs live-through is handled already (the live through ones are
934 : // all stack slots), but we need to handle the different type of stackmap
935 : // operands and memory effects here.
936 :
937 : // MI changes inside this loop as we grow operands.
938 5356 : for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
939 4935 : MachineOperand &MO = MI->getOperand(OperIdx);
940 4935 : if (!MO.isFI())
941 : continue;
942 :
943 : // foldMemoryOperand builds a new MI after replacing a single FI operand
944 : // with the canonical set of five x86 addressing-mode operands.
945 162 : int FI = MO.getIndex();
946 162 : MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
947 :
948 : // Copy operands before the frame-index.
949 3058 : for (unsigned i = 0; i < OperIdx; ++i)
950 2896 : MIB.add(MI->getOperand(i));
951 : // Add frame index operands recognized by stackmaps.cpp
952 162 : if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
953 : // indirect-mem-ref tag, size, #FI, offset.
954 : // Used for spills inserted by StatepointLowering. This codepath is not
955 : // used for patchpoints/stackmaps at all, for these spilling is done via
956 : // foldMemoryOperand callback only.
957 : assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
958 : MIB.addImm(StackMaps::IndirectMemRefOp);
959 : MIB.addImm(MFI.getObjectSize(FI));
960 128 : MIB.add(MI->getOperand(OperIdx));
961 : MIB.addImm(0);
962 : } else {
963 : // direct-mem-ref tag, #FI, offset.
964 : // Used by patchpoint, and direct alloca arguments to statepoints
965 : MIB.addImm(StackMaps::DirectMemRefOp);
966 34 : MIB.add(MI->getOperand(OperIdx));
967 : MIB.addImm(0);
968 : }
969 : // Copy the operands after the frame index.
970 936 : for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
971 774 : MIB.add(MI->getOperand(i));
972 :
973 : // Inherit previous memory operands.
974 : MIB.cloneMemRefs(*MI);
975 : assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
976 :
977 : // Add a new memory operand for this FI.
978 : assert(MFI.getObjectOffset(FI) != -1);
979 :
980 : auto Flags = MachineMemOperand::MOLoad;
981 324 : if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
982 : Flags |= MachineMemOperand::MOStore;
983 : Flags |= MachineMemOperand::MOVolatile;
984 : }
985 162 : MachineMemOperand *MMO = MF.getMachineMemOperand(
986 : MachinePointerInfo::getFixedStack(MF, FI), Flags,
987 162 : MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
988 162 : MIB->addMemOperand(MF, MMO);
989 :
990 : // Replace the instruction and update the operand index.
991 : MBB->insert(MachineBasicBlock::iterator(MI), MIB);
992 162 : OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
993 162 : MI->eraseFromParent();
994 : MI = MIB;
995 : }
996 421 : return MBB;
997 : }
998 :
999 : MachineBasicBlock *
1000 2 : TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI,
1001 : MachineBasicBlock *MBB) const {
1002 : assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1003 : "Called emitXRayCustomEvent on the wrong MI!");
1004 : auto &MF = *MI.getMF();
1005 2 : auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1006 6 : for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1007 4 : MIB.add(MI.getOperand(OpIdx));
1008 :
1009 : MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1010 2 : MI.eraseFromParent();
1011 2 : return MBB;
1012 : }
1013 :
1014 : MachineBasicBlock *
1015 2 : TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI,
1016 : MachineBasicBlock *MBB) const {
1017 : assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1018 : "Called emitXRayTypedEvent on the wrong MI!");
1019 : auto &MF = *MI.getMF();
1020 2 : auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1021 8 : for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1022 6 : MIB.add(MI.getOperand(OpIdx));
1023 :
1024 : MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1025 2 : MI.eraseFromParent();
1026 2 : return MBB;
1027 : }
1028 :
1029 : /// findRepresentativeClass - Return the largest legal super-reg register class
1030 : /// of the register class for the specified type and its associated "cost".
1031 : // This function is in TargetLowering because it uses RegClassForVT which would
1032 : // need to be moved to TargetRegisterInfo and would necessitate moving
1033 : // isTypeLegal over as well - a massive change that would just require
1034 : // TargetLowering having a TargetRegisterInfo class member that it would use.
1035 : std::pair<const TargetRegisterClass *, uint8_t>
1036 4224070 : TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1037 : MVT VT) const {
1038 4224070 : const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1039 4224070 : if (!RC)
1040 4032579 : return std::make_pair(RC, 0);
1041 :
1042 : // Compute the set of all super-register classes.
1043 191491 : BitVector SuperRegRC(TRI->getNumRegClasses());
1044 974826 : for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1045 : SuperRegRC.setBitsInMask(RCI.getMask());
1046 :
1047 : // Find the first legal register class with the largest spill size.
1048 : const TargetRegisterClass *BestRC = RC;
1049 2909347 : for (unsigned i : SuperRegRC.set_bits()) {
1050 2717856 : const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1051 : // We want the largest possible spill size.
1052 2717856 : if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1053 : continue;
1054 2292010 : if (!isLegalRC(*TRI, *SuperRC))
1055 2130752 : continue;
1056 : BestRC = SuperRC;
1057 : }
1058 191491 : return std::make_pair(BestRC, 1);
1059 : }
1060 :
1061 : /// computeRegisterProperties - Once all of the register classes are added,
1062 : /// this allows us to compute derived properties we expose.
1063 41316 : void TargetLoweringBase::computeRegisterProperties(
1064 : const TargetRegisterInfo *TRI) {
1065 : static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1066 : "Too many value types for ValueTypeActions to hold!");
1067 :
1068 : // Everything defaults to needing one register.
1069 4751340 : for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1070 4710024 : NumRegistersForVT[i] = 1;
1071 4710024 : RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1072 : }
1073 : // ...except isVoid, which doesn't need any registers.
1074 41316 : NumRegistersForVT[MVT::isVoid] = 0;
1075 :
1076 : // Find the largest integer register class.
1077 : unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1078 99024 : for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1079 : assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1080 :
1081 : // Every integer value type larger than this largest register takes twice as
1082 : // many registers to represent as the previous ValueType.
1083 99024 : for (unsigned ExpandedReg = LargestIntReg + 1;
1084 99024 : ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1085 57708 : NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1086 57708 : RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1087 57708 : TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1088 : ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1089 : TypeExpandInteger);
1090 : }
1091 :
1092 : // Inspect all of the ValueType's smaller than the largest integer
1093 : // register to see which ones need promotion.
1094 : unsigned LegalIntReg = LargestIntReg;
1095 190188 : for (unsigned IntReg = LargestIntReg - 1;
1096 190188 : IntReg >= (unsigned)MVT::i1; --IntReg) {
1097 148872 : MVT IVT = (MVT::SimpleValueType)IntReg;
1098 : if (isTypeLegal(IVT)) {
1099 : LegalIntReg = IntReg;
1100 : } else {
1101 83625 : RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1102 83625 : (const MVT::SimpleValueType)LegalIntReg;
1103 : ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1104 : }
1105 : }
1106 :
1107 : // ppcf128 type is really two f64's.
1108 : if (!isTypeLegal(MVT::ppcf128)) {
1109 : if (isTypeLegal(MVT::f64)) {
1110 35692 : NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1111 35692 : RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1112 35692 : TransformToType[MVT::ppcf128] = MVT::f64;
1113 : ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1114 : } else {
1115 5624 : NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1116 5624 : RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1117 5624 : TransformToType[MVT::ppcf128] = MVT::i128;
1118 : ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1119 : }
1120 : }
1121 :
1122 : // Decide how to handle f128. If the target does not have native f128 support,
1123 : // expand it to i128 and we will be generating soft float library calls.
1124 : if (!isTypeLegal(MVT::f128)) {
1125 30533 : NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1126 30533 : RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1127 30533 : TransformToType[MVT::f128] = MVT::i128;
1128 : ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1129 : }
1130 :
1131 : // Decide how to handle f64. If the target does not have native f64 support,
1132 : // expand it to i64 and we will be generating soft float library calls.
1133 : if (!isTypeLegal(MVT::f64)) {
1134 5624 : NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1135 5624 : RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1136 5624 : TransformToType[MVT::f64] = MVT::i64;
1137 : ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1138 : }
1139 :
1140 : // Decide how to handle f32. If the target does not have native f32 support,
1141 : // expand it to i32 and we will be generating soft float library calls.
1142 : if (!isTypeLegal(MVT::f32)) {
1143 5307 : NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1144 5307 : RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1145 5307 : TransformToType[MVT::f32] = MVT::i32;
1146 : ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1147 : }
1148 :
1149 : // Decide how to handle f16. If the target does not have native f16 support,
1150 : // promote it to f32, because there are no f16 library calls (except for
1151 : // conversions).
1152 : if (!isTypeLegal(MVT::f16)) {
1153 37064 : NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1154 37064 : RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1155 37064 : TransformToType[MVT::f16] = MVT::f32;
1156 : ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1157 : }
1158 :
1159 : // Loop over all of the vector value types to see which need transformations.
1160 3925019 : for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1161 3966335 : i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1162 3925019 : MVT VT = (MVT::SimpleValueType) i;
1163 : if (isTypeLegal(VT))
1164 226531 : continue;
1165 :
1166 3698488 : MVT EltVT = VT.getVectorElementType();
1167 : unsigned NElts = VT.getVectorNumElements();
1168 : bool IsLegalWiderType = false;
1169 7396976 : LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1170 3698490 : switch (PreferredAction) {
1171 2735767 : case TypePromoteInteger:
1172 : // Try to promote the elements of integer vectors. If no legal
1173 : // promotion was found, fall through to the widen-vector method.
1174 65486218 : for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1175 62939903 : MVT SVT = (MVT::SimpleValueType) nVT;
1176 : // Promote vectors of integers to vectors with the same number
1177 : // of elements, with a wider element type.
1178 104410705 : if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1179 62939902 : SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1180 189451 : TransformToType[i] = SVT;
1181 189451 : RegisterTypeForVT[i] = SVT;
1182 189451 : NumRegistersForVT[i] = 1;
1183 : ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1184 : IsLegalWiderType = true;
1185 189451 : break;
1186 : }
1187 2546315 : }
1188 : if (IsLegalWiderType)
1189 : break;
1190 : LLVM_FALLTHROUGH;
1191 :
1192 : case TypeWidenVector:
1193 : // Try to widen the vector.
1194 122230886 : for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1195 119512977 : MVT SVT = (MVT::SimpleValueType) nVT;
1196 238982580 : if (SVT.getVectorElementType() == EltVT
1197 132268389 : && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1198 43369 : TransformToType[i] = SVT;
1199 43369 : RegisterTypeForVT[i] = SVT;
1200 43369 : NumRegistersForVT[i] = 1;
1201 : ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1202 : IsLegalWiderType = true;
1203 43369 : break;
1204 : }
1205 2717909 : }
1206 : if (IsLegalWiderType)
1207 : break;
1208 : LLVM_FALLTHROUGH;
1209 :
1210 : case TypeSplitVector:
1211 : case TypeScalarizeVector: {
1212 3465664 : MVT IntermediateVT;
1213 3465664 : MVT RegisterVT;
1214 : unsigned NumIntermediates;
1215 3465664 : NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1216 : NumIntermediates, RegisterVT, this);
1217 3465667 : RegisterTypeForVT[i] = RegisterVT;
1218 :
1219 3465667 : MVT NVT = VT.getPow2VectorType();
1220 3465668 : if (NVT == VT) {
1221 : // Type is already a power of 2. The default action is to split.
1222 3465668 : TransformToType[i] = MVT::Other;
1223 3465668 : if (PreferredAction == TypeScalarizeVector)
1224 : ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1225 2892883 : else if (PreferredAction == TypeSplitVector)
1226 : ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1227 : else
1228 : // Set type action according to the number of elements.
1229 2717913 : ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1230 : : TypeSplitVector);
1231 : } else {
1232 0 : TransformToType[i] = NVT;
1233 : ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1234 : }
1235 : break;
1236 : }
1237 0 : default:
1238 0 : llvm_unreachable("Unknown vector legalization action!");
1239 : }
1240 : }
1241 :
1242 : // Determine the 'representative' register class for each value type.
1243 : // An representative register class is the largest (meaning one which is
1244 : // not a sub-register class / subreg register class) legal register class for
1245 : // a group of value types. For example, on i386, i8, i16, and i32
1246 : // representative would be GR32; while on x86_64 it's GR64.
1247 4751285 : for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1248 : const TargetRegisterClass* RRC;
1249 : uint8_t Cost;
1250 9419938 : std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1251 4709969 : RepRegClassForVT[i] = RRC;
1252 4709969 : RepRegClassCostForVT[i] = Cost;
1253 : }
1254 41316 : }
1255 :
1256 2210 : EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1257 : EVT VT) const {
1258 : assert(!VT.isVector() && "No default SetCC type for vectors!");
1259 2210 : return getPointerTy(DL).SimpleTy;
1260 : }
1261 :
1262 330 : MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1263 330 : return MVT::i32; // return the default value
1264 : }
1265 :
1266 : /// getVectorTypeBreakdown - Vector types are broken down into some number of
1267 : /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1268 : /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1269 : /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1270 : ///
1271 : /// This method returns the number of registers needed, and the VT for each
1272 : /// register. It also returns the VT and quantity of the intermediate values
1273 : /// before they are promoted/expanded.
1274 21570 : unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1275 : EVT &IntermediateVT,
1276 : unsigned &NumIntermediates,
1277 : MVT &RegisterVT) const {
1278 : unsigned NumElts = VT.getVectorNumElements();
1279 :
1280 : // If there is a wider vector type with the same element type as this one,
1281 : // or a promoted vector type that has the same number of elements which
1282 : // are wider, then we should convert to that legal vector type.
1283 : // This handles things like <2 x float> -> <4 x float> and
1284 : // <4 x i1> -> <4 x i32>.
1285 21570 : LegalizeTypeAction TA = getTypeAction(Context, VT);
1286 21570 : if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1287 4386 : EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1288 : if (isTypeLegal(RegisterEVT)) {
1289 2107 : IntermediateVT = RegisterEVT;
1290 2107 : RegisterVT = RegisterEVT.getSimpleVT();
1291 2107 : NumIntermediates = 1;
1292 2107 : return 1;
1293 : }
1294 : }
1295 :
1296 : // Figure out the right, legal destination reg to copy into.
1297 19463 : EVT EltTy = VT.getVectorElementType();
1298 :
1299 : unsigned NumVectorRegs = 1;
1300 :
1301 : // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1302 : // could break down into LHS/RHS like LegalizeDAG does.
1303 : if (!isPowerOf2_32(NumElts)) {
1304 : NumVectorRegs = NumElts;
1305 : NumElts = 1;
1306 : }
1307 :
1308 : // Divide the input until we get to a supported size. This will always
1309 : // end with a scalar if the target doesn't support vectors.
1310 42621 : while (NumElts > 1 && !isTypeLegal(
1311 : EVT::getVectorVT(Context, EltTy, NumElts))) {
1312 23158 : NumElts >>= 1;
1313 23158 : NumVectorRegs <<= 1;
1314 : }
1315 :
1316 19463 : NumIntermediates = NumVectorRegs;
1317 :
1318 19463 : EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1319 19463 : if (!isTypeLegal(NewVT))
1320 6330 : NewVT = EltTy;
1321 19463 : IntermediateVT = NewVT;
1322 :
1323 19463 : MVT DestVT = getRegisterType(Context, NewVT);
1324 19463 : RegisterVT = DestVT;
1325 19463 : unsigned NewVTSize = NewVT.getSizeInBits();
1326 :
1327 : // Convert sizes such as i33 to i64.
1328 : if (!isPowerOf2_32(NewVTSize))
1329 226 : NewVTSize = NextPowerOf2(NewVTSize);
1330 :
1331 19463 : if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1332 1646 : return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1333 :
1334 : // Otherwise, promotion or legal types use the same number of registers as
1335 : // the vector decimated to the appropriate level.
1336 : return NumVectorRegs;
1337 : }
1338 :
1339 : /// Get the EVTs and ArgFlags collections that represent the legalized return
1340 : /// type of the given function. This does not require a DAG or a return value,
1341 : /// and is suitable for use before any DAGs for the function are constructed.
1342 : /// TODO: Move this out of TargetLowering.cpp.
1343 2656241 : void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1344 : AttributeList attr,
1345 : SmallVectorImpl<ISD::OutputArg> &Outs,
1346 : const TargetLowering &TLI, const DataLayout &DL) {
1347 : SmallVector<EVT, 4> ValueVTs;
1348 2656241 : ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1349 2656241 : unsigned NumValues = ValueVTs.size();
1350 2656241 : if (NumValues == 0) return;
1351 :
1352 2014072 : for (unsigned j = 0, f = NumValues; j != f; ++j) {
1353 1014501 : EVT VT = ValueVTs[j];
1354 : ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1355 :
1356 1014501 : if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1357 : ExtendKind = ISD::SIGN_EXTEND;
1358 1003145 : else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1359 : ExtendKind = ISD::ZERO_EXTEND;
1360 :
1361 : // FIXME: C calling convention requires the return type to be promoted to
1362 : // at least 32-bit. But this is not necessary for non-C calling
1363 : // conventions. The frontend should mark functions whose return values
1364 : // require promoting with signext or zeroext attributes.
1365 135580 : if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1366 261472 : MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1367 130736 : if (VT.bitsLT(MinVT))
1368 122582 : VT = MinVT;
1369 : }
1370 :
1371 : unsigned NumParts =
1372 1014501 : TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1373 : MVT PartVT =
1374 1014501 : TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1375 :
1376 : // 'inreg' on function refers to return value
1377 : ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1378 1014501 : if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1379 : Flags.setInReg();
1380 :
1381 : // Propagate extension type if any
1382 1014501 : if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1383 : Flags.setSExt();
1384 1003145 : else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1385 : Flags.setZExt();
1386 :
1387 2052666 : for (unsigned i = 0; i < NumParts; ++i)
1388 2076330 : Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1389 : }
1390 : }
1391 :
1392 : /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1393 : /// function arguments in the caller parameter area. This is the actual
1394 : /// alignment, not its logarithm.
1395 521 : unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1396 : const DataLayout &DL) const {
1397 521 : return DL.getABITypeAlignment(Ty);
1398 : }
1399 :
1400 11253832 : bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1401 : const DataLayout &DL, EVT VT,
1402 : unsigned AddrSpace,
1403 : unsigned Alignment,
1404 : bool *Fast) const {
1405 : // Check if the specified alignment is sufficient based on the data layout.
1406 : // TODO: While using the data layout works in practice, a better solution
1407 : // would be to implement this check directly (make this a virtual function).
1408 : // For example, the ABI alignment may change based on software platform while
1409 : // this function should only be affected by hardware implementation.
1410 11253832 : Type *Ty = VT.getTypeForEVT(Context);
1411 11253832 : if (Alignment >= DL.getABITypeAlignment(Ty)) {
1412 : // Assume that an access that meets the ABI-specified alignment is fast.
1413 10535694 : if (Fast != nullptr)
1414 155954 : *Fast = true;
1415 10535694 : return true;
1416 : }
1417 :
1418 : // This is a misaligned access.
1419 718138 : return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1420 : }
1421 :
1422 8 : BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1423 8 : return BranchProbability(MinPercentageForPredictableBranch, 100);
1424 : }
1425 :
1426 : //===----------------------------------------------------------------------===//
1427 : // TargetTransformInfo Helpers
1428 : //===----------------------------------------------------------------------===//
1429 :
1430 449427 : int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1431 : enum InstructionOpcodes {
1432 : #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1433 : #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1434 : #include "llvm/IR/Instruction.def"
1435 : };
1436 : switch (static_cast<InstructionOpcodes>(Opcode)) {
1437 : case Ret: return 0;
1438 : case Br: return 0;
1439 : case Switch: return 0;
1440 : case IndirectBr: return 0;
1441 : case Invoke: return 0;
1442 : case Resume: return 0;
1443 : case Unreachable: return 0;
1444 : case CleanupRet: return 0;
1445 : case CatchRet: return 0;
1446 : case CatchPad: return 0;
1447 : case CatchSwitch: return 0;
1448 : case CleanupPad: return 0;
1449 : case Add: return ISD::ADD;
1450 : case FAdd: return ISD::FADD;
1451 : case Sub: return ISD::SUB;
1452 : case FSub: return ISD::FSUB;
1453 : case Mul: return ISD::MUL;
1454 : case FMul: return ISD::FMUL;
1455 : case UDiv: return ISD::UDIV;
1456 : case SDiv: return ISD::SDIV;
1457 : case FDiv: return ISD::FDIV;
1458 : case URem: return ISD::UREM;
1459 : case SRem: return ISD::SREM;
1460 : case FRem: return ISD::FREM;
1461 : case Shl: return ISD::SHL;
1462 : case LShr: return ISD::SRL;
1463 : case AShr: return ISD::SRA;
1464 : case And: return ISD::AND;
1465 : case Or: return ISD::OR;
1466 : case Xor: return ISD::XOR;
1467 : case Alloca: return 0;
1468 : case Load: return ISD::LOAD;
1469 : case Store: return ISD::STORE;
1470 : case GetElementPtr: return 0;
1471 : case Fence: return 0;
1472 : case AtomicCmpXchg: return 0;
1473 : case AtomicRMW: return 0;
1474 : case Trunc: return ISD::TRUNCATE;
1475 : case ZExt: return ISD::ZERO_EXTEND;
1476 : case SExt: return ISD::SIGN_EXTEND;
1477 : case FPToUI: return ISD::FP_TO_UINT;
1478 : case FPToSI: return ISD::FP_TO_SINT;
1479 : case UIToFP: return ISD::UINT_TO_FP;
1480 : case SIToFP: return ISD::SINT_TO_FP;
1481 : case FPTrunc: return ISD::FP_ROUND;
1482 : case FPExt: return ISD::FP_EXTEND;
1483 : case PtrToInt: return ISD::BITCAST;
1484 : case IntToPtr: return ISD::BITCAST;
1485 : case BitCast: return ISD::BITCAST;
1486 : case AddrSpaceCast: return ISD::ADDRSPACECAST;
1487 : case ICmp: return ISD::SETCC;
1488 : case FCmp: return ISD::SETCC;
1489 : case PHI: return 0;
1490 : case Call: return 0;
1491 : case Select: return ISD::SELECT;
1492 : case UserOp1: return 0;
1493 : case UserOp2: return 0;
1494 : case VAArg: return 0;
1495 : case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1496 : case InsertElement: return ISD::INSERT_VECTOR_ELT;
1497 : case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1498 : case ExtractValue: return ISD::MERGE_VALUES;
1499 : case InsertValue: return ISD::MERGE_VALUES;
1500 : case LandingPad: return 0;
1501 : }
1502 :
1503 0 : llvm_unreachable("Unknown instruction type encountered!");
1504 : }
1505 :
1506 : std::pair<int, MVT>
1507 1176765 : TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1508 : Type *Ty) const {
1509 1176765 : LLVMContext &C = Ty->getContext();
1510 1176765 : EVT MTy = getValueType(DL, Ty);
1511 :
1512 : int Cost = 1;
1513 : // We keep legalizing the type until we find a legal kind. We assume that
1514 : // the only operation that costs anything is the split. After splitting
1515 : // we need to handle two types.
1516 : while (true) {
1517 1456095 : LegalizeKind LK = getTypeConversion(C, MTy);
1518 :
1519 1456095 : if (LK.first == TypeLegal)
1520 : return std::make_pair(Cost, MTy.getSimpleVT());
1521 :
1522 279330 : if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1523 257659 : Cost *= 2;
1524 :
1525 : // Do not loop with f128 type.
1526 265 : if (MTy == LK.second)
1527 : return std::make_pair(Cost, MTy.getSimpleVT());
1528 :
1529 : // Keep legalizing the type.
1530 279330 : MTy = LK.second;
1531 279330 : }
1532 : }
1533 :
1534 141 : Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1535 : bool UseTLS) const {
1536 : // compiler-rt provides a variable with a magic name. Targets that do not
1537 : // link with compiler-rt may also provide such a variable.
1538 141 : Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1539 : const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1540 : auto UnsafeStackPtr =
1541 141 : dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1542 :
1543 141 : Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1544 :
1545 141 : if (!UnsafeStackPtr) {
1546 80 : auto TLSModel = UseTLS ?
1547 : GlobalValue::InitialExecTLSModel :
1548 : GlobalValue::NotThreadLocal;
1549 : // The global variable is not defined yet, define it ourselves.
1550 : // We use the initial-exec TLS model because we do not support the
1551 : // variable living anywhere other than in the main executable.
1552 80 : UnsafeStackPtr = new GlobalVariable(
1553 : *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1554 80 : UnsafeStackPtrVar, nullptr, TLSModel);
1555 : } else {
1556 : // The variable exists, check its type and attributes.
1557 61 : if (UnsafeStackPtr->getValueType() != StackPtrTy)
1558 0 : report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1559 61 : if (UseTLS != UnsafeStackPtr->isThreadLocal())
1560 0 : report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1561 0 : (UseTLS ? "" : "not ") + "be thread-local");
1562 : }
1563 141 : return UnsafeStackPtr;
1564 : }
1565 :
1566 139 : Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1567 278 : if (!TM.getTargetTriple().isAndroid())
1568 137 : return getDefaultSafeStackPointerLocation(IRB, true);
1569 :
1570 : // Android provides a libc function to retrieve the address of the current
1571 : // thread's unsafe stack pointer.
1572 2 : Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1573 2 : Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1574 2 : Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1575 2 : StackPtrTy->getPointerTo(0));
1576 2 : return IRB.CreateCall(Fn);
1577 : }
1578 :
1579 : //===----------------------------------------------------------------------===//
1580 : // Loop Strength Reduction hooks
1581 : //===----------------------------------------------------------------------===//
1582 :
1583 : /// isLegalAddressingMode - Return true if the addressing mode represented
1584 : /// by AM is legal for this target, for a load/store of the specified type.
1585 13024 : bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1586 : const AddrMode &AM, Type *Ty,
1587 : unsigned AS, Instruction *I) const {
1588 : // The default implementation of this implements a conservative RISCy, r+r and
1589 : // r+i addr mode.
1590 :
1591 : // Allows a sign-extended 16-bit immediate field.
1592 13024 : if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1593 : return false;
1594 :
1595 : // No global is ever allowed as a base.
1596 13018 : if (AM.BaseGV)
1597 : return false;
1598 :
1599 : // Only support r+r,
1600 11722 : switch (AM.Scale) {
1601 : case 0: // "r+i" or just "i", depending on HasBaseReg.
1602 : break;
1603 756 : case 1:
1604 756 : if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1605 : return false;
1606 : // Otherwise we have r+r or r+i.
1607 : break;
1608 170 : case 2:
1609 170 : if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1610 : return false;
1611 : // Allow 2*r as r+r.
1612 : break;
1613 : default: // Don't allow n * r
1614 : return false;
1615 : }
1616 :
1617 9668 : return true;
1618 : }
1619 :
1620 : //===----------------------------------------------------------------------===//
1621 : // Stack Protector
1622 : //===----------------------------------------------------------------------===//
1623 :
1624 : // For OpenBSD return its special guard variable. Otherwise return nullptr,
1625 : // so that SelectionDAG handle SSP.
1626 476 : Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1627 952 : if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1628 120 : Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1629 120 : PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1630 120 : return M.getOrInsertGlobal("__guard_local", PtrTy);
1631 : }
1632 : return nullptr;
1633 : }
1634 :
1635 : // Currently only support "standard" __stack_chk_guard.
1636 : // TODO: add LOAD_STACK_GUARD support.
1637 270 : void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1638 270 : if (!M.getNamedValue("__stack_chk_guard"))
1639 172 : new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1640 : GlobalVariable::ExternalLinkage,
1641 86 : nullptr, "__stack_chk_guard");
1642 270 : }
1643 :
1644 : // Currently only support "standard" __stack_chk_guard.
1645 : // TODO: add LOAD_STACK_GUARD support.
1646 677 : Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
1647 677 : return M.getNamedValue("__stack_chk_guard");
1648 : }
1649 :
1650 1472 : Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1651 1472 : return nullptr;
1652 : }
1653 :
1654 19153 : unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1655 19153 : return MinimumJumpTableEntries;
1656 : }
1657 :
1658 1137 : void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1659 : MinimumJumpTableEntries = Val;
1660 1137 : }
1661 :
1662 11300 : unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1663 11300 : return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1664 : }
1665 :
1666 11747 : unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1667 11747 : return MaximumJumpTableSize;
1668 : }
1669 :
1670 37 : void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1671 : MaximumJumpTableSize = Val;
1672 37 : }
1673 :
1674 : //===----------------------------------------------------------------------===//
1675 : // Reciprocal Estimates
1676 : //===----------------------------------------------------------------------===//
1677 :
1678 : /// Get the reciprocal estimate attribute string for a function that will
1679 : /// override the target defaults.
1680 2303 : static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1681 2303 : const Function &F = MF.getFunction();
1682 2303 : return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1683 : }
1684 :
1685 : /// Construct a string for the given reciprocal operation of the given type.
1686 : /// This string should match the corresponding option to the front-end's
1687 : /// "-mrecip" flag assuming those strings have been passed through in an
1688 : /// attribute string. For example, "vec-divf" for a division of a vXf32.
1689 1019 : static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1690 1224 : std::string Name = VT.isVector() ? "vec-" : "";
1691 :
1692 1019 : Name += IsSqrt ? "sqrt" : "div";
1693 :
1694 : // TODO: Handle "half" or other float types?
1695 2038 : if (VT.getScalarType() == MVT::f64) {
1696 : Name += "d";
1697 : } else {
1698 : assert(VT.getScalarType() == MVT::f32 &&
1699 : "Unexpected FP type for reciprocal estimate");
1700 : Name += "f";
1701 : }
1702 :
1703 1019 : return Name;
1704 : }
1705 :
1706 : /// Return the character position and value (a single numeric character) of a
1707 : /// customized refinement operation in the input string if it exists. Return
1708 : /// false if there is no customized refinement step count.
1709 1987 : static bool parseRefinementStep(StringRef In, size_t &Position,
1710 : uint8_t &Value) {
1711 : const char RefStepToken = ':';
1712 1987 : Position = In.find(RefStepToken);
1713 1987 : if (Position == StringRef::npos)
1714 : return false;
1715 :
1716 772 : StringRef RefStepString = In.substr(Position + 1);
1717 : // Allow exactly one numeric character for the additional refinement
1718 : // step parameter.
1719 772 : if (RefStepString.size() == 1) {
1720 : char RefStepChar = RefStepString[0];
1721 772 : if (RefStepChar >= '0' && RefStepChar <= '9') {
1722 772 : Value = RefStepChar - '0';
1723 772 : return true;
1724 : }
1725 : }
1726 0 : report_fatal_error("Invalid refinement step for -recip.");
1727 : }
1728 :
1729 : /// For the input attribute string, return one of the ReciprocalEstimate enum
1730 : /// status values (enabled, disabled, or not specified) for this operation on
1731 : /// the specified data type.
1732 1210 : static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1733 1210 : if (Override.empty())
1734 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1735 :
1736 : SmallVector<StringRef, 4> OverrideVector;
1737 568 : Override.split(OverrideVector, ',');
1738 568 : unsigned NumArgs = OverrideVector.size();
1739 :
1740 : // Check if "all", "none", or "default" was specified.
1741 568 : if (NumArgs == 1) {
1742 : // Look for an optional setting of the number of refinement steps needed
1743 : // for this type of reciprocal operation.
1744 : size_t RefPos;
1745 : uint8_t RefSteps;
1746 2 : if (parseRefinementStep(Override, RefPos, RefSteps)) {
1747 : // Split the string for further processing.
1748 2 : Override = Override.substr(0, RefPos);
1749 : }
1750 :
1751 : // All reciprocal types are enabled.
1752 : if (Override == "all")
1753 0 : return TargetLoweringBase::ReciprocalEstimate::Enabled;
1754 :
1755 : // All reciprocal types are disabled.
1756 : if (Override == "none")
1757 : return TargetLoweringBase::ReciprocalEstimate::Disabled;
1758 :
1759 : // Target defaults for enablement are used.
1760 : if (Override == "default")
1761 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1762 : }
1763 :
1764 : // The attribute string may omit the size suffix ('f'/'d').
1765 568 : std::string VTName = getReciprocalOpName(IsSqrt, VT);
1766 : std::string VTNameNoSize = VTName;
1767 : VTNameNoSize.pop_back();
1768 : static const char DisabledPrefix = '!';
1769 :
1770 1099 : for (StringRef RecipType : OverrideVector) {
1771 : size_t RefPos;
1772 : uint8_t RefSteps;
1773 1093 : if (parseRefinementStep(RecipType, RefPos, RefSteps))
1774 384 : RecipType = RecipType.substr(0, RefPos);
1775 :
1776 : // Ignore the disablement token for string matching.
1777 1093 : bool IsDisabled = RecipType[0] == DisabledPrefix;
1778 1093 : if (IsDisabled)
1779 265 : RecipType = RecipType.substr(1);
1780 :
1781 : if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1782 562 : return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1783 562 : : TargetLoweringBase::ReciprocalEstimate::Enabled;
1784 : }
1785 :
1786 6 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1787 : }
1788 :
1789 : /// For the input attribute string, return the customized refinement step count
1790 : /// for this operation on the specified data type. If the step count does not
1791 : /// exist, return the ReciprocalEstimate enum value for unspecified.
1792 1093 : static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1793 1093 : if (Override.empty())
1794 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1795 :
1796 : SmallVector<StringRef, 4> OverrideVector;
1797 451 : Override.split(OverrideVector, ',');
1798 451 : unsigned NumArgs = OverrideVector.size();
1799 :
1800 : // Check if "all", "default", or "none" was specified.
1801 451 : if (NumArgs == 1) {
1802 : // Look for an optional setting of the number of refinement steps needed
1803 : // for this type of reciprocal operation.
1804 : size_t RefPos;
1805 : uint8_t RefSteps;
1806 2 : if (!parseRefinementStep(Override, RefPos, RefSteps))
1807 0 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1808 :
1809 : // Split the string for further processing.
1810 2 : Override = Override.substr(0, RefPos);
1811 : assert(Override != "none" &&
1812 : "Disabled reciprocals, but specifed refinement steps?");
1813 :
1814 : // If this is a general override, return the specified number of steps.
1815 : if (Override == "all" || Override == "default")
1816 0 : return RefSteps;
1817 : }
1818 :
1819 : // The attribute string may omit the size suffix ('f'/'d').
1820 451 : std::string VTName = getReciprocalOpName(IsSqrt, VT);
1821 : std::string VTNameNoSize = VTName;
1822 : VTNameNoSize.pop_back();
1823 :
1824 1140 : for (StringRef RecipType : OverrideVector) {
1825 : size_t RefPos;
1826 : uint8_t RefSteps;
1827 890 : if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1828 506 : continue;
1829 :
1830 384 : RecipType = RecipType.substr(0, RefPos);
1831 : if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1832 201 : return RefSteps;
1833 : }
1834 :
1835 250 : return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1836 : }
1837 :
1838 251 : int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
1839 : MachineFunction &MF) const {
1840 251 : return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1841 : }
1842 :
1843 959 : int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
1844 : MachineFunction &MF) const {
1845 959 : return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1846 : }
1847 :
1848 208 : int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
1849 : MachineFunction &MF) const {
1850 208 : return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1851 : }
1852 :
1853 885 : int TargetLoweringBase::getDivRefinementSteps(EVT VT,
1854 : MachineFunction &MF) const {
1855 885 : return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1856 : }
1857 :
1858 407077 : void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
1859 407077 : MF.getRegInfo().freezeReservedRegs(MF);
1860 407077 : }
|
