Line data Source code
1 : //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file This file describes the general parts of a Subtarget.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
15 : #include "llvm/ADT/Optional.h"
16 : #include "llvm/CodeGen/MachineInstr.h"
17 : #include "llvm/CodeGen/TargetInstrInfo.h"
18 : #include "llvm/CodeGen/TargetSchedule.h"
19 : #include "llvm/MC/MCInst.h"
20 : #include "llvm/Support/Format.h"
21 : #include "llvm/Support/raw_ostream.h"
22 : #include <string>
23 :
24 : using namespace llvm;
25 :
26 43981 : TargetSubtargetInfo::TargetSubtargetInfo(
27 : const Triple &TT, StringRef CPU, StringRef FS,
28 : ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
29 : const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
30 : const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
31 43981 : const InstrStage *IS, const unsigned *OC, const unsigned *FP)
32 43981 : : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
33 43981 : }
34 :
35 : TargetSubtargetInfo::~TargetSubtargetInfo() = default;
36 :
37 382167 : bool TargetSubtargetInfo::enableAtomicExpand() const {
38 382167 : return true;
39 : }
40 :
41 0 : bool TargetSubtargetInfo::enableIndirectBrExpand() const {
42 0 : return false;
43 : }
44 :
45 44794 : bool TargetSubtargetInfo::enableMachineScheduler() const {
46 44794 : return false;
47 : }
48 :
49 197926 : bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
50 197926 : return enableMachineScheduler();
51 : }
52 :
53 193768 : bool TargetSubtargetInfo::enableRALocalReassignment(
54 : CodeGenOpt::Level OptLevel) const {
55 193768 : return true;
56 : }
57 :
58 82173 : bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
59 82173 : return false;
60 : }
61 :
62 142012 : bool TargetSubtargetInfo::enablePostRAScheduler() const {
63 142012 : return getSchedModel().PostRAScheduler;
64 : }
65 :
66 2778156 : bool TargetSubtargetInfo::useAA() const {
67 2778156 : return false;
68 : }
69 :
70 60869 : static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
71 : static const char *SchedPrefix = " sched: [";
72 : std::string Comment;
73 60869 : raw_string_ostream CS(Comment);
74 60869 : if (RThroughput != 0.0)
75 182607 : CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
76 60869 : << "]";
77 : else
78 0 : CS << SchedPrefix << Latency << ":?]";
79 : CS.flush();
80 60869 : return Comment;
81 : }
82 :
83 : /// Returns string representation of scheduler comment
84 8 : std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
85 16 : if (MI.isPseudo() || MI.isTerminator())
86 : return std::string();
87 : // We don't cache TSchedModel because it depends on TargetInstrInfo
88 : // that could be changed during the compilation
89 8 : TargetSchedModel TSchedModel;
90 8 : TSchedModel.init(this);
91 8 : unsigned Latency = TSchedModel.computeInstrLatency(&MI);
92 8 : double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
93 8 : return createSchedInfoStr(Latency, RThroughput);
94 : }
95 :
96 : /// Returns string representation of scheduler comment
97 63580 : std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
98 : // We don't cache TSchedModel because it depends on TargetInstrInfo
99 : // that could be changed during the compilation
100 63580 : TargetSchedModel TSchedModel;
101 63580 : TSchedModel.init(this);
102 : unsigned Latency;
103 63580 : if (TSchedModel.hasInstrSchedModel())
104 60861 : Latency = TSchedModel.computeInstrLatency(MCI);
105 2719 : else if (TSchedModel.hasInstrItineraries()) {
106 : auto *ItinData = TSchedModel.getInstrItineraries();
107 0 : Latency = ItinData->getStageLatency(
108 0 : getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
109 : } else
110 : return std::string();
111 60861 : double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
112 60861 : return createSchedInfoStr(Latency, RThroughput);
113 : }
114 :
115 3561 : void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
116 3561 : }
|