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       1             : //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// Contains the definition of a TargetInstrInfo class that is common
      12             : /// to all AMD GPUs.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
      17             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
      18             : 
      19             : #include "AMDGPU.h"
      20             : #include "Utils/AMDGPUBaseInfo.h"
      21             : #include "llvm/CodeGen/TargetInstrInfo.h"
      22             : 
      23             : #define GET_INSTRINFO_HEADER
      24             : #include "AMDGPUGenInstrInfo.inc"
      25             : #undef GET_INSTRINFO_HEADER
      26             : 
      27             : namespace llvm {
      28             : 
      29             : class AMDGPUSubtarget;
      30             : class MachineFunction;
      31             : class MachineInstr;
      32             : class MachineInstrBuilder;
      33             : 
      34           0 : class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
      35             : private:
      36             :   const AMDGPUSubtarget &ST;
      37             : 
      38             :   virtual void anchor();
      39             : protected:
      40             :   AMDGPUAS AMDGPUASI;
      41             : 
      42             : public:
      43             :   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
      44             : 
      45             :   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
      46             :                                int64_t Offset1, int64_t Offset2,
      47             :                                unsigned NumLoads) const override;
      48             : 
      49             :   /// Return a target-specific opcode if Opcode is a pseudo instruction.
      50             :   /// Return -1 if the target-specific opcode for the pseudo instruction does
      51             :   /// not exist. If Opcode is not a pseudo instruction, this is identity.
      52             :   int pseudoToMCOpcode(int Opcode) const;
      53             : 
      54             :   static bool isUniformMMO(const MachineMemOperand *MMO);
      55             : };
      56             : 
      57             : namespace AMDGPU {
      58             : 
      59             : struct RsrcIntrinsic {
      60             :   unsigned Intr;
      61             :   uint8_t RsrcArg;
      62             :   bool IsImage;
      63             : };
      64             : const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
      65             : 
      66             : struct D16ImageDimIntrinsic {
      67             :   unsigned Intr;
      68             :   unsigned D16HelperIntr;
      69             : };
      70             : const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
      71             : 
      72             : struct ImageDimIntrinsicInfo {
      73             :   unsigned Intr;
      74             :   unsigned BaseOpcode;
      75             :   MIMGDim Dim;
      76             : };
      77             : const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
      78             : 
      79             : } // end AMDGPU namespace
      80             : } // End llvm namespace
      81             : 
      82             : #endif