Line data Source code
1 : //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file
11 : ///
12 : /// This file contains declaration for AMDGPU ISA disassembler
13 : //
14 : //===----------------------------------------------------------------------===//
15 :
16 : #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 : #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 :
19 : #include "llvm/ADT/ArrayRef.h"
20 : #include "llvm/MC/MCContext.h"
21 : #include "llvm/MC/MCInstrInfo.h"
22 : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
23 : #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
24 : #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
25 :
26 : #include <algorithm>
27 : #include <cstdint>
28 : #include <memory>
29 :
30 : namespace llvm {
31 :
32 : class MCInst;
33 : class MCOperand;
34 : class MCSubtargetInfo;
35 : class Twine;
36 :
37 : //===----------------------------------------------------------------------===//
38 : // AMDGPUDisassembler
39 : //===----------------------------------------------------------------------===//
40 :
41 : class AMDGPUDisassembler : public MCDisassembler {
42 : private:
43 : std::unique_ptr<MCInstrInfo const> const MCII;
44 : const MCRegisterInfo &MRI;
45 : mutable ArrayRef<uint8_t> Bytes;
46 : mutable uint32_t Literal;
47 : mutable bool HasLiteral;
48 :
49 : public:
50 : AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51 56 : MCInstrInfo const *MCII) :
52 112 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()) {}
53 :
54 165 : ~AMDGPUDisassembler() override = default;
55 :
56 : DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
57 : ArrayRef<uint8_t> Bytes, uint64_t Address,
58 : raw_ostream &WS, raw_ostream &CS) const override;
59 :
60 : const char* getRegClassName(unsigned RegClassID) const;
61 :
62 : MCOperand createRegOperand(unsigned int RegId) const;
63 : MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
64 : MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
65 :
66 : MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
67 :
68 : DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
69 : uint64_t Address) const;
70 :
71 : DecodeStatus convertSDWAInst(MCInst &MI) const;
72 : DecodeStatus convertMIMGInst(MCInst &MI) const;
73 :
74 : MCOperand decodeOperand_VGPR_32(unsigned Val) const;
75 : MCOperand decodeOperand_VS_32(unsigned Val) const;
76 : MCOperand decodeOperand_VS_64(unsigned Val) const;
77 : MCOperand decodeOperand_VS_128(unsigned Val) const;
78 : MCOperand decodeOperand_VSrc16(unsigned Val) const;
79 : MCOperand decodeOperand_VSrcV216(unsigned Val) const;
80 :
81 : MCOperand decodeOperand_VReg_64(unsigned Val) const;
82 : MCOperand decodeOperand_VReg_96(unsigned Val) const;
83 : MCOperand decodeOperand_VReg_128(unsigned Val) const;
84 :
85 : MCOperand decodeOperand_SReg_32(unsigned Val) const;
86 : MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
87 : MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
88 : MCOperand decodeOperand_SReg_64(unsigned Val) const;
89 : MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
90 : MCOperand decodeOperand_SReg_128(unsigned Val) const;
91 : MCOperand decodeOperand_SReg_256(unsigned Val) const;
92 : MCOperand decodeOperand_SReg_512(unsigned Val) const;
93 :
94 : enum OpWidthTy {
95 : OPW32,
96 : OPW64,
97 : OPW128,
98 : OPW256,
99 : OPW512,
100 : OPW16,
101 : OPWV216,
102 : OPW_LAST_,
103 : OPW_FIRST_ = OPW32
104 : };
105 :
106 : unsigned getVgprClassId(const OpWidthTy Width) const;
107 : unsigned getSgprClassId(const OpWidthTy Width) const;
108 : unsigned getTtmpClassId(const OpWidthTy Width) const;
109 :
110 : static MCOperand decodeIntImmed(unsigned Imm);
111 : static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
112 : MCOperand decodeLiteralConstant() const;
113 :
114 : MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
115 : MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
116 : MCOperand decodeSpecialReg32(unsigned Val) const;
117 : MCOperand decodeSpecialReg64(unsigned Val) const;
118 :
119 : MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
120 : MCOperand decodeSDWASrc16(unsigned Val) const;
121 : MCOperand decodeSDWASrc32(unsigned Val) const;
122 : MCOperand decodeSDWAVopcDst(unsigned Val) const;
123 :
124 : int getTTmpIdx(unsigned Val) const;
125 :
126 : bool isVI() const;
127 : bool isGFX9() const;
128 : };
129 :
130 : //===----------------------------------------------------------------------===//
131 : // AMDGPUSymbolizer
132 : //===----------------------------------------------------------------------===//
133 :
134 : class AMDGPUSymbolizer : public MCSymbolizer {
135 : private:
136 : void *DisInfo;
137 :
138 : public:
139 : AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
140 : void *disInfo)
141 16 : : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
142 :
143 : bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
144 : int64_t Value, uint64_t Address,
145 : bool IsBranch, uint64_t Offset,
146 : uint64_t InstSize) override;
147 :
148 : void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
149 : int64_t Value,
150 : uint64_t Address) override;
151 : };
152 :
153 : } // end namespace llvm
154 :
155 : #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
