Line data Source code
1 : //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file provides AMDGPU specific target streamer methods.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "AMDGPUTargetStreamer.h"
15 : #include "AMDGPU.h"
16 : #include "SIDefines.h"
17 : #include "Utils/AMDGPUBaseInfo.h"
18 : #include "Utils/AMDKernelCodeTUtils.h"
19 : #include "llvm/ADT/Twine.h"
20 : #include "llvm/BinaryFormat/ELF.h"
21 : #include "llvm/IR/Constants.h"
22 : #include "llvm/IR/Function.h"
23 : #include "llvm/IR/Metadata.h"
24 : #include "llvm/IR/Module.h"
25 : #include "llvm/MC/MCContext.h"
26 : #include "llvm/MC/MCELFStreamer.h"
27 : #include "llvm/MC/MCObjectFileInfo.h"
28 : #include "llvm/MC/MCSectionELF.h"
29 : #include "llvm/Support/FormattedStream.h"
30 : #include "llvm/Support/TargetParser.h"
31 :
32 : namespace llvm {
33 : #include "AMDGPUPTNote.h"
34 : }
35 :
36 : using namespace llvm;
37 : using namespace llvm::AMDGPU;
38 :
39 : //===----------------------------------------------------------------------===//
40 : // AMDGPUTargetStreamer
41 : //===----------------------------------------------------------------------===//
42 :
43 22 : bool AMDGPUTargetStreamer::EmitHSAMetadata(StringRef HSAMetadataString) {
44 22 : HSAMD::Metadata HSAMetadata;
45 44 : if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
46 : return false;
47 :
48 16 : return EmitHSAMetadata(HSAMetadata);
49 : }
50 :
51 0 : StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
52 : AMDGPU::GPUKind AK;
53 :
54 0 : switch (ElfMach) {
55 0 : case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
56 0 : case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
57 0 : case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
58 0 : case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
59 0 : case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
60 0 : case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
61 0 : case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
62 0 : case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
63 0 : case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
64 0 : case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
65 0 : case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
66 0 : case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
67 0 : case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
68 0 : case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
69 0 : case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
70 0 : case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
71 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
72 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
73 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
74 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
75 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
76 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
77 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
78 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
79 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
80 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
81 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
82 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
83 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
84 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
85 0 : case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
86 0 : case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
87 : }
88 :
89 0 : StringRef GPUName = getArchNameAMDGCN(AK);
90 : if (GPUName != "")
91 0 : return GPUName;
92 0 : return getArchNameR600(AK);
93 : }
94 :
95 144 : unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
96 144 : AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
97 144 : if (AK == AMDGPU::GPUKind::GK_NONE)
98 32 : AK = parseArchR600(GPU);
99 :
100 144 : switch (AK) {
101 : case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
102 1 : case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
103 1 : case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
104 1 : case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
105 1 : case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
106 1 : case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
107 1 : case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
108 1 : case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
109 3 : case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
110 1 : case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
111 2 : case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
112 1 : case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
113 1 : case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
114 1 : case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
115 1 : case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
116 1 : case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
117 3 : case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
118 6 : case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
119 22 : case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
120 2 : case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
121 1 : case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
122 3 : case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
123 2 : case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
124 16 : case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
125 18 : case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
126 20 : case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
127 3 : case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
128 13 : case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
129 1 : case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
130 1 : case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
131 1 : case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
132 12 : case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
133 : }
134 :
135 0 : llvm_unreachable("unknown GPU");
136 : }
137 :
138 : //===----------------------------------------------------------------------===//
139 : // AMDGPUTargetAsmStreamer
140 : //===----------------------------------------------------------------------===//
141 :
142 2236 : AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
143 2236 : formatted_raw_ostream &OS)
144 2236 : : AMDGPUTargetStreamer(S), OS(OS) { }
145 :
146 36 : void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {
147 36 : OS << "\t.amdgcn_target \"" << Target << "\"\n";
148 36 : }
149 :
150 288 : void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
151 : uint32_t Major, uint32_t Minor) {
152 288 : OS << "\t.hsa_code_object_version " <<
153 576 : Twine(Major) << "," << Twine(Minor) << '\n';
154 288 : }
155 :
156 : void
157 334 : AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
158 : uint32_t Minor,
159 : uint32_t Stepping,
160 : StringRef VendorName,
161 : StringRef ArchName) {
162 334 : OS << "\t.hsa_code_object_isa " <<
163 1002 : Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
164 334 : ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
165 :
166 334 : }
167 :
168 : void
169 2256 : AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
170 2256 : OS << "\t.amd_kernel_code_t\n";
171 2256 : dumpAmdKernelCode(&Header, OS, "\t\t");
172 2256 : OS << "\t.end_amd_kernel_code_t\n";
173 2256 : }
174 :
175 2261 : void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
176 : unsigned Type) {
177 2261 : switch (Type) {
178 0 : default: llvm_unreachable("Invalid AMDGPU symbol type");
179 2261 : case ELF::STT_AMDGPU_HSA_KERNEL:
180 2261 : OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
181 : break;
182 : }
183 2261 : }
184 :
185 1812 : bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) {
186 1812 : OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
187 1812 : return true;
188 : }
189 :
190 294 : bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
191 : const AMDGPU::HSAMD::Metadata &HSAMetadata) {
192 : std::string HSAMetadataString;
193 294 : if (HSAMD::toString(HSAMetadata, HSAMetadataString))
194 : return false;
195 :
196 588 : OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
197 294 : OS << HSAMetadataString << '\n';
198 588 : OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
199 : return true;
200 : }
201 :
202 42 : bool AMDGPUTargetAsmStreamer::EmitPALMetadata(
203 : const PALMD::Metadata &PALMetadata) {
204 : std::string PALMetadataString;
205 42 : if (PALMD::toString(PALMetadata, PALMetadataString))
206 : return false;
207 :
208 84 : OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
209 : return true;
210 : }
211 :
212 39 : void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
213 : const MCSubtargetInfo &STI, StringRef KernelName,
214 : const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
215 : bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
216 39 : IsaVersion IVersion = getIsaVersion(STI.getCPU());
217 :
218 39 : OS << "\t.amdhsa_kernel " << KernelName << '\n';
219 :
220 : #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
221 : STREAM << "\t\t" << DIRECTIVE << " " \
222 : << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
223 :
224 39 : OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
225 : << '\n';
226 39 : OS << "\t\t.amdhsa_private_segment_fixed_size "
227 39 : << KD.private_segment_fixed_size << '\n';
228 :
229 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
230 : kernel_code_properties,
231 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
232 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
233 : kernel_code_properties,
234 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
235 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
236 : kernel_code_properties,
237 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
238 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
239 : kernel_code_properties,
240 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
241 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
242 : kernel_code_properties,
243 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
244 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
245 : kernel_code_properties,
246 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
247 39 : PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
248 : kernel_code_properties,
249 : amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
250 39 : PRINT_FIELD(
251 : OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
252 : compute_pgm_rsrc2,
253 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
254 39 : PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
255 : compute_pgm_rsrc2,
256 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
257 39 : PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
258 : compute_pgm_rsrc2,
259 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
260 39 : PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
261 : compute_pgm_rsrc2,
262 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
263 39 : PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
264 : compute_pgm_rsrc2,
265 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
266 39 : PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
267 : compute_pgm_rsrc2,
268 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
269 :
270 : // These directives are required.
271 39 : OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
272 39 : OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
273 :
274 39 : if (!ReserveVCC)
275 38 : OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
276 39 : if (IVersion.Major >= 7 && !ReserveFlatScr)
277 30 : OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
278 39 : if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
279 2 : OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
280 :
281 39 : PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
282 : compute_pgm_rsrc1,
283 : amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
284 39 : PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
285 : compute_pgm_rsrc1,
286 : amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
287 39 : PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
288 : compute_pgm_rsrc1,
289 : amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
290 39 : PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
291 : compute_pgm_rsrc1,
292 : amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
293 39 : PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
294 : compute_pgm_rsrc1,
295 : amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
296 39 : PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
297 : compute_pgm_rsrc1,
298 : amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
299 39 : if (IVersion.Major >= 9)
300 9 : PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
301 : compute_pgm_rsrc1,
302 : amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
303 39 : PRINT_FIELD(
304 : OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
305 : compute_pgm_rsrc2,
306 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
307 39 : PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
308 : compute_pgm_rsrc2,
309 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
310 39 : PRINT_FIELD(
311 : OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
312 : compute_pgm_rsrc2,
313 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
314 39 : PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
315 : compute_pgm_rsrc2,
316 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
317 39 : PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
318 : compute_pgm_rsrc2,
319 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
320 39 : PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
321 : compute_pgm_rsrc2,
322 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
323 39 : PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
324 : compute_pgm_rsrc2,
325 : amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
326 : #undef PRINT_FIELD
327 :
328 39 : OS << "\t.end_amdhsa_kernel\n";
329 39 : }
330 :
331 : //===----------------------------------------------------------------------===//
332 : // AMDGPUTargetELFStreamer
333 : //===----------------------------------------------------------------------===//
334 :
335 144 : AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(
336 144 : MCStreamer &S, const MCSubtargetInfo &STI)
337 144 : : AMDGPUTargetStreamer(S), Streamer(S) {
338 144 : MCAssembler &MCA = getStreamer().getAssembler();
339 144 : unsigned EFlags = MCA.getELFHeaderEFlags();
340 :
341 144 : EFlags &= ~ELF::EF_AMDGPU_MACH;
342 144 : EFlags |= getElfMach(STI.getCPU());
343 :
344 144 : EFlags &= ~ELF::EF_AMDGPU_XNACK;
345 144 : if (AMDGPU::hasXNACK(STI))
346 21 : EFlags |= ELF::EF_AMDGPU_XNACK;
347 :
348 : MCA.setELFHeaderEFlags(EFlags);
349 144 : }
350 :
351 977 : MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
352 977 : return static_cast<MCELFStreamer &>(Streamer);
353 : }
354 :
355 258 : void AMDGPUTargetELFStreamer::EmitAMDGPUNote(
356 : const MCExpr *DescSZ, unsigned NoteType,
357 : function_ref<void(MCELFStreamer &)> EmitDesc) {
358 258 : auto &S = getStreamer();
359 258 : auto &Context = S.getContext();
360 :
361 : auto NameSZ = sizeof(ElfNote::NoteName);
362 :
363 258 : S.PushSection();
364 258 : S.SwitchSection(Context.getELFSection(
365 258 : ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC));
366 258 : S.EmitIntValue(NameSZ, 4); // namesz
367 258 : S.EmitValue(DescSZ, 4); // descz
368 258 : S.EmitIntValue(NoteType, 4); // type
369 516 : S.EmitBytes(StringRef(ElfNote::NoteName, NameSZ)); // name
370 258 : S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
371 258 : EmitDesc(S); // desc
372 258 : S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
373 258 : S.PopSection();
374 258 : }
375 :
376 3 : void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {}
377 :
378 51 : void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
379 : uint32_t Major, uint32_t Minor) {
380 :
381 51 : EmitAMDGPUNote(
382 102 : MCConstantExpr::create(8, getContext()),
383 : ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION,
384 : [&](MCELFStreamer &OS){
385 51 : OS.EmitIntValue(Major, 4);
386 51 : OS.EmitIntValue(Minor, 4);
387 : }
388 : );
389 51 : }
390 :
391 : void
392 58 : AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
393 : uint32_t Minor,
394 : uint32_t Stepping,
395 : StringRef VendorName,
396 : StringRef ArchName) {
397 58 : uint16_t VendorNameSize = VendorName.size() + 1;
398 58 : uint16_t ArchNameSize = ArchName.size() + 1;
399 :
400 58 : unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
401 : sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
402 58 : VendorNameSize + ArchNameSize;
403 :
404 58 : EmitAMDGPUNote(
405 116 : MCConstantExpr::create(DescSZ, getContext()),
406 : ElfNote::NT_AMDGPU_HSA_ISA,
407 : [&](MCELFStreamer &OS) {
408 : OS.EmitIntValue(VendorNameSize, 2);
409 : OS.EmitIntValue(ArchNameSize, 2);
410 : OS.EmitIntValue(Major, 4);
411 : OS.EmitIntValue(Minor, 4);
412 : OS.EmitIntValue(Stepping, 4);
413 : OS.EmitBytes(VendorName);
414 : OS.EmitIntValue(0, 1); // NULL terminate VendorName
415 : OS.EmitBytes(ArchName);
416 : OS.EmitIntValue(0, 1); // NULL terminte ArchName
417 : }
418 : );
419 58 : }
420 :
421 : void
422 282 : AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
423 :
424 282 : MCStreamer &OS = getStreamer();
425 282 : OS.PushSection();
426 564 : OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
427 282 : OS.PopSection();
428 282 : }
429 :
430 287 : void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
431 : unsigned Type) {
432 287 : MCSymbolELF *Symbol = cast<MCSymbolELF>(
433 287 : getStreamer().getContext().getOrCreateSymbol(SymbolName));
434 287 : Symbol->setType(Type);
435 287 : }
436 :
437 99 : bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) {
438 : // Create two labels to mark the beginning and end of the desc field
439 : // and a MCExpr to calculate the size of the desc field.
440 99 : auto &Context = getContext();
441 99 : auto *DescBegin = Context.createTempSymbol();
442 99 : auto *DescEnd = Context.createTempSymbol();
443 : auto *DescSZ = MCBinaryExpr::createSub(
444 99 : MCSymbolRefExpr::create(DescEnd, Context),
445 99 : MCSymbolRefExpr::create(DescBegin, Context), Context);
446 :
447 198 : EmitAMDGPUNote(
448 : DescSZ,
449 : ELF::NT_AMD_AMDGPU_ISA,
450 : [&](MCELFStreamer &OS) {
451 : OS.EmitLabel(DescBegin);
452 : OS.EmitBytes(IsaVersionString);
453 : OS.EmitLabel(DescEnd);
454 : }
455 : );
456 99 : return true;
457 : }
458 :
459 45 : bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
460 : const AMDGPU::HSAMD::Metadata &HSAMetadata) {
461 : std::string HSAMetadataString;
462 45 : if (HSAMD::toString(HSAMetadata, HSAMetadataString))
463 : return false;
464 :
465 : // Create two labels to mark the beginning and end of the desc field
466 : // and a MCExpr to calculate the size of the desc field.
467 45 : auto &Context = getContext();
468 45 : auto *DescBegin = Context.createTempSymbol();
469 45 : auto *DescEnd = Context.createTempSymbol();
470 : auto *DescSZ = MCBinaryExpr::createSub(
471 45 : MCSymbolRefExpr::create(DescEnd, Context),
472 45 : MCSymbolRefExpr::create(DescBegin, Context), Context);
473 :
474 90 : EmitAMDGPUNote(
475 : DescSZ,
476 : ELF::NT_AMD_AMDGPU_HSA_METADATA,
477 : [&](MCELFStreamer &OS) {
478 : OS.EmitLabel(DescBegin);
479 : OS.EmitBytes(HSAMetadataString);
480 : OS.EmitLabel(DescEnd);
481 : }
482 : );
483 45 : return true;
484 : }
485 :
486 5 : bool AMDGPUTargetELFStreamer::EmitPALMetadata(
487 : const PALMD::Metadata &PALMetadata) {
488 5 : EmitAMDGPUNote(
489 15 : MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), getContext()),
490 : ELF::NT_AMD_AMDGPU_PAL_METADATA,
491 : [&](MCELFStreamer &OS){
492 49 : for (auto I : PALMetadata)
493 44 : OS.EmitIntValue(I, sizeof(uint32_t));
494 : }
495 : );
496 5 : return true;
497 : }
498 :
499 6 : void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
500 : const MCSubtargetInfo &STI, StringRef KernelName,
501 : const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
502 : uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
503 : bool ReserveXNACK) {
504 6 : auto &Streamer = getStreamer();
505 6 : auto &Context = Streamer.getContext();
506 :
507 6 : MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
508 6 : Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
509 6 : KernelDescriptorSymbol->setBinding(ELF::STB_GLOBAL);
510 6 : KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
511 : KernelDescriptorSymbol->setSize(
512 6 : MCConstantExpr::create(sizeof(KernelDescriptor), Context));
513 :
514 6 : MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
515 6 : Context.getOrCreateSymbol(Twine(KernelName)));
516 6 : KernelCodeSymbol->setBinding(ELF::STB_LOCAL);
517 :
518 6 : Streamer.EmitLabel(KernelDescriptorSymbol);
519 6 : Streamer.EmitBytes(StringRef(
520 : (const char*)&(KernelDescriptor),
521 6 : offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset)));
522 : // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
523 : // expression being created is:
524 : // (start of kernel code) - (start of kernel descriptor)
525 : // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
526 6 : Streamer.EmitValue(MCBinaryExpr::createSub(
527 12 : MCSymbolRefExpr::create(
528 6 : KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
529 12 : MCSymbolRefExpr::create(
530 6 : KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
531 : Context),
532 6 : sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
533 6 : Streamer.EmitBytes(StringRef(
534 : (const char*)&(KernelDescriptor) +
535 : offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) +
536 : sizeof(KernelDescriptor.kernel_code_entry_byte_offset),
537 : sizeof(KernelDescriptor) -
538 : offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) -
539 6 : sizeof(KernelDescriptor.kernel_code_entry_byte_offset)));
540 6 : }
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