Line data Source code
1 : //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains the base ARM implementation of TargetRegisterInfo class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "ARMBaseRegisterInfo.h"
15 : #include "ARM.h"
16 : #include "ARMBaseInstrInfo.h"
17 : #include "ARMFrameLowering.h"
18 : #include "ARMMachineFunctionInfo.h"
19 : #include "ARMSubtarget.h"
20 : #include "MCTargetDesc/ARMAddressingModes.h"
21 : #include "MCTargetDesc/ARMBaseInfo.h"
22 : #include "llvm/ADT/BitVector.h"
23 : #include "llvm/ADT/STLExtras.h"
24 : #include "llvm/ADT/SmallVector.h"
25 : #include "llvm/CodeGen/MachineBasicBlock.h"
26 : #include "llvm/CodeGen/MachineConstantPool.h"
27 : #include "llvm/CodeGen/MachineFrameInfo.h"
28 : #include "llvm/CodeGen/MachineFunction.h"
29 : #include "llvm/CodeGen/MachineInstr.h"
30 : #include "llvm/CodeGen/MachineInstrBuilder.h"
31 : #include "llvm/CodeGen/MachineOperand.h"
32 : #include "llvm/CodeGen/MachineRegisterInfo.h"
33 : #include "llvm/CodeGen/RegisterScavenging.h"
34 : #include "llvm/CodeGen/TargetInstrInfo.h"
35 : #include "llvm/CodeGen/TargetRegisterInfo.h"
36 : #include "llvm/CodeGen/VirtRegMap.h"
37 : #include "llvm/IR/Attributes.h"
38 : #include "llvm/IR/Constants.h"
39 : #include "llvm/IR/DebugLoc.h"
40 : #include "llvm/IR/Function.h"
41 : #include "llvm/IR/Type.h"
42 : #include "llvm/MC/MCInstrDesc.h"
43 : #include "llvm/Support/Debug.h"
44 : #include "llvm/Support/ErrorHandling.h"
45 : #include "llvm/Support/raw_ostream.h"
46 : #include "llvm/Target/TargetMachine.h"
47 : #include "llvm/Target/TargetOptions.h"
48 : #include <cassert>
49 : #include <utility>
50 :
51 : #define DEBUG_TYPE "arm-register-info"
52 :
53 : #define GET_REGINFO_TARGET_DESC
54 : #include "ARMGenRegisterInfo.inc"
55 :
56 : using namespace llvm;
57 :
58 5050 : ARMBaseRegisterInfo::ARMBaseRegisterInfo()
59 5050 : : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
60 :
61 : static unsigned getFramePointerReg(const ARMSubtarget &STI) {
62 : return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
63 : }
64 :
65 : const MCPhysReg*
66 201442 : ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
67 201442 : const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
68 201442 : bool UseSplitPush = STI.splitFramePushPop(*MF);
69 : const MCPhysReg *RegList =
70 : STI.isTargetDarwin()
71 163603 : ? CSR_iOS_SaveList
72 : : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
73 :
74 201442 : const Function &F = MF->getFunction();
75 201442 : if (F.getCallingConv() == CallingConv::GHC) {
76 : // GHC set of callee saved regs is empty as all those regs are
77 : // used for passing STG regs around
78 : return CSR_NoRegs_SaveList;
79 201422 : } else if (F.hasFnAttribute("interrupt")) {
80 198 : if (STI.isMClass()) {
81 : // M-class CPUs have hardware which saves the registers needed to allow a
82 : // function conforming to the AAPCS to function as a handler.
83 132 : return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
84 242 : } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
85 : // Fast interrupt mode gives the handler a private copy of R8-R14, so less
86 : // need to be saved to restore user-mode state.
87 22 : return CSR_FIQ_SaveList;
88 : } else {
89 : // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
90 : // exception handling.
91 110 : return CSR_GenericInt_SaveList;
92 : }
93 : }
94 :
95 402448 : if (STI.getTargetLowering()->supportSwiftError() &&
96 402448 : F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
97 : if (STI.isTargetDarwin())
98 : return CSR_iOS_SwiftError_SaveList;
99 :
100 : return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
101 870 : CSR_AAPCS_SwiftError_SaveList;
102 : }
103 :
104 37246 : if (STI.isTargetDarwin() && F.getCallingConv() == CallingConv::CXX_FAST_TLS)
105 341 : return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
106 341 : ? CSR_iOS_CXX_TLS_PE_SaveList
107 : : CSR_iOS_CXX_TLS_SaveList;
108 : return RegList;
109 : }
110 :
111 13444 : const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
112 : const MachineFunction *MF) const {
113 : assert(MF && "Invalid MachineFunction pointer.");
114 26888 : if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
115 46 : MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
116 30 : return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
117 : return nullptr;
118 : }
119 :
120 : const uint32_t *
121 8604 : ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
122 : CallingConv::ID CC) const {
123 8604 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
124 8604 : if (CC == CallingConv::GHC)
125 : // This is academic because all GHC calls are (supposed to be) tail calls
126 : return CSR_NoRegs_RegMask;
127 :
128 17204 : if (STI.getTargetLowering()->supportSwiftError() &&
129 17204 : MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
130 : return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
131 : : CSR_AAPCS_SwiftError_RegMask;
132 :
133 2989 : if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
134 : return CSR_iOS_CXX_TLS_RegMask;
135 : return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
136 : }
137 :
138 : const uint32_t*
139 1 : ARMBaseRegisterInfo::getNoPreservedMask() const {
140 1 : return CSR_NoRegs_RegMask;
141 : }
142 :
143 : const uint32_t *
144 79 : ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
145 : assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
146 : "only know about special TLS call on Darwin");
147 79 : return CSR_iOS_TLSCall_RegMask;
148 : }
149 :
150 : const uint32_t *
151 32 : ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
152 32 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
153 32 : if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
154 27 : return CSR_NoRegs_RegMask;
155 : else
156 : return CSR_FPRegs_RegMask;
157 : }
158 :
159 : const uint32_t *
160 54 : ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
161 : CallingConv::ID CC) const {
162 54 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
163 : // This should return a register mask that is the same as that returned by
164 : // getCallPreservedMask but that additionally preserves the register used for
165 : // the first i32 argument (which must also be the register used to return a
166 : // single i32 return value)
167 : //
168 : // In case that the calling convention does not use the same register for
169 : // both or otherwise does not want to enable this optimization, the function
170 : // should return NULL
171 54 : if (CC == CallingConv::GHC)
172 : // This is academic because all GHC calls are (supposed to be) tail calls
173 : return nullptr;
174 : return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
175 : : CSR_AAPCS_ThisReturn_RegMask;
176 : }
177 :
178 30932 : BitVector ARMBaseRegisterInfo::
179 : getReservedRegs(const MachineFunction &MF) const {
180 30932 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
181 30932 : const ARMFrameLowering *TFI = getFrameLowering(MF);
182 :
183 : // FIXME: avoid re-calculating this every time.
184 30932 : BitVector Reserved(getNumRegs());
185 30932 : markSuperRegs(Reserved, ARM::SP);
186 30932 : markSuperRegs(Reserved, ARM::PC);
187 30932 : markSuperRegs(Reserved, ARM::FPSCR);
188 30932 : markSuperRegs(Reserved, ARM::APSR_NZCV);
189 30932 : if (TFI->hasFP(MF))
190 4253 : markSuperRegs(Reserved, getFramePointerReg(STI));
191 30932 : if (hasBasePointer(MF))
192 78 : markSuperRegs(Reserved, BasePtr);
193 : // Some targets reserve R9.
194 25275 : if (STI.isR9Reserved())
195 1305 : markSuperRegs(Reserved, ARM::R9);
196 : // Reserve D16-D31 if the subtarget doesn't support them.
197 30932 : if (!STI.hasVFP3() || STI.hasD16()) {
198 : static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
199 213299 : for (unsigned R = 0; R < 16; ++R)
200 200752 : markSuperRegs(Reserved, ARM::D16 + R);
201 : }
202 : const TargetRegisterClass &RC = ARM::GPRPairRegClass;
203 247456 : for (unsigned Reg : RC)
204 649572 : for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
205 433048 : if (Reserved.test(*SI))
206 36568 : markSuperRegs(Reserved, Reg);
207 :
208 : assert(checkAllSuperRegsMarked(Reserved));
209 30932 : return Reserved;
210 : }
211 :
212 416 : bool ARMBaseRegisterInfo::
213 : isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
214 416 : return !getReservedRegs(MF).test(PhysReg);
215 : }
216 :
217 : const TargetRegisterClass *
218 15173 : ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
219 : const MachineFunction &) const {
220 : const TargetRegisterClass *Super = RC;
221 15173 : TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
222 : do {
223 42870 : switch (Super->getID()) {
224 : case ARM::GPRRegClassID:
225 : case ARM::SPRRegClassID:
226 : case ARM::DPRRegClassID:
227 : case ARM::QPRRegClassID:
228 : case ARM::QQPRRegClassID:
229 : case ARM::QQQQPRRegClassID:
230 : case ARM::GPRPairRegClassID:
231 : return Super;
232 : }
233 7006 : Super = *I++;
234 7006 : } while (Super);
235 : return RC;
236 : }
237 :
238 : const TargetRegisterClass *
239 186 : ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
240 : const {
241 186 : return &ARM::GPRRegClass;
242 : }
243 :
244 : const TargetRegisterClass *
245 8 : ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
246 8 : if (RC == &ARM::CCRRegClass)
247 8 : return &ARM::rGPRRegClass; // Can't copy CCR registers.
248 : return RC;
249 : }
250 :
251 : unsigned
252 1166166 : ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
253 : MachineFunction &MF) const {
254 1166166 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
255 1166166 : const ARMFrameLowering *TFI = getFrameLowering(MF);
256 :
257 2332332 : switch (RC->getID()) {
258 : default:
259 : return 0;
260 11322 : case ARM::tGPRRegClassID: {
261 : // hasFP ends up calling getMaxCallFrameComputed() which may not be
262 : // available when getPressureLimit() is called as part of
263 : // ScheduleDAGRRList.
264 11322 : bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
265 11322 : ? TFI->hasFP(MF) : true;
266 11322 : return 5 - HasFP;
267 : }
268 11322 : case ARM::GPRRegClassID: {
269 11322 : bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
270 11322 : ? TFI->hasFP(MF) : true;
271 22569 : return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
272 : }
273 22644 : case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
274 : case ARM::DPRRegClassID:
275 22644 : return 32 - 10;
276 : }
277 : }
278 :
279 : // Get the other register in a GPRPair.
280 1172 : static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
281 1172 : for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
282 1003 : if (ARM::GPRPairRegClass.contains(*Supers))
283 1473 : return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
284 169 : return 0;
285 : }
286 :
287 : // Resolve the RegPairEven / RegPairOdd register allocator hints.
288 : bool
289 94372 : ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
290 : ArrayRef<MCPhysReg> Order,
291 : SmallVectorImpl<MCPhysReg> &Hints,
292 : const MachineFunction &MF,
293 : const VirtRegMap *VRM,
294 : const LiveRegMatrix *Matrix) const {
295 94372 : const MachineRegisterInfo &MRI = MF.getRegInfo();
296 : std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
297 :
298 : unsigned Odd;
299 94372 : switch (Hint.first) {
300 : case ARMRI::RegPairEven:
301 : Odd = 0;
302 : break;
303 93 : case ARMRI::RegPairOdd:
304 : Odd = 1;
305 93 : break;
306 94190 : default:
307 94190 : TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
308 94190 : return false;
309 : }
310 :
311 : // This register should preferably be even (Odd == 0) or odd (Odd == 1).
312 : // Check if the other part of the pair has already been assigned, and provide
313 : // the paired register as the first hint.
314 : unsigned Paired = Hint.second;
315 182 : if (Paired == 0)
316 : return false;
317 :
318 182 : unsigned PairedPhys = 0;
319 182 : if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
320 0 : PairedPhys = Paired;
321 182 : } else if (VRM && VRM->hasPhys(Paired)) {
322 68 : PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
323 : }
324 :
325 : // First prefer the paired physreg.
326 182 : if (PairedPhys && is_contained(Order, PairedPhys))
327 68 : Hints.push_back(PairedPhys);
328 :
329 : // Then prefer even or odd registers.
330 2508 : for (unsigned Reg : Order) {
331 2326 : if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
332 : continue;
333 : // Don't provide hints that are paired to a reserved register.
334 1104 : unsigned Paired = getPairedGPR(Reg, !Odd, this);
335 1104 : if (!Paired || MRI.isReserved(Paired))
336 : continue;
337 846 : Hints.push_back(Reg);
338 : }
339 : return false;
340 : }
341 :
342 : void
343 21069 : ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
344 : MachineFunction &MF) const {
345 21069 : MachineRegisterInfo *MRI = &MF.getRegInfo();
346 : std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
347 21069 : if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
348 21069 : Hint.first == (unsigned)ARMRI::RegPairEven) &&
349 : TargetRegisterInfo::isVirtualRegister(Hint.second)) {
350 : // If 'Reg' is one of the even / odd register pair and it's now changed
351 : // (e.g. coalesced) into a different register. The other register of the
352 : // pair allocation hint must be updated to reflect the relationship
353 : // change.
354 : unsigned OtherReg = Hint.second;
355 : Hint = MRI->getRegAllocationHint(OtherReg);
356 : // Make sure the pair has not already divorced.
357 46 : if (Hint.second == Reg) {
358 46 : MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
359 46 : if (TargetRegisterInfo::isVirtualRegister(NewReg))
360 92 : MRI->setRegAllocationHint(NewReg,
361 : Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
362 : : ARMRI::RegPairOdd, OtherReg);
363 : }
364 : }
365 21069 : }
366 :
367 56980 : bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
368 56980 : const MachineFrameInfo &MFI = MF.getFrameInfo();
369 : const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
370 56980 : const ARMFrameLowering *TFI = getFrameLowering(MF);
371 :
372 : // When outgoing call frames are so large that we adjust the stack pointer
373 : // around the call, we can no longer use the stack pointer to reach the
374 : // emergency spill slot.
375 56980 : if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
376 : return true;
377 :
378 : // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
379 : // negative range for ldr/str (255), and thumb1 is positive offsets only.
380 : // It's going to be better to use the SP or Base Pointer instead. When there
381 : // are variable sized objects, we can't reference off of the SP, so we
382 : // reserve a Base Pointer.
383 56952 : if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
384 : // Conservatively estimate whether the negative offset from the frame
385 : // pointer will be sufficient to reach. If a function has a smallish
386 : // frame, it's less likely to have lots of spills and callee saved
387 : // space, so it's all more likely to be within range of the frame pointer.
388 : // If it's wrong, the scavenger will still enable access to work, it just
389 : // won't be optimal.
390 74 : if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
391 74 : return false;
392 : return true;
393 : }
394 :
395 : return false;
396 : }
397 :
398 14612 : bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
399 14612 : const MachineRegisterInfo *MRI = &MF.getRegInfo();
400 14612 : const ARMFrameLowering *TFI = getFrameLowering(MF);
401 : // We can't realign the stack if:
402 : // 1. Dynamic stack realignment is explicitly disabled,
403 : // 2. There are VLAs in the function and the base pointer is disabled.
404 14612 : if (!TargetRegisterInfo::canRealignStack(MF))
405 : return false;
406 : // Stack realignment requires a frame pointer. If we already started
407 : // register allocation with frame pointer elimination, it is too late now.
408 14611 : if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
409 : return false;
410 : // We may also need a base pointer if there are dynamic allocas or stack
411 : // pointer adjustments around calls.
412 13454 : if (TFI->hasReservedCallFrame(MF))
413 : return true;
414 : // A base pointer is required and allowed. Check that it isn't too late to
415 : // reserve it.
416 648 : return MRI->canReserveReg(BasePtr);
417 : }
418 :
419 10382 : bool ARMBaseRegisterInfo::
420 : cannotEliminateFrame(const MachineFunction &MF) const {
421 10382 : const MachineFrameInfo &MFI = MF.getFrameInfo();
422 10382 : if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
423 : return true;
424 10379 : return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
425 20739 : || needsStackRealignment(MF);
426 : }
427 :
428 : unsigned
429 53195 : ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
430 53195 : const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
431 53195 : const ARMFrameLowering *TFI = getFrameLowering(MF);
432 :
433 53195 : if (TFI->hasFP(MF))
434 : return getFramePointerReg(STI);
435 : return ARM::SP;
436 : }
437 :
438 : /// emitLoadConstPool - Emits a load from constpool to materialize the
439 : /// specified immediate.
440 0 : void ARMBaseRegisterInfo::emitLoadConstPool(
441 : MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
442 : const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
443 : ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
444 0 : MachineFunction &MF = *MBB.getParent();
445 0 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
446 0 : MachineConstantPool *ConstantPool = MF.getConstantPool();
447 : const Constant *C =
448 0 : ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val);
449 0 : unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
450 :
451 0 : BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
452 0 : .addReg(DestReg, getDefRegState(true), SubIdx)
453 : .addConstantPoolIndex(Idx)
454 : .addImm(0)
455 0 : .add(predOps(Pred, PredReg))
456 : .setMIFlags(MIFlags);
457 0 : }
458 :
459 41391 : bool ARMBaseRegisterInfo::
460 : requiresRegisterScavenging(const MachineFunction &MF) const {
461 41391 : return true;
462 : }
463 :
464 26380 : bool ARMBaseRegisterInfo::
465 : trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
466 26380 : return true;
467 : }
468 :
469 14596 : bool ARMBaseRegisterInfo::
470 : requiresFrameIndexScavenging(const MachineFunction &MF) const {
471 14596 : return true;
472 : }
473 :
474 14589 : bool ARMBaseRegisterInfo::
475 : requiresVirtualBaseRegisters(const MachineFunction &MF) const {
476 14589 : return true;
477 : }
478 :
479 5721 : int64_t ARMBaseRegisterInfo::
480 : getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
481 5721 : const MCInstrDesc &Desc = MI->getDesc();
482 5721 : unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
483 : int64_t InstrOffs = 0;
484 : int Scale = 1;
485 : unsigned ImmIdx = 0;
486 5721 : switch (AddrMode) {
487 4486 : case ARMII::AddrModeT2_i8:
488 : case ARMII::AddrModeT2_i12:
489 : case ARMII::AddrMode_i12:
490 4486 : InstrOffs = MI->getOperand(Idx+1).getImm();
491 : Scale = 1;
492 4486 : break;
493 285 : case ARMII::AddrMode5: {
494 : // VFP address mode.
495 285 : const MachineOperand &OffOp = MI->getOperand(Idx+1);
496 285 : InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
497 : if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
498 0 : InstrOffs = -InstrOffs;
499 : Scale = 4;
500 : break;
501 : }
502 0 : case ARMII::AddrMode2:
503 0 : ImmIdx = Idx+2;
504 0 : InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
505 : if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
506 0 : InstrOffs = -InstrOffs;
507 : break;
508 59 : case ARMII::AddrMode3:
509 59 : ImmIdx = Idx+2;
510 118 : InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
511 : if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
512 0 : InstrOffs = -InstrOffs;
513 : break;
514 891 : case ARMII::AddrModeT1_s:
515 891 : ImmIdx = Idx+1;
516 891 : InstrOffs = MI->getOperand(ImmIdx).getImm();
517 : Scale = 4;
518 891 : break;
519 0 : default:
520 0 : llvm_unreachable("Unsupported addressing mode!");
521 : }
522 :
523 5721 : return InstrOffs * Scale;
524 : }
525 :
526 : /// needsFrameBaseReg - Returns true if the instruction's frame index
527 : /// reference would be better served by a base register other than FP
528 : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
529 : /// references it should create new base registers for.
530 7504 : bool ARMBaseRegisterInfo::
531 : needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
532 22509 : for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
533 : assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
534 : }
535 :
536 : // It's the load/store FI references that cause issues, as it can be difficult
537 : // to materialize the offset if it won't fit in the literal field. Estimate
538 : // based on the size of the local frame and some conservative assumptions
539 : // about the rest of the stack frame (note, this is pre-regalloc, so
540 : // we don't know everything for certain yet) whether this offset is likely
541 : // to be out of range of the immediate. Return true if so.
542 :
543 : // We only generate virtual base registers for loads and stores, so
544 : // return false for everything else.
545 7504 : unsigned Opc = MI->getOpcode();
546 7504 : switch (Opc) {
547 : case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
548 : case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
549 : case ARM::t2LDRi12: case ARM::t2LDRi8:
550 : case ARM::t2STRi12: case ARM::t2STRi8:
551 : case ARM::VLDRS: case ARM::VLDRD:
552 : case ARM::VSTRS: case ARM::VSTRD:
553 : case ARM::tSTRspi: case ARM::tLDRspi:
554 : break;
555 : default:
556 : return false;
557 : }
558 :
559 : // Without a virtual base register, if the function has variable sized
560 : // objects, all fixed-size local references will be via the frame pointer,
561 : // Approximate the offset and see if it's legal for the instruction.
562 : // Note that the incoming offset is based on the SP value at function entry,
563 : // so it'll be negative.
564 5320 : MachineFunction &MF = *MI->getParent()->getParent();
565 5320 : const ARMFrameLowering *TFI = getFrameLowering(MF);
566 5320 : MachineFrameInfo &MFI = MF.getFrameInfo();
567 5320 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
568 :
569 : // Estimate an offset from the frame pointer.
570 : // Conservatively assume all callee-saved registers get pushed. R4-R6
571 : // will be earlier than the FP, so we ignore those.
572 : // R7, LR
573 5320 : int64_t FPOffset = Offset - 8;
574 : // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
575 5320 : if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
576 4539 : FPOffset -= 80;
577 : // Estimate an offset from the stack pointer.
578 : // The incoming offset is relating to the SP at the start of the function,
579 : // but when we access the local it'll be relative to the SP after local
580 : // allocation, so adjust our SP-relative offset by that allocation size.
581 5320 : Offset += MFI.getLocalFrameSize();
582 : // Assume that we'll have at least some spill slots allocated.
583 : // FIXME: This is a total SWAG number. We should run some statistics
584 : // and pick a real one.
585 5320 : Offset += 128; // 128 bytes of spill slots
586 :
587 : // If there's a frame pointer and the addressing mode allows it, try using it.
588 : // The FP is only available if there is no dynamic realignment. We
589 : // don't know for sure yet whether we'll need that, so we guess based
590 : // on whether there are any local variables that would trigger it.
591 5320 : unsigned StackAlign = TFI->getStackAlignment();
592 5320 : if (TFI->hasFP(MF) &&
593 3300 : !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
594 2829 : if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
595 : return false;
596 : }
597 : // If we can reference via the stack pointer, try that.
598 : // FIXME: This (and the code that resolves the references) can be improved
599 : // to only disallow SP relative references in the live range of
600 : // the VLA(s). In practice, it's unclear how much difference that
601 : // would make, but it may be worth doing.
602 2818 : if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
603 2747 : return false;
604 :
605 : // The offset likely isn't legal, we want to allocate a virtual base register.
606 : return true;
607 : }
608 :
609 : /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
610 : /// be a pointer to FrameIdx at the beginning of the basic block.
611 7 : void ARMBaseRegisterInfo::
612 : materializeFrameBaseRegister(MachineBasicBlock *MBB,
613 : unsigned BaseReg, int FrameIdx,
614 : int64_t Offset) const {
615 7 : ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
616 7 : unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
617 : (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
618 :
619 : MachineBasicBlock::iterator Ins = MBB->begin();
620 7 : DebugLoc DL; // Defaults to "unknown"
621 7 : if (Ins != MBB->end())
622 : DL = Ins->getDebugLoc();
623 :
624 7 : const MachineFunction &MF = *MBB->getParent();
625 7 : MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
626 7 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
627 7 : const MCInstrDesc &MCID = TII.get(ADDriOpc);
628 7 : MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
629 :
630 7 : MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
631 : .addFrameIndex(FrameIdx).addImm(Offset);
632 :
633 7 : if (!AFI->isThumb1OnlyFunction())
634 2 : MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
635 7 : }
636 :
637 30 : void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
638 : int64_t Offset) const {
639 30 : MachineBasicBlock &MBB = *MI.getParent();
640 30 : MachineFunction &MF = *MBB.getParent();
641 : const ARMBaseInstrInfo &TII =
642 30 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
643 30 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
644 30 : int Off = Offset; // ARM doesn't need the general 64-bit offsets
645 : unsigned i = 0;
646 :
647 : assert(!AFI->isThumb1OnlyFunction() &&
648 : "This resolveFrameIndex does not support Thumb1!");
649 :
650 120 : while (!MI.getOperand(i).isFI()) {
651 30 : ++i;
652 : assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
653 : }
654 : bool Done = false;
655 30 : if (!AFI->isThumbFunction())
656 15 : Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
657 : else {
658 : assert(AFI->isThumb2Function());
659 15 : Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
660 : }
661 : assert(Done && "Unable to resolve frame index!");
662 : (void)Done;
663 30 : }
664 :
665 5686 : bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
666 : int64_t Offset) const {
667 5686 : const MCInstrDesc &Desc = MI->getDesc();
668 5686 : unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
669 : unsigned i = 0;
670 17058 : for (; !MI->getOperand(i).isFI(); ++i)
671 : assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
672 :
673 : // AddrMode4 and AddrMode6 cannot handle any offset.
674 5686 : if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
675 0 : return Offset == 0;
676 :
677 : unsigned NumBits = 0;
678 : unsigned Scale = 1;
679 : bool isSigned = true;
680 5686 : switch (AddrMode) {
681 1980 : case ARMII::AddrModeT2_i8:
682 : case ARMII::AddrModeT2_i12:
683 : // i8 supports only negative, and i12 supports only positive, so
684 : // based on Offset sign, consider the appropriate instruction
685 : Scale = 1;
686 1980 : if (Offset < 0) {
687 : NumBits = 8;
688 1264 : Offset = -Offset;
689 : } else {
690 : NumBits = 12;
691 : }
692 : break;
693 : case ARMII::AddrMode5:
694 : // VFP address mode.
695 : NumBits = 8;
696 : Scale = 4;
697 : break;
698 2499 : case ARMII::AddrMode_i12:
699 : case ARMII::AddrMode2:
700 : NumBits = 12;
701 2499 : break;
702 59 : case ARMII::AddrMode3:
703 : NumBits = 8;
704 59 : break;
705 868 : case ARMII::AddrModeT1_s:
706 868 : NumBits = (BaseReg == ARM::SP ? 8 : 5);
707 : Scale = 4;
708 : isSigned = false;
709 : break;
710 0 : default:
711 0 : llvm_unreachable("Unsupported addressing mode!");
712 : }
713 :
714 5686 : Offset += getFrameIndexInstrOffset(MI, i);
715 : // Make sure the offset is encodable for instructions that scale the
716 : // immediate.
717 5686 : if ((Offset & (Scale-1)) != 0)
718 : return false;
719 :
720 5683 : if (isSigned && Offset < 0)
721 1487 : Offset = -Offset;
722 :
723 5683 : unsigned Mask = (1 << NumBits) - 1;
724 5683 : if ((unsigned)Offset <= Mask * Scale)
725 5292 : return true;
726 :
727 : return false;
728 : }
729 :
730 : void
731 13495 : ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
732 : int SPAdj, unsigned FIOperandNum,
733 : RegScavenger *RS) const {
734 : MachineInstr &MI = *II;
735 13495 : MachineBasicBlock &MBB = *MI.getParent();
736 13495 : MachineFunction &MF = *MBB.getParent();
737 : const ARMBaseInstrInfo &TII =
738 13495 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
739 13495 : const ARMFrameLowering *TFI = getFrameLowering(MF);
740 13495 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
741 : assert(!AFI->isThumb1OnlyFunction() &&
742 : "This eliminateFrameIndex does not support Thumb1!");
743 13495 : int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
744 : unsigned FrameReg;
745 :
746 13495 : int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
747 :
748 : // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
749 : // call frame setup/destroy instructions have already been eliminated. That
750 : // means the stack pointer cannot be used to access the emergency spill slot
751 : // when !hasReservedCallFrame().
752 : #ifndef NDEBUG
753 : if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
754 : assert(TFI->hasReservedCallFrame(MF) &&
755 : "Cannot use SP to access the emergency spill slot in "
756 : "functions without a reserved call frame");
757 : assert(!MF.getFrameInfo().hasVarSizedObjects() &&
758 : "Cannot use SP to access the emergency spill slot in "
759 : "functions with variable sized frame objects");
760 : }
761 : #endif // NDEBUG
762 :
763 : assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
764 :
765 : // Modify MI as necessary to handle as much of 'Offset' as possible
766 : bool Done = false;
767 13495 : if (!AFI->isThumbFunction())
768 7985 : Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
769 : else {
770 : assert(AFI->isThumb2Function());
771 5510 : Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
772 : }
773 13495 : if (Done)
774 11946 : return;
775 :
776 : // If we get here, the immediate doesn't fit into the instruction. We folded
777 : // as much as possible above, handle the rest, providing a register that is
778 : // SP+LargeImm.
779 : assert((Offset ||
780 : (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
781 : (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
782 : "This code isn't needed if offset already handled!");
783 :
784 : unsigned ScratchReg = 0;
785 1549 : int PIdx = MI.findFirstPredOperandIdx();
786 : ARMCC::CondCodes Pred = (PIdx == -1)
787 1549 : ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
788 1549 : unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
789 1549 : if (Offset == 0)
790 : // Must be addrmode4/6.
791 46 : MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
792 : else {
793 3052 : ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
794 1526 : if (!AFI->isThumbFunction())
795 768 : emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
796 : Offset, Pred, PredReg, TII);
797 : else {
798 : assert(AFI->isThumb2Function());
799 2284 : emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
800 : Offset, Pred, PredReg, TII);
801 : }
802 : // Update the original instruction to use the scratch register.
803 3052 : MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
804 : }
805 : }
806 :
807 22575 : bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
808 : const TargetRegisterClass *SrcRC,
809 : unsigned SubReg,
810 : const TargetRegisterClass *DstRC,
811 : unsigned DstSubReg,
812 : const TargetRegisterClass *NewRC,
813 : LiveIntervals &LIS) const {
814 22575 : auto MBB = MI->getParent();
815 22575 : auto MF = MBB->getParent();
816 22575 : const MachineRegisterInfo &MRI = MF->getRegInfo();
817 : // If not copying into a sub-register this should be ok because we shouldn't
818 : // need to split the reg.
819 22575 : if (!DstSubReg)
820 : return true;
821 : // Small registers don't frequently cause a problem, so we can coalesce them.
822 3512 : if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
823 : getRegSizeInBits(*SrcRC) < 256)
824 : return true;
825 :
826 : auto NewRCWeight =
827 442 : MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
828 : auto SrcRCWeight =
829 442 : MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
830 : auto DstRCWeight =
831 442 : MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
832 : // If the source register class is more expensive than the destination, the
833 : // coalescing is probably profitable.
834 442 : if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
835 : return true;
836 442 : if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
837 : return true;
838 :
839 : // If the register allocator isn't constrained, we can always allow coalescing
840 : // unfortunately we don't know yet if we will be constrained.
841 : // The goal of this heuristic is to restrict how many expensive registers
842 : // we allow to coalesce in a given basic block.
843 442 : auto AFI = MF->getInfo<ARMFunctionInfo>();
844 442 : auto It = AFI->getCoalescedWeight(MBB);
845 :
846 : LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
847 : << It->second << "\n");
848 : LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
849 : << NewRCWeight.RegWeight << "\n");
850 :
851 : // This number is the largest round number that which meets the criteria:
852 : // (1) addresses PR18825
853 : // (2) generates better code in some test cases (like vldm-shed-a9.ll)
854 : // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
855 : // In practice the SizeMultiplier will only factor in for straight line code
856 : // that uses a lot of NEON vectors, which isn't terribly common.
857 442 : unsigned SizeMultiplier = MBB->size()/100;
858 442 : SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
859 442 : if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
860 422 : It->second += NewRCWeight.RegWeight;
861 422 : return true;
862 : }
863 : return false;
864 : }
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