Line data Source code
1 : //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains the ARM implementation of TargetFrameLowering class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "ARMFrameLowering.h"
15 : #include "ARMBaseInstrInfo.h"
16 : #include "ARMBaseRegisterInfo.h"
17 : #include "ARMConstantPoolValue.h"
18 : #include "ARMMachineFunctionInfo.h"
19 : #include "ARMSubtarget.h"
20 : #include "MCTargetDesc/ARMAddressingModes.h"
21 : #include "MCTargetDesc/ARMBaseInfo.h"
22 : #include "Utils/ARMBaseInfo.h"
23 : #include "llvm/ADT/BitVector.h"
24 : #include "llvm/ADT/STLExtras.h"
25 : #include "llvm/ADT/SmallPtrSet.h"
26 : #include "llvm/ADT/SmallVector.h"
27 : #include "llvm/CodeGen/MachineBasicBlock.h"
28 : #include "llvm/CodeGen/MachineConstantPool.h"
29 : #include "llvm/CodeGen/MachineFrameInfo.h"
30 : #include "llvm/CodeGen/MachineFunction.h"
31 : #include "llvm/CodeGen/MachineInstr.h"
32 : #include "llvm/CodeGen/MachineInstrBuilder.h"
33 : #include "llvm/CodeGen/MachineModuleInfo.h"
34 : #include "llvm/CodeGen/MachineOperand.h"
35 : #include "llvm/CodeGen/MachineRegisterInfo.h"
36 : #include "llvm/CodeGen/RegisterScavenging.h"
37 : #include "llvm/CodeGen/TargetInstrInfo.h"
38 : #include "llvm/CodeGen/TargetOpcodes.h"
39 : #include "llvm/CodeGen/TargetRegisterInfo.h"
40 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 : #include "llvm/IR/Attributes.h"
42 : #include "llvm/IR/CallingConv.h"
43 : #include "llvm/IR/DebugLoc.h"
44 : #include "llvm/IR/Function.h"
45 : #include "llvm/MC/MCContext.h"
46 : #include "llvm/MC/MCDwarf.h"
47 : #include "llvm/MC/MCInstrDesc.h"
48 : #include "llvm/MC/MCRegisterInfo.h"
49 : #include "llvm/Support/CodeGen.h"
50 : #include "llvm/Support/CommandLine.h"
51 : #include "llvm/Support/Compiler.h"
52 : #include "llvm/Support/Debug.h"
53 : #include "llvm/Support/ErrorHandling.h"
54 : #include "llvm/Support/MathExtras.h"
55 : #include "llvm/Support/raw_ostream.h"
56 : #include "llvm/Target/TargetMachine.h"
57 : #include "llvm/Target/TargetOptions.h"
58 : #include <algorithm>
59 : #include <cassert>
60 : #include <cstddef>
61 : #include <cstdint>
62 : #include <iterator>
63 : #include <utility>
64 : #include <vector>
65 :
66 : #define DEBUG_TYPE "arm-frame-lowering"
67 :
68 : using namespace llvm;
69 :
70 : static cl::opt<bool>
71 : SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
72 : cl::desc("Align ARM NEON spills in prolog and epilog"));
73 :
74 : static MachineBasicBlock::iterator
75 : skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
76 : unsigned NumAlignedDPRCS2Regs);
77 :
78 5050 : ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
79 : : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
80 10100 : STI(sti) {}
81 :
82 362336 : bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
83 : // iOS always has a FP for backtracking, force other targets to keep their FP
84 : // when doing FastISel. The emitted code is currently superior, and in cases
85 : // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
86 690076 : return TargetFrameLowering::noFramePointerElim(MF) ||
87 327740 : MF.getSubtarget<ARMSubtarget>().useFastISel();
88 : }
89 :
90 : /// Returns true if the target can safely skip saving callee-saved registers
91 : /// for noreturn nounwind functions.
92 14 : bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const {
93 : assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
94 : MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
95 : !MF.getFunction().hasFnAttribute(Attribute::UWTable));
96 :
97 : // Frame pointer and link register are not treated as normal CSR, thus we
98 : // can always skip CSR saves for nonreturning functions.
99 14 : return true;
100 : }
101 :
102 : /// hasFP - Return true if the specified function should have a dedicated frame
103 : /// pointer register. This is true if the function has variable sized allocas
104 : /// or if frame pointer elimination is disabled.
105 149332 : bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
106 149332 : const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
107 149332 : const MachineFrameInfo &MFI = MF.getFrameInfo();
108 :
109 : // ABI-required frame pointer.
110 149332 : if (MF.getTarget().Options.DisableFramePointerElim(MF))
111 : return true;
112 :
113 : // Frame pointer required for use within this function.
114 126145 : return (RegInfo->needsStackRealignment(MF) ||
115 126145 : MFI.hasVarSizedObjects() ||
116 122856 : MFI.isFrameAddressTaken());
117 : }
118 :
119 : /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
120 : /// not required, we reserve argument space for call sites in the function
121 : /// immediately on entry to the current function. This eliminates the need for
122 : /// add/sub sp brackets around call sites. Returns true if the call frame is
123 : /// included as part of the stack frame.
124 62663 : bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
125 62663 : const MachineFrameInfo &MFI = MF.getFrameInfo();
126 : unsigned CFSize = MFI.getMaxCallFrameSize();
127 : // It's not always a good idea to include the call frame as part of the
128 : // stack frame. ARM (especially Thumb) has small immediate offset to
129 : // address the stack frame. So a large call frame can cause poor codegen
130 : // and may even makes it impossible to scavenge a register.
131 62662 : if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
132 : return false;
133 :
134 61450 : return !MFI.hasVarSizedObjects();
135 : }
136 :
137 : /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
138 : /// call frame pseudos can be simplified. Unlike most targets, having a FP
139 : /// is not sufficient here since we still may reference some objects via SP
140 : /// even when FP is available in Thumb2 mode.
141 : bool
142 18808 : ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
143 18808 : return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();
144 : }
145 :
146 0 : static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
147 : const MCPhysReg *CSRegs) {
148 : // Integer spill area is handled with "pop".
149 0 : if (isPopOpcode(MI.getOpcode())) {
150 : // The first two operands are predicates. The last two are
151 : // imp-def and imp-use of SP. Check everything in between.
152 0 : for (int i = 5, e = MI.getNumOperands(); i != e; ++i)
153 0 : if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
154 0 : return false;
155 0 : return true;
156 : }
157 0 : if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
158 0 : MI.getOpcode() == ARM::LDR_POST_REG ||
159 0 : MI.getOpcode() == ARM::t2LDR_POST) &&
160 0 : isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
161 0 : MI.getOperand(1).getReg() == ARM::SP)
162 0 : return true;
163 :
164 : return false;
165 : }
166 :
167 3772 : static void emitRegPlusImmediate(
168 : bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
169 : const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
170 : unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
171 : ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
172 3772 : if (isARM)
173 2415 : emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
174 : Pred, PredReg, TII, MIFlags);
175 : else
176 1357 : emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
177 : Pred, PredReg, TII, MIFlags);
178 3772 : }
179 :
180 : static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
181 : MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,
182 : const ARMBaseInstrInfo &TII, int NumBytes,
183 : unsigned MIFlags = MachineInstr::NoFlags,
184 : ARMCC::CondCodes Pred = ARMCC::AL,
185 : unsigned PredReg = 0) {
186 2798 : emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
187 : MIFlags, Pred, PredReg);
188 : }
189 :
190 1254 : static int sizeOfSPAdjustment(const MachineInstr &MI) {
191 : int RegSize;
192 2508 : switch (MI.getOpcode()) {
193 : case ARM::VSTMDDB_UPD:
194 : RegSize = 8;
195 : break;
196 966 : case ARM::STMDB_UPD:
197 : case ARM::t2STMDB_UPD:
198 : RegSize = 4;
199 966 : break;
200 : case ARM::t2STR_PRE:
201 : case ARM::STR_PRE_IMM:
202 : return 4;
203 0 : default:
204 0 : llvm_unreachable("Unknown push or pop like instruction");
205 : }
206 :
207 : int count = 0;
208 : // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
209 : // pred) so the list starts at 4.
210 5508 : for (int i = MI.getNumOperands() - 1; i >= 4; --i)
211 4262 : count += RegSize;
212 : return count;
213 : }
214 :
215 343 : static bool WindowsRequiresStackProbe(const MachineFunction &MF,
216 : size_t StackSizeInBytes) {
217 343 : const MachineFrameInfo &MFI = MF.getFrameInfo();
218 343 : const Function &F = MF.getFunction();
219 686 : unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096;
220 343 : if (F.hasFnAttribute("stack-probe-size"))
221 8 : F.getFnAttribute("stack-probe-size")
222 8 : .getValueAsString()
223 4 : .getAsInteger(0, StackProbeSize);
224 343 : return (StackSizeInBytes >= StackProbeSize) &&
225 8 : !F.hasFnAttribute("no-stack-arg-probe");
226 : }
227 :
228 : namespace {
229 :
230 13423 : struct StackAdjustingInsts {
231 : struct InstInfo {
232 : MachineBasicBlock::iterator I;
233 : unsigned SPAdjust;
234 : bool BeforeFPSet;
235 : };
236 :
237 : SmallVector<InstInfo, 4> Insts;
238 :
239 : void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
240 : bool BeforeFPSet = false) {
241 5601 : InstInfo Info = {I, SPAdjust, BeforeFPSet};
242 3756 : Insts.push_back(Info);
243 : }
244 :
245 : void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
246 : auto Info =
247 24 : llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
248 : assert(Info != Insts.end() && "invalid sp adjusting instruction");
249 24 : Info->SPAdjust += ExtraBytes;
250 : }
251 :
252 13423 : void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
253 : const ARMBaseInstrInfo &TII, bool HasFP) {
254 13423 : MachineFunction &MF = *MBB.getParent();
255 : unsigned CFAOffset = 0;
256 18345 : for (auto &Info : Insts) {
257 5469 : if (HasFP && !Info.BeforeFPSet)
258 : return;
259 :
260 4922 : CFAOffset -= Info.SPAdjust;
261 : unsigned CFIIndex = MF.addFrameInst(
262 4922 : MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
263 4922 : BuildMI(MBB, std::next(Info.I), dl,
264 4922 : TII.get(TargetOpcode::CFI_INSTRUCTION))
265 : .addCFIIndex(CFIIndex)
266 : .setMIFlags(MachineInstr::FrameSetup);
267 : }
268 : }
269 : };
270 :
271 : } // end anonymous namespace
272 :
273 : /// Emit an instruction sequence that will align the address in
274 : /// register Reg by zero-ing out the lower bits. For versions of the
275 : /// architecture that support Neon, this must be done in a single
276 : /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
277 : /// single instruction. That function only gets called when optimizing
278 : /// spilling of D registers on a core with the Neon instruction set
279 : /// present.
280 204 : static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
281 : const TargetInstrInfo &TII,
282 : MachineBasicBlock &MBB,
283 : MachineBasicBlock::iterator MBBI,
284 : const DebugLoc &DL, const unsigned Reg,
285 : const unsigned Alignment,
286 : const bool MustBeSingleInstruction) {
287 : const ARMSubtarget &AST =
288 204 : static_cast<const ARMSubtarget &>(MF.getSubtarget());
289 204 : const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
290 204 : const unsigned AlignMask = Alignment - 1;
291 204 : const unsigned NrBitsToZero = countTrailingZeros(Alignment);
292 : assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
293 204 : if (!AFI->isThumbFunction()) {
294 : // if the BFC instruction is available, use that to zero the lower
295 : // bits:
296 : // bfc Reg, #0, log2(Alignment)
297 : // otherwise use BIC, if the mask to zero the required number of bits
298 : // can be encoded in the bic immediate field
299 : // bic Reg, Reg, Alignment-1
300 : // otherwise, emit
301 : // lsr Reg, Reg, log2(Alignment)
302 : // lsl Reg, Reg, log2(Alignment)
303 114 : if (CanUseBFC) {
304 198 : BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
305 99 : .addReg(Reg, RegState::Kill)
306 99 : .addImm(~AlignMask)
307 99 : .add(predOps(ARMCC::AL));
308 15 : } else if (AlignMask <= 255) {
309 26 : BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
310 13 : .addReg(Reg, RegState::Kill)
311 13 : .addImm(AlignMask)
312 13 : .add(predOps(ARMCC::AL))
313 13 : .add(condCodeOp());
314 : } else {
315 : assert(!MustBeSingleInstruction &&
316 : "Shouldn't call emitAligningInstructions demanding a single "
317 : "instruction to be emitted for large stack alignment for a target "
318 : "without BFC.");
319 4 : BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
320 2 : .addReg(Reg, RegState::Kill)
321 2 : .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
322 2 : .add(predOps(ARMCC::AL))
323 2 : .add(condCodeOp());
324 4 : BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
325 2 : .addReg(Reg, RegState::Kill)
326 2 : .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
327 2 : .add(predOps(ARMCC::AL))
328 2 : .add(condCodeOp());
329 : }
330 : } else {
331 : // Since this is only reached for Thumb-2 targets, the BFC instruction
332 : // should always be available.
333 : assert(CanUseBFC);
334 180 : BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
335 90 : .addReg(Reg, RegState::Kill)
336 90 : .addImm(~AlignMask)
337 90 : .add(predOps(ARMCC::AL));
338 : }
339 204 : }
340 :
341 : /// We need the offset of the frame pointer relative to other MachineFrameInfo
342 : /// offsets which are encoded relative to SP at function begin.
343 : /// See also emitPrologue() for how the FP is set up.
344 : /// Unfortunately we cannot determine this value in determineCalleeSaves() yet
345 : /// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use
346 : /// this to produce a conservative estimate that we check in an assert() later.
347 0 : static int getMaxFPOffset(const Function &F, const ARMFunctionInfo &AFI) {
348 : // This is a conservative estimation: Assume the frame pointer being r7 and
349 : // pc("r15") up to r8 getting spilled before (= 8 registers).
350 14694 : return -AFI.getArgRegsSaveSize() - (8 * 4);
351 : }
352 :
353 13425 : void ARMFrameLowering::emitPrologue(MachineFunction &MF,
354 : MachineBasicBlock &MBB) const {
355 13425 : MachineBasicBlock::iterator MBBI = MBB.begin();
356 13425 : MachineFrameInfo &MFI = MF.getFrameInfo();
357 13425 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
358 13425 : MachineModuleInfo &MMI = MF.getMMI();
359 : MCContext &Context = MMI.getContext();
360 13425 : const TargetMachine &TM = MF.getTarget();
361 13425 : const MCRegisterInfo *MRI = Context.getRegisterInfo();
362 13425 : const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
363 13425 : const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
364 : assert(!AFI->isThumb1OnlyFunction() &&
365 : "This emitPrologue does not support Thumb1!");
366 13425 : bool isARM = !AFI->isThumbFunction();
367 13425 : unsigned Align = STI.getFrameLowering()->getStackAlignment();
368 13425 : unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
369 13425 : unsigned NumBytes = MFI.getStackSize();
370 : const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
371 :
372 : // Debug location must be unknown since the first debug location is used
373 : // to determine the end of the prologue.
374 13425 : DebugLoc dl;
375 :
376 13425 : unsigned FramePtr = RegInfo->getFrameRegister(MF);
377 :
378 : // Determine the sizes of each callee-save spill areas and record which frame
379 : // belongs to which callee-save spill areas.
380 : unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
381 : int FramePtrSpillFI = 0;
382 : int D8SpillFI = 0;
383 :
384 : // All calls are tail calls in GHC calling conv, and functions have no
385 : // prologue/epilogue.
386 26850 : if (MF.getFunction().getCallingConv() == CallingConv::GHC)
387 : return;
388 :
389 : StackAdjustingInsts DefCFAOffsetCandidates;
390 13423 : bool HasFP = hasFP(MF);
391 :
392 : // Allocate the vararg register save area.
393 13423 : if (ArgRegsSaveSize) {
394 44 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
395 : MachineInstr::FrameSetup);
396 44 : DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
397 : }
398 :
399 13423 : if (!AFI->hasStackFrame() &&
400 9772 : (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
401 9772 : if (NumBytes - ArgRegsSaveSize != 0) {
402 390 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
403 : MachineInstr::FrameSetup);
404 390 : DefCFAOffsetCandidates.addInst(std::prev(MBBI),
405 : NumBytes - ArgRegsSaveSize, true);
406 : }
407 9772 : DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
408 : return;
409 : }
410 :
411 : // Determine spill area sizes.
412 18977 : for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
413 11675 : unsigned Reg = CSI[i].getReg();
414 11675 : int FI = CSI[i].getFrameIdx();
415 11675 : switch (Reg) {
416 2185 : case ARM::R8:
417 : case ARM::R9:
418 : case ARM::R10:
419 : case ARM::R11:
420 : case ARM::R12:
421 2185 : if (STI.splitFramePushPop(MF)) {
422 212 : GPRCS2Size += 4;
423 212 : break;
424 : }
425 : LLVM_FALLTHROUGH;
426 : case ARM::R0:
427 : case ARM::R1:
428 : case ARM::R2:
429 : case ARM::R3:
430 : case ARM::R4:
431 : case ARM::R5:
432 : case ARM::R6:
433 : case ARM::R7:
434 : case ARM::LR:
435 10126 : if (Reg == FramePtr)
436 : FramePtrSpillFI = FI;
437 10126 : GPRCS1Size += 4;
438 10126 : break;
439 1337 : default:
440 : // This is a DPR. Exclude the aligned DPRCS2 spills.
441 1337 : if (Reg == ARM::D8)
442 : D8SpillFI = FI;
443 1337 : if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
444 1065 : DPRCSSize += 8;
445 : }
446 : }
447 :
448 : // Move past area 1.
449 : MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
450 3651 : if (GPRCS1Size > 0) {
451 : GPRCS1Push = LastPush = MBBI++;
452 : DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
453 : }
454 :
455 : // Determine starting offsets of spill areas.
456 3651 : unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
457 3651 : unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
458 3738 : unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
459 3651 : unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
460 3651 : unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
461 : int FramePtrOffsetInPush = 0;
462 3651 : if (HasFP) {
463 : int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);
464 : assert(getMaxFPOffset(MF.getFunction(), *AFI) <= FPOffset &&
465 : "Max FP estimation is wrong");
466 974 : FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize;
467 974 : AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
468 : NumBytes);
469 : }
470 : AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
471 : AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
472 : AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
473 :
474 : // Move past area 2.
475 3651 : if (GPRCS2Size > 0) {
476 : GPRCS2Push = LastPush = MBBI++;
477 : DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
478 : }
479 :
480 : // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
481 : // .cfi_offset operations will reflect that.
482 3651 : if (DPRGapSize) {
483 : assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
484 29 : if (LastPush != MBB.end() &&
485 14 : tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))
486 2 : DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
487 : else {
488 13 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
489 : MachineInstr::FrameSetup);
490 13 : DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
491 : }
492 : }
493 :
494 : // Move past area 3.
495 3651 : if (DPRCSSize > 0) {
496 : // Since vpush register list cannot have gaps, there may be multiple vpush
497 : // instructions in the prologue.
498 532 : while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
499 280 : DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
500 : LastPush = MBBI++;
501 : }
502 : }
503 :
504 : // Move past the aligned DPRCS2 area.
505 3651 : if (AFI->getNumAlignedDPRCS2Regs() > 0) {
506 40 : MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
507 : // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
508 : // leaves the stack pointer pointing to the DPRCS2 area.
509 : //
510 : // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
511 40 : NumBytes += MFI.getObjectOffset(D8SpillFI);
512 : } else
513 : NumBytes = DPRCSOffset;
514 :
515 7302 : if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
516 3 : uint32_t NumWords = NumBytes >> 2;
517 :
518 3 : if (NumWords < 65536)
519 6 : BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
520 3 : .addImm(NumWords)
521 : .setMIFlags(MachineInstr::FrameSetup)
522 3 : .add(predOps(ARMCC::AL));
523 : else
524 0 : BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
525 0 : .addImm(NumWords)
526 : .setMIFlags(MachineInstr::FrameSetup);
527 :
528 3 : switch (TM.getCodeModel()) {
529 : case CodeModel::Tiny:
530 : llvm_unreachable("Tiny code model not available on ARM.");
531 1 : case CodeModel::Small:
532 : case CodeModel::Medium:
533 : case CodeModel::Kernel:
534 2 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
535 1 : .add(predOps(ARMCC::AL))
536 : .addExternalSymbol("__chkstk")
537 1 : .addReg(ARM::R4, RegState::Implicit)
538 : .setMIFlags(MachineInstr::FrameSetup);
539 1 : break;
540 2 : case CodeModel::Large:
541 4 : BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
542 : .addExternalSymbol("__chkstk")
543 : .setMIFlags(MachineInstr::FrameSetup);
544 :
545 4 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
546 2 : .add(predOps(ARMCC::AL))
547 2 : .addReg(ARM::R12, RegState::Kill)
548 2 : .addReg(ARM::R4, RegState::Implicit)
549 : .setMIFlags(MachineInstr::FrameSetup);
550 2 : break;
551 : }
552 :
553 6 : BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
554 3 : .addReg(ARM::SP, RegState::Kill)
555 3 : .addReg(ARM::R4, RegState::Kill)
556 : .setMIFlags(MachineInstr::FrameSetup)
557 3 : .add(predOps(ARMCC::AL))
558 3 : .add(condCodeOp());
559 : NumBytes = 0;
560 : }
561 :
562 3648 : if (NumBytes) {
563 : // Adjust SP after all the callee-save spills.
564 2249 : if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
565 1109 : tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
566 22 : DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
567 : else {
568 1118 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
569 : MachineInstr::FrameSetup);
570 1118 : DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
571 : }
572 :
573 1140 : if (HasFP && isARM)
574 : // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
575 : // Note it's not safe to do this in Thumb2 mode because it would have
576 : // taken two instructions:
577 : // mov sp, r7
578 : // sub sp, #24
579 : // If an interrupt is taken between the two instructions, then sp is in
580 : // an inconsistent state (pointing to the middle of callee-saved area).
581 : // The interrupt handler can end up clobbering the registers.
582 : AFI->setShouldRestoreSPFromFP(true);
583 : }
584 :
585 : // Set FP to point to the stack slot that contains the previous FP.
586 : // For iOS, FP is R7, which has now been stored in spill area 1.
587 : // Otherwise, if this is not iOS, all the callee-saved registers go
588 : // into spill area 1, including the FP in R11. In either case, it
589 : // is in area one and the adjustment needs to take place just after
590 : // that push.
591 3651 : if (HasFP) {
592 974 : MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
593 974 : unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
594 974 : emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
595 : dl, TII, FramePtr, ARM::SP,
596 974 : PushSize + FramePtrOffsetInPush,
597 : MachineInstr::FrameSetup);
598 974 : if (FramePtrOffsetInPush + PushSize != 0) {
599 480 : unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
600 480 : nullptr, MRI->getDwarfRegNum(FramePtr, true),
601 480 : -(ArgRegsSaveSize - FramePtrOffsetInPush)));
602 960 : BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
603 : .addCFIIndex(CFIIndex)
604 : .setMIFlags(MachineInstr::FrameSetup);
605 : } else {
606 : unsigned CFIIndex =
607 494 : MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
608 494 : nullptr, MRI->getDwarfRegNum(FramePtr, true)));
609 988 : BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
610 : .addCFIIndex(CFIIndex)
611 : .setMIFlags(MachineInstr::FrameSetup);
612 : }
613 : }
614 :
615 : // Now that the prologue's actual instructions are finalised, we can insert
616 : // the necessary DWARF cf instructions to describe the situation. Start by
617 : // recording where each register ended up:
618 3651 : if (GPRCS1Size > 0) {
619 3640 : MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
620 : int CFIIndex;
621 15251 : for (const auto &Entry : CSI) {
622 11611 : unsigned Reg = Entry.getReg();
623 11611 : int FI = Entry.getFrameIdx();
624 11611 : switch (Reg) {
625 2185 : case ARM::R8:
626 : case ARM::R9:
627 : case ARM::R10:
628 : case ARM::R11:
629 : case ARM::R12:
630 2185 : if (STI.splitFramePushPop(MF))
631 : break;
632 : LLVM_FALLTHROUGH;
633 : case ARM::R0:
634 : case ARM::R1:
635 : case ARM::R2:
636 : case ARM::R3:
637 : case ARM::R4:
638 : case ARM::R5:
639 : case ARM::R6:
640 : case ARM::R7:
641 : case ARM::LR:
642 10126 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
643 10126 : nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
644 20252 : BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
645 : .addCFIIndex(CFIIndex)
646 : .setMIFlags(MachineInstr::FrameSetup);
647 10126 : break;
648 : }
649 : }
650 : }
651 :
652 3651 : if (GPRCS2Size > 0) {
653 116 : MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
654 1229 : for (const auto &Entry : CSI) {
655 1113 : unsigned Reg = Entry.getReg();
656 1113 : int FI = Entry.getFrameIdx();
657 1113 : switch (Reg) {
658 212 : case ARM::R8:
659 : case ARM::R9:
660 : case ARM::R10:
661 : case ARM::R11:
662 : case ARM::R12:
663 212 : if (STI.splitFramePushPop(MF)) {
664 212 : unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
665 : unsigned Offset = MFI.getObjectOffset(FI);
666 : unsigned CFIIndex = MF.addFrameInst(
667 212 : MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
668 424 : BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
669 : .addCFIIndex(CFIIndex)
670 : .setMIFlags(MachineInstr::FrameSetup);
671 : }
672 : break;
673 : }
674 : }
675 : }
676 :
677 3651 : if (DPRCSSize > 0) {
678 : // Since vpush register list cannot have gaps, there may be multiple vpush
679 : // instructions in the prologue.
680 252 : MachineBasicBlock::iterator Pos = std::next(LastPush);
681 2113 : for (const auto &Entry : CSI) {
682 1861 : unsigned Reg = Entry.getReg();
683 1861 : int FI = Entry.getFrameIdx();
684 1861 : if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
685 940 : (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
686 1065 : unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
687 : unsigned Offset = MFI.getObjectOffset(FI);
688 : unsigned CFIIndex = MF.addFrameInst(
689 1065 : MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
690 2130 : BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
691 : .addCFIIndex(CFIIndex)
692 : .setMIFlags(MachineInstr::FrameSetup);
693 : }
694 : }
695 : }
696 :
697 : // Now we can emit descriptions of where the canonical frame address was
698 : // throughout the process. If we have a frame pointer, it takes over the job
699 : // half-way through, so only the first few .cfi_def_cfa_offset instructions
700 : // actually get emitted.
701 3651 : DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
702 :
703 7302 : if (STI.isTargetELF() && hasFP(MF))
704 766 : MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
705 383 : AFI->getFramePtrSpillOffset());
706 :
707 : AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
708 : AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
709 : AFI->setDPRCalleeSavedGapSize(DPRGapSize);
710 : AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
711 :
712 : // If we need dynamic stack realignment, do it here. Be paranoid and make
713 : // sure if we also have VLAs, we have a base pointer for frame access.
714 : // If aligned NEON registers were spilled, the stack has already been
715 : // realigned.
716 3651 : if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
717 164 : unsigned MaxAlign = MFI.getMaxAlignment();
718 : assert(!AFI->isThumb1OnlyFunction());
719 164 : if (!AFI->isThumbFunction()) {
720 98 : emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
721 : false);
722 : } else {
723 : // We cannot use sp as source/dest register here, thus we're using r4 to
724 : // perform the calculations. We're emitting the following sequence:
725 : // mov r4, sp
726 : // -- use emitAligningInstructions to produce best sequence to zero
727 : // -- out lower bits in r4
728 : // mov sp, r4
729 : // FIXME: It will be better just to find spare register here.
730 132 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
731 66 : .addReg(ARM::SP, RegState::Kill)
732 66 : .add(predOps(ARMCC::AL));
733 66 : emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
734 : false);
735 132 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
736 66 : .addReg(ARM::R4, RegState::Kill)
737 66 : .add(predOps(ARMCC::AL));
738 : }
739 :
740 : AFI->setShouldRestoreSPFromFP(true);
741 : }
742 :
743 : // If we need a base pointer, set it up here. It's whatever the value
744 : // of the stack pointer is at this point. Any variable size objects
745 : // will be allocated after this, so we can still use the base pointer
746 : // to reference locals.
747 : // FIXME: Clarify FrameSetup flags here.
748 3651 : if (RegInfo->hasBasePointer(MF)) {
749 6 : if (isARM)
750 6 : BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
751 3 : .addReg(ARM::SP)
752 3 : .add(predOps(ARMCC::AL))
753 3 : .add(condCodeOp());
754 : else
755 6 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
756 3 : .addReg(ARM::SP)
757 3 : .add(predOps(ARMCC::AL));
758 : }
759 :
760 : // If the frame has variable sized objects then the epilogue must restore
761 : // the sp from fp. We can assume there's an FP here since hasFP already
762 : // checks for hasVarSizedObjects.
763 3651 : if (MFI.hasVarSizedObjects())
764 : AFI->setShouldRestoreSPFromFP(true);
765 : }
766 :
767 13453 : void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
768 : MachineBasicBlock &MBB) const {
769 13453 : MachineFrameInfo &MFI = MF.getFrameInfo();
770 13453 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
771 13453 : const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
772 : const ARMBaseInstrInfo &TII =
773 13453 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
774 : assert(!AFI->isThumb1OnlyFunction() &&
775 : "This emitEpilogue does not support Thumb1!");
776 13453 : bool isARM = !AFI->isThumbFunction();
777 :
778 13453 : unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
779 13453 : int NumBytes = (int)MFI.getStackSize();
780 13453 : unsigned FramePtr = RegInfo->getFrameRegister(MF);
781 :
782 : // All calls are tail calls in GHC calling conv, and functions have no
783 : // prologue/epilogue.
784 26906 : if (MF.getFunction().getCallingConv() == CallingConv::GHC)
785 2 : return;
786 :
787 : // First put ourselves on the first (from top) terminator instructions.
788 13451 : MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
789 13451 : DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
790 :
791 13451 : if (!AFI->hasStackFrame()) {
792 9853 : if (NumBytes - ArgRegsSaveSize != 0)
793 388 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
794 : } else {
795 : // Unwind MBBI to point to first LDR / VLDRD.
796 3598 : const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
797 3598 : if (MBBI != MBB.begin()) {
798 : do {
799 : --MBBI;
800 4922 : } while (MBBI != MBB.begin() && isCSRestore(*MBBI, TII, CSRegs));
801 3455 : if (!isCSRestore(*MBBI, TII, CSRegs))
802 : ++MBBI;
803 : }
804 :
805 : // Move SP to start of FP callee save spill area.
806 7196 : NumBytes -= (ArgRegsSaveSize +
807 7196 : AFI->getGPRCalleeSavedArea1Size() +
808 7196 : AFI->getGPRCalleeSavedArea2Size() +
809 7196 : AFI->getDPRCalleeSavedGapSize() +
810 3598 : AFI->getDPRCalleeSavedAreaSize());
811 :
812 : // Reset SP based on frame pointer only if the stack frame extends beyond
813 : // frame pointer stack slot or target is ELF and the function has FP.
814 3598 : if (AFI->shouldRestoreSPFromFP()) {
815 382 : NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
816 382 : if (NumBytes) {
817 254 : if (isARM)
818 154 : emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
819 : ARMCC::AL, 0, TII);
820 : else {
821 : // It's not possible to restore SP from FP in a single instruction.
822 : // For iOS, this looks like:
823 : // mov sp, r7
824 : // sub sp, #24
825 : // This is bad, if an interrupt is taken after the mov, sp is in an
826 : // inconsistent state.
827 : // Use the first callee-saved register as a scratch register.
828 : assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
829 : "No scratch register to restore SP from FP!");
830 100 : emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
831 : ARMCC::AL, 0, TII);
832 200 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
833 100 : .addReg(ARM::R4)
834 100 : .add(predOps(ARMCC::AL));
835 : }
836 : } else {
837 : // Thumb2 or ARM.
838 128 : if (isARM)
839 256 : BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
840 128 : .addReg(FramePtr)
841 128 : .add(predOps(ARMCC::AL))
842 128 : .add(condCodeOp());
843 : else
844 0 : BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
845 0 : .addReg(FramePtr)
846 0 : .add(predOps(ARMCC::AL));
847 : }
848 3976 : } else if (NumBytes &&
849 760 : !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
850 746 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
851 :
852 : // Increment past our save areas.
853 3598 : if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
854 : MBBI++;
855 : // Since vpop register list cannot have gaps, there may be multiple vpop
856 : // instructions in the epilogue.
857 289 : while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
858 : MBBI++;
859 : }
860 3598 : if (AFI->getDPRCalleeSavedGapSize()) {
861 : assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
862 : "unexpected DPR alignment gap");
863 13 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
864 : }
865 :
866 3598 : if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
867 3598 : if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
868 : }
869 :
870 13451 : if (ArgRegsSaveSize)
871 44 : emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
872 : }
873 :
874 : /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
875 : /// debug info. It's the same as what we use for resolving the code-gen
876 : /// references for now. FIXME: This can go wrong when references are
877 : /// SP-relative and simple call frames aren't used.
878 : int
879 22 : ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
880 : unsigned &FrameReg) const {
881 22 : return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
882 : }
883 :
884 : int
885 15229 : ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
886 : int FI, unsigned &FrameReg,
887 : int SPAdj) const {
888 15229 : const MachineFrameInfo &MFI = MF.getFrameInfo();
889 : const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
890 15229 : MF.getSubtarget().getRegisterInfo());
891 : const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
892 15229 : int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
893 15229 : int FPOffset = Offset - AFI->getFramePtrSpillOffset();
894 : bool isFixed = MFI.isFixedObjectIndex(FI);
895 :
896 15229 : FrameReg = ARM::SP;
897 15229 : Offset += SPAdj;
898 :
899 : // SP can move around if there are allocas. We may also lose track of SP
900 : // when emergency spilling inside a non-reserved call frame setup.
901 15229 : bool hasMovingSP = !hasReservedCallFrame(MF);
902 :
903 : // When dynamically realigning the stack, use the frame pointer for
904 : // parameters, and the stack/base pointer for locals.
905 15229 : if (RegInfo->needsStackRealignment(MF)) {
906 : assert(hasFP(MF) && "dynamic stack realignment without a FP!");
907 7225 : if (isFixed) {
908 66 : FrameReg = RegInfo->getFrameRegister(MF);
909 : Offset = FPOffset;
910 7159 : } else if (hasMovingSP) {
911 : assert(RegInfo->hasBasePointer(MF) &&
912 : "VLAs and dynamic stack alignment, but missing base pointer!");
913 468 : FrameReg = RegInfo->getBaseRegister();
914 : }
915 7225 : return Offset;
916 : }
917 :
918 : // If there is a frame pointer, use it when we can.
919 8004 : if (hasFP(MF) && AFI->hasStackFrame()) {
920 : // Use frame pointer to reference fixed objects. Use it for locals if
921 : // there are VLAs (and thus the SP isn't reliable as a base).
922 1679 : if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
923 272 : FrameReg = RegInfo->getFrameRegister(MF);
924 272 : return FPOffset;
925 1407 : } else if (hasMovingSP) {
926 : assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
927 35 : if (AFI->isThumb2Function()) {
928 : // Try to use the frame pointer if we can, else use the base pointer
929 : // since it's available. This is handy for the emergency spill slot, in
930 : // particular.
931 0 : if (FPOffset >= -255 && FPOffset < 0) {
932 0 : FrameReg = RegInfo->getFrameRegister(MF);
933 0 : return FPOffset;
934 : }
935 : }
936 1372 : } else if (AFI->isThumbFunction()) {
937 : // Prefer SP to base pointer, if the offset is suitably aligned and in
938 : // range as the effective range of the immediate offset is bigger when
939 : // basing off SP.
940 : // Use add <rd>, sp, #<imm8>
941 : // ldr <rd>, [sp, #<imm8>]
942 516 : if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
943 : return Offset;
944 : // In Thumb2 mode, the negative offset is very limited. Try to avoid
945 : // out of range references. ldr <rt>,[<rn>, #-<imm8>]
946 24 : if (AFI->isThumb2Function() && FPOffset >= -255 && FPOffset < 0) {
947 24 : FrameReg = RegInfo->getFrameRegister(MF);
948 24 : return FPOffset;
949 : }
950 856 : } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
951 : // Otherwise, use SP or FP, whichever is closer to the stack slot.
952 253 : FrameReg = RegInfo->getFrameRegister(MF);
953 253 : return FPOffset;
954 : }
955 : }
956 : // Use the base pointer if we have one.
957 6965 : if (RegInfo->hasBasePointer(MF))
958 35 : FrameReg = RegInfo->getBaseRegister();
959 : return Offset;
960 : }
961 :
962 10953 : void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
963 : MachineBasicBlock::iterator MI,
964 : const std::vector<CalleeSavedInfo> &CSI,
965 : unsigned StmOpc, unsigned StrOpc,
966 : bool NoGap,
967 : bool(*Func)(unsigned, bool),
968 : unsigned NumAlignedDPRCS2Regs,
969 : unsigned MIFlags) const {
970 10953 : MachineFunction &MF = *MBB.getParent();
971 10953 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
972 10953 : const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
973 :
974 10953 : DebugLoc DL;
975 :
976 : using RegAndKill = std::pair<unsigned, bool>;
977 :
978 : SmallVector<RegAndKill, 4> Regs;
979 21906 : unsigned i = CSI.size();
980 21934 : while (i != 0) {
981 : unsigned LastReg = 0;
982 46006 : for (; i != 0; --i) {
983 35053 : unsigned Reg = CSI[i-1].getReg();
984 35053 : if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
985 :
986 : // D-registers in the aligned area DPRCS2 are NOT spilled here.
987 11703 : if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
988 : continue;
989 :
990 11431 : const MachineRegisterInfo &MRI = MF.getRegInfo();
991 11431 : bool isLiveIn = MRI.isLiveIn(Reg);
992 11431 : if (!isLiveIn && !MRI.isReserved(Reg))
993 10429 : MBB.addLiveIn(Reg);
994 : // If NoGap is true, push consecutive registers and then leave the rest
995 : // for other instructions. e.g.
996 : // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
997 11431 : if (NoGap && LastReg && LastReg != Reg-1)
998 : break;
999 : LastReg = Reg;
1000 : // Do not set a kill flag on values that are also marked as live-in. This
1001 : // happens with the @llvm-returnaddress intrinsic and with arguments
1002 : // passed in callee saved registers.
1003 : // Omitting the kill flags is conservatively correct even if the live-in
1004 : // is not used after all.
1005 11403 : Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
1006 : }
1007 :
1008 10981 : if (Regs.empty())
1009 : continue;
1010 :
1011 : llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) {
1012 15000 : return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
1013 : });
1014 :
1015 8072 : if (Regs.size() > 1 || StrOpc== 0) {
1016 7500 : MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1017 3750 : .addReg(ARM::SP)
1018 : .setMIFlags(MIFlags)
1019 3750 : .add(predOps(ARMCC::AL));
1020 14867 : for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1021 22243 : MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1022 286 : } else if (Regs.size() == 1) {
1023 572 : BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1024 298 : .addReg(Regs[0].first, getKillRegState(Regs[0].second))
1025 286 : .addReg(ARM::SP)
1026 : .setMIFlags(MIFlags)
1027 : .addImm(-4)
1028 286 : .add(predOps(ARMCC::AL));
1029 : }
1030 : Regs.clear();
1031 :
1032 : // Put any subsequent vpush instructions before this one: they will refer to
1033 : // higher register numbers so need to be pushed first in order to preserve
1034 : // monotonicity.
1035 4036 : if (MI != MBB.begin())
1036 : --MI;
1037 : }
1038 10953 : }
1039 :
1040 10794 : void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
1041 : MachineBasicBlock::iterator MI,
1042 : std::vector<CalleeSavedInfo> &CSI,
1043 : unsigned LdmOpc, unsigned LdrOpc,
1044 : bool isVarArg, bool NoGap,
1045 : bool(*Func)(unsigned, bool),
1046 : unsigned NumAlignedDPRCS2Regs) const {
1047 10794 : MachineFunction &MF = *MBB.getParent();
1048 10794 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1049 10794 : const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1050 10794 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1051 10794 : DebugLoc DL;
1052 : bool isTailCall = false;
1053 : bool isInterrupt = false;
1054 : bool isTrap = false;
1055 10794 : if (MBB.end() != MI) {
1056 : DL = MI->getDebugLoc();
1057 10719 : unsigned RetOpcode = MI->getOpcode();
1058 10719 : isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
1059 10719 : isInterrupt =
1060 10719 : RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
1061 10719 : isTrap =
1062 10719 : RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
1063 10719 : RetOpcode == ARM::tTRAP;
1064 : }
1065 :
1066 : SmallVector<unsigned, 4> Regs;
1067 21588 : unsigned i = CSI.size();
1068 21614 : while (i != 0) {
1069 : unsigned LastReg = 0;
1070 : bool DeleteRet = false;
1071 45149 : for (; i != 0; --i) {
1072 34355 : CalleeSavedInfo &Info = CSI[i-1];
1073 34355 : unsigned Reg = Info.getReg();
1074 34563 : if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
1075 :
1076 : // The aligned reloads from area DPRCS2 are not inserted here.
1077 11469 : if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1078 : continue;
1079 :
1080 3549 : if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1081 14666 : !isTrap && STI.hasV5TOps()) {
1082 2620 : if (MBB.succ_empty()) {
1083 2584 : Reg = ARM::PC;
1084 : // Fold the return instruction into the LDM.
1085 : DeleteRet = true;
1086 2584 : LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
1087 : // We 'restore' LR into PC so it is not live out of the return block:
1088 : // Clear Restored bit.
1089 : Info.setRestored(false);
1090 : } else
1091 36 : LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1092 : }
1093 :
1094 : // If NoGap is true, pop consecutive registers and then leave the rest
1095 : // for other instructions. e.g.
1096 : // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1097 11261 : if (NoGap && LastReg && LastReg != Reg-1)
1098 : break;
1099 :
1100 11235 : LastReg = Reg;
1101 11235 : Regs.push_back(Reg);
1102 : }
1103 :
1104 10820 : if (Regs.empty())
1105 : continue;
1106 :
1107 : llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) {
1108 7244 : return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1109 : });
1110 :
1111 7982 : if (Regs.size() > 1 || LdrOpc == 0) {
1112 7428 : MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1113 3714 : .addReg(ARM::SP)
1114 3714 : .add(predOps(ARMCC::AL));
1115 14672 : for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1116 21916 : MIB.addReg(Regs[i], getDefRegState(true));
1117 3714 : if (DeleteRet) {
1118 2441 : if (MI != MBB.end()) {
1119 : MIB.copyImplicitOps(*MI);
1120 2441 : MI->eraseFromParent();
1121 : }
1122 : }
1123 3714 : MI = MIB;
1124 277 : } else if (Regs.size() == 1) {
1125 : // If we adjusted the reg to PC from LR above, switch it back here. We
1126 : // only do that for LDM.
1127 277 : if (Regs[0] == ARM::PC)
1128 143 : Regs[0] = ARM::LR;
1129 : MachineInstrBuilder MIB =
1130 554 : BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1131 277 : .addReg(ARM::SP, RegState::Define)
1132 277 : .addReg(ARM::SP);
1133 : // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1134 : // that refactoring is complete (eventually).
1135 277 : if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1136 198 : MIB.addReg(0);
1137 : MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1138 : } else
1139 : MIB.addImm(4);
1140 277 : MIB.add(predOps(ARMCC::AL));
1141 : }
1142 : Regs.clear();
1143 :
1144 : // Put any subsequent vpop instructions after this one: they will refer to
1145 : // higher register numbers so need to be popped afterwards.
1146 3991 : if (MI != MBB.end())
1147 : ++MI;
1148 : }
1149 10794 : }
1150 :
1151 : /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1152 : /// starting from d8. Also insert stack realignment code and leave the stack
1153 : /// pointer pointing to the d8 spill slot.
1154 40 : static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1155 : MachineBasicBlock::iterator MI,
1156 : unsigned NumAlignedDPRCS2Regs,
1157 : const std::vector<CalleeSavedInfo> &CSI,
1158 : const TargetRegisterInfo *TRI) {
1159 40 : MachineFunction &MF = *MBB.getParent();
1160 40 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1161 40 : DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1162 40 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1163 40 : MachineFrameInfo &MFI = MF.getFrameInfo();
1164 :
1165 : // Mark the D-register spill slots as properly aligned. Since MFI computes
1166 : // stack slot layout backwards, this can actually mean that the d-reg stack
1167 : // slot offsets can be wrong. The offset for d8 will always be correct.
1168 604 : for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1169 524 : unsigned DNum = CSI[i].getReg() - ARM::D8;
1170 524 : if (DNum > NumAlignedDPRCS2Regs - 1)
1171 : continue;
1172 272 : int FI = CSI[i].getFrameIdx();
1173 : // The even-numbered registers will be 16-byte aligned, the odd-numbered
1174 : // registers will be 8-byte aligned.
1175 272 : MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1176 :
1177 : // The stack slot for D8 needs to be maximally aligned because this is
1178 : // actually the point where we align the stack pointer. MachineFrameInfo
1179 : // computes all offsets relative to the incoming stack pointer which is a
1180 : // bit weird when realigning the stack. Any extra padding for this
1181 : // over-alignment is not realized because the code inserted below adjusts
1182 : // the stack pointer by numregs * 8 before aligning the stack pointer.
1183 272 : if (DNum == 0)
1184 40 : MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1185 : }
1186 :
1187 : // Move the stack pointer to the d8 spill slot, and align it at the same
1188 : // time. Leave the stack slot address in the scratch register r4.
1189 : //
1190 : // sub r4, sp, #numregs * 8
1191 : // bic r4, r4, #align - 1
1192 : // mov sp, r4
1193 : //
1194 40 : bool isThumb = AFI->isThumbFunction();
1195 : assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1196 : AFI->setShouldRestoreSPFromFP(true);
1197 :
1198 : // sub r4, sp, #numregs * 8
1199 : // The immediate is <= 64, so it doesn't need any special encoding.
1200 40 : unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1201 80 : BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1202 40 : .addReg(ARM::SP)
1203 40 : .addImm(8 * NumAlignedDPRCS2Regs)
1204 40 : .add(predOps(ARMCC::AL))
1205 40 : .add(condCodeOp());
1206 :
1207 40 : unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
1208 : // We must set parameter MustBeSingleInstruction to true, since
1209 : // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1210 : // stack alignment. Luckily, this can always be done since all ARM
1211 : // architecture versions that support Neon also support the BFC
1212 : // instruction.
1213 40 : emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1214 :
1215 : // mov sp, r4
1216 : // The stack pointer must be adjusted before spilling anything, otherwise
1217 : // the stack slots could be clobbered by an interrupt handler.
1218 : // Leave r4 live, it is used below.
1219 40 : Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1220 80 : MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1221 40 : .addReg(ARM::R4)
1222 40 : .add(predOps(ARMCC::AL));
1223 40 : if (!isThumb)
1224 16 : MIB.add(condCodeOp());
1225 :
1226 : // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1227 : // r4 holds the stack slot address.
1228 : unsigned NextReg = ARM::D8;
1229 :
1230 : // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1231 : // The writeback is only needed when emitting two vst1.64 instructions.
1232 40 : if (NumAlignedDPRCS2Regs >= 6) {
1233 32 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1234 : &ARM::QQPRRegClass);
1235 32 : MBB.addLiveIn(SupReg);
1236 64 : BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1237 32 : .addReg(ARM::R4, RegState::Kill)
1238 : .addImm(16)
1239 32 : .addReg(NextReg)
1240 32 : .addReg(SupReg, RegState::ImplicitKill)
1241 32 : .add(predOps(ARMCC::AL));
1242 : NextReg += 4;
1243 32 : NumAlignedDPRCS2Regs -= 4;
1244 : }
1245 :
1246 : // We won't modify r4 beyond this point. It currently points to the next
1247 : // register to be spilled.
1248 : unsigned R4BaseReg = NextReg;
1249 :
1250 : // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1251 40 : if (NumAlignedDPRCS2Regs >= 4) {
1252 31 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1253 : &ARM::QQPRRegClass);
1254 31 : MBB.addLiveIn(SupReg);
1255 62 : BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1256 31 : .addReg(ARM::R4)
1257 : .addImm(16)
1258 31 : .addReg(NextReg)
1259 31 : .addReg(SupReg, RegState::ImplicitKill)
1260 31 : .add(predOps(ARMCC::AL));
1261 31 : NextReg += 4;
1262 31 : NumAlignedDPRCS2Regs -= 4;
1263 : }
1264 :
1265 : // 16-byte aligned vst1.64 with 2 d-regs.
1266 40 : if (NumAlignedDPRCS2Regs >= 2) {
1267 9 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1268 : &ARM::QPRRegClass);
1269 9 : MBB.addLiveIn(SupReg);
1270 18 : BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1271 9 : .addReg(ARM::R4)
1272 : .addImm(16)
1273 9 : .addReg(SupReg)
1274 9 : .add(predOps(ARMCC::AL));
1275 9 : NextReg += 2;
1276 9 : NumAlignedDPRCS2Regs -= 2;
1277 : }
1278 :
1279 : // Finally, use a vanilla vstr.64 for the odd last register.
1280 40 : if (NumAlignedDPRCS2Regs) {
1281 2 : MBB.addLiveIn(NextReg);
1282 : // vstr.64 uses addrmode5 which has an offset scale of 4.
1283 4 : BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1284 2 : .addReg(NextReg)
1285 2 : .addReg(ARM::R4)
1286 2 : .addImm((NextReg - R4BaseReg) * 2)
1287 2 : .add(predOps(ARMCC::AL));
1288 : }
1289 :
1290 : // The last spill instruction inserted should kill the scratch register r4.
1291 40 : std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1292 40 : }
1293 :
1294 : /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1295 : /// iterator to the following instruction.
1296 : static MachineBasicBlock::iterator
1297 40 : skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1298 : unsigned NumAlignedDPRCS2Regs) {
1299 : // sub r4, sp, #numregs * 8
1300 : // bic r4, r4, #align - 1
1301 : // mov sp, r4
1302 : ++MI; ++MI; ++MI;
1303 : assert(MI->mayStore() && "Expecting spill instruction");
1304 :
1305 : // These switches all fall through.
1306 40 : switch(NumAlignedDPRCS2Regs) {
1307 : case 7:
1308 : ++MI;
1309 : assert(MI->mayStore() && "Expecting spill instruction");
1310 : LLVM_FALLTHROUGH;
1311 33 : default:
1312 : ++MI;
1313 : assert(MI->mayStore() && "Expecting spill instruction");
1314 : LLVM_FALLTHROUGH;
1315 40 : case 1:
1316 : case 2:
1317 : case 4:
1318 : assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1319 : ++MI;
1320 : }
1321 40 : return MI;
1322 : }
1323 :
1324 : /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1325 : /// starting from d8. These instructions are assumed to execute while the
1326 : /// stack is still aligned, unlike the code inserted by emitPopInst.
1327 32 : static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1328 : MachineBasicBlock::iterator MI,
1329 : unsigned NumAlignedDPRCS2Regs,
1330 : const std::vector<CalleeSavedInfo> &CSI,
1331 : const TargetRegisterInfo *TRI) {
1332 32 : MachineFunction &MF = *MBB.getParent();
1333 32 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1334 32 : DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1335 32 : const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1336 :
1337 : // Find the frame index assigned to d8.
1338 : int D8SpillFI = 0;
1339 428 : for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1340 792 : if (CSI[i].getReg() == ARM::D8) {
1341 32 : D8SpillFI = CSI[i].getFrameIdx();
1342 32 : break;
1343 : }
1344 :
1345 : // Materialize the address of the d8 spill slot into the scratch register r4.
1346 : // This can be fairly complicated if the stack frame is large, so just use
1347 : // the normal frame index elimination mechanism to do it. This code runs as
1348 : // the initial part of the epilog where the stack and base pointers haven't
1349 : // been changed yet.
1350 32 : bool isThumb = AFI->isThumbFunction();
1351 : assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1352 :
1353 32 : unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1354 64 : BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1355 : .addFrameIndex(D8SpillFI)
1356 : .addImm(0)
1357 32 : .add(predOps(ARMCC::AL))
1358 32 : .add(condCodeOp());
1359 :
1360 : // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1361 : unsigned NextReg = ARM::D8;
1362 :
1363 : // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1364 32 : if (NumAlignedDPRCS2Regs >= 6) {
1365 24 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1366 : &ARM::QQPRRegClass);
1367 48 : BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1368 24 : .addReg(ARM::R4, RegState::Define)
1369 24 : .addReg(ARM::R4, RegState::Kill)
1370 : .addImm(16)
1371 24 : .addReg(SupReg, RegState::ImplicitDefine)
1372 24 : .add(predOps(ARMCC::AL));
1373 : NextReg += 4;
1374 24 : NumAlignedDPRCS2Regs -= 4;
1375 : }
1376 :
1377 : // We won't modify r4 beyond this point. It currently points to the next
1378 : // register to be spilled.
1379 : unsigned R4BaseReg = NextReg;
1380 :
1381 : // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1382 32 : if (NumAlignedDPRCS2Regs >= 4) {
1383 23 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1384 : &ARM::QQPRRegClass);
1385 46 : BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1386 23 : .addReg(ARM::R4)
1387 : .addImm(16)
1388 23 : .addReg(SupReg, RegState::ImplicitDefine)
1389 23 : .add(predOps(ARMCC::AL));
1390 23 : NextReg += 4;
1391 23 : NumAlignedDPRCS2Regs -= 4;
1392 : }
1393 :
1394 : // 16-byte aligned vld1.64 with 2 d-regs.
1395 32 : if (NumAlignedDPRCS2Regs >= 2) {
1396 9 : unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1397 : &ARM::QPRRegClass);
1398 18 : BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1399 9 : .addReg(ARM::R4)
1400 : .addImm(16)
1401 9 : .add(predOps(ARMCC::AL));
1402 9 : NextReg += 2;
1403 9 : NumAlignedDPRCS2Regs -= 2;
1404 : }
1405 :
1406 : // Finally, use a vanilla vldr.64 for the remaining odd register.
1407 32 : if (NumAlignedDPRCS2Regs)
1408 4 : BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1409 2 : .addReg(ARM::R4)
1410 2 : .addImm(2 * (NextReg - R4BaseReg))
1411 2 : .add(predOps(ARMCC::AL));
1412 :
1413 : // Last store kills r4.
1414 32 : std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1415 32 : }
1416 :
1417 3651 : bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1418 : MachineBasicBlock::iterator MI,
1419 : const std::vector<CalleeSavedInfo> &CSI,
1420 : const TargetRegisterInfo *TRI) const {
1421 3651 : if (CSI.empty())
1422 : return false;
1423 :
1424 3651 : MachineFunction &MF = *MBB.getParent();
1425 3651 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1426 :
1427 3651 : unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1428 3651 : unsigned PushOneOpc = AFI->isThumbFunction() ?
1429 : ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1430 : unsigned FltOpc = ARM::VSTMDDB_UPD;
1431 3651 : unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1432 3651 : emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1433 : MachineInstr::FrameSetup);
1434 3651 : emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1435 : MachineInstr::FrameSetup);
1436 3651 : emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1437 : NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1438 :
1439 : // The code above does not insert spill code for the aligned DPRCS2 registers.
1440 : // The stack realignment code will be inserted between the push instructions
1441 : // and these spills.
1442 3651 : if (NumAlignedDPRCS2Regs)
1443 40 : emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1444 :
1445 : return true;
1446 : }
1447 :
1448 3598 : bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1449 : MachineBasicBlock::iterator MI,
1450 : std::vector<CalleeSavedInfo> &CSI,
1451 : const TargetRegisterInfo *TRI) const {
1452 3598 : if (CSI.empty())
1453 : return false;
1454 :
1455 3598 : MachineFunction &MF = *MBB.getParent();
1456 3598 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1457 3598 : bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1458 3598 : unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1459 :
1460 : // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1461 : // registers. Do that here instead.
1462 3598 : if (NumAlignedDPRCS2Regs)
1463 32 : emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1464 :
1465 3598 : unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1466 3598 : unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1467 : unsigned FltOpc = ARM::VLDMDIA_UPD;
1468 3598 : emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1469 : NumAlignedDPRCS2Regs);
1470 3598 : emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1471 : &isARMArea2Register, 0);
1472 3598 : emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1473 : &isARMArea1Register, 0);
1474 :
1475 3598 : return true;
1476 : }
1477 :
1478 : // FIXME: Make generic?
1479 653 : static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1480 : const ARMBaseInstrInfo &TII) {
1481 : unsigned FnSize = 0;
1482 2011 : for (auto &MBB : MF) {
1483 7203 : for (auto &MI : MBB)
1484 5845 : FnSize += TII.getInstSizeInBytes(MI);
1485 : }
1486 653 : return FnSize;
1487 : }
1488 :
1489 : /// estimateRSStackSizeLimit - Look at each instruction that references stack
1490 : /// frames and return the stack size limit beyond which some of these
1491 : /// instructions will require a scratch register during their expansion later.
1492 : // FIXME: Move to TII?
1493 14694 : static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1494 : const TargetFrameLowering *TFI) {
1495 14694 : const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1496 14694 : unsigned Limit = (1 << 12) - 1;
1497 35277 : for (auto &MBB : MF) {
1498 142594 : for (auto &MI : MBB) {
1499 633274 : for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1500 1051202 : if (!MI.getOperand(i).isFI())
1501 : continue;
1502 :
1503 : // When using ADDri to get the address of a stack object, 255 is the
1504 : // largest offset guaranteed to fit in the immediate offset.
1505 28676 : if (MI.getOpcode() == ARM::ADDri) {
1506 1254 : Limit = std::min(Limit, (1U << 8) - 1);
1507 1254 : break;
1508 : }
1509 :
1510 : // Otherwise check the addressing mode.
1511 13084 : switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1512 70 : case ARMII::AddrMode3:
1513 : case ARMII::AddrModeT2_i8:
1514 70 : Limit = std::min(Limit, (1U << 8) - 1);
1515 70 : break;
1516 1339 : case ARMII::AddrMode5:
1517 : case ARMII::AddrModeT2_i8s4:
1518 : case ARMII::AddrModeT2_ldrex:
1519 1339 : Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1520 1339 : break;
1521 3103 : case ARMII::AddrModeT2_i12:
1522 : // i12 supports only positive offset so these will be converted to
1523 : // i8 opcodes. See llvm::rewriteT2FrameIndex.
1524 3103 : if (TFI->hasFP(MF) && AFI->hasStackFrame())
1525 0 : Limit = std::min(Limit, (1U << 8) - 1);
1526 : break;
1527 : case ARMII::AddrMode4:
1528 : case ARMII::AddrMode6:
1529 : // Addressing modes 4 & 6 (load/store) instructions can't encode an
1530 : // immediate offset for stack references.
1531 : return 0;
1532 : default:
1533 : break;
1534 : }
1535 : break; // At most one FI per instruction
1536 : }
1537 : }
1538 : }
1539 :
1540 14673 : return Limit;
1541 : }
1542 :
1543 : // In functions that realign the stack, it can be an advantage to spill the
1544 : // callee-saved vector registers after realigning the stack. The vst1 and vld1
1545 : // instructions take alignment hints that can improve performance.
1546 : static void
1547 14694 : checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1548 14694 : MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1549 14694 : if (!SpillAlignedNEONRegs)
1550 : return;
1551 :
1552 : // Naked functions don't spill callee-saved registers.
1553 14691 : if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1554 : return;
1555 :
1556 : // We are planning to use NEON instructions vst1 / vld1.
1557 14690 : if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1558 : return;
1559 :
1560 : // Don't bother if the default stack alignment is sufficiently high.
1561 8371 : if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1562 : return;
1563 :
1564 : // Aligned spills require stack realignment.
1565 1841 : if (!static_cast<const ARMBaseRegisterInfo *>(
1566 1841 : MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1567 : return;
1568 :
1569 : // We always spill contiguous d-registers starting from d8. Count how many
1570 : // needs spilling. The register allocator will almost always use the
1571 : // callee-saved registers in order, but it can happen that there are holes in
1572 : // the range. Registers above the hole will be spilled to the standard DPRCS
1573 : // area.
1574 : unsigned NumSpills = 0;
1575 1106 : for (; NumSpills < 8; ++NumSpills)
1576 2150 : if (!SavedRegs.test(ARM::D8 + NumSpills))
1577 : break;
1578 :
1579 : // Don't do this for just one d-register. It's not worth it.
1580 829 : if (NumSpills < 2)
1581 : return;
1582 :
1583 : // Spill the first NumSpills D-registers after realigning the stack.
1584 40 : MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1585 :
1586 : // A scratch register is required for the vst1 / vld1 instructions.
1587 : SavedRegs.set(ARM::R4);
1588 : }
1589 :
1590 14694 : void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1591 : BitVector &SavedRegs,
1592 : RegScavenger *RS) const {
1593 14694 : TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1594 : // This tells PEI to spill the FP as if it is any other callee-save register
1595 : // to take advantage the eliminateFrameIndex machinery. This also ensures it
1596 : // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1597 : // to combine multiple loads / stores.
1598 : bool CanEliminateFrame = true;
1599 : bool CS1Spilled = false;
1600 : bool LRSpilled = false;
1601 : unsigned NumGPRSpills = 0;
1602 : unsigned NumFPRSpills = 0;
1603 : SmallVector<unsigned, 4> UnspilledCS1GPRs;
1604 : SmallVector<unsigned, 4> UnspilledCS2GPRs;
1605 : const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1606 14694 : MF.getSubtarget().getRegisterInfo());
1607 : const ARMBaseInstrInfo &TII =
1608 14694 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1609 14694 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1610 14694 : MachineFrameInfo &MFI = MF.getFrameInfo();
1611 14694 : MachineRegisterInfo &MRI = MF.getRegInfo();
1612 14694 : const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1613 : (void)TRI; // Silence unused warning in non-assert builds.
1614 14694 : unsigned FramePtr = RegInfo->getFrameRegister(MF);
1615 :
1616 : // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1617 : // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1618 : // since it's not always possible to restore sp from fp in a single
1619 : // instruction.
1620 : // FIXME: It will be better just to find spare register here.
1621 14694 : if (AFI->isThumb2Function() &&
1622 5021 : (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1623 : SavedRegs.set(ARM::R4);
1624 :
1625 : // If a stack probe will be emitted, spill R4 and LR, since they are
1626 : // clobbered by the stack probe call.
1627 : // This estimate should be a safe, conservative estimate. The actual
1628 : // stack probe is enabled based on the size of the local objects;
1629 : // this estimate also includes the varargs store size.
1630 29560 : if (STI.isTargetWindows() &&
1631 172 : WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))) {
1632 : SavedRegs.set(ARM::R4);
1633 : SavedRegs.set(ARM::LR);
1634 : }
1635 :
1636 14694 : if (AFI->isThumb1OnlyFunction()) {
1637 : // Spill LR if Thumb1 function uses variable length argument lists.
1638 1178 : if (AFI->getArgRegsSaveSize() > 0)
1639 : SavedRegs.set(ARM::LR);
1640 :
1641 : // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function
1642 : // requires stack alignment. We don't know for sure what the stack size
1643 : // will be, but for this, an estimate is good enough. If there anything
1644 : // changes it, it'll be a spill, which implies we've used all the registers
1645 : // and so R4 is already used, so not marking it here will be OK.
1646 : // FIXME: It will be better just to find spare register here.
1647 2303 : if (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) ||
1648 1125 : MFI.estimateStackSize(MF) > 508)
1649 : SavedRegs.set(ARM::R4);
1650 : }
1651 :
1652 : // See if we can spill vector registers to aligned stack.
1653 14694 : checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1654 :
1655 : // Spill the BasePtr if it's used.
1656 14694 : if (RegInfo->hasBasePointer(MF))
1657 24 : SavedRegs.set(RegInfo->getBaseRegister());
1658 :
1659 : // Don't spill FP if the frame can be eliminated. This is determined
1660 : // by scanning the callee-save registers to see if any is modified.
1661 14694 : const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1662 262344 : for (unsigned i = 0; CSRegs[i]; ++i) {
1663 247650 : unsigned Reg = CSRegs[i];
1664 : bool Spilled = false;
1665 247650 : if (SavedRegs.test(Reg)) {
1666 : Spilled = true;
1667 : CanEliminateFrame = false;
1668 : }
1669 :
1670 247650 : if (!ARM::GPRRegClass.contains(Reg)) {
1671 117800 : if (Spilled) {
1672 1348 : if (ARM::SPRRegClass.contains(Reg))
1673 0 : NumFPRSpills++;
1674 1348 : else if (ARM::DPRRegClass.contains(Reg))
1675 1348 : NumFPRSpills += 2;
1676 0 : else if (ARM::QPRRegClass.contains(Reg))
1677 0 : NumFPRSpills += 4;
1678 : }
1679 228478 : continue;
1680 : }
1681 :
1682 129850 : if (Spilled) {
1683 8698 : NumGPRSpills++;
1684 :
1685 8698 : if (!STI.splitFramePushPop(MF)) {
1686 6326 : if (Reg == ARM::LR)
1687 : LRSpilled = true;
1688 : CS1Spilled = true;
1689 6326 : continue;
1690 : }
1691 :
1692 : // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1693 2372 : switch (Reg) {
1694 1011 : case ARM::LR:
1695 : LRSpilled = true;
1696 : LLVM_FALLTHROUGH;
1697 : case ARM::R0: case ARM::R1:
1698 : case ARM::R2: case ARM::R3:
1699 : case ARM::R4: case ARM::R5:
1700 : case ARM::R6: case ARM::R7:
1701 : CS1Spilled = true;
1702 : break;
1703 : default:
1704 : break;
1705 : }
1706 : } else {
1707 121152 : if (!STI.splitFramePushPop(MF)) {
1708 104352 : UnspilledCS1GPRs.push_back(Reg);
1709 104352 : continue;
1710 : }
1711 :
1712 16800 : switch (Reg) {
1713 9147 : case ARM::R0: case ARM::R1:
1714 : case ARM::R2: case ARM::R3:
1715 : case ARM::R4: case ARM::R5:
1716 : case ARM::R6: case ARM::R7:
1717 : case ARM::LR:
1718 9147 : UnspilledCS1GPRs.push_back(Reg);
1719 9147 : break;
1720 7653 : default:
1721 7653 : UnspilledCS2GPRs.push_back(Reg);
1722 7653 : break;
1723 : }
1724 : }
1725 : }
1726 :
1727 : bool ForceLRSpill = false;
1728 14694 : if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1729 653 : unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1730 : // Force LR to be spilled if the Thumb function size is > 2048. This enables
1731 : // use of BL to implement far jump. If it turns out that it's not needed
1732 : // then the branch fix up path will undo it.
1733 653 : if (FnSize >= (1 << 11)) {
1734 : CanEliminateFrame = false;
1735 : ForceLRSpill = true;
1736 : }
1737 : }
1738 :
1739 : // If any of the stack slot references may be out of range of an immediate
1740 : // offset, make sure a register (or a spill slot) is available for the
1741 : // register scavenger. Note that if we're indexing off the frame pointer, the
1742 : // effective stack size is 4 bytes larger since the FP points to the stack
1743 : // slot of the previous FP. Also, if we have variable sized objects in the
1744 : // function, stack slot references will often be negative, and some of
1745 : // our instructions are positive-offset only, so conservatively consider
1746 : // that case to want a spill slot (or register) as well. Similarly, if
1747 : // the function adjusts the stack pointer during execution and the
1748 : // adjustments aren't already part of our stack size estimate, our offset
1749 : // calculations may be off, so be conservative.
1750 : // FIXME: We could add logic to be more precise about negative offsets
1751 : // and which instructions will need a scratch register for them. Is it
1752 : // worth the effort and added fragility?
1753 : unsigned EstimatedStackSize =
1754 14694 : MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
1755 :
1756 : // Determine biggest (positive) SP offset in MachineFrameInfo.
1757 14694 : int MaxFixedOffset = 0;
1758 16431 : for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
1759 3474 : int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I);
1760 1737 : MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);
1761 : }
1762 :
1763 14694 : bool HasFP = hasFP(MF);
1764 14694 : if (HasFP) {
1765 1951 : if (AFI->hasStackFrame())
1766 15 : EstimatedStackSize += 4;
1767 : } else {
1768 : // If FP is not used, SP will be used to access arguments, so count the
1769 : // size of arguments into the estimation.
1770 12743 : EstimatedStackSize += MaxFixedOffset;
1771 : }
1772 14694 : EstimatedStackSize += 16; // For possible paddings.
1773 :
1774 14694 : unsigned EstimatedRSStackSizeLimit = estimateRSStackSizeLimit(MF, this);
1775 : int MaxFPOffset = getMaxFPOffset(MF.getFunction(), *AFI);
1776 14526 : bool BigFrameOffsets = EstimatedStackSize >= EstimatedRSStackSizeLimit ||
1777 14526 : MFI.hasVarSizedObjects() ||
1778 29170 : (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF)) ||
1779 : // For large argument stacks fp relative addressed may overflow.
1780 1841 : (HasFP && (MaxFixedOffset - MaxFPOffset) >= (int)EstimatedRSStackSizeLimit);
1781 14694 : if (BigFrameOffsets ||
1782 14694 : !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1783 : AFI->setHasStackFrame(true);
1784 :
1785 4355 : if (HasFP) {
1786 1153 : SavedRegs.set(FramePtr);
1787 : // If the frame pointer is required by the ABI, also spill LR so that we
1788 : // emit a complete frame record.
1789 1153 : if (MF.getTarget().Options.DisableFramePointerElim(MF) && !LRSpilled) {
1790 : SavedRegs.set(ARM::LR);
1791 : LRSpilled = true;
1792 118 : NumGPRSpills++;
1793 118 : auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
1794 118 : if (LRPos != UnspilledCS1GPRs.end())
1795 118 : UnspilledCS1GPRs.erase(LRPos);
1796 : }
1797 : auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);
1798 1153 : if (FPPos != UnspilledCS1GPRs.end())
1799 1079 : UnspilledCS1GPRs.erase(FPPos);
1800 1153 : NumGPRSpills++;
1801 1153 : if (FramePtr == ARM::R7)
1802 : CS1Spilled = true;
1803 : }
1804 :
1805 : // This is true when we inserted a spill for an unused register that can now
1806 : // be used for register scavenging.
1807 : bool ExtraCSSpill = false;
1808 :
1809 4355 : if (AFI->isThumb1OnlyFunction()) {
1810 : // For Thumb1-only targets, we need some low registers when we save and
1811 : // restore the high registers (which aren't allocatable, but could be
1812 : // used by inline assembly) because the push/pop instructions can not
1813 : // access high registers. If necessary, we might need to push more low
1814 : // registers to ensure that there is at least one free that can be used
1815 : // for the saving & restoring, and preferably we should ensure that as
1816 : // many as are needed are available so that fewer push/pop instructions
1817 : // are required.
1818 :
1819 : // Low registers which are not currently pushed, but could be (r4-r7).
1820 : SmallVector<unsigned, 4> AvailableRegs;
1821 :
1822 : // Unused argument registers (r0-r3) can be clobbered in the prologue for
1823 : // free.
1824 644 : int EntryRegDeficit = 0;
1825 3220 : for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
1826 2576 : if (!MF.getRegInfo().isLiveIn(Reg)) {
1827 1883 : --EntryRegDeficit;
1828 : LLVM_DEBUG(dbgs()
1829 : << printReg(Reg, TRI)
1830 : << " is unused argument register, EntryRegDeficit = "
1831 : << EntryRegDeficit << "\n");
1832 : }
1833 : }
1834 :
1835 : // Unused return registers can be clobbered in the epilogue for free.
1836 644 : int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
1837 : LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount()
1838 : << " return regs used, ExitRegDeficit = "
1839 : << ExitRegDeficit << "\n");
1840 :
1841 644 : int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
1842 : LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
1843 :
1844 : // r4-r6 can be used in the prologue if they are pushed by the first push
1845 : // instruction.
1846 2576 : for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
1847 1932 : if (SavedRegs.test(Reg)) {
1848 620 : --RegDeficit;
1849 : LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1850 : << " is saved low register, RegDeficit = "
1851 : << RegDeficit << "\n");
1852 : } else {
1853 1312 : AvailableRegs.push_back(Reg);
1854 : LLVM_DEBUG(
1855 : dbgs()
1856 : << printReg(Reg, TRI)
1857 : << " is non-saved low register, adding to AvailableRegs\n");
1858 : }
1859 : }
1860 :
1861 : // r7 can be used if it is not being used as the frame pointer.
1862 644 : if (!HasFP) {
1863 478 : if (SavedRegs.test(ARM::R7)) {
1864 41 : --RegDeficit;
1865 : LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
1866 : << RegDeficit << "\n");
1867 : } else {
1868 437 : AvailableRegs.push_back(ARM::R7);
1869 : LLVM_DEBUG(
1870 : dbgs()
1871 : << "%r7 is non-saved low register, adding to AvailableRegs\n");
1872 : }
1873 : }
1874 :
1875 : // Each of r8-r11 needs to be copied to a low register, then pushed.
1876 3220 : for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
1877 2576 : if (SavedRegs.test(Reg)) {
1878 54 : ++RegDeficit;
1879 : LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1880 : << " is saved high register, RegDeficit = "
1881 : << RegDeficit << "\n");
1882 : }
1883 : }
1884 :
1885 : // LR can only be used by PUSH, not POP, and can't be used at all if the
1886 : // llvm.returnaddress intrinsic is used. This is only worth doing if we
1887 : // are more limited at function entry than exit.
1888 873 : if ((EntryRegDeficit > ExitRegDeficit) &&
1889 229 : !(MF.getRegInfo().isLiveIn(ARM::LR) &&
1890 0 : MF.getFrameInfo().isReturnAddressTaken())) {
1891 229 : if (SavedRegs.test(ARM::LR)) {
1892 180 : --RegDeficit;
1893 : LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = "
1894 : << RegDeficit << "\n");
1895 : } else {
1896 49 : AvailableRegs.push_back(ARM::LR);
1897 : LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");
1898 : }
1899 : }
1900 :
1901 : // If there are more high registers that need pushing than low registers
1902 : // available, push some more low registers so that we can use fewer push
1903 : // instructions. This might not reduce RegDeficit all the way to zero,
1904 : // because we can only guarantee that r4-r6 are available, but r8-r11 may
1905 : // need saving.
1906 : LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
1907 652 : for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
1908 8 : unsigned Reg = AvailableRegs.pop_back_val();
1909 : LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1910 : << " to make up reg deficit\n");
1911 : SavedRegs.set(Reg);
1912 8 : NumGPRSpills++;
1913 : CS1Spilled = true;
1914 : assert(!MRI.isReserved(Reg) && "Should not be reserved");
1915 8 : if (!MRI.isPhysRegUsed(Reg))
1916 : ExtraCSSpill = true;
1917 8 : UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
1918 8 : if (Reg == ARM::LR)
1919 : LRSpilled = true;
1920 : }
1921 : LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit
1922 : << "\n");
1923 : }
1924 :
1925 : // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to
1926 : // restore LR in that case.
1927 4999 : bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && MFI.hasTailCall();
1928 :
1929 : // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1930 : // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1931 4355 : if (!LRSpilled && CS1Spilled && !ExpensiveLRRestore) {
1932 : SavedRegs.set(ARM::LR);
1933 196 : NumGPRSpills++;
1934 : SmallVectorImpl<unsigned>::iterator LRPos;
1935 196 : LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
1936 196 : if (LRPos != UnspilledCS1GPRs.end())
1937 196 : UnspilledCS1GPRs.erase(LRPos);
1938 :
1939 : ForceLRSpill = false;
1940 196 : if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR))
1941 : ExtraCSSpill = true;
1942 : }
1943 :
1944 : // If stack and double are 8-byte aligned and we are spilling an odd number
1945 : // of GPRs, spill one extra callee save GPR so we won't have to pad between
1946 : // the integer and double callee save areas.
1947 : LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");
1948 4355 : unsigned TargetAlign = getStackAlignment();
1949 4355 : if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1950 2130 : if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1951 3852 : for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1952 3835 : unsigned Reg = UnspilledCS1GPRs[i];
1953 : // Don't spill high register if the function is thumb. In the case of
1954 : // Windows on ARM, accept R11 (frame pointer)
1955 2628 : if (!AFI->isThumbFunction() ||
1956 2628 : (STI.isTargetWindows() && Reg == ARM::R11) ||
1957 3835 : isARMLowRegister(Reg) ||
1958 1833 : (Reg == ARM::LR && !ExpensiveLRRestore)) {
1959 : SavedRegs.set(Reg);
1960 : LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1961 : << " to make up alignment\n");
1962 2002 : if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
1963 : ExtraCSSpill = true;
1964 : break;
1965 : }
1966 : }
1967 111 : } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1968 8 : unsigned Reg = UnspilledCS2GPRs.front();
1969 : SavedRegs.set(Reg);
1970 : LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1971 : << " to make up alignment\n");
1972 8 : if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
1973 : ExtraCSSpill = true;
1974 : }
1975 : }
1976 :
1977 : // Estimate if we might need to scavenge a register at some point in order
1978 : // to materialize a stack offset. If so, either spill one additional
1979 : // callee-saved register or reserve a special spill slot to facilitate
1980 : // register scavenging. Thumb1 needs a spill slot for stack pointer
1981 : // adjustments also, even when the frame itself is small.
1982 4355 : if (BigFrameOffsets && !ExtraCSSpill) {
1983 : // If any non-reserved CS register isn't spilled, just spill one or two
1984 : // extra. That should take care of it!
1985 132 : unsigned NumExtras = TargetAlign / 4;
1986 : SmallVector<unsigned, 2> Extras;
1987 295 : while (NumExtras && !UnspilledCS1GPRs.empty()) {
1988 163 : unsigned Reg = UnspilledCS1GPRs.back();
1989 : UnspilledCS1GPRs.pop_back();
1990 163 : if (!MRI.isReserved(Reg) &&
1991 163 : (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1992 : Reg == ARM::LR)) {
1993 163 : Extras.push_back(Reg);
1994 163 : NumExtras--;
1995 : }
1996 : }
1997 : // For non-Thumb1 functions, also check for hi-reg CS registers
1998 132 : if (!AFI->isThumb1OnlyFunction()) {
1999 104 : while (NumExtras && !UnspilledCS2GPRs.empty()) {
2000 2 : unsigned Reg = UnspilledCS2GPRs.back();
2001 : UnspilledCS2GPRs.pop_back();
2002 2 : if (!MRI.isReserved(Reg)) {
2003 2 : Extras.push_back(Reg);
2004 2 : NumExtras--;
2005 : }
2006 : }
2007 : }
2008 132 : if (NumExtras == 0) {
2009 255 : for (unsigned Reg : Extras) {
2010 : SavedRegs.set(Reg);
2011 155 : if (!MRI.isPhysRegUsed(Reg))
2012 : ExtraCSSpill = true;
2013 : }
2014 : }
2015 132 : if (!ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
2016 : // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
2017 : // closest to SP or frame pointer.
2018 : assert(RS && "Register scavenging not provided");
2019 : const TargetRegisterClass &RC = ARM::GPRRegClass;
2020 : unsigned Size = TRI->getSpillSize(RC);
2021 : unsigned Align = TRI->getSpillAlignment(RC);
2022 17 : RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
2023 : }
2024 : }
2025 : }
2026 :
2027 14694 : if (ForceLRSpill) {
2028 : SavedRegs.set(ARM::LR);
2029 : AFI->setLRIsSpilledForFarJump(true);
2030 : }
2031 14694 : }
2032 :
2033 13432 : MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
2034 : MachineFunction &MF, MachineBasicBlock &MBB,
2035 : MachineBasicBlock::iterator I) const {
2036 : const ARMBaseInstrInfo &TII =
2037 13432 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2038 13432 : if (!hasReservedCallFrame(MF)) {
2039 : // If we have alloca, convert as follows:
2040 : // ADJCALLSTACKDOWN -> sub, sp, sp, amount
2041 : // ADJCALLSTACKUP -> add, sp, sp, amount
2042 : MachineInstr &Old = *I;
2043 : DebugLoc dl = Old.getDebugLoc();
2044 170 : unsigned Amount = TII.getFrameSize(Old);
2045 170 : if (Amount != 0) {
2046 : // We need to keep the stack aligned properly. To do this, we round the
2047 : // amount of space needed for the outgoing arguments up to the next
2048 : // alignment boundary.
2049 42 : Amount = alignSPAdjust(Amount);
2050 :
2051 42 : ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2052 : assert(!AFI->isThumb1OnlyFunction() &&
2053 : "This eliminateCallFramePseudoInstr does not support Thumb1!");
2054 42 : bool isARM = !AFI->isThumbFunction();
2055 :
2056 : // Replace the pseudo instruction with a new instruction...
2057 42 : unsigned Opc = Old.getOpcode();
2058 42 : int PIdx = Old.findFirstPredOperandIdx();
2059 : ARMCC::CondCodes Pred =
2060 42 : (PIdx == -1) ? ARMCC::AL
2061 84 : : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
2062 : unsigned PredReg = TII.getFramePred(Old);
2063 42 : if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
2064 21 : emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
2065 : Pred, PredReg);
2066 : } else {
2067 : assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
2068 21 : emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
2069 : Pred, PredReg);
2070 : }
2071 : }
2072 : }
2073 13432 : return MBB.erase(I);
2074 : }
2075 :
2076 : /// Get the minimum constant for ARM that is greater than or equal to the
2077 : /// argument. In ARM, constants can have any value that can be produced by
2078 : /// rotating an 8-bit value to the right by an even number of bits within a
2079 : /// 32-bit word.
2080 112 : static uint32_t alignToARMConstant(uint32_t Value) {
2081 : unsigned Shifted = 0;
2082 :
2083 112 : if (Value == 0)
2084 : return 0;
2085 :
2086 648 : while (!(Value & 0xC0000000)) {
2087 596 : Value = Value << 2;
2088 596 : Shifted += 2;
2089 : }
2090 :
2091 52 : bool Carry = (Value & 0x00FFFFFF);
2092 52 : Value = ((Value & 0xFF000000) >> 24) + Carry;
2093 :
2094 52 : if (Value & 0x0000100)
2095 : Value = Value & 0x000001FC;
2096 :
2097 52 : if (Shifted > 24)
2098 36 : Value = Value >> (Shifted - 24);
2099 : else
2100 16 : Value = Value << (24 - Shifted);
2101 :
2102 : return Value;
2103 : }
2104 :
2105 : // The stack limit in the TCB is set to this many bytes above the actual
2106 : // stack limit.
2107 : static const uint64_t kSplitStackAvailable = 256;
2108 :
2109 : // Adjust the function prologue to enable split stacks. This currently only
2110 : // supports android and linux.
2111 : //
2112 : // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
2113 : // must be well defined in order to allow for consistent implementations of the
2114 : // __morestack helper function. The ABI is also not a normal ABI in that it
2115 : // doesn't follow the normal calling conventions because this allows the
2116 : // prologue of each function to be optimized further.
2117 : //
2118 : // Currently, the ABI looks like (when calling __morestack)
2119 : //
2120 : // * r4 holds the minimum stack size requested for this function call
2121 : // * r5 holds the stack size of the arguments to the function
2122 : // * the beginning of the function is 3 instructions after the call to
2123 : // __morestack
2124 : //
2125 : // Implementations of __morestack should use r4 to allocate a new stack, r5 to
2126 : // place the arguments on to the new stack, and the 3-instruction knowledge to
2127 : // jump directly to the body of the function when working on the new stack.
2128 : //
2129 : // An old (and possibly no longer compatible) implementation of __morestack for
2130 : // ARM can be found at [1].
2131 : //
2132 : // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
2133 64 : void ARMFrameLowering::adjustForSegmentedStacks(
2134 : MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2135 : unsigned Opcode;
2136 : unsigned CFIIndex;
2137 64 : const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
2138 64 : bool Thumb = ST->isThumb();
2139 :
2140 : // Sadly, this currently doesn't support varargs, platforms other than
2141 : // android/linux. Note that thumb1/thumb2 are support for android/linux.
2142 128 : if (MF.getFunction().isVarArg())
2143 0 : report_fatal_error("Segmented stacks do not support vararg functions.");
2144 64 : if (!ST->isTargetAndroid() && !ST->isTargetLinux())
2145 0 : report_fatal_error("Segmented stacks not supported on this platform.");
2146 :
2147 64 : MachineFrameInfo &MFI = MF.getFrameInfo();
2148 64 : MachineModuleInfo &MMI = MF.getMMI();
2149 : MCContext &Context = MMI.getContext();
2150 64 : const MCRegisterInfo *MRI = Context.getRegisterInfo();
2151 : const ARMBaseInstrInfo &TII =
2152 64 : *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2153 64 : ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
2154 64 : DebugLoc DL;
2155 :
2156 64 : uint64_t StackSize = MFI.getStackSize();
2157 :
2158 : // Do not generate a prologue for leaf functions with a stack of size zero.
2159 : // For non-leaf functions we have to allow for the possibility that the
2160 : // call is to a non-split function, as in PR37807.
2161 64 : if (StackSize == 0 && !MFI.hasTailCall())
2162 : return;
2163 :
2164 : // Use R4 and R5 as scratch registers.
2165 : // We save R4 and R5 before use and restore them before leaving the function.
2166 : unsigned ScratchReg0 = ARM::R4;
2167 : unsigned ScratchReg1 = ARM::R5;
2168 : uint64_t AlignedStackSize;
2169 :
2170 56 : MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
2171 56 : MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
2172 56 : MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
2173 56 : MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
2174 56 : MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
2175 :
2176 : // Grab everything that reaches PrologueMBB to update there liveness as well.
2177 : SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
2178 : SmallVector<MachineBasicBlock *, 2> WalkList;
2179 56 : WalkList.push_back(&PrologueMBB);
2180 :
2181 : do {
2182 : MachineBasicBlock *CurMBB = WalkList.pop_back_val();
2183 56 : for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
2184 0 : if (BeforePrologueRegion.insert(PredBB).second)
2185 0 : WalkList.push_back(PredBB);
2186 : }
2187 56 : } while (!WalkList.empty());
2188 :
2189 : // The order in that list is important.
2190 : // The blocks will all be inserted before PrologueMBB using that order.
2191 : // Therefore the block that should appear first in the CFG should appear
2192 : // first in the list.
2193 : MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
2194 56 : PostStackMBB};
2195 :
2196 336 : for (MachineBasicBlock *B : AddedBlocks)
2197 280 : BeforePrologueRegion.insert(B);
2198 :
2199 224 : for (const auto &LI : PrologueMBB.liveins()) {
2200 1008 : for (MachineBasicBlock *PredBB : BeforePrologueRegion)
2201 : PredBB->addLiveIn(LI);
2202 : }
2203 :
2204 : // Remove the newly added blocks from the list, since we know
2205 : // we do not have to do the following updates for them.
2206 336 : for (MachineBasicBlock *B : AddedBlocks) {
2207 : BeforePrologueRegion.erase(B);
2208 280 : MF.insert(PrologueMBB.getIterator(), B);
2209 : }
2210 :
2211 56 : for (MachineBasicBlock *MBB : BeforePrologueRegion) {
2212 : // Make sure the LiveIns are still sorted and unique.
2213 0 : MBB->sortUniqueLiveIns();
2214 : // Replace the edges to PrologueMBB by edges to the sequences
2215 : // we are about to add.
2216 0 : MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2217 : }
2218 :
2219 : // The required stack size that is aligned to ARM constant criterion.
2220 56 : AlignedStackSize = alignToARMConstant(StackSize);
2221 :
2222 : // When the frame size is less than 256 we just compare the stack
2223 : // boundary directly to the value of the stack pointer, per gcc.
2224 : bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
2225 :
2226 : // We will use two of the callee save registers as scratch registers so we
2227 : // need to save those registers onto the stack.
2228 : // We will use SR0 to hold stack limit and SR1 to hold the stack size
2229 : // requested and arguments for __morestack().
2230 : // SR0: Scratch Register #0
2231 : // SR1: Scratch Register #1
2232 : // push {SR0, SR1}
2233 56 : if (Thumb) {
2234 26 : BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
2235 26 : .add(predOps(ARMCC::AL))
2236 26 : .addReg(ScratchReg0)
2237 26 : .addReg(ScratchReg1);
2238 : } else {
2239 30 : BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2240 30 : .addReg(ARM::SP, RegState::Define)
2241 30 : .addReg(ARM::SP)
2242 30 : .add(predOps(ARMCC::AL))
2243 30 : .addReg(ScratchReg0)
2244 30 : .addReg(ScratchReg1);
2245 : }
2246 :
2247 : // Emit the relevant DWARF information about the change in stack pointer as
2248 : // well as where to find both r4 and r5 (the callee-save registers)
2249 : CFIIndex =
2250 56 : MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
2251 56 : BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2252 : .addCFIIndex(CFIIndex);
2253 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2254 56 : nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
2255 56 : BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2256 : .addCFIIndex(CFIIndex);
2257 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2258 56 : nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
2259 56 : BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2260 : .addCFIIndex(CFIIndex);
2261 :
2262 : // mov SR1, sp
2263 56 : if (Thumb) {
2264 26 : BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
2265 26 : .addReg(ARM::SP)
2266 26 : .add(predOps(ARMCC::AL));
2267 30 : } else if (CompareStackPointer) {
2268 22 : BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
2269 22 : .addReg(ARM::SP)
2270 22 : .add(predOps(ARMCC::AL))
2271 22 : .add(condCodeOp());
2272 : }
2273 :
2274 : // sub SR1, sp, #StackSize
2275 56 : if (!CompareStackPointer && Thumb) {
2276 8 : BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
2277 8 : .add(condCodeOp())
2278 8 : .addReg(ScratchReg1)
2279 8 : .addImm(AlignedStackSize)
2280 8 : .add(predOps(ARMCC::AL));
2281 48 : } else if (!CompareStackPointer) {
2282 8 : BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
2283 8 : .addReg(ARM::SP)
2284 8 : .addImm(AlignedStackSize)
2285 8 : .add(predOps(ARMCC::AL))
2286 8 : .add(condCodeOp());
2287 : }
2288 :
2289 56 : if (Thumb && ST->isThumb1Only()) {
2290 : unsigned PCLabelId = ARMFI->createPICLabelUId();
2291 24 : ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
2292 24 : MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);
2293 24 : MachineConstantPool *MCP = MF.getConstantPool();
2294 24 : unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
2295 :
2296 : // ldr SR0, [pc, offset(STACK_LIMIT)]
2297 24 : BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
2298 : .addConstantPoolIndex(CPI)
2299 24 : .add(predOps(ARMCC::AL));
2300 :
2301 : // ldr SR0, [SR0]
2302 24 : BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
2303 24 : .addReg(ScratchReg0)
2304 : .addImm(0)
2305 24 : .add(predOps(ARMCC::AL));
2306 : } else {
2307 : // Get TLS base address from the coprocessor
2308 : // mrc p15, #0, SR0, c13, c0, #3
2309 32 : BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
2310 : .addImm(15)
2311 : .addImm(0)
2312 : .addImm(13)
2313 : .addImm(0)
2314 : .addImm(3)
2315 32 : .add(predOps(ARMCC::AL));
2316 :
2317 : // Use the last tls slot on android and a private field of the TCP on linux.
2318 : assert(ST->isTargetAndroid() || ST->isTargetLinux());
2319 32 : unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
2320 :
2321 : // Get the stack limit from the right offset
2322 : // ldr SR0, [sr0, #4 * TlsOffset]
2323 32 : BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2324 32 : .addReg(ScratchReg0)
2325 32 : .addImm(4 * TlsOffset)
2326 32 : .add(predOps(ARMCC::AL));
2327 : }
2328 :
2329 : // Compare stack limit with stack size requested.
2330 : // cmp SR0, SR1
2331 56 : Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
2332 56 : BuildMI(GetMBB, DL, TII.get(Opcode))
2333 56 : .addReg(ScratchReg0)
2334 56 : .addReg(ScratchReg1)
2335 56 : .add(predOps(ARMCC::AL));
2336 :
2337 : // This jump is taken if StackLimit < SP - stack required.
2338 56 : Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
2339 56 : BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2340 : .addImm(ARMCC::LO)
2341 56 : .addReg(ARM::CPSR);
2342 :
2343 :
2344 : // Calling __morestack(StackSize, Size of stack arguments).
2345 : // __morestack knows that the stack size requested is in SR0(r4)
2346 : // and amount size of stack arguments is in SR1(r5).
2347 :
2348 : // Pass first argument for the __morestack by Scratch Register #0.
2349 : // The amount size of stack required
2350 56 : if (Thumb) {
2351 26 : BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
2352 26 : .add(condCodeOp())
2353 26 : .addImm(AlignedStackSize)
2354 26 : .add(predOps(ARMCC::AL));
2355 : } else {
2356 30 : BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2357 30 : .addImm(AlignedStackSize)
2358 30 : .add(predOps(ARMCC::AL))
2359 30 : .add(condCodeOp());
2360 : }
2361 : // Pass second argument for the __morestack by Scratch Register #1.
2362 : // The amount size of stack consumed to save function arguments.
2363 56 : if (Thumb) {
2364 26 : BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
2365 26 : .add(condCodeOp())
2366 26 : .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2367 26 : .add(predOps(ARMCC::AL));
2368 : } else {
2369 30 : BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2370 30 : .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2371 30 : .add(predOps(ARMCC::AL))
2372 30 : .add(condCodeOp());
2373 : }
2374 :
2375 : // push {lr} - Save return address of this function.
2376 56 : if (Thumb) {
2377 26 : BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
2378 26 : .add(predOps(ARMCC::AL))
2379 26 : .addReg(ARM::LR);
2380 : } else {
2381 30 : BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2382 30 : .addReg(ARM::SP, RegState::Define)
2383 30 : .addReg(ARM::SP)
2384 30 : .add(predOps(ARMCC::AL))
2385 30 : .addReg(ARM::LR);
2386 : }
2387 :
2388 : // Emit the DWARF info about the change in stack as well as where to find the
2389 : // previous link register
2390 : CFIIndex =
2391 56 : MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2392 56 : BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2393 : .addCFIIndex(CFIIndex);
2394 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2395 56 : nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2396 56 : BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2397 : .addCFIIndex(CFIIndex);
2398 :
2399 : // Call __morestack().
2400 56 : if (Thumb) {
2401 26 : BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
2402 26 : .add(predOps(ARMCC::AL))
2403 : .addExternalSymbol("__morestack");
2404 : } else {
2405 30 : BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2406 : .addExternalSymbol("__morestack");
2407 : }
2408 :
2409 : // pop {lr} - Restore return address of this original function.
2410 56 : if (Thumb) {
2411 26 : if (ST->isThumb1Only()) {
2412 24 : BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2413 24 : .add(predOps(ARMCC::AL))
2414 24 : .addReg(ScratchReg0);
2415 24 : BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2416 24 : .addReg(ScratchReg0)
2417 24 : .add(predOps(ARMCC::AL));
2418 : } else {
2419 2 : BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2420 2 : .addReg(ARM::LR, RegState::Define)
2421 2 : .addReg(ARM::SP, RegState::Define)
2422 2 : .addReg(ARM::SP)
2423 : .addImm(4)
2424 2 : .add(predOps(ARMCC::AL));
2425 : }
2426 : } else {
2427 30 : BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2428 30 : .addReg(ARM::SP, RegState::Define)
2429 30 : .addReg(ARM::SP)
2430 30 : .add(predOps(ARMCC::AL))
2431 30 : .addReg(ARM::LR);
2432 : }
2433 :
2434 : // Restore SR0 and SR1 in case of __morestack() was called.
2435 : // __morestack() will skip PostStackMBB block so we need to restore
2436 : // scratch registers from here.
2437 : // pop {SR0, SR1}
2438 56 : if (Thumb) {
2439 26 : BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2440 26 : .add(predOps(ARMCC::AL))
2441 26 : .addReg(ScratchReg0)
2442 26 : .addReg(ScratchReg1);
2443 : } else {
2444 30 : BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2445 30 : .addReg(ARM::SP, RegState::Define)
2446 30 : .addReg(ARM::SP)
2447 30 : .add(predOps(ARMCC::AL))
2448 30 : .addReg(ScratchReg0)
2449 30 : .addReg(ScratchReg1);
2450 : }
2451 :
2452 : // Update the CFA offset now that we've popped
2453 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2454 56 : BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2455 : .addCFIIndex(CFIIndex);
2456 :
2457 : // Return from this function.
2458 56 : BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
2459 :
2460 : // Restore SR0 and SR1 in case of __morestack() was not called.
2461 : // pop {SR0, SR1}
2462 56 : if (Thumb) {
2463 26 : BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
2464 26 : .add(predOps(ARMCC::AL))
2465 26 : .addReg(ScratchReg0)
2466 26 : .addReg(ScratchReg1);
2467 : } else {
2468 30 : BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2469 30 : .addReg(ARM::SP, RegState::Define)
2470 30 : .addReg(ARM::SP)
2471 30 : .add(predOps(ARMCC::AL))
2472 30 : .addReg(ScratchReg0)
2473 30 : .addReg(ScratchReg1);
2474 : }
2475 :
2476 : // Update the CFA offset now that we've popped
2477 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2478 56 : BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2479 : .addCFIIndex(CFIIndex);
2480 :
2481 : // Tell debuggers that r4 and r5 are now the same as they were in the
2482 : // previous function, that they're the "Same Value".
2483 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2484 56 : nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2485 56 : BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2486 : .addCFIIndex(CFIIndex);
2487 56 : CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2488 56 : nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2489 56 : BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2490 : .addCFIIndex(CFIIndex);
2491 :
2492 : // Organizing MBB lists
2493 56 : PostStackMBB->addSuccessor(&PrologueMBB);
2494 :
2495 56 : AllocMBB->addSuccessor(PostStackMBB);
2496 :
2497 56 : GetMBB->addSuccessor(PostStackMBB);
2498 56 : GetMBB->addSuccessor(AllocMBB);
2499 :
2500 56 : McrMBB->addSuccessor(GetMBB);
2501 :
2502 56 : PrevStackMBB->addSuccessor(McrMBB);
2503 :
2504 : #ifdef EXPENSIVE_CHECKS
2505 : MF.verify();
2506 : #endif
2507 : }
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