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1 : //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : ///
10 : /// \file
11 : /// This file provides WebAssembly-specific target descriptions.
12 : ///
13 : //===----------------------------------------------------------------------===//
14 :
15 : #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16 : #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
17 :
18 : #include "llvm/BinaryFormat/Wasm.h"
19 : #include "llvm/MC/MCInstrDesc.h"
20 : #include "llvm/Support/DataTypes.h"
21 : #include <memory>
22 :
23 : namespace llvm {
24 :
25 : class MCAsmBackend;
26 : class MCCodeEmitter;
27 : class MCContext;
28 : class MCInstrInfo;
29 : class MCObjectTargetWriter;
30 : class MCSubtargetInfo;
31 : class MVT;
32 : class Target;
33 : class Triple;
34 : class raw_pwrite_stream;
35 :
36 : Target &getTheWebAssemblyTarget32();
37 : Target &getTheWebAssemblyTarget64();
38 :
39 : MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
40 :
41 : MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
42 :
43 : std::unique_ptr<MCObjectTargetWriter>
44 : createWebAssemblyWasmObjectWriter(bool Is64Bit);
45 :
46 : namespace WebAssembly {
47 : enum OperandType {
48 : /// Basic block label in a branch construct.
49 : OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
50 : /// Local index.
51 : OPERAND_LOCAL,
52 : /// Global index.
53 : OPERAND_GLOBAL,
54 : /// 32-bit integer immediates.
55 : OPERAND_I32IMM,
56 : /// 64-bit integer immediates.
57 : OPERAND_I64IMM,
58 : /// 32-bit floating-point immediates.
59 : OPERAND_F32IMM,
60 : /// 64-bit floating-point immediates.
61 : OPERAND_F64IMM,
62 : /// 8-bit vector lane immediate
63 : OPERAND_VEC_I8IMM,
64 : /// 16-bit vector lane immediate
65 : OPERAND_VEC_I16IMM,
66 : /// 32-bit vector lane immediate
67 : OPERAND_VEC_I32IMM,
68 : /// 64-bit vector lane immediate
69 : OPERAND_VEC_I64IMM,
70 : /// 32-bit unsigned function indices.
71 : OPERAND_FUNCTION32,
72 : /// 32-bit unsigned memory offsets.
73 : OPERAND_OFFSET32,
74 : /// p2align immediate for load and store address alignment.
75 : OPERAND_P2ALIGN,
76 : /// signature immediate for block/loop.
77 : OPERAND_SIGNATURE,
78 : /// type signature immediate for call_indirect.
79 : OPERAND_TYPEINDEX,
80 : };
81 : } // end namespace WebAssembly
82 :
83 : namespace WebAssemblyII {
84 : enum {
85 : // For variadic instructions, this flag indicates whether an operand
86 : // in the variable_ops range is an immediate value.
87 : VariableOpIsImmediate = (1 << 0),
88 : // For immediate values in the variable_ops range, this flag indicates
89 : // whether the value represents a control-flow label.
90 : VariableOpImmediateIsLabel = (1 << 1)
91 : };
92 :
93 : /// Target Operand Flag enum.
94 : enum TOF {
95 : MO_NO_FLAG = 0,
96 :
97 : // Flags to indicate the type of the symbol being referenced
98 : MO_SYMBOL_FUNCTION = 0x1,
99 : MO_SYMBOL_GLOBAL = 0x2,
100 : MO_SYMBOL_MASK = 0x3,
101 : };
102 : } // end namespace WebAssemblyII
103 :
104 : } // end namespace llvm
105 :
106 : // Defines symbolic names for WebAssembly registers. This defines a mapping from
107 : // register name to register number.
108 : //
109 : #define GET_REGINFO_ENUM
110 : #include "WebAssemblyGenRegisterInfo.inc"
111 :
112 : // Defines symbolic names for the WebAssembly instructions.
113 : //
114 : #define GET_INSTRINFO_ENUM
115 : #include "WebAssemblyGenInstrInfo.inc"
116 :
117 : #define GET_SUBTARGETINFO_ENUM
118 : #include "WebAssemblyGenSubtargetInfo.inc"
119 :
120 : namespace llvm {
121 : namespace WebAssembly {
122 :
123 : /// Return the default p2align value for a load or store with the given opcode.
124 7145 : inline unsigned GetDefaultP2Align(unsigned Opcode) {
125 7145 : switch (Opcode) {
126 : case WebAssembly::LOAD8_S_I32:
127 : case WebAssembly::LOAD8_S_I32_S:
128 : case WebAssembly::LOAD8_U_I32:
129 : case WebAssembly::LOAD8_U_I32_S:
130 : case WebAssembly::LOAD8_S_I64:
131 : case WebAssembly::LOAD8_S_I64_S:
132 : case WebAssembly::LOAD8_U_I64:
133 : case WebAssembly::LOAD8_U_I64_S:
134 : case WebAssembly::ATOMIC_LOAD8_U_I32:
135 : case WebAssembly::ATOMIC_LOAD8_U_I32_S:
136 : case WebAssembly::ATOMIC_LOAD8_U_I64:
137 : case WebAssembly::ATOMIC_LOAD8_U_I64_S:
138 : case WebAssembly::STORE8_I32:
139 : case WebAssembly::STORE8_I32_S:
140 : case WebAssembly::STORE8_I64:
141 : case WebAssembly::STORE8_I64_S:
142 : case WebAssembly::ATOMIC_STORE8_I32:
143 : case WebAssembly::ATOMIC_STORE8_I32_S:
144 : case WebAssembly::ATOMIC_STORE8_I64:
145 : case WebAssembly::ATOMIC_STORE8_I64_S:
146 : case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
147 : case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
148 : case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
149 : case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
150 : case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
151 : case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
152 : case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
153 : case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
154 : case WebAssembly::ATOMIC_RMW8_U_AND_I32:
155 : case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
156 : case WebAssembly::ATOMIC_RMW8_U_AND_I64:
157 : case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
158 : case WebAssembly::ATOMIC_RMW8_U_OR_I32:
159 : case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
160 : case WebAssembly::ATOMIC_RMW8_U_OR_I64:
161 : case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
162 : case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
163 : case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
164 : case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
165 : case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
166 : case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
167 : case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
168 : case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
169 : case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
170 : case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
171 : case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
172 : case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
173 : case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
174 : return 0;
175 916 : case WebAssembly::LOAD16_S_I32:
176 : case WebAssembly::LOAD16_S_I32_S:
177 : case WebAssembly::LOAD16_U_I32:
178 : case WebAssembly::LOAD16_U_I32_S:
179 : case WebAssembly::LOAD16_S_I64:
180 : case WebAssembly::LOAD16_S_I64_S:
181 : case WebAssembly::LOAD16_U_I64:
182 : case WebAssembly::LOAD16_U_I64_S:
183 : case WebAssembly::ATOMIC_LOAD16_U_I32:
184 : case WebAssembly::ATOMIC_LOAD16_U_I32_S:
185 : case WebAssembly::ATOMIC_LOAD16_U_I64:
186 : case WebAssembly::ATOMIC_LOAD16_U_I64_S:
187 : case WebAssembly::STORE16_I32:
188 : case WebAssembly::STORE16_I32_S:
189 : case WebAssembly::STORE16_I64:
190 : case WebAssembly::STORE16_I64_S:
191 : case WebAssembly::ATOMIC_STORE16_I32:
192 : case WebAssembly::ATOMIC_STORE16_I32_S:
193 : case WebAssembly::ATOMIC_STORE16_I64:
194 : case WebAssembly::ATOMIC_STORE16_I64_S:
195 : case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
196 : case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
197 : case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
198 : case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
199 : case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
200 : case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
201 : case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
202 : case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
203 : case WebAssembly::ATOMIC_RMW16_U_AND_I32:
204 : case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
205 : case WebAssembly::ATOMIC_RMW16_U_AND_I64:
206 : case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
207 : case WebAssembly::ATOMIC_RMW16_U_OR_I32:
208 : case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
209 : case WebAssembly::ATOMIC_RMW16_U_OR_I64:
210 : case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
211 : case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
212 : case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
213 : case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
214 : case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
215 : case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
216 : case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
217 : case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
218 : case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
219 : case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
220 : case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
221 : case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
222 : case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
223 916 : return 1;
224 2075 : case WebAssembly::LOAD_I32:
225 : case WebAssembly::LOAD_I32_S:
226 : case WebAssembly::LOAD_F32:
227 : case WebAssembly::LOAD_F32_S:
228 : case WebAssembly::STORE_I32:
229 : case WebAssembly::STORE_I32_S:
230 : case WebAssembly::STORE_F32:
231 : case WebAssembly::STORE_F32_S:
232 : case WebAssembly::LOAD32_S_I64:
233 : case WebAssembly::LOAD32_S_I64_S:
234 : case WebAssembly::LOAD32_U_I64:
235 : case WebAssembly::LOAD32_U_I64_S:
236 : case WebAssembly::STORE32_I64:
237 : case WebAssembly::STORE32_I64_S:
238 : case WebAssembly::ATOMIC_LOAD_I32:
239 : case WebAssembly::ATOMIC_LOAD_I32_S:
240 : case WebAssembly::ATOMIC_LOAD32_U_I64:
241 : case WebAssembly::ATOMIC_LOAD32_U_I64_S:
242 : case WebAssembly::ATOMIC_STORE_I32:
243 : case WebAssembly::ATOMIC_STORE_I32_S:
244 : case WebAssembly::ATOMIC_STORE32_I64:
245 : case WebAssembly::ATOMIC_STORE32_I64_S:
246 : case WebAssembly::ATOMIC_RMW_ADD_I32:
247 : case WebAssembly::ATOMIC_RMW_ADD_I32_S:
248 : case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
249 : case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
250 : case WebAssembly::ATOMIC_RMW_SUB_I32:
251 : case WebAssembly::ATOMIC_RMW_SUB_I32_S:
252 : case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
253 : case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
254 : case WebAssembly::ATOMIC_RMW_AND_I32:
255 : case WebAssembly::ATOMIC_RMW_AND_I32_S:
256 : case WebAssembly::ATOMIC_RMW32_U_AND_I64:
257 : case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
258 : case WebAssembly::ATOMIC_RMW_OR_I32:
259 : case WebAssembly::ATOMIC_RMW_OR_I32_S:
260 : case WebAssembly::ATOMIC_RMW32_U_OR_I64:
261 : case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
262 : case WebAssembly::ATOMIC_RMW_XOR_I32:
263 : case WebAssembly::ATOMIC_RMW_XOR_I32_S:
264 : case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
265 : case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
266 : case WebAssembly::ATOMIC_RMW_XCHG_I32:
267 : case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
268 : case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
269 : case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
270 : case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
271 : case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
272 : case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
273 : case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
274 : case WebAssembly::ATOMIC_NOTIFY:
275 : case WebAssembly::ATOMIC_NOTIFY_S:
276 : case WebAssembly::ATOMIC_WAIT_I32:
277 : case WebAssembly::ATOMIC_WAIT_I32_S:
278 2075 : return 2;
279 2096 : case WebAssembly::LOAD_I64:
280 : case WebAssembly::LOAD_I64_S:
281 : case WebAssembly::LOAD_F64:
282 : case WebAssembly::LOAD_F64_S:
283 : case WebAssembly::STORE_I64:
284 : case WebAssembly::STORE_I64_S:
285 : case WebAssembly::STORE_F64:
286 : case WebAssembly::STORE_F64_S:
287 : case WebAssembly::ATOMIC_LOAD_I64:
288 : case WebAssembly::ATOMIC_LOAD_I64_S:
289 : case WebAssembly::ATOMIC_STORE_I64:
290 : case WebAssembly::ATOMIC_STORE_I64_S:
291 : case WebAssembly::ATOMIC_RMW_ADD_I64:
292 : case WebAssembly::ATOMIC_RMW_ADD_I64_S:
293 : case WebAssembly::ATOMIC_RMW_SUB_I64:
294 : case WebAssembly::ATOMIC_RMW_SUB_I64_S:
295 : case WebAssembly::ATOMIC_RMW_AND_I64:
296 : case WebAssembly::ATOMIC_RMW_AND_I64_S:
297 : case WebAssembly::ATOMIC_RMW_OR_I64:
298 : case WebAssembly::ATOMIC_RMW_OR_I64_S:
299 : case WebAssembly::ATOMIC_RMW_XOR_I64:
300 : case WebAssembly::ATOMIC_RMW_XOR_I64_S:
301 : case WebAssembly::ATOMIC_RMW_XCHG_I64:
302 : case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
303 : case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
304 : case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
305 : case WebAssembly::ATOMIC_WAIT_I64:
306 : case WebAssembly::ATOMIC_WAIT_I64_S:
307 2096 : return 3;
308 170 : case WebAssembly::LOAD_v16i8:
309 : case WebAssembly::LOAD_v16i8_S:
310 : case WebAssembly::LOAD_v8i16:
311 : case WebAssembly::LOAD_v8i16_S:
312 : case WebAssembly::LOAD_v4i32:
313 : case WebAssembly::LOAD_v4i32_S:
314 : case WebAssembly::LOAD_v2i64:
315 : case WebAssembly::LOAD_v2i64_S:
316 : case WebAssembly::LOAD_v4f32:
317 : case WebAssembly::LOAD_v4f32_S:
318 : case WebAssembly::LOAD_v2f64:
319 : case WebAssembly::LOAD_v2f64_S:
320 : case WebAssembly::STORE_v16i8:
321 : case WebAssembly::STORE_v16i8_S:
322 : case WebAssembly::STORE_v8i16:
323 : case WebAssembly::STORE_v8i16_S:
324 : case WebAssembly::STORE_v4i32:
325 : case WebAssembly::STORE_v4i32_S:
326 : case WebAssembly::STORE_v2i64:
327 : case WebAssembly::STORE_v2i64_S:
328 : case WebAssembly::STORE_v4f32:
329 : case WebAssembly::STORE_v4f32_S:
330 : case WebAssembly::STORE_v2f64:
331 : case WebAssembly::STORE_v2f64_S:
332 170 : return 4;
333 0 : default:
334 0 : llvm_unreachable("Only loads and stores have p2align values");
335 : }
336 : }
337 :
338 : /// The operand number of the load or store address in load/store instructions.
339 : static const unsigned LoadAddressOperandNo = 3;
340 : static const unsigned StoreAddressOperandNo = 2;
341 :
342 : /// The operand number of the load or store p2align in load/store instructions.
343 : static const unsigned LoadP2AlignOperandNo = 1;
344 : static const unsigned StoreP2AlignOperandNo = 0;
345 :
346 : /// This is used to indicate block signatures.
347 : enum class ExprType : unsigned {
348 : Void = 0x40,
349 : I32 = 0x7F,
350 : I64 = 0x7E,
351 : F32 = 0x7D,
352 : F64 = 0x7C,
353 : V128 = 0x7B,
354 : ExceptRef = 0x68
355 : };
356 :
357 : /// Instruction opcodes emitted via means other than CodeGen.
358 : static const unsigned Nop = 0x01;
359 : static const unsigned End = 0x0b;
360 :
361 : wasm::ValType toValType(const MVT &Ty);
362 :
363 : } // end namespace WebAssembly
364 : } // end namespace llvm
365 :
366 : #endif
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