/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Bug Summary

File:	lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Warning:	line 207, column 5 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AArch64ExpandPseudoInsts.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/AArch64 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

→

1//===- AArch64ExpandPseudoInsts.cpp - Expand pseudo instructions ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that expands pseudo instructions into target
11// instructions to allow proper scheduling and other late optimizations.  This
12// pass should be run after register allocation but before the post-regalloc
13// scheduling pass.
14//
15//===----------------------------------------------------------------------===//

17#include "AArch64InstrInfo.h"
18#include "AArch64Subtarget.h"
19#include "MCTargetDesc/AArch64AddressingModes.h"
20#include "Utils/AArch64BaseInfo.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/Triple.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/TargetSubtargetInfo.h"
31#include "llvm/IR/DebugLoc.h"
32#include "llvm/MC/MCInstrDesc.h"
33#include "llvm/Pass.h"
34#include "llvm/Support/CodeGen.h"
35#include "llvm/Support/MathExtras.h"
36#include "llvm/Target/TargetMachine.h"
37#include <cassert>
38#include <cstdint>
39#include <iterator>
40#include <limits>
41#include <utility>

43using namespace llvm;

45#define AARCH64_EXPAND_PSEUDO_NAME"AArch64 pseudo instruction expansion pass" "AArch64 pseudo instruction expansion pass"

47namespace {

49class AArch64ExpandPseudo : public MachineFunctionPass {
50public:
const AArch64InstrInfo *TII;

static char ID;

AArch64ExpandPseudo() : MachineFunctionPass(ID) {
  initializeAArch64ExpandPseudoPass(*PassRegistry::getPassRegistry());
}

bool runOnMachineFunction(MachineFunction &Fn) override;

StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME"AArch64 pseudo instruction expansion pass"; }

63private:
bool expandMBB(MachineBasicBlock &MBB);
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
              MachineBasicBlock::iterator &NextMBBI);
bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                  unsigned BitSize);

bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                    unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
                    unsigned ExtendImm, unsigned ZeroReg,
                    MachineBasicBlock::iterator &NextMBBI);
bool expandCMP_SWAP_128(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MBBI,
                        MachineBasicBlock::iterator &NextMBBI);
77};

79} // end anonymous namespace

81char AArch64ExpandPseudo::ID = 0;

83INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",static void *initializeAArch64ExpandPseudoPassOnce(PassRegistry
 &Registry) { PassInfo *PI = new PassInfo( "AArch64 pseudo instruction expansion pass"
, "aarch64-expand-pseudo", &AArch64ExpandPseudo::ID, PassInfo
::NormalCtor_t(callDefaultCtor<AArch64ExpandPseudo>), false
, false); Registry.registerPass(*PI, true); return PI; } static
 llvm::once_flag InitializeAArch64ExpandPseudoPassFlag; void llvm
::initializeAArch64ExpandPseudoPass(PassRegistry &Registry
) { llvm::call_once(InitializeAArch64ExpandPseudoPassFlag, initializeAArch64ExpandPseudoPassOnce
, std::ref(Registry)); }
              AARCH64_EXPAND_PSEUDO_NAME, false, false)static void *initializeAArch64ExpandPseudoPassOnce(PassRegistry
 &Registry) { PassInfo *PI = new PassInfo( "AArch64 pseudo instruction expansion pass"
, "aarch64-expand-pseudo", &AArch64ExpandPseudo::ID, PassInfo
::NormalCtor_t(callDefaultCtor<AArch64ExpandPseudo>), false
, false); Registry.registerPass(*PI, true); return PI; } static
 llvm::once_flag InitializeAArch64ExpandPseudoPassFlag; void llvm
::initializeAArch64ExpandPseudoPass(PassRegistry &Registry
) { llvm::call_once(InitializeAArch64ExpandPseudoPassFlag, initializeAArch64ExpandPseudoPassOnce
, std::ref(Registry)); }

86/// \brief Transfer implicit operands on the pseudo instruction to the
87/// instructions created from the expansion.
88static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
                         MachineInstrBuilder &DefMI) {
const MCInstrDesc &Desc = OldMI.getDesc();
for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); i != e;
33
←
Loop condition is true.  Entering loop body→
     ++i) {
  const MachineOperand &MO = OldMI.getOperand(i);
  assert(MO.isReg() && MO.getReg())(static_cast <bool> (MO.isReg() && MO.getReg())
 ? void (0) : __assert_fail ("MO.isReg() && MO.getReg()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 94, __extension__ __PRETTY_FUNCTION__));
34
←
Within the expansion of the macro 'assert':
→
a
Assuming the condition is true
  if (MO.isUse())
35
←
Assuming the condition is false→
36
←
Taking false branch→
    UseMI.add(MO);
  else
    DefMI.add(MO);
37
←
Calling 'MachineInstrBuilder::add'→
}
100}

102/// \brief Helper function which extracts the specified 16-bit chunk from a
103/// 64-bit value.
104static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
assert(ChunkIdx < 4 && "Out of range chunk index specified!")(static_cast <bool> (ChunkIdx < 4 && "Out of range chunk index specified!"
) ? void (0) : __assert_fail ("ChunkIdx < 4 && \"Out of range chunk index specified!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 105, __extension__ __PRETTY_FUNCTION__));

return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
108}

110/// \brief Helper function which replicates a 16-bit chunk within a 64-bit
111/// value. Indices correspond to element numbers in a v4i16.
112static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) {
assert((FromIdx < 4) && (ToIdx < 4) && "Out of range chunk index specified!")(static_cast <bool> ((FromIdx < 4) && (ToIdx
 < 4) && "Out of range chunk index specified!") ? void
 (0) : __assert_fail ("(FromIdx < 4) && (ToIdx < 4) && \"Out of range chunk index specified!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 113, __extension__ __PRETTY_FUNCTION__));
const unsigned ShiftAmt = ToIdx * 16;

// Replicate the source chunk to the destination position.
const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
// Clear the destination chunk.
Imm &= ~(0xFFFFLL << ShiftAmt);
// Insert the replicated chunk.
return Imm | Chunk;
122}

124/// \brief Helper function which tries to materialize a 64-bit value with an
125/// ORR + MOVK instruction sequence.
126static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI,
                     MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator &MBBI,
                     const AArch64InstrInfo *TII, unsigned ChunkIdx) {
assert(ChunkIdx < 4 && "Out of range chunk index specified!")(static_cast <bool> (ChunkIdx < 4 && "Out of range chunk index specified!"
) ? void (0) : __assert_fail ("ChunkIdx < 4 && \"Out of range chunk index specified!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 130, __extension__ __PRETTY_FUNCTION__));
const unsigned ShiftAmt = ChunkIdx * 16;

uint64_t Encoding;
if (AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding)) {
  // Create the ORR-immediate instruction.
  MachineInstrBuilder MIB =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
          .add(MI.getOperand(0))
          .addReg(AArch64::XZR)
          .addImm(Encoding);

  // Create the MOVK instruction.
  const unsigned Imm16 = getChunk(UImm, ChunkIdx);
  const unsigned DstReg = MI.getOperand(0).getReg();
  const bool DstIsDead = MI.getOperand(0).isDead();
  MachineInstrBuilder MIB1 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
          .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
          .addReg(DstReg)
          .addImm(Imm16)
          .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));

  transferImpOps(MI, MIB, MIB1);
  MI.eraseFromParent();
  return true;
}

return false;
159}

161/// \brief Check whether the given 16-bit chunk replicated to full 64-bit width
162/// can be materialized with an ORR instruction.
163static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;

return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
167}

169/// \brief Check for identical 16-bit chunks within the constant and if so
170/// materialize them with a single ORR instruction. The remaining one or two
171/// 16-bit chunks will be materialized with MOVK instructions.
172///
173/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
174/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
175/// an ORR instruction.
176static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
                               MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator &MBBI,
                               const AArch64InstrInfo *TII) {
using CountMap = DenseMap<uint64_t, unsigned>;

CountMap Counts;

// Scan the constant and count how often every chunk occurs.
for (unsigned Idx = 0; Idx < 4; ++Idx)
  ++Counts[getChunk(UImm, Idx)];

// Traverse the chunks to find one which occurs more than once.
for (CountMap::const_iterator Chunk = Counts.begin(), End = Counts.end();
     Chunk != End; ++Chunk) {
  const uint64_t ChunkVal = Chunk->first;
  const unsigned Count = Chunk->second;

  uint64_t Encoding = 0;

  // We are looking for chunks which have two or three instances and can be
  // materialized with an ORR instruction.
  if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
    continue;

  const bool CountThree = Count == 3;
  // Create the ORR-immediate instruction.
  MachineInstrBuilder MIB =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
          .add(MI.getOperand(0))
          .addReg(AArch64::XZR)
          .addImm(Encoding);

  const unsigned DstReg = MI.getOperand(0).getReg();
  const bool DstIsDead = MI.getOperand(0).isDead();

  unsigned ShiftAmt = 0;
  uint64_t Imm16 = 0;
  // Find the first chunk not materialized with the ORR instruction.
  for (; ShiftAmt < 64; ShiftAmt += 16) {
    Imm16 = (UImm >> ShiftAmt) & 0xFFFF;

    if (Imm16 != ChunkVal)
      break;
  }

  // Create the first MOVK instruction.
  MachineInstrBuilder MIB1 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
          .addReg(DstReg,
                  RegState::Define | getDeadRegState(DstIsDead && CountThree))
          .addReg(DstReg)
          .addImm(Imm16)
          .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));

  // In case we have three instances the whole constant is now materialized
  // and we can exit.
  if (CountThree) {
    transferImpOps(MI, MIB, MIB1);
    MI.eraseFromParent();
    return true;
  }

  // Find the remaining chunk which needs to be materialized.
  for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
    Imm16 = (UImm >> ShiftAmt) & 0xFFFF;

    if (Imm16 != ChunkVal)
      break;
  }

  // Create the second MOVK instruction.
  MachineInstrBuilder MIB2 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
          .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
          .addReg(DstReg)
          .addImm(Imm16)
          .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));

  transferImpOps(MI, MIB, MIB2);
  MI.eraseFromParent();
  return true;
}

return false;
261}

263/// \brief Check whether this chunk matches the pattern '1...0...'. This pattern
264/// starts a contiguous sequence of ones if we look at the bits from the LSB
265/// towards the MSB.
266static bool isStartChunk(uint64_t Chunk) {
if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
  return false;

return isMask_64(~Chunk);
271}

273/// \brief Check whether this chunk matches the pattern '0...1...' This pattern
274/// ends a contiguous sequence of ones if we look at the bits from the LSB
275/// towards the MSB.
276static bool isEndChunk(uint64_t Chunk) {
if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
  return false;

return isMask_64(Chunk);
281}

283/// \brief Clear or set all bits in the chunk at the given index.
284static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
const uint64_t Mask = 0xFFFF;

if (Clear)
  // Clear chunk in the immediate.
  Imm &= ~(Mask << (Idx * 16));
else
  // Set all bits in the immediate for the particular chunk.
  Imm |= Mask << (Idx * 16);

return Imm;
295}

297/// \brief Check whether the constant contains a sequence of contiguous ones,
298/// which might be interrupted by one or two chunks. If so, materialize the
299/// sequence of contiguous ones with an ORR instruction.
300/// Materialize the chunks which are either interrupting the sequence or outside
301/// of the sequence with a MOVK instruction.
302///
303/// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
304/// which ends the sequence (0...1...). Then we are looking for constants which
305/// contain at least one S and E chunk.
306/// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
307///
308/// We are also looking for constants like |S|A|B|E| where the contiguous
309/// sequence of ones wraps around the MSB into the LSB.
310static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
                            MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator &MBBI,
                            const AArch64InstrInfo *TII) {
const int NotSet = -1;
const uint64_t Mask = 0xFFFF;

int StartIdx = NotSet;
int EndIdx = NotSet;
// Try to find the chunks which start/end a contiguous sequence of ones.
for (int Idx = 0; Idx < 4; ++Idx) {
  int64_t Chunk = getChunk(UImm, Idx);
  // Sign extend the 16-bit chunk to 64-bit.
  Chunk = (Chunk << 48) >> 48;

  if (isStartChunk(Chunk))
    StartIdx = Idx;
  else if (isEndChunk(Chunk))
    EndIdx = Idx;
}

// Early exit in case we can't find a start/end chunk.
if (StartIdx == NotSet || EndIdx == NotSet)
  return false;

// Outside of the contiguous sequence of ones everything needs to be zero.
uint64_t Outside = 0;
// Chunks between the start and end chunk need to have all their bits set.
uint64_t Inside = Mask;

// If our contiguous sequence of ones wraps around from the MSB into the LSB,
// just swap indices and pretend we are materializing a contiguous sequence
// of zeros surrounded by a contiguous sequence of ones.
if (StartIdx > EndIdx) {
  std::swap(StartIdx, EndIdx);
  std::swap(Outside, Inside);
}

uint64_t OrrImm = UImm;
int FirstMovkIdx = NotSet;
int SecondMovkIdx = NotSet;

// Find out which chunks we need to patch up to obtain a contiguous sequence
// of ones.
for (int Idx = 0; Idx < 4; ++Idx) {
  const uint64_t Chunk = getChunk(UImm, Idx);

  // Check whether we are looking at a chunk which is not part of the
  // contiguous sequence of ones.
  if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
    OrrImm = updateImm(OrrImm, Idx, Outside == 0);

    // Remember the index we need to patch.
    if (FirstMovkIdx == NotSet)
      FirstMovkIdx = Idx;
    else
      SecondMovkIdx = Idx;

    // Check whether we are looking a chunk which is part of the contiguous
    // sequence of ones.
  } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
    OrrImm = updateImm(OrrImm, Idx, Inside != Mask);

    // Remember the index we need to patch.
    if (FirstMovkIdx == NotSet)
      FirstMovkIdx = Idx;
    else
      SecondMovkIdx = Idx;
  }
}
assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!")(static_cast <bool> (FirstMovkIdx != NotSet && "Constant materializable with single ORR!"
) ? void (0) : __assert_fail ("FirstMovkIdx != NotSet && \"Constant materializable with single ORR!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 380, __extension__ __PRETTY_FUNCTION__));

// Create the ORR-immediate instruction.
uint64_t Encoding = 0;
AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
MachineInstrBuilder MIB =
    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
        .add(MI.getOperand(0))
        .addReg(AArch64::XZR)
        .addImm(Encoding);

const unsigned DstReg = MI.getOperand(0).getReg();
const bool DstIsDead = MI.getOperand(0).isDead();

const bool SingleMovk = SecondMovkIdx == NotSet;
// Create the first MOVK instruction.
MachineInstrBuilder MIB1 =
    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
        .addReg(DstReg,
                RegState::Define | getDeadRegState(DstIsDead && SingleMovk))
        .addReg(DstReg)
        .addImm(getChunk(UImm, FirstMovkIdx))
        .addImm(
            AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16));

// Early exit in case we only need to emit a single MOVK instruction.
if (SingleMovk) {
  transferImpOps(MI, MIB, MIB1);
  MI.eraseFromParent();
  return true;
}

// Create the second MOVK instruction.
MachineInstrBuilder MIB2 =
    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
        .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
        .addReg(DstReg)
        .addImm(getChunk(UImm, SecondMovkIdx))
        .addImm(
            AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16));

transferImpOps(MI, MIB, MIB2);
MI.eraseFromParent();
return true;
424}

426/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
427/// real move-immediate instructions to synthesize the immediate.
428bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator MBBI,
                                     unsigned BitSize) {
MachineInstr &MI = *MBBI;
unsigned DstReg = MI.getOperand(0).getReg();
uint64_t Imm = MI.getOperand(1).getImm();
const unsigned Mask = 0xFFFF;

if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
6
←
Assuming 'DstReg' is not equal to XZR→
7
←
Assuming 'DstReg' is not equal to WZR→
8
←
Taking false branch→
  // Useless def, and we don't want to risk creating an invalid ORR (which
  // would really write to sp).
  MI.eraseFromParent();
  return true;
}

// Try a MOVI instruction (aka ORR-immediate with the zero register).
uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
uint64_t Encoding;
if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
9
←
Taking false branch→
  unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
  MachineInstrBuilder MIB =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
          .add(MI.getOperand(0))
          .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
          .addImm(Encoding);
  transferImpOps(MI, MIB, MIB);
  MI.eraseFromParent();
  return true;
}

// Scan the immediate and count the number of 16-bit chunks which are either
// all ones or all zeros.
unsigned OneChunks = 0;
unsigned ZeroChunks = 0;
for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
10
←
Loop condition is true.  Entering loop body→
15
←
Loop condition is true.  Entering loop body→
18
←
Loop condition is false. Execution continues on line 493→
  const unsigned Chunk = (Imm >> Shift) & Mask;
  if (Chunk == Mask)
11
←
Assuming 'Chunk' is not equal to 'Mask'→
12
←
Taking false branch→
16
←
Assuming 'Chunk' is equal to 'Mask'→
17
←
Taking true branch→
    OneChunks++;
  else if (Chunk == 0)
13
←
Assuming 'Chunk' is not equal to 0→
14
←
Taking false branch→
    ZeroChunks++;
}

// Since we can't materialize the constant with a single ORR instruction,
// let's see whether we can materialize 3/4 of the constant with an ORR
// instruction and use an additional MOVK instruction to materialize the
// remaining 1/4.
//
// We are looking for constants with a pattern like: |A|X|B|X| or |X|A|X|B|.
//
// E.g. assuming |A|X|A|X| is a pattern which can be materialized with ORR,
// we would create the following instruction sequence:
//
// ORR x0, xzr, |A|X|A|X|
// MOVK x0, |B|, LSL #16
//
// Only look at 64-bit constants which can't be materialized with a single
// instruction e.g. which have less than either three all zero or all one
// chunks.
//
// Ignore 32-bit constants here, they always can be materialized with a
// MOVZ/MOVN + MOVK pair. Since the 32-bit constant can't be materialized
// with a single ORR, the best sequence we can achieve is a ORR + MOVK pair.
// Thus we fall back to the default code below which in the best case creates
// a single MOVZ/MOVN instruction (in case one chunk is all zero or all one).
//
if (BitSize == 64 && OneChunks < 3 && ZeroChunks < 3) {
  // If we interpret the 64-bit constant as a v4i16, are elements 0 and 2
  // identical?
  if (getChunk(UImm, 0) == getChunk(UImm, 2)) {
    // See if we can come up with a constant which can be materialized with
    // ORR-immediate by replicating element 3 into element 1.
    uint64_t OrrImm = replicateChunk(UImm, 3, 1);
    if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 1))
      return true;

    // See if we can come up with a constant which can be materialized with
    // ORR-immediate by replicating element 1 into element 3.
    OrrImm = replicateChunk(UImm, 1, 3);
    if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 3))
      return true;

    // If we interpret the 64-bit constant as a v4i16, are elements 1 and 3
    // identical?
  } else if (getChunk(UImm, 1) == getChunk(UImm, 3)) {
    // See if we can come up with a constant which can be materialized with
    // ORR-immediate by replicating element 2 into element 0.
    uint64_t OrrImm = replicateChunk(UImm, 2, 0);
    if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 0))
      return true;

    // See if we can come up with a constant which can be materialized with
    // ORR-immediate by replicating element 1 into element 3.
    OrrImm = replicateChunk(UImm, 0, 2);
    if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 2))
      return true;
  }
}

// Check for identical 16-bit chunks within the constant and if so materialize
// them with a single ORR instruction. The remaining one or two 16-bit chunks
// will be materialized with MOVK instructions.
if (BitSize == 64 && tryToreplicateChunks(UImm, MI, MBB, MBBI, TII))
  return true;

// Check whether the constant contains a sequence of contiguous ones, which
// might be interrupted by one or two chunks. If so, materialize the sequence
// of contiguous ones with an ORR instruction. Materialize the chunks which
// are either interrupting the sequence or outside of the sequence with a
// MOVK instruction.
if (BitSize == 64 && trySequenceOfOnes(UImm, MI, MBB, MBBI, TII))
  return true;

// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
// more MOVK instructions to insert additional 16-bit portions into the
// lower bits.
bool isNeg = false;

// Use MOVN to materialize the high bits if we have more all one chunks
// than all zero chunks.
if (OneChunks > ZeroChunks) {
19
←
Taking true branch→
  isNeg = true;
  Imm = ~Imm;
}

unsigned FirstOpc;
if (BitSize == 32) {
20
←
Taking true branch→
  Imm &= (1LL << 32) - 1;
  FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64::MOVZWi);
21
←
'?' condition is true→
} else {
  FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
}
unsigned Shift = 0;     // LSL amount for high bits with MOVZ/MOVN
unsigned LastShift = 0; // LSL amount for last MOVK
if (Imm != 0) {
22
←
Assuming 'Imm' is not equal to 0→
23
←
Taking true branch→
  unsigned LZ = countLeadingZeros(Imm);
  unsigned TZ = countTrailingZeros(Imm);
  Shift = (TZ / 16) * 16;
  LastShift = ((63 - LZ) / 16) * 16;
}
unsigned Imm16 = (Imm >> Shift) & Mask;
bool DstIsDead = MI.getOperand(0).isDead();
MachineInstrBuilder MIB1 =
    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
        .addReg(DstReg, RegState::Define |
                getDeadRegState(DstIsDead && Shift == LastShift))
24
←
Assuming 'DstIsDead' is 0→
        .addImm(Imm16)
        .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));

// If a MOVN was used for the high bits of a negative value, flip the rest
// of the bits back for use with MOVK.
if (isNeg)
25
←
Taking true branch→
  Imm = ~Imm;

if (Shift == LastShift) {
26
←
Taking false branch→
  transferImpOps(MI, MIB1, MIB1);
  MI.eraseFromParent();
  return true;
}

MachineInstrBuilder MIB2;
27
←
Calling defaulted default constructor for 'MachineInstrBuilder'→
29
←
Returning from default constructor for 'MachineInstrBuilder'→
unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
30
←
'?' condition is true→
while (Shift < LastShift) {
31
←
Loop condition is false. Execution continues on line 603→
  Shift += 16;
  Imm16 = (Imm >> Shift) & Mask;
  if (Imm16 == (isNeg ? Mask : 0))
    continue; // This 16-bit portion is already set correctly.
  MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
             .addReg(DstReg,
                     RegState::Define |
                     getDeadRegState(DstIsDead && Shift == LastShift))
             .addReg(DstReg)
             .addImm(Imm16)
             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
}

transferImpOps(MI, MIB1, MIB2);
32
←
Calling 'transferImpOps'→
MI.eraseFromParent();
return true;
606}

608bool AArch64ExpandPseudo::expandCMP_SWAP(
  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
  unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
  MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
const MachineOperand &Dest = MI.getOperand(0);
unsigned StatusReg = MI.getOperand(1).getReg();
bool StatusDead = MI.getOperand(1).isDead();
// Duplicating undef operands into 2 instructions does not guarantee the same
// value on both; However undef should be replaced by xzr anyway.
assert(!MI.getOperand(2).isUndef() && "cannot handle undef")(static_cast <bool> (!MI.getOperand(2).isUndef() &&
 "cannot handle undef") ? void (0) : __assert_fail ("!MI.getOperand(2).isUndef() && \"cannot handle undef\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 619, __extension__ __PRETTY_FUNCTION__));
unsigned AddrReg = MI.getOperand(2).getReg();
unsigned DesiredReg = MI.getOperand(3).getReg();
unsigned NewReg = MI.getOperand(4).getReg();

MachineFunction *MF = MBB.getParent();
auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());

MF->insert(++MBB.getIterator(), LoadCmpBB);
MF->insert(++LoadCmpBB->getIterator(), StoreBB);
MF->insert(++StoreBB->getIterator(), DoneBB);

// .Lloadcmp:
//     mov wStatus, 0
//     ldaxr xDest, [xAddr]
//     cmp xDest, xDesired
//     b.ne .Ldone
if (!StatusDead)
  BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
    .addImm(0).addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
    .addReg(AddrReg);
BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
    .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
    .addReg(DesiredReg)
    .addImm(ExtendImm);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
    .addImm(AArch64CC::NE)
    .addMBB(DoneBB)
    .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
LoadCmpBB->addSuccessor(DoneBB);
LoadCmpBB->addSuccessor(StoreBB);

// .Lstore:
//     stlxr wStatus, xNew, [xAddr]
//     cbnz wStatus, .Lloadcmp
BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
    .addReg(NewReg)
    .addReg(AddrReg);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
    .addReg(StatusReg, getKillRegState(StatusDead))
    .addMBB(LoadCmpBB);
StoreBB->addSuccessor(LoadCmpBB);
StoreBB->addSuccessor(DoneBB);

DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
DoneBB->transferSuccessors(&MBB);

MBB.addSuccessor(LoadCmpBB);

NextMBBI = MBB.end();
MI.eraseFromParent();

// Recompute livein lists.
LivePhysRegs LiveRegs;
computeAndAddLiveIns(LiveRegs, *DoneBB);
computeAndAddLiveIns(LiveRegs, *StoreBB);
computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
// Do an extra pass around the loop to get loop carried registers right.
StoreBB->clearLiveIns();
computeAndAddLiveIns(LiveRegs, *StoreBB);
LoadCmpBB->clearLiveIns();
computeAndAddLiveIns(LiveRegs, *LoadCmpBB);

return true;
686}

688bool AArch64ExpandPseudo::expandCMP_SWAP_128(
  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
MachineOperand &DestLo = MI.getOperand(0);
MachineOperand &DestHi = MI.getOperand(1);
unsigned StatusReg = MI.getOperand(2).getReg();
bool StatusDead = MI.getOperand(2).isDead();
// Duplicating undef operands into 2 instructions does not guarantee the same
// value on both; However undef should be replaced by xzr anyway.
assert(!MI.getOperand(3).isUndef() && "cannot handle undef")(static_cast <bool> (!MI.getOperand(3).isUndef() &&
 "cannot handle undef") ? void (0) : __assert_fail ("!MI.getOperand(3).isUndef() && \"cannot handle undef\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 699, __extension__ __PRETTY_FUNCTION__));
unsigned AddrReg = MI.getOperand(3).getReg();
unsigned DesiredLoReg = MI.getOperand(4).getReg();
unsigned DesiredHiReg = MI.getOperand(5).getReg();
unsigned NewLoReg = MI.getOperand(6).getReg();
unsigned NewHiReg = MI.getOperand(7).getReg();

MachineFunction *MF = MBB.getParent();
auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());

MF->insert(++MBB.getIterator(), LoadCmpBB);
MF->insert(++LoadCmpBB->getIterator(), StoreBB);
MF->insert(++StoreBB->getIterator(), DoneBB);

// .Lloadcmp:
//     ldaxp xDestLo, xDestHi, [xAddr]
//     cmp xDestLo, xDesiredLo
//     sbcs xDestHi, xDesiredHi
//     b.ne .Ldone
BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
    .addReg(DestLo.getReg(), RegState::Define)
    .addReg(DestHi.getReg(), RegState::Define)
    .addReg(AddrReg);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
    .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
    .addReg(DesiredLoReg)
    .addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
  .addUse(AArch64::WZR)
  .addUse(AArch64::WZR)
  .addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
    .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
    .addReg(DesiredHiReg)
    .addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
    .addUse(StatusReg, RegState::Kill)
    .addUse(StatusReg, RegState::Kill)
    .addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
    .addUse(StatusReg, getKillRegState(StatusDead))
    .addMBB(DoneBB);
LoadCmpBB->addSuccessor(DoneBB);
LoadCmpBB->addSuccessor(StoreBB);

// .Lstore:
//     stlxp wStatus, xNewLo, xNewHi, [xAddr]
//     cbnz wStatus, .Lloadcmp
BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)
    .addReg(NewLoReg)
    .addReg(NewHiReg)
    .addReg(AddrReg);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
    .addReg(StatusReg, getKillRegState(StatusDead))
    .addMBB(LoadCmpBB);
StoreBB->addSuccessor(LoadCmpBB);
StoreBB->addSuccessor(DoneBB);

DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
DoneBB->transferSuccessors(&MBB);

MBB.addSuccessor(LoadCmpBB);

NextMBBI = MBB.end();
MI.eraseFromParent();

// Recompute liveness bottom up.
LivePhysRegs LiveRegs;
computeAndAddLiveIns(LiveRegs, *DoneBB);
computeAndAddLiveIns(LiveRegs, *StoreBB);
computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
// Do an extra pass in the loop to get the loop carried dependencies right.
StoreBB->clearLiveIns();
computeAndAddLiveIns(LiveRegs, *StoreBB);
LoadCmpBB->clearLiveIns();
computeAndAddLiveIns(LiveRegs, *LoadCmpBB);

return true;
779}

781/// \brief If MBBI references a pseudo instruction that should be expanded here,
782/// do the expansion and return true.  Otherwise return false.
783bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MBBI,
                                 MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
switch (Opcode) {
4
←
Control jumps to 'case MOVi32imm:'  at line 937→
default:
  break;

case AArch64::ADDWrr:
case AArch64::SUBWrr:
case AArch64::ADDXrr:
case AArch64::SUBXrr:
case AArch64::ADDSWrr:
case AArch64::SUBSWrr:
case AArch64::ADDSXrr:
case AArch64::SUBSXrr:
case AArch64::ANDWrr:
case AArch64::ANDXrr:
case AArch64::BICWrr:
case AArch64::BICXrr:
case AArch64::ANDSWrr:
case AArch64::ANDSXrr:
case AArch64::BICSWrr:
case AArch64::BICSXrr:
case AArch64::EONWrr:
case AArch64::EONXrr:
case AArch64::EORWrr:
case AArch64::EORXrr:
case AArch64::ORNWrr:
case AArch64::ORNXrr:
case AArch64::ORRWrr:
case AArch64::ORRXrr: {
  unsigned Opcode;
  switch (MI.getOpcode()) {
  default:
    return false;
  case AArch64::ADDWrr:      Opcode = AArch64::ADDWrs; break;
  case AArch64::SUBWrr:      Opcode = AArch64::SUBWrs; break;
  case AArch64::ADDXrr:      Opcode = AArch64::ADDXrs; break;
  case AArch64::SUBXrr:      Opcode = AArch64::SUBXrs; break;
  case AArch64::ADDSWrr:     Opcode = AArch64::ADDSWrs; break;
  case AArch64::SUBSWrr:     Opcode = AArch64::SUBSWrs; break;
  case AArch64::ADDSXrr:     Opcode = AArch64::ADDSXrs; break;
  case AArch64::SUBSXrr:     Opcode = AArch64::SUBSXrs; break;
  case AArch64::ANDWrr:      Opcode = AArch64::ANDWrs; break;
  case AArch64::ANDXrr:      Opcode = AArch64::ANDXrs; break;
  case AArch64::BICWrr:      Opcode = AArch64::BICWrs; break;
  case AArch64::BICXrr:      Opcode = AArch64::BICXrs; break;
  case AArch64::ANDSWrr:     Opcode = AArch64::ANDSWrs; break;
  case AArch64::ANDSXrr:     Opcode = AArch64::ANDSXrs; break;
  case AArch64::BICSWrr:     Opcode = AArch64::BICSWrs; break;
  case AArch64::BICSXrr:     Opcode = AArch64::BICSXrs; break;
  case AArch64::EONWrr:      Opcode = AArch64::EONWrs; break;
  case AArch64::EONXrr:      Opcode = AArch64::EONXrs; break;
  case AArch64::EORWrr:      Opcode = AArch64::EORWrs; break;
  case AArch64::EORXrr:      Opcode = AArch64::EORXrs; break;
  case AArch64::ORNWrr:      Opcode = AArch64::ORNWrs; break;
  case AArch64::ORNXrr:      Opcode = AArch64::ORNXrs; break;
  case AArch64::ORRWrr:      Opcode = AArch64::ORRWrs; break;
  case AArch64::ORRXrr:      Opcode = AArch64::ORRXrs; break;
  }
  MachineInstrBuilder MIB1 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
              MI.getOperand(0).getReg())
          .add(MI.getOperand(1))
          .add(MI.getOperand(2))
          .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
  transferImpOps(MI, MIB1, MIB1);
  MI.eraseFromParent();
  return true;
}

case AArch64::LOADgot: {
  // Expand into ADRP + LDR.
  unsigned DstReg = MI.getOperand(0).getReg();
  const MachineOperand &MO1 = MI.getOperand(1);
  unsigned Flags = MO1.getTargetFlags();
  MachineInstrBuilder MIB1 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
  MachineInstrBuilder MIB2 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRXui))
          .add(MI.getOperand(0))
          .addReg(DstReg);

  if (MO1.isGlobal()) {
    MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
    MIB2.addGlobalAddress(MO1.getGlobal(), 0,
                          Flags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
  } else if (MO1.isSymbol()) {
    MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | AArch64II::MO_PAGE);
    MIB2.addExternalSymbol(MO1.getSymbolName(),
                           Flags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
  } else {
    assert(MO1.isCPI() &&(static_cast <bool> (MO1.isCPI() && "Only expect globals, externalsymbols, or constant pools"
) ? void (0) : __assert_fail ("MO1.isCPI() && \"Only expect globals, externalsymbols, or constant pools\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 878, __extension__ __PRETTY_FUNCTION__))
           "Only expect globals, externalsymbols, or constant pools")(static_cast <bool> (MO1.isCPI() && "Only expect globals, externalsymbols, or constant pools"
) ? void (0) : __assert_fail ("MO1.isCPI() && \"Only expect globals, externalsymbols, or constant pools\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
, 878, __extension__ __PRETTY_FUNCTION__));
    MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                              Flags | AArch64II::MO_PAGE);
    MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                              Flags | AArch64II::MO_PAGEOFF |
                                  AArch64II::MO_NC);
  }

  transferImpOps(MI, MIB1, MIB2);
  MI.eraseFromParent();
  return true;
}

case AArch64::MOVaddr:
case AArch64::MOVaddrJT:
case AArch64::MOVaddrCP:
case AArch64::MOVaddrBA:
case AArch64::MOVaddrTLS:
case AArch64::MOVaddrEXT: {
  // Expand into ADRP + ADD.
  unsigned DstReg = MI.getOperand(0).getReg();
  MachineInstrBuilder MIB1 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
          .add(MI.getOperand(1));

  MachineInstrBuilder MIB2 =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
          .add(MI.getOperand(0))
          .addReg(DstReg)
          .add(MI.getOperand(2))
          .addImm(0);

  transferImpOps(MI, MIB1, MIB2);
  MI.eraseFromParent();
  return true;
}
case AArch64::ADDlowTLS:
  // Produce a plain ADD
  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
      .add(MI.getOperand(0))
      .add(MI.getOperand(1))
      .add(MI.getOperand(2))
      .addImm(0);
  MI.eraseFromParent();
  return true;

case AArch64::MOVbaseTLS: {
  unsigned DstReg = MI.getOperand(0).getReg();
  auto SysReg = AArch64SysReg::TPIDR_EL0;
  MachineFunction *MF = MBB.getParent();
  if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
      MF->getTarget().getCodeModel() == CodeModel::Kernel)
    SysReg = AArch64SysReg::TPIDR_EL1;
  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
      .addImm(SysReg);
  MI.eraseFromParent();
  return true;
}

case AArch64::MOVi32imm:
  return expandMOVImm(MBB, MBBI, 32);
5
←
Calling 'AArch64ExpandPseudo::expandMOVImm'→
case AArch64::MOVi64imm:
  return expandMOVImm(MBB, MBBI, 64);
case AArch64::RET_ReallyLR: {
  // Hiding the LR use with RET_ReallyLR may lead to extra kills in the
  // function and missing live-ins. We are fine in practice because callee
  // saved register handling ensures the register value is restored before
  // RET, but we need the undef flag here to appease the MachineVerifier
  // liveness checks.
  MachineInstrBuilder MIB =
      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
        .addReg(AArch64::LR, RegState::Undef);
  transferImpOps(MI, MIB, MIB);
  MI.eraseFromParent();
  return true;
}
case AArch64::CMP_SWAP_8:
  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB,
                        AArch64::SUBSWrx,
                        AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0),
                        AArch64::WZR, NextMBBI);
case AArch64::CMP_SWAP_16:
  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH,
                        AArch64::SUBSWrx,
                        AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0),
                        AArch64::WZR, NextMBBI);
case AArch64::CMP_SWAP_32:
  return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW,
                        AArch64::SUBSWrs,
                        AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
                        AArch64::WZR, NextMBBI);
case AArch64::CMP_SWAP_64:
  return expandCMP_SWAP(MBB, MBBI,
                        AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs,
                        AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
                        AArch64::XZR, NextMBBI);
case AArch64::CMP_SWAP_128:
  return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);

case AArch64::AESMCrrTied:
case AArch64::AESIMCrrTied: {
  MachineInstrBuilder MIB =
  BuildMI(MBB, MBBI, MI.getDebugLoc(),
          TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
                                                    AArch64::AESIMCrr))
    .add(MI.getOperand(0))
    .add(MI.getOperand(1));
  transferImpOps(MI, MIB, MIB);
  MI.eraseFromParent();
  return true;
 }
}
return false;
991}

993/// \brief Iterate over the instructions in basic block MBB and expand any
994/// pseudo instructions.  Return true if anything was modified.
995bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;

MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
2
←
Loop condition is true.  Entering loop body→
  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
  Modified |= expandMI(MBB, MBBI, NMBBI);
3
←
Calling 'AArch64ExpandPseudo::expandMI'→
  MBBI = NMBBI;
}

return Modified;
1006}

1008bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());

bool Modified = false;
for (auto &MBB : MF)
  Modified |= expandMBB(MBB);
1
Calling 'AArch64ExpandPseudo::expandMBB'→
return Modified;
1015}

1017/// \brief Returns an instance of the pseudo instruction expansion pass.
1018FunctionPass *llvm::createAArch64ExpandPseudoPass() {
return new AArch64ExpandPseudo();
1020}

←

/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h

1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file exposes a function named BuildMI, which is useful for dramatically
11// simplifying how MachineInstr's are created.  It allows use of code like this:
12//
13//   M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
14//           .addReg(argVal1)
15//           .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//

19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H

22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35#include <utility>

37namespace llvm {

39class MCInstrDesc;
40class MDNode;

42namespace RegState {

enum {
  Define         = 0x2,
  Implicit       = 0x4,
  Kill           = 0x8,
  Dead           = 0x10,
  Undef          = 0x20,
  EarlyClobber   = 0x40,
  Debug          = 0x80,
  InternalRead   = 0x100,
  Renamable      = 0x200,
  DefineNoRead   = Define | Undef,
  ImplicitDefine = Implicit | Define,
  ImplicitKill   = Implicit | Kill
};

59} // end namespace RegState

61class MachineInstrBuilder {
MachineFunction *MF = nullptr;
MachineInstr *MI = nullptr;
28
←
Null pointer value stored to 'MIB2.MI'→

65public:
MachineInstrBuilder() = default;

/// Create a MachineInstrBuilder for manipulating an existing instruction.
/// F must be the machine function that was used to allocate I.
MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
    : MF(&F), MI(&*I) {}

/// Allow automatic conversion to the machine instruction we are working on.
operator MachineInstr*() const { return MI; }
MachineInstr *operator->() const { return MI; }
operator MachineBasicBlock::iterator() const { return MI; }

/// If conversion operators fail, use this method to get the MachineInstr
/// explicitly.
MachineInstr *getInstr() const { return MI; }

/// Add a new virtual register operand.
const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
                                  unsigned SubReg = 0) const {
  assert((flags & 0x1) == 0 &&(static_cast <bool> ((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? void (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __extension__ __PRETTY_FUNCTION__))
         "Passing in 'true' to addReg is forbidden! Use enums instead.")(static_cast <bool> ((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? void (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __extension__ __PRETTY_FUNCTION__));
  MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
                                             flags & RegState::Define,
                                             flags & RegState::Implicit,
                                             flags & RegState::Kill,
                                             flags & RegState::Dead,
                                             flags & RegState::Undef,
                                             flags & RegState::EarlyClobber,
                                             SubReg,
                                             flags & RegState::Debug,
                                             flags & RegState::InternalRead,
                                             flags & RegState::Renamable));
  return *this;
}

/// Add a virtual register definition operand.
const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
                                  unsigned SubReg = 0) const {
  return addReg(RegNo, Flags | RegState::Define, SubReg);
}

/// Add a virtual register use operand. It is an error for Flags to contain
/// `RegState::Define` when calling this function.
const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0,
                                  unsigned SubReg = 0) const {
  assert(!(Flags & RegState::Define) &&(static_cast <bool> (!(Flags & RegState::Define) &&
 "Misleading addUse defines register, use addReg instead.") ?
 void (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __extension__ __PRETTY_FUNCTION__))
         "Misleading addUse defines register, use addReg instead.")(static_cast <bool> (!(Flags & RegState::Define) &&
 "Misleading addUse defines register, use addReg instead.") ?
 void (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __extension__ __PRETTY_FUNCTION__));
  return addReg(RegNo, Flags, SubReg);
}

/// Add a new immediate operand.
const MachineInstrBuilder &addImm(int64_t Val) const {
  MI->addOperand(*MF, MachineOperand::CreateImm(Val));
  return *this;
}

const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
  MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
  return *this;
}

const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
  MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
  return *this;
}

const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
                                  unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addFrameIndex(int Idx) const {
  MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
  return *this;
}

const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
                                                int Offset = 0,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
                                                        TargetFlags));
  return *this;
}

const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
                                            int64_t Offset = 0,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addExternalSymbol(const char *FnName,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
                                           int64_t Offset = 0,
                                        unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
  MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
  return *this;
}

const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
  MI->addMemOperand(*MF, MMO);
  return *this;
}

const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b,
                                      MachineInstr::mmo_iterator e) const {
  MI->setMemRefs(b, e);
  return *this;
}

const MachineInstrBuilder &setMemRefs(std::pair<MachineInstr::mmo_iterator,
                                      unsigned> MemOperandsRef) const {
  MI->setMemRefs(MemOperandsRef);
  return *this;
}

const MachineInstrBuilder &add(const MachineOperand &MO) const {
  MI->addOperand(*MF, MO);
38
←
Called C++ object pointer is null
  return *this;
}

const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
  for (const MachineOperand &MO : MOs) {
    MI->addOperand(*MF, MO);
  }
  return *this;
}

const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
  MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
  assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__))
                             : true) &&(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__))
         "first MDNode argument of a DBG_VALUE not a variable")(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__));
  return *this;
}

const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
  MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
  return *this;
}

const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
  MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
  return *this;
}

const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
  MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
  return *this;
}

const MachineInstrBuilder &addSym(MCSymbol *Sym,
                                  unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
  return *this;
}

const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
  MI->setFlags(Flags);
  return *this;
}

const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
  MI->setFlag(Flag);
  return *this;
}

// Add a displacement from an existing MachineOperand with an added offset.
const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
                                   unsigned char TargetFlags = 0) const {
  // If caller specifies new TargetFlags then use it, otherwise the
  // default behavior is to copy the target flags from the existing
  // MachineOperand. This means if the caller wants to clear the
  // target flags it needs to do so explicitly.
  if (0 == TargetFlags)
    TargetFlags = Disp.getTargetFlags();

  switch (Disp.getType()) {
    default:
      llvm_unreachable("Unhandled operand type in addDisp()")::llvm::llvm_unreachable_internal("Unhandled operand type in addDisp()"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 269);
    case MachineOperand::MO_Immediate:
      return addImm(Disp.getImm() + off);
    case MachineOperand::MO_ConstantPoolIndex:
      return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
                                  TargetFlags);
    case MachineOperand::MO_GlobalAddress:
      return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
                              TargetFlags);
  }
}

/// Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder &
copyImplicitOps(const MachineInstr &OtherMI) const {
  MI->copyImplicitOps(*MF, OtherMI);
  return *this;
}

bool constrainAllUses(const TargetInstrInfo &TII,
                      const TargetRegisterInfo &TRI,
                      const RegisterBankInfo &RBI) const {
  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
}
293};

295/// Builder interface. Specify how to create the initial instruction itself.
296inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
299}

301/// This version of the builder sets up the first operand as a
302/// destination virtual register.
303inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                 const MCInstrDesc &MCID, unsigned DestReg) {
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
         .addReg(DestReg, RegState::Define);
307}

309/// This version of the builder inserts the newly-built instruction before
310/// the given position in the given MachineBasicBlock, and sets up the first
311/// operand as a destination virtual register.
312inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 unsigned DestReg) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
320}

322/// This version of the builder inserts the newly-built instruction before
323/// the given position in the given MachineBasicBlock, and sets up the first
324/// operand as a destination virtual register.
325///
326/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
327/// added to the same bundle.
328inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::instr_iterator I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 unsigned DestReg) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
336}

338inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 unsigned DestReg) {
// Calling the overload for instr_iterator is always correct.  However, the
// definition is not available in headers, so inline the check.
if (I.isInsideBundle())
  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
346}

348inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 unsigned DestReg) {
return BuildMI(BB, *I, DL, MCID, DestReg);
352}

354/// This version of the builder inserts the newly-built instruction before the
355/// given position in the given MachineBasicBlock, and does NOT take a
356/// destination register.
357inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI);
365}

367inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::instr_iterator I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI);
375}

377inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
// Calling the overload for instr_iterator is always correct.  However, the
// definition is not available in headers, so inline the check.
if (I.isInsideBundle())
  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
385}

387inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return BuildMI(BB, *I, DL, MCID);
391}

393/// This version of the builder inserts the newly-built instruction at the end
394/// of the given MachineBasicBlock, and does NOT take a destination register.
395inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return BuildMI(*BB, BB->end(), DL, MCID);
398}

400/// This version of the builder inserts the newly-built instruction at the
401/// end of the given MachineBasicBlock, and sets up the first operand as a
402/// destination virtual register.
403inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
                                 const MCInstrDesc &MCID, unsigned DestReg) {
return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
406}

408/// This version of the builder builds a DBG_VALUE intrinsic
409/// for either a value in a register or a register-indirect
410/// address.  The convention is that a DBG_VALUE is indirect iff the
411/// second operand is an immediate.
412MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          unsigned Reg, const MDNode *Variable,
                          const MDNode *Expr);

417/// This version of the builder builds a DBG_VALUE intrinsic
418/// for either a value in a register or a register-indirect
419/// address and inserts it at position I.
420MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                          MachineBasicBlock::iterator I, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          unsigned Reg, const MDNode *Variable,
                          const MDNode *Expr);

426/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
427MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
                                  MachineBasicBlock::iterator I,
                                  const MachineInstr &Orig, int FrameIndex);

431/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
432/// modifying an instruction in place while iterating over a basic block.
433void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex);

435inline unsigned getDefRegState(bool B) {
return B ? RegState::Define : 0;
437}
438inline unsigned getImplRegState(bool B) {
return B ? RegState::Implicit : 0;
440}
441inline unsigned getKillRegState(bool B) {
return B ? RegState::Kill : 0;
443}
444inline unsigned getDeadRegState(bool B) {
return B ? RegState::Dead : 0;
446}
447inline unsigned getUndefRegState(bool B) {
return B ? RegState::Undef : 0;
449}
450inline unsigned getInternalReadRegState(bool B) {
return B ? RegState::InternalRead : 0;
452}
453inline unsigned getDebugRegState(bool B) {
return B ? RegState::Debug : 0;
455}
456inline unsigned getRenamableRegState(bool B) {
return B ? RegState::Renamable : 0;
458}

460/// Get all register state flags from machine operand \p RegOp.
461inline unsigned getRegState(const MachineOperand &RegOp) {
assert(RegOp.isReg() && "Not a register operand")(static_cast <bool> (RegOp.isReg() && "Not a register operand"
) ? void (0) : __assert_fail ("RegOp.isReg() && \"Not a register operand\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 462, __extension__ __PRETTY_FUNCTION__));
return getDefRegState(RegOp.isDef())                    |
       getImplRegState(RegOp.isImplicit())              |
       getKillRegState(RegOp.isKill())                  |
       getDeadRegState(RegOp.isDead())                  |
       getUndefRegState(RegOp.isUndef())                |
       getInternalReadRegState(RegOp.isInternalRead())  |
       getDebugRegState(RegOp.isDebug())                |
       getRenamableRegState(
           TargetRegisterInfo::isPhysicalRegister(RegOp.getReg()) &&
           RegOp.isRenamable());
473}

475/// Helper class for constructing bundles of MachineInstrs.
476///
477/// MIBundleBuilder can create a bundle from scratch by inserting new
478/// MachineInstrs one at a time, or it can create a bundle from a sequence of
479/// existing MachineInstrs in a basic block.
480class MIBundleBuilder {
MachineBasicBlock &MBB;
MachineBasicBlock::instr_iterator Begin;
MachineBasicBlock::instr_iterator End;

485public:
/// Create an MIBundleBuilder that inserts instructions into a new bundle in
/// BB above the bundle or instruction at Pos.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
    : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}

/// Create a bundle from the sequence of instructions between B and E.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
                MachineBasicBlock::iterator E)
    : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
  assert(B != E && "No instructions to bundle")(static_cast <bool> (B != E && "No instructions to bundle"
) ? void (0) : __assert_fail ("B != E && \"No instructions to bundle\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/MachineInstrBuilder.h"
, 495, __extension__ __PRETTY_FUNCTION__));
  ++B;
  while (B != E) {
    MachineInstr &MI = *B;
    ++B;
    MI.bundleWithPred();
  }
}

/// Create an MIBundleBuilder representing an existing instruction or bundle
/// that has MI as its head.
explicit MIBundleBuilder(MachineInstr *MI)
    : MBB(*MI->getParent()), Begin(MI),
      End(getBundleEnd(MI->getIterator())) {}

/// Return a reference to the basic block containing this bundle.
MachineBasicBlock &getMBB() const { return MBB; }

/// Return true if no instructions have been inserted in this bundle yet.
/// Empty bundles aren't representable in a MachineBasicBlock.
bool empty() const { return Begin == End; }

/// Return an iterator to the first bundled instruction.
MachineBasicBlock::instr_iterator begin() const { return Begin; }

/// Return an iterator beyond the last bundled instruction.
MachineBasicBlock::instr_iterator end() const { return End; }

/// Insert MI into this bundle before I which must point to an instruction in
/// the bundle, or end().
MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
                        MachineInstr *MI) {
  MBB.insert(I, MI);
  if (I == Begin) {
    if (!empty())
      MI->bundleWithSucc();
    Begin = MI->getIterator();
    return *this;
  }
  if (I == End) {
    MI->bundleWithPred();
    return *this;
  }
  // MI was inserted in the middle of the bundle, so its neighbors' flags are
  // already fine. Update MI's bundle flags manually.
  MI->setFlag(MachineInstr::BundledPred);
  MI->setFlag(MachineInstr::BundledSucc);
  return *this;
}

/// Insert MI into MBB by prepending it to the instructions in the bundle.
/// MI will become the first instruction in the bundle.
MIBundleBuilder &prepend(MachineInstr *MI) {
  return insert(begin(), MI);
}

/// Insert MI into MBB by appending it to the instructions in the bundle.
/// MI will become the last instruction in the bundle.
MIBundleBuilder &append(MachineInstr *MI) {
  return insert(end(), MI);
}
556};

558} // end namespace llvm

560#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H