/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Bug Summary

File:	llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:	line 1114, column 10 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AArch64ISelDAGToDAG.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AArch64 -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AArch64 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-04-14-063029-18377-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

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1//===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the AArch64 target.
10//
11//===----------------------------------------------------------------------===//

13#include "AArch64MachineFunctionInfo.h"
14#include "AArch64TargetMachine.h"
15#include "MCTargetDesc/AArch64AddressingModes.h"
16#include "llvm/ADT/APSInt.h"
17#include "llvm/CodeGen/SelectionDAGISel.h"
18#include "llvm/IR/Function.h" // To access function attributes.
19#include "llvm/IR/GlobalValue.h"
20#include "llvm/IR/Intrinsics.h"
21#include "llvm/IR/IntrinsicsAArch64.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/KnownBits.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/raw_ostream.h"

28using namespace llvm;

30#define DEBUG_TYPE"aarch64-isel" "aarch64-isel"

32//===--------------------------------------------------------------------===//
33/// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
34/// instructions for SelectionDAG operations.
35///
36namespace {

38class AArch64DAGToDAGISel : public SelectionDAGISel {

/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
/// make the right decision when generating code for different targets.
const AArch64Subtarget *Subtarget;

44public:
explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
                             CodeGenOpt::Level OptLevel)
    : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}

StringRef getPassName() const override {
  return "AArch64 Instruction Selection";
}

bool runOnMachineFunction(MachineFunction &MF) override {
  Subtarget = &MF.getSubtarget<AArch64Subtarget>();
  return SelectionDAGISel::runOnMachineFunction(MF);
}

void Select(SDNode *Node) override;

/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                  unsigned ConstraintID,
                                  std::vector<SDValue> &OutOps) override;

template <signed Low, signed High, signed Scale>
bool SelectRDVLImm(SDValue N, SDValue &Imm);

bool tryMLAV64LaneV128(SDNode *N);
bool tryMULLV64LaneV128(unsigned IntNo, SDNode *N);
bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
  return SelectShiftedRegister(N, false, Reg, Shift);
}
bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
  return SelectShiftedRegister(N, true, Reg, Shift);
}
bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed7S(N, 1, Base, OffImm);
}
bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed7S(N, 2, Base, OffImm);
}
bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed7S(N, 4, Base, OffImm);
}
bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed7S(N, 8, Base, OffImm);
}
bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed7S(N, 16, Base, OffImm);
}
bool SelectAddrModeIndexedS9S128(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexedBitWidth(N, true, 9, 16, Base, OffImm);
}
bool SelectAddrModeIndexedU6S128(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexedBitWidth(N, false, 6, 16, Base, OffImm);
}
bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed(N, 1, Base, OffImm);
}
bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed(N, 2, Base, OffImm);
}
bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed(N, 4, Base, OffImm);
}
bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed(N, 8, Base, OffImm);
}
bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeIndexed(N, 16, Base, OffImm);
}
bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeUnscaled(N, 1, Base, OffImm);
}
bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeUnscaled(N, 2, Base, OffImm);
}
bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeUnscaled(N, 4, Base, OffImm);
}
bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeUnscaled(N, 8, Base, OffImm);
}
bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
  return SelectAddrModeUnscaled(N, 16, Base, OffImm);
}

template<int Width>
bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
                       SDValue &SignExtend, SDValue &DoShift) {
  return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
}

template<int Width>
bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
                       SDValue &SignExtend, SDValue &DoShift) {
  return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
}

bool SelectDupZeroOrUndef(SDValue N) {
  switch(N->getOpcode()) {
  case ISD::UNDEF:
    return true;
  case AArch64ISD::DUP:
  case ISD::SPLAT_VECTOR: {
    auto Opnd0 = N->getOperand(0);
    if (auto CN = dyn_cast<ConstantSDNode>(Opnd0))
      if (CN->isNullValue())
        return true;
    if (auto CN = dyn_cast<ConstantFPSDNode>(Opnd0))
      if (CN->isZero())
        return true;
    break;
  }
  default:
    break;
  }

  return false;
}

bool SelectDupZero(SDValue N) {
  switch(N->getOpcode()) {
  case AArch64ISD::DUP:
  case ISD::SPLAT_VECTOR: {
    auto Opnd0 = N->getOperand(0);
    if (auto CN = dyn_cast<ConstantSDNode>(Opnd0))
      if (CN->isNullValue())
        return true;
    if (auto CN = dyn_cast<ConstantFPSDNode>(Opnd0))
      if (CN->isZero())
        return true;
    break;
  }
  }

  return false;
}

template<MVT::SimpleValueType VT>
bool SelectSVEAddSubImm(SDValue N, SDValue &Imm, SDValue &Shift) {
  return SelectSVEAddSubImm(N, VT, Imm, Shift);
}

template<MVT::SimpleValueType VT>
bool SelectSVELogicalImm(SDValue N, SDValue &Imm) {
  return SelectSVELogicalImm(N, VT, Imm);
}

template <MVT::SimpleValueType VT>
bool SelectSVEArithImm(SDValue N, SDValue &Imm) {
  return SelectSVEArithImm(N, VT, Imm);
}

template <unsigned Low, unsigned High, bool AllowSaturation = false>
bool SelectSVEShiftImm(SDValue N, SDValue &Imm) {
  return SelectSVEShiftImm(N, Low, High, AllowSaturation, Imm);
}

// Returns a suitable CNT/INC/DEC/RDVL multiplier to calculate VSCALE*N.
template<signed Min, signed Max, signed Scale, bool Shift>
bool SelectCntImm(SDValue N, SDValue &Imm) {
  if (!isa<ConstantSDNode>(N))
    return false;

  int64_t MulImm = cast<ConstantSDNode>(N)->getSExtValue();
  if (Shift)
    MulImm = 1LL << MulImm;

  if ((MulImm % std::abs(Scale)) != 0)
    return false;

  MulImm /= Scale;
  if ((MulImm >= Min) && (MulImm <= Max)) {
    Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32);
    return true;
  }

  return false;
}

/// Form sequences of consecutive 64/128-bit registers for use in NEON
/// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
/// between 1 and 4 elements. If it contains a single element that is returned
/// unchanged; otherwise a REG_SEQUENCE value is returned.
SDValue createDTuple(ArrayRef<SDValue> Vecs);
SDValue createQTuple(ArrayRef<SDValue> Vecs);
// Form a sequence of SVE registers for instructions using list of vectors,
// e.g. structured loads and stores (ldN, stN).
SDValue createZTuple(ArrayRef<SDValue> Vecs);

/// Generic helper for the createDTuple/createQTuple
/// functions. Those should almost always be called instead.
SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
                    const unsigned SubRegs[]);

void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);

bool tryIndexedLoad(SDNode *N);

bool trySelectStackSlotTagP(SDNode *N);
void SelectTagP(SDNode *N);

void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
                   unsigned SubRegIdx);
void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
                       unsigned SubRegIdx);
void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
                          unsigned Opc_rr, unsigned Opc_ri);

bool SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base, SDValue &OffImm);
/// SVE Reg+Imm addressing mode.
template <int64_t Min, int64_t Max>
bool SelectAddrModeIndexedSVE(SDNode *Root, SDValue N, SDValue &Base,
                              SDValue &OffImm);
/// SVE Reg+Reg address mode.
template <unsigned Scale>
bool SelectSVERegRegAddrMode(SDValue N, SDValue &Base, SDValue &Offset) {
  return SelectSVERegRegAddrMode(N, Scale, Base, Offset);
}

void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
                           unsigned Opc_rr, unsigned Opc_ri);
std::tuple<unsigned, SDValue, SDValue>
findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr, unsigned Opc_ri,
                         const SDValue &OldBase, const SDValue &OldOffset,
                         unsigned Scale);

bool tryBitfieldExtractOp(SDNode *N);
bool tryBitfieldExtractOpFromSExt(SDNode *N);
bool tryBitfieldInsertOp(SDNode *N);
bool tryBitfieldInsertInZeroOp(SDNode *N);
bool tryShiftAmountMod(SDNode *N);
bool tryHighFPExt(SDNode *N);

bool tryReadRegister(SDNode *N);
bool tryWriteRegister(SDNode *N);

289// Include the pieces autogenerated from the target description.
290#include "AArch64GenDAGISel.inc"

292private:
bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
                           SDValue &Shift);
bool SelectAddrModeIndexed7S(SDValue N, unsigned Size, SDValue &Base,
                             SDValue &OffImm) {
  return SelectAddrModeIndexedBitWidth(N, true, 7, Size, Base, OffImm);
}
bool SelectAddrModeIndexedBitWidth(SDValue N, bool IsSignedImm, unsigned BW,
                                   unsigned Size, SDValue &Base,
                                   SDValue &OffImm);
bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
                           SDValue &OffImm);
bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
                            SDValue &OffImm);
bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
                       SDValue &Offset, SDValue &SignExtend,
                       SDValue &DoShift);
bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
                       SDValue &Offset, SDValue &SignExtend,
                       SDValue &DoShift);
bool isWorthFolding(SDValue V) const;
bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
                       SDValue &Offset, SDValue &SignExtend);

template<unsigned RegWidth>
bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
  return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
}

bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);

bool SelectCMP_SWAP(SDNode *N);

bool SelectSVE8BitLslImm(SDValue N, SDValue &Imm, SDValue &Shift);

bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);

bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm);

bool SelectSVESignedArithImm(SDValue N, SDValue &Imm);
bool SelectSVEShiftImm(SDValue N, uint64_t Low, uint64_t High,
                       bool AllowSaturation, SDValue &Imm);

bool SelectSVEArithImm(SDValue N, MVT VT, SDValue &Imm);
bool SelectSVERegRegAddrMode(SDValue N, unsigned Scale, SDValue &Base,
                             SDValue &Offset);
338};
339} // end anonymous namespace

341/// isIntImmediate - This method tests to see if the node is a constant
342/// operand. If so Imm will receive the 32-bit value.
343static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
  Imm = C->getZExtValue();
  return true;
}
return false;
349}

351// isIntImmediate - This method tests to see if a constant operand.
352// If so Imm will receive the value.
353static bool isIntImmediate(SDValue N, uint64_t &Imm) {
return isIntImmediate(N.getNode(), Imm);
355}

357// isOpcWithIntImmediate - This method tests to see if the node is a specific
358// opcode and that it has a immediate integer right operand.
359// If so Imm will receive the 32 bit value.
360static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
                                uint64_t &Imm) {
return N->getOpcode() == Opc &&
       isIntImmediate(N->getOperand(1).getNode(), Imm);
364}

366bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
  const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
  llvm_unreachable("Unexpected asm memory constraint")::llvm::llvm_unreachable_internal("Unexpected asm memory constraint"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 370);
case InlineAsm::Constraint_m:
case InlineAsm::Constraint_Q:
  // We need to make sure that this one operand does not end up in XZR, thus
  // require the address to be in a PointerRegClass register.
  const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
  const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
  SDLoc dl(Op);
  SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
  SDValue NewOp =
      SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
                                     dl, Op.getValueType(),
                                     Op, RC), 0);
  OutOps.push_back(NewOp);
  return false;
}
return true;
387}

389/// SelectArithImmed - Select an immediate value that can be represented as
390/// a 12-bit value shifted left by either 0 or 12.  If so, return true with
391/// Val set to the 12-bit value and Shift set to the shifter operand.
392bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
                                         SDValue &Shift) {
// This function is called from the addsub_shifted_imm ComplexPattern,
// which lists [imm] as the list of opcode it's interested in, however
// we still need to check whether the operand is actually an immediate
// here because the ComplexPattern opcode list is only used in
// root-level opcode matching.
if (!isa<ConstantSDNode>(N.getNode()))
  return false;

uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
unsigned ShiftAmt;

if (Immed >> 12 == 0) {
  ShiftAmt = 0;
} else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
  ShiftAmt = 12;
  Immed = Immed >> 12;
} else
  return false;

unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
SDLoc dl(N);
Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
return true;
418}

420/// SelectNegArithImmed - As above, but negates the value before trying to
421/// select it.
422bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
                                            SDValue &Shift) {
// This function is called from the addsub_shifted_imm ComplexPattern,
// which lists [imm] as the list of opcode it's interested in, however
// we still need to check whether the operand is actually an immediate
// here because the ComplexPattern opcode list is only used in
// root-level opcode matching.
if (!isa<ConstantSDNode>(N.getNode()))
  return false;

// The immediate operand must be a 24-bit zero-extended immediate.
uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();

// This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
// have the opposite effect on the C flag, so this pattern mustn't match under
// those circumstances.
if (Immed == 0)
  return false;

if (N.getValueType() == MVT::i32)
  Immed = ~((uint32_t)Immed) + 1;
else
  Immed = ~Immed + 1ULL;
if (Immed & 0xFFFFFFFFFF000000ULL)
  return false;

Immed &= 0xFFFFFFULL;
return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
                        Shift);
451}

453/// getShiftTypeForNode - Translate a shift node to the corresponding
454/// ShiftType value.
455static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
switch (N.getOpcode()) {
default:
  return AArch64_AM::InvalidShiftExtend;
case ISD::SHL:
  return AArch64_AM::LSL;
case ISD::SRL:
  return AArch64_AM::LSR;
case ISD::SRA:
  return AArch64_AM::ASR;
case ISD::ROTR:
  return AArch64_AM::ROR;
}
468}

470/// Determine whether it is worth it to fold SHL into the addressing
471/// mode.
472static bool isWorthFoldingSHL(SDValue V) {
assert(V.getOpcode() == ISD::SHL && "invalid opcode")((V.getOpcode() == ISD::SHL && "invalid opcode") ? static_cast
<void> (0) : __assert_fail ("V.getOpcode() == ISD::SHL && \"invalid opcode\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 473, __PRETTY_FUNCTION__));
// It is worth folding logical shift of up to three places.
auto *CSD = dyn_cast<ConstantSDNode>(V.getOperand(1));
if (!CSD)
  return false;
unsigned ShiftVal = CSD->getZExtValue();
if (ShiftVal > 3)
  return false;

// Check if this particular node is reused in any non-memory related
// operation.  If yes, do not try to fold this node into the address
// computation, since the computation will be kept.
const SDNode *Node = V.getNode();
for (SDNode *UI : Node->uses())
  if (!isa<MemSDNode>(*UI))
    for (SDNode *UII : UI->uses())
      if (!isa<MemSDNode>(*UII))
        return false;
return true;
492}

494/// Determine whether it is worth to fold V into an extended register.
495bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
// Trivial if we are optimizing for code size or if there is only
// one use of the value.
if (CurDAG->shouldOptForSize() || V.hasOneUse())
  return true;
// If a subtarget has a fastpath LSL we can fold a logical shift into
// the addressing mode and save a cycle.
if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
    isWorthFoldingSHL(V))
  return true;
if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
  const SDValue LHS = V.getOperand(0);
  const SDValue RHS = V.getOperand(1);
  if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
    return true;
  if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
    return true;
}

// It hurts otherwise, since the value will be reused.
return false;
516}

518/// SelectShiftedRegister - Select a "shifted register" operand.  If the value
519/// is not shifted, set the Shift operand to default of "LSL 0".  The logical
520/// instructions allow the shifted register to be rotated, but the arithmetic
521/// instructions do not.  The AllowROR parameter specifies whether ROR is
522/// supported.
523bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
                                              SDValue &Reg, SDValue &Shift) {
AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
if (ShType == AArch64_AM::InvalidShiftExtend)
  return false;
if (!AllowROR && ShType == AArch64_AM::ROR)
  return false;

if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
  unsigned BitSize = N.getValueSizeInBits();
  unsigned Val = RHS->getZExtValue() & (BitSize - 1);
  unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);

  Reg = N.getOperand(0);
  Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
  return isWorthFolding(N);
}

return false;
542}

544/// getExtendTypeForNode - Translate an extend node to the corresponding
545/// ExtendType value.
546static AArch64_AM::ShiftExtendType
547getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
if (N.getOpcode() == ISD::SIGN_EXTEND ||
    N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
  EVT SrcVT;
  if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
    SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
  else
    SrcVT = N.getOperand(0).getValueType();

  if (!IsLoadStore && SrcVT == MVT::i8)
    return AArch64_AM::SXTB;
  else if (!IsLoadStore && SrcVT == MVT::i16)
    return AArch64_AM::SXTH;
  else if (SrcVT == MVT::i32)
    return AArch64_AM::SXTW;
  assert(SrcVT != MVT::i64 && "extend from 64-bits?")((SrcVT != MVT::i64 && "extend from 64-bits?") ? static_cast
<void> (0) : __assert_fail ("SrcVT != MVT::i64 && \"extend from 64-bits?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 562, __PRETTY_FUNCTION__));

  return AArch64_AM::InvalidShiftExtend;
} else if (N.getOpcode() == ISD::ZERO_EXTEND ||
           N.getOpcode() == ISD::ANY_EXTEND) {
  EVT SrcVT = N.getOperand(0).getValueType();
  if (!IsLoadStore && SrcVT == MVT::i8)
    return AArch64_AM::UXTB;
  else if (!IsLoadStore && SrcVT == MVT::i16)
    return AArch64_AM::UXTH;
  else if (SrcVT == MVT::i32)
    return AArch64_AM::UXTW;
  assert(SrcVT != MVT::i64 && "extend from 64-bits?")((SrcVT != MVT::i64 && "extend from 64-bits?") ? static_cast
<void> (0) : __assert_fail ("SrcVT != MVT::i64 && \"extend from 64-bits?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 574, __PRETTY_FUNCTION__));

  return AArch64_AM::InvalidShiftExtend;
} else if (N.getOpcode() == ISD::AND) {
  ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
  if (!CSD)
    return AArch64_AM::InvalidShiftExtend;
  uint64_t AndMask = CSD->getZExtValue();

  switch (AndMask) {
  default:
    return AArch64_AM::InvalidShiftExtend;
  case 0xFF:
    return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend;
  case 0xFFFF:
    return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
  case 0xFFFFFFFF:
    return AArch64_AM::UXTW;
  }
}

return AArch64_AM::InvalidShiftExtend;
596}

598// Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
599static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
    DL->getOpcode() != AArch64ISD::DUPLANE32)
  return false;

SDValue SV = DL->getOperand(0);
if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
  return false;

SDValue EV = SV.getOperand(1);
if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
  return false;

ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
LaneOp = EV.getOperand(0);

return true;
618}

620// Helper for SelectOpcV64LaneV128 - Recognize operations where one operand is a
621// high lane extract.
622static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
                           SDValue &LaneOp, int &LaneIdx) {

if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
  std::swap(Op0, Op1);
  if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
    return false;
}
StdOp = Op1;
return true;
632}

634/// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
635/// is a lane in the upper half of a 128-bit vector.  Recognize and select this
636/// so that we don't emit unnecessary lane extracts.
637bool AArch64DAGToDAGISel::tryMLAV64LaneV128(SDNode *N) {
SDLoc dl(N);
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
SDValue MLAOp1;   // Will hold ordinary multiplicand for MLA.
SDValue MLAOp2;   // Will hold lane-accessed multiplicand for MLA.
int LaneIdx = -1; // Will hold the lane index.

if (Op1.getOpcode() != ISD::MUL ||
    !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
                      LaneIdx)) {
  std::swap(Op0, Op1);
  if (Op1.getOpcode() != ISD::MUL ||
      !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
                        LaneIdx))
    return false;
}

SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);

SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };

unsigned MLAOpc = ~0U;

switch (N->getSimpleValueType(0).SimpleTy) {
default:
  llvm_unreachable("Unrecognized MLA.")::llvm::llvm_unreachable_internal("Unrecognized MLA.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 663);
case MVT::v4i16:
  MLAOpc = AArch64::MLAv4i16_indexed;
  break;
case MVT::v8i16:
  MLAOpc = AArch64::MLAv8i16_indexed;
  break;
case MVT::v2i32:
  MLAOpc = AArch64::MLAv2i32_indexed;
  break;
case MVT::v4i32:
  MLAOpc = AArch64::MLAv4i32_indexed;
  break;
}

ReplaceNode(N, CurDAG->getMachineNode(MLAOpc, dl, N->getValueType(0), Ops));
return true;
680}

682bool AArch64DAGToDAGISel::tryMULLV64LaneV128(unsigned IntNo, SDNode *N) {
SDLoc dl(N);
SDValue SMULLOp0;
SDValue SMULLOp1;
int LaneIdx;

if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
                      LaneIdx))
  return false;

SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);

SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };

unsigned SMULLOpc = ~0U;

if (IntNo == Intrinsic::aarch64_neon_smull) {
  switch (N->getSimpleValueType(0).SimpleTy) {
  default:
    llvm_unreachable("Unrecognized SMULL.")::llvm::llvm_unreachable_internal("Unrecognized SMULL.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 701);
  case MVT::v4i32:
    SMULLOpc = AArch64::SMULLv4i16_indexed;
    break;
  case MVT::v2i64:
    SMULLOpc = AArch64::SMULLv2i32_indexed;
    break;
  }
} else if (IntNo == Intrinsic::aarch64_neon_umull) {
  switch (N->getSimpleValueType(0).SimpleTy) {
  default:
    llvm_unreachable("Unrecognized SMULL.")::llvm::llvm_unreachable_internal("Unrecognized SMULL.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 712);
  case MVT::v4i32:
    SMULLOpc = AArch64::UMULLv4i16_indexed;
    break;
  case MVT::v2i64:
    SMULLOpc = AArch64::UMULLv2i32_indexed;
    break;
  }
} else
  llvm_unreachable("Unrecognized intrinsic.")::llvm::llvm_unreachable_internal("Unrecognized intrinsic.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 721);

ReplaceNode(N, CurDAG->getMachineNode(SMULLOpc, dl, N->getValueType(0), Ops));
return true;
725}

727/// Instructions that accept extend modifiers like UXTW expect the register
728/// being extended to be a GPR32, but the incoming DAG might be acting on a
729/// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
730/// this is the case.
731static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
if (N.getValueType() == MVT::i32)
  return N;

SDLoc dl(N);
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                             dl, MVT::i32, N, SubReg);
return SDValue(Node, 0);
740}

742// Returns a suitable CNT/INC/DEC/RDVL multiplier to calculate VSCALE*N.
743template<signed Low, signed High, signed Scale>
744bool AArch64DAGToDAGISel::SelectRDVLImm(SDValue N, SDValue &Imm) {
if (!isa<ConstantSDNode>(N))
  return false;

int64_t MulImm = cast<ConstantSDNode>(N)->getSExtValue();
if ((MulImm % std::abs(Scale)) == 0) {
  int64_t RDVLImm = MulImm / Scale;
  if ((RDVLImm >= Low) && (RDVLImm <= High)) {
    Imm = CurDAG->getTargetConstant(RDVLImm, SDLoc(N), MVT::i32);
    return true;
  }
}

return false;
758}

760/// SelectArithExtendedRegister - Select a "extended register" operand.  This
761/// operand folds in an extend followed by an optional left shift.
762bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
                                                    SDValue &Shift) {
unsigned ShiftVal = 0;
AArch64_AM::ShiftExtendType Ext;

if (N.getOpcode() == ISD::SHL) {
  ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
  if (!CSD)
    return false;
  ShiftVal = CSD->getZExtValue();
  if (ShiftVal > 4)
    return false;

  Ext = getExtendTypeForNode(N.getOperand(0));
  if (Ext == AArch64_AM::InvalidShiftExtend)
    return false;

  Reg = N.getOperand(0).getOperand(0);
} else {
  Ext = getExtendTypeForNode(N);
  if (Ext == AArch64_AM::InvalidShiftExtend)
    return false;

  Reg = N.getOperand(0);

  // Don't match if free 32-bit -> 64-bit zext can be used instead.
  if (Ext == AArch64_AM::UXTW &&
      Reg->getValueType(0).getSizeInBits() == 32 && isDef32(*Reg.getNode()))
    return false;
}

// AArch64 mandates that the RHS of the operation must use the smallest
// register class that could contain the size being extended from.  Thus,
// if we're folding a (sext i8), we need the RHS to be a GPR32, even though
// there might not be an actual 32-bit value in the program.  We can
// (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX)((Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX)
 ? static_cast<void> (0) : __assert_fail ("Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 798, __PRETTY_FUNCTION__));
Reg = narrowIfNeeded(CurDAG, Reg);
Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N),
                                  MVT::i32);
return isWorthFolding(N);
803}

805/// If there's a use of this ADDlow that's not itself a load/store then we'll
806/// need to create a real ADD instruction from it anyway and there's no point in
807/// folding it into the mem op. Theoretically, it shouldn't matter, but there's
808/// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
809/// leads to duplicated ADRP instructions.
810static bool isWorthFoldingADDlow(SDValue N) {
for (auto Use : N->uses()) {
  if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
      Use->getOpcode() != ISD::ATOMIC_LOAD &&
      Use->getOpcode() != ISD::ATOMIC_STORE)
    return false;

  // ldar and stlr have much more restrictive addressing modes (just a
  // register).
  if (isStrongerThanMonotonic(cast<MemSDNode>(Use)->getOrdering()))
    return false;
}

return true;
824}

826/// SelectAddrModeIndexedBitWidth - Select a "register plus scaled (un)signed BW-bit
827/// immediate" address.  The "Size" argument is the size in bytes of the memory
828/// reference, which determines the scale.
829bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSignedImm,
                                                      unsigned BW, unsigned Size,
                                                      SDValue &Base,
                                                      SDValue &OffImm) {
SDLoc dl(N);
const DataLayout &DL = CurDAG->getDataLayout();
const TargetLowering *TLI = getTargetLowering();
if (N.getOpcode() == ISD::FrameIndex) {
  int FI = cast<FrameIndexSDNode>(N)->getIndex();
  Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
  OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
  return true;
}

// As opposed to the (12-bit) Indexed addressing mode below, the 7/9-bit signed
// selected here doesn't support labels/immediates, only base+offset.
if (CurDAG->isBaseWithConstantOffset(N)) {
  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
    if (IsSignedImm) {
      int64_t RHSC = RHS->getSExtValue();
      unsigned Scale = Log2_32(Size);
      int64_t Range = 0x1LL << (BW - 1);

      if ((RHSC & (Size - 1)) == 0 && RHSC >= -(Range << Scale) &&
          RHSC < (Range << Scale)) {
        Base = N.getOperand(0);
        if (Base.getOpcode() == ISD::FrameIndex) {
          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
          Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
        }
        OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
        return true;
      }
    } else {
      // unsigned Immediate
      uint64_t RHSC = RHS->getZExtValue();
      unsigned Scale = Log2_32(Size);
      uint64_t Range = 0x1ULL << BW;

      if ((RHSC & (Size - 1)) == 0 && RHSC < (Range << Scale)) {
        Base = N.getOperand(0);
        if (Base.getOpcode() == ISD::FrameIndex) {
          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
          Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
        }
        OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
        return true;
      }
    }
  }
}
// Base only. The address will be materialized into a register before
// the memory is accessed.
//    add x0, Xbase, #offset
//    stp x1, x2, [x0]
Base = N;
OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
return true;
887}

889/// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
890/// immediate" address.  The "Size" argument is the size in bytes of the memory
891/// reference, which determines the scale.
892bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
                                            SDValue &Base, SDValue &OffImm) {
SDLoc dl(N);
const DataLayout &DL = CurDAG->getDataLayout();
const TargetLowering *TLI = getTargetLowering();
if (N.getOpcode() == ISD::FrameIndex) {
  int FI = cast<FrameIndexSDNode>(N)->getIndex();
  Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
  OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
  return true;
}

if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) {
  GlobalAddressSDNode *GAN =
      dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
  Base = N.getOperand(0);
  OffImm = N.getOperand(1);
  if (!GAN)
    return true;

  if (GAN->getOffset() % Size == 0 &&
      GAN->getGlobal()->getPointerAlignment(DL) >= Size)
    return true;
}

if (CurDAG->isBaseWithConstantOffset(N)) {
  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
    int64_t RHSC = (int64_t)RHS->getZExtValue();
    unsigned Scale = Log2_32(Size);
    if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
      Base = N.getOperand(0);
      if (Base.getOpcode() == ISD::FrameIndex) {
        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
        Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
      }
      OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
      return true;
    }
  }
}

// Before falling back to our general case, check if the unscaled
// instructions can handle this. If so, that's preferable.
if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
  return false;

// Base only. The address will be materialized into a register before
// the memory is accessed.
//    add x0, Xbase, #offset
//    ldr x0, [x0]
Base = N;
OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
return true;
945}

947/// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
948/// immediate" address.  This should only match when there is an offset that
949/// is not valid for a scaled immediate addressing mode.  The "Size" argument
950/// is the size in bytes of the memory reference, which is needed here to know
951/// what is valid for a scaled immediate.
952bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
                                               SDValue &Base,
                                               SDValue &OffImm) {
if (!CurDAG->isBaseWithConstantOffset(N))
  return false;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
  int64_t RHSC = RHS->getSExtValue();
  // If the offset is valid as a scaled immediate, don't match here.
  if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
      RHSC < (0x1000 << Log2_32(Size)))
    return false;
  if (RHSC >= -256 && RHSC < 256) {
    Base = N.getOperand(0);
    if (Base.getOpcode() == ISD::FrameIndex) {
      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
      const TargetLowering *TLI = getTargetLowering();
      Base = CurDAG->getTargetFrameIndex(
          FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    }
    OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i64);
    return true;
  }
}
return false;
976}

978static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
SDLoc dl(N);
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
SDValue ImpDef = SDValue(
    CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
MachineSDNode *Node = CurDAG->getMachineNode(
    TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
return SDValue(Node, 0);
986}

988/// Check if the given SHL node (\p N), can be used to form an
989/// extended register for an addressing mode.
990bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
                                          bool WantExtend, SDValue &Offset,
                                          SDValue &SignExtend) {
assert(N.getOpcode() == ISD::SHL && "Invalid opcode.")((N.getOpcode() == ISD::SHL && "Invalid opcode.") ? static_cast
<void> (0) : __assert_fail ("N.getOpcode() == ISD::SHL && \"Invalid opcode.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 993, __PRETTY_FUNCTION__));
ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
  return false;

SDLoc dl(N);
if (WantExtend) {
  AArch64_AM::ShiftExtendType Ext =
      getExtendTypeForNode(N.getOperand(0), true);
  if (Ext == AArch64_AM::InvalidShiftExtend)
    return false;

  Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
  SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
                                         MVT::i32);
} else {
  Offset = N.getOperand(0);
  SignExtend = CurDAG->getTargetConstant(0, dl, MVT::i32);
}

unsigned LegalShiftVal = Log2_32(Size);
unsigned ShiftVal = CSD->getZExtValue();

if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
  return false;

return isWorthFolding(N);
1020}

1022bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
                                          SDValue &Base, SDValue &Offset,
                                          SDValue &SignExtend,
                                          SDValue &DoShift) {
if (N.getOpcode() != ISD::ADD)
  return false;
SDValue LHS = N.getOperand(0);
SDValue RHS = N.getOperand(1);
SDLoc dl(N);

// We don't want to match immediate adds here, because they are better lowered
// to the register-immediate addressing modes.
if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
  return false;

// Check if this particular node is reused in any non-memory related
// operation.  If yes, do not try to fold this node into the address
// computation, since the computation will be kept.
const SDNode *Node = N.getNode();
for (SDNode *UI : Node->uses()) {
  if (!isa<MemSDNode>(*UI))
    return false;
}

// Remember if it is worth folding N when it produces extended register.
bool IsExtendedRegisterWorthFolding = isWorthFolding(N);

// Try to match a shifted extend on the RHS.
if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
    SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
  Base = LHS;
  DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
  return true;
}

// Try to match a shifted extend on the LHS.
if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
    SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
  Base = RHS;
  DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
  return true;
}

// There was no shift, whatever else we find.
DoShift = CurDAG->getTargetConstant(false, dl, MVT::i32);

AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
// Try to match an unshifted extend on the LHS.
if (IsExtendedRegisterWorthFolding &&
    (Ext = getExtendTypeForNode(LHS, true)) !=
        AArch64_AM::InvalidShiftExtend) {
  Base = RHS;
  Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
  SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
                                         MVT::i32);
  if (isWorthFolding(LHS))
    return true;
}

// Try to match an unshifted extend on the RHS.
if (IsExtendedRegisterWorthFolding &&
    (Ext = getExtendTypeForNode(RHS, true)) !=
        AArch64_AM::InvalidShiftExtend) {
  Base = LHS;
  Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
  SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
                                         MVT::i32);
  if (isWorthFolding(RHS))
    return true;
}

return false;
1094}

1096// Check if the given immediate is preferred by ADD. If an immediate can be
1097// encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
1098// encoded by one MOVZ, return true.
1099static bool isPreferredADD(int64_t ImmOff) {
// Constant in [0x0, 0xfff] can be encoded in ADD.
if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
  return true;
// Check if it can be encoded in an "ADD LSL #12".
if ((ImmOff & 0xffffffffff000fffLL) == 0x0LL)
  // As a single MOVZ is faster than a "ADD of LSL #12", ignore such constant.
  return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
         (ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
return false;
1109}

1111bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
                                          SDValue &Base, SDValue &Offset,
                                          SDValue &SignExtend,
                                          SDValue &DoShift) {
if (N.getOpcode() != ISD::ADD)
  return false;
SDValue LHS = N.getOperand(0);
SDValue RHS = N.getOperand(1);
SDLoc DL(N);

// Check if this particular node is reused in any non-memory related
// operation.  If yes, do not try to fold this node into the address
// computation, since the computation will be kept.
const SDNode *Node = N.getNode();
for (SDNode *UI : Node->uses()) {
  if (!isa<MemSDNode>(*UI))
    return false;
}

// Watch out if RHS is a wide immediate, it can not be selected into
// [BaseReg+Imm] addressing mode. Also it may not be able to be encoded into
// ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
// instructions like:
//     MOV  X0, WideImmediate
//     ADD  X1, BaseReg, X0
//     LDR  X2, [X1, 0]
// For such situation, using [BaseReg, XReg] addressing mode can save one
// ADD/SUB:
//     MOV  X0, WideImmediate
//     LDR  X2, [BaseReg, X0]
if (isa<ConstantSDNode>(RHS)) {
  int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
  unsigned Scale = Log2_32(Size);
  // Skip the immediate can be selected by load/store addressing mode.
  // Also skip the immediate can be encoded by a single ADD (SUB is also
  // checked by using -ImmOff).
  if ((ImmOff % Size == 0 && ImmOff >= 0 && ImmOff < (0x1000 << Scale)) ||
      isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
    return false;

  SDValue Ops[] = { RHS };
  SDNode *MOVI =
      CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
  SDValue MOVIV = SDValue(MOVI, 0);
  // This ADD of two X register will be selected into [Reg+Reg] mode.
  N = CurDAG->getNode(ISD::ADD, DL, MVT::i64, LHS, MOVIV);
}

// Remember if it is worth folding N when it produces extended register.
bool IsExtendedRegisterWorthFolding = isWorthFolding(N);

// Try to match a shifted extend on the RHS.
if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
    SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
  Base = LHS;
  DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
  return true;
}

// Try to match a shifted extend on the LHS.
if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
    SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
  Base = RHS;
  DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
  return true;
}

// Match any non-shifted, non-extend, non-immediate add expression.
Base = LHS;
Offset = RHS;
SignExtend = CurDAG->getTargetConstant(false, DL, MVT::i32);
DoShift = CurDAG->getTargetConstant(false, DL, MVT::i32);
// Reg1 + Reg2 is free: no check needed.
return true;
1185}

1187SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
static const unsigned RegClassIDs[] = {
    AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
                                   AArch64::dsub2, AArch64::dsub3};

return createTuple(Regs, RegClassIDs, SubRegs);
1194}

1196SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
static const unsigned RegClassIDs[] = {
    AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
                                   AArch64::qsub2, AArch64::qsub3};

return createTuple(Regs, RegClassIDs, SubRegs);
1203}

1205SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) {
static const unsigned RegClassIDs[] = {AArch64::ZPR2RegClassID,
                                       AArch64::ZPR3RegClassID,
                                       AArch64::ZPR4RegClassID};
static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1,
                                   AArch64::zsub2, AArch64::zsub3};

return createTuple(Regs, RegClassIDs, SubRegs);
1213}

1215SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
                                       const unsigned RegClassIDs[],
                                       const unsigned SubRegs[]) {
// There's no special register-class for a vector-list of 1 element: it's just
// a vector.
if (Regs.size() == 1)
  return Regs[0];

assert(Regs.size() >= 2 && Regs.size() <= 4)((Regs.size() >= 2 && Regs.size() <= 4) ? static_cast
<void> (0) : __assert_fail ("Regs.size() >= 2 && Regs.size() <= 4"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1223, __PRETTY_FUNCTION__));

SDLoc DL(Regs[0]);

SmallVector<SDValue, 4> Ops;

// First operand of REG_SEQUENCE is the desired RegClass.
Ops.push_back(
    CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32));

// Then we get pairs of source & subregister-position for the components.
for (unsigned i = 0; i < Regs.size(); ++i) {
  Ops.push_back(Regs[i]);
  Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32));
}

SDNode *N =
    CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
return SDValue(N, 0);
1242}

1244void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
                                    bool isExt) {
SDLoc dl(N);
EVT VT = N->getValueType(0);

unsigned ExtOff = isExt;

// Form a REG_SEQUENCE to force register allocation.
unsigned Vec0Off = ExtOff + 1;
SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
                             N->op_begin() + Vec0Off + NumVecs);
SDValue RegSeq = createQTuple(Regs);

SmallVector<SDValue, 6> Ops;
if (isExt)
  Ops.push_back(N->getOperand(1));
Ops.push_back(RegSeq);
Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
1263}

1265bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (LD->isUnindexed())
  return false;
EVT VT = LD->getMemoryVT();
EVT DstVT = N->getValueType(0);
ISD::MemIndexedMode AM = LD->getAddressingMode();
bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;

// We're not doing validity checking here. That was done when checking
// if we should mark the load as indexed or not. We're just selecting
// the right instruction.
unsigned Opcode = 0;

ISD::LoadExtType ExtType = LD->getExtensionType();
bool InsertTo64 = false;
if (VT == MVT::i64)
  Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
else if (VT == MVT::i32) {
  if (ExtType == ISD::NON_EXTLOAD)
    Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
  else if (ExtType == ISD::SEXTLOAD)
    Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
  else {
    Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
    InsertTo64 = true;
    // The result of the load is only i32. It's the subreg_to_reg that makes
    // it into an i64.
    DstVT = MVT::i32;
  }
} else if (VT == MVT::i16) {
  if (ExtType == ISD::SEXTLOAD) {
    if (DstVT == MVT::i64)
      Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
    else
      Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
  } else {
    Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
    InsertTo64 = DstVT == MVT::i64;
    // The result of the load is only i32. It's the subreg_to_reg that makes
    // it into an i64.
    DstVT = MVT::i32;
  }
} else if (VT == MVT::i8) {
  if (ExtType == ISD::SEXTLOAD) {
    if (DstVT == MVT::i64)
      Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
    else
      Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost;
  } else {
    Opcode = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost;
    InsertTo64 = DstVT == MVT::i64;
    // The result of the load is only i32. It's the subreg_to_reg that makes
    // it into an i64.
    DstVT = MVT::i32;
  }
} else if (VT == MVT::f16) {
  Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
} else if (VT == MVT::bf16) {
  Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
} else if (VT == MVT::f32) {
  Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
} else if (VT == MVT::f64 || VT.is64BitVector()) {
  Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost;
} else if (VT.is128BitVector()) {
  Opcode = IsPre ? AArch64::LDRQpre : AArch64::LDRQpost;
} else
  return false;
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
int OffsetVal = (int)OffsetOp->getZExtValue();
SDLoc dl(N);
SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
SDValue Ops[] = { Base, Offset, Chain };
SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
                                     MVT::Other, Ops);

// Transfer memoperands.
MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(Res), {MemOp});

// Either way, we're replacing the node, so tell the caller that.
SDValue LoadedVal = SDValue(Res, 1);
if (InsertTo64) {
  SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
  LoadedVal =
      SDValue(CurDAG->getMachineNode(
                  AArch64::SUBREG_TO_REG, dl, MVT::i64,
                  CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,
                  SubReg),
              0);
}

ReplaceUses(SDValue(N, 0), LoadedVal);
ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
CurDAG->RemoveDeadNode(N);
return true;
1364}

1366void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
                                   unsigned SubRegIdx) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);

SDValue Ops[] = {N->getOperand(2), // Mem operand;
                 Chain};

const EVT ResTys[] = {MVT::Untyped, MVT::Other};

SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
SDValue SuperReg = SDValue(Ld, 0);
for (unsigned i = 0; i < NumVecs; ++i)
  ReplaceUses(SDValue(N, i),
      CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));

ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));

// Transfer memoperands. In the case of AArch64::LD64B, there won't be one,
// because it's too simple to have needed special treatment during lowering.
if (auto *MemIntr = dyn_cast<MemIntrinsicSDNode>(N)) {
  MachineMemOperand *MemOp = MemIntr->getMemOperand();
  CurDAG->setNodeMemRefs(cast<MachineSDNode>(Ld), {MemOp});
}

CurDAG->RemoveDeadNode(N);
1393}

1395void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
                                       unsigned Opc, unsigned SubRegIdx) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);

SDValue Ops[] = {N->getOperand(1), // Mem operand
                 N->getOperand(2), // Incremental
                 Chain};

const EVT ResTys[] = {MVT::i64, // Type of the write back register
                      MVT::Untyped, MVT::Other};

SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);

// Update uses of write back register
ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));

// Update uses of vector list
SDValue SuperReg = SDValue(Ld, 1);
if (NumVecs == 1)
  ReplaceUses(SDValue(N, 0), SuperReg);
else
  for (unsigned i = 0; i < NumVecs; ++i)
    ReplaceUses(SDValue(N, i),
        CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));

// Update the chain
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
CurDAG->RemoveDeadNode(N);
1425}

1427/// Optimize \param OldBase and \param OldOffset selecting the best addressing
1428/// mode. Returns a tuple consisting of an Opcode, an SDValue representing the
1429/// new Base and an SDValue representing the new offset.
1430std::tuple<unsigned, SDValue, SDValue>
1431AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr,
                                            unsigned Opc_ri,
                                            const SDValue &OldBase,
                                            const SDValue &OldOffset,
                                            unsigned Scale) {
SDValue NewBase = OldBase;
SDValue NewOffset = OldOffset;
// Detect a possible Reg+Imm addressing mode.
const bool IsRegImm = SelectAddrModeIndexedSVE</*Min=*/-8, /*Max=*/7>(
    N, OldBase, NewBase, NewOffset);

// Detect a possible reg+reg addressing mode, but only if we haven't already
// detected a Reg+Imm one.
const bool IsRegReg =
    !IsRegImm && SelectSVERegRegAddrMode(OldBase, Scale, NewBase, NewOffset);

// Select the instruction.
return std::make_tuple(IsRegReg ? Opc_rr : Opc_ri, NewBase, NewOffset);
1449}

1451void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs,
                                             unsigned Scale, unsigned Opc_ri,
                                             unsigned Opc_rr) {
assert(Scale < 4 && "Invalid scaling value.")((Scale < 4 && "Invalid scaling value.") ? static_cast
<void> (0) : __assert_fail ("Scale < 4 && \"Invalid scaling value.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1454, __PRETTY_FUNCTION__));
SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);

// Optimize addressing mode.
SDValue Base, Offset;
unsigned Opc;
std::tie(Opc, Base, Offset) = findAddrModeSVELoadStore(
    N, Opc_rr, Opc_ri, N->getOperand(2),
    CurDAG->getTargetConstant(0, DL, MVT::i64), Scale);

SDValue Ops[] = {N->getOperand(1), // Predicate
                 Base,             // Memory operand
                 Offset, Chain};

const EVT ResTys[] = {MVT::Untyped, MVT::Other};

SDNode *Load = CurDAG->getMachineNode(Opc, DL, ResTys, Ops);
SDValue SuperReg = SDValue(Load, 0);
for (unsigned i = 0; i < NumVecs; ++i)
  ReplaceUses(SDValue(N, i), CurDAG->getTargetExtractSubreg(
                                 AArch64::zsub0 + i, DL, VT, SuperReg));

// Copy chain
unsigned ChainIdx = NumVecs;
ReplaceUses(SDValue(N, ChainIdx), SDValue(Load, 1));
CurDAG->RemoveDeadNode(N);
1482}

1484void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
                                    unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getOperand(2)->getValueType(0);

// Form a REG_SEQUENCE to force register allocation.
bool Is128Bit = VT.getSizeInBits() == 128;
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);

SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);

// Transfer memoperands.
MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});

ReplaceNode(N, St);
1502}

1504void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
                                              unsigned Scale, unsigned Opc_rr,
                                              unsigned Opc_ri) {
SDLoc dl(N);

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SDValue RegSeq = createZTuple(Regs);

// Optimize addressing mode.
unsigned Opc;
SDValue Offset, Base;
std::tie(Opc, Base, Offset) = findAddrModeSVELoadStore(
    N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),
    CurDAG->getTargetConstant(0, dl, MVT::i64), Scale);

SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
                 Base,                               // address
                 Offset,                             // offset
                 N->getOperand(0)};                  // chain
SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);

ReplaceNode(N, St);
1527}

1529bool AArch64DAGToDAGISel::SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base,
                                                    SDValue &OffImm) {
SDLoc dl(N);
const DataLayout &DL = CurDAG->getDataLayout();
const TargetLowering *TLI = getTargetLowering();

// Try to match it for the frame address
if (auto FINode = dyn_cast<FrameIndexSDNode>(N)) {
  int FI = FINode->getIndex();
  Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
  OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
  return true;
}

return false;
1544}

1546void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
                                        unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getOperand(2)->getValueType(0);
const EVT ResTys[] = {MVT::i64,    // Type of the write back register
                      MVT::Other}; // Type for the Chain

// Form a REG_SEQUENCE to force register allocation.
bool Is128Bit = VT.getSizeInBits() == 128;
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);

SDValue Ops[] = {RegSeq,
                 N->getOperand(NumVecs + 1), // base register
                 N->getOperand(NumVecs + 2), // Incremental
                 N->getOperand(0)};          // Chain
SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);

ReplaceNode(N, St);
1565}

1567namespace {
1568/// WidenVector - Given a value in the V64 register class, produce the
1569/// equivalent value in the V128 register class.
1570class WidenVector {
SelectionDAG &DAG;

1573public:
WidenVector(SelectionDAG &DAG) : DAG(DAG) {}

SDValue operator()(SDValue V64Reg) {
  EVT VT = V64Reg.getValueType();
  unsigned NarrowSize = VT.getVectorNumElements();
  MVT EltTy = VT.getVectorElementType().getSimpleVT();
  MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
  SDLoc DL(V64Reg);

  SDValue Undef =
      SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
  return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
}
1587};
1588} // namespace

1590/// NarrowVector - Given a value in the V128 register class, produce the
1591/// equivalent value in the V64 register class.
1592static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
EVT VT = V128Reg.getValueType();
8
←
Calling 'SDValue::getValueType'→
unsigned WideSize = VT.getVectorNumElements();
MVT EltTy = VT.getVectorElementType().getSimpleVT();
MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);

return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
                                  V128Reg);
1600}

1602void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
                                       unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);

if (Narrow)
  transform(Regs, Regs.begin(),
                 WidenVector(*CurDAG));

SDValue RegSeq = createQTuple(Regs);

const EVT ResTys[] = {MVT::Untyped, MVT::Other};

unsigned LaneNo =
    cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();

SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                 N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
SDValue SuperReg = SDValue(Ld, 0);

EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
                                  AArch64::qsub2, AArch64::qsub3 };
for (unsigned i = 0; i < NumVecs; ++i) {
  SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
  if (Narrow)
    NV = NarrowVector(NV, *CurDAG);
  ReplaceUses(SDValue(N, i), NV);
}

ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
CurDAG->RemoveDeadNode(N);
1639}

1641void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
                                           unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
bool Narrow = VT.getSizeInBits() == 64;
1
Assuming the condition is true→

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);

if (Narrow1.1
'Narrow' is true
1
'Narrow' is true
)
2
←
Taking true branch→
  transform(Regs, Regs.begin(),
                 WidenVector(*CurDAG));

SDValue RegSeq = createQTuple(Regs);

const EVT ResTys[] = {MVT::i64, // Type of the write back register
                      RegSeq->getValueType(0), MVT::Other};

unsigned LaneNo =
    cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();

SDValue Ops[] = {RegSeq,
                 CurDAG->getTargetConstant(LaneNo, dl,
                                           MVT::i64),         // Lane Number
                 N->getOperand(NumVecs + 2),                  // Base register
                 N->getOperand(NumVecs + 3),                  // Incremental
                 N->getOperand(0)};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);

// Update uses of the write back register
ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));

// Update uses of the vector list
SDValue SuperReg = SDValue(Ld, 1);
if (NumVecs == 1) {
3
←
Assuming 'NumVecs' is equal to 1→
4
←
Taking true branch→
  ReplaceUses(SDValue(N, 0),
              Narrow4.1
'Narrow' is true
1
'Narrow' is true
 ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
5
←
'?' condition is true→
6
←
Null pointer value stored to 'V128Reg.Node'→
7
←
Calling 'NarrowVector'→
} else {
  EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
  static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
                                    AArch64::qsub2, AArch64::qsub3 };
  for (unsigned i = 0; i < NumVecs; ++i) {
    SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
                                                SuperReg);
    if (Narrow)
      NV = NarrowVector(NV, *CurDAG);
    ReplaceUses(SDValue(N, i), NV);
  }
}

// Update the Chain
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
CurDAG->RemoveDeadNode(N);
1694}

1696void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
                                        unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getOperand(2)->getValueType(0);
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);

if (Narrow)
  transform(Regs, Regs.begin(),
                 WidenVector(*CurDAG));

SDValue RegSeq = createQTuple(Regs);

unsigned LaneNo =
    cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();

SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                 N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);

// Transfer memoperands.
MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});

ReplaceNode(N, St);
1723}

1725void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
                                            unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getOperand(2)->getValueType(0);
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);

if (Narrow)
  transform(Regs, Regs.begin(),
                 WidenVector(*CurDAG));

SDValue RegSeq = createQTuple(Regs);

const EVT ResTys[] = {MVT::i64, // Type of the write back register
                      MVT::Other};

unsigned LaneNo =
    cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();

SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                 N->getOperand(NumVecs + 2), // Base Register
                 N->getOperand(NumVecs + 3), // Incremental
                 N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);

// Transfer memoperands.
MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});

ReplaceNode(N, St);
1757}

1759static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
                                     unsigned &Opc, SDValue &Opd0,
                                     unsigned &LSB, unsigned &MSB,
                                     unsigned NumberOfIgnoredLowBits,
                                     bool BiggerPattern) {
assert(N->getOpcode() == ISD::AND &&((N->getOpcode() == ISD::AND && "N must be a AND operation to call this function"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::AND && \"N must be a AND operation to call this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1765, __PRETTY_FUNCTION__))
       "N must be a AND operation to call this function")((N->getOpcode() == ISD::AND && "N must be a AND operation to call this function"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::AND && \"N must be a AND operation to call this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1765, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);

// Here we can test the type of VT and return false when the type does not
// match, but since it is done prior to that call in the current context
// we turned that into an assert to avoid redundant code.
assert((VT == MVT::i32 || VT == MVT::i64) &&(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1773, __PRETTY_FUNCTION__))
       "Type checking must have been done before calling this function")(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1773, __PRETTY_FUNCTION__));

// FIXME: simplify-demanded-bits in DAGCombine will probably have
// changed the AND node to a 32-bit mask operation. We'll have to
// undo that as part of the transform here if we want to catch all
// the opportunities.
// Currently the NumberOfIgnoredLowBits argument helps to recover
// form these situations when matching bigger pattern (bitfield insert).

// For unsigned extracts, check for a shift right and mask
uint64_t AndImm = 0;
if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
  return false;

const SDNode *Op0 = N->getOperand(0).getNode();

// Because of simplify-demanded-bits in DAGCombine, the mask may have been
// simplified. Try to undo that
AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);

// The immediate is a mask of the low bits iff imm & (imm+1) == 0
if (AndImm & (AndImm + 1))
  return false;

bool ClampMSB = false;
uint64_t SrlImm = 0;
// Handle the SRL + ANY_EXTEND case.
if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
    isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
  // Extend the incoming operand of the SRL to 64-bit.
  Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
  // Make sure to clamp the MSB so that we preserve the semantics of the
  // original operations.
  ClampMSB = true;
} else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
           isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
                                 SrlImm)) {
  // If the shift result was truncated, we can still combine them.
  Opd0 = Op0->getOperand(0).getOperand(0);

  // Use the type of SRL node.
  VT = Opd0->getValueType(0);
} else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
  Opd0 = Op0->getOperand(0);
} else if (BiggerPattern) {
  // Let's pretend a 0 shift right has been performed.
  // The resulting code will be at least as good as the original one
  // plus it may expose more opportunities for bitfield insert pattern.
  // FIXME: Currently we limit this to the bigger pattern, because
  // some optimizations expect AND and not UBFM.
  Opd0 = N->getOperand(0);
} else
  return false;

// Bail out on large immediates. This happens when no proper
// combining/constant folding was performed.
if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) {
  LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false)
      (dbgs() << Ndo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false)
              << ": Found large shift immediate, this should not happen\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false);
  return false;
}

LSB = SrlImm;
MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
                               : countTrailingOnes<uint64_t>(AndImm)) -
      1;
if (ClampMSB)
  // Since we're moving the extend before the right shift operation, we need
  // to clamp the MSB to make sure we don't shift in undefined bits instead of
  // the zeros which would get shifted in with the original right shift
  // operation.
  MSB = MSB > 31 ? 31 : MSB;

Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
return true;
1849}

1851static bool isBitfieldExtractOpFromSExtInReg(SDNode *N, unsigned &Opc,
                                           SDValue &Opd0, unsigned &Immr,
                                           unsigned &Imms) {
assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG)((N->getOpcode() == ISD::SIGN_EXTEND_INREG) ? static_cast<
void> (0) : __assert_fail ("N->getOpcode() == ISD::SIGN_EXTEND_INREG"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1854, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);
unsigned BitWidth = VT.getSizeInBits();
assert((VT == MVT::i32 || VT == MVT::i64) &&(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1859, __PRETTY_FUNCTION__))
       "Type checking must have been done before calling this function")(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1859, __PRETTY_FUNCTION__));

SDValue Op = N->getOperand(0);
if (Op->getOpcode() == ISD::TRUNCATE) {
  Op = Op->getOperand(0);
  VT = Op->getValueType(0);
  BitWidth = VT.getSizeInBits();
}

uint64_t ShiftImm;
if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
    !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
  return false;

unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
if (ShiftImm + Width > BitWidth)
  return false;

Opc = (VT == MVT::i32) ? AArch64::SBFMWri : AArch64::SBFMXri;
Opd0 = Op.getOperand(0);
Immr = ShiftImm;
Imms = ShiftImm + Width - 1;
return true;
1882}

1884static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
                                        SDValue &Opd0, unsigned &LSB,
                                        unsigned &MSB) {
// We are looking for the following pattern which basically extracts several
// continuous bits from the source value and places it from the LSB of the
// destination value, all other bits of the destination value or set to zero:
//
// Value2 = AND Value, MaskImm
// SRL Value2, ShiftImm
//
// with MaskImm >> ShiftImm to search for the bit width.
//
// This gets selected into a single UBFM:
//
// UBFM Value, ShiftImm, BitWide + SrlImm -1
//

if (N->getOpcode() != ISD::SRL)
  return false;

uint64_t AndMask = 0;
if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask))
  return false;

Opd0 = N->getOperand(0).getOperand(0);

uint64_t SrlImm = 0;
if (!isIntImmediate(N->getOperand(1), SrlImm))
  return false;

// Check whether we really have several bits extract here.
unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
if (BitWide && isMask_64(AndMask >> SrlImm)) {
  if (N->getValueType(0) == MVT::i32)
    Opc = AArch64::UBFMWri;
  else
    Opc = AArch64::UBFMXri;

  LSB = SrlImm;
  MSB = BitWide + SrlImm - 1;
  return true;
}

return false;
1928}

1930static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
                                     unsigned &Immr, unsigned &Imms,
                                     bool BiggerPattern) {
assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "N must be a SHR/SRA operation to call this function"
) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"N must be a SHR/SRA operation to call this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1934, __PRETTY_FUNCTION__))
       "N must be a SHR/SRA operation to call this function")(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "N must be a SHR/SRA operation to call this function"
) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"N must be a SHR/SRA operation to call this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1934, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);

// Here we can test the type of VT and return false when the type does not
// match, but since it is done prior to that call in the current context
// we turned that into an assert to avoid redundant code.
assert((VT == MVT::i32 || VT == MVT::i64) &&(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1942, __PRETTY_FUNCTION__))
       "Type checking must have been done before calling this function")(((VT == MVT::i32 || VT == MVT::i64) && "Type checking must have been done before calling this function"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"Type checking must have been done before calling this function\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1942, __PRETTY_FUNCTION__));

// Check for AND + SRL doing several bits extract.
if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
  return true;

// We're looking for a shift of a shift.
uint64_t ShlImm = 0;
uint64_t TruncBits = 0;
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, ShlImm)) {
  Opd0 = N->getOperand(0).getOperand(0);
} else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
           N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
  // We are looking for a shift of truncate. Truncate from i64 to i32 could
  // be considered as setting high 32 bits as zero. Our strategy here is to
  // always generate 64bit UBFM. This consistency will help the CSE pass
  // later find more redundancy.
  Opd0 = N->getOperand(0).getOperand(0);
  TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
  VT = Opd0.getValueType();
  assert(VT == MVT::i64 && "the promoted type should be i64")((VT == MVT::i64 && "the promoted type should be i64"
) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i64 && \"the promoted type should be i64\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1962, __PRETTY_FUNCTION__));
} else if (BiggerPattern) {
  // Let's pretend a 0 shift left has been performed.
  // FIXME: Currently we limit this to the bigger pattern case,
  // because some optimizations expect AND and not UBFM
  Opd0 = N->getOperand(0);
} else
  return false;

// Missing combines/constant folding may have left us with strange
// constants.
if (ShlImm >= VT.getSizeInBits()) {
  LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false)
      (dbgs() << Ndo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false)
              << ": Found large shift immediate, this should not happen\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { (dbgs() << N << ": Found large shift immediate, this should not happen\n"
); } } while (false);
  return false;
}

uint64_t SrlImm = 0;
if (!isIntImmediate(N->getOperand(1), SrlImm))
  return false;

assert(SrlImm > 0 && SrlImm < VT.getSizeInBits() &&((SrlImm > 0 && SrlImm < VT.getSizeInBits() &&
 "bad amount in shift node!") ? static_cast<void> (0) :
 __assert_fail ("SrlImm > 0 && SrlImm < VT.getSizeInBits() && \"bad amount in shift node!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1985, __PRETTY_FUNCTION__))
       "bad amount in shift node!")((SrlImm > 0 && SrlImm < VT.getSizeInBits() &&
 "bad amount in shift node!") ? static_cast<void> (0) :
 __assert_fail ("SrlImm > 0 && SrlImm < VT.getSizeInBits() && \"bad amount in shift node!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1985, __PRETTY_FUNCTION__));
int immr = SrlImm - ShlImm;
Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
Imms = VT.getSizeInBits() - ShlImm - TruncBits - 1;
// SRA requires a signed extraction
if (VT == MVT::i32)
  Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
else
  Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
return true;
1995}

1997bool AArch64DAGToDAGISel::tryBitfieldExtractOpFromSExt(SDNode *N) {
assert(N->getOpcode() == ISD::SIGN_EXTEND)((N->getOpcode() == ISD::SIGN_EXTEND) ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::SIGN_EXTEND"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 1998, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);
EVT NarrowVT = N->getOperand(0)->getValueType(0);
if (VT != MVT::i64 || NarrowVT != MVT::i32)
  return false;

uint64_t ShiftImm;
SDValue Op = N->getOperand(0);
if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
  return false;

SDLoc dl(N);
// Extend the incoming operand of the shift to 64-bits.
SDValue Opd0 = Widen(CurDAG, Op.getOperand(0));
unsigned Immr = ShiftImm;
unsigned Imms = NarrowVT.getSizeInBits() - 1;
SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
                 CurDAG->getTargetConstant(Imms, dl, VT)};
CurDAG->SelectNodeTo(N, AArch64::SBFMXri, VT, Ops);
return true;
2019}

2021/// Try to form fcvtl2 instructions from a floating-point extend of a high-half
2022/// extract of a subvector.
2023bool AArch64DAGToDAGISel::tryHighFPExt(SDNode *N) {
assert(N->getOpcode() == ISD::FP_EXTEND)((N->getOpcode() == ISD::FP_EXTEND) ? static_cast<void>
 (0) : __assert_fail ("N->getOpcode() == ISD::FP_EXTEND", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2024, __PRETTY_FUNCTION__));

// There are 2 forms of fcvtl2 - extend to double or extend to float.
SDValue Extract = N->getOperand(0);
EVT VT = N->getValueType(0);
EVT NarrowVT = Extract.getValueType();
if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) &&
    (VT != MVT::v4f32 || NarrowVT != MVT::v4f16))
  return false;

// Optionally look past a bitcast.
Extract = peekThroughBitcasts(Extract);
if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
  return false;

// Match extract from start of high half index.
// Example: v8i16 -> v4i16 means the extract must begin at index 4.
unsigned ExtractIndex = Extract.getConstantOperandVal(1);
if (ExtractIndex != Extract.getValueType().getVectorNumElements())
  return false;

auto Opcode = VT == MVT::v2f64 ? AArch64::FCVTLv4i32 : AArch64::FCVTLv8i16;
CurDAG->SelectNodeTo(N, Opcode, VT, Extract.getOperand(0));
return true;
2048}

2050static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
                              SDValue &Opd0, unsigned &Immr, unsigned &Imms,
                              unsigned NumberOfIgnoredLowBits = 0,
                              bool BiggerPattern = false) {
if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
  return false;

switch (N->getOpcode()) {
default:
  if (!N->isMachineOpcode())
    return false;
  break;
case ISD::AND:
  return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
                                    NumberOfIgnoredLowBits, BiggerPattern);
case ISD::SRL:
case ISD::SRA:
  return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imms, BiggerPattern);

case ISD::SIGN_EXTEND_INREG:
  return isBitfieldExtractOpFromSExtInReg(N, Opc, Opd0, Immr, Imms);
}

unsigned NOpc = N->getMachineOpcode();
switch (NOpc) {
default:
  return false;
case AArch64::SBFMWri:
case AArch64::UBFMWri:
case AArch64::SBFMXri:
case AArch64::UBFMXri:
  Opc = NOpc;
  Opd0 = N->getOperand(0);
  Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
  Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
  return true;
}
// Unreachable
return false;
2089}

2091bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
unsigned Opc, Immr, Imms;
SDValue Opd0;
if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms))
  return false;

EVT VT = N->getValueType(0);
SDLoc dl(N);

// If the bit extract operation is 64bit but the original type is 32bit, we
// need to add one EXTRACT_SUBREG.
if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
  SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
                     CurDAG->getTargetConstant(Imms, dl, MVT::i64)};

  SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
  SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
  ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
                                        MVT::i32, SDValue(BFM, 0), SubReg));
  return true;
}

SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
                 CurDAG->getTargetConstant(Imms, dl, VT)};
CurDAG->SelectNodeTo(N, Opc, VT, Ops);
return true;
2117}

2119/// Does DstMask form a complementary pair with the mask provided by
2120/// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
2121/// this asks whether DstMask zeroes precisely those bits that will be set by
2122/// the other half.
2123static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
                            unsigned NumberOfIgnoredHighBits, EVT VT) {
assert((VT == MVT::i32 || VT == MVT::i64) &&(((VT == MVT::i32 || VT == MVT::i64) && "i32 or i64 mask type expected!"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"i32 or i64 mask type expected!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2126, __PRETTY_FUNCTION__))
       "i32 or i64 mask type expected!")(((VT == MVT::i32 || VT == MVT::i64) && "i32 or i64 mask type expected!"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"i32 or i64 mask type expected!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2126, __PRETTY_FUNCTION__));
unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;

APInt SignificantDstMask = APInt(BitWidth, DstMask);
APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);

return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
       (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
2134}

2136// Look for bits that will be useful for later uses.
2137// A bit is consider useless as soon as it is dropped and never used
2138// before it as been dropped.
2139// E.g., looking for useful bit of x
2140// 1. y = x & 0x7
2141// 2. z = y >> 2
2142// After #1, x useful bits are 0x7, then the useful bits of x, live through
2143// y.
2144// After #2, the useful bits of x are 0x4.
2145// However, if x is used on an unpredicatable instruction, then all its bits
2146// are useful.
2147// E.g.
2148// 1. y = x & 0x7
2149// 2. z = y >> 2
2150// 3. str x, [@x]
2151static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);

2153static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
                                            unsigned Depth) {
uint64_t Imm =
    cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
getUsefulBits(Op, UsefulBits, Depth + 1);
2160}

2162static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
                                           uint64_t Imm, uint64_t MSB,
                                           unsigned Depth) {
// inherit the bitwidth value
APInt OpUsefulBits(UsefulBits);
OpUsefulBits = 1;

if (MSB >= Imm) {
  OpUsefulBits <<= MSB - Imm + 1;
  --OpUsefulBits;
  // The interesting part will be in the lower part of the result
  getUsefulBits(Op, OpUsefulBits, Depth + 1);
  // The interesting part was starting at Imm in the argument
  OpUsefulBits <<= Imm;
} else {
  OpUsefulBits <<= MSB + 1;
  --OpUsefulBits;
  // The interesting part will be shifted in the result
  OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
  getUsefulBits(Op, OpUsefulBits, Depth + 1);
  // The interesting part was at zero in the argument
  OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
}

UsefulBits &= OpUsefulBits;
2187}

2189static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
                                unsigned Depth) {
uint64_t Imm =
    cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
uint64_t MSB =
    cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();

getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
2197}

2199static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
                                            unsigned Depth) {
uint64_t ShiftTypeAndValue =
    cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
APInt Mask(UsefulBits);
Mask.clearAllBits();
Mask.flipAllBits();

if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
  // Shift Left
  uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
  Mask <<= ShiftAmt;
  getUsefulBits(Op, Mask, Depth + 1);
  Mask.lshrInPlace(ShiftAmt);
} else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
  // Shift Right
  // We do not handle AArch64_AM::ASR, because the sign will change the
  // number of useful bits
  uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
  Mask.lshrInPlace(ShiftAmt);
  getUsefulBits(Op, Mask, Depth + 1);
  Mask <<= ShiftAmt;
} else
  return;

UsefulBits &= Mask;
2225}

2227static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
                               unsigned Depth) {
uint64_t Imm =
    cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
uint64_t MSB =
    cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();

APInt OpUsefulBits(UsefulBits);
OpUsefulBits = 1;

APInt ResultUsefulBits(UsefulBits.getBitWidth(), 0);
ResultUsefulBits.flipAllBits();
APInt Mask(UsefulBits.getBitWidth(), 0);

getUsefulBits(Op, ResultUsefulBits, Depth + 1);

if (MSB >= Imm) {
  // The instruction is a BFXIL.
  uint64_t Width = MSB - Imm + 1;
  uint64_t LSB = Imm;

  OpUsefulBits <<= Width;
  --OpUsefulBits;

  if (Op.getOperand(1) == Orig) {
    // Copy the low bits from the result to bits starting from LSB.
    Mask = ResultUsefulBits & OpUsefulBits;
    Mask <<= LSB;
  }

  if (Op.getOperand(0) == Orig)
    // Bits starting from LSB in the input contribute to the result.
    Mask |= (ResultUsefulBits & ~OpUsefulBits);
} else {
  // The instruction is a BFI.
  uint64_t Width = MSB + 1;
  uint64_t LSB = UsefulBits.getBitWidth() - Imm;

  OpUsefulBits <<= Width;
  --OpUsefulBits;
  OpUsefulBits <<= LSB;

  if (Op.getOperand(1) == Orig) {
    // Copy the bits from the result to the zero bits.
    Mask = ResultUsefulBits & OpUsefulBits;
    Mask.lshrInPlace(LSB);
  }

  if (Op.getOperand(0) == Orig)
    Mask |= (ResultUsefulBits & ~OpUsefulBits);
}

UsefulBits &= Mask;
2280}

2282static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
                              SDValue Orig, unsigned Depth) {

// Users of this node should have already been instruction selected
// FIXME: Can we turn that into an assert?
if (!UserNode->isMachineOpcode())
  return;

switch (UserNode->getMachineOpcode()) {
default:
  return;
case AArch64::ANDSWri:
case AArch64::ANDSXri:
case AArch64::ANDWri:
case AArch64::ANDXri:
  // We increment Depth only when we call the getUsefulBits
  return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
                                           Depth);
case AArch64::UBFMWri:
case AArch64::UBFMXri:
  return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);

case AArch64::ORRWrs:
case AArch64::ORRXrs:
  if (UserNode->getOperand(1) != Orig)
    return;
  return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
                                           Depth);
case AArch64::BFMWri:
case AArch64::BFMXri:
  return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);

case AArch64::STRBBui:
case AArch64::STURBBi:
  if (UserNode->getOperand(0) != Orig)
    return;
  UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
  return;

case AArch64::STRHHui:
case AArch64::STURHHi:
  if (UserNode->getOperand(0) != Orig)
    return;
  UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
  return;
}
2328}

2330static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
if (Depth >= SelectionDAG::MaxRecursionDepth)
  return;
// Initialize UsefulBits
if (!Depth) {
  unsigned Bitwidth = Op.getScalarValueSizeInBits();
  // At the beginning, assume every produced bits is useful
  UsefulBits = APInt(Bitwidth, 0);
  UsefulBits.flipAllBits();
}
APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);

for (SDNode *Node : Op.getNode()->uses()) {
  // A use cannot produce useful bits
  APInt UsefulBitsForUse = APInt(UsefulBits);
  getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
  UsersUsefulBits |= UsefulBitsForUse;
}
// UsefulBits contains the produced bits that are meaningful for the
// current definition, thus a user cannot make a bit meaningful at
// this point
UsefulBits &= UsersUsefulBits;
2352}

2354/// Create a machine node performing a notional SHL of Op by ShlAmount. If
2355/// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
2356/// 0, return Op unchanged.
2357static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
if (ShlAmount == 0)
  return Op;

EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned BitWidth = VT.getSizeInBits();
unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;

SDNode *ShiftNode;
if (ShlAmount > 0) {
  // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
  ShiftNode = CurDAG->getMachineNode(
      UBFMOpc, dl, VT, Op,
      CurDAG->getTargetConstant(BitWidth - ShlAmount, dl, VT),
      CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, dl, VT));
} else {
  // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
  assert(ShlAmount < 0 && "expected right shift")((ShlAmount < 0 && "expected right shift") ? static_cast
<void> (0) : __assert_fail ("ShlAmount < 0 && \"expected right shift\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2375, __PRETTY_FUNCTION__));
  int ShrAmount = -ShlAmount;
  ShiftNode = CurDAG->getMachineNode(
      UBFMOpc, dl, VT, Op, CurDAG->getTargetConstant(ShrAmount, dl, VT),
      CurDAG->getTargetConstant(BitWidth - 1, dl, VT));
}

return SDValue(ShiftNode, 0);
2383}

2385/// Does this tree qualify as an attempt to move a bitfield into position,
2386/// essentially "(and (shl VAL, N), Mask)".
2387static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
                                  bool BiggerPattern,
                                  SDValue &Src, int &ShiftAmount,
                                  int &MaskWidth) {
EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
(void)BitWidth;
assert(BitWidth == 32 || BitWidth == 64)((BitWidth == 32 || BitWidth == 64) ? static_cast<void>
 (0) : __assert_fail ("BitWidth == 32 || BitWidth == 64", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2394, __PRETTY_FUNCTION__));

KnownBits Known = CurDAG->computeKnownBits(Op);

// Non-zero in the sense that they're not provably zero, which is the key
// point if we want to use this value
uint64_t NonZeroBits = (~Known.Zero).getZExtValue();

// Discard a constant AND mask if present. It's safe because the node will
// already have been factored into the computeKnownBits calculation above.
uint64_t AndImm;
if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
  assert((~APInt(BitWidth, AndImm) & ~Known.Zero) == 0)(((~APInt(BitWidth, AndImm) & ~Known.Zero) == 0) ? static_cast
<void> (0) : __assert_fail ("(~APInt(BitWidth, AndImm) & ~Known.Zero) == 0"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2406, __PRETTY_FUNCTION__));
  Op = Op.getOperand(0);
}

// Don't match if the SHL has more than one use, since then we'll end up
// generating SHL+UBFIZ instead of just keeping SHL+AND.
if (!BiggerPattern && !Op.hasOneUse())
  return false;

uint64_t ShlImm;
if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
  return false;
Op = Op.getOperand(0);

if (!isShiftedMask_64(NonZeroBits))
  return false;

ShiftAmount = countTrailingZeros(NonZeroBits);
MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);

// BFI encompasses sufficiently many nodes that it's worth inserting an extra
// LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
// amount.  BiggerPattern is true when this pattern is being matched for BFI,
// BiggerPattern is false when this pattern is being matched for UBFIZ, in
// which case it is not profitable to insert an extra shift.
if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
  return false;
Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);

return true;
2436}

2438static bool isShiftedMask(uint64_t Mask, EVT VT) {
assert(VT == MVT::i32 || VT == MVT::i64)((VT == MVT::i32 || VT == MVT::i64) ? static_cast<void>
 (0) : __assert_fail ("VT == MVT::i32 || VT == MVT::i64", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2439, __PRETTY_FUNCTION__));
if (VT == MVT::i32)
  return isShiftedMask_32(Mask);
return isShiftedMask_64(Mask);
2443}

2445// Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being
2446// inserted only sets known zero bits.
2447static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
assert(N->getOpcode() == ISD::OR && "Expect a OR operation")((N->getOpcode() == ISD::OR && "Expect a OR operation"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::OR && \"Expect a OR operation\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2448, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
  return false;

unsigned BitWidth = VT.getSizeInBits();

uint64_t OrImm;
if (!isOpcWithIntImmediate(N, ISD::OR, OrImm))
  return false;

// Skip this transformation if the ORR immediate can be encoded in the ORR.
// Otherwise, we'll trade an AND+ORR for ORR+BFI/BFXIL, which is most likely
// performance neutral.
if (AArch64_AM::isLogicalImmediate(OrImm, BitWidth))
  return false;

uint64_t MaskImm;
SDValue And = N->getOperand(0);
// Must be a single use AND with an immediate operand.
if (!And.hasOneUse() ||
    !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm))
  return false;

// Compute the Known Zero for the AND as this allows us to catch more general
// cases than just looking for AND with imm.
KnownBits Known = CurDAG->computeKnownBits(And);

// Non-zero in the sense that they're not provably zero, which is the key
// point if we want to use this value.
uint64_t NotKnownZero = (~Known.Zero).getZExtValue();

// The KnownZero mask must be a shifted mask (e.g., 1110..011, 11100..00).
if (!isShiftedMask(Known.Zero.getZExtValue(), VT))
  return false;

// The bits being inserted must only set those bits that are known to be zero.
if ((OrImm & NotKnownZero) != 0) {
  // FIXME:  It's okay if the OrImm sets NotKnownZero bits to 1, but we don't
  // currently handle this case.
  return false;
}

// BFI/BFXIL dst, src, #lsb, #width.
int LSB = countTrailingOnes(NotKnownZero);
int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();

// BFI/BFXIL is an alias of BFM, so translate to BFM operands.
unsigned ImmR = (BitWidth - LSB) % BitWidth;
unsigned ImmS = Width - 1;

// If we're creating a BFI instruction avoid cases where we need more
// instructions to materialize the BFI constant as compared to the original
// ORR.  A BFXIL will use the same constant as the original ORR, so the code
// should be no worse in this case.
bool IsBFI = LSB != 0;
uint64_t BFIImm = OrImm >> LSB;
if (IsBFI && !AArch64_AM::isLogicalImmediate(BFIImm, BitWidth)) {
  // We have a BFI instruction and we know the constant can't be materialized
  // with a ORR-immediate with the zero register.
  unsigned OrChunks = 0, BFIChunks = 0;
  for (unsigned Shift = 0; Shift < BitWidth; Shift += 16) {
    if (((OrImm >> Shift) & 0xFFFF) != 0)
      ++OrChunks;
    if (((BFIImm >> Shift) & 0xFFFF) != 0)
      ++BFIChunks;
  }
  if (BFIChunks > OrChunks)
    return false;
}

// Materialize the constant to be inserted.
SDLoc DL(N);
unsigned MOVIOpc = VT == MVT::i32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
SDNode *MOVI = CurDAG->getMachineNode(
    MOVIOpc, DL, VT, CurDAG->getTargetConstant(BFIImm, DL, VT));

// Create the BFI/BFXIL instruction.
SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
                 CurDAG->getTargetConstant(ImmR, DL, VT),
                 CurDAG->getTargetConstant(ImmS, DL, VT)};
unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
CurDAG->SelectNodeTo(N, Opc, VT, Ops);
return true;
2533}

2535static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
                                    SelectionDAG *CurDAG) {
assert(N->getOpcode() == ISD::OR && "Expect a OR operation")((N->getOpcode() == ISD::OR && "Expect a OR operation"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::OR && \"Expect a OR operation\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2537, __PRETTY_FUNCTION__));

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
  return false;

unsigned BitWidth = VT.getSizeInBits();

// Because of simplify-demanded-bits in DAGCombine, involved masks may not
// have the expected shape. Try to undo that.

unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();

// Given a OR operation, check if we have the following pattern
// ubfm c, b, imm, imm2 (or something that does the same jobs, see
//                       isBitfieldExtractOp)
// d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
//                 countTrailingZeros(mask2) == imm2 - imm + 1
// f = d | c
// if yes, replace the OR instruction with:
// f = BFM Opd0, Opd1, LSB, MSB ; where LSB = imm, and MSB = imm2

// OR is commutative, check all combinations of operand order and values of
// BiggerPattern, i.e.
//     Opd0, Opd1, BiggerPattern=false
//     Opd1, Opd0, BiggerPattern=false
//     Opd0, Opd1, BiggerPattern=true
//     Opd1, Opd0, BiggerPattern=true
// Several of these combinations may match, so check with BiggerPattern=false
// first since that will produce better results by matching more instructions
// and/or inserting fewer extra instructions.
for (int I = 0; I < 4; ++I) {

  SDValue Dst, Src;
  unsigned ImmR, ImmS;
  bool BiggerPattern = I / 2;
  SDValue OrOpd0Val = N->getOperand(I % 2);
  SDNode *OrOpd0 = OrOpd0Val.getNode();
  SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
  SDNode *OrOpd1 = OrOpd1Val.getNode();

  unsigned BFXOpc;
  int DstLSB, Width;
  if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
                          NumberOfIgnoredLowBits, BiggerPattern)) {
    // Check that the returned opcode is compatible with the pattern,
    // i.e., same type and zero extended (U and not S)
    if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
        (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
      continue;

    // Compute the width of the bitfield insertion
    DstLSB = 0;
    Width = ImmS - ImmR + 1;
    // FIXME: This constraint is to catch bitfield insertion we may
    // want to widen the pattern if we want to grab general bitfied
    // move case
    if (Width <= 0)
      continue;

    // If the mask on the insertee is correct, we have a BFXIL operation. We
    // can share the ImmR and ImmS values from the already-computed UBFM.
  } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
                                     BiggerPattern,
                                     Src, DstLSB, Width)) {
    ImmR = (BitWidth - DstLSB) % BitWidth;
    ImmS = Width - 1;
  } else
    continue;

  // Check the second part of the pattern
  EVT VT = OrOpd1Val.getValueType();
  assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand")(((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand"
) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"unexpected OR operand\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2610, __PRETTY_FUNCTION__));

  // Compute the Known Zero for the candidate of the first operand.
  // This allows to catch more general case than just looking for
  // AND with imm. Indeed, simplify-demanded-bits may have removed
  // the AND instruction because it proves it was useless.
  KnownBits Known = CurDAG->computeKnownBits(OrOpd1Val);

  // Check if there is enough room for the second operand to appear
  // in the first one
  APInt BitsToBeInserted =
      APInt::getBitsSet(Known.getBitWidth(), DstLSB, DstLSB + Width);

  if ((BitsToBeInserted & ~Known.Zero) != 0)
    continue;

  // Set the first operand
  uint64_t Imm;
  if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
      isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
    // In that case, we can eliminate the AND
    Dst = OrOpd1->getOperand(0);
  else
    // Maybe the AND has been removed by simplify-demanded-bits
    // or is useful because it discards more bits
    Dst = OrOpd1Val;

  // both parts match
  SDLoc DL(N);
  SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
                   CurDAG->getTargetConstant(ImmS, DL, VT)};
  unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
  CurDAG->SelectNodeTo(N, Opc, VT, Ops);
  return true;
}

// Generate a BFXIL from 'or (and X, Mask0Imm), (and Y, Mask1Imm)' iff
// Mask0Imm and ~Mask1Imm are equivalent and one of the MaskImms is a shifted
// mask (e.g., 0x000ffff0).
uint64_t Mask0Imm, Mask1Imm;
SDValue And0 = N->getOperand(0);
SDValue And1 = N->getOperand(1);
if (And0.hasOneUse() && And1.hasOneUse() &&
    isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
    isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) &&
    APInt(BitWidth, Mask0Imm) == ~APInt(BitWidth, Mask1Imm) &&
    (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) {

  // ORR is commutative, so canonicalize to the form 'or (and X, Mask0Imm),
  // (and Y, Mask1Imm)' where Mask1Imm is the shifted mask masking off the
  // bits to be inserted.
  if (isShiftedMask(Mask0Imm, VT)) {
    std::swap(And0, And1);
    std::swap(Mask0Imm, Mask1Imm);
  }

  SDValue Src = And1->getOperand(0);
  SDValue Dst = And0->getOperand(0);
  unsigned LSB = countTrailingZeros(Mask1Imm);
  int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();

  // The BFXIL inserts the low-order bits from a source register, so right
  // shift the needed bits into place.
  SDLoc DL(N);
  unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
  SDNode *LSR = CurDAG->getMachineNode(
      ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT),
      CurDAG->getTargetConstant(BitWidth - 1, DL, VT));

  // BFXIL is an alias of BFM, so translate to BFM operands.
  unsigned ImmR = (BitWidth - LSB) % BitWidth;
  unsigned ImmS = Width - 1;

  // Create the BFXIL instruction.
  SDValue Ops[] = {Dst, SDValue(LSR, 0),
                   CurDAG->getTargetConstant(ImmR, DL, VT),
                   CurDAG->getTargetConstant(ImmS, DL, VT)};
  unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
  CurDAG->SelectNodeTo(N, Opc, VT, Ops);
  return true;
}

return false;
2693}

2695bool AArch64DAGToDAGISel::tryBitfieldInsertOp(SDNode *N) {
if (N->getOpcode() != ISD::OR)
  return false;

APInt NUsefulBits;
getUsefulBits(SDValue(N, 0), NUsefulBits);

// If all bits are not useful, just return UNDEF.
if (!NUsefulBits) {
  CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF, N->getValueType(0));
  return true;
}

if (tryBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG))
  return true;

return tryBitfieldInsertOpFromOrAndImm(N, CurDAG);
2712}

2714/// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the
2715/// equivalent of a left shift by a constant amount followed by an and masking
2716/// out a contiguous set of bits.
2717bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) {
if (N->getOpcode() != ISD::AND)
  return false;

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
  return false;

SDValue Op0;
int DstLSB, Width;
if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
                             Op0, DstLSB, Width))
  return false;

// ImmR is the rotate right amount.
unsigned ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
// ImmS is the most significant bit of the source to be moved.
unsigned ImmS = Width - 1;

SDLoc DL(N);
SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
                 CurDAG->getTargetConstant(ImmS, DL, VT)};
unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
CurDAG->SelectNodeTo(N, Opc, VT, Ops);
return true;
2742}

2744/// tryShiftAmountMod - Take advantage of built-in mod of shift amount in
2745/// variable shift/rotate instructions.
2746bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) {
EVT VT = N->getValueType(0);

unsigned Opc;
switch (N->getOpcode()) {
case ISD::ROTR:
  Opc = (VT == MVT::i32) ? AArch64::RORVWr : AArch64::RORVXr;
  break;
case ISD::SHL:
  Opc = (VT == MVT::i32) ? AArch64::LSLVWr : AArch64::LSLVXr;
  break;
case ISD::SRL:
  Opc = (VT == MVT::i32) ? AArch64::LSRVWr : AArch64::LSRVXr;
  break;
case ISD::SRA:
  Opc = (VT == MVT::i32) ? AArch64::ASRVWr : AArch64::ASRVXr;
  break;
default:
  return false;
}

uint64_t Size;
uint64_t Bits;
if (VT == MVT::i32) {
  Bits = 5;
  Size = 32;
} else if (VT == MVT::i64) {
  Bits = 6;
  Size = 64;
} else
  return false;

SDValue ShiftAmt = N->getOperand(1);
SDLoc DL(N);
SDValue NewShiftAmt;

// Skip over an extend of the shift amount.
if (ShiftAmt->getOpcode() == ISD::ZERO_EXTEND ||
    ShiftAmt->getOpcode() == ISD::ANY_EXTEND)
  ShiftAmt = ShiftAmt->getOperand(0);

if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
  SDValue Add0 = ShiftAmt->getOperand(0);
  SDValue Add1 = ShiftAmt->getOperand(1);
  uint64_t Add0Imm;
  uint64_t Add1Imm;
  // If we are shifting by X+/-N where N == 0 mod Size, then just shift by X
  // to avoid the ADD/SUB.
  if (isIntImmediate(Add1, Add1Imm) && (Add1Imm % Size == 0))
    NewShiftAmt = Add0;
  // If we are shifting by N-X where N == 0 mod Size, then just shift by -X to
  // generate a NEG instead of a SUB of a constant.
  else if (ShiftAmt->getOpcode() == ISD::SUB &&
           isIntImmediate(Add0, Add0Imm) && Add0Imm != 0 &&
           (Add0Imm % Size == 0)) {
    unsigned NegOpc;
    unsigned ZeroReg;
    EVT SubVT = ShiftAmt->getValueType(0);
    if (SubVT == MVT::i32) {
      NegOpc = AArch64::SUBWrr;
      ZeroReg = AArch64::WZR;
    } else {
      assert(SubVT == MVT::i64)((SubVT == MVT::i64) ? static_cast<void> (0) : __assert_fail
 ("SubVT == MVT::i64", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2808, __PRETTY_FUNCTION__));
      NegOpc = AArch64::SUBXrr;
      ZeroReg = AArch64::XZR;
    }
    SDValue Zero =
        CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT);
    MachineSDNode *Neg =
        CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1);
    NewShiftAmt = SDValue(Neg, 0);
  } else
    return false;
} else {
  // If the shift amount is masked with an AND, check that the mask covers the
  // bits that are implicitly ANDed off by the above opcodes and if so, skip
  // the AND.
  uint64_t MaskImm;
  if (!isOpcWithIntImmediate(ShiftAmt.getNode(), ISD::AND, MaskImm) &&
      !isOpcWithIntImmediate(ShiftAmt.getNode(), AArch64ISD::ANDS, MaskImm))
    return false;

  if (countTrailingOnes(MaskImm) < Bits)
    return false;

  NewShiftAmt = ShiftAmt->getOperand(0);
}

// Narrow/widen the shift amount to match the size of the shift operation.
if (VT == MVT::i32)
  NewShiftAmt = narrowIfNeeded(CurDAG, NewShiftAmt);
else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) {
  SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32);
  MachineSDNode *Ext = CurDAG->getMachineNode(
      AArch64::SUBREG_TO_REG, DL, VT,
      CurDAG->getTargetConstant(0, DL, MVT::i64), NewShiftAmt, SubReg);
  NewShiftAmt = SDValue(Ext, 0);
}

SDValue Ops[] = {N->getOperand(0), NewShiftAmt};
CurDAG->SelectNodeTo(N, Opc, VT, Ops);
return true;
2848}

2850bool
2851AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
                                            unsigned RegWidth) {
APFloat FVal(0.0);
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
  FVal = CN->getValueAPF();
else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
  // Some otherwise illegal constants are allowed in this case.
  if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
      !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
    return false;

  ConstantPoolSDNode *CN =
      dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
  FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
} else
  return false;

// An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
// is between 1 and 32 for a destination w-register, or 1 and 64 for an
// x-register.
//
// By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
// want THIS_NODE to be 2^fbits. This is much easier to deal with using
// integers.
bool IsExact;

// fbits is between 1 and 64 in the worst-case, which means the fmul
// could have 2^64 as an actual operand. Need 65 bits of precision.
APSInt IntVal(65, true);
FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);

// N.b. isPowerOf2 also checks for > 0.
if (!IsExact || !IntVal.isPowerOf2()) return false;
unsigned FBits = IntVal.logBase2();

// Checks above should have guaranteed that we haven't lost information in
// finding FBits, but it must still be in range.
if (FBits == 0 || FBits > RegWidth) return false;

FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32);
return true;
2892}

2894// Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields
2895// of the string and obtains the integer values from them and combines these
2896// into a single value to be used in the MRS/MSR instruction.
2897static int getIntOperandFromRegisterString(StringRef RegString) {
SmallVector<StringRef, 5> Fields;
RegString.split(Fields, ':');

if (Fields.size() == 1)
  return -1;

assert(Fields.size() == 5((Fields.size() == 5 && "Invalid number of fields in read register string"
) ? static_cast<void> (0) : __assert_fail ("Fields.size() == 5 && \"Invalid number of fields in read register string\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2905, __PRETTY_FUNCTION__))
          && "Invalid number of fields in read register string")((Fields.size() == 5 && "Invalid number of fields in read register string"
) ? static_cast<void> (0) : __assert_fail ("Fields.size() == 5 && \"Invalid number of fields in read register string\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2905, __PRETTY_FUNCTION__));

SmallVector<int, 5> Ops;
bool AllIntFields = true;

for (StringRef Field : Fields) {
  unsigned IntField;
  AllIntFields &= !Field.getAsInteger(10, IntField);
  Ops.push_back(IntField);
}

assert(AllIntFields &&((AllIntFields && "Unexpected non-integer value in special register string."
) ? static_cast<void> (0) : __assert_fail ("AllIntFields && \"Unexpected non-integer value in special register string.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2917, __PRETTY_FUNCTION__))
        "Unexpected non-integer value in special register string.")((AllIntFields && "Unexpected non-integer value in special register string."
) ? static_cast<void> (0) : __assert_fail ("AllIntFields && \"Unexpected non-integer value in special register string.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2917, __PRETTY_FUNCTION__));

// Need to combine the integer fields of the string into a single value
// based on the bit encoding of MRS/MSR instruction.
return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
       (Ops[3] << 3) | (Ops[4]);
2923}

2925// Lower the read_register intrinsic to an MRS instruction node if the special
2926// register string argument is either of the form detailed in the ALCE (the
2927// form described in getIntOperandsFromRegsterString) or is a named register
2928// known by the MRS SysReg mapper.
2929bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
SDLoc DL(N);

int Reg = getIntOperandFromRegisterString(RegString->getString());
if (Reg != -1) {
  ReplaceNode(N, CurDAG->getMachineNode(
                     AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
                     CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                     N->getOperand(0)));
  return true;
}

// Use the sysreg mapper to map the remaining possible strings to the
// value for the register to be used for the instruction operand.
auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
if (TheReg && TheReg->Readable &&
    TheReg->haveFeatures(Subtarget->getFeatureBits()))
  Reg = TheReg->Encoding;
else
  Reg = AArch64SysReg::parseGenericRegister(RegString->getString());

if (Reg != -1) {
  ReplaceNode(N, CurDAG->getMachineNode(
                     AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
                     CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                     N->getOperand(0)));
  return true;
}

if (RegString->getString() == "pc") {
  ReplaceNode(N, CurDAG->getMachineNode(
                     AArch64::ADR, DL, N->getSimpleValueType(0), MVT::Other,
                     CurDAG->getTargetConstant(0, DL, MVT::i32),
                     N->getOperand(0)));
  return true;
}

return false;
2969}

2971// Lower the write_register intrinsic to an MSR instruction node if the special
2972// register string argument is either of the form detailed in the ALCE (the
2973// form described in getIntOperandsFromRegsterString) or is a named register
2974// known by the MSR SysReg mapper.
2975bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
SDLoc DL(N);

int Reg = getIntOperandFromRegisterString(RegString->getString());
if (Reg != -1) {
  ReplaceNode(
      N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other,
                                CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                                N->getOperand(2), N->getOperand(0)));
  return true;
}

// Check if the register was one of those allowed as the pstatefield value in
// the MSR (immediate) instruction. To accept the values allowed in the
// pstatefield for the MSR (immediate) instruction, we also require that an
// immediate value has been provided as an argument, we know that this is
// the case as it has been ensured by semantic checking.
auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());
if (PMapper) {
  assert (isa<ConstantSDNode>(N->getOperand(2))((isa<ConstantSDNode>(N->getOperand(2)) && "Expected a constant integer expression."
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N->getOperand(2)) && \"Expected a constant integer expression.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2997, __PRETTY_FUNCTION__))
            && "Expected a constant integer expression.")((isa<ConstantSDNode>(N->getOperand(2)) && "Expected a constant integer expression."
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N->getOperand(2)) && \"Expected a constant integer expression.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 2997, __PRETTY_FUNCTION__));
  unsigned Reg = PMapper->Encoding;
  uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
  unsigned State;
  if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO || Reg == AArch64PState::SSBS) {
    assert(Immed < 2 && "Bad imm")((Immed < 2 && "Bad imm") ? static_cast<void>
 (0) : __assert_fail ("Immed < 2 && \"Bad imm\"", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3002, __PRETTY_FUNCTION__));
    State = AArch64::MSRpstateImm1;
  } else {
    assert(Immed < 16 && "Bad imm")((Immed < 16 && "Bad imm") ? static_cast<void>
 (0) : __assert_fail ("Immed < 16 && \"Bad imm\"",
 "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3005, __PRETTY_FUNCTION__));
    State = AArch64::MSRpstateImm4;
  }
  ReplaceNode(N, CurDAG->getMachineNode(
                     State, DL, MVT::Other,
                     CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                     CurDAG->getTargetConstant(Immed, DL, MVT::i16),
                     N->getOperand(0)));
  return true;
}

// Use the sysreg mapper to attempt to map the remaining possible strings
// to the value for the register to be used for the MSR (register)
// instruction operand.
auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
if (TheReg && TheReg->Writeable &&
    TheReg->haveFeatures(Subtarget->getFeatureBits()))
  Reg = TheReg->Encoding;
else
  Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
if (Reg != -1) {
  ReplaceNode(N, CurDAG->getMachineNode(
                     AArch64::MSR, DL, MVT::Other,
                     CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                     N->getOperand(2), N->getOperand(0)));
  return true;
}

return false;
3034}

3036/// We've got special pseudo-instructions for these
3037bool AArch64DAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
unsigned Opcode;
EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();

// Leave IR for LSE if subtarget supports it.
if (Subtarget->hasLSE()) return false;

if (MemTy == MVT::i8)
  Opcode = AArch64::CMP_SWAP_8;
else if (MemTy == MVT::i16)
  Opcode = AArch64::CMP_SWAP_16;
else if (MemTy == MVT::i32)
  Opcode = AArch64::CMP_SWAP_32;
else if (MemTy == MVT::i64)
  Opcode = AArch64::CMP_SWAP_64;
else
  llvm_unreachable("Unknown AtomicCmpSwap type")::llvm::llvm_unreachable_internal("Unknown AtomicCmpSwap type"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3053);

MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32;
SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
                 N->getOperand(0)};
SDNode *CmpSwap = CurDAG->getMachineNode(
    Opcode, SDLoc(N),
    CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);

MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp});

ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
CurDAG->RemoveDeadNode(N);

return true;
3070}

3072bool AArch64DAGToDAGISel::SelectSVE8BitLslImm(SDValue N, SDValue &Base,
                                                SDValue &Offset) {
auto C = dyn_cast<ConstantSDNode>(N);
if (!C)
  return false;

auto Ty = N->getValueType(0);

int64_t Imm = C->getSExtValue();
SDLoc DL(N);

if ((Imm >= -128) && (Imm <= 127)) {
  Base = CurDAG->getTargetConstant(Imm, DL, Ty);
  Offset = CurDAG->getTargetConstant(0, DL, Ty);
  return true;
}

if (((Imm % 256) == 0) && (Imm >= -32768) && (Imm <= 32512)) {
  Base = CurDAG->getTargetConstant(Imm/256, DL, Ty);
  Offset = CurDAG->getTargetConstant(8, DL, Ty);
  return true;
}

return false;
3096}

3098bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift) {
if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
  const int64_t ImmVal = CNode->getZExtValue();
  SDLoc DL(N);

  switch (VT.SimpleTy) {
  case MVT::i8:
    if ((ImmVal & 0xFF) == ImmVal) {
      Shift = CurDAG->getTargetConstant(0, DL, MVT::i32);
      Imm = CurDAG->getTargetConstant(ImmVal, DL, MVT::i32);
      return true;
    }
    break;
  case MVT::i16:
  case MVT::i32:
  case MVT::i64:
    if ((ImmVal & 0xFF) == ImmVal) {
      Shift = CurDAG->getTargetConstant(0, DL, MVT::i32);
      Imm = CurDAG->getTargetConstant(ImmVal, DL, MVT::i32);
      return true;
    } else if ((ImmVal & 0xFF00) == ImmVal) {
      Shift = CurDAG->getTargetConstant(8, DL, MVT::i32);
      Imm = CurDAG->getTargetConstant(ImmVal >> 8, DL, MVT::i32);
      return true;
    }
    break;
  default:
    break;
  }
}

return false;
3130}

3132bool AArch64DAGToDAGISel::SelectSVESignedArithImm(SDValue N, SDValue &Imm) {
if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
  int64_t ImmVal = CNode->getSExtValue();
  SDLoc DL(N);
  if (ImmVal >= -128 && ImmVal < 128) {
    Imm = CurDAG->getTargetConstant(ImmVal, DL, MVT::i32);
    return true;
  }
}
return false;
3142}

3144bool AArch64DAGToDAGISel::SelectSVEArithImm(SDValue N, MVT VT, SDValue &Imm) {
if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
  uint64_t ImmVal = CNode->getZExtValue();

  switch (VT.SimpleTy) {
  case MVT::i8:
    ImmVal &= 0xFF;
    break;
  case MVT::i16:
    ImmVal &= 0xFFFF;
    break;
  case MVT::i32:
    ImmVal &= 0xFFFFFFFF;
    break;
  case MVT::i64:
    break;
  default:
    llvm_unreachable("Unexpected type")::llvm::llvm_unreachable_internal("Unexpected type", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3161);
  }

  if (ImmVal < 256) {
    Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i32);
    return true;
  }
}
return false;
3170}

3172bool AArch64DAGToDAGISel::SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm) {
if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
  uint64_t ImmVal = CNode->getZExtValue();
  SDLoc DL(N);

  // Shift mask depending on type size.
  switch (VT.SimpleTy) {
    case MVT::i8:
      ImmVal &= 0xFF;
      ImmVal |= ImmVal << 8;
      ImmVal |= ImmVal << 16;
      ImmVal |= ImmVal << 32;
      break;
    case MVT::i16:
      ImmVal &= 0xFFFF;
      ImmVal |= ImmVal << 16;
      ImmVal |= ImmVal << 32;
      break;
    case MVT::i32:
      ImmVal &= 0xFFFFFFFF;
      ImmVal |= ImmVal << 32;
      break;
    case MVT::i64:
      break;
    default:
      llvm_unreachable("Unexpected type")::llvm::llvm_unreachable_internal("Unexpected type", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3197);
  }

  uint64_t encoding;
  if (AArch64_AM::processLogicalImmediate(ImmVal, 64, encoding)) {
    Imm = CurDAG->getTargetConstant(encoding, DL, MVT::i64);
    return true;
  }
}
return false;
3207}

3209// SVE shift intrinsics allow shift amounts larger than the element's bitwidth.
3210// Rather than attempt to normalise everything we can sometimes saturate the
3211// shift amount during selection. This function also allows for consistent
3212// isel patterns by ensuring the resulting "Imm" node is of the i32 type
3213// required by the instructions.
3214bool AArch64DAGToDAGISel::SelectSVEShiftImm(SDValue N, uint64_t Low,
                                          uint64_t High, bool AllowSaturation,
                                          SDValue &Imm) {
if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
  uint64_t ImmVal = CN->getZExtValue();

  // Reject shift amounts that are too small.
  if (ImmVal < Low)
    return false;

  // Reject or saturate shift amounts that are too big.
  if (ImmVal > High) {
    if (!AllowSaturation)
      return false;
    ImmVal = High;
  }

  Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i32);
  return true;
}

return false;
3236}

3238bool AArch64DAGToDAGISel::trySelectStackSlotTagP(SDNode *N) {
// tagp(FrameIndex, IRGstack, tag_offset):
// since the offset between FrameIndex and IRGstack is a compile-time
// constant, this can be lowered to a single ADDG instruction.
if (!(isa<FrameIndexSDNode>(N->getOperand(1)))) {
  return false;
}

SDValue IRG_SP = N->getOperand(2);
if (IRG_SP->getOpcode() != ISD::INTRINSIC_W_CHAIN ||
    cast<ConstantSDNode>(IRG_SP->getOperand(1))->getZExtValue() !=
        Intrinsic::aarch64_irg_sp) {
  return false;
}

const TargetLowering *TLI = getTargetLowering();
SDLoc DL(N);
int FI = cast<FrameIndexSDNode>(N->getOperand(1))->getIndex();
SDValue FiOp = CurDAG->getTargetFrameIndex(
    FI, TLI->getPointerTy(CurDAG->getDataLayout()));
int TagOffset = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();

SDNode *Out = CurDAG->getMachineNode(
    AArch64::TAGPstack, DL, MVT::i64,
    {FiOp, CurDAG->getTargetConstant(0, DL, MVT::i64), N->getOperand(2),
     CurDAG->getTargetConstant(TagOffset, DL, MVT::i64)});
ReplaceNode(N, Out);
return true;
3266}

3268void AArch64DAGToDAGISel::SelectTagP(SDNode *N) {
assert(isa<ConstantSDNode>(N->getOperand(3)) &&((isa<ConstantSDNode>(N->getOperand(3)) && "llvm.aarch64.tagp third argument must be an immediate"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N->getOperand(3)) && \"llvm.aarch64.tagp third argument must be an immediate\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3270, __PRETTY_FUNCTION__))
       "llvm.aarch64.tagp third argument must be an immediate")((isa<ConstantSDNode>(N->getOperand(3)) && "llvm.aarch64.tagp third argument must be an immediate"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N->getOperand(3)) && \"llvm.aarch64.tagp third argument must be an immediate\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3270, __PRETTY_FUNCTION__));
if (trySelectStackSlotTagP(N))
  return;
// FIXME: above applies in any case when offset between Op1 and Op2 is a
// compile-time constant, not just for stack allocations.

// General case for unrelated pointers in Op1 and Op2.
SDLoc DL(N);
int TagOffset = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
SDNode *N1 = CurDAG->getMachineNode(AArch64::SUBP, DL, MVT::i64,
                                    {N->getOperand(1), N->getOperand(2)});
SDNode *N2 = CurDAG->getMachineNode(AArch64::ADDXrr, DL, MVT::i64,
                                    {SDValue(N1, 0), N->getOperand(2)});
SDNode *N3 = CurDAG->getMachineNode(
    AArch64::ADDG, DL, MVT::i64,
    {SDValue(N2, 0), CurDAG->getTargetConstant(0, DL, MVT::i64),
     CurDAG->getTargetConstant(TagOffset, DL, MVT::i64)});
ReplaceNode(N, N3);
3288}

3290// NOTE: We cannot use EXTRACT_SUBREG in all cases because the fixed length
3291// vector types larger than NEON don't have a matching SubRegIndex.
3292static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
assert(V.getValueType().isScalableVector() &&((V.getValueType().isScalableVector() && V.getValueType
().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock
 && "Expected to extract from a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isScalableVector() && V.getValueType().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to extract from a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3296, __PRETTY_FUNCTION__))
       V.getValueType().getSizeInBits().getKnownMinSize() ==((V.getValueType().isScalableVector() && V.getValueType
().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock
 && "Expected to extract from a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isScalableVector() && V.getValueType().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to extract from a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3296, __PRETTY_FUNCTION__))
           AArch64::SVEBitsPerBlock &&((V.getValueType().isScalableVector() && V.getValueType
().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock
 && "Expected to extract from a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isScalableVector() && V.getValueType().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to extract from a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3296, __PRETTY_FUNCTION__))
       "Expected to extract from a packed scalable vector!")((V.getValueType().isScalableVector() && V.getValueType
().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock
 && "Expected to extract from a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isScalableVector() && V.getValueType().getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to extract from a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3296, __PRETTY_FUNCTION__));
assert(VT.isFixedLengthVector() &&((VT.isFixedLengthVector() && "Expected to extract a fixed length vector!"
) ? static_cast<void> (0) : __assert_fail ("VT.isFixedLengthVector() && \"Expected to extract a fixed length vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3298, __PRETTY_FUNCTION__))
       "Expected to extract a fixed length vector!")((VT.isFixedLengthVector() && "Expected to extract a fixed length vector!"
) ? static_cast<void> (0) : __assert_fail ("VT.isFixedLengthVector() && \"Expected to extract a fixed length vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3298, __PRETTY_FUNCTION__));

SDLoc DL(V);
switch (VT.getSizeInBits()) {
case 64: {
  auto SubReg = DAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
  return DAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT, V, SubReg);
}
case 128: {
  auto SubReg = DAG->getTargetConstant(AArch64::zsub, DL, MVT::i32);
  return DAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT, V, SubReg);
}
default: {
  auto RC = DAG->getTargetConstant(AArch64::ZPRRegClassID, DL, MVT::i64);
  return DAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
}
}
3315}

3317// NOTE: We cannot use INSERT_SUBREG in all cases because the fixed length
3318// vector types larger than NEON don't have a matching SubRegIndex.
3319static SDNode *insertSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
assert(VT.isScalableVector() &&((VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize
() == AArch64::SVEBitsPerBlock && "Expected to insert into a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to insert into a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3322, __PRETTY_FUNCTION__))
       VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock &&((VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize
() == AArch64::SVEBitsPerBlock && "Expected to insert into a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to insert into a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3322, __PRETTY_FUNCTION__))
       "Expected to insert into a packed scalable vector!")((VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize
() == AArch64::SVEBitsPerBlock && "Expected to insert into a packed scalable vector!"
) ? static_cast<void> (0) : __assert_fail ("VT.isScalableVector() && VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && \"Expected to insert into a packed scalable vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3322, __PRETTY_FUNCTION__));
assert(V.getValueType().isFixedLengthVector() &&((V.getValueType().isFixedLengthVector() && "Expected to insert a fixed length vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isFixedLengthVector() && \"Expected to insert a fixed length vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3324, __PRETTY_FUNCTION__))
       "Expected to insert a fixed length vector!")((V.getValueType().isFixedLengthVector() && "Expected to insert a fixed length vector!"
) ? static_cast<void> (0) : __assert_fail ("V.getValueType().isFixedLengthVector() && \"Expected to insert a fixed length vector!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 3324, __PRETTY_FUNCTION__));

SDLoc DL(V);
switch (V.getValueType().getSizeInBits()) {
case 64: {
  auto SubReg = DAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
  auto Container = DAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
  return DAG->getMachineNode(TargetOpcode::INSERT_SUBREG, DL, VT,
                             SDValue(Container, 0), V, SubReg);
}
case 128: {
  auto SubReg = DAG->getTargetConstant(AArch64::zsub, DL, MVT::i32);
  auto Container = DAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
  return DAG->getMachineNode(TargetOpcode::INSERT_SUBREG, DL, VT,
                             SDValue(Container, 0), V, SubReg);
}
default: {
  auto RC = DAG->getTargetConstant(AArch64::ZPRRegClassID, DL, MVT::i64);
  return DAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
}
}
3345}

3347void AArch64DAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
  LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-isel")) { errs() << "== "; Node->dump(CurDAG
); errs() << "\n"; } } while (false);
  Node->setNodeId(-1);
  return;
}

// Few custom selection stuff.
EVT VT = Node->getValueType(0);

switch (Node->getOpcode()) {
default:
  break;

case ISD::ATOMIC_CMP_SWAP:
  if (SelectCMP_SWAP(Node))
    return;
  break;

case ISD::READ_REGISTER:
  if (tryReadRegister(Node))
    return;
  break;

case ISD::WRITE_REGISTER:
  if (tryWriteRegister(Node))
    return;
  break;

case ISD::ADD:
  if (tryMLAV64LaneV128(Node))
    return;
  break;

case ISD::LOAD: {
  // Try to select as an indexed load. Fall through to normal processing
  // if we can't.
  if (tryIndexedLoad(Node))
    return;
  break;
}

case ISD::SRL:
case ISD::AND:
case ISD::SRA:
case ISD::SIGN_EXTEND_INREG:
  if (tryBitfieldExtractOp(Node))
    return;
  if (tryBitfieldInsertInZeroOp(Node))
    return;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ISD::ROTR:
case ISD::SHL:
  if (tryShiftAmountMod(Node))
    return;
  break;

case ISD::SIGN_EXTEND:
  if (tryBitfieldExtractOpFromSExt(Node))
    return;
  break;

case ISD::FP_EXTEND:
  if (tryHighFPExt(Node))
    return;
  break;

case ISD::OR:
  if (tryBitfieldInsertOp(Node))
    return;
  break;

case ISD::EXTRACT_SUBVECTOR: {
  // Bail when not a "cast" like extract_subvector.
  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue() != 0)
    break;

  // Bail when normal isel can do the job.
  EVT InVT = Node->getOperand(0).getValueType();
  if (VT.isScalableVector() || InVT.isFixedLengthVector())
    break;

  // NOTE: We can only get here when doing fixed length SVE code generation.
  // We do manual selection because the types involved are not linked to real
  // registers (despite being legal) and must be coerced into SVE registers.
  //
  // NOTE: If the above changes, be aware that selection will still not work
  // because the td definition of extract_vector does not support extracting
  // a fixed length vector from a scalable vector.

  ReplaceNode(Node, extractSubReg(CurDAG, VT, Node->getOperand(0)));
  return;
}

case ISD::INSERT_SUBVECTOR: {
  // Bail when not a "cast" like insert_subvector.
  if (cast<ConstantSDNode>(Node->getOperand(2))->getZExtValue() != 0)
    break;
  if (!Node->getOperand(0).isUndef())
    break;

  // Bail when normal isel should do the job.
  EVT InVT = Node->getOperand(1).getValueType();
  if (VT.isFixedLengthVector() || InVT.isScalableVector())
    break;

  // NOTE: We can only get here when doing fixed length SVE code generation.
  // We do manual selection because the types involved are not linked to real
  // registers (despite being legal) and must be coerced into SVE registers.
  //
  // NOTE: If the above changes, be aware that selection will still not work
  // because the td definition of insert_vector does not support inserting a
  // fixed length vector into a scalable vector.

  ReplaceNode(Node, insertSubReg(CurDAG, VT, Node->getOperand(1)));
  return;
}

case ISD::Constant: {
  // Materialize zero constants as copies from WZR/XZR.  This allows
  // the coalescer to propagate these into other instructions.
  ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
  if (ConstNode->isNullValue()) {
    if (VT == MVT::i32) {
      SDValue New = CurDAG->getCopyFromReg(
          CurDAG->getEntryNode(), SDLoc(Node), AArch64::WZR, MVT::i32);
      ReplaceNode(Node, New.getNode());
      return;
    } else if (VT == MVT::i64) {
      SDValue New = CurDAG->getCopyFromReg(
          CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
      ReplaceNode(Node, New.getNode());
      return;
    }
  }
  break;
}

case ISD::FrameIndex: {
  // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
  int FI = cast<FrameIndexSDNode>(Node)->getIndex();
  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
  const TargetLowering *TLI = getTargetLowering();
  SDValue TFI = CurDAG->getTargetFrameIndex(
      FI, TLI->getPointerTy(CurDAG->getDataLayout()));
  SDLoc DL(Node);
  SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
                    CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
  CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
  return;
}
case ISD::INTRINSIC_W_CHAIN: {
  unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
  switch (IntNo) {
  default:
    break;
  case Intrinsic::aarch64_ldaxp:
  case Intrinsic::aarch64_ldxp: {
    unsigned Op =
        IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
    SDValue MemAddr = Node->getOperand(2);
    SDLoc DL(Node);
    SDValue Chain = Node->getOperand(0);

    SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
                                        MVT::Other, MemAddr, Chain);

    // Transfer memoperands.
    MachineMemOperand *MemOp =
        cast<MemIntrinsicSDNode>(Node)->getMemOperand();
    CurDAG->setNodeMemRefs(cast<MachineSDNode>(Ld), {MemOp});
    ReplaceNode(Node, Ld);
    return;
  }
  case Intrinsic::aarch64_stlxp:
  case Intrinsic::aarch64_stxp: {
    unsigned Op =
        IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
    SDLoc DL(Node);
    SDValue Chain = Node->getOperand(0);
    SDValue ValLo = Node->getOperand(2);
    SDValue ValHi = Node->getOperand(3);
    SDValue MemAddr = Node->getOperand(4);

    // Place arguments in the right order.
    SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};

    SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
    // Transfer memoperands.
    MachineMemOperand *MemOp =
        cast<MemIntrinsicSDNode>(Node)->getMemOperand();
    CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});

    ReplaceNode(Node, St);
    return;
  }
  case Intrinsic::aarch64_neon_ld1x2:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld1x3:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld1x4:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld2:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld3:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld4:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld2r:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld3r:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld4r:
    if (VT == MVT::v8i8) {
      SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
      return;
    } else if (VT == MVT::v16i8) {
      SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
      SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
      SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld2lane:
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectLoadLane(Node, 2, AArch64::LD2i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectLoadLane(Node, 2, AArch64::LD2i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectLoadLane(Node, 2, AArch64::LD2i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectLoadLane(Node, 2, AArch64::LD2i64);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld3lane:
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectLoadLane(Node, 3, AArch64::LD3i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectLoadLane(Node, 3, AArch64::LD3i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectLoadLane(Node, 3, AArch64::LD3i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectLoadLane(Node, 3, AArch64::LD3i64);
      return;
    }
    break;
  case Intrinsic::aarch64_neon_ld4lane:
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectLoadLane(Node, 4, AArch64::LD4i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectLoadLane(Node, 4, AArch64::LD4i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectLoadLane(Node, 4, AArch64::LD4i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectLoadLane(Node, 4, AArch64::LD4i64);
      return;
    }
    break;
  case Intrinsic::aarch64_ld64b:
    SelectLoad(Node, 8, AArch64::LD64B, AArch64::x8sub_0);
    return;
  }
} break;
case ISD::INTRINSIC_WO_CHAIN: {
  unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
  switch (IntNo) {
  default:
    break;
  case Intrinsic::aarch64_tagp:
    SelectTagP(Node);
    return;
  case Intrinsic::aarch64_neon_tbl2:
    SelectTable(Node, 2,
                VT == MVT::v8i8 ? AArch64::TBLv8i8Two : AArch64::TBLv16i8Two,
                false);
    return;
  case Intrinsic::aarch64_neon_tbl3:
    SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
                                         : AArch64::TBLv16i8Three,
                false);
    return;
  case Intrinsic::aarch64_neon_tbl4:
    SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
                                         : AArch64::TBLv16i8Four,
                false);
    return;
  case Intrinsic::aarch64_neon_tbx2:
    SelectTable(Node, 2,
                VT == MVT::v8i8 ? AArch64::TBXv8i8Two : AArch64::TBXv16i8Two,
                true);
    return;
  case Intrinsic::aarch64_neon_tbx3:
    SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
                                         : AArch64::TBXv16i8Three,
                true);
    return;
  case Intrinsic::aarch64_neon_tbx4:
    SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
                                         : AArch64::TBXv16i8Four,
                true);
    return;
  case Intrinsic::aarch64_neon_smull:
  case Intrinsic::aarch64_neon_umull:
    if (tryMULLV64LaneV128(IntNo, Node))
      return;
    break;
  }
  break;
}
case ISD::INTRINSIC_VOID: {
  unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
  if (Node->getNumOperands() >= 3)
    VT = Node->getOperand(2)->getValueType(0);
  switch (IntNo) {
  default:
    break;
  case Intrinsic::aarch64_neon_st1x2: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 2, AArch64::ST1Twov8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 2, AArch64::ST1Twov16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 2, AArch64::ST1Twov4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 2, AArch64::ST1Twov8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 2, AArch64::ST1Twov2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 2, AArch64::ST1Twov4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 2, AArch64::ST1Twov2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 2, AArch64::ST1Twov1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st1x3: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 3, AArch64::ST1Threev8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 3, AArch64::ST1Threev16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 3, AArch64::ST1Threev4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 3, AArch64::ST1Threev8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 3, AArch64::ST1Threev2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 3, AArch64::ST1Threev4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 3, AArch64::ST1Threev2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 3, AArch64::ST1Threev1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st1x4: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 4, AArch64::ST1Fourv8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 4, AArch64::ST1Fourv16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 4, AArch64::ST1Fourv4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 4, AArch64::ST1Fourv8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 4, AArch64::ST1Fourv2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 4, AArch64::ST1Fourv4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 4, AArch64::ST1Fourv2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 4, AArch64::ST1Fourv1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st2: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 2, AArch64::ST2Twov8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 2, AArch64::ST2Twov16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 2, AArch64::ST2Twov4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 2, AArch64::ST2Twov8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 2, AArch64::ST2Twov2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 2, AArch64::ST2Twov4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 2, AArch64::ST2Twov2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 2, AArch64::ST1Twov1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st3: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 3, AArch64::ST3Threev8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 3, AArch64::ST3Threev16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 3, AArch64::ST3Threev4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 3, AArch64::ST3Threev8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 3, AArch64::ST3Threev2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 3, AArch64::ST3Threev4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 3, AArch64::ST3Threev2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 3, AArch64::ST1Threev1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st4: {
    if (VT == MVT::v8i8) {
      SelectStore(Node, 4, AArch64::ST4Fourv8b);
      return;
    } else if (VT == MVT::v16i8) {
      SelectStore(Node, 4, AArch64::ST4Fourv16b);
      return;
    } else if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v4bf16) {
      SelectStore(Node, 4, AArch64::ST4Fourv4h);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v8f16 ||
               VT == MVT::v8bf16) {
      SelectStore(Node, 4, AArch64::ST4Fourv8h);
      return;
    } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
      SelectStore(Node, 4, AArch64::ST4Fourv2s);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
      SelectStore(Node, 4, AArch64::ST4Fourv4s);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
      SelectStore(Node, 4, AArch64::ST4Fourv2d);
      return;
    } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
      SelectStore(Node, 4, AArch64::ST1Fourv1d);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st2lane: {
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectStoreLane(Node, 2, AArch64::ST2i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectStoreLane(Node, 2, AArch64::ST2i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectStoreLane(Node, 2, AArch64::ST2i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectStoreLane(Node, 2, AArch64::ST2i64);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st3lane: {
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectStoreLane(Node, 3, AArch64::ST3i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectStoreLane(Node, 3, AArch64::ST3i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectStoreLane(Node, 3, AArch64::ST3i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectStoreLane(Node, 3, AArch64::ST3i64);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_neon_st4lane: {
    if (VT == MVT::v16i8 || VT == MVT::v8i8) {
      SelectStoreLane(Node, 4, AArch64::ST4i8);
      return;
    } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
               VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
      SelectStoreLane(Node, 4, AArch64::ST4i16);
      return;
    } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
               VT == MVT::v2f32) {
      SelectStoreLane(Node, 4, AArch64::ST4i32);
      return;
    } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
               VT == MVT::v1f64) {
      SelectStoreLane(Node, 4, AArch64::ST4i64);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_sve_st2: {
    if (VT == MVT::nxv16i8) {
      SelectPredicatedStore(Node, 2, 0, AArch64::ST2B, AArch64::ST2B_IMM);
      return;
    } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
               (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
      SelectPredicatedStore(Node, 2, 1, AArch64::ST2H, AArch64::ST2H_IMM);
      return;
    } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
      SelectPredicatedStore(Node, 2, 2, AArch64::ST2W, AArch64::ST2W_IMM);
      return;
    } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
      SelectPredicatedStore(Node, 2, 3, AArch64::ST2D, AArch64::ST2D_IMM);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_sve_st3: {
    if (VT == MVT::nxv16i8) {
      SelectPredicatedStore(Node, 3, 0, AArch64::ST3B, AArch64::ST3B_IMM);
      return;
    } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
               (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
      SelectPredicatedStore(Node, 3, 1, AArch64::ST3H, AArch64::ST3H_IMM);
      return;
    } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
      SelectPredicatedStore(Node, 3, 2, AArch64::ST3W, AArch64::ST3W_IMM);
      return;
    } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
      SelectPredicatedStore(Node, 3, 3, AArch64::ST3D, AArch64::ST3D_IMM);
      return;
    }
    break;
  }
  case Intrinsic::aarch64_sve_st4: {
    if (VT == MVT::nxv16i8) {
      SelectPredicatedStore(Node, 4, 0, AArch64::ST4B, AArch64::ST4B_IMM);
      return;
    } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
               (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
      SelectPredicatedStore(Node, 4, 1, AArch64::ST4H, AArch64::ST4H_IMM);
      return;
    } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
      SelectPredicatedStore(Node, 4, 2, AArch64::ST4W, AArch64::ST4W_IMM);
      return;
    } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
      SelectPredicatedStore(Node, 4, 3, AArch64::ST4D, AArch64::ST4D_IMM);
      return;
    }
    break;
  }
  }
  break;
}
case AArch64ISD::LD2post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD3post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD4post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD1x2post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD1x3post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD1x4post: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD1DUPpost: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD2DUPpost: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD3DUPpost: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD4DUPpost: {
  if (VT == MVT::v8i8) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16  || VT == MVT::v8bf16) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
    return;
  }
  break;
}
case AArch64ISD::LD1LANEpost: {
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
    return;
  }
  break;
}
case AArch64ISD::LD2LANEpost: {
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
    return;
  }
  break;
}
case AArch64ISD::LD3LANEpost: {
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
    return;
  }
  break;
}
case AArch64ISD::LD4LANEpost: {
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
    return;
  }
  break;
}
case AArch64ISD::ST2post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
    SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST3post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
    SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST4post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST1x2post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
    SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST1x3post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16 ) {
    SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST1x4post: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v8i8) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
    return;
  } else if (VT == MVT::v16i8) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
    return;
  } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
    return;
  } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
    return;
  } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
    return;
  }
  break;
}
case AArch64ISD::ST2LANEpost: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
    return;
  }
  break;
}
case AArch64ISD::ST3LANEpost: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
    return;
  }
  break;
}
case AArch64ISD::ST4LANEpost: {
  VT = Node->getOperand(1).getValueType();
  if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
    return;
  } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
             VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
    SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
    return;
  } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
             VT == MVT::v2f32) {
    SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
    return;
  } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
             VT == MVT::v1f64) {
    SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
    return;
  }
  break;
}
case AArch64ISD::SVE_LD2_MERGE_ZERO: {
  if (VT == MVT::nxv16i8) {
    SelectPredicatedLoad(Node, 2, 0, AArch64::LD2B_IMM, AArch64::LD2B);
    return;
  } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
             (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
    SelectPredicatedLoad(Node, 2, 1, AArch64::LD2H_IMM, AArch64::LD2H);
    return;
  } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
    SelectPredicatedLoad(Node, 2, 2, AArch64::LD2W_IMM, AArch64::LD2W);
    return;
  } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
    SelectPredicatedLoad(Node, 2, 3, AArch64::LD2D_IMM, AArch64::LD2D);
    return;
  }
  break;
}
case AArch64ISD::SVE_LD3_MERGE_ZERO: {
  if (VT == MVT::nxv16i8) {
    SelectPredicatedLoad(Node, 3, 0, AArch64::LD3B_IMM, AArch64::LD3B);
    return;
  } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
             (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
    SelectPredicatedLoad(Node, 3, 1, AArch64::LD3H_IMM, AArch64::LD3H);
    return;
  } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
    SelectPredicatedLoad(Node, 3, 2, AArch64::LD3W_IMM, AArch64::LD3W);
    return;
  } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
    SelectPredicatedLoad(Node, 3, 3, AArch64::LD3D_IMM, AArch64::LD3D);
    return;
  }
  break;
}
case AArch64ISD::SVE_LD4_MERGE_ZERO: {
  if (VT == MVT::nxv16i8) {
    SelectPredicatedLoad(Node, 4, 0, AArch64::LD4B_IMM, AArch64::LD4B);
    return;
  } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
             (VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
    SelectPredicatedLoad(Node, 4, 1, AArch64::LD4H_IMM, AArch64::LD4H);
    return;
  } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
    SelectPredicatedLoad(Node, 4, 2, AArch64::LD4W_IMM, AArch64::LD4W);
    return;
  } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
    SelectPredicatedLoad(Node, 4, 3, AArch64::LD4D_IMM, AArch64::LD4D);
    return;
  }
  break;
}
}

// Select the default instruction
SelectCode(Node);
4835}

4837/// createAArch64ISelDag - This pass converts a legalized DAG into a
4838/// AArch64-specific DAG, ready for instruction scheduling.
4839FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
                                       CodeGenOpt::Level OptLevel) {
return new AArch64DAGToDAGISel(TM, OptLevel);
4842}

4844/// When \p PredVT is a scalable vector predicate in the form
4845/// MVT::nx<M>xi1, it builds the correspondent scalable vector of
4846/// integers MVT::nx<M>xi<bits> s.t. M x bits = 128. When targeting
4847/// structured vectors (NumVec >1), the output data type is
4848/// MVT::nx<M*NumVec>xi<bits> s.t. M x bits = 128. If the input
4849/// PredVT is not in the form MVT::nx<M>xi1, it returns an invalid
4850/// EVT.
4851static EVT getPackedVectorTypeFromPredicateType(LLVMContext &Ctx, EVT PredVT,
                                              unsigned NumVec) {
assert(NumVec > 0 && NumVec < 5 && "Invalid number of vectors.")((NumVec > 0 && NumVec < 5 && "Invalid number of vectors."
) ? static_cast<void> (0) : __assert_fail ("NumVec > 0 && NumVec < 5 && \"Invalid number of vectors.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp"
, 4853, __PRETTY_FUNCTION__));
if (!PredVT.isScalableVector() || PredVT.getVectorElementType() != MVT::i1)
  return EVT();

if (PredVT != MVT::nxv16i1 && PredVT != MVT::nxv8i1 &&
    PredVT != MVT::nxv4i1 && PredVT != MVT::nxv2i1)
  return EVT();

ElementCount EC = PredVT.getVectorElementCount();
EVT ScalarVT =
    EVT::getIntegerVT(Ctx, AArch64::SVEBitsPerBlock / EC.getKnownMinValue());
EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC * NumVec);

return MemVT;
4867}

4869/// Return the EVT of the data associated to a memory operation in \p
4870/// Root. If such EVT cannot be retrived, it returns an invalid EVT.
4871static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
if (isa<MemSDNode>(Root))
  return cast<MemSDNode>(Root)->getMemoryVT();

if (isa<MemIntrinsicSDNode>(Root))
  return cast<MemIntrinsicSDNode>(Root)->getMemoryVT();

const unsigned Opcode = Root->getOpcode();
// For custom ISD nodes, we have to look at them individually to extract the
// type of the data moved to/from memory.
switch (Opcode) {
case AArch64ISD::LD1_MERGE_ZERO:
case AArch64ISD::LD1S_MERGE_ZERO:
case AArch64ISD::LDNF1_MERGE_ZERO:
case AArch64ISD::LDNF1S_MERGE_ZERO:
  return cast<VTSDNode>(Root->getOperand(3))->getVT();
case AArch64ISD::ST1_PRED:
  return cast<VTSDNode>(Root->getOperand(4))->getVT();
case AArch64ISD::SVE_LD2_MERGE_ZERO:
  return getPackedVectorTypeFromPredicateType(
      Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/2);
case AArch64ISD::SVE_LD3_MERGE_ZERO:
  return getPackedVectorTypeFromPredicateType(
      Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/3);
case AArch64ISD::SVE_LD4_MERGE_ZERO:
  return getPackedVectorTypeFromPredicateType(
      Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/4);
default:
  break;
}

if (Opcode != ISD::INTRINSIC_VOID)
  return EVT();

const unsigned IntNo =
    cast<ConstantSDNode>(Root->getOperand(1))->getZExtValue();
if (IntNo != Intrinsic::aarch64_sve_prf)
  return EVT();

// We are using an SVE prefetch intrinsic. Type must be inferred
// from the width of the predicate.
return getPackedVectorTypeFromPredicateType(
    Ctx, Root->getOperand(2)->getValueType(0), /*NumVec=*/1);
4914}

4916/// SelectAddrModeIndexedSVE - Attempt selection of the addressing mode:
4917/// Base + OffImm * sizeof(MemVT) for Min >= OffImm <= Max
4918/// where Root is the memory access using N for its address.
4919template <int64_t Min, int64_t Max>
4920bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
                                                 SDValue &Base,
                                                 SDValue &OffImm) {
const EVT MemVT = getMemVTFromNode(*(CurDAG->getContext()), Root);

if (MemVT == EVT())
  return false;

if (N.getOpcode() != ISD::ADD)
  return false;

SDValue VScale = N.getOperand(1);
if (VScale.getOpcode() != ISD::VSCALE)
  return false;

TypeSize TS = MemVT.getSizeInBits();
int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinSize()) / 8;
int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();

if ((MulImm % MemWidthBytes) != 0)
  return false;

int64_t Offset = MulImm / MemWidthBytes;
if (Offset < Min || Offset > Max)
  return false;

Base = N.getOperand(0);
OffImm = CurDAG->getTargetConstant(Offset, SDLoc(N), MVT::i64);
return true;
4949}

4951/// Select register plus register addressing mode for SVE, with scaled
4952/// offset.
4953bool AArch64DAGToDAGISel::SelectSVERegRegAddrMode(SDValue N, unsigned Scale,
                                                SDValue &Base,
                                                SDValue &Offset) {
if (N.getOpcode() != ISD::ADD)
  return false;

// Process an ADD node.
const SDValue LHS = N.getOperand(0);
const SDValue RHS = N.getOperand(1);

// 8 bit data does not come with the SHL node, so it is treated
// separately.
if (Scale == 0) {
  Base = LHS;
  Offset = RHS;
  return true;
}

// Check if the RHS is a shift node with a constant.
if (RHS.getOpcode() != ISD::SHL)
  return false;

const SDValue ShiftRHS = RHS.getOperand(1);
if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS))
  if (C->getZExtValue() == Scale) {
    Base = LHS;
    Offset = RHS.getOperand(0);
    return true;
  }

return false;
4984}

←

/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG.  These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//

18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H

21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>

57namespace llvm {

59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;

72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
                  bool force = false);

75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG.  Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
const EVT *VTs;
unsigned int NumVTs;
82};

84namespace ISD {

/// Node predicates

88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);

93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
                                bool BuildVectorOnly = false);

99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
                                 bool BuildVectorOnly = false);

105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);

109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);

113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);

117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);

121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);

125} // end namespace ISD

127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation.  Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node.  This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
friend struct DenseMapInfo<SDValue>;

SDNode *Node = nullptr; // The node defining the value we are using.
unsigned ResNo = 0;     // Which return value of the node we are using.

144public:
SDValue() = default;
SDValue(SDNode *node, unsigned resno);

/// get the index which selects a specific result in the SDNode
unsigned getResNo() const { return ResNo; }

/// get the SDNode which holds the desired result
SDNode *getNode() const { return Node; }

/// set the SDNode
void setNode(SDNode *N) { Node = N; }

inline SDNode *operator->() const { return Node; }

bool operator==(const SDValue &O) const {
  return Node == O.Node && ResNo == O.ResNo;
}
bool operator!=(const SDValue &O) const {
  return !operator==(O);
}
bool operator<(const SDValue &O) const {
  return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
}
explicit operator bool() const {
  return Node != nullptr;
}

SDValue getValue(unsigned R) const {
  return SDValue(Node, R);
}

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return the ValueType of the referenced return value.
inline EVT getValueType() const;

/// Return the simple ValueType of the referenced return value.
MVT getSimpleValueType() const {
  return getValueType().getSimpleVT();
}

/// Returns the size of the value in bits.
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits() const {
  return getValueType().getSizeInBits();
}

uint64_t getScalarValueSizeInBits() const {
  return getValueType().getScalarType().getFixedSizeInBits();
}

// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
inline unsigned getMachineOpcode() const;
inline const DebugLoc &getDebugLoc() const;
inline void dump() const;
inline void dump(const SelectionDAG *G) const;
inline void dumpr() const;
inline void dumpr(const SelectionDAG *G) const;

/// Return true if this operand (which must be a chain) reaches the
/// specified operand without crossing any side-effecting instructions.
/// In practice, this looks through token factors and non-volatile loads.
/// In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest,
                                    unsigned Depth = 2) const;

/// Return true if there are no nodes using value ResNo of Node.
inline bool use_empty() const;

/// Return true if there is exactly one node using value ResNo of Node.
inline bool hasOneUse() const;
230};

232template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
  SDValue V;
  V.ResNo = -1U;
  return V;
}

static inline SDValue getTombstoneKey() {
  SDValue V;
  V.ResNo = -2U;
  return V;
}

static unsigned getHashValue(const SDValue &Val) {
  return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
          (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
}

static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
  return LHS == RHS;
}
253};

255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDValue &Val) {
  return Val.getNode();
}
263};
264template<> struct simplify_type<const SDValue> {
using SimpleType = /*const*/ SDNode *;

static SimpleType getSimplifiedValue(const SDValue &Val) {
  return Val.getNode();
}
270};

272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
/// Val - The value being used.
SDValue Val;
/// User - The user of this value.
SDNode *User = nullptr;
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev = nullptr;
SDUse *Next = nullptr;

287public:
SDUse() = default;
SDUse(const SDUse &U) = delete;
SDUse &operator=(const SDUse &) = delete;

/// Normally SDUse will just implicitly convert to an SDValue that it holds.
operator const SDValue&() const { return Val; }

/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }

/// This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }

/// Get the next SDUse in the use list.
SDUse *getNext() const { return Next; }

/// Convenience function for get().getNode().
SDNode *getNode() const { return Val.getNode(); }
/// Convenience function for get().getResNo().
unsigned getResNo() const { return Val.getResNo(); }
/// Convenience function for get().getValueType().
EVT getValueType() const { return Val.getValueType(); }

/// Convenience function for get().operator==
bool operator==(const SDValue &V) const {
  return Val == V;
}

/// Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
  return Val != V;
}

/// Convenience function for get().operator<
bool operator<(const SDValue &V) const {
  return Val < V;
}

327private:
friend class SelectionDAG;
friend class SDNode;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

void setUser(SDNode *p) { User = p; }

/// Remove this use from its existing use list, assign it the
/// given value, and add it to the new value's node's use list.
inline void set(const SDValue &V);
/// Like set, but only supports initializing a newly-allocated
/// SDUse with a non-null value.
inline void setInitial(const SDValue &V);
/// Like set, but only sets the Node portion of the value,
/// leaving the ResNo portion unmodified.
inline void setNode(SDNode *N);

void addToList(SDUse **List) {
  Next = *List;
  if (Next) Next->Prev = &Next;
  Prev = List;
  *List = this;
}

void removeFromList() {
  *Prev = Next;
  if (Next) Next->Prev = Prev;
}
356};

358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDUse &Val) {
  return Val.getNode();
}
366};

368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
bool NoUnsignedWrap : 1;
bool NoSignedWrap : 1;
bool Exact : 1;
bool NoNaNs : 1;
bool NoInfs : 1;
bool NoSignedZeros : 1;
bool AllowReciprocal : 1;
bool AllowContract : 1;
bool ApproximateFuncs : 1;
bool AllowReassociation : 1;

// We assume instructions do not raise floating-point exceptions by default,
// and only those marked explicitly may do so.  We could choose to represent
// this via a positive "FPExcept" flags like on the MI level, but having a
// negative "NoFPExcept" flag here (that defaults to true) makes the flag
// intersection logic more straightforward.
bool NoFPExcept : 1;

391public:
/// Default constructor turns off all optimization flags.
SDNodeFlags()
    : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
      NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
      AllowContract(false), ApproximateFuncs(false),
      AllowReassociation(false), NoFPExcept(false) {}

/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
  setNoNaNs(FPMO.hasNoNaNs());
  setNoInfs(FPMO.hasNoInfs());
  setNoSignedZeros(FPMO.hasNoSignedZeros());
  setAllowReciprocal(FPMO.hasAllowReciprocal());
  setAllowContract(FPMO.hasAllowContract());
  setApproximateFuncs(FPMO.hasApproxFunc());
  setAllowReassociation(FPMO.hasAllowReassoc());
}

// These are mutators for each flag.
void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
void setNoSignedWrap(bool b) { NoSignedWrap = b; }
void setExact(bool b) { Exact = b; }
void setNoNaNs(bool b) { NoNaNs = b; }
void setNoInfs(bool b) { NoInfs = b; }
void setNoSignedZeros(bool b) { NoSignedZeros = b; }
void setAllowReciprocal(bool b) { AllowReciprocal = b; }
void setAllowContract(bool b) { AllowContract = b; }
void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
void setAllowReassociation(bool b) { AllowReassociation = b; }
void setNoFPExcept(bool b) { NoFPExcept = b; }

// These are accessors for each flag.
bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
bool hasNoSignedWrap() const { return NoSignedWrap; }
bool hasExact() const { return Exact; }
bool hasNoNaNs() const { return NoNaNs; }
bool hasNoInfs() const { return NoInfs; }
bool hasNoSignedZeros() const { return NoSignedZeros; }
bool hasAllowReciprocal() const { return AllowReciprocal; }
bool hasAllowContract() const { return AllowContract; }
bool hasApproximateFuncs() const { return ApproximateFuncs; }
bool hasAllowReassociation() const { return AllowReassociation; }
bool hasNoFPExcept() const { return NoFPExcept; }

/// Clear any flags in this flag set that aren't also set in Flags. All
/// flags will be cleared if Flags are undefined.
void intersectWith(const SDNodeFlags Flags) {
  NoUnsignedWrap &= Flags.NoUnsignedWrap;
  NoSignedWrap &= Flags.NoSignedWrap;
  Exact &= Flags.Exact;
  NoNaNs &= Flags.NoNaNs;
  NoInfs &= Flags.NoInfs;
  NoSignedZeros &= Flags.NoSignedZeros;
  AllowReciprocal &= Flags.AllowReciprocal;
  AllowContract &= Flags.AllowContract;
  ApproximateFuncs &= Flags.ApproximateFuncs;
  AllowReassociation &= Flags.AllowReassociation;
  NoFPExcept &= Flags.NoFPExcept;
}
451};

453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
/// The operation that this node performs.
int16_t NodeType;

460protected:
// We define a set of mini-helper classes to help us interpret the bits in our
// SubclassData.  These are designed to fit within a uint16_t so they pack
// with NodeType.

465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif

475BEGIN_TWO_BYTE_PACK()
class SDNodeBitfields {
  friend class SDNode;
  friend class MemIntrinsicSDNode;
  friend class MemSDNode;
  friend class SelectionDAG;

  uint16_t HasDebugValue : 1;
  uint16_t IsMemIntrinsic : 1;
  uint16_t IsDivergent : 1;
};
enum { NumSDNodeBits = 3 };

class ConstantSDNodeBitfields {
  friend class ConstantSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsOpaque : 1;
};

class MemSDNodeBitfields {
  friend class MemSDNode;
  friend class MemIntrinsicSDNode;
  friend class AtomicSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsVolatile : 1;
  uint16_t IsNonTemporal : 1;
  uint16_t IsDereferenceable : 1;
  uint16_t IsInvariant : 1;
};
enum { NumMemSDNodeBits = NumSDNodeBits + 4 };

class LSBaseSDNodeBitfields {
  friend class LSBaseSDNode;
  friend class MaskedLoadStoreSDNode;
  friend class MaskedGatherScatterSDNode;

  uint16_t : NumMemSDNodeBits;

  // This storage is shared between disparate class hierarchies to hold an
  // enumeration specific to the class hierarchy in use.
  //   LSBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedGatherScatterSDNode => enum ISD::MemIndexType
  uint16_t AddressingMode : 3;
};
enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };

class LoadSDNodeBitfields {
  friend class LoadSDNode;
  friend class MaskedLoadSDNode;
  friend class MaskedGatherSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t ExtTy : 2; // enum ISD::LoadExtType
  uint16_t IsExpanding : 1;
};

class StoreSDNodeBitfields {
  friend class StoreSDNode;
  friend class MaskedStoreSDNode;
  friend class MaskedScatterSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t IsTruncating : 1;
  uint16_t IsCompressing : 1;
};

union {
  char RawSDNodeBits[sizeof(uint16_t)];
  SDNodeBitfields SDNodeBits;
  ConstantSDNodeBitfields ConstantSDNodeBits;
  MemSDNodeBitfields MemSDNodeBits;
  LSBaseSDNodeBitfields LSBaseSDNodeBits;
  LoadSDNodeBitfields LoadSDNodeBits;
  StoreSDNodeBitfields StoreSDNodeBits;
};
557END_TWO_BYTE_PACK()
558#undef BEGIN_TWO_BYTE_PACK
559#undef END_TWO_BYTE_PACK

// RawSDNodeBits must cover the entirety of the union.  This means that all of
// the union's members must have size <= RawSDNodeBits.  We write the RHS as
// "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");

571private:
friend class SelectionDAG;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

/// Unique id per SDNode in the DAG.
int NodeId = -1;

/// The values that are used by this operation.
SDUse *OperandList = nullptr;

/// The types of the values this node defines.  SDNode's may
/// define multiple values simultaneously.
const EVT *ValueList;

/// List of uses for this SDNode.
SDUse *UseList = nullptr;

/// The number of entries in the Operand/Value list.
unsigned short NumOperands = 0;
unsigned short NumValues;

// The ordering of the SDNodes. It roughly corresponds to the ordering of the
// original LLVM instructions.
// This is used for turning off scheduling, because we'll forgo
// the normal scheduling algorithms and output the instructions according to
// this ordering.
unsigned IROrder;

/// Source line information.
DebugLoc debugLoc;

/// Return a pointer to the specified value type.
static const EVT *getValueTypeList(EVT VT);

SDNodeFlags Flags;

608public:
/// Unique and persistent id per SDNode in the DAG.
/// Used for debug printing.
uint16_t PersistentId;

//===--------------------------------------------------------------------===//
//  Accessors
//

/// Return the SelectionDAG opcode value for this node. For
/// pre-isel nodes (those for which isMachineOpcode returns false), these
/// are the opcode values in the ISD and <target>ISD namespaces. For
/// post-isel opcodes, see getMachineOpcode.
unsigned getOpcode()  const { return (unsigned short)NodeType; }

/// Test if this node has a target-specific opcode (in the
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }

/// Test if this node has a target-specific opcode that may raise
/// FP exceptions (in the \<target\>ISD namespace and greater than
/// FIRST_TARGET_STRICTFP_OPCODE).  Note that all target memory
/// opcode are currently automatically considered to possibly raise
/// FP exceptions as well.
bool isTargetStrictFPOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
}

/// Test if this node has a target-specific
/// memory-referencing opcode (in the \<target\>ISD namespace and
/// greater than FIRST_TARGET_MEMORY_OPCODE).
bool isTargetMemoryOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
}

/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }

/// Test if this node is a memory intrinsic (with valid pointer information).
/// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
/// non-memory intrinsics (with chains) that are not really instances of
/// MemSDNode. For such nodes, we need some extra state to determine the
/// proper classof relationship.
bool isMemIntrinsic() const {
  return (NodeType == ISD::INTRINSIC_W_CHAIN ||
          NodeType == ISD::INTRINSIC_VOID) &&
         SDNodeBits.IsMemIntrinsic;
}

/// Test if this node is a strict floating point pseudo-op.
bool isStrictFPOpcode() {
  switch (NodeType) {
    default:
      return false;
    case ISD::STRICT_FP16_TO_FP:
    case ISD::STRICT_FP_TO_FP16:
664#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
    case ISD::STRICT_##DAGN:
666#include "llvm/IR/ConstrainedOps.def"
      return true;
  }
}

/// Test if this node has a post-isel opcode, directly
/// corresponding to a MachineInstr opcode.
bool isMachineOpcode() const { return NodeType < 0; }

/// This may only be called if isMachineOpcode returns
/// true. It returns the MachineInstr opcode value that the node's opcode
/// corresponds to.
unsigned getMachineOpcode() const {
  assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
 static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 679, __PRETTY_FUNCTION__));
  return ~NodeType;
}

bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }

bool isDivergent() const { return SDNodeBits.IsDivergent; }

/// Return true if there are no uses of this node.
bool use_empty() const { return UseList == nullptr; }

/// Return true if there is exactly one use of this node.
bool hasOneUse() const { return hasSingleElement(uses()); }

/// Return the number of uses of this node. This method takes
/// time proportional to the number of uses.
size_t use_size() const { return std::distance(use_begin(), use_end()); }

/// Return the unique node id.
int getNodeId() const { return NodeId; }

/// Set unique node id.
void setNodeId(int Id) { NodeId = Id; }

/// Return the node ordering.
unsigned getIROrder() const { return IROrder; }

/// Set the node ordering.
void setIROrder(unsigned Order) { IROrder = Order; }

/// Return the source location info.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Set source location info.  Try to avoid this, putting
/// it in the constructor is preferable.
void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }

/// This class provides iterator support for SDUse
/// operands that use a specific SDNode.
class use_iterator {
  friend class SDNode;

  SDUse *Op = nullptr;

  explicit use_iterator(SDUse *op) : Op(op) {}

public:
  using iterator_category = std::forward_iterator_tag;
  using value_type = SDUse;
  using difference_type = std::ptrdiff_t;
  using pointer = value_type *;
  using reference = value_type &;

  use_iterator() = default;
  use_iterator(const use_iterator &I) : Op(I.Op) {}

  bool operator==(const use_iterator &x) const {
    return Op == x.Op;
  }
  bool operator!=(const use_iterator &x) const {
    return !operator==(x);
  }

  /// Return true if this iterator is at the end of uses list.
  bool atEnd() const { return Op == nullptr; }

  // Iterator traversal: forward iteration only.
  use_iterator &operator++() {          // Preincrement
    assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 748, __PRETTY_FUNCTION__));
    Op = Op->getNext();
    return *this;
  }

  use_iterator operator++(int) {        // Postincrement
    use_iterator tmp = *this; ++*this; return tmp;
  }

  /// Retrieve a pointer to the current user node.
  SDNode *operator*() const {
    assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 759, __PRETTY_FUNCTION__));
    return Op->getUser();
  }

  SDNode *operator->() const { return operator*(); }

  SDUse &getUse() const { return *Op; }

  /// Retrieve the operand # of this use in its user.
  unsigned getOperandNo() const {
    assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 769, __PRETTY_FUNCTION__));
    return (unsigned)(Op - Op->getUser()->OperandList);
  }
};

/// Provide iteration support to walk over all uses of an SDNode.
use_iterator use_begin() const {
  return use_iterator(UseList);
}

static use_iterator use_end() { return use_iterator(nullptr); }

inline iterator_range<use_iterator> uses() {
  return make_range(use_begin(), use_end());
}
inline iterator_range<use_iterator> uses() const {
  return make_range(use_begin(), use_end());
}

/// Return true if there are exactly NUSES uses of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;

/// Return true if there are any use of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasAnyUseOfValue(unsigned Value) const;

/// Return true if this node is the only use of N.
bool isOnlyUserOf(const SDNode *N) const;

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return true if this node is a predecessor of N.
/// NOTE: Implemented on top of hasPredecessor and every bit as
/// expensive. Use carefully.
bool isPredecessorOf(const SDNode *N) const {
  return N->hasPredecessor(this);
}

/// Return true if N is a predecessor of this node.
/// N is either an operand of this node, or can be reached by recursively
/// traversing up the operands.
/// NOTE: This is an expensive method. Use it carefully.
bool hasPredecessor(const SDNode *N) const;

/// Returns true if N is a predecessor of any node in Worklist. This
/// helper keeps Visited and Worklist sets externally to allow unions
/// searches to be performed in parallel, caching of results across
/// queries and incremental addition to Worklist. Stops early if N is
/// found but will resume. Remember to clear Visited and Worklists
/// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
/// giving up. The TopologicalPrune flag signals that positive NodeIds are
/// topologically ordered (Operands have strictly smaller node id) and search
/// can be pruned leveraging this.
static bool hasPredecessorHelper(const SDNode *N,
                                 SmallPtrSetImpl<const SDNode *> &Visited,
                                 SmallVectorImpl<const SDNode *> &Worklist,
                                 unsigned int MaxSteps = 0,
                                 bool TopologicalPrune = false) {
  SmallVector<const SDNode *, 8> DeferredNodes;
  if (Visited.count(N))
    return true;

  // Node Id's are assigned in three places: As a topological
  // ordering (> 0), during legalization (results in values set to
  // 0), new nodes (set to -1). If N has a topolgical id then we
  // know that all nodes with ids smaller than it cannot be
  // successors and we need not check them. Filter out all node
  // that can't be matches. We add them to the worklist before exit
  // in case of multiple calls. Note that during selection the topological id
  // may be violated if a node's predecessor is selected before it. We mark
  // this at selection negating the id of unselected successors and
  // restricting topological pruning to positive ids.

  int NId = N->getNodeId();
  // If we Invalidated the Id, reconstruct original NId.
  if (NId < -1)
    NId = -(NId + 1);

  bool Found = false;
  while (!Worklist.empty()) {
    const SDNode *M = Worklist.pop_back_val();
    int MId = M->getNodeId();
    if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
        (MId > 0) && (MId < NId)) {
      DeferredNodes.push_back(M);
      continue;
    }
    for (const SDValue &OpV : M->op_values()) {
      SDNode *Op = OpV.getNode();
      if (Visited.insert(Op).second)
        Worklist.push_back(Op);
      if (Op == N)
        Found = true;
    }
    if (Found)
      break;
    if (MaxSteps != 0 && Visited.size() >= MaxSteps)
      break;
  }
  // Push deferred nodes back on worklist.
  Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
  // If we bailed early, conservatively return found.
  if (MaxSteps != 0 && Visited.size() >= MaxSteps)
    return true;
  return Found;
}

/// Return true if all the users of N are contained in Nodes.
/// NOTE: Requires at least one match, but doesn't require them all.
static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);

/// Return the number of values used by this operation.
unsigned getNumOperands() const { return NumOperands; }

/// Return the maximum number of operands that a SDNode can hold.
static constexpr size_t getMaxNumOperands() {
  return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
}

/// Helper method returns the integer value of a ConstantSDNode operand.
inline uint64_t getConstantOperandVal(unsigned Num) const;

/// Helper method returns the APInt of a ConstantSDNode operand.
inline const APInt &getConstantOperandAPInt(unsigned Num) const;

const SDValue &getOperand(unsigned Num) const {
  assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 897, __PRETTY_FUNCTION__));
  return OperandList[Num];
}

using op_iterator = SDUse *;

op_iterator op_begin() const { return OperandList; }
op_iterator op_end() const { return OperandList+NumOperands; }
ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }

/// Iterator for directly iterating over the operand SDValue's.
struct value_op_iterator
    : iterator_adaptor_base<value_op_iterator, op_iterator,
                            std::random_access_iterator_tag, SDValue,
                            ptrdiff_t, value_op_iterator *,
                            value_op_iterator *> {
  explicit value_op_iterator(SDUse *U = nullptr)
    : iterator_adaptor_base(U) {}

  const SDValue &operator*() const { return I->get(); }
};

iterator_range<value_op_iterator> op_values() const {
  return make_range(value_op_iterator(op_begin()),
                    value_op_iterator(op_end()));
}

SDVTList getVTList() const {
  SDVTList X = { ValueList, NumValues };
  return X;
}

/// If this node has a glue operand, return the node
/// to which the glue operand points. Otherwise return NULL.
SDNode *getGluedNode() const {
  if (getNumOperands() != 0 &&
      getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
    return getOperand(getNumOperands()-1).getNode();
  return nullptr;
}

/// If this node has a glue value with a user, return
/// the user (there is at most one). Otherwise return NULL.
SDNode *getGluedUser() const {
  for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
    if (UI.getUse().get().getValueType() == MVT::Glue)
      return *UI;
  return nullptr;
}

SDNodeFlags getFlags() const { return Flags; }
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }

/// Clear any flags in this node that aren't also set in Flags.
/// If Flags is not in a defined state then this has no effect.
void intersectFlagsWith(const SDNodeFlags Flags);

/// Return the number of values defined/returned by this operator.
unsigned getNumValues() const { return NumValues; }

/// Return the type of a specified result.
EVT getValueType(unsigned ResNo) const {
  assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
 static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 959, __PRETTY_FUNCTION__));
  return ValueList[ResNo];
}

/// Return the type of a specified result as a simple type.
MVT getSimpleValueType(unsigned ResNo) const {
  return getValueType(ResNo).getSimpleVT();
}

/// Returns MVT::getSizeInBits(getValueType(ResNo)).
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits(unsigned ResNo) const {
  return getValueType(ResNo).getSizeInBits();
}

using value_iterator = const EVT *;

value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }
iterator_range<value_iterator> values() const {
  return llvm::make_range(value_begin(), value_end());
}

/// Return the opcode of this operation for printing.
std::string getOperationName(const SelectionDAG *G = nullptr) const;
static const char* getIndexedModeName(ISD::MemIndexedMode AM);
void print_types(raw_ostream &OS, const SelectionDAG *G) const;
void print_details(raw_ostream &OS, const SelectionDAG *G) const;
void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and all children down to
/// the leaves.  The given SelectionDAG allows target-specific nodes
/// to be printed in human-readable form.  Unlike printr, this will
/// print the whole DAG, including children that appear multiple
/// times.
///
void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and children up to
/// depth "depth."  The given SelectionDAG allows target-specific
/// nodes to be printed in human-readable form.  Unlike printr, this
/// will print children that appear multiple times wherever they are
/// used.
///
void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
                     unsigned depth = 100) const;

/// Dump this node, for debugging.
void dump() const;

/// Dump (recursively) this node and its use-def subgraph.
void dumpr() const;

/// Dump this node, for debugging.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dump(const SelectionDAG *G) const;

/// Dump (recursively) this node and its use-def subgraph.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dumpr(const SelectionDAG *G) const;

/// printrFull to dbgs().  The given SelectionDAG allows
/// target-specific nodes to be printed in human-readable form.
/// Unlike dumpr, this will print the whole DAG, including children
/// that appear multiple times.
void dumprFull(const SelectionDAG *G = nullptr) const;

/// printrWithDepth to dbgs().  The given
/// SelectionDAG allows target-specific nodes to be printed in
/// human-readable form.  Unlike dumpr, this will print children
/// that appear multiple times wherever they are used.
///
void dumprWithDepth(const SelectionDAG *G = nullptr,
                    unsigned depth = 100) const;

/// Gather unique data for the node.
void Profile(FoldingSetNodeID &ID) const;

/// This method should only be used by the SDUse class.
void addUse(SDUse &U) { U.addToList(&UseList); }

1046protected:
static SDVTList getSDVTList(EVT VT) {
  SDVTList Ret = { getValueTypeList(VT), 1 };
  return Ret;
}

/// Create an SDNode.
///
/// SDNodes are created without any operands, and never own the operand
/// storage. To add operands, see SelectionDAG::createOperands.
SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
    : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
      IROrder(Order), debugLoc(std::move(dl)) {
  memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1060, __PRETTY_FUNCTION__));
  assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __PRETTY_FUNCTION__))
         "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __PRETTY_FUNCTION__));
}

/// Release the operands and set this node to have zero operands.
void DropOperands();
1067};

1069/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1070/// into SDNode creation functions.
1071/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1072/// from the original Instruction, and IROrder is the ordinal position of
1073/// the instruction.
1074/// When an SDNode is created after the DAG is being built, both DebugLoc and
1075/// the IROrder are propagated from the original SDNode.
1076/// So SDLoc class provides two constructors besides the default one, one to
1077/// be used by the DAGBuilder, the other to be used by others.
1078class SDLoc {
1079private:
DebugLoc DL;
int IROrder = 0;

1083public:
SDLoc() = default;
SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
SDLoc(const Instruction *I, int Order) : IROrder(Order) {
  assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1088, __PRETTY_FUNCTION__));
  if (I)
    DL = I->getDebugLoc();
}

unsigned getIROrder() const { return IROrder; }
const DebugLoc &getDebugLoc() const { return DL; }
1095};

1097// Define inline functions from the SDValue class.

1099inline SDValue::SDValue(SDNode *node, unsigned resno)
  : Node(node), ResNo(resno) {
// Explicitly check for !ResNo to avoid use-after-free, because there are
// callers that use SDValue(N, 0) with a deleted N to indicate successful
// combines.
assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
 "Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __PRETTY_FUNCTION__))
       "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
 "Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __PRETTY_FUNCTION__));
assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1106, __PRETTY_FUNCTION__));
1107}

1109inline unsigned SDValue::getOpcode() const {
return Node->getOpcode();
1111}

1113inline EVT SDValue::getValueType() const {
return Node->getValueType(ResNo);
9
←
Called C++ object pointer is null
1115}

1117inline unsigned SDValue::getNumOperands() const {
return Node->getNumOperands();
1119}

1121inline const SDValue &SDValue::getOperand(unsigned i) const {
return Node->getOperand(i);
1123}

1125inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Node->getConstantOperandVal(i);
1127}

1129inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
return Node->getConstantOperandAPInt(i);
1131}

1133inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
1135}

1137inline bool SDValue::isTargetMemoryOpcode() const {
return Node->isTargetMemoryOpcode();
1139}

1141inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
1143}

1145inline unsigned SDValue::getMachineOpcode() const {
return Node->getMachineOpcode();
1147}

1149inline bool SDValue::isUndef() const {
return Node->isUndef();
1151}

1153inline bool SDValue::use_empty() const {
return !Node->hasAnyUseOfValue(ResNo);
1155}

1157inline bool SDValue::hasOneUse() const {
return Node->hasNUsesOfValue(1, ResNo);
1159}

1161inline const DebugLoc &SDValue::getDebugLoc() const {
return Node->getDebugLoc();
1163}

1165inline void SDValue::dump() const {
return Node->dump();
1167}

1169inline void SDValue::dump(const SelectionDAG *G) const {
return Node->dump(G);
1171}

1173inline void SDValue::dumpr() const {
return Node->dumpr();
1175}

1177inline void SDValue::dumpr(const SelectionDAG *G) const {
return Node->dumpr(G);
1179}

1181// Define inline functions from the SDUse class.

1183inline void SDUse::set(const SDValue &V) {
if (Val.getNode()) removeFromList();
Val = V;
if (V.getNode()) V.getNode()->addUse(*this);
1187}

1189inline void SDUse::setInitial(const SDValue &V) {
Val = V;
V.getNode()->addUse(*this);
1192}

1194inline void SDUse::setNode(SDNode *N) {
if (Val.getNode()) removeFromList();
Val.setNode(N);
if (N) N->addUse(*this);
1198}

1200/// This class is used to form a handle around another node that
1201/// is persistent and is updated across invocations of replaceAllUsesWith on its
1202/// operand.  This node should be directly created by end-users and not added to
1203/// the AllNodes list.
1204class HandleSDNode : public SDNode {
SDUse Op;

1207public:
explicit HandleSDNode(SDValue X)
  : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
  // HandleSDNodes are never inserted into the DAG, so they won't be
  // auto-numbered. Use ID 65535 as a sentinel.
  PersistentId = 0xffff;

  // Manually set up the operand list. This node type is special in that it's
  // always stack allocated and SelectionDAG does not manage its operands.
  // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
  // be so special.
  Op.setUser(this);
  Op.setInitial(X);
  NumOperands = 1;
  OperandList = &Op;
}
~HandleSDNode();

const SDValue &getValue() const { return Op; }
1226};

1228class AddrSpaceCastSDNode : public SDNode {
1229private:
unsigned SrcAddrSpace;
unsigned DestAddrSpace;

1233public:
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
                    unsigned SrcAS, unsigned DestAS);

unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
unsigned getDestAddressSpace() const { return DestAddrSpace; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ADDRSPACECAST;
}
1243};

1245/// This is an abstract virtual class for memory operations.
1246class MemSDNode : public SDNode {
1247private:
// VT of in-memory value.
EVT MemoryVT;

1251protected:
/// Memory reference information.
MachineMemOperand *MMO;

1255public:
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
          EVT memvt, MachineMemOperand *MMO);

bool readMem() const { return MMO->isLoad(); }
bool writeMem() const { return MMO->isStore(); }

/// Returns alignment and volatility of the memory access
Align getOriginalAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }
LLVM_ATTRIBUTE_DEPRECATED(unsigned getOriginalAlignment() const,[[deprecated("Use getOriginalAlign() instead")]] unsigned getOriginalAlignment
() const
                          "Use getOriginalAlign() instead")[[deprecated("Use getOriginalAlign() instead")]] unsigned getOriginalAlignment
() const {
  return MMO->getBaseAlign().value();
}
// FIXME: Remove once transition to getAlign is over.
unsigned getAlignment() const { return MMO->getAlign().value(); }

/// Return the SubclassData value, without HasDebugValue. This contains an
/// encoding of the volatile flag, as well as bits used by subclasses. This
/// function should only be used to compute a FoldingSetNodeID value.
/// The HasDebugValue bit is masked out because CSE map needs to match
/// nodes with debug info with nodes without debug info. Same is about
/// isDivergent bit.
unsigned getRawSubclassData() const {
  uint16_t Data;
  union {
    char RawSDNodeBits[sizeof(uint16_t)];
    SDNodeBitfields SDNodeBits;
  };
  memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
  SDNodeBits.HasDebugValue = 0;
  SDNodeBits.IsDivergent = false;
  memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
  return Data;
}

bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
bool isInvariant() const { return MemSDNodeBits.IsInvariant; }

// Returns the offset from the location of the access.
int64_t getSrcValueOffset() const { return MMO->getOffset(); }

/// Returns the AA info that describes the dereference.
AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }

/// Returns the Ranges that describes the dereference.
const MDNode *getRanges() const { return MMO->getRanges(); }

/// Returns the synchronization scope ID for this memory operation.
SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }

/// Return the atomic ordering requirements for this memory operation. For
/// cmpxchg atomic operations, return the atomic ordering requirements when
/// store occurs.
AtomicOrdering getOrdering() const { return MMO->getOrdering(); }

/// Return true if the memory operation ordering is Unordered or higher.
bool isAtomic() const { return MMO->isAtomic(); }

/// Returns true if the memory operation doesn't imply any ordering
/// constraints on surrounding memory operations beyond the normal memory
/// aliasing rules.
bool isUnordered() const { return MMO->isUnordered(); }

/// Returns true if the memory operation is neither atomic or volatile.
bool isSimple() const { return !isAtomic() && !isVolatile(); }

/// Return the type of the in-memory value.
EVT getMemoryVT() const { return MemoryVT; }

/// Return a MachineMemOperand object describing the memory
/// reference performed by operation.
MachineMemOperand *getMemOperand() const { return MMO; }

const MachinePointerInfo &getPointerInfo() const {
  return MMO->getPointerInfo();
}

/// Return the address space for the associated pointer
unsigned getAddressSpace() const {
  return getPointerInfo().getAddrSpace();
}

/// Update this MemSDNode's MachineMemOperand information
/// to reflect the alignment of NewMMO, if it has a greater alignment.
/// This must only be used when the new alignment applies to all users of
/// this MachineMemOperand.
void refineAlignment(const MachineMemOperand *NewMMO) {
  MMO->refineAlignment(NewMMO);
}

const SDValue &getChain() const { return getOperand(0); }

const SDValue &getBasePtr() const {
  switch (getOpcode()) {
  case ISD::STORE:
  case ISD::MSTORE:
    return getOperand(2);
  case ISD::MGATHER:
  case ISD::MSCATTER:
    return getOperand(3);
  default:
    return getOperand(1);
  }
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // For some targets, we lower some target intrinsics to a MemIntrinsicNode
  // with either an intrinsic or a target opcode.
  return N->getOpcode() == ISD::LOAD                ||
         N->getOpcode() == ISD::STORE               ||
         N->getOpcode() == ISD::PREFETCH            ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE        ||
         N->getOpcode() == ISD::MLOAD               ||
         N->getOpcode() == ISD::MSTORE              ||
         N->getOpcode() == ISD::MGATHER             ||
         N->getOpcode() == ISD::MSCATTER            ||
         N->isMemIntrinsic()                        ||
         N->isTargetMemoryOpcode();
}
1395};

1397/// This is an SDNode representing atomic operations.
1398class AtomicSDNode : public MemSDNode {
1399public:
AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
             EVT MemVT, MachineMemOperand *MMO)
  : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
  assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1404, __PRETTY_FUNCTION__))
          MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1404, __PRETTY_FUNCTION__));
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }

/// Returns true if this SDNode represents cmpxchg atomic operation, false
/// otherwise.
bool isCompareAndSwap() const {
  unsigned Op = getOpcode();
  return Op == ISD::ATOMIC_CMP_SWAP ||
         Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
}

/// For cmpxchg atomic operations, return the atomic ordering requirements
/// when store does not occur.
AtomicOrdering getFailureOrdering() const {
  assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
 static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1421, __PRETTY_FUNCTION__));
  return MMO->getFailureOrdering();
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE;
}
1446};

1448/// This SDNode is used for target intrinsics that touch
1449/// memory and need an associated MachineMemOperand. Its opcode may be
1450/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1451/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1452class MemIntrinsicSDNode : public MemSDNode {
1453public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
                   SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
    : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
  SDNodeBits.IsMemIntrinsic = true;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // We lower some target intrinsics to their target opcode
  // early a node with a target opcode can be of this class
  return N->isMemIntrinsic()             ||
         N->getOpcode() == ISD::PREFETCH ||
         N->isTargetMemoryOpcode();
}
1468};

1470/// This SDNode is used to implement the code generator
1471/// support for the llvm IR shufflevector instruction.  It combines elements
1472/// from two input vectors into a new input vector, with the selection and
1473/// ordering of elements determined by an array of integers, referred to as
1474/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
1475/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1476/// An index of -1 is treated as undef, such that the code generator may put
1477/// any value in the corresponding element of the result.
1478class ShuffleVectorSDNode : public SDNode {
// The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
// is freed when the SelectionDAG object is destroyed.
const int *Mask;

1483protected:
friend class SelectionDAG;

ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
    : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}

1489public:
ArrayRef<int> getMask() const {
  EVT VT = getValueType(0);
  return makeArrayRef(Mask, VT.getVectorNumElements());
}

int getMaskElt(unsigned Idx) const {
  assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1496, __PRETTY_FUNCTION__));
  return Mask[Idx];
}

bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }

int getSplatIndex() const {
  assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1503, __PRETTY_FUNCTION__));
  EVT VT = getValueType(0);
  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
    if (Mask[i] >= 0)
      return Mask[i];

  // We can choose any index value here and be correct because all elements
  // are undefined. Return 0 for better potential for callers to simplify.
  return 0;
}

static bool isSplatMask(const int *Mask, EVT VT);

/// Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static void commuteMask(MutableArrayRef<int> Mask) {
  unsigned NumElems = Mask.size();
  for (unsigned i = 0; i != NumElems; ++i) {
    int idx = Mask[i];
    if (idx < 0)
      continue;
    else if (idx < (int)NumElems)
      Mask[i] = idx + NumElems;
    else
      Mask[i] = idx - NumElems;
  }
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VECTOR_SHUFFLE;
}
1534};

1536class ConstantSDNode : public SDNode {
friend class SelectionDAG;

const ConstantInt *Value;

ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
             getSDVTList(VT)),
      Value(val) {
  ConstantSDNodeBits.IsOpaque = isOpaque;
}

1548public:
const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); }
uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
  return Value->getLimitedValue(Limit);
}
MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); }
Align getAlignValue() const { return Value->getAlignValue(); }

bool isOne() const { return Value->isOne(); }
bool isNullValue() const { return Value->isZero(); }
bool isAllOnesValue() const { return Value->isMinusOne(); }

bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Constant ||
         N->getOpcode() == ISD::TargetConstant;
}
1569};

1571uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1573}

1575const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1577}

1579class ConstantFPSDNode : public SDNode {
friend class SelectionDAG;

const ConstantFP *Value;

ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
             DebugLoc(), getSDVTList(VT)),
      Value(val) {}

1589public:
const APFloat& getValueAPF() const { return Value->getValueAPF(); }
const ConstantFP *getConstantFPValue() const { return Value; }

/// Return true if the value is positive or negative zero.
bool isZero() const { return Value->isZero(); }

/// Return true if the value is a NaN.
bool isNaN() const { return Value->isNaN(); }

/// Return true if the value is an infinity
bool isInfinity() const { return Value->isInfinity(); }

/// Return true if the value is negative.
bool isNegative() const { return Value->isNegative(); }

/// We don't rely on operator== working on double values, as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit comparison of
/// two floating point values.

/// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like.  Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
  return Value->getValueAPF().isExactlyValue(V);
}
bool isExactlyValue(const APFloat& V) const;

static bool isValueValidForType(EVT VT, const APFloat& Val);

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantFP ||
         N->getOpcode() == ISD::TargetConstantFP;
}
1624};

1626/// Returns true if \p V is a constant integer zero.
1627bool isNullConstant(SDValue V);

1629/// Returns true if \p V is an FP constant with a value of positive zero.
1630bool isNullFPConstant(SDValue V);

1632/// Returns true if \p V is an integer constant with all bits set.
1633bool isAllOnesConstant(SDValue V);

1635/// Returns true if \p V is a constant integer one.
1636bool isOneConstant(SDValue V);

1638/// Return the non-bitcasted source operand of \p V if it exists.
1639/// If \p V is not a bitcasted value, it is returned as-is.
1640SDValue peekThroughBitcasts(SDValue V);

1642/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1643/// If \p V is not a bitcasted one-use value, it is returned as-is.
1644SDValue peekThroughOneUseBitcasts(SDValue V);

1646/// Return the non-extracted vector source operand of \p V if it exists.
1647/// If \p V is not an extracted subvector, it is returned as-is.
1648SDValue peekThroughExtractSubvectors(SDValue V);

1650/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1651/// constant is canonicalized to be operand 1.
1652bool isBitwiseNot(SDValue V, bool AllowUndefs = false);

1654/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1655ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1658/// Returns the SDNode if it is a demanded constant splat BuildVector or
1659/// constant int.
1660ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
                                  bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1664/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1665ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);

1667/// Returns the SDNode if it is a demanded constant splat BuildVector or
1668/// constant float.
1669ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
                                      bool AllowUndefs = false);

1672/// Return true if the value is a constant 0 integer or a splatted vector of
1673/// a constant 0 integer (with no undefs by default).
1674/// Build vector implicit truncation is not an issue for null values.
1675bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);

1677/// Return true if the value is a constant 1 integer or a splatted vector of a
1678/// constant 1 integer (with no undefs).
1679/// Does not permit build vector implicit truncation.
1680bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);

1682/// Return true if the value is a constant -1 integer or a splatted vector of a
1683/// constant -1 integer (with no undefs).
1684/// Does not permit build vector implicit truncation.
1685bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);

1687/// Return true if \p V is either a integer or FP constant.
1688inline bool isIntOrFPConstant(SDValue V) {
return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1690}

1692class GlobalAddressSDNode : public SDNode {
friend class SelectionDAG;

const GlobalValue *TheGlobal;
int64_t Offset;
unsigned TargetFlags;

GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
                    const GlobalValue *GA, EVT VT, int64_t o,
                    unsigned TF);

1703public:
const GlobalValue *getGlobal() const { return TheGlobal; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }
// Return the address space this GlobalAddress belongs to.
unsigned getAddressSpace() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::GlobalAddress ||
         N->getOpcode() == ISD::TargetGlobalAddress ||
         N->getOpcode() == ISD::GlobalTLSAddress ||
         N->getOpcode() == ISD::TargetGlobalTLSAddress;
}
1716};

1718class FrameIndexSDNode : public SDNode {
friend class SelectionDAG;

int FI;

FrameIndexSDNode(int fi, EVT VT, bool isTarg)
  : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
    0, DebugLoc(), getSDVTList(VT)), FI(fi) {
}

1728public:
int getIndex() const { return FI; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::FrameIndex ||
         N->getOpcode() == ISD::TargetFrameIndex;
}
1735};

1737/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1738/// the offet and size that are started/ended in the underlying FrameIndex.
1739class LifetimeSDNode : public SDNode {
friend class SelectionDAG;
int64_t Size;
int64_t Offset; // -1 if offset is unknown.

LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
               SDVTList VTs, int64_t Size, int64_t Offset)
    : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1747public:
int64_t getFrameIndex() const {
  return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
}

bool hasOffset() const { return Offset >= 0; }
int64_t getOffset() const {
  assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1754, __PRETTY_FUNCTION__));
  return Offset;
}
int64_t getSize() const {
  assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1758, __PRETTY_FUNCTION__));
  return Size;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LIFETIME_START ||
         N->getOpcode() == ISD::LIFETIME_END;
}
1767};

1769/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and
1770/// the index of the basic block being probed. A pseudo probe serves as a place
1771/// holder and will be removed at the end of compilation. It does not have any
1772/// operand because we do not want the instruction selection to deal with any.
1773class PseudoProbeSDNode : public SDNode {
friend class SelectionDAG;
uint64_t Guid;
uint64_t Index;
uint32_t Attributes;

PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl,
                  SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr)
    : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index),
      Attributes(Attr) {}

1784public:
uint64_t getGuid() const { return Guid; }
uint64_t getIndex() const { return Index; }
uint32_t getAttributes() const { return Attributes; }

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::PSEUDO_PROBE;
}
1793};

1795class JumpTableSDNode : public SDNode {
friend class SelectionDAG;

int JTI;
unsigned TargetFlags;

JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
  : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
    0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
}

1806public:
int getIndex() const { return JTI; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::JumpTable ||
         N->getOpcode() == ISD::TargetJumpTable;
}
1814};

1816class ConstantPoolSDNode : public SDNode {
friend class SelectionDAG;

union {
  const Constant *ConstVal;
  MachineConstantPoolValue *MachineCPVal;
} Val;
int Offset;  // It's a MachineConstantPoolValue if top bit is set.
Align Alignment; // Minimum alignment requirement of CP.
unsigned TargetFlags;

ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1832, __PRETTY_FUNCTION__));
  Val.ConstVal = c;
}

ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1841, __PRETTY_FUNCTION__));
  Val.MachineCPVal = v;
  Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
}

1846public:
bool isMachineConstantPoolEntry() const {
  return Offset < 0;
}

const Constant *getConstVal() const {
  assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1852, __PRETTY_FUNCTION__));
  return Val.ConstVal;
}

MachineConstantPoolValue *getMachineCPVal() const {
  assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1857, __PRETTY_FUNCTION__));
  return Val.MachineCPVal;
}

int getOffset() const {
  return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
}

// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or the desired value.
Align getAlign() const { return Alignment; }
unsigned getTargetFlags() const { return TargetFlags; }

Type *getType() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantPool ||
         N->getOpcode() == ISD::TargetConstantPool;
}
1876};

1878/// Completely target-dependent object reference.
1879class TargetIndexSDNode : public SDNode {
friend class SelectionDAG;

unsigned TargetFlags;
int Index;
int64_t Offset;

1886public:
TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
    : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
      TargetFlags(TF), Index(Idx), Offset(Ofs) {}

unsigned getTargetFlags() const { return TargetFlags; }
int getIndex() const { return Index; }
int64_t getOffset() const { return Offset; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::TargetIndex;
}
1898};

1900class BasicBlockSDNode : public SDNode {
friend class SelectionDAG;

MachineBasicBlock *MBB;

/// Debug info is meaningful and potentially useful here, but we create
/// blocks out of order when they're jumped to, which makes it a bit
/// harder.  Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
  : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
{}

1912public:
MachineBasicBlock *getBasicBlock() const { return MBB; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BasicBlock;
}
1918};

1920/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1921class BuildVectorSDNode : public SDNode {
1922public:
// These are constructed as SDNodes and then cast to BuildVectorSDNodes.
explicit BuildVectorSDNode() = delete;

/// Check if this is a constant splat, and if so, find the
/// smallest element size that splats the vector.  If MinSplatBits is
/// nonzero, the element size must be at least that large.  Note that the
/// splat element may be the entire vector (i.e., a one element vector).
/// Returns the splat element value in SplatValue.  Any undefined bits in
/// that value are zero, and the corresponding bits in the SplatUndef mask
/// are set.  The SplatBitSize value is set to the splat element size in
/// bits.  HasAnyUndefs is set to true if any bits in the vector are
/// undefined.  isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
                     unsigned &SplatBitSize, bool &HasAnyUndefs,
                     unsigned MinSplatBits = 0,
                     bool isBigEndian = false) const;

/// Returns the demanded splatted value or a null value if this is not a
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(const APInt &DemandedElts,
                      BitVector *UndefElements = nullptr) const;

/// Returns the splatted value or a null value if this is not a splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// The DemandedElts mask indicates the elements that must be present,
/// undemanded elements in Sequence may be null (SDValue()). If passed a
/// non-null UndefElements bitvector, it will resize it to match the original
/// vector width and set the bits where elements are undef. If result is
/// false, Sequence will be empty.
bool getRepeatedSequence(const APInt &DemandedElts,
                         SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the original vector width and set the bits where elements are undef.
/// If result is false, Sequence will be empty.
bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant or null if this is not a constant
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(const APInt &DemandedElts,
                     BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant or null if this is not a constant
/// splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant FP or null if this is not a
/// constant FP splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(const APInt &DemandedElts,
                       BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant FP or null if this is not a constant
/// FP splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;

/// If this is a constant FP splat and the splatted constant FP is an
/// exact power or 2, return the log base 2 integer value.  Otherwise,
/// return -1.
///
/// The BitWidth specifies the necessary bit precision.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
                                        uint32_t BitWidth) const;

bool isConstant() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BUILD_VECTOR;
}
2031};

2033/// An SDNode that holds an arbitrary LLVM IR Value. This is
2034/// used when the SelectionDAG needs to make a simple reference to something
2035/// in the LLVM IR representation.
2036///
2037class SrcValueSDNode : public SDNode {
friend class SelectionDAG;

const Value *V;

/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
  : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}

2046public:
/// Return the contained Value.
const Value *getValue() const { return V; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::SRCVALUE;
}
2053};

2055class MDNodeSDNode : public SDNode {
friend class SelectionDAG;

const MDNode *MD;

explicit MDNodeSDNode(const MDNode *md)
: SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
{}

2064public:
const MDNode *getMD() const { return MD; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MDNODE_SDNODE;
}
2070};

2072class RegisterSDNode : public SDNode {
friend class SelectionDAG;

Register Reg;

RegisterSDNode(Register reg, EVT VT)
  : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}

2080public:
Register getReg() const { return Reg; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Register;
}
2086};

2088class RegisterMaskSDNode : public SDNode {
friend class SelectionDAG;

// The memory for RegMask is not owned by the node.
const uint32_t *RegMask;

RegisterMaskSDNode(const uint32_t *mask)
  : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
    RegMask(mask) {}

2098public:
const uint32_t *getRegMask() const { return RegMask; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::RegisterMask;
}
2104};

2106class BlockAddressSDNode : public SDNode {
friend class SelectionDAG;

const BlockAddress *BA;
int64_t Offset;
unsigned TargetFlags;

BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
                   int64_t o, unsigned Flags)
  : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
           BA(ba), Offset(o), TargetFlags(Flags) {}

2118public:
const BlockAddress *getBlockAddress() const { return BA; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BlockAddress ||
         N->getOpcode() == ISD::TargetBlockAddress;
}
2127};

2129class LabelSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Label;

LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
    : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
  assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
 ? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2136, __PRETTY_FUNCTION__));
}

2139public:
MCSymbol *getLabel() const { return Label; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::EH_LABEL ||
         N->getOpcode() == ISD::ANNOTATION_LABEL;
}
2146};

2148class ExternalSymbolSDNode : public SDNode {
friend class SelectionDAG;

const char *Symbol;
unsigned TargetFlags;

ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
    : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
             DebugLoc(), getSDVTList(VT)),
      Symbol(Sym), TargetFlags(TF) {}

2159public:
const char *getSymbol() const { return Symbol; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ExternalSymbol ||
         N->getOpcode() == ISD::TargetExternalSymbol;
}
2167};

2169class MCSymbolSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Symbol;

MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
    : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}

2177public:
MCSymbol *getMCSymbol() const { return Symbol; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MCSymbol;
}
2183};

2185class CondCodeSDNode : public SDNode {
friend class SelectionDAG;

ISD::CondCode Condition;

explicit CondCodeSDNode(ISD::CondCode Cond)
  : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    Condition(Cond) {}

2194public:
ISD::CondCode get() const { return Condition; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::CONDCODE;
}
2200};

2202/// This class is used to represent EVT's, which are used
2203/// to parameterize some operations.
2204class VTSDNode : public SDNode {
friend class SelectionDAG;

EVT ValueType;

explicit VTSDNode(EVT VT)
  : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    ValueType(VT) {}

2213public:
EVT getVT() const { return ValueType; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VALUETYPE;
}
2219};

2221/// Base class for LoadSDNode and StoreSDNode
2222class LSBaseSDNode : public MemSDNode {
2223public:
LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
             SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
             MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2229, __PRETTY_FUNCTION__));
}

const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD ||
         N->getOpcode() == ISD::STORE;
}
2252};

2254/// This class is used to represent ISD::LOAD nodes.
2255class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG;

LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
           ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
           MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2263, __PRETTY_FUNCTION__));
  assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2264, __PRETTY_FUNCTION__));
}

2267public:
/// Return whether this is a plain node,
/// or one of the varieties of value-extending loads.
ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD;
}
2280};

2282/// This class is used to represent ISD::STORE nodes.
2283class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG;

StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
            ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
            MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
 ? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2291, __PRETTY_FUNCTION__));
  assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2292, __PRETTY_FUNCTION__));
}

2295public:
/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
void setTruncatingStore(bool Truncating) {
  StoreSDNodeBits.IsTruncating = Truncating;
}

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::STORE;
}
2311};

2313/// This base class is used to represent MLOAD and MSTORE nodes
2314class MaskedLoadStoreSDNode : public MemSDNode {
2315public:
friend class SelectionDAG;

MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
                      const DebugLoc &dl, SDVTList VTs,
                      ISD::MemIndexedMode AM, EVT MemVT,
                      MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2324, __PRETTY_FUNCTION__));
}

// MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
// MaskedStoreSDNode (Chain, data, ptr, offset, mask)
// Mask is a vector of i1 elements
const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
}
const SDValue &getMask() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD ||
         N->getOpcode() == ISD::MSTORE;
}
2353};

2355/// This class is used to represent an MLOAD node
2356class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2357public:
friend class SelectionDAG;

MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
                 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  LoadSDNodeBits.IsExpanding = IsExpanding;
}

ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }
const SDValue &getMask() const { return getOperand(3); }
const SDValue &getPassThru() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD;
}

bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2382};

2384/// This class is used to represent an MSTORE node
2385class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2386public:
friend class SelectionDAG;

MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                  ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
                  EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  StoreSDNodeBits.IsCompressing = isCompressing;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

/// Returns true if the op does a compression to the vector before storing.
/// The node contiguously stores the active elements (integers or floats)
/// in src (those with their respective bit set in writemask k) to unaligned
/// memory at base_addr.
bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }
const SDValue &getMask() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSTORE;
}
2416};

2418/// This is a base class used to represent
2419/// MGATHER and MSCATTER nodes
2420///
2421class MaskedGatherScatterSDNode : public MemSDNode {
2422public:
friend class SelectionDAG;

MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
                          const DebugLoc &dl, SDVTList VTs, EVT MemVT,
                          MachineMemOperand *MMO, ISD::MemIndexType IndexType)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
  assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ?
 static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2430, __PRETTY_FUNCTION__));
}

/// How is Index applied to BasePtr when computing addresses.
ISD::MemIndexType getIndexType() const {
  return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
}
void setIndexType(ISD::MemIndexType IndexType) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
}
bool isIndexScaled() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::UNSIGNED_SCALED);
}
bool isIndexSigned() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::SIGNED_UNSCALED);
}

// In the both nodes address is Op1, mask is Op2:
// MaskedGatherSDNode  (Chain, passthru, mask, base, index, scale)
// MaskedScatterSDNode (Chain, value, mask, base, index, scale)
// Mask is a vector of i1 elements
const SDValue &getBasePtr() const { return getOperand(3); }
const SDValue &getIndex()   const { return getOperand(4); }
const SDValue &getMask()    const { return getOperand(2); }
const SDValue &getScale()   const { return getOperand(5); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER ||
         N->getOpcode() == ISD::MSCATTER;
}
2462};

2464/// This class is used to represent an MGATHER node
2465///
2466class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2467public:
friend class SelectionDAG;

MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                   EVT MemVT, MachineMemOperand *MMO,
                   ISD::MemIndexType IndexType, ISD::LoadExtType ETy)
    : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  LoadSDNodeBits.ExtTy = ETy;
}

const SDValue &getPassThru() const { return getOperand(1); }

ISD::LoadExtType getExtensionType() const {
  return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER;
}
2487};

2489/// This class is used to represent an MSCATTER node
2490///
2491class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2492public:
friend class SelectionDAG;

MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                    EVT MemVT, MachineMemOperand *MMO,
                    ISD::MemIndexType IndexType, bool IsTrunc)
    : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  StoreSDNodeBits.IsTruncating = IsTrunc;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

const SDValue &getValue() const { return getOperand(1); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSCATTER;
}
2513};

2515/// An SDNode that represents everything that will be needed
2516/// to construct a MachineInstr. These nodes are created during the
2517/// instruction selection proper phase.
2518///
2519/// Note that the only supported way to set the `memoperands` is by calling the
2520/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2521/// inside the DAG rather than in the node.
2522class MachineSDNode : public SDNode {
2523private:
friend class SelectionDAG;

MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
    : SDNode(Opc, Order, DL, VTs) {}

// We use a pointer union between a single `MachineMemOperand` pointer and
// a pointer to an array of `MachineMemOperand` pointers. This is null when
// the number of these is zero, the single pointer variant used when the
// number is one, and the array is used for larger numbers.
//
// The array is allocated via the `SelectionDAG`'s allocator and so will
// always live until the DAG is cleaned up and doesn't require ownership here.
//
// We can't use something simpler like `TinyPtrVector` here because `SDNode`
// subclasses aren't managed in a conforming C++ manner. See the comments on
// `SelectionDAG::MorphNodeTo` which details what all goes on, but the
// constraint here is that these don't manage memory with their constructor or
// destructor and can be initialized to a good state even if they start off
// uninitialized.
PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};

// Note that this could be folded into the above `MemRefs` member if doing so
// is advantageous at some point. We don't need to store this in most cases.
// However, at the moment this doesn't appear to make the allocation any
// smaller and makes the code somewhat simpler to read.
int NumMemRefs = 0;

2551public:
using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;

ArrayRef<MachineMemOperand *> memoperands() const {
  // Special case the common cases.
  if (NumMemRefs == 0)
    return {};
  if (NumMemRefs == 1)
    return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);

  // Otherwise we have an actual array.
  return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
}
mmo_iterator memoperands_begin() const { return memoperands().begin(); }
mmo_iterator memoperands_end() const { return memoperands().end(); }
bool memoperands_empty() const { return memoperands().empty(); }

/// Clear out the memory reference descriptor list.
void clearMemRefs() {
  MemRefs = nullptr;
  NumMemRefs = 0;
}

static bool classof(const SDNode *N) {
  return N->isMachineOpcode();
}
2577};

2579/// An SDNode that records if a register contains a value that is guaranteed to
2580/// be aligned accordingly.
2581class AssertAlignSDNode : public SDNode {
Align Alignment;

2584public:
AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A)
    : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {}

Align getAlign() const { return Alignment; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::AssertAlign;
}
2593};

2595class SDNodeIterator {
const SDNode *Node;
unsigned Operand;

SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}

2601public:
using iterator_category = std::forward_iterator_tag;
using value_type = SDNode;
using difference_type = std::ptrdiff_t;
using pointer = value_type *;
using reference = value_type &;

bool operator==(const SDNodeIterator& x) const {
  return Operand == x.Operand;
}
bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }

pointer operator*() const {
  return Node->getOperand(Operand).getNode();
}
pointer operator->() const { return operator*(); }

SDNodeIterator& operator++() {                // Preincrement
  ++Operand;
  return *this;
}
SDNodeIterator operator++(int) { // Postincrement
  SDNodeIterator tmp = *this; ++*this; return tmp;
}
size_t operator-(SDNodeIterator Other) const {
  assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2627, __PRETTY_FUNCTION__))
         "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2627, __PRETTY_FUNCTION__));
  return Operand - Other.Operand;
}

static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
static SDNodeIterator end  (const SDNode *N) {
  return SDNodeIterator(N, N->getNumOperands());
}

unsigned getOperand() const { return Operand; }
const SDNode *getNode() const { return Node; }
2638};

2640template <> struct GraphTraits<SDNode*> {
using NodeRef = SDNode *;
using ChildIteratorType = SDNodeIterator;

static NodeRef getEntryNode(SDNode *N) { return N; }

static ChildIteratorType child_begin(NodeRef N) {
  return SDNodeIterator::begin(N);
}

static ChildIteratorType child_end(NodeRef N) {
  return SDNodeIterator::end(N);
}
2653};

2655/// A representation of the largest SDNode, for use in sizeof().
2656///
2657/// This needs to be a union because the largest node differs on 32 bit systems
2658/// with 4 and 8 byte pointer alignment, respectively.
2659using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
                                          BlockAddressSDNode,
                                          GlobalAddressSDNode,
                                          PseudoProbeSDNode>;

2664/// The SDNode class with the greatest alignment requirement.
2665using MostAlignedSDNode = GlobalAddressSDNode;

2667namespace ISD {

/// Returns true if the specified node is a non-extending and unindexed load.
inline bool isNormalLoad(const SDNode *N) {
  const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
  return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
    Ld->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-extending load.
inline bool isNON_EXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}

/// Returns true if the specified node is a EXTLOAD.
inline bool isEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}

/// Returns true if the specified node is a SEXTLOAD.
inline bool isSEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}

/// Returns true if the specified node is a ZEXTLOAD.
inline bool isZEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}

/// Returns true if the specified node is an unindexed load.
inline bool isUNINDEXEDLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-truncating
/// and unindexed store.
inline bool isNormalStore(const SDNode *N) {
  const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
  return St && !St->isTruncatingStore() &&
    St->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-truncating store.
inline bool isNON_TRUNCStore(const SDNode *N) {
  return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore();
}

/// Returns true if the specified node is a truncating store.
inline bool isTRUNCStore(const SDNode *N) {
  return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore();
}

/// Returns true if the specified node is an unindexed store.
inline bool isUNINDEXEDStore(const SDNode *N) {
  return isa<StoreSDNode>(N) &&
    cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Attempt to match a unary predicate against a scalar/splat constant or
/// every element of a constant BUILD_VECTOR.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
bool matchUnaryPredicate(SDValue Op,
                         std::function<bool(ConstantSDNode *)> Match,
                         bool AllowUndefs = false);

/// Attempt to match a binary predicate against a pair of scalar/splat
/// constants or every element of a pair of constant BUILD_VECTORs.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
/// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
bool matchBinaryPredicate(
    SDValue LHS, SDValue RHS,
    std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
    bool AllowUndefs = false, bool AllowTypeMismatch = false);

/// Returns true if the specified value is the overflow result from one
/// of the overflow intrinsic nodes.
inline bool isOverflowIntrOpRes(SDValue Op) {
  unsigned Opc = Op.getOpcode();
  return (Op.getResNo() == 1 &&
          (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
           Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
}

2755} // end namespace ISD

2757} // end namespace llvm

2759#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H