Bug Summary

File:build/source/build-llvm/tools/clang/stage2-bins/lib/Target/AMDGPU/AMDGPUGenPreLegalizeGICombiner.inc
Warning:line 3096, column 7
Value stored to 'Partition' is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name AMDGPUPreLegalizerCombiner.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-17/lib/clang/17 -D _DEBUG -D _GLIBCXX_ASSERTIONS -D _GNU_SOURCE -D _LIBCPP_ENABLE_ASSERTIONS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AMDGPU -I /build/source/llvm/lib/Target/AMDGPU -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-17/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1679443490 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-03-22-005342-16304-1 -x c++ /build/source/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Combiner *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
10#include "llvm/ADT/SparseBitVector.h"
11namespace llvm {
12extern cl::OptionCategory GICombinerOptionCategory;
13} // end namespace llvm
14#endif // ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
15
16#ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
17class AMDGPUGenPreLegalizerCombinerHelperRuleConfig {
18 SparseBitVector<> DisabledRules;
19
20public:
21 bool parseCommandLineOption();
22 bool isRuleDisabled(unsigned ID) const;
23 bool setRuleEnabled(StringRef RuleIdentifier);
24 bool setRuleDisabled(StringRef RuleIdentifier);
25};
26
27class AMDGPUGenPreLegalizerCombinerHelper : public AMDGPUPreLegalizerCombinerHelperState {
28 const AMDGPUGenPreLegalizerCombinerHelperRuleConfig *RuleConfig;
29
30public:
31 template <typename... Args>AMDGPUGenPreLegalizerCombinerHelper(const AMDGPUGenPreLegalizerCombinerHelperRuleConfig &RuleConfig, Args &&... args) : AMDGPUPreLegalizerCombinerHelperState(std::forward<Args>(args)...), RuleConfig(&RuleConfig) {}
32
33 bool tryCombineAll(
34 GISelChangeObserver &Observer,
35 MachineInstr &MI,
36 MachineIRBuilder &B) const;
37};
38
39static std::optional<uint64_t> getRuleIdxForIdentifier(StringRef RuleIdentifier) {
40 uint64_t I;
41 // getAtInteger(...) returns false on success
42 bool Parsed = !RuleIdentifier.getAsInteger(0, I);
43 if (Parsed)
44 return I;
45
46#ifndef NDEBUG
47 switch (RuleIdentifier.size()) {
48 default: break;
49 case 9: // 4 strings to match.
50 switch (RuleIdentifier[0]) {
51 default: break;
52 case 'a': // 1 string to match.
53 if (memcmp(RuleIdentifier.data()+1, "ddo_by_0", 8) != 0)
54 break;
55 return 74; // "addo_by_0"
56 case 'c': // 1 string to match.
57 if (memcmp(RuleIdentifier.data()+1, "opy_prop", 8) != 0)
58 break;
59 return 0; // "copy_prop"
60 case 'm': // 2 strings to match.
61 if (memcmp(RuleIdentifier.data()+1, "ulo_by_", 7) != 0)
62 break;
63 switch (RuleIdentifier[8]) {
64 default: break;
65 case '0': // 1 string to match.
66 return 73; // "mulo_by_0"
67 case '2': // 1 string to match.
68 return 72; // "mulo_by_2"
69 }
70 break;
71 }
72 break;
73 case 10: // 3 strings to match.
74 switch (RuleIdentifier[0]) {
75 default: break;
76 case 'i': // 1 string to match.
77 if (memcmp(RuleIdentifier.data()+1, "2p_to_p2i", 9) != 0)
78 break;
79 return 29; // "i2p_to_p2i"
80 case 'm': // 1 string to match.
81 if (memcmp(RuleIdentifier.data()+1, "ul_to_shl", 9) != 0)
82 break;
83 return 1; // "mul_to_shl"
84 case 'p': // 1 string to match.
85 if (memcmp(RuleIdentifier.data()+1, "2i_to_i2p", 9) != 0)
86 break;
87 return 28; // "p2i_to_i2p"
88 }
89 break;
90 case 11: // 4 strings to match.
91 switch (RuleIdentifier[0]) {
92 default: break;
93 case 'a': // 1 string to match.
94 if (memcmp(RuleIdentifier.data()+1, "dd_sub_reg", 10) != 0)
95 break;
96 return 33; // "add_sub_reg"
97 case 's': // 1 string to match.
98 if (memcmp(RuleIdentifier.data()+1, "ub_add_reg", 10) != 0)
99 break;
100 return 106; // "sub_add_reg"
101 case 't': // 1 string to match.
102 if (memcmp(RuleIdentifier.data()+1, "runc_shift", 10) != 0)
103 break;
104 return 68; // "trunc_shift"
105 case 'u': // 1 string to match.
106 if (memcmp(RuleIdentifier.data()+1, "nmerge_cst", 10) != 0)
107 break;
108 return 63; // "unmerge_cst"
109 }
110 break;
111 case 12: // 6 strings to match.
112 switch (RuleIdentifier[0]) {
113 default: break;
114 case 'a': // 1 string to match.
115 if (memcmp(RuleIdentifier.data()+1, "dde_to_addo", 11) != 0)
116 break;
117 return 75; // "adde_to_addo"
118 case 'e': // 1 string to match.
119 if (memcmp(RuleIdentifier.data()+1, "xt_ext_fold", 11) != 0)
120 break;
121 return 59; // "ext_ext_fold"
122 case 'f': // 1 string to match.
123 if (memcmp(RuleIdentifier.data()+1, "sub_to_fneg", 11) != 0)
124 break;
125 return 109; // "fsub_to_fneg"
126 case 'm': // 1 string to match.
127 if (memcmp(RuleIdentifier.data()+1, "ulh_to_lshr", 11) != 0)
128 break;
129 return 94; // "mulh_to_lshr"
130 case 'n': // 1 string to match.
131 if (memcmp(RuleIdentifier.data()+1, "ot_cmp_fold", 11) != 0)
132 break;
133 return 60; // "not_cmp_fold"
134 case 'r': // 1 string to match.
135 if (memcmp(RuleIdentifier.data()+1, "edundant_or", 11) != 0)
136 break;
137 return 53; // "redundant_or"
138 }
139 break;
140 case 13: // 9 strings to match.
141 switch (RuleIdentifier[0]) {
142 default: break;
143 case 'c': // 1 string to match.
144 if (memcmp(RuleIdentifier.data()+1, "onstant_fold", 12) != 0)
145 break;
146 return 90; // "constant_fold"
147 case 'f': // 1 string to match.
148 if (memcmp(RuleIdentifier.data()+1, "oldable_fneg", 12) != 0)
149 break;
150 return 112; // "foldable_fneg"
151 case 'l': // 1 string to match.
152 if (memcmp(RuleIdentifier.data()+1, "oad_and_mask", 12) != 0)
153 break;
154 return 9; // "load_and_mask"
155 case 'm': // 1 string to match.
156 if (memcmp(RuleIdentifier.data()+1, "erge_unmerge", 12) != 0)
157 break;
158 return 66; // "merge_unmerge"
159 case 'r': // 1 string to match.
160 if (memcmp(RuleIdentifier.data()+1, "edundant_and", 12) != 0)
161 break;
162 return 51; // "redundant_and"
163 case 's': // 1 string to match.
164 if (memcmp(RuleIdentifier.data()+1, "div_by_const", 12) != 0)
165 break;
166 return 93; // "sdiv_by_const"
167 case 'u': // 3 strings to match.
168 switch (RuleIdentifier[1]) {
169 default: break;
170 case 'd': // 1 string to match.
171 if (memcmp(RuleIdentifier.data()+2, "iv_by_const", 11) != 0)
172 break;
173 return 92; // "udiv_by_const"
174 case 'n': // 2 strings to match.
175 if (memcmp(RuleIdentifier.data()+2, "merge_", 6) != 0)
176 break;
177 switch (RuleIdentifier[8]) {
178 default: break;
179 case 'm': // 1 string to match.
180 if (memcmp(RuleIdentifier.data()+9, "erge", 4) != 0)
181 break;
182 return 62; // "unmerge_merge"
183 case 'u': // 1 string to match.
184 if (memcmp(RuleIdentifier.data()+9, "ndef", 4) != 0)
185 break;
186 return 21; // "unmerge_undef"
187 }
188 break;
189 }
190 break;
191 }
192 break;
193 case 14: // 8 strings to match.
194 switch (RuleIdentifier[0]) {
195 default: break;
196 case 'b': // 1 string to match.
197 if (memcmp(RuleIdentifier.data()+1, "inop_same_val", 13) != 0)
198 break;
199 return 25; // "binop_same_val"
200 case 'c': // 1 string to match.
201 if (memcmp(RuleIdentifier.data()+1, "onstant_fp_op", 13) != 0)
202 break;
203 return 69; // "constant_fp_op"
204 case 'f': // 2 strings to match.
205 switch (RuleIdentifier[1]) {
206 default: break;
207 case 'a': // 1 string to match.
208 if (memcmp(RuleIdentifier.data()+2, "bs_fneg_fold", 12) != 0)
209 break;
210 return 91; // "fabs_fneg_fold"
211 case 'n': // 1 string to match.
212 if (memcmp(RuleIdentifier.data()+2, "eg_fneg_fold", 12) != 0)
213 break;
214 return 31; // "fneg_fneg_fold"
215 }
216 break;
217 case 'm': // 1 string to match.
218 if (memcmp(RuleIdentifier.data()+1, "ul_by_neg_one", 13) != 0)
219 break;
220 return 3; // "mul_by_neg_one"
221 case 'r': // 1 string to match.
222 if (memcmp(RuleIdentifier.data()+1, "eassoc_ptradd", 13) != 0)
223 break;
224 return 42; // "reassoc_ptradd"
225 case 's': // 1 string to match.
226 if (memcmp(RuleIdentifier.data()+1, "hifts_too_big", 13) != 0)
227 break;
228 return 41; // "shifts_too_big"
229 case 't': // 1 string to match.
230 if (memcmp(RuleIdentifier.data()+1, "runc_ext_fold", 13) != 0)
231 break;
232 return 67; // "trunc_ext_fold"
233 }
234 break;
235 case 15: // 6 strings to match.
236 switch (RuleIdentifier[0]) {
237 default: break;
238 case 'e': // 1 string to match.
239 if (memcmp(RuleIdentifier.data()+1, "xtending_loads", 14) != 0)
240 break;
241 return 8; // "extending_loads"
242 case 'i': // 1 string to match.
243 if (memcmp(RuleIdentifier.data()+1, "dempotent_prop", 14) != 0)
244 break;
245 return 4; // "idempotent_prop"
246 case 'l': // 1 string to match.
247 if (memcmp(RuleIdentifier.data()+1, "oad_or_combine", 14) != 0)
248 break;
249 return 81; // "load_or_combine"
250 case 'o': // 1 string to match.
251 if (memcmp(RuleIdentifier.data()+1, "verlapping_and", 14) != 0)
252 break;
253 return 71; // "overlapping_and"
254 case 's': // 1 string to match.
255 if (memcmp(RuleIdentifier.data()+1, "elect_same_val", 14) != 0)
256 break;
257 return 23; // "select_same_val"
258 case 'z': // 1 string to match.
259 if (memcmp(RuleIdentifier.data()+1, "ext_trunc_fold", 14) != 0)
260 break;
261 return 55; // "zext_trunc_fold"
262 }
263 break;
264 case 16: // 5 strings to match.
265 switch (RuleIdentifier[0]) {
266 default: break;
267 case 'c': // 1 string to match.
268 if (memcmp(RuleIdentifier.data()+1, "lamp_i64_to_i16", 15) != 0)
269 break;
270 return 111; // "clamp_i64_to_i16"
271 case 's': // 2 strings to match.
272 if (memcmp(RuleIdentifier.data()+1, "elect_", 6) != 0)
273 break;
274 switch (RuleIdentifier[7]) {
275 default: break;
276 case 't': // 1 string to match.
277 if (memcmp(RuleIdentifier.data()+8, "o_minmax", 8) != 0)
278 break;
279 return 107; // "select_to_minmax"
280 case 'u': // 1 string to match.
281 if (memcmp(RuleIdentifier.data()+8, "ndef_cmp", 8) != 0)
282 break;
283 return 48; // "select_undef_cmp"
284 }
285 break;
286 case 't': // 1 string to match.
287 if (memcmp(RuleIdentifier.data()+1, "runcstore_merge", 15) != 0)
288 break;
289 return 82; // "truncstore_merge"
290 case 'u': // 1 string to match.
291 if (memcmp(RuleIdentifier.data()+1, "ndef_to_fp_zero", 15) != 0)
292 break;
293 return 11; // "undef_to_fp_zero"
294 }
295 break;
296 case 17: // 9 strings to match.
297 switch (RuleIdentifier[0]) {
298 default: break;
299 case 'a': // 2 strings to match.
300 switch (RuleIdentifier[1]) {
301 default: break;
302 case 'd': // 1 string to match.
303 if (memcmp(RuleIdentifier.data()+2, "d_p2i_to_ptradd", 15) != 0)
304 break;
305 return 2; // "add_p2i_to_ptradd"
306 case 'n': // 1 string to match.
307 if (memcmp(RuleIdentifier.data()+2, "yext_trunc_fold", 15) != 0)
308 break;
309 return 30; // "anyext_trunc_fold"
310 }
311 break;
312 case 'd': // 1 string to match.
313 if (memcmp(RuleIdentifier.data()+1, "iv_rem_to_divrem", 16) != 0)
314 break;
315 return 83; // "div_rem_to_divrem"
316 case 'e': // 1 string to match.
317 if (memcmp(RuleIdentifier.data()+1, "rase_undef_store", 16) != 0)
318 break;
319 return 20; // "erase_undef_store"
320 case 'p': // 1 string to match.
321 if (memcmp(RuleIdentifier.data()+1, "tr_add_with_zero", 16) != 0)
322 break;
323 return 78; // "ptr_add_with_zero"
324 case 's': // 2 strings to match.
325 switch (RuleIdentifier[1]) {
326 default: break;
327 case 'e': // 1 string to match.
328 if (memcmp(RuleIdentifier.data()+2, "lect_to_logical", 15) != 0)
329 break;
330 return 50; // "select_to_logical"
331 case 'h': // 1 string to match.
332 if (memcmp(RuleIdentifier.data()+2, "ift_immed_chain", 15) != 0)
333 break;
334 return 79; // "shift_immed_chain"
335 }
336 break;
337 case 'u': // 2 strings to match.
338 switch (RuleIdentifier[1]) {
339 default: break;
340 case 'n': // 1 string to match.
341 if (memcmp(RuleIdentifier.data()+2, "def_to_int_zero", 15) != 0)
342 break;
343 return 12; // "undef_to_int_zero"
344 case 'r': // 1 string to match.
345 if (memcmp(RuleIdentifier.data()+2, "em_pow2_to_mask", 15) != 0)
346 break;
347 return 54; // "urem_pow2_to_mask"
348 }
349 break;
350 }
351 break;
352 case 18: // 4 strings to match.
353 switch (RuleIdentifier[0]) {
354 default: break;
355 case 'b': // 1 string to match.
356 if (memcmp(RuleIdentifier.data()+1, "inop_left_to_zero", 17) != 0)
357 break;
358 return 26; // "binop_left_to_zero"
359 case 'c': // 1 string to match.
360 if (memcmp(RuleIdentifier.data()+1, "ombine_minmax_nan", 17) != 0)
361 break;
362 return 76; // "combine_minmax_nan"
363 case 'r': // 1 string to match.
364 if (memcmp(RuleIdentifier.data()+1, "ight_identity_one", 17) != 0)
365 break;
366 return 32; // "right_identity_one"
367 case 's': // 1 string to match.
368 if (memcmp(RuleIdentifier.data()+1, "ext_inreg_of_load", 17) != 0)
369 break;
370 return 45; // "sext_inreg_of_load"
371 }
372 break;
373 case 19: // 8 strings to match.
374 switch (RuleIdentifier[0]) {
375 default: break;
376 case 'b': // 1 string to match.
377 if (memcmp(RuleIdentifier.data()+1, "inop_right_to_zero", 18) != 0)
378 break;
379 return 27; // "binop_right_to_zero"
380 case 'c': // 1 string to match.
381 if (memcmp(RuleIdentifier.data()+1, "onst_ptradd_to_i2p", 18) != 0)
382 break;
383 return 70; // "const_ptradd_to_i2p"
384 case 'e': // 1 string to match.
385 if (memcmp(RuleIdentifier.data()+1, "xtend_through_phis", 18) != 0)
386 break;
387 return 38; // "extend_through_phis"
388 case 'p': // 1 string to match.
389 if (memcmp(RuleIdentifier.data()+1, "tr_add_immed_chain", 18) != 0)
390 break;
391 return 43; // "ptr_add_immed_chain"
392 case 'r': // 1 string to match.
393 if (memcmp(RuleIdentifier.data()+1, "ight_identity_zero", 18) != 0)
394 break;
395 return 24; // "right_identity_zero"
396 case 's': // 2 strings to match.
397 switch (RuleIdentifier[1]) {
398 default: break;
399 case 'e': // 1 string to match.
400 if (memcmp(RuleIdentifier.data()+2, "lect_constant_cmp", 17) != 0)
401 break;
402 return 49; // "select_constant_cmp"
403 case 'i': // 1 string to match.
404 if (memcmp(RuleIdentifier.data()+2, "mplify_add_to_sub", 17) != 0)
405 break;
406 return 39; // "simplify_add_to_sub"
407 }
408 break;
409 case 'u': // 1 string to match.
410 if (memcmp(RuleIdentifier.data()+1, "nary_undef_to_zero", 18) != 0)
411 break;
412 return 16; // "unary_undef_to_zero"
413 }
414 break;
415 case 20: // 5 strings to match.
416 switch (RuleIdentifier[0]) {
417 default: break;
418 case 'a': // 1 string to match.
419 if (memcmp(RuleIdentifier.data()+1, "nd_or_disjoint_mask", 19) != 0)
420 break;
421 return 96; // "and_or_disjoint_mask"
422 case 'b': // 1 string to match.
423 if (memcmp(RuleIdentifier.data()+1, "itcast_bitcast_fold", 19) != 0)
424 break;
425 return 37; // "bitcast_bitcast_fold"
426 case 'r': // 2 strings to match.
427 if (memcmp(RuleIdentifier.data()+1, "edu", 3) != 0)
428 break;
429 switch (RuleIdentifier[4]) {
430 default: break;
431 case 'c': // 1 string to match.
432 if (memcmp(RuleIdentifier.data()+5, "e_shl_of_extend", 15) != 0)
433 break;
434 return 46; // "reduce_shl_of_extend"
435 case 'n': // 1 string to match.
436 if (memcmp(RuleIdentifier.data()+5, "dant_sext_inreg", 15) != 0)
437 break;
438 return 52; // "redundant_sext_inreg"
439 }
440 break;
441 case 'u': // 1 string to match.
442 if (memcmp(RuleIdentifier.data()+1, "nmerge_zext_to_zext", 19) != 0)
443 break;
444 return 65; // "unmerge_zext_to_zext"
445 }
446 break;
447 case 21: // 2 strings to match.
448 if (memcmp(RuleIdentifier.data()+0, "un", 2) != 0)
449 break;
450 switch (RuleIdentifier[2]) {
451 default: break;
452 case 'd': // 1 string to match.
453 if (memcmp(RuleIdentifier.data()+3, "ef_to_negative_one", 18) != 0)
454 break;
455 return 13; // "undef_to_negative_one"
456 case 'm': // 1 string to match.
457 if (memcmp(RuleIdentifier.data()+3, "erge_dead_to_trunc", 18) != 0)
458 break;
459 return 64; // "unmerge_dead_to_trunc"
460 }
461 break;
462 case 22: // 7 strings to match.
463 switch (RuleIdentifier[0]) {
464 default: break;
465 case 'f': // 2 strings to match.
466 switch (RuleIdentifier[1]) {
467 default: break;
468 case 'o': // 1 string to match.
469 if (memcmp(RuleIdentifier.data()+2, "ld_binop_into_select", 20) != 0)
470 break;
471 return 105; // "fold_binop_into_select"
472 case 'u': // 1 string to match.
473 if (memcmp(RuleIdentifier.data()+2, "nnel_shift_to_rotate", 20) != 0)
474 break;
475 return 85; // "funnel_shift_to_rotate"
476 }
477 break;
478 case 'i': // 1 string to match.
479 if (memcmp(RuleIdentifier.data()+1, "cmp_to_lhs_known_bits", 21) != 0)
480 break;
481 return 57; // "icmp_to_lhs_known_bits"
482 case 'p': // 1 string to match.
483 if (memcmp(RuleIdentifier.data()+1, "ropagate_undef_any_op", 21) != 0)
484 break;
485 return 17; // "propagate_undef_any_op"
486 case 'r': // 1 string to match.
487 if (memcmp(RuleIdentifier.data()+1, "edundant_neg_operands", 21) != 0)
488 break;
489 return 95; // "redundant_neg_operands"
490 case 's': // 1 string to match.
491 if (memcmp(RuleIdentifier.data()+1, "hl_ashr_to_sext_inreg", 21) != 0)
492 break;
493 return 44; // "shl_ashr_to_sext_inreg"
494 case 't': // 1 string to match.
495 if (memcmp(RuleIdentifier.data()+1, "runc_buildvector_fold", 21) != 0)
496 break;
497 return 35; // "trunc_buildvector_fold"
498 }
499 break;
500 case 23: // 2 strings to match.
501 switch (RuleIdentifier[0]) {
502 default: break;
503 case 'c': // 1 string to match.
504 if (memcmp(RuleIdentifier.data()+1, "ommute_constant_to_rhs", 22) != 0)
505 break;
506 return 110; // "commute_constant_to_rhs"
507 case 'p': // 1 string to match.
508 if (memcmp(RuleIdentifier.data()+1, "ropagate_undef_all_ops", 22) != 0)
509 break;
510 return 18; // "propagate_undef_all_ops"
511 }
512 break;
513 case 24: // 4 strings to match.
514 switch (RuleIdentifier[0]) {
515 default: break;
516 case 'b': // 1 string to match.
517 if (memcmp(RuleIdentifier.data()+1, "inop_left_undef_to_zero", 23) != 0)
518 break;
519 return 14; // "binop_left_undef_to_zero"
520 case 'n': // 1 string to match.
521 if (memcmp(RuleIdentifier.data()+1, "arrow_binop_feeding_and", 23) != 0)
522 break;
523 return 47; // "narrow_binop_feeding_and"
524 case 's': // 1 string to match.
525 if (memcmp(RuleIdentifier.data()+1, "ext_inreg_to_zext_inreg", 23) != 0)
526 break;
527 return 58; // "sext_inreg_to_zext_inreg"
528 case 'x': // 1 string to match.
529 if (memcmp(RuleIdentifier.data()+1, "or_of_and_with_same_reg", 23) != 0)
530 break;
531 return 77; // "xor_of_and_with_same_reg"
532 }
533 break;
534 case 25: // 4 strings to match.
535 switch (RuleIdentifier[0]) {
536 default: break;
537 case 'b': // 3 strings to match.
538 switch (RuleIdentifier[1]) {
539 default: break;
540 case 'i': // 2 strings to match.
541 if (memcmp(RuleIdentifier.data()+2, "tfield_extract_from_", 20) != 0)
542 break;
543 switch (RuleIdentifier[22]) {
544 default: break;
545 case 'a': // 1 string to match.
546 if (memcmp(RuleIdentifier.data()+23, "nd", 2) != 0)
547 break;
548 return 87; // "bitfield_extract_from_and"
549 case 's': // 1 string to match.
550 if (memcmp(RuleIdentifier.data()+23, "hr", 2) != 0)
551 break;
552 return 88; // "bitfield_extract_from_shr"
553 }
554 break;
555 case 'u': // 1 string to match.
556 if (memcmp(RuleIdentifier.data()+2, "ildvector_identity_fold", 23) != 0)
557 break;
558 return 34; // "buildvector_identity_fold"
559 }
560 break;
561 case 'e': // 1 string to match.
562 if (memcmp(RuleIdentifier.data()+1, "xtract_vec_elt_build_vec", 24) != 0)
563 break;
564 return 6; // "extract_vec_elt_build_vec"
565 }
566 break;
567 case 26: // 3 strings to match.
568 switch (RuleIdentifier[0]) {
569 default: break;
570 case 'b': // 1 string to match.
571 if (memcmp(RuleIdentifier.data()+1, "inop_right_undef_to_undef", 25) != 0)
572 break;
573 return 15; // "binop_right_undef_to_undef"
574 case 'c': // 1 string to match.
575 if (memcmp(RuleIdentifier.data()+1, "ombine_indexed_load_store", 25) != 0)
576 break;
577 return 10; // "combine_indexed_load_store"
578 case 'f': // 1 string to match.
579 if (memcmp(RuleIdentifier.data()+1, "unnel_shift_from_or_shift", 25) != 0)
580 break;
581 return 84; // "funnel_shift_from_or_shift"
582 }
583 break;
584 case 27: // 2 strings to match.
585 switch (RuleIdentifier[0]) {
586 default: break;
587 case 'r': // 1 string to match.
588 if (memcmp(RuleIdentifier.data()+1, "edundant_binop_in_equality", 26) != 0)
589 break;
590 return 108; // "redundant_binop_in_equality"
591 case 't': // 1 string to match.
592 if (memcmp(RuleIdentifier.data()+1, "runc_lshr_buildvector_fold", 26) != 0)
593 break;
594 return 36; // "trunc_lshr_buildvector_fold"
595 }
596 break;
597 case 28: // 3 strings to match.
598 switch (RuleIdentifier[0]) {
599 default: break;
600 case 'o': // 1 string to match.
601 if (memcmp(RuleIdentifier.data()+1, "pt_brcond_by_inverting_cond", 27) != 0)
602 break;
603 return 61; // "opt_brcond_by_inverting_cond"
604 case 'p': // 1 string to match.
605 if (memcmp(RuleIdentifier.data()+1, "ropagate_undef_shuffle_mask", 27) != 0)
606 break;
607 return 19; // "propagate_undef_shuffle_mask"
608 case 's': // 1 string to match.
609 if (memcmp(RuleIdentifier.data()+1, "hift_of_shifted_logic_chain", 27) != 0)
610 break;
611 return 80; // "shift_of_shifted_logic_chain"
612 }
613 break;
614 case 29: // 2 strings to match.
615 switch (RuleIdentifier[0]) {
616 default: break;
617 case 'b': // 1 string to match.
618 if (memcmp(RuleIdentifier.data()+1, "itfield_extract_from_shr_and", 28) != 0)
619 break;
620 return 89; // "bitfield_extract_from_shr_and"
621 case 'i': // 1 string to match.
622 if (memcmp(RuleIdentifier.data()+1, "cmp_to_true_false_known_bits", 28) != 0)
623 break;
624 return 56; // "icmp_to_true_false_known_bits"
625 }
626 break;
627 case 32: // 3 strings to match.
628 switch (RuleIdentifier[0]) {
629 default: break;
630 case 'b': // 1 string to match.
631 if (memcmp(RuleIdentifier.data()+1, "itfield_extract_from_sext_inreg", 31) != 0)
632 break;
633 return 86; // "bitfield_extract_from_sext_inreg"
634 case 'c': // 2 strings to match.
635 if (memcmp(RuleIdentifier.data()+1, "ombine_f", 8) != 0)
636 break;
637 switch (RuleIdentifier[9]) {
638 default: break;
639 case 'a': // 1 string to match.
640 if (memcmp(RuleIdentifier.data()+10, "dd_fmul_to_fmad_or_fma", 22) != 0)
641 break;
642 return 97; // "combine_fadd_fmul_to_fmad_or_fma"
643 case 's': // 1 string to match.
644 if (memcmp(RuleIdentifier.data()+10, "ub_fmul_to_fmad_or_fma", 22) != 0)
645 break;
646 return 101; // "combine_fsub_fmul_to_fmad_or_fma"
647 }
648 break;
649 }
650 break;
651 case 34: // 1 string to match.
652 if (memcmp(RuleIdentifier.data()+0, "extract_all_elts_from_build_vector", 34) != 0)
653 break;
654 return 7; // "extract_all_elts_from_build_vector"
655 case 36: // 3 strings to match.
656 switch (RuleIdentifier[0]) {
657 default: break;
658 case 'c': // 2 strings to match.
659 if (memcmp(RuleIdentifier.data()+1, "ombine_", 7) != 0)
660 break;
661 switch (RuleIdentifier[8]) {
662 default: break;
663 case 'f': // 1 string to match.
664 if (memcmp(RuleIdentifier.data()+9, "add_fma_fmul_to_fmad_or_fma", 27) != 0)
665 break;
666 return 99; // "combine_fadd_fma_fmul_to_fmad_or_fma"
667 case 'i': // 1 string to match.
668 if (memcmp(RuleIdentifier.data()+9, "nsert_vec_elts_build_vector", 27) != 0)
669 break;
670 return 5; // "combine_insert_vec_elts_build_vector"
671 }
672 break;
673 case 'i': // 1 string to match.
674 if (memcmp(RuleIdentifier.data()+1, "nsert_extract_vec_elt_out_of_bounds", 35) != 0)
675 break;
676 return 22; // "insert_extract_vec_elt_out_of_bounds"
677 }
678 break;
679 case 37: // 2 strings to match.
680 switch (RuleIdentifier[0]) {
681 default: break;
682 case 'c': // 1 string to match.
683 if (memcmp(RuleIdentifier.data()+1, "ombine_fsub_fneg_fmul_to_fmad_or_fma", 36) != 0)
684 break;
685 return 102; // "combine_fsub_fneg_fmul_to_fmad_or_fma"
686 case 'h': // 1 string to match.
687 if (memcmp(RuleIdentifier.data()+1, "oist_logic_op_with_same_opcode_hands", 36) != 0)
688 break;
689 return 40; // "hoist_logic_op_with_same_opcode_hands"
690 }
691 break;
692 case 38: // 2 strings to match.
693 if (memcmp(RuleIdentifier.data()+0, "combine_f", 9) != 0)
694 break;
695 switch (RuleIdentifier[9]) {
696 default: break;
697 case 'a': // 1 string to match.
698 if (memcmp(RuleIdentifier.data()+10, "dd_fpext_fmul_to_fmad_or_fma", 28) != 0)
699 break;
700 return 98; // "combine_fadd_fpext_fmul_to_fmad_or_fma"
701 case 's': // 1 string to match.
702 if (memcmp(RuleIdentifier.data()+10, "ub_fpext_fmul_to_fmad_or_fma", 28) != 0)
703 break;
704 return 103; // "combine_fsub_fpext_fmul_to_fmad_or_fma"
705 }
706 break;
707 case 42: // 1 string to match.
708 if (memcmp(RuleIdentifier.data()+0, "combine_fadd_fpext_fma_fmul_to_fmad_or_fma", 42) != 0)
709 break;
710 return 100; // "combine_fadd_fpext_fma_fmul_to_fmad_or_fma"
711 case 43: // 1 string to match.
712 if (memcmp(RuleIdentifier.data()+0, "combine_fsub_fpext_fneg_fmul_to_fmad_or_fma", 43) != 0)
713 break;
714 return 104; // "combine_fsub_fpext_fneg_fmul_to_fmad_or_fma"
715 }
716#endif // ifndef NDEBUG
717
718 return std::nullopt;
719}
720static std::optional<std::pair<uint64_t, uint64_t>> getRuleRangeForIdentifier(StringRef RuleIdentifier) {
721 std::pair<StringRef, StringRef> RangePair = RuleIdentifier.split('-');
722 if (!RangePair.second.empty()) {
723 const auto First = getRuleIdxForIdentifier(RangePair.first);
724 const auto Last = getRuleIdxForIdentifier(RangePair.second);
725 if (!First || !Last)
726 return std::nullopt;
727 if (First >= Last)
728 report_fatal_error("Beginning of range should be before end of range");
729 return {{*First, *Last + 1}};
730 }
731 if (RangePair.first == "*") {
732 return {{0, 113}};
733 }
734 const auto I = getRuleIdxForIdentifier(RangePair.first);
735 if (!I)
736 return std::nullopt;
737 return {{*I, *I + 1}};
738}
739
740bool AMDGPUGenPreLegalizerCombinerHelperRuleConfig::setRuleEnabled(StringRef RuleIdentifier) {
741 auto MaybeRange = getRuleRangeForIdentifier(RuleIdentifier);
742 if (!MaybeRange)
743 return false;
744 for (auto I = MaybeRange->first; I < MaybeRange->second; ++I)
745 DisabledRules.reset(I);
746 return true;
747}
748
749bool AMDGPUGenPreLegalizerCombinerHelperRuleConfig::setRuleDisabled(StringRef RuleIdentifier) {
750 auto MaybeRange = getRuleRangeForIdentifier(RuleIdentifier);
751 if (!MaybeRange)
752 return false;
753 for (auto I = MaybeRange->first; I < MaybeRange->second; ++I)
754 DisabledRules.set(I);
755 return true;
756}
757
758bool AMDGPUGenPreLegalizerCombinerHelperRuleConfig::isRuleDisabled(unsigned RuleID) const {
759 return DisabledRules.test(RuleID);
760}
761#endif // ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
762
763#ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
764
765std::vector<std::string> AMDGPUPreLegalizerCombinerHelperOption;
766cl::list<std::string> AMDGPUPreLegalizerCombinerHelperDisableOption(
767 "amdgpuprelegalizercombinerhelper-disable-rule",
768 cl::desc("Disable one or more combiner rules temporarily in the AMDGPUPreLegalizerCombinerHelper pass"),
769 cl::CommaSeparated,
770 cl::Hidden,
771 cl::cat(GICombinerOptionCategory),
772 cl::callback([](const std::string &Str) {
773 AMDGPUPreLegalizerCombinerHelperOption.push_back(Str);
774 }));
775cl::list<std::string> AMDGPUPreLegalizerCombinerHelperOnlyEnableOption(
776 "amdgpuprelegalizercombinerhelper-only-enable-rule",
777 cl::desc("Disable all rules in the AMDGPUPreLegalizerCombinerHelper pass then re-enable the specified ones"),
778 cl::Hidden,
779 cl::cat(GICombinerOptionCategory),
780 cl::callback([](const std::string &CommaSeparatedArg) {
781 StringRef Str = CommaSeparatedArg;
782 AMDGPUPreLegalizerCombinerHelperOption.push_back("*");
783 do {
784 auto X = Str.split(",");
785 AMDGPUPreLegalizerCombinerHelperOption.push_back(("!" + X.first).str());
786 Str = X.second;
787 } while (!Str.empty());
788 }));
789
790bool AMDGPUGenPreLegalizerCombinerHelperRuleConfig::parseCommandLineOption() {
791 for (StringRef Identifier : AMDGPUPreLegalizerCombinerHelperOption) {
792 bool Enabled = Identifier.consume_front("!");
793 if (Enabled && !setRuleEnabled(Identifier))
794 return false;
795 if (!Enabled && !setRuleDisabled(Identifier))
796 return false;
797 }
798 return true;
799}
800
801bool AMDGPUGenPreLegalizerCombinerHelper::tryCombineAll(
802 GISelChangeObserver &Observer,
803 MachineInstr &MI,
804 MachineIRBuilder &B) const {
805 MachineBasicBlock *MBB = MI.getParent();
806 MachineFunction *MF = MBB->getParent();
807 MachineRegisterInfo &MRI = MF->getRegInfo();
808 SmallVector<MachineInstr *, 8> MIs = {&MI};
809
810 (void)MBB; (void)MF; (void)MRI; (void)RuleConfig;
811
812 // Match data
813 unsigned MatchData1;
814 std::pair<Register, bool> MatchData2;
815 SmallVector<Register, 4> MatchData5;
816 Register MatchData6;
817 SmallVector<std::pair<Register, MachineInstr*>> MatchData7;
818 PreferredTuple MatchData8;
819 std::function<void(MachineIRBuilder &)> MatchData9;
820 IndexedLoadStoreMatchInfo MatchData10;
821 std::function<void(MachineIRBuilder &)> MatchData21;
822 Register MatchData28;
823 Register MatchData29;
824 Register MatchData30;
825 Register MatchData31;
826 Register MatchData33;
827 Register MatchData34;
828 Register MatchData35;
829 Register MatchData36;
830 MachineInstr* MatchData38;
831 std::tuple<Register, Register> MatchData39;
832 InstructionStepsMatchInfo MatchData40;
833 std::function<void(MachineIRBuilder &)> MatchData42;
834 PtrAddChain MatchData43;
835 std::tuple<Register, int64_t> MatchData44;
836 std::tuple<Register, unsigned> MatchData45;
837 RegisterImmPair MatchData46;
838 std::function<void(MachineIRBuilder &)> MatchData47;
839 unsigned MatchData49;
840 std::function<void(MachineIRBuilder &)> MatchData50;
841 Register MatchData51;
842 Register MatchData53;
843 Register MatchData55;
844 int64_t MatchData56;
845 std::function<void(MachineIRBuilder &)> MatchData57;
846 std::tuple<Register, unsigned> MatchData59;
847 SmallVector<Register, 4> MatchData60;
848 MachineInstr * MatchData61;
849 SmallVector<Register, 8> MatchData62;
850 SmallVector<APInt, 8> MatchData63;
851 Register MatchData66;
852 std::pair<Register, unsigned> MatchData67;
853 std::pair<MachineInstr*, LLT> MatchData68;
854 std::optional<APFloat> MatchData69;
855 APInt MatchData70;
856 std::function<void(MachineIRBuilder &)> MatchData71;
857 std::function<void(MachineIRBuilder &)> MatchData72;
858 std::function<void(MachineIRBuilder &)> MatchData73;
859 std::function<void(MachineIRBuilder &)> MatchData74;
860 std::function<void(MachineIRBuilder &)> MatchData75;
861 unsigned MatchData76;
862 std::pair<Register, Register> MatchData77;
863 RegisterImmPair MatchData79;
864 ShiftOfShiftedLogic MatchData80;
865 std::function<void(MachineIRBuilder &)> MatchData81;
866 MergeTruncStoresInfo MatchData82;
867 MachineInstr * MatchData83;
868 std::function<void(MachineIRBuilder &)> MatchData84;
869 std::function<void(MachineIRBuilder &)> MatchData86;
870 std::function<void(MachineIRBuilder &)> MatchData87;
871 std::function<void(MachineIRBuilder &)> MatchData88;
872 std::function<void(MachineIRBuilder &)> MatchData89;
873 APInt MatchData90;
874 std::function<void(MachineIRBuilder &)> MatchData91;
875 std::function<void(MachineIRBuilder &)> MatchData95;
876 std::function<void(MachineIRBuilder &)> MatchData96;
877 std::function<void(MachineIRBuilder &)> MatchData97;
878 std::function<void(MachineIRBuilder &)> MatchData98;
879 std::function<void(MachineIRBuilder &)> MatchData99;
880 std::function<void(MachineIRBuilder &)> MatchData100;
881 std::function<void(MachineIRBuilder &)> MatchData101;
882 std::function<void(MachineIRBuilder &)> MatchData102;
883 std::function<void(MachineIRBuilder &)> MatchData103;
884 std::function<void(MachineIRBuilder &)> MatchData104;
885 unsigned MatchData105;
886 std::function<void(MachineIRBuilder &)> MatchData106;
887 std::function<void(MachineIRBuilder &)> MatchData107;
888 std::function<void(MachineIRBuilder &)> MatchData108;
889 Register MatchData109;
890 AMDGPUPreLegalizerCombinerHelper::ClampI64ToI16MatchInfo MatchData111;
891 MachineInstr * MatchData112;
892
893 int Partition = -1;
894 Partition = -1;
895 switch (MIs[0]->getOpcode()) {
896 case TargetOpcode::COPY: Partition = 0; break;
897 case TargetOpcode::G_MUL: Partition = 1; break;
898 case TargetOpcode::G_ADD: Partition = 2; break;
899 case TargetOpcode::G_FREEZE: Partition = 3; break;
900 case TargetOpcode::G_FABS: Partition = 4; break;
901 case TargetOpcode::G_FCANONICALIZE: Partition = 5; break;
902 case TargetOpcode::G_INSERT_VECTOR_ELT: Partition = 6; break;
903 case TargetOpcode::G_EXTRACT_VECTOR_ELT: Partition = 7; break;
904 case TargetOpcode::G_BUILD_VECTOR: Partition = 8; break;
905 case TargetOpcode::G_LOAD: Partition = 9; break;
906 case TargetOpcode::G_SEXTLOAD: Partition = 10; break;
907 case TargetOpcode::G_ZEXTLOAD: Partition = 11; break;
908 case TargetOpcode::G_AND: Partition = 12; break;
909 case TargetOpcode::G_STORE: Partition = 13; break;
910 case TargetOpcode::G_UITOFP: Partition = 14; break;
911 case TargetOpcode::G_SITOFP: Partition = 15; break;
912 case TargetOpcode::G_OR: Partition = 16; break;
913 case TargetOpcode::G_SHL: Partition = 17; break;
914 case TargetOpcode::G_UDIV: Partition = 18; break;
915 case TargetOpcode::G_UREM: Partition = 19; break;
916 case TargetOpcode::G_ASHR: Partition = 20; break;
917 case TargetOpcode::G_LSHR: Partition = 21; break;
918 case TargetOpcode::G_ABS: Partition = 22; break;
919 case TargetOpcode::G_FPTOSI: Partition = 23; break;
920 case TargetOpcode::G_FPTOUI: Partition = 24; break;
921 case TargetOpcode::G_SUB: Partition = 25; break;
922 case TargetOpcode::G_XOR: Partition = 26; break;
923 case TargetOpcode::G_TRUNC: Partition = 27; break;
924 case TargetOpcode::G_SHUFFLE_VECTOR: Partition = 28; break;
925 case TargetOpcode::G_UNMERGE_VALUES: Partition = 29; break;
926 case TargetOpcode::G_SELECT: Partition = 30; break;
927 case TargetOpcode::G_PTR_ADD: Partition = 31; break;
928 case TargetOpcode::G_ROTL: Partition = 32; break;
929 case TargetOpcode::G_ROTR: Partition = 33; break;
930 case TargetOpcode::G_SDIV: Partition = 34; break;
931 case TargetOpcode::G_SREM: Partition = 35; break;
932 case TargetOpcode::G_INTTOPTR: Partition = 36; break;
933 case TargetOpcode::G_PTRTOINT: Partition = 37; break;
934 case TargetOpcode::G_ANYEXT: Partition = 38; break;
935 case TargetOpcode::G_FNEG: Partition = 39; break;
936 case TargetOpcode::G_BUILD_VECTOR_TRUNC: Partition = 40; break;
937 case TargetOpcode::G_BITCAST: Partition = 41; break;
938 case TargetOpcode::G_PHI: Partition = 42; break;
939 case TargetOpcode::G_SEXT_INREG: Partition = 43; break;
940 case TargetOpcode::G_ZEXT: Partition = 44; break;
941 case TargetOpcode::G_ICMP: Partition = 45; break;
942 case TargetOpcode::G_SEXT: Partition = 46; break;
943 case TargetOpcode::G_BR: Partition = 47; break;
944 case TargetOpcode::G_MERGE_VALUES: Partition = 48; break;
945 case TargetOpcode::G_FPTRUNC: Partition = 49; break;
946 case TargetOpcode::G_FSQRT: Partition = 50; break;
947 case TargetOpcode::G_FLOG2: Partition = 51; break;
948 case TargetOpcode::G_UMULO: Partition = 52; break;
949 case TargetOpcode::G_SMULO: Partition = 53; break;
950 case TargetOpcode::G_UADDO: Partition = 54; break;
951 case TargetOpcode::G_SADDO: Partition = 55; break;
952 case TargetOpcode::G_UADDE: Partition = 56; break;
953 case TargetOpcode::G_SADDE: Partition = 57; break;
954 case TargetOpcode::G_USUBE: Partition = 58; break;
955 case TargetOpcode::G_SSUBE: Partition = 59; break;
956 case TargetOpcode::G_FMINNUM: Partition = 60; break;
957 case TargetOpcode::G_FMAXNUM: Partition = 61; break;
958 case TargetOpcode::G_FMINIMUM: Partition = 62; break;
959 case TargetOpcode::G_FMAXIMUM: Partition = 63; break;
960 case TargetOpcode::G_SSHLSAT: Partition = 64; break;
961 case TargetOpcode::G_USHLSAT: Partition = 65; break;
962 case TargetOpcode::G_FSHL: Partition = 66; break;
963 case TargetOpcode::G_FSHR: Partition = 67; break;
964 case TargetOpcode::G_UMULH: Partition = 68; break;
965 case TargetOpcode::G_FADD: Partition = 69; break;
966 case TargetOpcode::G_FSUB: Partition = 70; break;
967 case TargetOpcode::G_FMUL: Partition = 71; break;
968 case TargetOpcode::G_FDIV: Partition = 72; break;
969 case TargetOpcode::G_FMAD: Partition = 73; break;
970 case TargetOpcode::G_FMA: Partition = 74; break;
971 case TargetOpcode::G_SMIN: Partition = 75; break;
972 case TargetOpcode::G_SMAX: Partition = 76; break;
973 case TargetOpcode::G_UMIN: Partition = 77; break;
974 case TargetOpcode::G_UMAX: Partition = 78; break;
975 case TargetOpcode::G_FREM: Partition = 79; break;
976 }
977 // Default case but without conflicting with potential default case in selection.
978 if (Partition == -1) return false;
979 if (Partition == 0 /* TargetOpcode::COPY */) {
980 // Leaf name: copy_prop
981 // Rule: copy_prop
982 if (!RuleConfig->isRuleDisabled(0)) {
983 if (1
984 && [&]() {
985 return Helper.matchCombineCopy(*MIs[0]);
986 return true;
987 }() ) {
988 LLVM_DEBUG(dbgs() << "Applying rule 'copy_prop'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'copy_prop'\n"
; } } while (false)
;
989 Helper.applyCombineCopy(*MIs[0]);
990 return true;
991 }
992 }
993 return false;
994 }
995 if (Partition == 1 /* TargetOpcode::G_MUL */) {
996 // Leaf name: mul_to_shl
997 // Rule: mul_to_shl
998 if (!RuleConfig->isRuleDisabled(1)) {
999 if (1
1000 && [&]() {
1001 return Helper.matchCombineMulToShl(*MIs[0], MatchData1);
1002 return true;
1003 }() ) {
1004 LLVM_DEBUG(dbgs() << "Applying rule 'mul_to_shl'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mul_to_shl'\n"
; } } while (false)
;
1005 Helper.applyCombineMulToShl(*MIs[0], MatchData1);
1006 return true;
1007 }
1008 }
1009 // Leaf name: mul_by_neg_one
1010 // Rule: mul_by_neg_one
1011 if (!RuleConfig->isRuleDisabled(3)) {
1012 if (1
1013 && [&]() {
1014 return Helper.matchConstantOp(MIs[0]->getOperand(2), -1);
1015 return true;
1016 }() ) {
1017 LLVM_DEBUG(dbgs() << "Applying rule 'mul_by_neg_one'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mul_by_neg_one'\n"
; } } while (false)
;
1018 Helper.applyCombineMulByNegativeOne(*MIs[0]);
1019 return true;
1020 }
1021 }
1022 // Leaf name: undef_to_int_zero
1023 // Rule: undef_to_int_zero
1024 if (!RuleConfig->isRuleDisabled(12)) {
1025 if (1
1026 && [&]() {
1027 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1028 return true;
1029 }() ) {
1030 LLVM_DEBUG(dbgs() << "Applying rule 'undef_to_int_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'undef_to_int_zero'\n"
; } } while (false)
;
1031 Helper.replaceInstWithConstant(*MIs[0], 0);
1032 return true;
1033 }
1034 }
1035 // Leaf name: binop_right_to_zero
1036 // Rule: binop_right_to_zero
1037 if (!RuleConfig->isRuleDisabled(27)) {
1038 if (1
1039 && [&]() {
1040 return Helper.matchOperandIsZero(*MIs[0], 2);
1041 return true;
1042 }() ) {
1043 LLVM_DEBUG(dbgs() << "Applying rule 'binop_right_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_right_to_zero'\n"
; } } while (false)
;
1044 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 2);
1045 return true;
1046 }
1047 }
1048 // Leaf name: right_identity_one
1049 // Rule: right_identity_one
1050 if (!RuleConfig->isRuleDisabled(32)) {
1051 if (1
1052 && [&]() {
1053 return Helper.matchConstantOp(MIs[0]->getOperand(2), 1);
1054 return true;
1055 }() ) {
1056 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_one'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_one'\n"
; } } while (false)
;
1057 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1058 return true;
1059 }
1060 }
1061 // Leaf name: constant_fold
1062 // Rule: constant_fold
1063 if (!RuleConfig->isRuleDisabled(90)) {
1064 if (1
1065 && [&]() {
1066 return Helper.matchConstantFold(*MIs[0], MatchData90);
1067 return true;
1068 }() ) {
1069 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
1070 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
1071 return true;
1072 }
1073 }
1074 // Leaf name: commute_constant_to_rhs
1075 // Rule: commute_constant_to_rhs
1076 if (!RuleConfig->isRuleDisabled(110)) {
1077 if (1
1078 && [&]() {
1079
1080 return getIConstantVRegVal(MIs[0]->getOperand(1).getReg(), MRI).has_value();
1081
1082 return true;
1083 }() ) {
1084 LLVM_DEBUG(dbgs() << "Applying rule 'commute_constant_to_rhs'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'commute_constant_to_rhs'\n"
; } } while (false)
;
1085
1086 Observer.changingInstr(*MIs[0]);
1087 Register LHSReg = MIs[0]->getOperand(1).getReg();
1088 Register RHSReg = MIs[0]->getOperand(2).getReg();
1089 MIs[0]->getOperand(1).setReg(RHSReg);
1090 MIs[0]->getOperand(2).setReg(LHSReg);
1091 Observer.changedInstr(*MIs[0]);
1092
1093 return true;
1094 }
1095 }
1096 return false;
1097 }
1098 if (Partition == 2 /* TargetOpcode::G_ADD */) {
1099 // Leaf name: add_p2i_to_ptradd
1100 // Rule: add_p2i_to_ptradd
1101 if (!RuleConfig->isRuleDisabled(2)) {
1102 if (1
1103 && [&]() {
1104 return Helper.matchCombineAddP2IToPtrAdd(*MIs[0], MatchData2);
1105 return true;
1106 }() ) {
1107 LLVM_DEBUG(dbgs() << "Applying rule 'add_p2i_to_ptradd'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'add_p2i_to_ptradd'\n"
; } } while (false)
;
1108 Helper.applyCombineAddP2IToPtrAdd(*MIs[0], MatchData2);
1109 return true;
1110 }
1111 }
1112 // Leaf name: propagate_undef_any_op
1113 // Rule: propagate_undef_any_op
1114 if (!RuleConfig->isRuleDisabled(17)) {
1115 if (1
1116 && [&]() {
1117 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1118 return true;
1119 }() ) {
1120 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
1121 Helper.replaceInstWithUndef(*MIs[0]);
1122 return true;
1123 }
1124 }
1125 // Leaf name: right_identity_zero
1126 // Rule: right_identity_zero
1127 if (!RuleConfig->isRuleDisabled(24)) {
1128 if (1
1129 && [&]() {
1130 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
1131 return true;
1132 }() ) {
1133 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
1134 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1135 return true;
1136 }
1137 }
1138 // Leaf name: add_sub_reg
1139 // Rule: add_sub_reg
1140 if (!RuleConfig->isRuleDisabled(33)) {
1141 if (1
1142 && [&]() {
1143 return Helper.matchAddSubSameReg(*MIs[0], MatchData33);
1144 return true;
1145 }() ) {
1146 LLVM_DEBUG(dbgs() << "Applying rule 'add_sub_reg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'add_sub_reg'\n"
; } } while (false)
;
1147 return Helper.replaceSingleDefInstWithReg(*MIs[0],
1148 MatchData33);
1149 return true;
1150 }
1151 }
1152 // Leaf name: simplify_add_to_sub
1153 // Rule: simplify_add_to_sub
1154 if (!RuleConfig->isRuleDisabled(39)) {
1155 if (1
1156 && [&]() {
1157 return Helper.matchSimplifyAddToSub(*MIs[0], MatchData39);
1158 return true;
1159 }() ) {
1160 LLVM_DEBUG(dbgs() << "Applying rule 'simplify_add_to_sub'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'simplify_add_to_sub'\n"
; } } while (false)
;
1161 Helper.applySimplifyAddToSub(*MIs[0], MatchData39);
1162 return true;
1163 }
1164 }
1165 // Leaf name: constant_fold
1166 // Rule: constant_fold
1167 if (!RuleConfig->isRuleDisabled(90)) {
1168 if (1
1169 && [&]() {
1170 return Helper.matchConstantFold(*MIs[0], MatchData90);
1171 return true;
1172 }() ) {
1173 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
1174 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
1175 return true;
1176 }
1177 }
1178 // Leaf name: fold_binop_into_select
1179 // Rule: fold_binop_into_select
1180 if (!RuleConfig->isRuleDisabled(105)) {
1181 if (1
1182 && [&]() {
1183 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
1184 return true;
1185 }() ) {
1186 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
1187 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
1188 return true;
1189 }
1190 }
1191 // Leaf name: commute_constant_to_rhs
1192 // Rule: commute_constant_to_rhs
1193 if (!RuleConfig->isRuleDisabled(110)) {
1194 if (1
1195 && [&]() {
1196
1197 return getIConstantVRegVal(MIs[0]->getOperand(1).getReg(), MRI).has_value();
1198
1199 return true;
1200 }() ) {
1201 LLVM_DEBUG(dbgs() << "Applying rule 'commute_constant_to_rhs'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'commute_constant_to_rhs'\n"
; } } while (false)
;
1202
1203 Observer.changingInstr(*MIs[0]);
1204 Register LHSReg = MIs[0]->getOperand(1).getReg();
1205 Register RHSReg = MIs[0]->getOperand(2).getReg();
1206 MIs[0]->getOperand(1).setReg(RHSReg);
1207 MIs[0]->getOperand(2).setReg(LHSReg);
1208 Observer.changedInstr(*MIs[0]);
1209
1210 return true;
1211 }
1212 }
1213 return false;
1214 }
1215 if (Partition == 3 /* TargetOpcode::G_FREEZE */) {
1216 // Leaf name: idempotent_prop
1217 // Rule: idempotent_prop
1218 if (!RuleConfig->isRuleDisabled(4)) {
1219 if (1
1220 && [&]() {
1221 return MRI.getVRegDef(MIs[0]->getOperand(1).getReg())->getOpcode() ==
1222 MIs[0]->getOpcode();
1223 return true;
1224 }() ) {
1225 LLVM_DEBUG(dbgs() << "Applying rule 'idempotent_prop'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'idempotent_prop'\n"
; } } while (false)
;
1226 Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1227 return true;
1228 }
1229 }
1230 return false;
1231 }
1232 if (Partition == 4 /* TargetOpcode::G_FABS */) {
1233 // Leaf name: idempotent_prop
1234 // Rule: idempotent_prop
1235 if (!RuleConfig->isRuleDisabled(4)) {
1236 if (1
1237 && [&]() {
1238 return MRI.getVRegDef(MIs[0]->getOperand(1).getReg())->getOpcode() ==
1239 MIs[0]->getOpcode();
1240 return true;
1241 }() ) {
1242 LLVM_DEBUG(dbgs() << "Applying rule 'idempotent_prop'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'idempotent_prop'\n"
; } } while (false)
;
1243 Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1244 return true;
1245 }
1246 }
1247 // Leaf name: constant_fp_op
1248 // Rule: constant_fp_op
1249 if (!RuleConfig->isRuleDisabled(69)) {
1250 if (1
1251 && [&]() {
1252 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
1253 return true;
1254 }() ) {
1255 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
1256 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
1257 return true;
1258 }
1259 }
1260 // Leaf name: fabs_fneg_fold
1261 // Rule: fabs_fneg_fold
1262 if (!RuleConfig->isRuleDisabled(91)) {
1263 if (1
1264 && [&]() {
1265 return Helper.matchCombineFAbsOfFNeg(*MIs[0], MatchData91);
1266 return true;
1267 }() ) {
1268 LLVM_DEBUG(dbgs() << "Applying rule 'fabs_fneg_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fabs_fneg_fold'\n"
; } } while (false)
;
1269 Helper.applyBuildFnNoErase(*MIs[0], MatchData91);
1270 return true;
1271 }
1272 }
1273 return false;
1274 }
1275 if (Partition == 5 /* TargetOpcode::G_FCANONICALIZE */) {
1276 // Leaf name: idempotent_prop
1277 // Rule: idempotent_prop
1278 if (!RuleConfig->isRuleDisabled(4)) {
1279 if (1
1280 && [&]() {
1281 return MRI.getVRegDef(MIs[0]->getOperand(1).getReg())->getOpcode() ==
1282 MIs[0]->getOpcode();
1283 return true;
1284 }() ) {
1285 LLVM_DEBUG(dbgs() << "Applying rule 'idempotent_prop'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'idempotent_prop'\n"
; } } while (false)
;
1286 Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1287 return true;
1288 }
1289 }
1290 return false;
1291 }
1292 if (Partition == 6 /* TargetOpcode::G_INSERT_VECTOR_ELT */) {
1293 // Leaf name: combine_insert_vec_elts_build_vector
1294 // Rule: combine_insert_vec_elts_build_vector
1295 if (!RuleConfig->isRuleDisabled(5)) {
1296 if (1
1297 && [&]() {
1298 return Helper.matchCombineInsertVecElts(*MIs[0], MatchData5);
1299 return true;
1300 }() ) {
1301 LLVM_DEBUG(dbgs() << "Applying rule 'combine_insert_vec_elts_build_vector'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_insert_vec_elts_build_vector'\n"
; } } while (false)
;
1302 Helper.applyCombineInsertVecElts(*MIs[0], MatchData5);
1303 return true;
1304 }
1305 }
1306 // Leaf name: insert_extract_vec_elt_out_of_bounds
1307 // Rule: insert_extract_vec_elt_out_of_bounds
1308 if (!RuleConfig->isRuleDisabled(22)) {
1309 if (1
1310 && [&]() {
1311 return Helper.matchInsertExtractVecEltOutOfBounds(*MIs[0]);
1312 return true;
1313 }() ) {
1314 LLVM_DEBUG(dbgs() << "Applying rule 'insert_extract_vec_elt_out_of_bounds'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'insert_extract_vec_elt_out_of_bounds'\n"
; } } while (false)
;
1315 Helper.replaceInstWithUndef(*MIs[0]);
1316 return true;
1317 }
1318 }
1319 return false;
1320 }
1321 if (Partition == 7 /* TargetOpcode::G_EXTRACT_VECTOR_ELT */) {
1322 // Leaf name: extract_vec_elt_build_vec
1323 // Rule: extract_vec_elt_build_vec
1324 if (!RuleConfig->isRuleDisabled(6)) {
1325 if (1
1326 && [&]() {
1327 return Helper.matchExtractVecEltBuildVec(*MIs[0], MatchData6);
1328 return true;
1329 }() ) {
1330 LLVM_DEBUG(dbgs() << "Applying rule 'extract_vec_elt_build_vec'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extract_vec_elt_build_vec'\n"
; } } while (false)
;
1331 Helper.applyExtractVecEltBuildVec(*MIs[0], MatchData6);
1332 return true;
1333 }
1334 }
1335 // Leaf name: insert_extract_vec_elt_out_of_bounds
1336 // Rule: insert_extract_vec_elt_out_of_bounds
1337 if (!RuleConfig->isRuleDisabled(22)) {
1338 if (1
1339 && [&]() {
1340 return Helper.matchInsertExtractVecEltOutOfBounds(*MIs[0]);
1341 return true;
1342 }() ) {
1343 LLVM_DEBUG(dbgs() << "Applying rule 'insert_extract_vec_elt_out_of_bounds'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'insert_extract_vec_elt_out_of_bounds'\n"
; } } while (false)
;
1344 Helper.replaceInstWithUndef(*MIs[0]);
1345 return true;
1346 }
1347 }
1348 return false;
1349 }
1350 if (Partition == 8 /* TargetOpcode::G_BUILD_VECTOR */) {
1351 // Leaf name: extract_all_elts_from_build_vector
1352 // Rule: extract_all_elts_from_build_vector
1353 if (!RuleConfig->isRuleDisabled(7)) {
1354 if (1
1355 && [&]() {
1356 return Helper.matchExtractAllEltsFromBuildVector(*MIs[0], MatchData7);
1357 return true;
1358 }() ) {
1359 LLVM_DEBUG(dbgs() << "Applying rule 'extract_all_elts_from_build_vector'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extract_all_elts_from_build_vector'\n"
; } } while (false)
;
1360 Helper.applyExtractAllEltsFromBuildVector(*MIs[0], MatchData7);
1361 return true;
1362 }
1363 }
1364 // Leaf name: buildvector_identity_fold
1365 // Rule: buildvector_identity_fold
1366 if (!RuleConfig->isRuleDisabled(34)) {
1367 if (1
1368 && [&]() {
1369 return Helper.matchBuildVectorIdentityFold(*MIs[0], MatchData34);
1370 return true;
1371 }() ) {
1372 LLVM_DEBUG(dbgs() << "Applying rule 'buildvector_identity_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'buildvector_identity_fold'\n"
; } } while (false)
;
1373 Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData34);
1374 return true;
1375 }
1376 }
1377 return false;
1378 }
1379 if (Partition == 9 /* TargetOpcode::G_LOAD */) {
1380 // Leaf name: extending_loads
1381 // Rule: extending_loads
1382 if (!RuleConfig->isRuleDisabled(8)) {
1383 if (1
1384 && [&]() {
1385 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData8);
1386 return true;
1387 }() ) {
1388 LLVM_DEBUG(dbgs() << "Applying rule 'extending_loads'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extending_loads'\n"
; } } while (false)
;
1389 Helper.applyCombineExtendingLoads(*MIs[0], MatchData8);
1390 return true;
1391 }
1392 }
1393 // Leaf name: combine_indexed_load_store
1394 // Rule: combine_indexed_load_store
1395 if (!RuleConfig->isRuleDisabled(10)) {
1396 if (1
1397 && [&]() {
1398 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData10);
1399 return true;
1400 }() ) {
1401 LLVM_DEBUG(dbgs() << "Applying rule 'combine_indexed_load_store'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_indexed_load_store'\n"
; } } while (false)
;
1402 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData10);
1403 return true;
1404 }
1405 }
1406 return false;
1407 }
1408 if (Partition == 10 /* TargetOpcode::G_SEXTLOAD */) {
1409 // Leaf name: extending_loads
1410 // Rule: extending_loads
1411 if (!RuleConfig->isRuleDisabled(8)) {
1412 if (1
1413 && [&]() {
1414 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData8);
1415 return true;
1416 }() ) {
1417 LLVM_DEBUG(dbgs() << "Applying rule 'extending_loads'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extending_loads'\n"
; } } while (false)
;
1418 Helper.applyCombineExtendingLoads(*MIs[0], MatchData8);
1419 return true;
1420 }
1421 }
1422 // Leaf name: combine_indexed_load_store
1423 // Rule: combine_indexed_load_store
1424 if (!RuleConfig->isRuleDisabled(10)) {
1425 if (1
1426 && [&]() {
1427 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData10);
1428 return true;
1429 }() ) {
1430 LLVM_DEBUG(dbgs() << "Applying rule 'combine_indexed_load_store'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_indexed_load_store'\n"
; } } while (false)
;
1431 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData10);
1432 return true;
1433 }
1434 }
1435 return false;
1436 }
1437 if (Partition == 11 /* TargetOpcode::G_ZEXTLOAD */) {
1438 // Leaf name: extending_loads
1439 // Rule: extending_loads
1440 if (!RuleConfig->isRuleDisabled(8)) {
1441 if (1
1442 && [&]() {
1443 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData8);
1444 return true;
1445 }() ) {
1446 LLVM_DEBUG(dbgs() << "Applying rule 'extending_loads'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extending_loads'\n"
; } } while (false)
;
1447 Helper.applyCombineExtendingLoads(*MIs[0], MatchData8);
1448 return true;
1449 }
1450 }
1451 // Leaf name: combine_indexed_load_store
1452 // Rule: combine_indexed_load_store
1453 if (!RuleConfig->isRuleDisabled(10)) {
1454 if (1
1455 && [&]() {
1456 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData10);
1457 return true;
1458 }() ) {
1459 LLVM_DEBUG(dbgs() << "Applying rule 'combine_indexed_load_store'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_indexed_load_store'\n"
; } } while (false)
;
1460 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData10);
1461 return true;
1462 }
1463 }
1464 return false;
1465 }
1466 if (Partition == 12 /* TargetOpcode::G_AND */) {
1467 // Leaf name: load_and_mask
1468 // Rule: load_and_mask
1469 if (!RuleConfig->isRuleDisabled(9)) {
1470 if (1
1471 && [&]() {
1472 return Helper.matchCombineLoadWithAndMask(*MIs[0], MatchData9);
1473 return true;
1474 }() ) {
1475 LLVM_DEBUG(dbgs() << "Applying rule 'load_and_mask'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'load_and_mask'\n"
; } } while (false)
;
1476 Helper.applyBuildFn(*MIs[0], MatchData9);
1477 return true;
1478 }
1479 }
1480 // Leaf name: undef_to_int_zero
1481 // Rule: undef_to_int_zero
1482 if (!RuleConfig->isRuleDisabled(12)) {
1483 if (1
1484 && [&]() {
1485 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1486 return true;
1487 }() ) {
1488 LLVM_DEBUG(dbgs() << "Applying rule 'undef_to_int_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'undef_to_int_zero'\n"
; } } while (false)
;
1489 Helper.replaceInstWithConstant(*MIs[0], 0);
1490 return true;
1491 }
1492 }
1493 // Leaf name: binop_same_val
1494 // Rule: binop_same_val
1495 if (!RuleConfig->isRuleDisabled(25)) {
1496 if (1
1497 && [&]() {
1498 return Helper.matchBinOpSameVal(*MIs[0]);
1499 return true;
1500 }() ) {
1501 LLVM_DEBUG(dbgs() << "Applying rule 'binop_same_val'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_same_val'\n"
; } } while (false)
;
1502 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1503 return true;
1504 }
1505 }
1506 // Leaf name: hoist_logic_op_with_same_opcode_hands
1507 // Rule: hoist_logic_op_with_same_opcode_hands
1508 if (!RuleConfig->isRuleDisabled(40)) {
1509 if (1
1510 && [&]() {
1511 return Helper.matchHoistLogicOpWithSameOpcodeHands(*MIs[0], MatchData40);
1512 return true;
1513 }() ) {
1514 LLVM_DEBUG(dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n"
; } } while (false)
;
1515 Helper.applyBuildInstructionSteps(*MIs[0], MatchData40);
1516 return true;
1517 }
1518 }
1519 // Leaf name: narrow_binop_feeding_and
1520 // Rule: narrow_binop_feeding_and
1521 if (!RuleConfig->isRuleDisabled(47)) {
1522 if (1
1523 && [&]() {
1524 return Helper.matchNarrowBinopFeedingAnd(*MIs[0], MatchData47);
1525 return true;
1526 }() ) {
1527 LLVM_DEBUG(dbgs() << "Applying rule 'narrow_binop_feeding_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'narrow_binop_feeding_and'\n"
; } } while (false)
;
1528 Helper.applyBuildFnNoErase(*MIs[0], MatchData47);
1529 return true;
1530 }
1531 }
1532 // Leaf name: redundant_and
1533 // Rule: redundant_and
1534 if (!RuleConfig->isRuleDisabled(51)) {
1535 if (1
1536 && [&]() {
1537 return Helper.matchRedundantAnd(*MIs[0], MatchData51);
1538 return true;
1539 }() ) {
1540 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_and'\n"
; } } while (false)
;
1541 return Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData51);
1542 return true;
1543 }
1544 }
1545 // Leaf name: overlapping_and
1546 // Rule: overlapping_and
1547 if (!RuleConfig->isRuleDisabled(71)) {
1548 if (1
1549 && [&]() {
1550 return Helper.matchOverlappingAnd(*MIs[0], MatchData71);
1551 return true;
1552 }() ) {
1553 LLVM_DEBUG(dbgs() << "Applying rule 'overlapping_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'overlapping_and'\n"
; } } while (false)
;
1554 Helper.applyBuildFn(*MIs[0], MatchData71);
1555 return true;
1556 }
1557 }
1558 // Leaf name: bitfield_extract_from_and
1559 // Rule: bitfield_extract_from_and
1560 if (!RuleConfig->isRuleDisabled(87)) {
1561 if (1
1562 && [&]() {
1563 return Helper.matchBitfieldExtractFromAnd(*MIs[0], MatchData87);
1564 return true;
1565 }() ) {
1566 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_and'\n"
; } } while (false)
;
1567 Helper.applyBuildFn(*MIs[0], MatchData87);
1568 return true;
1569 }
1570 }
1571 // Leaf name: constant_fold
1572 // Rule: constant_fold
1573 if (!RuleConfig->isRuleDisabled(90)) {
1574 if (1
1575 && [&]() {
1576 return Helper.matchConstantFold(*MIs[0], MatchData90);
1577 return true;
1578 }() ) {
1579 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
1580 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
1581 return true;
1582 }
1583 }
1584 // Leaf name: and_or_disjoint_mask
1585 // Rule: and_or_disjoint_mask
1586 if (!RuleConfig->isRuleDisabled(96)) {
1587 if (1
1588 && [&]() {
1589 return Helper.matchAndOrDisjointMask(*MIs[0], MatchData96);
1590 return true;
1591 }() ) {
1592 LLVM_DEBUG(dbgs() << "Applying rule 'and_or_disjoint_mask'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'and_or_disjoint_mask'\n"
; } } while (false)
;
1593 Helper.applyBuildFnNoErase(*MIs[0], MatchData96);
1594 return true;
1595 }
1596 }
1597 // Leaf name: fold_binop_into_select
1598 // Rule: fold_binop_into_select
1599 if (!RuleConfig->isRuleDisabled(105)) {
1600 if (1
1601 && [&]() {
1602 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
1603 return true;
1604 }() ) {
1605 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
1606 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
1607 return true;
1608 }
1609 }
1610 // Leaf name: commute_constant_to_rhs
1611 // Rule: commute_constant_to_rhs
1612 if (!RuleConfig->isRuleDisabled(110)) {
1613 if (1
1614 && [&]() {
1615
1616 return getIConstantVRegVal(MIs[0]->getOperand(1).getReg(), MRI).has_value();
1617
1618 return true;
1619 }() ) {
1620 LLVM_DEBUG(dbgs() << "Applying rule 'commute_constant_to_rhs'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'commute_constant_to_rhs'\n"
; } } while (false)
;
1621
1622 Observer.changingInstr(*MIs[0]);
1623 Register LHSReg = MIs[0]->getOperand(1).getReg();
1624 Register RHSReg = MIs[0]->getOperand(2).getReg();
1625 MIs[0]->getOperand(1).setReg(RHSReg);
1626 MIs[0]->getOperand(2).setReg(LHSReg);
1627 Observer.changedInstr(*MIs[0]);
1628
1629 return true;
1630 }
1631 }
1632 return false;
1633 }
1634 if (Partition == 13 /* TargetOpcode::G_STORE */) {
1635 // Leaf name: combine_indexed_load_store
1636 // Rule: combine_indexed_load_store
1637 if (!RuleConfig->isRuleDisabled(10)) {
1638 if (1
1639 && [&]() {
1640 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData10);
1641 return true;
1642 }() ) {
1643 LLVM_DEBUG(dbgs() << "Applying rule 'combine_indexed_load_store'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_indexed_load_store'\n"
; } } while (false)
;
1644 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData10);
1645 return true;
1646 }
1647 }
1648 // Leaf name: erase_undef_store
1649 // Rule: erase_undef_store
1650 if (!RuleConfig->isRuleDisabled(20)) {
1651 if (1
1652 && [&]() {
1653 return Helper.matchUndefStore(*MIs[0]);
1654 return true;
1655 }() ) {
1656 LLVM_DEBUG(dbgs() << "Applying rule 'erase_undef_store'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'erase_undef_store'\n"
; } } while (false)
;
1657 return Helper.eraseInst(*MIs[0]);
1658 return true;
1659 }
1660 }
1661 // Leaf name: truncstore_merge
1662 // Rule: truncstore_merge
1663 if (!RuleConfig->isRuleDisabled(82)) {
1664 if (1
1665 && [&]() {
1666 return Helper.matchTruncStoreMerge(*MIs[0], MatchData82);
1667 return true;
1668 }() ) {
1669 LLVM_DEBUG(dbgs() << "Applying rule 'truncstore_merge'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'truncstore_merge'\n"
; } } while (false)
;
1670 Helper.applyTruncStoreMerge(*MIs[0], MatchData82);
1671 return true;
1672 }
1673 }
1674 return false;
1675 }
1676 if (Partition == 14 /* TargetOpcode::G_UITOFP */) {
1677 // Leaf name: undef_to_fp_zero
1678 // Rule: undef_to_fp_zero
1679 if (!RuleConfig->isRuleDisabled(11)) {
1680 if (1
1681 && [&]() {
1682 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1683 return true;
1684 }() ) {
1685 LLVM_DEBUG(dbgs() << "Applying rule 'undef_to_fp_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'undef_to_fp_zero'\n"
; } } while (false)
;
1686 Helper.replaceInstWithFConstant(*MIs[0], 0.0);
1687 return true;
1688 }
1689 }
1690 return false;
1691 }
1692 if (Partition == 15 /* TargetOpcode::G_SITOFP */) {
1693 // Leaf name: undef_to_fp_zero
1694 // Rule: undef_to_fp_zero
1695 if (!RuleConfig->isRuleDisabled(11)) {
1696 if (1
1697 && [&]() {
1698 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1699 return true;
1700 }() ) {
1701 LLVM_DEBUG(dbgs() << "Applying rule 'undef_to_fp_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'undef_to_fp_zero'\n"
; } } while (false)
;
1702 Helper.replaceInstWithFConstant(*MIs[0], 0.0);
1703 return true;
1704 }
1705 }
1706 return false;
1707 }
1708 if (Partition == 16 /* TargetOpcode::G_OR */) {
1709 // Leaf name: undef_to_negative_one
1710 // Rule: undef_to_negative_one
1711 if (!RuleConfig->isRuleDisabled(13)) {
1712 if (1
1713 && [&]() {
1714 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
1715 return true;
1716 }() ) {
1717 LLVM_DEBUG(dbgs() << "Applying rule 'undef_to_negative_one'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'undef_to_negative_one'\n"
; } } while (false)
;
1718 Helper.replaceInstWithConstant(*MIs[0], -1);
1719 return true;
1720 }
1721 }
1722 // Leaf name: right_identity_zero
1723 // Rule: right_identity_zero
1724 if (!RuleConfig->isRuleDisabled(24)) {
1725 if (1
1726 && [&]() {
1727 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
1728 return true;
1729 }() ) {
1730 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
1731 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1732 return true;
1733 }
1734 }
1735 // Leaf name: binop_same_val
1736 // Rule: binop_same_val
1737 if (!RuleConfig->isRuleDisabled(25)) {
1738 if (1
1739 && [&]() {
1740 return Helper.matchBinOpSameVal(*MIs[0]);
1741 return true;
1742 }() ) {
1743 LLVM_DEBUG(dbgs() << "Applying rule 'binop_same_val'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_same_val'\n"
; } } while (false)
;
1744 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1745 return true;
1746 }
1747 }
1748 // Leaf name: hoist_logic_op_with_same_opcode_hands
1749 // Rule: hoist_logic_op_with_same_opcode_hands
1750 if (!RuleConfig->isRuleDisabled(40)) {
1751 if (1
1752 && [&]() {
1753 return Helper.matchHoistLogicOpWithSameOpcodeHands(*MIs[0], MatchData40);
1754 return true;
1755 }() ) {
1756 LLVM_DEBUG(dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n"
; } } while (false)
;
1757 Helper.applyBuildInstructionSteps(*MIs[0], MatchData40);
1758 return true;
1759 }
1760 }
1761 // Leaf name: redundant_or
1762 // Rule: redundant_or
1763 if (!RuleConfig->isRuleDisabled(53)) {
1764 if (1
1765 && [&]() {
1766 return Helper.matchRedundantOr(*MIs[0], MatchData53);
1767 return true;
1768 }() ) {
1769 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_or'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_or'\n"
; } } while (false)
;
1770 return Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData53);
1771 return true;
1772 }
1773 }
1774 // Leaf name: load_or_combine
1775 // Rule: load_or_combine
1776 if (!RuleConfig->isRuleDisabled(81)) {
1777 if (1
1778 && [&]() {
1779 return Helper.matchLoadOrCombine(*MIs[0], MatchData81);
1780 return true;
1781 }() ) {
1782 LLVM_DEBUG(dbgs() << "Applying rule 'load_or_combine'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'load_or_combine'\n"
; } } while (false)
;
1783 Helper.applyBuildFn(*MIs[0], MatchData81);
1784 return true;
1785 }
1786 }
1787 // Leaf name: funnel_shift_from_or_shift
1788 // Rule: funnel_shift_from_or_shift
1789 if (!RuleConfig->isRuleDisabled(84)) {
1790 if (1
1791 && [&]() {
1792 return Helper.matchOrShiftToFunnelShift(*MIs[0], MatchData84);
1793 return true;
1794 }() ) {
1795 LLVM_DEBUG(dbgs() << "Applying rule 'funnel_shift_from_or_shift'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'funnel_shift_from_or_shift'\n"
; } } while (false)
;
1796 Helper.applyBuildFn(*MIs[0], MatchData84);
1797 return true;
1798 }
1799 }
1800 // Leaf name: constant_fold
1801 // Rule: constant_fold
1802 if (!RuleConfig->isRuleDisabled(90)) {
1803 if (1
1804 && [&]() {
1805 return Helper.matchConstantFold(*MIs[0], MatchData90);
1806 return true;
1807 }() ) {
1808 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
1809 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
1810 return true;
1811 }
1812 }
1813 // Leaf name: fold_binop_into_select
1814 // Rule: fold_binop_into_select
1815 if (!RuleConfig->isRuleDisabled(105)) {
1816 if (1
1817 && [&]() {
1818 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
1819 return true;
1820 }() ) {
1821 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
1822 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
1823 return true;
1824 }
1825 }
1826 // Leaf name: commute_constant_to_rhs
1827 // Rule: commute_constant_to_rhs
1828 if (!RuleConfig->isRuleDisabled(110)) {
1829 if (1
1830 && [&]() {
1831
1832 return getIConstantVRegVal(MIs[0]->getOperand(1).getReg(), MRI).has_value();
1833
1834 return true;
1835 }() ) {
1836 LLVM_DEBUG(dbgs() << "Applying rule 'commute_constant_to_rhs'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'commute_constant_to_rhs'\n"
; } } while (false)
;
1837
1838 Observer.changingInstr(*MIs[0]);
1839 Register LHSReg = MIs[0]->getOperand(1).getReg();
1840 Register RHSReg = MIs[0]->getOperand(2).getReg();
1841 MIs[0]->getOperand(1).setReg(RHSReg);
1842 MIs[0]->getOperand(2).setReg(LHSReg);
1843 Observer.changedInstr(*MIs[0]);
1844
1845 return true;
1846 }
1847 }
1848 return false;
1849 }
1850 if (Partition == 17 /* TargetOpcode::G_SHL */) {
1851 // Leaf name: binop_left_undef_to_zero
1852 // Rule: binop_left_undef_to_zero
1853 if (!RuleConfig->isRuleDisabled(14)) {
1854 if (1
1855 && [&]() {
1856 return Helper.matchOperandIsUndef(*MIs[0], 1);
1857 return true;
1858 }() ) {
1859 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_undef_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_undef_to_zero'\n"
; } } while (false)
;
1860 Helper.replaceInstWithConstant(*MIs[0], 0);
1861 return true;
1862 }
1863 }
1864 // Leaf name: binop_right_undef_to_undef
1865 // Rule: binop_right_undef_to_undef
1866 if (!RuleConfig->isRuleDisabled(15)) {
1867 if (1
1868 && [&]() {
1869 return Helper.matchOperandIsUndef(*MIs[0], 2);
1870 return true;
1871 }() ) {
1872 LLVM_DEBUG(dbgs() << "Applying rule 'binop_right_undef_to_undef'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_right_undef_to_undef'\n"
; } } while (false)
;
1873 Helper.replaceInstWithUndef(*MIs[0]);
1874 return true;
1875 }
1876 }
1877 // Leaf name: right_identity_zero
1878 // Rule: right_identity_zero
1879 if (!RuleConfig->isRuleDisabled(24)) {
1880 if (1
1881 && [&]() {
1882 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
1883 return true;
1884 }() ) {
1885 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
1886 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1887 return true;
1888 }
1889 }
1890 // Leaf name: shifts_too_big
1891 // Rule: shifts_too_big
1892 if (!RuleConfig->isRuleDisabled(41)) {
1893 if (1
1894 && [&]() {
1895 return Helper.matchShiftsTooBig(*MIs[0]);
1896 return true;
1897 }() ) {
1898 LLVM_DEBUG(dbgs() << "Applying rule 'shifts_too_big'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shifts_too_big'\n"
; } } while (false)
;
1899 Helper.replaceInstWithUndef(*MIs[0]);
1900 return true;
1901 }
1902 }
1903 // Leaf name: reduce_shl_of_extend
1904 // Rule: reduce_shl_of_extend
1905 if (!RuleConfig->isRuleDisabled(46)) {
1906 if (1
1907 && [&]() {
1908 return Helper.matchCombineShlOfExtend(*MIs[0], MatchData46);
1909 return true;
1910 }() ) {
1911 LLVM_DEBUG(dbgs() << "Applying rule 'reduce_shl_of_extend'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'reduce_shl_of_extend'\n"
; } } while (false)
;
1912 Helper.applyCombineShlOfExtend(*MIs[0], MatchData46);
1913 return true;
1914 }
1915 }
1916 // Leaf name: shift_immed_chain
1917 // Rule: shift_immed_chain
1918 if (!RuleConfig->isRuleDisabled(79)) {
1919 if (1
1920 && [&]() {
1921 return Helper.matchShiftImmedChain(*MIs[0], MatchData79);
1922 return true;
1923 }() ) {
1924 LLVM_DEBUG(dbgs() << "Applying rule 'shift_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_immed_chain'\n"
; } } while (false)
;
1925 Helper.applyShiftImmedChain(*MIs[0], MatchData79);
1926 return true;
1927 }
1928 }
1929 // Leaf name: shift_of_shifted_logic_chain
1930 // Rule: shift_of_shifted_logic_chain
1931 if (!RuleConfig->isRuleDisabled(80)) {
1932 if (1
1933 && [&]() {
1934 return Helper.matchShiftOfShiftedLogic(*MIs[0], MatchData80);
1935 return true;
1936 }() ) {
1937 LLVM_DEBUG(dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n"
; } } while (false)
;
1938 Helper.applyShiftOfShiftedLogic(*MIs[0], MatchData80);
1939 return true;
1940 }
1941 }
1942 // Leaf name: fold_binop_into_select
1943 // Rule: fold_binop_into_select
1944 if (!RuleConfig->isRuleDisabled(105)) {
1945 if (1
1946 && [&]() {
1947 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
1948 return true;
1949 }() ) {
1950 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
1951 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
1952 return true;
1953 }
1954 }
1955 return false;
1956 }
1957 if (Partition == 18 /* TargetOpcode::G_UDIV */) {
1958 // Leaf name: binop_left_undef_to_zero
1959 // Rule: binop_left_undef_to_zero
1960 if (!RuleConfig->isRuleDisabled(14)) {
1961 if (1
1962 && [&]() {
1963 return Helper.matchOperandIsUndef(*MIs[0], 1);
1964 return true;
1965 }() ) {
1966 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_undef_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_undef_to_zero'\n"
; } } while (false)
;
1967 Helper.replaceInstWithConstant(*MIs[0], 0);
1968 return true;
1969 }
1970 }
1971 // Leaf name: binop_left_to_zero
1972 // Rule: binop_left_to_zero
1973 if (!RuleConfig->isRuleDisabled(26)) {
1974 if (1
1975 && [&]() {
1976 return Helper.matchOperandIsZero(*MIs[0], 1);
1977 return true;
1978 }() ) {
1979 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_to_zero'\n"
; } } while (false)
;
1980 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
1981 return true;
1982 }
1983 }
1984 // Leaf name: div_rem_to_divrem
1985 // Rule: div_rem_to_divrem
1986 if (!RuleConfig->isRuleDisabled(83)) {
1987 if (1
1988 && [&]() {
1989 return Helper.matchCombineDivRem(*MIs[0], MatchData83);
1990 return true;
1991 }() ) {
1992 LLVM_DEBUG(dbgs() << "Applying rule 'div_rem_to_divrem'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'div_rem_to_divrem'\n"
; } } while (false)
;
1993 Helper.applyCombineDivRem(*MIs[0], MatchData83);
1994 return true;
1995 }
1996 }
1997 // Leaf name: udiv_by_const
1998 // Rule: udiv_by_const
1999 if (!RuleConfig->isRuleDisabled(92)) {
2000 if (1
2001 && [&]() {
2002 return Helper.matchUDivByConst(*MIs[0]);
2003 return true;
2004 }() ) {
2005 LLVM_DEBUG(dbgs() << "Applying rule 'udiv_by_const'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'udiv_by_const'\n"
; } } while (false)
;
2006 Helper.applyUDivByConst(*MIs[0]);
2007 return true;
2008 }
2009 }
2010 // Leaf name: fold_binop_into_select
2011 // Rule: fold_binop_into_select
2012 if (!RuleConfig->isRuleDisabled(105)) {
2013 if (1
2014 && [&]() {
2015 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2016 return true;
2017 }() ) {
2018 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2019 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2020 return true;
2021 }
2022 }
2023 return false;
2024 }
2025 if (Partition == 19 /* TargetOpcode::G_UREM */) {
2026 // Leaf name: binop_left_undef_to_zero
2027 // Rule: binop_left_undef_to_zero
2028 if (!RuleConfig->isRuleDisabled(14)) {
2029 if (1
2030 && [&]() {
2031 return Helper.matchOperandIsUndef(*MIs[0], 1);
2032 return true;
2033 }() ) {
2034 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_undef_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_undef_to_zero'\n"
; } } while (false)
;
2035 Helper.replaceInstWithConstant(*MIs[0], 0);
2036 return true;
2037 }
2038 }
2039 // Leaf name: binop_left_to_zero
2040 // Rule: binop_left_to_zero
2041 if (!RuleConfig->isRuleDisabled(26)) {
2042 if (1
2043 && [&]() {
2044 return Helper.matchOperandIsZero(*MIs[0], 1);
2045 return true;
2046 }() ) {
2047 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_to_zero'\n"
; } } while (false)
;
2048 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2049 return true;
2050 }
2051 }
2052 // Leaf name: urem_pow2_to_mask
2053 // Rule: urem_pow2_to_mask
2054 if (!RuleConfig->isRuleDisabled(54)) {
2055 if (1
2056 && [&]() {
2057 return Helper.matchOperandIsKnownToBeAPowerOfTwo(*MIs[0], 2);
2058 return true;
2059 }() ) {
2060 LLVM_DEBUG(dbgs() << "Applying rule 'urem_pow2_to_mask'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'urem_pow2_to_mask'\n"
; } } while (false)
;
2061 Helper.applySimplifyURemByPow2(*MIs[0]);
2062 return true;
2063 }
2064 }
2065 // Leaf name: div_rem_to_divrem
2066 // Rule: div_rem_to_divrem
2067 if (!RuleConfig->isRuleDisabled(83)) {
2068 if (1
2069 && [&]() {
2070 return Helper.matchCombineDivRem(*MIs[0], MatchData83);
2071 return true;
2072 }() ) {
2073 LLVM_DEBUG(dbgs() << "Applying rule 'div_rem_to_divrem'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'div_rem_to_divrem'\n"
; } } while (false)
;
2074 Helper.applyCombineDivRem(*MIs[0], MatchData83);
2075 return true;
2076 }
2077 }
2078 // Leaf name: fold_binop_into_select
2079 // Rule: fold_binop_into_select
2080 if (!RuleConfig->isRuleDisabled(105)) {
2081 if (1
2082 && [&]() {
2083 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2084 return true;
2085 }() ) {
2086 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2087 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2088 return true;
2089 }
2090 }
2091 return false;
2092 }
2093 if (Partition == 20 /* TargetOpcode::G_ASHR */) {
2094 // Leaf name: binop_right_undef_to_undef
2095 // Rule: binop_right_undef_to_undef
2096 if (!RuleConfig->isRuleDisabled(15)) {
2097 if (1
2098 && [&]() {
2099 return Helper.matchOperandIsUndef(*MIs[0], 2);
2100 return true;
2101 }() ) {
2102 LLVM_DEBUG(dbgs() << "Applying rule 'binop_right_undef_to_undef'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_right_undef_to_undef'\n"
; } } while (false)
;
2103 Helper.replaceInstWithUndef(*MIs[0]);
2104 return true;
2105 }
2106 }
2107 // Leaf name: right_identity_zero
2108 // Rule: right_identity_zero
2109 if (!RuleConfig->isRuleDisabled(24)) {
2110 if (1
2111 && [&]() {
2112 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2113 return true;
2114 }() ) {
2115 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2116 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2117 return true;
2118 }
2119 }
2120 // Leaf name: shifts_too_big
2121 // Rule: shifts_too_big
2122 if (!RuleConfig->isRuleDisabled(41)) {
2123 if (1
2124 && [&]() {
2125 return Helper.matchShiftsTooBig(*MIs[0]);
2126 return true;
2127 }() ) {
2128 LLVM_DEBUG(dbgs() << "Applying rule 'shifts_too_big'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shifts_too_big'\n"
; } } while (false)
;
2129 Helper.replaceInstWithUndef(*MIs[0]);
2130 return true;
2131 }
2132 }
2133 // Leaf name: shl_ashr_to_sext_inreg
2134 // Rule: shl_ashr_to_sext_inreg
2135 if (!RuleConfig->isRuleDisabled(44)) {
2136 if (1
2137 && [&]() {
2138 return Helper.matchAshrShlToSextInreg(*MIs[0], MatchData44);
2139 return true;
2140 }() ) {
2141 LLVM_DEBUG(dbgs() << "Applying rule 'shl_ashr_to_sext_inreg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shl_ashr_to_sext_inreg'\n"
; } } while (false)
;
2142 Helper.applyAshShlToSextInreg(*MIs[0], MatchData44);
2143 return true;
2144 }
2145 }
2146 // Leaf name: shift_immed_chain
2147 // Rule: shift_immed_chain
2148 if (!RuleConfig->isRuleDisabled(79)) {
2149 if (1
2150 && [&]() {
2151 return Helper.matchShiftImmedChain(*MIs[0], MatchData79);
2152 return true;
2153 }() ) {
2154 LLVM_DEBUG(dbgs() << "Applying rule 'shift_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_immed_chain'\n"
; } } while (false)
;
2155 Helper.applyShiftImmedChain(*MIs[0], MatchData79);
2156 return true;
2157 }
2158 }
2159 // Leaf name: shift_of_shifted_logic_chain
2160 // Rule: shift_of_shifted_logic_chain
2161 if (!RuleConfig->isRuleDisabled(80)) {
2162 if (1
2163 && [&]() {
2164 return Helper.matchShiftOfShiftedLogic(*MIs[0], MatchData80);
2165 return true;
2166 }() ) {
2167 LLVM_DEBUG(dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n"
; } } while (false)
;
2168 Helper.applyShiftOfShiftedLogic(*MIs[0], MatchData80);
2169 return true;
2170 }
2171 }
2172 // Leaf name: bitfield_extract_from_shr
2173 // Rule: bitfield_extract_from_shr
2174 if (!RuleConfig->isRuleDisabled(88)) {
2175 if (1
2176 && [&]() {
2177 return Helper.matchBitfieldExtractFromShr(*MIs[0], MatchData88);
2178 return true;
2179 }() ) {
2180 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_shr'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_shr'\n"
; } } while (false)
;
2181 Helper.applyBuildFn(*MIs[0], MatchData88);
2182 return true;
2183 }
2184 }
2185 // Leaf name: bitfield_extract_from_shr_and
2186 // Rule: bitfield_extract_from_shr_and
2187 if (!RuleConfig->isRuleDisabled(89)) {
2188 if (1
2189 && [&]() {
2190 return Helper.matchBitfieldExtractFromShrAnd(*MIs[0], MatchData89);
2191 return true;
2192 }() ) {
2193 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_shr_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_shr_and'\n"
; } } while (false)
;
2194 Helper.applyBuildFn(*MIs[0], MatchData89);
2195 return true;
2196 }
2197 }
2198 // Leaf name: fold_binop_into_select
2199 // Rule: fold_binop_into_select
2200 if (!RuleConfig->isRuleDisabled(105)) {
2201 if (1
2202 && [&]() {
2203 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2204 return true;
2205 }() ) {
2206 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2207 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2208 return true;
2209 }
2210 }
2211 return false;
2212 }
2213 if (Partition == 21 /* TargetOpcode::G_LSHR */) {
2214 // Leaf name: binop_right_undef_to_undef
2215 // Rule: binop_right_undef_to_undef
2216 if (!RuleConfig->isRuleDisabled(15)) {
2217 if (1
2218 && [&]() {
2219 return Helper.matchOperandIsUndef(*MIs[0], 2);
2220 return true;
2221 }() ) {
2222 LLVM_DEBUG(dbgs() << "Applying rule 'binop_right_undef_to_undef'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_right_undef_to_undef'\n"
; } } while (false)
;
2223 Helper.replaceInstWithUndef(*MIs[0]);
2224 return true;
2225 }
2226 }
2227 // Leaf name: right_identity_zero
2228 // Rule: right_identity_zero
2229 if (!RuleConfig->isRuleDisabled(24)) {
2230 if (1
2231 && [&]() {
2232 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2233 return true;
2234 }() ) {
2235 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2236 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2237 return true;
2238 }
2239 }
2240 // Leaf name: shifts_too_big
2241 // Rule: shifts_too_big
2242 if (!RuleConfig->isRuleDisabled(41)) {
2243 if (1
2244 && [&]() {
2245 return Helper.matchShiftsTooBig(*MIs[0]);
2246 return true;
2247 }() ) {
2248 LLVM_DEBUG(dbgs() << "Applying rule 'shifts_too_big'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shifts_too_big'\n"
; } } while (false)
;
2249 Helper.replaceInstWithUndef(*MIs[0]);
2250 return true;
2251 }
2252 }
2253 // Leaf name: shift_immed_chain
2254 // Rule: shift_immed_chain
2255 if (!RuleConfig->isRuleDisabled(79)) {
2256 if (1
2257 && [&]() {
2258 return Helper.matchShiftImmedChain(*MIs[0], MatchData79);
2259 return true;
2260 }() ) {
2261 LLVM_DEBUG(dbgs() << "Applying rule 'shift_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_immed_chain'\n"
; } } while (false)
;
2262 Helper.applyShiftImmedChain(*MIs[0], MatchData79);
2263 return true;
2264 }
2265 }
2266 // Leaf name: shift_of_shifted_logic_chain
2267 // Rule: shift_of_shifted_logic_chain
2268 if (!RuleConfig->isRuleDisabled(80)) {
2269 if (1
2270 && [&]() {
2271 return Helper.matchShiftOfShiftedLogic(*MIs[0], MatchData80);
2272 return true;
2273 }() ) {
2274 LLVM_DEBUG(dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n"
; } } while (false)
;
2275 Helper.applyShiftOfShiftedLogic(*MIs[0], MatchData80);
2276 return true;
2277 }
2278 }
2279 // Leaf name: bitfield_extract_from_shr
2280 // Rule: bitfield_extract_from_shr
2281 if (!RuleConfig->isRuleDisabled(88)) {
2282 if (1
2283 && [&]() {
2284 return Helper.matchBitfieldExtractFromShr(*MIs[0], MatchData88);
2285 return true;
2286 }() ) {
2287 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_shr'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_shr'\n"
; } } while (false)
;
2288 Helper.applyBuildFn(*MIs[0], MatchData88);
2289 return true;
2290 }
2291 }
2292 // Leaf name: bitfield_extract_from_shr_and
2293 // Rule: bitfield_extract_from_shr_and
2294 if (!RuleConfig->isRuleDisabled(89)) {
2295 if (1
2296 && [&]() {
2297 return Helper.matchBitfieldExtractFromShrAnd(*MIs[0], MatchData89);
2298 return true;
2299 }() ) {
2300 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_shr_and'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_shr_and'\n"
; } } while (false)
;
2301 Helper.applyBuildFn(*MIs[0], MatchData89);
2302 return true;
2303 }
2304 }
2305 // Leaf name: fold_binop_into_select
2306 // Rule: fold_binop_into_select
2307 if (!RuleConfig->isRuleDisabled(105)) {
2308 if (1
2309 && [&]() {
2310 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2311 return true;
2312 }() ) {
2313 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2314 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2315 return true;
2316 }
2317 }
2318 return false;
2319 }
2320 if (Partition == 22 /* TargetOpcode::G_ABS */) {
2321 // Leaf name: unary_undef_to_zero
2322 // Rule: unary_undef_to_zero
2323 if (!RuleConfig->isRuleDisabled(16)) {
2324 if (1
2325 && [&]() {
2326 return Helper.matchOperandIsUndef(*MIs[0], 1);
2327 return true;
2328 }() ) {
2329 LLVM_DEBUG(dbgs() << "Applying rule 'unary_undef_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unary_undef_to_zero'\n"
; } } while (false)
;
2330 Helper.replaceInstWithConstant(*MIs[0], 0);
2331 return true;
2332 }
2333 }
2334 return false;
2335 }
2336 if (Partition == 23 /* TargetOpcode::G_FPTOSI */) {
2337 // Leaf name: propagate_undef_any_op
2338 // Rule: propagate_undef_any_op
2339 if (!RuleConfig->isRuleDisabled(17)) {
2340 if (1
2341 && [&]() {
2342 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
2343 return true;
2344 }() ) {
2345 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
2346 Helper.replaceInstWithUndef(*MIs[0]);
2347 return true;
2348 }
2349 }
2350 return false;
2351 }
2352 if (Partition == 24 /* TargetOpcode::G_FPTOUI */) {
2353 // Leaf name: propagate_undef_any_op
2354 // Rule: propagate_undef_any_op
2355 if (!RuleConfig->isRuleDisabled(17)) {
2356 if (1
2357 && [&]() {
2358 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
2359 return true;
2360 }() ) {
2361 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
2362 Helper.replaceInstWithUndef(*MIs[0]);
2363 return true;
2364 }
2365 }
2366 return false;
2367 }
2368 if (Partition == 25 /* TargetOpcode::G_SUB */) {
2369 // Leaf name: propagate_undef_any_op
2370 // Rule: propagate_undef_any_op
2371 if (!RuleConfig->isRuleDisabled(17)) {
2372 if (1
2373 && [&]() {
2374 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
2375 return true;
2376 }() ) {
2377 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
2378 Helper.replaceInstWithUndef(*MIs[0]);
2379 return true;
2380 }
2381 }
2382 // Leaf name: right_identity_zero
2383 // Rule: right_identity_zero
2384 if (!RuleConfig->isRuleDisabled(24)) {
2385 if (1
2386 && [&]() {
2387 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2388 return true;
2389 }() ) {
2390 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2391 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2392 return true;
2393 }
2394 }
2395 // Leaf name: constant_fold
2396 // Rule: constant_fold
2397 if (!RuleConfig->isRuleDisabled(90)) {
2398 if (1
2399 && [&]() {
2400 return Helper.matchConstantFold(*MIs[0], MatchData90);
2401 return true;
2402 }() ) {
2403 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
2404 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
2405 return true;
2406 }
2407 }
2408 // Leaf name: fold_binop_into_select
2409 // Rule: fold_binop_into_select
2410 if (!RuleConfig->isRuleDisabled(105)) {
2411 if (1
2412 && [&]() {
2413 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2414 return true;
2415 }() ) {
2416 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2417 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2418 return true;
2419 }
2420 }
2421 // Leaf name: sub_add_reg
2422 // Rule: sub_add_reg
2423 if (!RuleConfig->isRuleDisabled(106)) {
2424 if (1
2425 && [&]() {
2426 return Helper.matchSubAddSameReg(*MIs[0], MatchData106);
2427 return true;
2428 }() ) {
2429 LLVM_DEBUG(dbgs() << "Applying rule 'sub_add_reg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'sub_add_reg'\n"
; } } while (false)
;
2430 Helper.applyBuildFn(*MIs[0], MatchData106);
2431 return true;
2432 }
2433 }
2434 return false;
2435 }
2436 if (Partition == 26 /* TargetOpcode::G_XOR */) {
2437 // Leaf name: propagate_undef_any_op
2438 // Rule: propagate_undef_any_op
2439 if (!RuleConfig->isRuleDisabled(17)) {
2440 if (1
2441 && [&]() {
2442 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
2443 return true;
2444 }() ) {
2445 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
2446 Helper.replaceInstWithUndef(*MIs[0]);
2447 return true;
2448 }
2449 }
2450 // Leaf name: right_identity_zero
2451 // Rule: right_identity_zero
2452 if (!RuleConfig->isRuleDisabled(24)) {
2453 if (1
2454 && [&]() {
2455 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2456 return true;
2457 }() ) {
2458 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2459 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2460 return true;
2461 }
2462 }
2463 // Leaf name: hoist_logic_op_with_same_opcode_hands
2464 // Rule: hoist_logic_op_with_same_opcode_hands
2465 if (!RuleConfig->isRuleDisabled(40)) {
2466 if (1
2467 && [&]() {
2468 return Helper.matchHoistLogicOpWithSameOpcodeHands(*MIs[0], MatchData40);
2469 return true;
2470 }() ) {
2471 LLVM_DEBUG(dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'hoist_logic_op_with_same_opcode_hands'\n"
; } } while (false)
;
2472 Helper.applyBuildInstructionSteps(*MIs[0], MatchData40);
2473 return true;
2474 }
2475 }
2476 // Leaf name: not_cmp_fold
2477 // Rule: not_cmp_fold
2478 if (!RuleConfig->isRuleDisabled(60)) {
2479 if (1
2480 && [&]() {
2481 return Helper.matchNotCmp(*MIs[0], MatchData60);
2482 return true;
2483 }() ) {
2484 LLVM_DEBUG(dbgs() << "Applying rule 'not_cmp_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'not_cmp_fold'\n"
; } } while (false)
;
2485 Helper.applyNotCmp(*MIs[0], MatchData60);
2486 return true;
2487 }
2488 }
2489 // Leaf name: xor_of_and_with_same_reg
2490 // Rule: xor_of_and_with_same_reg
2491 if (!RuleConfig->isRuleDisabled(77)) {
2492 if (1
2493 && [&]() {
2494 return Helper.matchXorOfAndWithSameReg(*MIs[0], MatchData77);
2495 return true;
2496 }() ) {
2497 LLVM_DEBUG(dbgs() << "Applying rule 'xor_of_and_with_same_reg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'xor_of_and_with_same_reg'\n"
; } } while (false)
;
2498 Helper.applyXorOfAndWithSameReg(*MIs[0], MatchData77);
2499 return true;
2500 }
2501 }
2502 // Leaf name: constant_fold
2503 // Rule: constant_fold
2504 if (!RuleConfig->isRuleDisabled(90)) {
2505 if (1
2506 && [&]() {
2507 return Helper.matchConstantFold(*MIs[0], MatchData90);
2508 return true;
2509 }() ) {
2510 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fold'\n"
; } } while (false)
;
2511 Helper.replaceInstWithConstant(*MIs[0], MatchData90);
2512 return true;
2513 }
2514 }
2515 // Leaf name: fold_binop_into_select
2516 // Rule: fold_binop_into_select
2517 if (!RuleConfig->isRuleDisabled(105)) {
2518 if (1
2519 && [&]() {
2520 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2521 return true;
2522 }() ) {
2523 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2524 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2525 return true;
2526 }
2527 }
2528 // Leaf name: commute_constant_to_rhs
2529 // Rule: commute_constant_to_rhs
2530 if (!RuleConfig->isRuleDisabled(110)) {
2531 if (1
2532 && [&]() {
2533
2534 return getIConstantVRegVal(MIs[0]->getOperand(1).getReg(), MRI).has_value();
2535
2536 return true;
2537 }() ) {
2538 LLVM_DEBUG(dbgs() << "Applying rule 'commute_constant_to_rhs'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'commute_constant_to_rhs'\n"
; } } while (false)
;
2539
2540 Observer.changingInstr(*MIs[0]);
2541 Register LHSReg = MIs[0]->getOperand(1).getReg();
2542 Register RHSReg = MIs[0]->getOperand(2).getReg();
2543 MIs[0]->getOperand(1).setReg(RHSReg);
2544 MIs[0]->getOperand(2).setReg(LHSReg);
2545 Observer.changedInstr(*MIs[0]);
2546
2547 return true;
2548 }
2549 }
2550 return false;
2551 }
2552 if (Partition == 27 /* TargetOpcode::G_TRUNC */) {
2553 // Leaf name: propagate_undef_any_op
2554 // Rule: propagate_undef_any_op
2555 if (!RuleConfig->isRuleDisabled(17)) {
2556 if (1
2557 && [&]() {
2558 return Helper.matchAnyExplicitUseIsUndef(*MIs[0]);
2559 return true;
2560 }() ) {
2561 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_any_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_any_op'\n"
; } } while (false)
;
2562 Helper.replaceInstWithUndef(*MIs[0]);
2563 return true;
2564 }
2565 }
2566 // Leaf name: trunc_buildvector_fold
2567 // Rule: trunc_buildvector_fold
2568 if (!RuleConfig->isRuleDisabled(35)) {
2569 if (1
2570 && [&]() {
2571 return Helper.matchTruncBuildVectorFold(*MIs[0], MatchData35);
2572 return true;
2573 }() ) {
2574 LLVM_DEBUG(dbgs() << "Applying rule 'trunc_buildvector_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'trunc_buildvector_fold'\n"
; } } while (false)
;
2575 Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData35);
2576 return true;
2577 }
2578 }
2579 // Leaf name: trunc_lshr_buildvector_fold
2580 // Rule: trunc_lshr_buildvector_fold
2581 if (!RuleConfig->isRuleDisabled(36)) {
2582 if (1
2583 && [&]() {
2584 return Helper.matchTruncLshrBuildVectorFold(*MIs[0], MatchData36);
2585 return true;
2586 }() ) {
2587 LLVM_DEBUG(dbgs() << "Applying rule 'trunc_lshr_buildvector_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'trunc_lshr_buildvector_fold'\n"
; } } while (false)
;
2588 Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData36);
2589 return true;
2590 }
2591 }
2592 // Leaf name: trunc_ext_fold
2593 // Rule: trunc_ext_fold
2594 if (!RuleConfig->isRuleDisabled(67)) {
2595 if (1
2596 && [&]() {
2597 return Helper.matchCombineTruncOfExt(*MIs[0], MatchData67);
2598 return true;
2599 }() ) {
2600 LLVM_DEBUG(dbgs() << "Applying rule 'trunc_ext_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'trunc_ext_fold'\n"
; } } while (false)
;
2601 Helper.applyCombineTruncOfExt(*MIs[0], MatchData67);
2602 return true;
2603 }
2604 }
2605 // Leaf name: trunc_shift
2606 // Rule: trunc_shift
2607 if (!RuleConfig->isRuleDisabled(68)) {
2608 if (1
2609 && [&]() {
2610 return Helper.matchCombineTruncOfShift(*MIs[0], MatchData68);
2611 return true;
2612 }() ) {
2613 LLVM_DEBUG(dbgs() << "Applying rule 'trunc_shift'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'trunc_shift'\n"
; } } while (false)
;
2614 Helper.applyCombineTruncOfShift(*MIs[0], MatchData68);
2615 return true;
2616 }
2617 }
2618 // Leaf name: clamp_i64_to_i16
2619 // Rule: clamp_i64_to_i16
2620 if (!RuleConfig->isRuleDisabled(111)) {
2621 if (1
2622 && [&]() {
2623 return PreLegalizerHelper.matchClampI64ToI16(*MIs[0], MRI, *MF, MatchData111);
2624 return true;
2625 }() ) {
2626 LLVM_DEBUG(dbgs() << "Applying rule 'clamp_i64_to_i16'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'clamp_i64_to_i16'\n"
; } } while (false)
;
2627 PreLegalizerHelper.applyClampI64ToI16(*MIs[0], MatchData111);
2628 return true;
2629 }
2630 }
2631 return false;
2632 }
2633 if (Partition == 28 /* TargetOpcode::G_SHUFFLE_VECTOR */) {
2634 // Leaf name: propagate_undef_all_ops
2635 // Rule: propagate_undef_all_ops
2636 if (!RuleConfig->isRuleDisabled(18)) {
2637 if (1
2638 && [&]() {
2639 return Helper.matchAllExplicitUsesAreUndef(*MIs[0]);
2640 return true;
2641 }() ) {
2642 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_all_ops'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_all_ops'\n"
; } } while (false)
;
2643 Helper.replaceInstWithUndef(*MIs[0]);
2644 return true;
2645 }
2646 }
2647 // Leaf name: propagate_undef_shuffle_mask
2648 // Rule: propagate_undef_shuffle_mask
2649 if (!RuleConfig->isRuleDisabled(19)) {
2650 if (1
2651 && [&]() {
2652 return Helper.matchUndefShuffleVectorMask(*MIs[0]);
2653 return true;
2654 }() ) {
2655 LLVM_DEBUG(dbgs() << "Applying rule 'propagate_undef_shuffle_mask'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'propagate_undef_shuffle_mask'\n"
; } } while (false)
;
2656 Helper.replaceInstWithUndef(*MIs[0]);
2657 return true;
2658 }
2659 }
2660 return false;
2661 }
2662 if (Partition == 29 /* TargetOpcode::G_UNMERGE_VALUES */) {
2663 // Leaf name: unmerge_undef
2664 // Rule: unmerge_undef
2665 if (!RuleConfig->isRuleDisabled(21)) {
2666 if (1
2667 && [&]() {
2668 return Helper.matchCombineUnmergeUndef(*MIs[0], MatchData21);
2669 return true;
2670 }() ) {
2671 LLVM_DEBUG(dbgs() << "Applying rule 'unmerge_undef'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unmerge_undef'\n"
; } } while (false)
;
2672 Helper.applyBuildFn(*MIs[0], MatchData21);
2673 return true;
2674 }
2675 }
2676 // Leaf name: unmerge_merge
2677 // Rule: unmerge_merge
2678 if (!RuleConfig->isRuleDisabled(62)) {
2679 if (1
2680 && [&]() {
2681 return Helper.matchCombineUnmergeMergeToPlainValues(*MIs[0], MatchData62);
2682 return true;
2683 }() ) {
2684 LLVM_DEBUG(dbgs() << "Applying rule 'unmerge_merge'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unmerge_merge'\n"
; } } while (false)
;
2685 Helper.applyCombineUnmergeMergeToPlainValues(*MIs[0], MatchData62);
2686 return true;
2687 }
2688 }
2689 // Leaf name: unmerge_cst
2690 // Rule: unmerge_cst
2691 if (!RuleConfig->isRuleDisabled(63)) {
2692 if (1
2693 && [&]() {
2694 return Helper.matchCombineUnmergeConstant(*MIs[0], MatchData63);
2695 return true;
2696 }() ) {
2697 LLVM_DEBUG(dbgs() << "Applying rule 'unmerge_cst'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unmerge_cst'\n"
; } } while (false)
;
2698 Helper.applyCombineUnmergeConstant(*MIs[0], MatchData63);
2699 return true;
2700 }
2701 }
2702 // Leaf name: unmerge_dead_to_trunc
2703 // Rule: unmerge_dead_to_trunc
2704 if (!RuleConfig->isRuleDisabled(64)) {
2705 if (1
2706 && [&]() {
2707 return Helper.matchCombineUnmergeWithDeadLanesToTrunc(*MIs[0]);
2708 return true;
2709 }() ) {
2710 LLVM_DEBUG(dbgs() << "Applying rule 'unmerge_dead_to_trunc'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unmerge_dead_to_trunc'\n"
; } } while (false)
;
2711 Helper.applyCombineUnmergeWithDeadLanesToTrunc(*MIs[0]);
2712 return true;
2713 }
2714 }
2715 // Leaf name: unmerge_zext_to_zext
2716 // Rule: unmerge_zext_to_zext
2717 if (!RuleConfig->isRuleDisabled(65)) {
2718 if (1
2719 && [&]() {
2720 return Helper.matchCombineUnmergeZExtToZExt(*MIs[0]);
2721 return true;
2722 }() ) {
2723 LLVM_DEBUG(dbgs() << "Applying rule 'unmerge_zext_to_zext'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'unmerge_zext_to_zext'\n"
; } } while (false)
;
2724 Helper.applyCombineUnmergeZExtToZExt(*MIs[0]);
2725 return true;
2726 }
2727 }
2728 return false;
2729 }
2730 if (Partition == 30 /* TargetOpcode::G_SELECT */) {
2731 // Leaf name: select_same_val
2732 // Rule: select_same_val
2733 if (!RuleConfig->isRuleDisabled(23)) {
2734 if (1
2735 && [&]() {
2736 return Helper.matchSelectSameVal(*MIs[0]);
2737 return true;
2738 }() ) {
2739 LLVM_DEBUG(dbgs() << "Applying rule 'select_same_val'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'select_same_val'\n"
; } } while (false)
;
2740 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 2);
2741 return true;
2742 }
2743 }
2744 // Leaf name: select_undef_cmp
2745 // Rule: select_undef_cmp
2746 if (!RuleConfig->isRuleDisabled(48)) {
2747 if (1
2748 && [&]() {
2749 return Helper.matchUndefSelectCmp(*MIs[0]);
2750 return true;
2751 }() ) {
2752 LLVM_DEBUG(dbgs() << "Applying rule 'select_undef_cmp'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'select_undef_cmp'\n"
; } } while (false)
;
2753 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 2);
2754 return true;
2755 }
2756 }
2757 // Leaf name: select_constant_cmp
2758 // Rule: select_constant_cmp
2759 if (!RuleConfig->isRuleDisabled(49)) {
2760 if (1
2761 && [&]() {
2762 return Helper.matchConstantSelectCmp(*MIs[0], MatchData49);
2763 return true;
2764 }() ) {
2765 LLVM_DEBUG(dbgs() << "Applying rule 'select_constant_cmp'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'select_constant_cmp'\n"
; } } while (false)
;
2766 return Helper.replaceSingleDefInstWithOperand(*MIs[0], MatchData49);
2767 return true;
2768 }
2769 }
2770 // Leaf name: select_to_logical
2771 // Rule: select_to_logical
2772 if (!RuleConfig->isRuleDisabled(50)) {
2773 if (1
2774 && [&]() {
2775 return Helper.matchSelectToLogical(*MIs[0], MatchData50);
2776 return true;
2777 }() ) {
2778 LLVM_DEBUG(dbgs() << "Applying rule 'select_to_logical'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'select_to_logical'\n"
; } } while (false)
;
2779 Helper.applyBuildFn(*MIs[0], MatchData50);
2780 return true;
2781 }
2782 }
2783 // Leaf name: select_to_minmax
2784 // Rule: select_to_minmax
2785 if (!RuleConfig->isRuleDisabled(107)) {
2786 if (1
2787 && [&]() {
2788 return Helper.matchSimplifySelectToMinMax(*MIs[0], MatchData107);
2789 return true;
2790 }() ) {
2791 LLVM_DEBUG(dbgs() << "Applying rule 'select_to_minmax'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'select_to_minmax'\n"
; } } while (false)
;
2792 Helper.applyBuildFn(*MIs[0], MatchData107);
2793 return true;
2794 }
2795 }
2796 return false;
2797 }
2798 if (Partition == 31 /* TargetOpcode::G_PTR_ADD */) {
2799 // Leaf name: right_identity_zero
2800 // Rule: right_identity_zero
2801 if (!RuleConfig->isRuleDisabled(24)) {
2802 if (1
2803 && [&]() {
2804 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2805 return true;
2806 }() ) {
2807 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2808 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2809 return true;
2810 }
2811 }
2812 // Leaf name: reassoc_ptradd
2813 // Rule: reassoc_ptradd
2814 if (!RuleConfig->isRuleDisabled(42)) {
2815 if (1
2816 && [&]() {
2817 return Helper.matchReassocPtrAdd(*MIs[0], MatchData42);
2818 return true;
2819 }() ) {
2820 LLVM_DEBUG(dbgs() << "Applying rule 'reassoc_ptradd'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'reassoc_ptradd'\n"
; } } while (false)
;
2821 Helper.applyBuildFnNoErase(*MIs[0], MatchData42);
2822 return true;
2823 }
2824 }
2825 // Leaf name: ptr_add_immed_chain
2826 // Rule: ptr_add_immed_chain
2827 if (!RuleConfig->isRuleDisabled(43)) {
2828 if (1
2829 && [&]() {
2830 return Helper.matchPtrAddImmedChain(*MIs[0], MatchData43);
2831 return true;
2832 }() ) {
2833 LLVM_DEBUG(dbgs() << "Applying rule 'ptr_add_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'ptr_add_immed_chain'\n"
; } } while (false)
;
2834 Helper.applyPtrAddImmedChain(*MIs[0], MatchData43);
2835 return true;
2836 }
2837 }
2838 // Leaf name: const_ptradd_to_i2p
2839 // Rule: const_ptradd_to_i2p
2840 if (!RuleConfig->isRuleDisabled(70)) {
2841 if (1
2842 && [&]() {
2843 return Helper.matchCombineConstPtrAddToI2P(*MIs[0], MatchData70);
2844 return true;
2845 }() ) {
2846 LLVM_DEBUG(dbgs() << "Applying rule 'const_ptradd_to_i2p'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'const_ptradd_to_i2p'\n"
; } } while (false)
;
2847 Helper.applyCombineConstPtrAddToI2P(*MIs[0], MatchData70);
2848 return true;
2849 }
2850 }
2851 // Leaf name: ptr_add_with_zero
2852 // Rule: ptr_add_with_zero
2853 if (!RuleConfig->isRuleDisabled(78)) {
2854 if (1
2855 && [&]() {
2856 return Helper.matchPtrAddZero(*MIs[0]);
2857 return true;
2858 }() ) {
2859 LLVM_DEBUG(dbgs() << "Applying rule 'ptr_add_with_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'ptr_add_with_zero'\n"
; } } while (false)
;
2860 Helper.applyPtrAddZero(*MIs[0]);
2861 return true;
2862 }
2863 }
2864 // Leaf name: fold_binop_into_select
2865 // Rule: fold_binop_into_select
2866 if (!RuleConfig->isRuleDisabled(105)) {
2867 if (1
2868 && [&]() {
2869 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2870 return true;
2871 }() ) {
2872 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2873 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2874 return true;
2875 }
2876 }
2877 return false;
2878 }
2879 if (Partition == 32 /* TargetOpcode::G_ROTL */) {
2880 // Leaf name: right_identity_zero
2881 // Rule: right_identity_zero
2882 if (!RuleConfig->isRuleDisabled(24)) {
2883 if (1
2884 && [&]() {
2885 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2886 return true;
2887 }() ) {
2888 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2889 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2890 return true;
2891 }
2892 }
2893 return false;
2894 }
2895 if (Partition == 33 /* TargetOpcode::G_ROTR */) {
2896 // Leaf name: right_identity_zero
2897 // Rule: right_identity_zero
2898 if (!RuleConfig->isRuleDisabled(24)) {
2899 if (1
2900 && [&]() {
2901 return Helper.matchConstantOp(MIs[0]->getOperand(2), 0);
2902 return true;
2903 }() ) {
2904 LLVM_DEBUG(dbgs() << "Applying rule 'right_identity_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'right_identity_zero'\n"
; } } while (false)
;
2905 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2906 return true;
2907 }
2908 }
2909 return false;
2910 }
2911 if (Partition == 34 /* TargetOpcode::G_SDIV */) {
2912 // Leaf name: binop_left_to_zero
2913 // Rule: binop_left_to_zero
2914 if (!RuleConfig->isRuleDisabled(26)) {
2915 if (1
2916 && [&]() {
2917 return Helper.matchOperandIsZero(*MIs[0], 1);
2918 return true;
2919 }() ) {
2920 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_to_zero'\n"
; } } while (false)
;
2921 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2922 return true;
2923 }
2924 }
2925 // Leaf name: div_rem_to_divrem
2926 // Rule: div_rem_to_divrem
2927 if (!RuleConfig->isRuleDisabled(83)) {
2928 if (1
2929 && [&]() {
2930 return Helper.matchCombineDivRem(*MIs[0], MatchData83);
2931 return true;
2932 }() ) {
2933 LLVM_DEBUG(dbgs() << "Applying rule 'div_rem_to_divrem'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'div_rem_to_divrem'\n"
; } } while (false)
;
2934 Helper.applyCombineDivRem(*MIs[0], MatchData83);
2935 return true;
2936 }
2937 }
2938 // Leaf name: sdiv_by_const
2939 // Rule: sdiv_by_const
2940 if (!RuleConfig->isRuleDisabled(93)) {
2941 if (1
2942 && [&]() {
2943 return Helper.matchSDivByConst(*MIs[0]);
2944 return true;
2945 }() ) {
2946 LLVM_DEBUG(dbgs() << "Applying rule 'sdiv_by_const'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'sdiv_by_const'\n"
; } } while (false)
;
2947 Helper.applySDivByConst(*MIs[0]);
2948 return true;
2949 }
2950 }
2951 // Leaf name: fold_binop_into_select
2952 // Rule: fold_binop_into_select
2953 if (!RuleConfig->isRuleDisabled(105)) {
2954 if (1
2955 && [&]() {
2956 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2957 return true;
2958 }() ) {
2959 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
2960 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
2961 return true;
2962 }
2963 }
2964 return false;
2965 }
2966 if (Partition == 35 /* TargetOpcode::G_SREM */) {
2967 // Leaf name: binop_left_to_zero
2968 // Rule: binop_left_to_zero
2969 if (!RuleConfig->isRuleDisabled(26)) {
2970 if (1
2971 && [&]() {
2972 return Helper.matchOperandIsZero(*MIs[0], 1);
2973 return true;
2974 }() ) {
2975 LLVM_DEBUG(dbgs() << "Applying rule 'binop_left_to_zero'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'binop_left_to_zero'\n"
; } } while (false)
;
2976 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
2977 return true;
2978 }
2979 }
2980 // Leaf name: div_rem_to_divrem
2981 // Rule: div_rem_to_divrem
2982 if (!RuleConfig->isRuleDisabled(83)) {
2983 if (1
2984 && [&]() {
2985 return Helper.matchCombineDivRem(*MIs[0], MatchData83);
2986 return true;
2987 }() ) {
2988 LLVM_DEBUG(dbgs() << "Applying rule 'div_rem_to_divrem'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'div_rem_to_divrem'\n"
; } } while (false)
;
2989 Helper.applyCombineDivRem(*MIs[0], MatchData83);
2990 return true;
2991 }
2992 }
2993 // Leaf name: fold_binop_into_select
2994 // Rule: fold_binop_into_select
2995 if (!RuleConfig->isRuleDisabled(105)) {
2996 if (1
2997 && [&]() {
2998 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
2999 return true;
3000 }() ) {
3001 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3002 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3003 return true;
3004 }
3005 }
3006 return false;
3007 }
3008 if (Partition == 36 /* TargetOpcode::G_INTTOPTR */) {
3009 // Leaf name: p2i_to_i2p
3010 // Rule: p2i_to_i2p
3011 if (!RuleConfig->isRuleDisabled(28)) {
3012 if (1
3013 && [&]() {
3014 return Helper.matchCombineI2PToP2I(*MIs[0], MatchData28);
3015 return true;
3016 }() ) {
3017 LLVM_DEBUG(dbgs() << "Applying rule 'p2i_to_i2p'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'p2i_to_i2p'\n"
; } } while (false)
;
3018 Helper.applyCombineI2PToP2I(*MIs[0], MatchData28);
3019 return true;
3020 }
3021 }
3022 return false;
3023 }
3024 if (Partition == 37 /* TargetOpcode::G_PTRTOINT */) {
3025 Partition = -1;
3026 if (MIs.size() <= 1) MIs.resize(2);
3027 MIs[1] = nullptr;
3028 if (MIs[0]->getOperand(1).isReg())
3029 MIs[1] = MRI.getVRegDef(MIs[0]->getOperand(1).getReg());
3030 if (MIs[1] != nullptr) Partition = 0;
3031 if (Partition == -1) return false;
3032 if (Partition == 0 /* true */) {
3033 Partition = -1;
3034 switch (MIs[1]->getOpcode()) {
3035 case TargetOpcode::G_INTTOPTR: Partition = 0; break;
3036 }
3037 // Default case but without conflicting with potential default case in selection.
3038 if (Partition == -1) return false;
3039 if (Partition == 0 /* TargetOpcode::G_INTTOPTR */) {
3040 // Leaf name: i2p_to_p2i
3041 // Rule: i2p_to_p2i
3042 if (!RuleConfig->isRuleDisabled(29)) {
3043 if (1
3044 && [&]() {
3045 MatchData29 = MIs[1]->getOperand(1).getReg();
3046 return true;
3047 }() ) {
3048 LLVM_DEBUG(dbgs() << "Applying rule 'i2p_to_p2i'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'i2p_to_p2i'\n"
; } } while (false)
;
3049 Helper.applyCombineP2IToI2P(*MIs[0], MatchData29);
3050 return true;
3051 }
3052 }
3053 return false;
3054 }
3055 }
3056 }
3057 if (Partition == 38 /* TargetOpcode::G_ANYEXT */) {
3058 // Leaf name: anyext_trunc_fold
3059 // Rule: anyext_trunc_fold
3060 if (!RuleConfig->isRuleDisabled(30)) {
3061 if (1
3062 && [&]() {
3063 return Helper.matchCombineAnyExtTrunc(*MIs[0], MatchData30);
3064 return true;
3065 }() ) {
3066 LLVM_DEBUG(dbgs() << "Applying rule 'anyext_trunc_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'anyext_trunc_fold'\n"
; } } while (false)
;
3067 return Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData30);
3068 return true;
3069 }
3070 }
3071 // Leaf name: ext_ext_fold
3072 // Rule: ext_ext_fold
3073 if (!RuleConfig->isRuleDisabled(59)) {
3074 if (1
3075 && [&]() {
3076 return Helper.matchCombineExtOfExt(*MIs[0], MatchData59);
3077 return true;
3078 }() ) {
3079 LLVM_DEBUG(dbgs() << "Applying rule 'ext_ext_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'ext_ext_fold'\n"
; } } while (false)
;
3080 Helper.applyCombineExtOfExt(*MIs[0], MatchData59);
3081 return true;
3082 }
3083 }
3084 return false;
3085 }
3086 if (Partition == 39 /* TargetOpcode::G_FNEG */) {
3087 Partition = -1;
3088 if (MIs.size() <= 1) MIs.resize(2);
3089 MIs[1] = nullptr;
3090 if (MIs[0]->getOperand(1).isReg())
3091 MIs[1] = MRI.getVRegDef(MIs[0]->getOperand(1).getReg());
3092 if (MIs[1] == nullptr) Partition = 1;
3093 if (MIs[1] != nullptr) Partition = 0;
3094 if (Partition == -1) return false;
3095 if (Partition == 0 /* true */) {
3096 Partition = -1;
Value stored to 'Partition' is never read
3097 switch (MIs[1]->getOpcode()) {
3098 case TargetOpcode::G_FNEG: Partition = 0; break;
3099 default: Partition = 1; break;
3100 }
3101 // Default case but without conflicting with potential default case in selection.
3102 if (Partition == -1) return false;
3103 if (Partition == 0 /* TargetOpcode::G_FNEG */) {
3104 // Leaf name: fneg_fneg_fold
3105 // Rule: fneg_fneg_fold
3106 if (!RuleConfig->isRuleDisabled(31)) {
3107 if (1
3108 && [&]() {
3109 MatchData31 = MIs[1]->getOperand(1).getReg();
3110 return true;
3111 }() ) {
3112 LLVM_DEBUG(dbgs() << "Applying rule 'fneg_fneg_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fneg_fneg_fold'\n"
; } } while (false)
;
3113 return Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData31);
3114 return true;
3115 }
3116 }
3117 // Leaf name: constant_fp_op
3118 // Rule: constant_fp_op
3119 if (!RuleConfig->isRuleDisabled(69)) {
3120 if (1
3121 && [&]() {
3122 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3123 return true;
3124 }() ) {
3125 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3126 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3127 return true;
3128 }
3129 }
3130 // Leaf name: foldable_fneg
3131 // Rule: foldable_fneg
3132 if (!RuleConfig->isRuleDisabled(112)) {
3133 if (1
3134 && [&]() {
3135 return Helper.matchFoldableFneg(*MIs[0], MatchData112);
3136 return true;
3137 }() ) {
3138 LLVM_DEBUG(dbgs() << "Applying rule 'foldable_fneg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'foldable_fneg'\n"
; } } while (false)
;
3139 Helper.applyFoldableFneg(*MIs[0], MatchData112);
3140 return true;
3141 }
3142 }
3143 return false;
3144 }
3145 if (Partition == 1 /* * or nullptr */) {
3146 // Leaf name: constant_fp_op
3147 // Rule: constant_fp_op
3148 if (!RuleConfig->isRuleDisabled(69)) {
3149 if (1
3150 && [&]() {
3151 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3152 return true;
3153 }() ) {
3154 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3155 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3156 return true;
3157 }
3158 }
3159 // Leaf name: foldable_fneg
3160 // Rule: foldable_fneg
3161 if (!RuleConfig->isRuleDisabled(112)) {
3162 if (1
3163 && [&]() {
3164 return Helper.matchFoldableFneg(*MIs[0], MatchData112);
3165 return true;
3166 }() ) {
3167 LLVM_DEBUG(dbgs() << "Applying rule 'foldable_fneg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'foldable_fneg'\n"
; } } while (false)
;
3168 Helper.applyFoldableFneg(*MIs[0], MatchData112);
3169 return true;
3170 }
3171 }
3172 return false;
3173 }
3174 }
3175 if (Partition == 1 /* false */) {
3176 // Leaf name: constant_fp_op
3177 // Rule: constant_fp_op
3178 if (!RuleConfig->isRuleDisabled(69)) {
3179 if (1
3180 && [&]() {
3181 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3182 return true;
3183 }() ) {
3184 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3185 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3186 return true;
3187 }
3188 }
3189 // Leaf name: foldable_fneg
3190 // Rule: foldable_fneg
3191 if (!RuleConfig->isRuleDisabled(112)) {
3192 if (1
3193 && [&]() {
3194 return Helper.matchFoldableFneg(*MIs[0], MatchData112);
3195 return true;
3196 }() ) {
3197 LLVM_DEBUG(dbgs() << "Applying rule 'foldable_fneg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'foldable_fneg'\n"
; } } while (false)
;
3198 Helper.applyFoldableFneg(*MIs[0], MatchData112);
3199 return true;
3200 }
3201 }
3202 return false;
3203 }
3204 }
3205 if (Partition == 40 /* TargetOpcode::G_BUILD_VECTOR_TRUNC */) {
3206 // Leaf name: buildvector_identity_fold
3207 // Rule: buildvector_identity_fold
3208 if (!RuleConfig->isRuleDisabled(34)) {
3209 if (1
3210 && [&]() {
3211 return Helper.matchBuildVectorIdentityFold(*MIs[0], MatchData34);
3212 return true;
3213 }() ) {
3214 LLVM_DEBUG(dbgs() << "Applying rule 'buildvector_identity_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'buildvector_identity_fold'\n"
; } } while (false)
;
3215 Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData34);
3216 return true;
3217 }
3218 }
3219 return false;
3220 }
3221 if (Partition == 41 /* TargetOpcode::G_BITCAST */) {
3222 Partition = -1;
3223 if (MIs.size() <= 1) MIs.resize(2);
3224 MIs[1] = nullptr;
3225 if (MIs[0]->getOperand(1).isReg())
3226 MIs[1] = MRI.getVRegDef(MIs[0]->getOperand(1).getReg());
3227 if (MIs[1] != nullptr) Partition = 0;
3228 if (Partition == -1) return false;
3229 if (Partition == 0 /* true */) {
3230 Partition = -1;
3231 switch (MIs[1]->getOpcode()) {
3232 case TargetOpcode::G_BITCAST: Partition = 0; break;
3233 }
3234 // Default case but without conflicting with potential default case in selection.
3235 if (Partition == -1) return false;
3236 if (Partition == 0 /* TargetOpcode::G_BITCAST */) {
3237 // Leaf name: bitcast_bitcast_fold
3238 // Rule: bitcast_bitcast_fold
3239 if (!RuleConfig->isRuleDisabled(37)) {
3240 if (1
3241 && [&]() {
3242 return MRI.getType(MIs[1]->getOperand(1).getReg()) == MRI.getType(MIs[0]->getOperand(0).getReg());
3243 return true;
3244 }() ) {
3245 LLVM_DEBUG(dbgs() << "Applying rule 'bitcast_bitcast_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitcast_bitcast_fold'\n"
; } } while (false)
;
3246 Helper.replaceSingleDefInstWithReg(*MIs[0], MIs[1]->getOperand(1).getReg());
3247 return true;
3248 }
3249 }
3250 return false;
3251 }
3252 }
3253 }
3254 if (Partition == 42 /* TargetOpcode::G_PHI */) {
3255 // Leaf name: extend_through_phis
3256 // Rule: extend_through_phis
3257 if (!RuleConfig->isRuleDisabled(38)) {
3258 if (1
3259 && [&]() {
3260 return Helper.matchExtendThroughPhis(*MIs[0], MatchData38);
3261 return true;
3262 }() ) {
3263 LLVM_DEBUG(dbgs() << "Applying rule 'extend_through_phis'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'extend_through_phis'\n"
; } } while (false)
;
3264 Helper.applyExtendThroughPhis(*MIs[0], MatchData38);
3265 return true;
3266 }
3267 }
3268 return false;
3269 }
3270 if (Partition == 43 /* TargetOpcode::G_SEXT_INREG */) {
3271 // Leaf name: sext_inreg_of_load
3272 // Rule: sext_inreg_of_load
3273 if (!RuleConfig->isRuleDisabled(45)) {
3274 if (1
3275 && [&]() {
3276 return Helper.matchSextInRegOfLoad(*MIs[0], MatchData45);
3277 return true;
3278 }() ) {
3279 LLVM_DEBUG(dbgs() << "Applying rule 'sext_inreg_of_load'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'sext_inreg_of_load'\n"
; } } while (false)
;
3280 Helper.applySextInRegOfLoad(*MIs[0], MatchData45);
3281 return true;
3282 }
3283 }
3284 // Leaf name: redundant_sext_inreg
3285 // Rule: redundant_sext_inreg
3286 if (!RuleConfig->isRuleDisabled(52)) {
3287 if (1
3288 && [&]() {
3289 return Helper.matchRedundantSExtInReg(*MIs[0]);
3290 return true;
3291 }() ) {
3292 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_sext_inreg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_sext_inreg'\n"
; } } while (false)
;
3293 return Helper.replaceSingleDefInstWithOperand(*MIs[0], 1);
3294 return true;
3295 }
3296 }
3297 // Leaf name: sext_inreg_to_zext_inreg
3298 // Rule: sext_inreg_to_zext_inreg
3299 if (!RuleConfig->isRuleDisabled(58)) {
3300 if (1
3301 && [&]() {
3302
3303 unsigned BitWidth = MRI.getType(MIs[0]->getOperand(1).getReg()).getScalarSizeInBits();
3304 return Helper.getKnownBits()->maskedValueIsZero(MIs[0]->getOperand(1).getReg(),
3305 APInt::getOneBitSet(BitWidth, MIs[0]->getOperand(2).getImm() - 1));
3306 return true;
3307 }() ) {
3308 LLVM_DEBUG(dbgs() << "Applying rule 'sext_inreg_to_zext_inreg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'sext_inreg_to_zext_inreg'\n"
; } } while (false)
;
3309
3310 Helper.getBuilder().setInstrAndDebugLoc(*MIs[0]);
3311 Helper.getBuilder().buildZExtInReg(MIs[0]->getOperand(0), MIs[0]->getOperand(1), MIs[0]->getOperand(2).getImm());
3312 MIs[0]->eraseFromParent();
3313 return true;
3314
3315 return true;
3316 }
3317 }
3318 // Leaf name: bitfield_extract_from_sext_inreg
3319 // Rule: bitfield_extract_from_sext_inreg
3320 if (!RuleConfig->isRuleDisabled(86)) {
3321 if (1
3322 && [&]() {
3323 return Helper.matchBitfieldExtractFromSExtInReg(*MIs[0], MatchData86);
3324 return true;
3325 }() ) {
3326 LLVM_DEBUG(dbgs() << "Applying rule 'bitfield_extract_from_sext_inreg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'bitfield_extract_from_sext_inreg'\n"
; } } while (false)
;
3327 Helper.applyBuildFn(*MIs[0], MatchData86);
3328 return true;
3329 }
3330 }
3331 return false;
3332 }
3333 if (Partition == 44 /* TargetOpcode::G_ZEXT */) {
3334 // Leaf name: zext_trunc_fold
3335 // Rule: zext_trunc_fold
3336 if (!RuleConfig->isRuleDisabled(55)) {
3337 if (1
3338 && [&]() {
3339 return Helper.matchCombineZextTrunc(*MIs[0], MatchData55);
3340 return true;
3341 }() ) {
3342 LLVM_DEBUG(dbgs() << "Applying rule 'zext_trunc_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'zext_trunc_fold'\n"
; } } while (false)
;
3343 return Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData55);
3344 return true;
3345 }
3346 }
3347 // Leaf name: ext_ext_fold
3348 // Rule: ext_ext_fold
3349 if (!RuleConfig->isRuleDisabled(59)) {
3350 if (1
3351 && [&]() {
3352 return Helper.matchCombineExtOfExt(*MIs[0], MatchData59);
3353 return true;
3354 }() ) {
3355 LLVM_DEBUG(dbgs() << "Applying rule 'ext_ext_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'ext_ext_fold'\n"
; } } while (false)
;
3356 Helper.applyCombineExtOfExt(*MIs[0], MatchData59);
3357 return true;
3358 }
3359 }
3360 return false;
3361 }
3362 if (Partition == 45 /* TargetOpcode::G_ICMP */) {
3363 // Leaf name: icmp_to_true_false_known_bits
3364 // Rule: icmp_to_true_false_known_bits
3365 if (!RuleConfig->isRuleDisabled(56)) {
3366 if (1
3367 && [&]() {
3368 return Helper.matchICmpToTrueFalseKnownBits(*MIs[0], MatchData56);
3369 return true;
3370 }() ) {
3371 LLVM_DEBUG(dbgs() << "Applying rule 'icmp_to_true_false_known_bits'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'icmp_to_true_false_known_bits'\n"
; } } while (false)
;
3372 Helper.replaceInstWithConstant(*MIs[0], MatchData56);
3373 return true;
3374 }
3375 }
3376 // Leaf name: icmp_to_lhs_known_bits
3377 // Rule: icmp_to_lhs_known_bits
3378 if (!RuleConfig->isRuleDisabled(57)) {
3379 if (1
3380 && [&]() {
3381 return Helper.matchICmpToLHSKnownBits(*MIs[0], MatchData57);
3382 return true;
3383 }() ) {
3384 LLVM_DEBUG(dbgs() << "Applying rule 'icmp_to_lhs_known_bits'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'icmp_to_lhs_known_bits'\n"
; } } while (false)
;
3385 Helper.applyBuildFn(*MIs[0], MatchData57);
3386 return true;
3387 }
3388 }
3389 // Leaf name: redundant_binop_in_equality
3390 // Rule: redundant_binop_in_equality
3391 if (!RuleConfig->isRuleDisabled(108)) {
3392 if (1
3393 && [&]() {
3394 return Helper.matchRedundantBinOpInEquality(*MIs[0], MatchData108);
3395 return true;
3396 }() ) {
3397 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_binop_in_equality'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_binop_in_equality'\n"
; } } while (false)
;
3398 Helper.applyBuildFn(*MIs[0], MatchData108);
3399 return true;
3400 }
3401 }
3402 return false;
3403 }
3404 if (Partition == 46 /* TargetOpcode::G_SEXT */) {
3405 // Leaf name: ext_ext_fold
3406 // Rule: ext_ext_fold
3407 if (!RuleConfig->isRuleDisabled(59)) {
3408 if (1
3409 && [&]() {
3410 return Helper.matchCombineExtOfExt(*MIs[0], MatchData59);
3411 return true;
3412 }() ) {
3413 LLVM_DEBUG(dbgs() << "Applying rule 'ext_ext_fold'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'ext_ext_fold'\n"
; } } while (false)
;
3414 Helper.applyCombineExtOfExt(*MIs[0], MatchData59);
3415 return true;
3416 }
3417 }
3418 return false;
3419 }
3420 if (Partition == 47 /* TargetOpcode::G_BR */) {
3421 // Leaf name: opt_brcond_by_inverting_cond
3422 // Rule: opt_brcond_by_inverting_cond
3423 if (!RuleConfig->isRuleDisabled(61)) {
3424 if (1
3425 && [&]() {
3426 return Helper.matchOptBrCondByInvertingCond(*MIs[0], MatchData61);
3427 return true;
3428 }() ) {
3429 LLVM_DEBUG(dbgs() << "Applying rule 'opt_brcond_by_inverting_cond'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'opt_brcond_by_inverting_cond'\n"
; } } while (false)
;
3430 Helper.applyOptBrCondByInvertingCond(*MIs[0], MatchData61);
3431 return true;
3432 }
3433 }
3434 return false;
3435 }
3436 if (Partition == 48 /* TargetOpcode::G_MERGE_VALUES */) {
3437 // Leaf name: merge_unmerge
3438 // Rule: merge_unmerge
3439 if (!RuleConfig->isRuleDisabled(66)) {
3440 if (1
3441 && [&]() {
3442 return Helper.matchCombineMergeUnmerge(*MIs[0], MatchData66);
3443 return true;
3444 }() ) {
3445 LLVM_DEBUG(dbgs() << "Applying rule 'merge_unmerge'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'merge_unmerge'\n"
; } } while (false)
;
3446 Helper.replaceSingleDefInstWithReg(*MIs[0], MatchData66);
3447 return true;
3448 }
3449 }
3450 return false;
3451 }
3452 if (Partition == 49 /* TargetOpcode::G_FPTRUNC */) {
3453 // Leaf name: constant_fp_op
3454 // Rule: constant_fp_op
3455 if (!RuleConfig->isRuleDisabled(69)) {
3456 if (1
3457 && [&]() {
3458 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3459 return true;
3460 }() ) {
3461 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3462 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3463 return true;
3464 }
3465 }
3466 return false;
3467 }
3468 if (Partition == 50 /* TargetOpcode::G_FSQRT */) {
3469 // Leaf name: constant_fp_op
3470 // Rule: constant_fp_op
3471 if (!RuleConfig->isRuleDisabled(69)) {
3472 if (1
3473 && [&]() {
3474 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3475 return true;
3476 }() ) {
3477 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3478 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3479 return true;
3480 }
3481 }
3482 return false;
3483 }
3484 if (Partition == 51 /* TargetOpcode::G_FLOG2 */) {
3485 // Leaf name: constant_fp_op
3486 // Rule: constant_fp_op
3487 if (!RuleConfig->isRuleDisabled(69)) {
3488 if (1
3489 && [&]() {
3490 return Helper.matchCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3491 return true;
3492 }() ) {
3493 LLVM_DEBUG(dbgs() << "Applying rule 'constant_fp_op'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'constant_fp_op'\n"
; } } while (false)
;
3494 Helper.applyCombineConstantFoldFpUnary(*MIs[0], MatchData69);
3495 return true;
3496 }
3497 }
3498 return false;
3499 }
3500 if (Partition == 52 /* TargetOpcode::G_UMULO */) {
3501 // Leaf name: mulo_by_2
3502 // Rule: mulo_by_2
3503 if (!RuleConfig->isRuleDisabled(72)) {
3504 if (1
3505 && [&]() {
3506 return Helper.matchMulOBy2(*MIs[0], MatchData72);
3507 return true;
3508 }() ) {
3509 LLVM_DEBUG(dbgs() << "Applying rule 'mulo_by_2'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mulo_by_2'\n"
; } } while (false)
;
3510 Helper.applyBuildFnNoErase(*MIs[0], MatchData72);
3511 return true;
3512 }
3513 }
3514 // Leaf name: mulo_by_0
3515 // Rule: mulo_by_0
3516 if (!RuleConfig->isRuleDisabled(73)) {
3517 if (1
3518 && [&]() {
3519 return Helper.matchMulOBy0(*MIs[0], MatchData73);
3520 return true;
3521 }() ) {
3522 LLVM_DEBUG(dbgs() << "Applying rule 'mulo_by_0'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mulo_by_0'\n"
; } } while (false)
;
3523 Helper.applyBuildFn(*MIs[0], MatchData73);
3524 return true;
3525 }
3526 }
3527 return false;
3528 }
3529 if (Partition == 53 /* TargetOpcode::G_SMULO */) {
3530 // Leaf name: mulo_by_2
3531 // Rule: mulo_by_2
3532 if (!RuleConfig->isRuleDisabled(72)) {
3533 if (1
3534 && [&]() {
3535 return Helper.matchMulOBy2(*MIs[0], MatchData72);
3536 return true;
3537 }() ) {
3538 LLVM_DEBUG(dbgs() << "Applying rule 'mulo_by_2'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mulo_by_2'\n"
; } } while (false)
;
3539 Helper.applyBuildFnNoErase(*MIs[0], MatchData72);
3540 return true;
3541 }
3542 }
3543 // Leaf name: mulo_by_0
3544 // Rule: mulo_by_0
3545 if (!RuleConfig->isRuleDisabled(73)) {
3546 if (1
3547 && [&]() {
3548 return Helper.matchMulOBy0(*MIs[0], MatchData73);
3549 return true;
3550 }() ) {
3551 LLVM_DEBUG(dbgs() << "Applying rule 'mulo_by_0'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mulo_by_0'\n"
; } } while (false)
;
3552 Helper.applyBuildFn(*MIs[0], MatchData73);
3553 return true;
3554 }
3555 }
3556 return false;
3557 }
3558 if (Partition == 54 /* TargetOpcode::G_UADDO */) {
3559 // Leaf name: addo_by_0
3560 // Rule: addo_by_0
3561 if (!RuleConfig->isRuleDisabled(74)) {
3562 if (1
3563 && [&]() {
3564 return Helper.matchAddOBy0(*MIs[0], MatchData74);
3565 return true;
3566 }() ) {
3567 LLVM_DEBUG(dbgs() << "Applying rule 'addo_by_0'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'addo_by_0'\n"
; } } while (false)
;
3568 Helper.applyBuildFn(*MIs[0], MatchData74);
3569 return true;
3570 }
3571 }
3572 return false;
3573 }
3574 if (Partition == 55 /* TargetOpcode::G_SADDO */) {
3575 // Leaf name: addo_by_0
3576 // Rule: addo_by_0
3577 if (!RuleConfig->isRuleDisabled(74)) {
3578 if (1
3579 && [&]() {
3580 return Helper.matchAddOBy0(*MIs[0], MatchData74);
3581 return true;
3582 }() ) {
3583 LLVM_DEBUG(dbgs() << "Applying rule 'addo_by_0'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'addo_by_0'\n"
; } } while (false)
;
3584 Helper.applyBuildFn(*MIs[0], MatchData74);
3585 return true;
3586 }
3587 }
3588 return false;
3589 }
3590 if (Partition == 56 /* TargetOpcode::G_UADDE */) {
3591 // Leaf name: adde_to_addo
3592 // Rule: adde_to_addo
3593 if (!RuleConfig->isRuleDisabled(75)) {
3594 if (1
3595 && [&]() {
3596 return Helper.matchAddEToAddO(*MIs[0], MatchData75);
3597 return true;
3598 }() ) {
3599 LLVM_DEBUG(dbgs() << "Applying rule 'adde_to_addo'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'adde_to_addo'\n"
; } } while (false)
;
3600 Helper.applyBuildFnNoErase(*MIs[0], MatchData75);
3601 return true;
3602 }
3603 }
3604 return false;
3605 }
3606 if (Partition == 57 /* TargetOpcode::G_SADDE */) {
3607 // Leaf name: adde_to_addo
3608 // Rule: adde_to_addo
3609 if (!RuleConfig->isRuleDisabled(75)) {
3610 if (1
3611 && [&]() {
3612 return Helper.matchAddEToAddO(*MIs[0], MatchData75);
3613 return true;
3614 }() ) {
3615 LLVM_DEBUG(dbgs() << "Applying rule 'adde_to_addo'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'adde_to_addo'\n"
; } } while (false)
;
3616 Helper.applyBuildFnNoErase(*MIs[0], MatchData75);
3617 return true;
3618 }
3619 }
3620 return false;
3621 }
3622 if (Partition == 58 /* TargetOpcode::G_USUBE */) {
3623 // Leaf name: adde_to_addo
3624 // Rule: adde_to_addo
3625 if (!RuleConfig->isRuleDisabled(75)) {
3626 if (1
3627 && [&]() {
3628 return Helper.matchAddEToAddO(*MIs[0], MatchData75);
3629 return true;
3630 }() ) {
3631 LLVM_DEBUG(dbgs() << "Applying rule 'adde_to_addo'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'adde_to_addo'\n"
; } } while (false)
;
3632 Helper.applyBuildFnNoErase(*MIs[0], MatchData75);
3633 return true;
3634 }
3635 }
3636 return false;
3637 }
3638 if (Partition == 59 /* TargetOpcode::G_SSUBE */) {
3639 // Leaf name: adde_to_addo
3640 // Rule: adde_to_addo
3641 if (!RuleConfig->isRuleDisabled(75)) {
3642 if (1
3643 && [&]() {
3644 return Helper.matchAddEToAddO(*MIs[0], MatchData75);
3645 return true;
3646 }() ) {
3647 LLVM_DEBUG(dbgs() << "Applying rule 'adde_to_addo'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'adde_to_addo'\n"
; } } while (false)
;
3648 Helper.applyBuildFnNoErase(*MIs[0], MatchData75);
3649 return true;
3650 }
3651 }
3652 return false;
3653 }
3654 if (Partition == 60 /* TargetOpcode::G_FMINNUM */) {
3655 // Leaf name: combine_minmax_nan
3656 // Rule: combine_minmax_nan
3657 if (!RuleConfig->isRuleDisabled(76)) {
3658 if (1
3659 && [&]() {
3660 return Helper.matchCombineFMinMaxNaN(*MIs[0], MatchData76);
3661 return true;
3662 }() ) {
3663 LLVM_DEBUG(dbgs() << "Applying rule 'combine_minmax_nan'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_minmax_nan'\n"
; } } while (false)
;
3664 Helper.replaceSingleDefInstWithOperand(*MIs[0], MatchData76);
3665 return true;
3666 }
3667 }
3668 // Leaf name: fold_binop_into_select
3669 // Rule: fold_binop_into_select
3670 if (!RuleConfig->isRuleDisabled(105)) {
3671 if (1
3672 && [&]() {
3673 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
3674 return true;
3675 }() ) {
3676 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3677 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3678 return true;
3679 }
3680 }
3681 return false;
3682 }
3683 if (Partition == 61 /* TargetOpcode::G_FMAXNUM */) {
3684 // Leaf name: combine_minmax_nan
3685 // Rule: combine_minmax_nan
3686 if (!RuleConfig->isRuleDisabled(76)) {
3687 if (1
3688 && [&]() {
3689 return Helper.matchCombineFMinMaxNaN(*MIs[0], MatchData76);
3690 return true;
3691 }() ) {
3692 LLVM_DEBUG(dbgs() << "Applying rule 'combine_minmax_nan'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_minmax_nan'\n"
; } } while (false)
;
3693 Helper.replaceSingleDefInstWithOperand(*MIs[0], MatchData76);
3694 return true;
3695 }
3696 }
3697 // Leaf name: fold_binop_into_select
3698 // Rule: fold_binop_into_select
3699 if (!RuleConfig->isRuleDisabled(105)) {
3700 if (1
3701 && [&]() {
3702 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
3703 return true;
3704 }() ) {
3705 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3706 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3707 return true;
3708 }
3709 }
3710 return false;
3711 }
3712 if (Partition == 62 /* TargetOpcode::G_FMINIMUM */) {
3713 // Leaf name: combine_minmax_nan
3714 // Rule: combine_minmax_nan
3715 if (!RuleConfig->isRuleDisabled(76)) {
3716 if (1
3717 && [&]() {
3718 return Helper.matchCombineFMinMaxNaN(*MIs[0], MatchData76);
3719 return true;
3720 }() ) {
3721 LLVM_DEBUG(dbgs() << "Applying rule 'combine_minmax_nan'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_minmax_nan'\n"
; } } while (false)
;
3722 Helper.replaceSingleDefInstWithOperand(*MIs[0], MatchData76);
3723 return true;
3724 }
3725 }
3726 // Leaf name: fold_binop_into_select
3727 // Rule: fold_binop_into_select
3728 if (!RuleConfig->isRuleDisabled(105)) {
3729 if (1
3730 && [&]() {
3731 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
3732 return true;
3733 }() ) {
3734 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3735 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3736 return true;
3737 }
3738 }
3739 return false;
3740 }
3741 if (Partition == 63 /* TargetOpcode::G_FMAXIMUM */) {
3742 // Leaf name: combine_minmax_nan
3743 // Rule: combine_minmax_nan
3744 if (!RuleConfig->isRuleDisabled(76)) {
3745 if (1
3746 && [&]() {
3747 return Helper.matchCombineFMinMaxNaN(*MIs[0], MatchData76);
3748 return true;
3749 }() ) {
3750 LLVM_DEBUG(dbgs() << "Applying rule 'combine_minmax_nan'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_minmax_nan'\n"
; } } while (false)
;
3751 Helper.replaceSingleDefInstWithOperand(*MIs[0], MatchData76);
3752 return true;
3753 }
3754 }
3755 // Leaf name: fold_binop_into_select
3756 // Rule: fold_binop_into_select
3757 if (!RuleConfig->isRuleDisabled(105)) {
3758 if (1
3759 && [&]() {
3760 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
3761 return true;
3762 }() ) {
3763 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3764 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3765 return true;
3766 }
3767 }
3768 return false;
3769 }
3770 if (Partition == 64 /* TargetOpcode::G_SSHLSAT */) {
3771 // Leaf name: shift_immed_chain
3772 // Rule: shift_immed_chain
3773 if (!RuleConfig->isRuleDisabled(79)) {
3774 if (1
3775 && [&]() {
3776 return Helper.matchShiftImmedChain(*MIs[0], MatchData79);
3777 return true;
3778 }() ) {
3779 LLVM_DEBUG(dbgs() << "Applying rule 'shift_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_immed_chain'\n"
; } } while (false)
;
3780 Helper.applyShiftImmedChain(*MIs[0], MatchData79);
3781 return true;
3782 }
3783 }
3784 // Leaf name: shift_of_shifted_logic_chain
3785 // Rule: shift_of_shifted_logic_chain
3786 if (!RuleConfig->isRuleDisabled(80)) {
3787 if (1
3788 && [&]() {
3789 return Helper.matchShiftOfShiftedLogic(*MIs[0], MatchData80);
3790 return true;
3791 }() ) {
3792 LLVM_DEBUG(dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n"
; } } while (false)
;
3793 Helper.applyShiftOfShiftedLogic(*MIs[0], MatchData80);
3794 return true;
3795 }
3796 }
3797 return false;
3798 }
3799 if (Partition == 65 /* TargetOpcode::G_USHLSAT */) {
3800 // Leaf name: shift_immed_chain
3801 // Rule: shift_immed_chain
3802 if (!RuleConfig->isRuleDisabled(79)) {
3803 if (1
3804 && [&]() {
3805 return Helper.matchShiftImmedChain(*MIs[0], MatchData79);
3806 return true;
3807 }() ) {
3808 LLVM_DEBUG(dbgs() << "Applying rule 'shift_immed_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_immed_chain'\n"
; } } while (false)
;
3809 Helper.applyShiftImmedChain(*MIs[0], MatchData79);
3810 return true;
3811 }
3812 }
3813 // Leaf name: shift_of_shifted_logic_chain
3814 // Rule: shift_of_shifted_logic_chain
3815 if (!RuleConfig->isRuleDisabled(80)) {
3816 if (1
3817 && [&]() {
3818 return Helper.matchShiftOfShiftedLogic(*MIs[0], MatchData80);
3819 return true;
3820 }() ) {
3821 LLVM_DEBUG(dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'shift_of_shifted_logic_chain'\n"
; } } while (false)
;
3822 Helper.applyShiftOfShiftedLogic(*MIs[0], MatchData80);
3823 return true;
3824 }
3825 }
3826 return false;
3827 }
3828 if (Partition == 66 /* TargetOpcode::G_FSHL */) {
3829 // Leaf name: funnel_shift_to_rotate
3830 // Rule: funnel_shift_to_rotate
3831 if (!RuleConfig->isRuleDisabled(85)) {
3832 if (1
3833 && [&]() {
3834 return Helper.matchFunnelShiftToRotate(*MIs[0]);
3835 return true;
3836 }() ) {
3837 LLVM_DEBUG(dbgs() << "Applying rule 'funnel_shift_to_rotate'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'funnel_shift_to_rotate'\n"
; } } while (false)
;
3838 Helper.applyFunnelShiftToRotate(*MIs[0]);
3839 return true;
3840 }
3841 }
3842 return false;
3843 }
3844 if (Partition == 67 /* TargetOpcode::G_FSHR */) {
3845 // Leaf name: funnel_shift_to_rotate
3846 // Rule: funnel_shift_to_rotate
3847 if (!RuleConfig->isRuleDisabled(85)) {
3848 if (1
3849 && [&]() {
3850 return Helper.matchFunnelShiftToRotate(*MIs[0]);
3851 return true;
3852 }() ) {
3853 LLVM_DEBUG(dbgs() << "Applying rule 'funnel_shift_to_rotate'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'funnel_shift_to_rotate'\n"
; } } while (false)
;
3854 Helper.applyFunnelShiftToRotate(*MIs[0]);
3855 return true;
3856 }
3857 }
3858 return false;
3859 }
3860 if (Partition == 68 /* TargetOpcode::G_UMULH */) {
3861 // Leaf name: mulh_to_lshr
3862 // Rule: mulh_to_lshr
3863 if (!RuleConfig->isRuleDisabled(94)) {
3864 if (1
3865 && [&]() {
3866 return Helper.matchUMulHToLShr(*MIs[0]);
3867 return true;
3868 }() ) {
3869 LLVM_DEBUG(dbgs() << "Applying rule 'mulh_to_lshr'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'mulh_to_lshr'\n"
; } } while (false)
;
3870 Helper.applyUMulHToLShr(*MIs[0]);
3871 return true;
3872 }
3873 }
3874 return false;
3875 }
3876 if (Partition == 69 /* TargetOpcode::G_FADD */) {
3877 // Leaf name: redundant_neg_operands
3878 // Rule: redundant_neg_operands
3879 if (!RuleConfig->isRuleDisabled(95)) {
3880 if (1
3881 && [&]() {
3882 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
3883 return true;
3884 }() ) {
3885 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
3886 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
3887 return true;
3888 }
3889 }
3890 // Leaf name: combine_fadd_fmul_to_fmad_or_fma
3891 // Rule: combine_fadd_fmul_to_fmad_or_fma
3892 if (!RuleConfig->isRuleDisabled(97)) {
3893 if (1
3894 && [&]() {
3895 return Helper.matchCombineFAddFMulToFMadOrFMA(*MIs[0],
3896 MatchData97);
3897 return true;
3898 }() ) {
3899 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fadd_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fadd_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3900 Helper.applyBuildFn(*MIs[0], MatchData97);
3901 return true;
3902 }
3903 }
3904 // Leaf name: combine_fadd_fpext_fmul_to_fmad_or_fma
3905 // Rule: combine_fadd_fpext_fmul_to_fmad_or_fma
3906 if (!RuleConfig->isRuleDisabled(98)) {
3907 if (1
3908 && [&]() {
3909 return Helper.matchCombineFAddFpExtFMulToFMadOrFMA(*MIs[0],
3910 MatchData98);
3911 return true;
3912 }() ) {
3913 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fadd_fpext_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fadd_fpext_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3914 Helper.applyBuildFn(*MIs[0], MatchData98);
3915 return true;
3916 }
3917 }
3918 // Leaf name: combine_fadd_fma_fmul_to_fmad_or_fma
3919 // Rule: combine_fadd_fma_fmul_to_fmad_or_fma
3920 if (!RuleConfig->isRuleDisabled(99)) {
3921 if (1
3922 && [&]() {
3923 return Helper.matchCombineFAddFMAFMulToFMadOrFMA(*MIs[0],
3924 MatchData99);
3925 return true;
3926 }() ) {
3927 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fadd_fma_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fadd_fma_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3928 Helper.applyBuildFn(*MIs[0], MatchData99);
3929 return true;
3930 }
3931 }
3932 // Leaf name: combine_fadd_fpext_fma_fmul_to_fmad_or_fma
3933 // Rule: combine_fadd_fpext_fma_fmul_to_fmad_or_fma
3934 if (!RuleConfig->isRuleDisabled(100)) {
3935 if (1
3936 && [&]() {
3937 return Helper.matchCombineFAddFpExtFMulToFMadOrFMAAggressive(
3938 *MIs[0], MatchData100);
3939 return true;
3940 }() ) {
3941 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fadd_fpext_fma_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fadd_fpext_fma_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3942 Helper.applyBuildFn(*MIs[0], MatchData100);
3943 return true;
3944 }
3945 }
3946 // Leaf name: fold_binop_into_select
3947 // Rule: fold_binop_into_select
3948 if (!RuleConfig->isRuleDisabled(105)) {
3949 if (1
3950 && [&]() {
3951 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
3952 return true;
3953 }() ) {
3954 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
3955 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
3956 return true;
3957 }
3958 }
3959 return false;
3960 }
3961 if (Partition == 70 /* TargetOpcode::G_FSUB */) {
3962 // Leaf name: redundant_neg_operands
3963 // Rule: redundant_neg_operands
3964 if (!RuleConfig->isRuleDisabled(95)) {
3965 if (1
3966 && [&]() {
3967 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
3968 return true;
3969 }() ) {
3970 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
3971 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
3972 return true;
3973 }
3974 }
3975 // Leaf name: combine_fsub_fmul_to_fmad_or_fma
3976 // Rule: combine_fsub_fmul_to_fmad_or_fma
3977 if (!RuleConfig->isRuleDisabled(101)) {
3978 if (1
3979 && [&]() {
3980 return Helper.matchCombineFSubFMulToFMadOrFMA(*MIs[0],
3981 MatchData101);
3982 return true;
3983 }() ) {
3984 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fsub_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fsub_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3985 Helper.applyBuildFn(*MIs[0], MatchData101);
3986 return true;
3987 }
3988 }
3989 // Leaf name: combine_fsub_fneg_fmul_to_fmad_or_fma
3990 // Rule: combine_fsub_fneg_fmul_to_fmad_or_fma
3991 if (!RuleConfig->isRuleDisabled(102)) {
3992 if (1
3993 && [&]() {
3994 return Helper.matchCombineFSubFNegFMulToFMadOrFMA(*MIs[0],
3995 MatchData102);
3996 return true;
3997 }() ) {
3998 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fsub_fneg_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fsub_fneg_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
3999 Helper.applyBuildFn(*MIs[0], MatchData102);
4000 return true;
4001 }
4002 }
4003 // Leaf name: combine_fsub_fpext_fmul_to_fmad_or_fma
4004 // Rule: combine_fsub_fpext_fmul_to_fmad_or_fma
4005 if (!RuleConfig->isRuleDisabled(103)) {
4006 if (1
4007 && [&]() {
4008 return Helper.matchCombineFSubFpExtFMulToFMadOrFMA(*MIs[0],
4009 MatchData103);
4010 return true;
4011 }() ) {
4012 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fsub_fpext_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fsub_fpext_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
4013 Helper.applyBuildFn(*MIs[0], MatchData103);
4014 return true;
4015 }
4016 }
4017 // Leaf name: combine_fsub_fpext_fneg_fmul_to_fmad_or_fma
4018 // Rule: combine_fsub_fpext_fneg_fmul_to_fmad_or_fma
4019 if (!RuleConfig->isRuleDisabled(104)) {
4020 if (1
4021 && [&]() {
4022 return Helper.matchCombineFSubFpExtFNegFMulToFMadOrFMA(
4023 *MIs[0], MatchData104);
4024 return true;
4025 }() ) {
4026 LLVM_DEBUG(dbgs() << "Applying rule 'combine_fsub_fpext_fneg_fmul_to_fmad_or_fma'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'combine_fsub_fpext_fneg_fmul_to_fmad_or_fma'\n"
; } } while (false)
;
4027 Helper.applyBuildFn(*MIs[0], MatchData104);
4028 return true;
4029 }
4030 }
4031 // Leaf name: fold_binop_into_select
4032 // Rule: fold_binop_into_select
4033 if (!RuleConfig->isRuleDisabled(105)) {
4034 if (1
4035 && [&]() {
4036 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4037 return true;
4038 }() ) {
4039 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4040 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4041 return true;
4042 }
4043 }
4044 // Leaf name: fsub_to_fneg
4045 // Rule: fsub_to_fneg
4046 if (!RuleConfig->isRuleDisabled(109)) {
4047 if (1
4048 && [&]() {
4049 return Helper.matchFsubToFneg(*MIs[0], MatchData109);
4050 return true;
4051 }() ) {
4052 LLVM_DEBUG(dbgs() << "Applying rule 'fsub_to_fneg'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fsub_to_fneg'\n"
; } } while (false)
;
4053 Helper.applyFsubToFneg(*MIs[0], MatchData109);
4054 return true;
4055 }
4056 }
4057 return false;
4058 }
4059 if (Partition == 71 /* TargetOpcode::G_FMUL */) {
4060 // Leaf name: redundant_neg_operands
4061 // Rule: redundant_neg_operands
4062 if (!RuleConfig->isRuleDisabled(95)) {
4063 if (1
4064 && [&]() {
4065 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
4066 return true;
4067 }() ) {
4068 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
4069 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
4070 return true;
4071 }
4072 }
4073 // Leaf name: fold_binop_into_select
4074 // Rule: fold_binop_into_select
4075 if (!RuleConfig->isRuleDisabled(105)) {
4076 if (1
4077 && [&]() {
4078 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4079 return true;
4080 }() ) {
4081 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4082 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4083 return true;
4084 }
4085 }
4086 return false;
4087 }
4088 if (Partition == 72 /* TargetOpcode::G_FDIV */) {
4089 // Leaf name: redundant_neg_operands
4090 // Rule: redundant_neg_operands
4091 if (!RuleConfig->isRuleDisabled(95)) {
4092 if (1
4093 && [&]() {
4094 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
4095 return true;
4096 }() ) {
4097 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
4098 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
4099 return true;
4100 }
4101 }
4102 // Leaf name: fold_binop_into_select
4103 // Rule: fold_binop_into_select
4104 if (!RuleConfig->isRuleDisabled(105)) {
4105 if (1
4106 && [&]() {
4107 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4108 return true;
4109 }() ) {
4110 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4111 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4112 return true;
4113 }
4114 }
4115 return false;
4116 }
4117 if (Partition == 73 /* TargetOpcode::G_FMAD */) {
4118 // Leaf name: redundant_neg_operands
4119 // Rule: redundant_neg_operands
4120 if (!RuleConfig->isRuleDisabled(95)) {
4121 if (1
4122 && [&]() {
4123 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
4124 return true;
4125 }() ) {
4126 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
4127 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
4128 return true;
4129 }
4130 }
4131 return false;
4132 }
4133 if (Partition == 74 /* TargetOpcode::G_FMA */) {
4134 // Leaf name: redundant_neg_operands
4135 // Rule: redundant_neg_operands
4136 if (!RuleConfig->isRuleDisabled(95)) {
4137 if (1
4138 && [&]() {
4139 return Helper.matchRedundantNegOperands(*MIs[0], MatchData95);
4140 return true;
4141 }() ) {
4142 LLVM_DEBUG(dbgs() << "Applying rule 'redundant_neg_operands'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'redundant_neg_operands'\n"
; } } while (false)
;
4143 Helper.applyBuildFnNoErase(*MIs[0], MatchData95);
4144 return true;
4145 }
4146 }
4147 return false;
4148 }
4149 if (Partition == 75 /* TargetOpcode::G_SMIN */) {
4150 // Leaf name: fold_binop_into_select
4151 // Rule: fold_binop_into_select
4152 if (!RuleConfig->isRuleDisabled(105)) {
4153 if (1
4154 && [&]() {
4155 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4156 return true;
4157 }() ) {
4158 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4159 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4160 return true;
4161 }
4162 }
4163 return false;
4164 }
4165 if (Partition == 76 /* TargetOpcode::G_SMAX */) {
4166 // Leaf name: fold_binop_into_select
4167 // Rule: fold_binop_into_select
4168 if (!RuleConfig->isRuleDisabled(105)) {
4169 if (1
4170 && [&]() {
4171 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4172 return true;
4173 }() ) {
4174 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4175 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4176 return true;
4177 }
4178 }
4179 return false;
4180 }
4181 if (Partition == 77 /* TargetOpcode::G_UMIN */) {
4182 // Leaf name: fold_binop_into_select
4183 // Rule: fold_binop_into_select
4184 if (!RuleConfig->isRuleDisabled(105)) {
4185 if (1
4186 && [&]() {
4187 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4188 return true;
4189 }() ) {
4190 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4191 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4192 return true;
4193 }
4194 }
4195 return false;
4196 }
4197 if (Partition == 78 /* TargetOpcode::G_UMAX */) {
4198 // Leaf name: fold_binop_into_select
4199 // Rule: fold_binop_into_select
4200 if (!RuleConfig->isRuleDisabled(105)) {
4201 if (1
4202 && [&]() {
4203 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4204 return true;
4205 }() ) {
4206 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4207 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4208 return true;
4209 }
4210 }
4211 return false;
4212 }
4213 if (Partition == 79 /* TargetOpcode::G_FREM */) {
4214 // Leaf name: fold_binop_into_select
4215 // Rule: fold_binop_into_select
4216 if (!RuleConfig->isRuleDisabled(105)) {
4217 if (1
4218 && [&]() {
4219 return Helper.matchFoldBinOpIntoSelect(*MIs[0], MatchData105);
4220 return true;
4221 }() ) {
4222 LLVM_DEBUG(dbgs() << "Applying rule 'fold_binop_into_select'\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpu-prelegalizer-combiner")) { dbgs() << "Applying rule 'fold_binop_into_select'\n"
; } } while (false)
;
4223 return Helper.applyFoldBinOpIntoSelect(*MIs[0], MatchData105);
4224 return true;
4225 }
4226 }
4227 return false;
4228 }
4229
4230 return false;
4231}
4232#endif // ifdef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP