Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1198, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AMDGPUISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This is the parent TargetLowering class for hardware code gen
11/// targets.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUISelLowering.h"
16#include "AMDGPU.h"
17#include "AMDGPUCallLowering.h"
18#include "AMDGPUFrameLowering.h"
19#include "AMDGPURegisterInfo.h"
20#include "AMDGPUSubtarget.h"
21#include "AMDGPUTargetMachine.h"
22#include "Utils/AMDGPUBaseInfo.h"
23#include "R600MachineFunctionInfo.h"
24#include "SIInstrInfo.h"
25#include "SIMachineFunctionInfo.h"
26#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
27#include "llvm/CodeGen/Analysis.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DataLayout.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/Support/KnownBits.h"
36#include "llvm/Support/MathExtras.h"
37using namespace llvm;
38
39#include "AMDGPUGenCallingConv.inc"
40
41// Find a larger type to do a load / store of a vector with.
42EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
43 unsigned StoreSize = VT.getStoreSizeInBits();
44 if (StoreSize <= 32)
45 return EVT::getIntegerVT(Ctx, StoreSize);
46
47 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32")((StoreSize % 32 == 0 && "Store size not a multiple of 32"
) ? static_cast<void> (0) : __assert_fail ("StoreSize % 32 == 0 && \"Store size not a multiple of 32\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 47, __PRETTY_FUNCTION__))
;
48 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
49}
50
51unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
52 EVT VT = Op.getValueType();
53 KnownBits Known = DAG.computeKnownBits(Op);
54 return VT.getSizeInBits() - Known.countMinLeadingZeros();
55}
56
57unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
58 EVT VT = Op.getValueType();
59
60 // In order for this to be a signed 24-bit value, bit 23, must
61 // be a sign bit.
62 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
63}
64
65AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
66 const AMDGPUSubtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
68 // Lower floating point store/load to integer store/load to reduce the number
69 // of patterns in tablegen.
70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
72
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
75
76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
78
79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
81
82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
83 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
84
85 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
86 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
87
88 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
89 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
90
91 setOperationAction(ISD::LOAD, MVT::v32f32, Promote);
92 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
93
94 setOperationAction(ISD::LOAD, MVT::i64, Promote);
95 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
96
97 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
98 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
99
100 setOperationAction(ISD::LOAD, MVT::f64, Promote);
101 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
102
103 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
104 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
105
106 // There are no 64-bit extloads. These should be done as a 32-bit extload and
107 // an extension to 64-bit.
108 for (MVT VT : MVT::integer_valuetypes()) {
109 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
110 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
112 }
113
114 for (MVT VT : MVT::integer_valuetypes()) {
115 if (VT == MVT::i64)
116 continue;
117
118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
122
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
127
128 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
129 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
130 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
132 }
133
134 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
135 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
138 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
150 }
151
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
154 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand);
155 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
156 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
158 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
159
160 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
161 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
164
165 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
168 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
169
170 setOperationAction(ISD::STORE, MVT::f32, Promote);
171 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
172
173 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
174 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
175
176 setOperationAction(ISD::STORE, MVT::v3f32, Promote);
177 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
178
179 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
180 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
181
182 setOperationAction(ISD::STORE, MVT::v5f32, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
184
185 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
186 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
187
188 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
189 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
190
191 setOperationAction(ISD::STORE, MVT::v32f32, Promote);
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
193
194 setOperationAction(ISD::STORE, MVT::i64, Promote);
195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
196
197 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
198 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
199
200 setOperationAction(ISD::STORE, MVT::f64, Promote);
201 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
202
203 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
205
206 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
207 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
208 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
209 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
210
211 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
212 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
213 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
214 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
215
216 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
217 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
218 setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand);
219 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
220 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
221 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand);
222 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand);
223
224 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
225 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
226
227 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
228 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
229
230 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
231 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
232
233 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
234 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
235
236
237 setOperationAction(ISD::Constant, MVT::i32, Legal);
238 setOperationAction(ISD::Constant, MVT::i64, Legal);
239 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
240 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
241
242 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
243 setOperationAction(ISD::BRIND, MVT::Other, Expand);
244
245 // This is totally unsupported, just custom lower to produce an error.
246 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
247
248 // Library functions. These default to Expand, but we have instructions
249 // for them.
250 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
251 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
252 setOperationAction(ISD::FPOW, MVT::f32, Legal);
253 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
254 setOperationAction(ISD::FABS, MVT::f32, Legal);
255 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
256 setOperationAction(ISD::FRINT, MVT::f32, Legal);
257 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
258 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
259 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
260
261 setOperationAction(ISD::FROUND, MVT::f32, Custom);
262 setOperationAction(ISD::FROUND, MVT::f64, Custom);
263
264 setOperationAction(ISD::FLOG, MVT::f32, Custom);
265 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
266 setOperationAction(ISD::FEXP, MVT::f32, Custom);
267
268
269 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
270 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
271
272 setOperationAction(ISD::FREM, MVT::f32, Custom);
273 setOperationAction(ISD::FREM, MVT::f64, Custom);
274
275 // Expand to fneg + fadd.
276 setOperationAction(ISD::FSUB, MVT::f64, Expand);
277
278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
280 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
286 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
287 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
288 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
289 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
290 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
291 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
292 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
293 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
294 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
295 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
296 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
297 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
298 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
299 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
300
301 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
302 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
303 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
304
305 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
306 for (MVT VT : ScalarIntVTs) {
307 // These should use [SU]DIVREM, so set them to expand
308 setOperationAction(ISD::SDIV, VT, Expand);
309 setOperationAction(ISD::UDIV, VT, Expand);
310 setOperationAction(ISD::SREM, VT, Expand);
311 setOperationAction(ISD::UREM, VT, Expand);
312
313 // GPU does not have divrem function for signed or unsigned.
314 setOperationAction(ISD::SDIVREM, VT, Custom);
315 setOperationAction(ISD::UDIVREM, VT, Custom);
316
317 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
318 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
319 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
320
321 setOperationAction(ISD::BSWAP, VT, Expand);
322 setOperationAction(ISD::CTTZ, VT, Expand);
323 setOperationAction(ISD::CTLZ, VT, Expand);
324
325 // AMDGPU uses ADDC/SUBC/ADDE/SUBE
326 setOperationAction(ISD::ADDC, VT, Legal);
327 setOperationAction(ISD::SUBC, VT, Legal);
328 setOperationAction(ISD::ADDE, VT, Legal);
329 setOperationAction(ISD::SUBE, VT, Legal);
330 }
331
332 // The hardware supports 32-bit ROTR, but not ROTL.
333 setOperationAction(ISD::ROTL, MVT::i32, Expand);
334 setOperationAction(ISD::ROTL, MVT::i64, Expand);
335 setOperationAction(ISD::ROTR, MVT::i64, Expand);
336
337 setOperationAction(ISD::MUL, MVT::i64, Expand);
338 setOperationAction(ISD::MULHU, MVT::i64, Expand);
339 setOperationAction(ISD::MULHS, MVT::i64, Expand);
340 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
341 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
343 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
344 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
345
346 setOperationAction(ISD::SMIN, MVT::i32, Legal);
347 setOperationAction(ISD::UMIN, MVT::i32, Legal);
348 setOperationAction(ISD::SMAX, MVT::i32, Legal);
349 setOperationAction(ISD::UMAX, MVT::i32, Legal);
350
351 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
352 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
353 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
355
356 static const MVT::SimpleValueType VectorIntTypes[] = {
357 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32
358 };
359
360 for (MVT VT : VectorIntTypes) {
361 // Expand the following operations for the current type by default.
362 setOperationAction(ISD::ADD, VT, Expand);
363 setOperationAction(ISD::AND, VT, Expand);
364 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
365 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
366 setOperationAction(ISD::MUL, VT, Expand);
367 setOperationAction(ISD::MULHU, VT, Expand);
368 setOperationAction(ISD::MULHS, VT, Expand);
369 setOperationAction(ISD::OR, VT, Expand);
370 setOperationAction(ISD::SHL, VT, Expand);
371 setOperationAction(ISD::SRA, VT, Expand);
372 setOperationAction(ISD::SRL, VT, Expand);
373 setOperationAction(ISD::ROTL, VT, Expand);
374 setOperationAction(ISD::ROTR, VT, Expand);
375 setOperationAction(ISD::SUB, VT, Expand);
376 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
377 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
378 setOperationAction(ISD::SDIV, VT, Expand);
379 setOperationAction(ISD::UDIV, VT, Expand);
380 setOperationAction(ISD::SREM, VT, Expand);
381 setOperationAction(ISD::UREM, VT, Expand);
382 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
383 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
384 setOperationAction(ISD::SDIVREM, VT, Custom);
385 setOperationAction(ISD::UDIVREM, VT, Expand);
386 setOperationAction(ISD::SELECT, VT, Expand);
387 setOperationAction(ISD::VSELECT, VT, Expand);
388 setOperationAction(ISD::SELECT_CC, VT, Expand);
389 setOperationAction(ISD::XOR, VT, Expand);
390 setOperationAction(ISD::BSWAP, VT, Expand);
391 setOperationAction(ISD::CTPOP, VT, Expand);
392 setOperationAction(ISD::CTTZ, VT, Expand);
393 setOperationAction(ISD::CTLZ, VT, Expand);
394 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
395 setOperationAction(ISD::SETCC, VT, Expand);
396 }
397
398 static const MVT::SimpleValueType FloatVectorTypes[] = {
399 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32
400 };
401
402 for (MVT VT : FloatVectorTypes) {
403 setOperationAction(ISD::FABS, VT, Expand);
404 setOperationAction(ISD::FMINNUM, VT, Expand);
405 setOperationAction(ISD::FMAXNUM, VT, Expand);
406 setOperationAction(ISD::FADD, VT, Expand);
407 setOperationAction(ISD::FCEIL, VT, Expand);
408 setOperationAction(ISD::FCOS, VT, Expand);
409 setOperationAction(ISD::FDIV, VT, Expand);
410 setOperationAction(ISD::FEXP2, VT, Expand);
411 setOperationAction(ISD::FEXP, VT, Expand);
412 setOperationAction(ISD::FLOG2, VT, Expand);
413 setOperationAction(ISD::FREM, VT, Expand);
414 setOperationAction(ISD::FLOG, VT, Expand);
415 setOperationAction(ISD::FLOG10, VT, Expand);
416 setOperationAction(ISD::FPOW, VT, Expand);
417 setOperationAction(ISD::FFLOOR, VT, Expand);
418 setOperationAction(ISD::FTRUNC, VT, Expand);
419 setOperationAction(ISD::FMUL, VT, Expand);
420 setOperationAction(ISD::FMA, VT, Expand);
421 setOperationAction(ISD::FRINT, VT, Expand);
422 setOperationAction(ISD::FNEARBYINT, VT, Expand);
423 setOperationAction(ISD::FSQRT, VT, Expand);
424 setOperationAction(ISD::FSIN, VT, Expand);
425 setOperationAction(ISD::FSUB, VT, Expand);
426 setOperationAction(ISD::FNEG, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SELECT_CC, VT, Expand);
429 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
430 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
431 setOperationAction(ISD::SETCC, VT, Expand);
432 setOperationAction(ISD::FCANONICALIZE, VT, Expand);
433 }
434
435 // This causes using an unrolled select operation rather than expansion with
436 // bit operations. This is in general better, but the alternative using BFI
437 // instructions may be better if the select sources are SGPRs.
438 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
439 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
440
441 setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
442 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
443
444 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
445 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
446
447 setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
448 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
449
450 // There are no libcalls of any kind.
451 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
452 setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
453
454 setSchedulingPreference(Sched::RegPressure);
455 setJumpIsExpensive(true);
456
457 // FIXME: This is only partially true. If we have to do vector compares, any
458 // SGPR pair can be a condition register. If we have a uniform condition, we
459 // are better off doing SALU operations, where there is only one SCC. For now,
460 // we don't have a way of knowing during instruction selection if a condition
461 // will be uniform and we always use vector compares. Assume we are using
462 // vector compares until that is fixed.
463 setHasMultipleConditionRegisters(true);
464
465 setMinCmpXchgSizeInBits(32);
466 setSupportsUnalignedAtomics(false);
467
468 PredictableSelectIsExpensive = false;
469
470 // We want to find all load dependencies for long chains of stores to enable
471 // merging into very wide vectors. The problem is with vectors with > 4
472 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
473 // vectors are a legal type, even though we have to split the loads
474 // usually. When we can more precisely specify load legality per address
475 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
476 // smarter so that they can figure out what to do in 2 iterations without all
477 // N > 4 stores on the same chain.
478 GatherAllAliasesMaxDepth = 16;
479
480 // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
481 // about these during lowering.
482 MaxStoresPerMemcpy = 0xffffffff;
483 MaxStoresPerMemmove = 0xffffffff;
484 MaxStoresPerMemset = 0xffffffff;
485
486 setTargetDAGCombine(ISD::BITCAST);
487 setTargetDAGCombine(ISD::SHL);
488 setTargetDAGCombine(ISD::SRA);
489 setTargetDAGCombine(ISD::SRL);
490 setTargetDAGCombine(ISD::TRUNCATE);
491 setTargetDAGCombine(ISD::MUL);
492 setTargetDAGCombine(ISD::MULHU);
493 setTargetDAGCombine(ISD::MULHS);
494 setTargetDAGCombine(ISD::SELECT);
495 setTargetDAGCombine(ISD::SELECT_CC);
496 setTargetDAGCombine(ISD::STORE);
497 setTargetDAGCombine(ISD::FADD);
498 setTargetDAGCombine(ISD::FSUB);
499 setTargetDAGCombine(ISD::FNEG);
500 setTargetDAGCombine(ISD::FABS);
501 setTargetDAGCombine(ISD::AssertZext);
502 setTargetDAGCombine(ISD::AssertSext);
503 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
504}
505
506//===----------------------------------------------------------------------===//
507// Target Information
508//===----------------------------------------------------------------------===//
509
510LLVM_READNONE__attribute__((__const__))
511static bool fnegFoldsIntoOp(unsigned Opc) {
512 switch (Opc) {
513 case ISD::FADD:
514 case ISD::FSUB:
515 case ISD::FMUL:
516 case ISD::FMA:
517 case ISD::FMAD:
518 case ISD::FMINNUM:
519 case ISD::FMAXNUM:
520 case ISD::FMINNUM_IEEE:
521 case ISD::FMAXNUM_IEEE:
522 case ISD::FSIN:
523 case ISD::FTRUNC:
524 case ISD::FRINT:
525 case ISD::FNEARBYINT:
526 case ISD::FCANONICALIZE:
527 case AMDGPUISD::RCP:
528 case AMDGPUISD::RCP_LEGACY:
529 case AMDGPUISD::RCP_IFLAG:
530 case AMDGPUISD::SIN_HW:
531 case AMDGPUISD::FMUL_LEGACY:
532 case AMDGPUISD::FMIN_LEGACY:
533 case AMDGPUISD::FMAX_LEGACY:
534 case AMDGPUISD::FMED3:
535 return true;
536 default:
537 return false;
538 }
539}
540
541/// \p returns true if the operation will definitely need to use a 64-bit
542/// encoding, and thus will use a VOP3 encoding regardless of the source
543/// modifiers.
544LLVM_READONLY__attribute__((__pure__))
545static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
546 return N->getNumOperands() > 2 || VT == MVT::f64;
547}
548
549// Most FP instructions support source modifiers, but this could be refined
550// slightly.
551LLVM_READONLY__attribute__((__pure__))
552static bool hasSourceMods(const SDNode *N) {
553 if (isa<MemSDNode>(N))
554 return false;
555
556 switch (N->getOpcode()) {
557 case ISD::CopyToReg:
558 case ISD::SELECT:
559 case ISD::FDIV:
560 case ISD::FREM:
561 case ISD::INLINEASM:
562 case ISD::INLINEASM_BR:
563 case AMDGPUISD::DIV_SCALE:
564 case ISD::INTRINSIC_W_CHAIN:
565
566 // TODO: Should really be looking at the users of the bitcast. These are
567 // problematic because bitcasts are used to legalize all stores to integer
568 // types.
569 case ISD::BITCAST:
570 return false;
571 case ISD::INTRINSIC_WO_CHAIN: {
572 switch (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue()) {
573 case Intrinsic::amdgcn_interp_p1:
574 case Intrinsic::amdgcn_interp_p2:
575 case Intrinsic::amdgcn_interp_mov:
576 case Intrinsic::amdgcn_interp_p1_f16:
577 case Intrinsic::amdgcn_interp_p2_f16:
578 return false;
579 default:
580 return true;
581 }
582 }
583 default:
584 return true;
585 }
586}
587
588bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
589 unsigned CostThreshold) {
590 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
591 // it is truly free to use a source modifier in all cases. If there are
592 // multiple users but for each one will necessitate using VOP3, there will be
593 // a code size increase. Try to avoid increasing code size unless we know it
594 // will save on the instruction count.
595 unsigned NumMayIncreaseSize = 0;
596 MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
597
598 // XXX - Should this limit number of uses to check?
599 for (const SDNode *U : N->uses()) {
600 if (!hasSourceMods(U))
601 return false;
602
603 if (!opMustUseVOP3Encoding(U, VT)) {
604 if (++NumMayIncreaseSize > CostThreshold)
605 return false;
606 }
607 }
608
609 return true;
610}
611
612MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
613 return MVT::i32;
614}
615
616bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
617 return true;
618}
619
620// The backend supports 32 and 64 bit floating point immediates.
621// FIXME: Why are we reporting vectors of FP immediates as legal?
622bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
623 bool ForCodeSize) const {
624 EVT ScalarVT = VT.getScalarType();
625 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
626 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
627}
628
629// We don't want to shrink f64 / f32 constants.
630bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
631 EVT ScalarVT = VT.getScalarType();
632 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
633}
634
635bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
636 ISD::LoadExtType ExtTy,
637 EVT NewVT) const {
638 // TODO: This may be worth removing. Check regression tests for diffs.
639 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
640 return false;
641
642 unsigned NewSize = NewVT.getStoreSizeInBits();
643
644 // If we are reducing to a 32-bit load, this is always better.
645 if (NewSize == 32)
646 return true;
647
648 EVT OldVT = N->getValueType(0);
649 unsigned OldSize = OldVT.getStoreSizeInBits();
650
651 MemSDNode *MN = cast<MemSDNode>(N);
652 unsigned AS = MN->getAddressSpace();
653 // Do not shrink an aligned scalar load to sub-dword.
654 // Scalar engine cannot do sub-dword loads.
655 if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
656 (AS == AMDGPUAS::CONSTANT_ADDRESS ||
657 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
658 (isa<LoadSDNode>(N) &&
659 AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
660 AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand()))
661 return false;
662
663 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
664 // extloads, so doing one requires using a buffer_load. In cases where we
665 // still couldn't use a scalar load, using the wider load shouldn't really
666 // hurt anything.
667
668 // If the old size already had to be an extload, there's no harm in continuing
669 // to reduce the width.
670 return (OldSize < 32);
671}
672
673bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
674 const SelectionDAG &DAG,
675 const MachineMemOperand &MMO) const {
676
677 assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits())((LoadTy.getSizeInBits() == CastTy.getSizeInBits()) ? static_cast
<void> (0) : __assert_fail ("LoadTy.getSizeInBits() == CastTy.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 677, __PRETTY_FUNCTION__))
;
678
679 if (LoadTy.getScalarType() == MVT::i32)
680 return false;
681
682 unsigned LScalarSize = LoadTy.getScalarSizeInBits();
683 unsigned CastScalarSize = CastTy.getScalarSizeInBits();
684
685 if ((LScalarSize >= CastScalarSize) && (CastScalarSize < 32))
686 return false;
687
688 bool Fast = false;
689 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
690 CastTy, MMO, &Fast) &&
691 Fast;
692}
693
694// SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
695// profitable with the expansion for 64-bit since it's generally good to
696// speculate things.
697// FIXME: These should really have the size as a parameter.
698bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
699 return true;
700}
701
702bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
703 return true;
704}
705
706bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {
707 switch (N->getOpcode()) {
708 default:
709 return false;
710 case ISD::EntryToken:
711 case ISD::TokenFactor:
712 return true;
713 case ISD::INTRINSIC_WO_CHAIN:
714 {
715 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
716 switch (IntrID) {
717 default:
718 return false;
719 case Intrinsic::amdgcn_readfirstlane:
720 case Intrinsic::amdgcn_readlane:
721 return true;
722 }
723 }
724 break;
725 case ISD::LOAD:
726 {
727 if (cast<LoadSDNode>(N)->getMemOperand()->getAddrSpace() ==
728 AMDGPUAS::CONSTANT_ADDRESS_32BIT)
729 return true;
730 return false;
731 }
732 break;
733 }
734}
735
736//===---------------------------------------------------------------------===//
737// Target Properties
738//===---------------------------------------------------------------------===//
739
740bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
741 assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 741, __PRETTY_FUNCTION__))
;
742
743 // Packed operations do not have a fabs modifier.
744 return VT == MVT::f32 || VT == MVT::f64 ||
745 (Subtarget->has16BitInsts() && VT == MVT::f16);
746}
747
748bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
749 assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 749, __PRETTY_FUNCTION__))
;
750 return VT == MVT::f32 || VT == MVT::f64 ||
751 (Subtarget->has16BitInsts() && VT == MVT::f16) ||
752 (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
753}
754
755bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
756 unsigned NumElem,
757 unsigned AS) const {
758 return true;
759}
760
761bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
762 // There are few operations which truly have vector input operands. Any vector
763 // operation is going to involve operations on each component, and a
764 // build_vector will be a copy per element, so it always makes sense to use a
765 // build_vector input in place of the extracted element to avoid a copy into a
766 // super register.
767 //
768 // We should probably only do this if all users are extracts only, but this
769 // should be the common case.
770 return true;
771}
772
773bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
774 // Truncate is just accessing a subregister.
775
776 unsigned SrcSize = Source.getSizeInBits();
777 unsigned DestSize = Dest.getSizeInBits();
778
779 return DestSize < SrcSize && DestSize % 32 == 0 ;
780}
781
782bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
783 // Truncate is just accessing a subregister.
784
785 unsigned SrcSize = Source->getScalarSizeInBits();
786 unsigned DestSize = Dest->getScalarSizeInBits();
787
788 if (DestSize== 16 && Subtarget->has16BitInsts())
789 return SrcSize >= 32;
790
791 return DestSize < SrcSize && DestSize % 32 == 0;
792}
793
794bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
795 unsigned SrcSize = Src->getScalarSizeInBits();
796 unsigned DestSize = Dest->getScalarSizeInBits();
797
798 if (SrcSize == 16 && Subtarget->has16BitInsts())
799 return DestSize >= 32;
800
801 return SrcSize == 32 && DestSize == 64;
802}
803
804bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
805 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
806 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
807 // this will enable reducing 64-bit operations the 32-bit, which is always
808 // good.
809
810 if (Src == MVT::i16)
811 return Dest == MVT::i32 ||Dest == MVT::i64 ;
812
813 return Src == MVT::i32 && Dest == MVT::i64;
814}
815
816bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
817 return isZExtFree(Val.getValueType(), VT2);
818}
819
820bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
821 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
822 // limited number of native 64-bit operations. Shrinking an operation to fit
823 // in a single 32-bit register should always be helpful. As currently used,
824 // this is much less general than the name suggests, and is only used in
825 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
826 // not profitable, and may actually be harmful.
827 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
828}
829
830//===---------------------------------------------------------------------===//
831// TargetLowering Callbacks
832//===---------------------------------------------------------------------===//
833
834CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
835 bool IsVarArg) {
836 switch (CC) {
837 case CallingConv::AMDGPU_VS:
838 case CallingConv::AMDGPU_GS:
839 case CallingConv::AMDGPU_PS:
840 case CallingConv::AMDGPU_CS:
841 case CallingConv::AMDGPU_HS:
842 case CallingConv::AMDGPU_ES:
843 case CallingConv::AMDGPU_LS:
844 return CC_AMDGPU;
845 case CallingConv::C:
846 case CallingConv::Fast:
847 case CallingConv::Cold:
848 return CC_AMDGPU_Func;
849 case CallingConv::AMDGPU_KERNEL:
850 case CallingConv::SPIR_KERNEL:
851 default:
852 report_fatal_error("Unsupported calling convention for call");
853 }
854}
855
856CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
857 bool IsVarArg) {
858 switch (CC) {
859 case CallingConv::AMDGPU_KERNEL:
860 case CallingConv::SPIR_KERNEL:
861 llvm_unreachable("kernels should not be handled here")::llvm::llvm_unreachable_internal("kernels should not be handled here"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 861)
;
862 case CallingConv::AMDGPU_VS:
863 case CallingConv::AMDGPU_GS:
864 case CallingConv::AMDGPU_PS:
865 case CallingConv::AMDGPU_CS:
866 case CallingConv::AMDGPU_HS:
867 case CallingConv::AMDGPU_ES:
868 case CallingConv::AMDGPU_LS:
869 return RetCC_SI_Shader;
870 case CallingConv::C:
871 case CallingConv::Fast:
872 case CallingConv::Cold:
873 return RetCC_AMDGPU_Func;
874 default:
875 report_fatal_error("Unsupported calling convention.");
876 }
877}
878
879/// The SelectionDAGBuilder will automatically promote function arguments
880/// with illegal types. However, this does not work for the AMDGPU targets
881/// since the function arguments are stored in memory as these illegal types.
882/// In order to handle this properly we need to get the original types sizes
883/// from the LLVM IR Function and fixup the ISD:InputArg values before
884/// passing them to AnalyzeFormalArguments()
885
886/// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
887/// input values across multiple registers. Each item in the Ins array
888/// represents a single value that will be stored in registers. Ins[x].VT is
889/// the value type of the value that will be stored in the register, so
890/// whatever SDNode we lower the argument to needs to be this type.
891///
892/// In order to correctly lower the arguments we need to know the size of each
893/// argument. Since Ins[x].VT gives us the size of the register that will
894/// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
895/// for the orignal function argument so that we can deduce the correct memory
896/// type to use for Ins[x]. In most cases the correct memory type will be
897/// Ins[x].ArgVT. However, this will not always be the case. If, for example,
898/// we have a kernel argument of type v8i8, this argument will be split into
899/// 8 parts and each part will be represented by its own item in the Ins array.
900/// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
901/// the argument before it was split. From this, we deduce that the memory type
902/// for each individual part is i8. We pass the memory type as LocVT to the
903/// calling convention analysis function and the register type (Ins[x].VT) as
904/// the ValVT.
905void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
906 CCState &State,
907 const SmallVectorImpl<ISD::InputArg> &Ins) const {
908 const MachineFunction &MF = State.getMachineFunction();
909 const Function &Fn = MF.getFunction();
910 LLVMContext &Ctx = Fn.getParent()->getContext();
911 const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
912 const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
913 CallingConv::ID CC = Fn.getCallingConv();
914
915 unsigned MaxAlign = 1;
916 uint64_t ExplicitArgOffset = 0;
917 const DataLayout &DL = Fn.getParent()->getDataLayout();
918
919 unsigned InIndex = 0;
920
921 for (const Argument &Arg : Fn.args()) {
922 Type *BaseArgTy = Arg.getType();
923 unsigned Align = DL.getABITypeAlignment(BaseArgTy);
924 MaxAlign = std::max(Align, MaxAlign);
925 unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
926
927 uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
928 ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
929
930 // We're basically throwing away everything passed into us and starting over
931 // to get accurate in-memory offsets. The "PartOffset" is completely useless
932 // to us as computed in Ins.
933 //
934 // We also need to figure out what type legalization is trying to do to get
935 // the correct memory offsets.
936
937 SmallVector<EVT, 16> ValueVTs;
938 SmallVector<uint64_t, 16> Offsets;
939 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
940
941 for (unsigned Value = 0, NumValues = ValueVTs.size();
942 Value != NumValues; ++Value) {
943 uint64_t BasePartOffset = Offsets[Value];
944
945 EVT ArgVT = ValueVTs[Value];
946 EVT MemVT = ArgVT;
947 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
948 unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
949
950 if (NumRegs == 1) {
951 // This argument is not split, so the IR type is the memory type.
952 if (ArgVT.isExtended()) {
953 // We have an extended type, like i24, so we should just use the
954 // register type.
955 MemVT = RegisterVT;
956 } else {
957 MemVT = ArgVT;
958 }
959 } else if (ArgVT.isVector() && RegisterVT.isVector() &&
960 ArgVT.getScalarType() == RegisterVT.getScalarType()) {
961 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements())((ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements
()) ? static_cast<void> (0) : __assert_fail ("ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 961, __PRETTY_FUNCTION__))
;
962 // We have a vector value which has been split into a vector with
963 // the same scalar type, but fewer elements. This should handle
964 // all the floating-point vector types.
965 MemVT = RegisterVT;
966 } else if (ArgVT.isVector() &&
967 ArgVT.getVectorNumElements() == NumRegs) {
968 // This arg has been split so that each element is stored in a separate
969 // register.
970 MemVT = ArgVT.getScalarType();
971 } else if (ArgVT.isExtended()) {
972 // We have an extended type, like i65.
973 MemVT = RegisterVT;
974 } else {
975 unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
976 assert(ArgVT.getStoreSizeInBits() % NumRegs == 0)((ArgVT.getStoreSizeInBits() % NumRegs == 0) ? static_cast<
void> (0) : __assert_fail ("ArgVT.getStoreSizeInBits() % NumRegs == 0"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 976, __PRETTY_FUNCTION__))
;
977 if (RegisterVT.isInteger()) {
978 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
979 } else if (RegisterVT.isVector()) {
980 assert(!RegisterVT.getScalarType().isFloatingPoint())((!RegisterVT.getScalarType().isFloatingPoint()) ? static_cast
<void> (0) : __assert_fail ("!RegisterVT.getScalarType().isFloatingPoint()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 980, __PRETTY_FUNCTION__))
;
981 unsigned NumElements = RegisterVT.getVectorNumElements();
982 assert(MemoryBits % NumElements == 0)((MemoryBits % NumElements == 0) ? static_cast<void> (0
) : __assert_fail ("MemoryBits % NumElements == 0", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 982, __PRETTY_FUNCTION__))
;
983 // This vector type has been split into another vector type with
984 // a different elements size.
985 EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
986 MemoryBits / NumElements);
987 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
988 } else {
989 llvm_unreachable("cannot deduce memory type.")::llvm::llvm_unreachable_internal("cannot deduce memory type."
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 989)
;
990 }
991 }
992
993 // Convert one element vectors to scalar.
994 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
995 MemVT = MemVT.getScalarType();
996
997 // Round up vec3/vec5 argument.
998 if (MemVT.isVector() && !MemVT.isPow2VectorType()) {
999 assert(MemVT.getVectorNumElements() == 3 ||((MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements
() == 5) ? static_cast<void> (0) : __assert_fail ("MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements() == 5"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1000, __PRETTY_FUNCTION__))
1000 MemVT.getVectorNumElements() == 5)((MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements
() == 5) ? static_cast<void> (0) : __assert_fail ("MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements() == 5"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1000, __PRETTY_FUNCTION__))
;
1001 MemVT = MemVT.getPow2VectorType(State.getContext());
1002 }
1003
1004 unsigned PartOffset = 0;
1005 for (unsigned i = 0; i != NumRegs; ++i) {
1006 State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1007 BasePartOffset + PartOffset,
1008 MemVT.getSimpleVT(),
1009 CCValAssign::Full));
1010 PartOffset += MemVT.getStoreSize();
1011 }
1012 }
1013 }
1014}
1015
1016SDValue AMDGPUTargetLowering::LowerReturn(
1017 SDValue Chain, CallingConv::ID CallConv,
1018 bool isVarArg,
1019 const SmallVectorImpl<ISD::OutputArg> &Outs,
1020 const SmallVectorImpl<SDValue> &OutVals,
1021 const SDLoc &DL, SelectionDAG &DAG) const {
1022 // FIXME: Fails for r600 tests
1023 //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1024 // "wave terminate should not have return values");
1025 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1026}
1027
1028//===---------------------------------------------------------------------===//
1029// Target specific lowering
1030//===---------------------------------------------------------------------===//
1031
1032/// Selects the correct CCAssignFn for a given CallingConvention value.
1033CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1034 bool IsVarArg) {
1035 return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1036}
1037
1038CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1039 bool IsVarArg) {
1040 return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1041}
1042
1043SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1044 SelectionDAG &DAG,
1045 MachineFrameInfo &MFI,
1046 int ClobberedFI) const {
1047 SmallVector<SDValue, 8> ArgChains;
1048 int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1049 int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1050
1051 // Include the original chain at the beginning of the list. When this is
1052 // used by target LowerCall hooks, this helps legalize find the
1053 // CALLSEQ_BEGIN node.
1054 ArgChains.push_back(Chain);
1055
1056 // Add a chain value for each stack argument corresponding
1057 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1058 UE = DAG.getEntryNode().getNode()->use_end();
1059 U != UE; ++U) {
1060 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1061 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1062 if (FI->getIndex() < 0) {
1063 int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1064 int64_t InLastByte = InFirstByte;
1065 InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1066
1067 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1068 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1069 ArgChains.push_back(SDValue(L, 1));
1070 }
1071 }
1072 }
1073 }
1074
1075 // Build a tokenfactor for all the chains.
1076 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1077}
1078
1079SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1080 SmallVectorImpl<SDValue> &InVals,
1081 StringRef Reason) const {
1082 SDValue Callee = CLI.Callee;
1083 SelectionDAG &DAG = CLI.DAG;
1084
1085 const Function &Fn = DAG.getMachineFunction().getFunction();
1086
1087 StringRef FuncName("<unknown>");
1088
1089 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1090 FuncName = G->getSymbol();
1091 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1092 FuncName = G->getGlobal()->getName();
1093
1094 DiagnosticInfoUnsupported NoCalls(
1095 Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1096 DAG.getContext()->diagnose(NoCalls);
1097
1098 if (!CLI.IsTailCall) {
1099 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1100 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1101 }
1102
1103 return DAG.getEntryNode();
1104}
1105
1106SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1107 SmallVectorImpl<SDValue> &InVals) const {
1108 return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1109}
1110
1111SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1112 SelectionDAG &DAG) const {
1113 const Function &Fn = DAG.getMachineFunction().getFunction();
1114
1115 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1116 SDLoc(Op).getDebugLoc());
1117 DAG.getContext()->diagnose(NoDynamicAlloca);
1118 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1119 return DAG.getMergeValues(Ops, SDLoc());
1120}
1121
1122SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1123 SelectionDAG &DAG) const {
1124 switch (Op.getOpcode()) {
1125 default:
1126 Op->print(errs(), &DAG);
1127 llvm_unreachable("Custom lowering code for this"::llvm::llvm_unreachable_internal("Custom lowering code for this"
"instruction is not implemented yet!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1128)
1128 "instruction is not implemented yet!")::llvm::llvm_unreachable_internal("Custom lowering code for this"
"instruction is not implemented yet!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1128)
;
1129 break;
1130 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1131 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1132 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1133 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1134 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1135 case ISD::FREM: return LowerFREM(Op, DAG);
1136 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1137 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1138 case ISD::FRINT: return LowerFRINT(Op, DAG);
1139 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1140 case ISD::FROUND: return LowerFROUND(Op, DAG);
1141 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1142 case ISD::FLOG:
1143 return LowerFLOG(Op, DAG, 1.0F / numbers::log2ef);
1144 case ISD::FLOG10:
1145 return LowerFLOG(Op, DAG, numbers::ln2f / numbers::ln10f);
1146 case ISD::FEXP:
1147 return lowerFEXP(Op, DAG);
1148 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1149 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1150 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1151 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1152 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1153 case ISD::CTTZ:
1154 case ISD::CTTZ_ZERO_UNDEF:
1155 case ISD::CTLZ:
1156 case ISD::CTLZ_ZERO_UNDEF:
1157 return LowerCTLZ_CTTZ(Op, DAG);
1158 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1159 }
1160 return Op;
1161}
1162
1163void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1164 SmallVectorImpl<SDValue> &Results,
1165 SelectionDAG &DAG) const {
1166 switch (N->getOpcode()) {
1167 case ISD::SIGN_EXTEND_INREG:
1168 // Different parts of legalization seem to interpret which type of
1169 // sign_extend_inreg is the one to check for custom lowering. The extended
1170 // from type is what really matters, but some places check for custom
1171 // lowering of the result type. This results in trying to use
1172 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1173 // nothing here and let the illegal result integer be handled normally.
1174 return;
1175 default:
1176 return;
1177 }
1178}
1179
1180bool AMDGPUTargetLowering::hasDefinedInitializer(const GlobalValue *GV) {
1181 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1182 if (!GVar || !GVar->hasInitializer())
1183 return false;
1184
1185 return !isa<UndefValue>(GVar->getInitializer());
1186}
1187
1188SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1189 SDValue Op,
1190 SelectionDAG &DAG) const {
1191
1192 const DataLayout &DL = DAG.getDataLayout();
1193 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1194 const GlobalValue *GV = G->getGlobal();
1195
1196 if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1197 G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
1198 if (!MFI->isEntryFunction()) {
1199 const Function &Fn = DAG.getMachineFunction().getFunction();
1200 DiagnosticInfoUnsupported BadLDSDecl(
1201 Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1202 DAG.getContext()->diagnose(BadLDSDecl);
1203 }
1204
1205 // XXX: What does the value of G->getOffset() mean?
1206 assert(G->getOffset() == 0 &&((G->getOffset() == 0 && "Do not know what to do with an non-zero offset"
) ? static_cast<void> (0) : __assert_fail ("G->getOffset() == 0 && \"Do not know what to do with an non-zero offset\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1207, __PRETTY_FUNCTION__))
1207 "Do not know what to do with an non-zero offset")((G->getOffset() == 0 && "Do not know what to do with an non-zero offset"
) ? static_cast<void> (0) : __assert_fail ("G->getOffset() == 0 && \"Do not know what to do with an non-zero offset\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1207, __PRETTY_FUNCTION__))
;
1208
1209 // TODO: We could emit code to handle the initialization somewhere.
1210 if (!hasDefinedInitializer(GV)) {
1211 unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1212 return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1213 }
1214 }
1215
1216 const Function &Fn = DAG.getMachineFunction().getFunction();
1217 DiagnosticInfoUnsupported BadInit(
1218 Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1219 DAG.getContext()->diagnose(BadInit);
1220 return SDValue();
1221}
1222
1223SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1224 SelectionDAG &DAG) const {
1225 SmallVector<SDValue, 8> Args;
1226
1227 EVT VT = Op.getValueType();
1228 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1229 SDLoc SL(Op);
1230 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1231 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1232
1233 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1234 return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1235 }
1236
1237 for (const SDUse &U : Op->ops())
1238 DAG.ExtractVectorElements(U.get(), Args);
1239
1240 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1241}
1242
1243SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1244 SelectionDAG &DAG) const {
1245
1246 SmallVector<SDValue, 8> Args;
1247 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1248 EVT VT = Op.getValueType();
1249 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1250 VT.getVectorNumElements());
1251
1252 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1253}
1254
1255/// Generate Min/Max node
1256SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1257 SDValue LHS, SDValue RHS,
1258 SDValue True, SDValue False,
1259 SDValue CC,
1260 DAGCombinerInfo &DCI) const {
1261 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1262 return SDValue();
1263
1264 SelectionDAG &DAG = DCI.DAG;
1265 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1266 switch (CCOpcode) {
1267 case ISD::SETOEQ:
1268 case ISD::SETONE:
1269 case ISD::SETUNE:
1270 case ISD::SETNE:
1271 case ISD::SETUEQ:
1272 case ISD::SETEQ:
1273 case ISD::SETFALSE:
1274 case ISD::SETFALSE2:
1275 case ISD::SETTRUE:
1276 case ISD::SETTRUE2:
1277 case ISD::SETUO:
1278 case ISD::SETO:
1279 break;
1280 case ISD::SETULE:
1281 case ISD::SETULT: {
1282 if (LHS == True)
1283 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1284 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1285 }
1286 case ISD::SETOLE:
1287 case ISD::SETOLT:
1288 case ISD::SETLE:
1289 case ISD::SETLT: {
1290 // Ordered. Assume ordered for undefined.
1291
1292 // Only do this after legalization to avoid interfering with other combines
1293 // which might occur.
1294 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1295 !DCI.isCalledByLegalizer())
1296 return SDValue();
1297
1298 // We need to permute the operands to get the correct NaN behavior. The
1299 // selected operand is the second one based on the failing compare with NaN,
1300 // so permute it based on the compare type the hardware uses.
1301 if (LHS == True)
1302 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1303 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1304 }
1305 case ISD::SETUGE:
1306 case ISD::SETUGT: {
1307 if (LHS == True)
1308 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1309 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1310 }
1311 case ISD::SETGT:
1312 case ISD::SETGE:
1313 case ISD::SETOGE:
1314 case ISD::SETOGT: {
1315 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1316 !DCI.isCalledByLegalizer())
1317 return SDValue();
1318
1319 if (LHS == True)
1320 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1321 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1322 }
1323 case ISD::SETCC_INVALID:
1324 llvm_unreachable("Invalid setcc condcode!")::llvm::llvm_unreachable_internal("Invalid setcc condcode!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1324)
;
1325 }
1326 return SDValue();
1327}
1328
1329std::pair<SDValue, SDValue>
1330AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1331 SDLoc SL(Op);
1332
1333 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1334
1335 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1336 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1337
1338 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1339 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1340
1341 return std::make_pair(Lo, Hi);
1342}
1343
1344SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1345 SDLoc SL(Op);
1346
1347 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1348 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1349 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1350}
1351
1352SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1353 SDLoc SL(Op);
1354
1355 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1356 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1357 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1358}
1359
1360// Split a vector type into two parts. The first part is a power of two vector.
1361// The second part is whatever is left over, and is a scalar if it would
1362// otherwise be a 1-vector.
1363std::pair<EVT, EVT>
1364AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1365 EVT LoVT, HiVT;
1366 EVT EltVT = VT.getVectorElementType();
1367 unsigned NumElts = VT.getVectorNumElements();
1368 unsigned LoNumElts = PowerOf2Ceil((NumElts + 1) / 2);
1369 LoVT = EVT::getVectorVT(*DAG.getContext(), EltVT, LoNumElts);
1370 HiVT = NumElts - LoNumElts == 1
1371 ? EltVT
1372 : EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts);
1373 return std::make_pair(LoVT, HiVT);
1374}
1375
1376// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
1377// scalar.
1378std::pair<SDValue, SDValue>
1379AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1380 const EVT &LoVT, const EVT &HiVT,
1381 SelectionDAG &DAG) const {
1382 assert(LoVT.getVectorNumElements() +((LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements
() : 1) <= N.getValueType().getVectorNumElements() &&
"More vector elements requested than available!") ? static_cast
<void> (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1385, __PRETTY_FUNCTION__))
1383 (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <=((LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements
() : 1) <= N.getValueType().getVectorNumElements() &&
"More vector elements requested than available!") ? static_cast
<void> (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1385, __PRETTY_FUNCTION__))
1384 N.getValueType().getVectorNumElements() &&((LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements
() : 1) <= N.getValueType().getVectorNumElements() &&
"More vector elements requested than available!") ? static_cast
<void> (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1385, __PRETTY_FUNCTION__))
1385 "More vector elements requested than available!")((LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements
() : 1) <= N.getValueType().getVectorNumElements() &&
"More vector elements requested than available!") ? static_cast
<void> (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1385, __PRETTY_FUNCTION__))
;
1386 auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1387 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
1388 DAG.getConstant(0, DL, IdxTy));
1389 SDValue Hi = DAG.getNode(
1390 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL,
1391 HiVT, N, DAG.getConstant(LoVT.getVectorNumElements(), DL, IdxTy));
1392 return std::make_pair(Lo, Hi);
1393}
1394
1395SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1396 SelectionDAG &DAG) const {
1397 LoadSDNode *Load = cast<LoadSDNode>(Op);
1398 EVT VT = Op.getValueType();
1399 SDLoc SL(Op);
1400
1401
1402 // If this is a 2 element vector, we really want to scalarize and not create
1403 // weird 1 element vectors.
1404 if (VT.getVectorNumElements() == 2) {
1405 SDValue Ops[2];
1406 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(Load, DAG);
1407 return DAG.getMergeValues(Ops, SL);
1408 }
1409
1410 SDValue BasePtr = Load->getBasePtr();
1411 EVT MemVT = Load->getMemoryVT();
1412
1413 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1414
1415 EVT LoVT, HiVT;
1416 EVT LoMemVT, HiMemVT;
1417 SDValue Lo, Hi;
1418
1419 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1420 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1421 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG);
1422
1423 unsigned Size = LoMemVT.getStoreSize();
1424 unsigned BaseAlign = Load->getAlignment();
1425 unsigned HiAlign = MinAlign(BaseAlign, Size);
1426
1427 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1428 Load->getChain(), BasePtr, SrcValue, LoMemVT,
1429 BaseAlign, Load->getMemOperand()->getFlags());
1430 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1431 SDValue HiLoad =
1432 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1433 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1434 HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1435
1436 auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1437 SDValue Join;
1438 if (LoVT == HiVT) {
1439 // This is the case that the vector is power of two so was evenly split.
1440 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
1441 } else {
1442 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1443 DAG.getConstant(0, SL, IdxTy));
1444 Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR
1445 : ISD::INSERT_VECTOR_ELT,
1446 SL, VT, Join, HiLoad,
1447 DAG.getConstant(LoVT.getVectorNumElements(), SL, IdxTy));
1448 }
1449
1450 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1451 LoLoad.getValue(1), HiLoad.getValue(1))};
1452
1453 return DAG.getMergeValues(Ops, SL);
1454}
1455
1456// Widen a vector load from vec3 to vec4.
1457SDValue AMDGPUTargetLowering::WidenVectorLoad(SDValue Op,
1458 SelectionDAG &DAG) const {
1459 LoadSDNode *Load = cast<LoadSDNode>(Op);
1460 EVT VT = Op.getValueType();
1461 assert(VT.getVectorNumElements() == 3)((VT.getVectorNumElements() == 3) ? static_cast<void> (
0) : __assert_fail ("VT.getVectorNumElements() == 3", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1461, __PRETTY_FUNCTION__))
;
1462 SDValue BasePtr = Load->getBasePtr();
1463 EVT MemVT = Load->getMemoryVT();
1464 SDLoc SL(Op);
1465 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1466 unsigned BaseAlign = Load->getAlignment();
1467
1468 EVT WideVT =
1469 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
1470 EVT WideMemVT =
1471 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), 4);
1472 SDValue WideLoad = DAG.getExtLoad(
1473 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
1474 WideMemVT, BaseAlign, Load->getMemOperand()->getFlags());
1475 return DAG.getMergeValues(
1476 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1477 DAG.getConstant(0, SL, getVectorIdxTy(DAG.getDataLayout()))),
1478 WideLoad.getValue(1)},
1479 SL);
1480}
1481
1482SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1483 SelectionDAG &DAG) const {
1484 StoreSDNode *Store = cast<StoreSDNode>(Op);
1485 SDValue Val = Store->getValue();
1486 EVT VT = Val.getValueType();
1487
1488 // If this is a 2 element vector, we really want to scalarize and not create
1489 // weird 1 element vectors.
1490 if (VT.getVectorNumElements() == 2)
1491 return scalarizeVectorStore(Store, DAG);
1492
1493 EVT MemVT = Store->getMemoryVT();
1494 SDValue Chain = Store->getChain();
1495 SDValue BasePtr = Store->getBasePtr();
1496 SDLoc SL(Op);
1497
1498 EVT LoVT, HiVT;
1499 EVT LoMemVT, HiMemVT;
1500 SDValue Lo, Hi;
1501
1502 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1503 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1504 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG);
1505
1506 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1507
1508 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1509 unsigned BaseAlign = Store->getAlignment();
1510 unsigned Size = LoMemVT.getStoreSize();
1511 unsigned HiAlign = MinAlign(BaseAlign, Size);
1512
1513 SDValue LoStore =
1514 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1515 Store->getMemOperand()->getFlags());
1516 SDValue HiStore =
1517 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1518 HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1519
1520 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1521}
1522
1523// This is a shortcut for integer division because we have fast i32<->f32
1524// conversions, and fast f32 reciprocal instructions. The fractional part of a
1525// float is enough to accurately represent up to a 24-bit signed integer.
1526SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1527 bool Sign) const {
1528 SDLoc DL(Op);
1529 EVT VT = Op.getValueType();
1530 SDValue LHS = Op.getOperand(0);
1531 SDValue RHS = Op.getOperand(1);
1532 MVT IntVT = MVT::i32;
1533 MVT FltVT = MVT::f32;
1534
1535 unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1536 if (LHSSignBits < 9)
1537 return SDValue();
1538
1539 unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1540 if (RHSSignBits < 9)
1541 return SDValue();
1542
1543 unsigned BitSize = VT.getSizeInBits();
1544 unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1545 unsigned DivBits = BitSize - SignBits;
1546 if (Sign)
1547 ++DivBits;
1548
1549 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1550 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1551
1552 SDValue jq = DAG.getConstant(1, DL, IntVT);
1553
1554 if (Sign) {
1555 // char|short jq = ia ^ ib;
1556 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1557
1558 // jq = jq >> (bitsize - 2)
1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1560 DAG.getConstant(BitSize - 2, DL, VT));
1561
1562 // jq = jq | 0x1
1563 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1564 }
1565
1566 // int ia = (int)LHS;
1567 SDValue ia = LHS;
1568
1569 // int ib, (int)RHS;
1570 SDValue ib = RHS;
1571
1572 // float fa = (float)ia;
1573 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1574
1575 // float fb = (float)ib;
1576 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1577
1578 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1579 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1580
1581 // fq = trunc(fq);
1582 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1583
1584 // float fqneg = -fq;
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1586
1587 MachineFunction &MF = DAG.getMachineFunction();
1588 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
1589
1590 // float fr = mad(fqneg, fb, fa);
1591 unsigned OpCode = MFI->getMode().FP32Denormals ?
1592 (unsigned)AMDGPUISD::FMAD_FTZ :
1593 (unsigned)ISD::FMAD;
1594 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1595
1596 // int iq = (int)fq;
1597 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1598
1599 // fr = fabs(fr);
1600 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1601
1602 // fb = fabs(fb);
1603 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1604
1605 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1606
1607 // int cv = fr >= fb;
1608 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1609
1610 // jq = (cv ? jq : 0);
1611 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1612
1613 // dst = iq + jq;
1614 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1615
1616 // Rem needs compensation, it's easier to recompute it
1617 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1618 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1619
1620 // Truncate to number of bits this divide really is.
1621 if (Sign) {
1622 SDValue InRegSize
1623 = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1624 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1625 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1626 } else {
1627 SDValue TruncMask = DAG.getConstant((UINT64_C(1)1UL << DivBits) - 1, DL, VT);
1628 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1629 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1630 }
1631
1632 return DAG.getMergeValues({ Div, Rem }, DL);
1633}
1634
1635void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1636 SelectionDAG &DAG,
1637 SmallVectorImpl<SDValue> &Results) const {
1638 SDLoc DL(Op);
1639 EVT VT = Op.getValueType();
1640
1641 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64")((VT == MVT::i64 && "LowerUDIVREM64 expects an i64") ?
static_cast<void> (0) : __assert_fail ("VT == MVT::i64 && \"LowerUDIVREM64 expects an i64\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1641, __PRETTY_FUNCTION__))
;
1642
1643 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1644
1645 SDValue One = DAG.getConstant(1, DL, HalfVT);
1646 SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1647
1648 //HiLo split
1649 SDValue LHS = Op.getOperand(0);
1650 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1651 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1652
1653 SDValue RHS = Op.getOperand(1);
1654 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1655 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1656
1657 if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1658 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1659
1660 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1661 LHS_Lo, RHS_Lo);
1662
1663 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1664 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1665
1666 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1667 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1668 return;
1669 }
1670
1671 if (isTypeLegal(MVT::i64)) {
1672 MachineFunction &MF = DAG.getMachineFunction();
1673 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1674
1675 // Compute denominator reciprocal.
1676 unsigned FMAD = MFI->getMode().FP32Denormals ?
1677 (unsigned)AMDGPUISD::FMAD_FTZ :
1678 (unsigned)ISD::FMAD;
1679
1680 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1681 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1682 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1683 DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1684 Cvt_Lo);
1685 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1686 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1687 DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1688 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1689 DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1690 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1691 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1692 DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1693 Mul1);
1694 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1695 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1696 SDValue Rcp64 = DAG.getBitcast(VT,
1697 DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1698
1699 SDValue Zero64 = DAG.getConstant(0, DL, VT);
1700 SDValue One64 = DAG.getConstant(1, DL, VT);
1701 SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1702 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1703
1704 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1705 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1706 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1707 SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1708 Zero);
1709 SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1710 One);
1711
1712 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1713 Mulhi1_Lo, Zero1);
1714 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1715 Mulhi1_Hi, Add1_Lo.getValue(1));
1716 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1717 SDValue Add1 = DAG.getBitcast(VT,
1718 DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1719
1720 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1721 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1722 SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1723 Zero);
1724 SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1725 One);
1726
1727 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1728 Mulhi2_Lo, Zero1);
1729 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1730 Mulhi2_Hi, Add1_Lo.getValue(1));
1731 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1732 Zero, Add2_Lo.getValue(1));
1733 SDValue Add2 = DAG.getBitcast(VT,
1734 DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1735 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1736
1737 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1738
1739 SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1740 SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1741 SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1742 Mul3_Lo, Zero1);
1743 SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1744 Mul3_Hi, Sub1_Lo.getValue(1));
1745 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1746 SDValue Sub1 = DAG.getBitcast(VT,
1747 DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1748
1749 SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1750 SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1751 ISD::SETUGE);
1752 SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1753 ISD::SETUGE);
1754 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1755
1756 // TODO: Here and below portions of the code can be enclosed into if/endif.
1757 // Currently control flow is unconditional and we have 4 selects after
1758 // potential endif to substitute PHIs.
1759
1760 // if C3 != 0 ...
1761 SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1762 RHS_Lo, Zero1);
1763 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1764 RHS_Hi, Sub1_Lo.getValue(1));
1765 SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1766 Zero, Sub2_Lo.getValue(1));
1767 SDValue Sub2 = DAG.getBitcast(VT,
1768 DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1769
1770 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1771
1772 SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1773 ISD::SETUGE);
1774 SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1775 ISD::SETUGE);
1776 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1777
1778 // if (C6 != 0)
1779 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1780
1781 SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1782 RHS_Lo, Zero1);
1783 SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1784 RHS_Hi, Sub2_Lo.getValue(1));
1785 SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1786 Zero, Sub3_Lo.getValue(1));
1787 SDValue Sub3 = DAG.getBitcast(VT,
1788 DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1789
1790 // endif C6
1791 // endif C3
1792
1793 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1794 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1795
1796 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1797 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1798
1799 Results.push_back(Div);
1800 Results.push_back(Rem);
1801
1802 return;
1803 }
1804
1805 // r600 expandion.
1806 // Get Speculative values
1807 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1808 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1809
1810 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1811 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1812 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1813
1814 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1815 SDValue DIV_Lo = Zero;
1816
1817 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1818
1819 for (unsigned i = 0; i < halfBitWidth; ++i) {
1820 const unsigned bitPos = halfBitWidth - i - 1;
1821 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1822 // Get value of high bit
1823 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1824 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1825 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1826
1827 // Shift
1828 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1829 // Add LHS high bit
1830 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1831
1832 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1833 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1834
1835 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1836
1837 // Update REM
1838 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1839 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1840 }
1841
1842 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1843 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1844 Results.push_back(DIV);
1845 Results.push_back(REM);
1846}
1847
1848SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1849 SelectionDAG &DAG) const {
1850 SDLoc DL(Op);
1851 EVT VT = Op.getValueType();
1852
1853 if (VT == MVT::i64) {
1854 SmallVector<SDValue, 2> Results;
1855 LowerUDIVREM64(Op, DAG, Results);
1856 return DAG.getMergeValues(Results, DL);
1857 }
1858
1859 if (VT == MVT::i32) {
1860 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1861 return Res;
1862 }
1863
1864 SDValue Num = Op.getOperand(0);
1865 SDValue Den = Op.getOperand(1);
1866
1867 // RCP = URECIP(Den) = 2^32 / Den + e
1868 // e is rounding error.
1869 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1870
1871 // RCP_LO = mul(RCP, Den) */
1872 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1873
1874 // RCP_HI = mulhu (RCP, Den) */
1875 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1876
1877 // NEG_RCP_LO = -RCP_LO
1878 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1879 RCP_LO);
1880
1881 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1882 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1883 NEG_RCP_LO, RCP_LO,
1884 ISD::SETEQ);
1885 // Calculate the rounding error from the URECIP instruction
1886 // E = mulhu(ABS_RCP_LO, RCP)
1887 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1888
1889 // RCP_A_E = RCP + E
1890 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1891
1892 // RCP_S_E = RCP - E
1893 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1894
1895 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1896 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1897 RCP_A_E, RCP_S_E,
1898 ISD::SETEQ);
1899 // Quotient = mulhu(Tmp0, Num)
1900 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1901
1902 // Num_S_Remainder = Quotient * Den
1903 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1904
1905 // Remainder = Num - Num_S_Remainder
1906 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1907
1908 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1909 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1910 DAG.getConstant(-1, DL, VT),
1911 DAG.getConstant(0, DL, VT),
1912 ISD::SETUGE);
1913 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1914 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1915 Num_S_Remainder,
1916 DAG.getConstant(-1, DL, VT),
1917 DAG.getConstant(0, DL, VT),
1918 ISD::SETUGE);
1919 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1920 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1921 Remainder_GE_Zero);
1922
1923 // Calculate Division result:
1924
1925 // Quotient_A_One = Quotient + 1
1926 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1927 DAG.getConstant(1, DL, VT));
1928
1929 // Quotient_S_One = Quotient - 1
1930 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1931 DAG.getConstant(1, DL, VT));
1932
1933 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1934 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1935 Quotient, Quotient_A_One, ISD::SETEQ);
1936
1937 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1938 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1939 Quotient_S_One, Div, ISD::SETEQ);
1940
1941 // Calculate Rem result:
1942
1943 // Remainder_S_Den = Remainder - Den
1944 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1945
1946 // Remainder_A_Den = Remainder + Den
1947 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1948
1949 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1950 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1951 Remainder, Remainder_S_Den, ISD::SETEQ);
1952
1953 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1954 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1955 Remainder_A_Den, Rem, ISD::SETEQ);
1956 SDValue Ops[2] = {
1957 Div,
1958 Rem
1959 };
1960 return DAG.getMergeValues(Ops, DL);
1961}
1962
1963SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1964 SelectionDAG &DAG) const {
1965 SDLoc DL(Op);
1966 EVT VT = Op.getValueType();
1967
1968 SDValue LHS = Op.getOperand(0);
1969 SDValue RHS = Op.getOperand(1);
1970
1971 SDValue Zero = DAG.getConstant(0, DL, VT);
1972 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1973
1974 if (VT == MVT::i32) {
1975 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1976 return Res;
1977 }
1978
1979 if (VT == MVT::i64 &&
1980 DAG.ComputeNumSignBits(LHS) > 32 &&
1981 DAG.ComputeNumSignBits(RHS) > 32) {
1982 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1983
1984 //HiLo split
1985 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1986 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1987 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1988 LHS_Lo, RHS_Lo);
1989 SDValue Res[2] = {
1990 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1991 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1992 };
1993 return DAG.getMergeValues(Res, DL);
1994 }
1995
1996 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1997 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1998 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1999 SDValue RSign = LHSign; // Remainder sign is the same as LHS
2000
2001 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
2002 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
2003
2004 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
2005 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
2006
2007 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2008 SDValue Rem = Div.getValue(1);
2009
2010 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
2011 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
2012
2013 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
2014 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2015
2016 SDValue Res[2] = {
2017 Div,
2018 Rem
2019 };
2020 return DAG.getMergeValues(Res, DL);
2021}
2022
2023// (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
2024SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2025 SDLoc SL(Op);
2026 EVT VT = Op.getValueType();
2027 SDValue X = Op.getOperand(0);
2028 SDValue Y = Op.getOperand(1);
2029
2030 // TODO: Should this propagate fast-math-flags?
2031
2032 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
2033 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
2034 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
2035
2036 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
2037}
2038
2039SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2040 SDLoc SL(Op);
2041 SDValue Src = Op.getOperand(0);
2042
2043 // result = trunc(src)
2044 // if (src > 0.0 && src != result)
2045 // result += 1.0
2046
2047 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2048
2049 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2050 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2051
2052 EVT SetCCVT =
2053 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2054
2055 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2056 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2057 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2058
2059 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2060 // TODO: Should this propagate fast-math-flags?
2061 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2062}
2063
2064static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
2065 SelectionDAG &DAG) {
2066 const unsigned FractBits = 52;
2067 const unsigned ExpBits = 11;
2068
2069 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2070 Hi,
2071 DAG.getConstant(FractBits - 32, SL, MVT::i32),
2072 DAG.getConstant(ExpBits, SL, MVT::i32));
2073 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2074 DAG.getConstant(1023, SL, MVT::i32));
2075
2076 return Exp;
2077}
2078
2079SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2080 SDLoc SL(Op);
2081 SDValue Src = Op.getOperand(0);
2082
2083 assert(Op.getValueType() == MVT::f64)((Op.getValueType() == MVT::f64) ? static_cast<void> (0
) : __assert_fail ("Op.getValueType() == MVT::f64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2083, __PRETTY_FUNCTION__))
;
2084
2085 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2086 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2087
2088 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2089
2090 // Extract the upper half, since this is where we will find the sign and
2091 // exponent.
2092 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2093
2094 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2095
2096 const unsigned FractBits = 52;
2097
2098 // Extract the sign bit.
2099 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1)1U << 31, SL, MVT::i32);
2100 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2101
2102 // Extend back to 64-bits.
2103 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2104 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2105
2106 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2107 const SDValue FractMask
2108 = DAG.getConstant((UINT64_C(1)1UL << FractBits) - 1, SL, MVT::i64);
2109
2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2111 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2112 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2113
2114 EVT SetCCVT =
2115 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2116
2117 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2118
2119 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2120 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2121
2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2123 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2124
2125 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2126}
2127
2128SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2129 SDLoc SL(Op);
2130 SDValue Src = Op.getOperand(0);
2131
2132 assert(Op.getValueType() == MVT::f64)((Op.getValueType() == MVT::f64) ? static_cast<void> (0
) : __assert_fail ("Op.getValueType() == MVT::f64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2132, __PRETTY_FUNCTION__))
;
2133
2134 APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2135 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2136 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2137
2138 // TODO: Should this propagate fast-math-flags?
2139
2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2141 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2142
2143 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2144
2145 APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2146 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2147
2148 EVT SetCCVT =
2149 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2150 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2151
2152 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2153}
2154
2155SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2156 // FNEARBYINT and FRINT are the same, except in their handling of FP
2157 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2158 // rint, so just treat them as equivalent.
2159 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2160}
2161
2162// XXX - May require not supporting f32 denormals?
2163
2164// Don't handle v2f16. The extra instructions to scalarize and repack around the
2165// compare and vselect end up producing worse code than scalarizing the whole
2166// operation.
2167SDValue AMDGPUTargetLowering::LowerFROUND_LegalFTRUNC(SDValue Op,
2168 SelectionDAG &DAG) const {
2169 SDLoc SL(Op);
2170 SDValue X = Op.getOperand(0);
2171 EVT VT = Op.getValueType();
2172
2173 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2174
2175 // TODO: Should this propagate fast-math-flags?
2176
2177 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2178
2179 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2180
2181 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2182 const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2183 const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2184
2185 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2186
2187 EVT SetCCVT =
2188 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2189
2190 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2191
2192 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2193
2194 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2195}
2196
2197SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2198 SDLoc SL(Op);
2199 SDValue X = Op.getOperand(0);
2200
2201 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2202
2203 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2204 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2205 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2206 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2207 EVT SetCCVT =
2208 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2209
2210 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2211
2212 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2213
2214 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2215
2216 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff)0x000fffffffffffffL, SL,
2217 MVT::i64);
2218
2219 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2220 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2221 DAG.getConstant(INT64_C(0x0008000000000000)0x0008000000000000L, SL,
2222 MVT::i64),
2223 Exp);
2224
2225 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2226 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2227 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2228 ISD::SETNE);
2229
2230 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2231 D, DAG.getConstant(0, SL, MVT::i64));
2232 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2233
2234 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2235 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2236
2237 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2238 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2239 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2240
2241 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2242 ExpEqNegOne,
2243 DAG.getConstantFP(1.0, SL, MVT::f64),
2244 DAG.getConstantFP(0.0, SL, MVT::f64));
2245
2246 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2247
2248 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2249 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2250
2251 return K;
2252}
2253
2254SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2255 EVT VT = Op.getValueType();
2256
2257 if (isOperationLegal(ISD::FTRUNC, VT))
2258 return LowerFROUND_LegalFTRUNC(Op, DAG);
2259
2260 if (VT == MVT::f64)
2261 return LowerFROUND64(Op, DAG);
2262
2263 llvm_unreachable("unhandled type")::llvm::llvm_unreachable_internal("unhandled type", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2263)
;
2264}
2265
2266SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2267 SDLoc SL(Op);
2268 SDValue Src = Op.getOperand(0);
2269
2270 // result = trunc(src);
2271 // if (src < 0.0 && src != result)
2272 // result += -1.0.
2273
2274 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2275
2276 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2277 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2278
2279 EVT SetCCVT =
2280 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2281
2282 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2283 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2284 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2285
2286 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2287 // TODO: Should this propagate fast-math-flags?
2288 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2289}
2290
2291SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2292 double Log2BaseInverted) const {
2293 EVT VT = Op.getValueType();
2294
2295 SDLoc SL(Op);
2296 SDValue Operand = Op.getOperand(0);
2297 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2298 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2299
2300 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2301}
2302
2303// exp2(M_LOG2E_F * f);
2304SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
2305 EVT VT = Op.getValueType();
2306 SDLoc SL(Op);
2307 SDValue Src = Op.getOperand(0);
2308
2309 const SDValue K = DAG.getConstantFP(numbers::log2e, SL, VT);
2310 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2311 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2312}
2313
2314static bool isCtlzOpc(unsigned Opc) {
2315 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2316}
2317
2318static bool isCttzOpc(unsigned Opc) {
2319 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2320}
2321
2322SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2323 SDLoc SL(Op);
2324 SDValue Src = Op.getOperand(0);
2325 bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2326 Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
2327
2328 unsigned ISDOpc, NewOpc;
2329 if (isCtlzOpc(Op.getOpcode())) {
2330 ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2331 NewOpc = AMDGPUISD::FFBH_U32;
2332 } else if (isCttzOpc(Op.getOpcode())) {
2333 ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2334 NewOpc = AMDGPUISD::FFBL_B32;
2335 } else
2336 llvm_unreachable("Unexpected OPCode!!!")::llvm::llvm_unreachable_internal("Unexpected OPCode!!!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2336)
;
2337
2338
2339 if (ZeroUndef && Src.getValueType() == MVT::i32)
2340 return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2341
2342 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2343
2344 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2345 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2346
2347 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2348 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2349
2350 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2351 *DAG.getContext(), MVT::i32);
2352
2353 SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2354 SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2355
2356 SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2357 SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2358
2359 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2360 SDValue Add, NewOpr;
2361 if (isCtlzOpc(Op.getOpcode())) {
2362 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2363 // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2364 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2365 } else {
2366 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2367 // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2368 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2369 }
2370
2371 if (!ZeroUndef) {
2372 // Test if the full 64-bit input is zero.
2373
2374 // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2375 // which we probably don't want.
2376 SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2377 SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2378 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2379
2380 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2381 // with the same cycles, otherwise it is slower.
2382 // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2383 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2384
2385 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2386
2387 // The instruction returns -1 for 0 input, but the defined intrinsic
2388 // behavior is to return the number of bits.
2389 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2390 SrcIsZero, Bits32, NewOpr);
2391 }
2392
2393 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2394}
2395
2396SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2397 bool Signed) const {
2398 // Unsigned
2399 // cul2f(ulong u)
2400 //{
2401 // uint lz = clz(u);
2402 // uint e = (u != 0) ? 127U + 63U - lz : 0;
2403 // u = (u << lz) & 0x7fffffffffffffffUL;
2404 // ulong t = u & 0xffffffffffUL;
2405 // uint v = (e << 23) | (uint)(u >> 40);
2406 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2407 // return as_float(v + r);
2408 //}
2409 // Signed
2410 // cl2f(long l)
2411 //{
2412 // long s = l >> 63;
2413 // float r = cul2f((l + s) ^ s);
2414 // return s ? -r : r;
2415 //}
2416
2417 SDLoc SL(Op);
2418 SDValue Src = Op.getOperand(0);
2419 SDValue L = Src;
2420
2421 SDValue S;
2422 if (Signed) {
2423 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2425
2426 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2427 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2428 }
2429
2430 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2431 *DAG.getContext(), MVT::f32);
2432
2433
2434 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2435 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2436 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2437 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2438
2439 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2440 SDValue E = DAG.getSelect(SL, MVT::i32,
2441 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2442 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2443 ZeroI32);
2444
2445 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2446 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2447 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2448
2449 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2450 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2451
2452 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2453 U, DAG.getConstant(40, SL, MVT::i64));
2454
2455 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2456 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2457 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2458
2459 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2460 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2461 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2462
2463 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2464
2465 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2466
2467 SDValue R = DAG.getSelect(SL, MVT::i32,
2468 RCmp,
2469 One,
2470 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2471 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2472 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2473
2474 if (!Signed)
2475 return R;
2476
2477 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2478 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2479}
2480
2481SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2482 bool Signed) const {
2483 SDLoc SL(Op);
2484 SDValue Src = Op.getOperand(0);
2485
2486 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2487
2488 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2489 DAG.getConstant(0, SL, MVT::i32));
2490 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2491 DAG.getConstant(1, SL, MVT::i32));
2492
2493 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2494 SL, MVT::f64, Hi);
2495
2496 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2497
2498 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2499 DAG.getConstant(32, SL, MVT::i32));
2500 // TODO: Should this propagate fast-math-flags?
2501 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2502}
2503
2504SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2505 SelectionDAG &DAG) const {
2506 // TODO: Factor out code common with LowerSINT_TO_FP.
2507 EVT DestVT = Op.getValueType();
2508 SDValue Src = Op.getOperand(0);
2509 EVT SrcVT = Src.getValueType();
2510
2511 if (SrcVT == MVT::i16) {
2512 if (DestVT == MVT::f16)
2513 return Op;
2514 SDLoc DL(Op);
2515
2516 // Promote src to i32
2517 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src);
2518 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
2519 }
2520
2521 assert(SrcVT == MVT::i64 && "operation should be legal")((SrcVT == MVT::i64 && "operation should be legal") ?
static_cast<void> (0) : __assert_fail ("SrcVT == MVT::i64 && \"operation should be legal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2521, __PRETTY_FUNCTION__))
;
2522
2523 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2524 SDLoc DL(Op);
2525
2526 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2527 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2528 SDValue FPRound =
2529 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2530
2531 return FPRound;
2532 }
2533
2534 if (DestVT == MVT::f32)
2535 return LowerINT_TO_FP32(Op, DAG, false);
2536
2537 assert(DestVT == MVT::f64)((DestVT == MVT::f64) ? static_cast<void> (0) : __assert_fail
("DestVT == MVT::f64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2537, __PRETTY_FUNCTION__))
;
2538 return LowerINT_TO_FP64(Op, DAG, false);
2539}
2540
2541SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2542 SelectionDAG &DAG) const {
2543 EVT DestVT = Op.getValueType();
2544
2545 SDValue Src = Op.getOperand(0);
2546 EVT SrcVT = Src.getValueType();
2547
2548 if (SrcVT == MVT::i16) {
2549 if (DestVT == MVT::f16)
2550 return Op;
2551
2552 SDLoc DL(Op);
2553 // Promote src to i32
2554 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src);
2555 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);
2556 }
2557
2558 assert(SrcVT == MVT::i64 && "operation should be legal")((SrcVT == MVT::i64 && "operation should be legal") ?
static_cast<void> (0) : __assert_fail ("SrcVT == MVT::i64 && \"operation should be legal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2558, __PRETTY_FUNCTION__))
;
2559
2560 // TODO: Factor out code common with LowerUINT_TO_FP.
2561
2562 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2563 SDLoc DL(Op);
2564 SDValue Src = Op.getOperand(0);
2565
2566 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2567 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2568 SDValue FPRound =
2569 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2570
2571 return FPRound;
2572 }
2573
2574 if (DestVT == MVT::f32)
2575 return LowerINT_TO_FP32(Op, DAG, true);
2576
2577 assert(DestVT == MVT::f64)((DestVT == MVT::f64) ? static_cast<void> (0) : __assert_fail
("DestVT == MVT::f64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2577, __PRETTY_FUNCTION__))
;
2578 return LowerINT_TO_FP64(Op, DAG, true);
2579}
2580
2581SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2582 bool Signed) const {
2583 SDLoc SL(Op);
2584
2585 SDValue Src = Op.getOperand(0);
2586
2587 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2588
2589 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)0x3df0000000000000UL), SL,
2590 MVT::f64);
2591 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)0xc1f0000000000000UL), SL,
2592 MVT::f64);
2593 // TODO: Should this propagate fast-math-flags?
2594 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2595
2596 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2597
2598
2599 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2600
2601 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2602 MVT::i32, FloorMul);
2603 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2604
2605 SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2606
2607 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2608}
2609
2610SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2611 SDLoc DL(Op);
2612 SDValue N0 = Op.getOperand(0);
2613
2614 // Convert to target node to get known bits
2615 if (N0.getValueType() == MVT::f32)
2616 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2617
2618 if (getTargetMachine().Options.UnsafeFPMath) {
2619 // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2620 return SDValue();
2621 }
2622
2623 assert(N0.getSimpleValueType() == MVT::f64)((N0.getSimpleValueType() == MVT::f64) ? static_cast<void>
(0) : __assert_fail ("N0.getSimpleValueType() == MVT::f64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2623, __PRETTY_FUNCTION__))
;
2624
2625 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2626 const unsigned ExpMask = 0x7ff;
2627 const unsigned ExpBiasf64 = 1023;
2628 const unsigned ExpBiasf16 = 15;
2629 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2630 SDValue One = DAG.getConstant(1, DL, MVT::i32);
2631 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2632 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2633 DAG.getConstant(32, DL, MVT::i64));
2634 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2635 U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2636 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2637 DAG.getConstant(20, DL, MVT::i64));
2638 E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2639 DAG.getConstant(ExpMask, DL, MVT::i32));
2640 // Subtract the fp64 exponent bias (1023) to get the real exponent and
2641 // add the f16 bias (15) to get the biased exponent for the f16 format.
2642 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2643 DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2644
2645 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2646 DAG.getConstant(8, DL, MVT::i32));
2647 M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2648 DAG.getConstant(0xffe, DL, MVT::i32));
2649
2650 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2651 DAG.getConstant(0x1ff, DL, MVT::i32));
2652 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2653
2654 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2655 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2656
2657 // (M != 0 ? 0x0200 : 0) | 0x7c00;
2658 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2659 DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2660 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2661
2662 // N = M | (E << 12);
2663 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2664 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2665 DAG.getConstant(12, DL, MVT::i32)));
2666
2667 // B = clamp(1-E, 0, 13);
2668 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2669 One, E);
2670 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2671 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2672 DAG.getConstant(13, DL, MVT::i32));
2673
2674 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2675 DAG.getConstant(0x1000, DL, MVT::i32));
2676
2677 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2678 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2679 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2680 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2681
2682 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2683 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2684 DAG.getConstant(0x7, DL, MVT::i32));
2685 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2686 DAG.getConstant(2, DL, MVT::i32));
2687 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2688 One, Zero, ISD::SETEQ);
2689 SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2690 One, Zero, ISD::SETGT);
2691 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2692 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2693
2694 V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2695 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2696 V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2697 I, V, ISD::SETEQ);
2698
2699 // Extract the sign bit.
2700 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2701 DAG.getConstant(16, DL, MVT::i32));
2702 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2703 DAG.getConstant(0x8000, DL, MVT::i32));
2704
2705 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2706 return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2707}
2708
2709SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2710 SelectionDAG &DAG) const {
2711 SDValue Src = Op.getOperand(0);
2712
2713 // TODO: Factor out code common with LowerFP_TO_UINT.
2714
2715 EVT SrcVT = Src.getValueType();
2716 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2717 SDLoc DL(Op);
2718
2719 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2720 SDValue FpToInt32 =
2721 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2722
2723 return FpToInt32;
2724 }
2725
2726 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2727 return LowerFP64_TO_INT(Op, DAG, true);
2728
2729 return SDValue();
2730}
2731
2732SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2733 SelectionDAG &DAG) const {
2734 SDValue Src = Op.getOperand(0);
2735
2736 // TODO: Factor out code common with LowerFP_TO_SINT.
2737
2738 EVT SrcVT = Src.getValueType();
2739 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2740 SDLoc DL(Op);
2741
2742 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2743 SDValue FpToInt32 =
2744 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2745
2746 return FpToInt32;
2747 }
2748
2749 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2750 return LowerFP64_TO_INT(Op, DAG, false);
2751
2752 return SDValue();
2753}
2754
2755SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2756 SelectionDAG &DAG) const {
2757 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2758 MVT VT = Op.getSimpleValueType();
2759 MVT ScalarVT = VT.getScalarType();
2760
2761 assert(VT.isVector())((VT.isVector()) ? static_cast<void> (0) : __assert_fail
("VT.isVector()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2761, __PRETTY_FUNCTION__))
;
2762
2763 SDValue Src = Op.getOperand(0);
2764 SDLoc DL(Op);
2765
2766 // TODO: Don't scalarize on Evergreen?
2767 unsigned NElts = VT.getVectorNumElements();
2768 SmallVector<SDValue, 8> Args;
2769 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2770
2771 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2772 for (unsigned I = 0; I < NElts; ++I)
2773 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2774
2775 return DAG.getBuildVector(VT, DL, Args);
2776}
2777
2778//===----------------------------------------------------------------------===//
2779// Custom DAG optimizations
2780//===----------------------------------------------------------------------===//
2781
2782static bool isU24(SDValue Op, SelectionDAG &DAG) {
2783 return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2784}
2785
2786static bool isI24(SDValue Op, SelectionDAG &DAG) {
2787 EVT VT = Op.getValueType();
2788 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2789 // as unsigned 24-bit values.
2790 AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2791}
2792
2793static SDValue simplifyI24(SDNode *Node24,
2794 TargetLowering::DAGCombinerInfo &DCI) {
2795 SelectionDAG &DAG = DCI.DAG;
2796 bool IsIntrin = Node24->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
2797
2798 SDValue LHS = IsIntrin ? Node24->getOperand(1) : Node24->getOperand(0);
2799 SDValue RHS = IsIntrin ? Node24->getOperand(2) : Node24->getOperand(1);
2800 unsigned NewOpcode = Node24->getOpcode();
2801 if (IsIntrin) {
2802 unsigned IID = cast<ConstantSDNode>(Node24->getOperand(0))->getZExtValue();
2803 NewOpcode = IID == Intrinsic::amdgcn_mul_i24 ?
2804 AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
2805 }
2806
2807 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2808
2809 // First try to simplify using GetDemandedBits which allows the operands to
2810 // have other uses, but will only perform simplifications that involve
2811 // bypassing some nodes for this user.
2812 SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
2813 SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
2814 if (DemandedLHS || DemandedRHS)
2815 return DAG.getNode(NewOpcode, SDLoc(Node24), Node24->getVTList(),
2816 DemandedLHS ? DemandedLHS : LHS,
2817 DemandedRHS ? DemandedRHS : RHS);
2818
2819 // Now try SimplifyDemandedBits which can simplify the nodes used by our
2820 // operands if this node is the only user.
2821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2822 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2823 return SDValue(Node24, 0);
2824 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2825 return SDValue(Node24, 0);
2826
2827 return SDValue();
2828}
2829
2830template <typename IntTy>
2831static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2832 uint32_t Width, const SDLoc &DL) {
2833 if (Width + Offset < 32) {
2834 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2835 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2836 return DAG.getConstant(Result, DL, MVT::i32);
2837 }
2838
2839 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2840}
2841
2842static bool hasVolatileUser(SDNode *Val) {
2843 for (SDNode *U : Val->uses()) {
2844 if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2845 if (M->isVolatile())
2846 return true;
2847 }
2848 }
2849
2850 return false;
2851}
2852
2853bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2854 // i32 vectors are the canonical memory type.
2855 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2856 return false;
2857
2858 if (!VT.isByteSized())
2859 return false;
2860
2861 unsigned Size = VT.getStoreSize();
2862
2863 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2864 return false;
2865
2866 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2867 return false;
2868
2869 return true;
2870}
2871
2872// Replace load of an illegal type with a store of a bitcast to a friendlier
2873// type.
2874SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2875 DAGCombinerInfo &DCI) const {
2876 if (!DCI.isBeforeLegalize())
2877 return SDValue();
2878
2879 LoadSDNode *LN = cast<LoadSDNode>(N);
2880 if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2881 return SDValue();
2882
2883 SDLoc SL(N);
2884 SelectionDAG &DAG = DCI.DAG;
2885 EVT VT = LN->getMemoryVT();
2886
2887 unsigned Size = VT.getStoreSize();
2888 unsigned Align = LN->getAlignment();
2889 if (Align < Size && isTypeLegal(VT)) {
2890 bool IsFast;
2891 unsigned AS = LN->getAddressSpace();
2892
2893 // Expand unaligned loads earlier than legalization. Due to visitation order
2894 // problems during legalization, the emitted instructions to pack and unpack
2895 // the bytes again are not eliminated in the case of an unaligned copy.
2896 if (!allowsMisalignedMemoryAccesses(
2897 VT, AS, Align, LN->getMemOperand()->getFlags(), &IsFast)) {
2898 SDValue Ops[2];
2899
2900 if (VT.isVector())
2901 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(LN, DAG);
2902 else
2903 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2904
2905 return DAG.getMergeValues(Ops, SDLoc(N));
2906 }
2907
2908 if (!IsFast)
2909 return SDValue();
2910 }
2911
2912 if (!shouldCombineMemoryType(VT))
2913 return SDValue();
2914
2915 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2916
2917 SDValue NewLoad
2918 = DAG.getLoad(NewVT, SL, LN->getChain(),
2919 LN->getBasePtr(), LN->getMemOperand());
2920
2921 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2922 DCI.CombineTo(N, BC, NewLoad.getValue(1));
2923 return SDValue(N, 0);
2924}
2925
2926// Replace store of an illegal type with a store of a bitcast to a friendlier
2927// type.
2928SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2929 DAGCombinerInfo &DCI) const {
2930 if (!DCI.isBeforeLegalize())
2931 return SDValue();
2932
2933 StoreSDNode *SN = cast<StoreSDNode>(N);
2934 if (SN->isVolatile() || !ISD::isNormalStore(SN))
2935 return SDValue();
2936
2937 EVT VT = SN->getMemoryVT();
2938 unsigned Size = VT.getStoreSize();
2939
2940 SDLoc SL(N);
2941 SelectionDAG &DAG = DCI.DAG;
2942 unsigned Align = SN->getAlignment();
2943 if (Align < Size && isTypeLegal(VT)) {
2944 bool IsFast;
2945 unsigned AS = SN->getAddressSpace();
2946
2947 // Expand unaligned stores earlier than legalization. Due to visitation
2948 // order problems during legalization, the emitted instructions to pack and
2949 // unpack the bytes again are not eliminated in the case of an unaligned
2950 // copy.
2951 if (!allowsMisalignedMemoryAccesses(
2952 VT, AS, Align, SN->getMemOperand()->getFlags(), &IsFast)) {
2953 if (VT.isVector())
2954 return scalarizeVectorStore(SN, DAG);
2955
2956 return expandUnalignedStore(SN, DAG);
2957 }
2958
2959 if (!IsFast)
2960 return SDValue();
2961 }
2962
2963 if (!shouldCombineMemoryType(VT))
2964 return SDValue();
2965
2966 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2967 SDValue Val = SN->getValue();
2968
2969 //DCI.AddToWorklist(Val.getNode());
2970
2971 bool OtherUses = !Val.hasOneUse();
2972 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2973 if (OtherUses) {
2974 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2975 DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2976 }
2977
2978 return DAG.getStore(SN->getChain(), SL, CastVal,
2979 SN->getBasePtr(), SN->getMemOperand());
2980}
2981
2982// FIXME: This should go in generic DAG combiner with an isTruncateFree check,
2983// but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
2984// issues.
2985SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
2986 DAGCombinerInfo &DCI) const {
2987 SelectionDAG &DAG = DCI.DAG;
2988 SDValue N0 = N->getOperand(0);
2989
2990 // (vt2 (assertzext (truncate vt0:x), vt1)) ->
2991 // (vt2 (truncate (assertzext vt0:x, vt1)))
2992 if (N0.getOpcode() == ISD::TRUNCATE) {
2993 SDValue N1 = N->getOperand(1);
2994 EVT ExtVT = cast<VTSDNode>(N1)->getVT();
2995 SDLoc SL(N);
2996
2997 SDValue Src = N0.getOperand(0);
2998 EVT SrcVT = Src.getValueType();
2999 if (SrcVT.bitsGE(ExtVT)) {
3000 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3001 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
3002 }
3003 }
3004
3005 return SDValue();
3006}
3007
3008SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
3009 SDNode *N, DAGCombinerInfo &DCI) const {
3010 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3011 switch (IID) {
3012 case Intrinsic::amdgcn_mul_i24:
3013 case Intrinsic::amdgcn_mul_u24:
3014 return simplifyI24(N, DCI);
3015 default:
3016 return SDValue();
3017 }
3018}
3019
3020/// Split the 64-bit value \p LHS into two 32-bit components, and perform the
3021/// binary operation \p Opc to it with the corresponding constant operands.
3022SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3023 DAGCombinerInfo &DCI, const SDLoc &SL,
3024 unsigned Opc, SDValue LHS,
3025 uint32_t ValLo, uint32_t ValHi) const {
3026 SelectionDAG &DAG = DCI.DAG;
3027 SDValue Lo, Hi;
3028 std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
3029
3030 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
3031 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
3032
3033 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
3034 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
3035
3036 // Re-visit the ands. It's possible we eliminated one of them and it could
3037 // simplify the vector.
3038 DCI.AddToWorklist(Lo.getNode());
3039 DCI.AddToWorklist(Hi.getNode());
3040
3041 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
3042 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3043}
3044
3045SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
3046 DAGCombinerInfo &DCI) const {
3047 EVT VT = N->getValueType(0);
3048
3049 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3050 if (!RHS)
3051 return SDValue();
3052
3053 SDValue LHS = N->getOperand(0);
3054 unsigned RHSVal = RHS->getZExtValue();
3055 if (!RHSVal)
3056 return LHS;
3057
3058 SDLoc SL(N);
3059 SelectionDAG &DAG = DCI.DAG;
3060
3061 switch (LHS->getOpcode()) {
3062 default:
3063 break;
3064 case ISD::ZERO_EXTEND:
3065 case ISD::SIGN_EXTEND:
3066 case ISD::ANY_EXTEND: {
3067 SDValue X = LHS->getOperand(0);
3068
3069 if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
3070 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
3071 // Prefer build_vector as the canonical form if packed types are legal.
3072 // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
3073 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
3074 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3075 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
3076 }
3077
3078 // shl (ext x) => zext (shl x), if shift does not overflow int
3079 if (VT != MVT::i64)
3080 break;
3081 KnownBits Known = DAG.computeKnownBits(X);
3082 unsigned LZ = Known.countMinLeadingZeros();
3083 if (LZ < RHSVal)
3084 break;
3085 EVT XVT = X.getValueType();
3086 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3087 return DAG.getZExtOrTrunc(Shl, SL, VT);
3088 }
3089 }
3090
3091 if (VT != MVT::i64)
3092 return SDValue();
3093
3094 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3095
3096 // On some subtargets, 64-bit shift is a quarter rate instruction. In the
3097 // common case, splitting this into a move and a 32-bit shift is faster and
3098 // the same code size.
3099 if (RHSVal < 32)
3100 return SDValue();
3101
3102 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3103
3104 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3105 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3106
3107 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3108
3109 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3110 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3111}
3112
3113SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
3114 DAGCombinerInfo &DCI) const {
3115 if (N->getValueType(0) != MVT::i64)
3116 return SDValue();
3117
3118 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3119 if (!RHS)
3120 return SDValue();
3121
3122 SelectionDAG &DAG = DCI.DAG;
3123 SDLoc SL(N);
3124 unsigned RHSVal = RHS->getZExtValue();
3125
3126 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3127 if (RHSVal == 32) {
3128 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3130 DAG.getConstant(31, SL, MVT::i32));
3131
3132 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3133 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3134 }
3135
3136 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3137 if (RHSVal == 63) {
3138 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3139 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3140 DAG.getConstant(31, SL, MVT::i32));
3141 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3142 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3143 }
3144
3145 return SDValue();
3146}
3147
3148SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3149 DAGCombinerInfo &DCI) const {
3150 auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3151 if (!RHS)
3152 return SDValue();
3153
3154 EVT VT = N->getValueType(0);
3155 SDValue LHS = N->getOperand(0);
3156 unsigned ShiftAmt = RHS->getZExtValue();
3157 SelectionDAG &DAG = DCI.DAG;
3158 SDLoc SL(N);
3159
3160 // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
3161 // this improves the ability to match BFE patterns in isel.
3162 if (LHS.getOpcode() == ISD::AND) {
3163 if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
3164 if (Mask->getAPIntValue().isShiftedMask() &&
3165 Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {
3166 return DAG.getNode(
3167 ISD::AND, SL, VT,
3168 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
3169 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
3170 }
3171 }
3172 }
3173
3174 if (VT != MVT::i64)
3175 return SDValue();
3176
3177 if (ShiftAmt < 32)
3178 return SDValue();
3179
3180 // srl i64:x, C for C >= 32
3181 // =>
3182 // build_pair (srl hi_32(x), C - 32), 0
3183 SDValue One = DAG.getConstant(1, SL, MVT::i32);
3184 SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3185
3186 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);
3187 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);
3188
3189 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3190 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3191
3192 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3193
3194 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3195}
3196
3197SDValue AMDGPUTargetLowering::performTruncateCombine(
3198 SDNode *N, DAGCombinerInfo &DCI) const {
3199 SDLoc SL(N);
3200 SelectionDAG &DAG = DCI.DAG;
3201 EVT VT = N->getValueType(0);
3202 SDValue Src = N->getOperand(0);
3203
3204 // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3205 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3206 SDValue Vec = Src.getOperand(0);
3207 if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3208 SDValue Elt0 = Vec.getOperand(0);
3209 EVT EltVT = Elt0.getValueType();
3210 if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3211 if (EltVT.isFloatingPoint()) {
3212 Elt0 = DAG.getNode(ISD::BITCAST, SL,
3213 EltVT.changeTypeToInteger(), Elt0);
3214 }
3215
3216 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3217 }
3218 }
3219 }
3220
3221 // Equivalent of above for accessing the high element of a vector as an
3222 // integer operation.
3223 // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3224 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3225 if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3226 if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3227 SDValue BV = stripBitcast(Src.getOperand(0));
3228 if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3229 BV.getValueType().getVectorNumElements() == 2) {
3230 SDValue SrcElt = BV.getOperand(1);
3231 EVT SrcEltVT = SrcElt.getValueType();
3232 if (SrcEltVT.isFloatingPoint()) {
3233 SrcElt = DAG.getNode(ISD::BITCAST, SL,
3234 SrcEltVT.changeTypeToInteger(), SrcElt);
3235 }
3236
3237 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3238 }
3239 }
3240 }
3241 }
3242
3243 // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3244 //
3245 // i16 (trunc (srl i64:x, K)), K <= 16 ->
3246 // i16 (trunc (srl (i32 (trunc x), K)))
3247 if (VT.getScalarSizeInBits() < 32) {
3248 EVT SrcVT = Src.getValueType();
3249 if (SrcVT.getScalarSizeInBits() > 32 &&
3250 (Src.getOpcode() == ISD::SRL ||
3251 Src.getOpcode() == ISD::SRA ||
3252 Src.getOpcode() == ISD::SHL)) {
3253 SDValue Amt = Src.getOperand(1);
3254 KnownBits Known = DAG.computeKnownBits(Amt);
3255 unsigned Size = VT.getScalarSizeInBits();
3256 if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3257 (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3258 EVT MidVT = VT.isVector() ?
3259 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
3260 VT.getVectorNumElements()) : MVT::i32;
3261
3262 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3263 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3264 Src.getOperand(0));
3265 DCI.AddToWorklist(Trunc.getNode());
3266
3267 if (Amt.getValueType() != NewShiftVT) {
3268 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3269 DCI.AddToWorklist(Amt.getNode());
3270 }
3271
3272 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3273 Trunc, Amt);
3274 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3275 }
3276 }
3277 }
3278
3279 return SDValue();
3280}
3281
3282// We need to specifically handle i64 mul here to avoid unnecessary conversion
3283// instructions. If we only match on the legalized i64 mul expansion,
3284// SimplifyDemandedBits will be unable to remove them because there will be
3285// multiple uses due to the separate mul + mulh[su].
3286static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3287 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3288 if (Size <= 32) {
3289 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3290 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3291 }
3292
3293 // Because we want to eliminate extension instructions before the
3294 // operation, we need to create a single user here (i.e. not the separate
3295 // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3296
3297 unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
3298
3299 SDValue Mul = DAG.getNode(MulOpc, SL,
3300 DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3301
3302 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3303 Mul.getValue(0), Mul.getValue(1));
3304}
3305
3306SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3307 DAGCombinerInfo &DCI) const {
3308 EVT VT = N->getValueType(0);
3309
3310 unsigned Size = VT.getSizeInBits();
3311 if (VT.isVector() || Size > 64)
3312 return SDValue();
3313
3314 // There are i16 integer mul/mad.
3315 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3316 return SDValue();
3317
3318 SelectionDAG &DAG = DCI.DAG;
3319 SDLoc DL(N);
3320
3321 SDValue N0 = N->getOperand(0);
3322 SDValue N1 = N->getOperand(1);
3323
3324 // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3325 // in the source into any_extends if the result of the mul is truncated. Since
3326 // we can assume the high bits are whatever we want, use the underlying value
3327 // to avoid the unknown high bits from interfering.
3328 if (N0.getOpcode() == ISD::ANY_EXTEND)
3329 N0 = N0.getOperand(0);
3330
3331 if (N1.getOpcode() == ISD::ANY_EXTEND)
3332 N1 = N1.getOperand(0);
3333
3334 SDValue Mul;
3335
3336 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3337 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3338 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3339 Mul = getMul24(DAG, DL, N0, N1, Size, false);
3340 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3341 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3342 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3343 Mul = getMul24(DAG, DL, N0, N1, Size, true);
3344 } else {
3345 return SDValue();
3346 }
3347
3348 // We need to use sext even for MUL_U24, because MUL_U24 is used
3349 // for signed multiply of 8 and 16-bit types.
3350 return DAG.getSExtOrTrunc(Mul, DL, VT);
3351}
3352
3353SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3354 DAGCombinerInfo &DCI) const {
3355 EVT VT = N->getValueType(0);
3356
3357 if (!Subtarget->hasMulI24() || VT.isVector())
3358 return SDValue();
3359
3360 SelectionDAG &DAG = DCI.DAG;
3361 SDLoc DL(N);
3362
3363 SDValue N0 = N->getOperand(0);
3364 SDValue N1 = N->getOperand(1);
3365
3366 if (!isI24(N0, DAG) || !isI24(N1, DAG))
3367 return SDValue();
3368
3369 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3370 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3371
3372 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3373 DCI.AddToWorklist(Mulhi.getNode());
3374 return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3375}
3376
3377SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3378 DAGCombinerInfo &DCI) const {
3379 EVT VT = N->getValueType(0);
3380
3381 if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3382 return SDValue();
3383
3384 SelectionDAG &DAG = DCI.DAG;
3385 SDLoc DL(N);
3386
3387 SDValue N0 = N->getOperand(0);
3388 SDValue N1 = N->getOperand(1);
3389
3390 if (!isU24(N0, DAG) || !isU24(N1, DAG))
3391 return SDValue();
3392
3393 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3394 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3395
3396 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3397 DCI.AddToWorklist(Mulhi.getNode());
3398 return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3399}
3400
3401SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
3402 SDNode *N, DAGCombinerInfo &DCI) const {
3403 SelectionDAG &DAG = DCI.DAG;
3404
3405 // Simplify demanded bits before splitting into multiple users.
3406 if (SDValue V = simplifyI24(N, DCI))
3407 return V;
3408
3409 SDValue N0 = N->getOperand(0);
3410 SDValue N1 = N->getOperand(1);
3411
3412 bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3413
3414 unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3415 unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3416
3417 SDLoc SL(N);
3418
3419 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3420 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3421 return DAG.getMergeValues({ MulLo, MulHi }, SL);
3422}
3423
3424static bool isNegativeOne(SDValue Val) {
3425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3426 return C->isAllOnesValue();
3427 return false;
3428}
3429
3430SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3431 SDValue Op,
3432 const SDLoc &DL,
3433 unsigned Opc) const {
3434 EVT VT = Op.getValueType();
3435 EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3436 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3437 LegalVT != MVT::i16))
3438 return SDValue();
3439
3440 if (VT != MVT::i32)
3441 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3442
3443 SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3444 if (VT != MVT::i32)
3445 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3446
3447 return FFBX;
3448}
3449
3450// The native instructions return -1 on 0 input. Optimize out a select that
3451// produces -1 on 0.
3452//
3453// TODO: If zero is not undef, we could also do this if the output is compared
3454// against the bitwidth.
3455//
3456// TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3457SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3458 SDValue LHS, SDValue RHS,
3459 DAGCombinerInfo &DCI) const {
3460 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3461 if (!CmpRhs || !CmpRhs->isNullValue())
3462 return SDValue();
3463
3464 SelectionDAG &DAG = DCI.DAG;
3465 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3466 SDValue CmpLHS = Cond.getOperand(0);
3467
3468 unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3469 AMDGPUISD::FFBH_U32;
3470
3471 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3472 // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3473 if (CCOpcode == ISD::SETEQ &&
3474 (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3475 RHS.getOperand(0) == CmpLHS &&
3476 isNegativeOne(LHS)) {
3477 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3478 }
3479
3480 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3481 // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3482 if (CCOpcode == ISD::SETNE &&
3483 (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3484 LHS.getOperand(0) == CmpLHS &&
3485 isNegativeOne(RHS)) {
3486 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3487 }
3488
3489 return SDValue();
3490}
3491
3492static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI,
3493 unsigned Op,
3494 const SDLoc &SL,
3495 SDValue Cond,
3496 SDValue N1,
3497 SDValue N2) {
3498 SelectionDAG &DAG = DCI.DAG;
3499 EVT VT = N1.getValueType();
3500
3501 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3502 N1.getOperand(0), N2.getOperand(0));
3503 DCI.AddToWorklist(NewSelect.getNode());
3504 return DAG.getNode(Op, SL, VT, NewSelect);
3505}
3506
3507// Pull a free FP operation out of a select so it may fold into uses.
3508//
3509// select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3510// select c, (fneg x), k -> fneg (select c, x, (fneg k))
3511//
3512// select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3513// select c, (fabs x), +k -> fabs (select c, x, k)
3514static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
3515 SDValue N) {
3516 SelectionDAG &DAG = DCI.DAG;
3517 SDValue Cond = N.getOperand(0);
3518 SDValue LHS = N.getOperand(1);
3519 SDValue RHS = N.getOperand(2);
3520
3521 EVT VT = N.getValueType();
3522 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3523 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3524 return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3525 SDLoc(N), Cond, LHS, RHS);
3526 }
3527
3528 bool Inv = false;
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3530 std::swap(LHS, RHS);
3531 Inv = true;
3532 }
3533
3534 // TODO: Support vector constants.
3535 ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3537 SDLoc SL(N);
3538 // If one side is an fneg/fabs and the other is a constant, we can push the
3539 // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3540 SDValue NewLHS = LHS.getOperand(0);
3541 SDValue NewRHS = RHS;
3542
3543 // Careful: if the neg can be folded up, don't try to pull it back down.
3544 bool ShouldFoldNeg = true;
3545
3546 if (NewLHS.hasOneUse()) {
3547 unsigned Opc = NewLHS.getOpcode();
3548 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3549 ShouldFoldNeg = false;
3550 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3551 ShouldFoldNeg = false;
3552 }
3553
3554 if (ShouldFoldNeg) {
3555 if (LHS.getOpcode() == ISD::FNEG)
3556 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3557 else if (CRHS->isNegative())
3558 return SDValue();
3559
3560 if (Inv)
3561 std::swap(NewLHS, NewRHS);
3562
3563 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3564 Cond, NewLHS, NewRHS);
3565 DCI.AddToWorklist(NewSelect.getNode());
3566 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3567 }
3568 }
3569
3570 return SDValue();
3571}
3572
3573
3574SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3575 DAGCombinerInfo &DCI) const {
3576 if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3577 return Folded;
3578
3579 SDValue Cond = N->getOperand(0);
3580 if (Cond.getOpcode() != ISD::SETCC)
3581 return SDValue();
3582
3583 EVT VT = N->getValueType(0);
3584 SDValue LHS = Cond.getOperand(0);
3585 SDValue RHS = Cond.getOperand(1);
3586 SDValue CC = Cond.getOperand(2);
3587
3588 SDValue True = N->getOperand(1);
3589 SDValue False = N->getOperand(2);
3590
3591 if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3592 SelectionDAG &DAG = DCI.DAG;
3593 if (DAG.isConstantValueOfAnyType(True) &&
3594 !DAG.isConstantValueOfAnyType(False)) {
3595 // Swap cmp + select pair to move constant to false input.
3596 // This will allow using VOPC cndmasks more often.
3597 // select (setcc x, y), k, x -> select (setccinv x, y), x, k
3598
3599 SDLoc SL(N);
3600 ISD::CondCode NewCC =
3601 getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), LHS.getValueType());
3602
3603 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3604 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3605 }
3606
3607 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3608 SDValue MinMax
3609 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3610 // Revisit this node so we can catch min3/max3/med3 patterns.
3611 //DCI.AddToWorklist(MinMax.getNode());
3612 return MinMax;
3613 }
3614 }
3615
3616 // There's no reason to not do this if the condition has other uses.
3617 return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3618}
3619
3620static bool isInv2Pi(const APFloat &APF) {
3621 static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3622 static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3623 static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3624
3625 return APF.bitwiseIsEqual(KF16) ||
3626 APF.bitwiseIsEqual(KF32) ||
3627 APF.bitwiseIsEqual(KF64);
3628}
3629
3630// 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3631// additional cost to negate them.
3632bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
3633 if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3634 if (C->isZero() && !C->isNegative())
3635 return true;
3636
3637 if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3638 return true;
3639 }
3640
3641 return false;
3642}
3643
3644static unsigned inverseMinMax(unsigned Opc) {
3645 switch (Opc) {
3646 case ISD::FMAXNUM:
3647 return ISD::FMINNUM;
3648 case ISD::FMINNUM:
3649 return ISD::FMAXNUM;
3650 case ISD::FMAXNUM_IEEE:
3651 return ISD::FMINNUM_IEEE;
3652 case ISD::FMINNUM_IEEE:
3653 return ISD::FMAXNUM_IEEE;
3654 case AMDGPUISD::FMAX_LEGACY:
3655 return AMDGPUISD::FMIN_LEGACY;
3656 case AMDGPUISD::FMIN_LEGACY:
3657 return AMDGPUISD::FMAX_LEGACY;
3658 default:
3659 llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 3659)
;
3660 }
3661}
3662
3663SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3664 DAGCombinerInfo &DCI) const {
3665 SelectionDAG &DAG = DCI.DAG;
3666 SDValue N0 = N->getOperand(0);
3667 EVT VT = N->getValueType(0);
3668
3669 unsigned Opc = N0.getOpcode();
3670
3671 // If the input has multiple uses and we can either fold the negate down, or
3672 // the other uses cannot, give up. This both prevents unprofitable
3673 // transformations and infinite loops: we won't repeatedly try to fold around
3674 // a negate that has no 'good' form.
3675 if (N0.hasOneUse()) {
3676 // This may be able to fold into the source, but at a code size cost. Don't
3677 // fold if the fold into the user is free.
3678 if (allUsesHaveSourceMods(N, 0))
3679 return SDValue();
3680 } else {
3681 if (fnegFoldsIntoOp(Opc) &&
3682 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))
3683 return SDValue();
3684 }
3685
3686 SDLoc SL(N);
3687 switch (Opc) {
3688 case ISD::FADD: {
3689 if (!mayIgnoreSignedZero(N0))
3690 return SDValue();
3691
3692 // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3693 SDValue LHS = N0.getOperand(0);
3694 SDValue RHS = N0.getOperand(1);
3695
3696 if (LHS.getOpcode() != ISD::FNEG)
3697 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3698 else
3699 LHS = LHS.getOperand(0);
3700
3701 if (RHS.getOpcode() != ISD::FNEG)
3702 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3703 else
3704 RHS = RHS.getOperand(0);
3705
3706 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3707 if (Res.getOpcode() != ISD::FADD)
3708 return SDValue(); // Op got folded away.
3709 if (!N0.hasOneUse())
3710 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3711 return Res;
3712 }
3713 case ISD::FMUL:
3714 case AMDGPUISD::FMUL_LEGACY: {
3715 // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3716 // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3717 SDValue LHS = N0.getOperand(0);
3718 SDValue RHS = N0.getOperand(1);
3719
3720 if (LHS.getOpcode() == ISD::FNEG)
3721 LHS = LHS.getOperand(0);
3722 else if (RHS.getOpcode() == ISD::FNEG)
3723 RHS = RHS.getOperand(0);
3724 else
3725 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3726
3727 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3728 if (Res.getOpcode() != Opc)
3729 return SDValue(); // Op got folded away.
3730 if (!N0.hasOneUse())
3731 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3732 return Res;
3733 }
3734 case ISD::FMA:
3735 case ISD::FMAD: {
3736 if (!mayIgnoreSignedZero(N0))
3737 return SDValue();
3738
3739 // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3740 SDValue LHS = N0.getOperand(0);
3741 SDValue MHS = N0.getOperand(1);
3742 SDValue RHS = N0.getOperand(2);
3743
3744 if (LHS.getOpcode() == ISD::FNEG)
3745 LHS = LHS.getOperand(0);
3746 else if (MHS.getOpcode() == ISD::FNEG)
3747 MHS = MHS.getOperand(0);
3748 else
3749 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3750
3751 if (RHS.getOpcode() != ISD::FNEG)
3752 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3753 else
3754 RHS = RHS.getOperand(0);
3755
3756 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3757 if (Res.getOpcode() != Opc)
3758 return SDValue(); // Op got folded away.
3759 if (!N0.hasOneUse())
3760 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3761 return Res;
3762 }
3763 case ISD::FMAXNUM:
3764 case ISD::FMINNUM:
3765 case ISD::FMAXNUM_IEEE:
3766 case ISD::FMINNUM_IEEE:
3767 case AMDGPUISD::FMAX_LEGACY:
3768 case AMDGPUISD::FMIN_LEGACY: {
3769 // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3770 // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3771 // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3772 // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3773
3774 SDValue LHS = N0.getOperand(0);
3775 SDValue RHS = N0.getOperand(1);
3776
3777 // 0 doesn't have a negated inline immediate.
3778 // TODO: This constant check should be generalized to other operations.
3779 if (isConstantCostlierToNegate(RHS))
3780 return SDValue();
3781
3782 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3783 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3784 unsigned Opposite = inverseMinMax(Opc);
3785
3786 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3787 if (Res.getOpcode() != Opposite)
3788 return SDValue(); // Op got folded away.
3789 if (!N0.hasOneUse())
3790 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3791 return Res;
3792 }
3793 case AMDGPUISD::FMED3: {
3794 SDValue Ops[3];
3795 for (unsigned I = 0; I < 3; ++I)
3796 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3797
3798 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3799 if (Res.getOpcode() != AMDGPUISD::FMED3)
3800 return SDValue(); // Op got folded away.
3801 if (!N0.hasOneUse())
3802 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3803 return Res;
3804 }
3805 case ISD::FP_EXTEND:
3806 case ISD::FTRUNC:
3807 case ISD::FRINT:
3808 case ISD::FNEARBYINT: // XXX - Should fround be handled?
3809 case ISD::FSIN:
3810 case ISD::FCANONICALIZE:
3811 case AMDGPUISD::RCP:
3812 case AMDGPUISD::RCP_LEGACY:
3813 case AMDGPUISD::RCP_IFLAG:
3814 case AMDGPUISD::SIN_HW: {
3815 SDValue CvtSrc = N0.getOperand(0);
3816 if (CvtSrc.getOpcode() == ISD::FNEG) {
3817 // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3818 // (fneg (rcp (fneg x))) -> (rcp x)
3819 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3820 }
3821
3822 if (!N0.hasOneUse())
3823 return SDValue();
3824
3825 // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3826 // (fneg (rcp x)) -> (rcp (fneg x))
3827 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3828 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3829 }
3830 case ISD::FP_ROUND: {
3831 SDValue CvtSrc = N0.getOperand(0);
3832
3833 if (CvtSrc.getOpcode() == ISD::FNEG) {
3834 // (fneg (fp_round (fneg x))) -> (fp_round x)
3835 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3836 CvtSrc.getOperand(0), N0.getOperand(1));
3837 }
3838
3839 if (!N0.hasOneUse())
3840 return SDValue();
3841
3842 // (fneg (fp_round x)) -> (fp_round (fneg x))
3843 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3844 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3845 }
3846 case ISD::FP16_TO_FP: {
3847 // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3848 // f16, but legalization of f16 fneg ends up pulling it out of the source.
3849 // Put the fneg back as a legal source operation that can be matched later.
3850 SDLoc SL(N);
3851
3852 SDValue Src = N0.getOperand(0);
3853 EVT SrcVT = Src.getValueType();
3854
3855 // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3856 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3857 DAG.getConstant(0x8000, SL, SrcVT));
3858 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3859 }
3860 default:
3861 return SDValue();
3862 }
3863}
3864
3865SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3866 DAGCombinerInfo &DCI) const {
3867 SelectionDAG &DAG = DCI.DAG;
3868 SDValue N0 = N->getOperand(0);
3869
3870 if (!N0.hasOneUse())
3871 return SDValue();
3872
3873 switch (N0.getOpcode()) {
3874 case ISD::FP16_TO_FP: {
3875 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal")((!Subtarget->has16BitInsts() && "should only see if f16 is illegal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->has16BitInsts() && \"should only see if f16 is illegal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 3875, __PRETTY_FUNCTION__))
;
3876 SDLoc SL(N);
3877 SDValue Src = N0.getOperand(0);
3878 EVT SrcVT = Src.getValueType();
3879
3880 // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3881 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3882 DAG.getConstant(0x7fff, SL, SrcVT));
3883 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3884 }
3885 default:
3886 return SDValue();
3887 }
3888}
3889
3890SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
3891 DAGCombinerInfo &DCI) const {
3892 const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3893 if (!CFP)
3894 return SDValue();
3895
3896 // XXX - Should this flush denormals?
3897 const APFloat &Val = CFP->getValueAPF();
3898 APFloat One(Val.getSemantics(), "1.0");
3899 return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3900}
3901
3902SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
3903 DAGCombinerInfo &DCI) const {
3904 SelectionDAG &DAG = DCI.DAG;
3905 SDLoc DL(N);
3906
3907 switch(N->getOpcode()) {
1
Control jumps to 'case BFE_I32:' at line 4014
3908 default:
3909 break;
3910 case ISD::BITCAST: {
3911 EVT DestVT = N->getValueType(0);
3912
3913 // Push casts through vector builds. This helps avoid emitting a large
3914 // number of copies when materializing floating point vector constants.
3915 //
3916 // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3917 // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3918 if (DestVT.isVector()) {
3919 SDValue Src = N->getOperand(0);
3920 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3921 EVT SrcVT = Src.getValueType();
3922 unsigned NElts = DestVT.getVectorNumElements();
3923
3924 if (SrcVT.getVectorNumElements() == NElts) {
3925 EVT DestEltVT = DestVT.getVectorElementType();
3926
3927 SmallVector<SDValue, 8> CastedElts;
3928 SDLoc SL(N);
3929 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3930 SDValue Elt = Src.getOperand(I);
3931 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3932 }
3933
3934 return DAG.getBuildVector(DestVT, SL, CastedElts);
3935 }
3936 }
3937 }
3938
3939 if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
3940 break;
3941
3942 // Fold bitcasts of constants.
3943 //
3944 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3945 // TODO: Generalize and move to DAGCombiner
3946 SDValue Src = N->getOperand(0);
3947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3948 if (Src.getValueType() == MVT::i64) {
3949 SDLoc SL(N);
3950 uint64_t CVal = C->getZExtValue();
3951 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3952 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3953 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3954 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
3955 }
3956 }
3957
3958 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3959 const APInt &Val = C->getValueAPF().bitcastToAPInt();
3960 SDLoc SL(N);
3961 uint64_t CVal = Val.getZExtValue();
3962 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3963 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3964 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3965
3966 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3967 }
3968
3969 break;
3970 }
3971 case ISD::SHL: {
3972 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3973 break;
3974
3975 return performShlCombine(N, DCI);
3976 }
3977 case ISD::SRL: {
3978 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3979 break;
3980
3981 return performSrlCombine(N, DCI);
3982 }
3983 case ISD::SRA: {
3984 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3985 break;
3986
3987 return performSraCombine(N, DCI);
3988 }
3989 case ISD::TRUNCATE:
3990 return performTruncateCombine(N, DCI);
3991 case ISD::MUL:
3992 return performMulCombine(N, DCI);
3993 case ISD::MULHS:
3994 return performMulhsCombine(N, DCI);
3995 case ISD::MULHU:
3996 return performMulhuCombine(N, DCI);
3997 case AMDGPUISD::MUL_I24:
3998 case AMDGPUISD::MUL_U24:
3999 case AMDGPUISD::MULHI_I24:
4000 case AMDGPUISD::MULHI_U24: {
4001 if (SDValue V = simplifyI24(N, DCI))
4002 return V;
4003 return SDValue();
4004 }
4005 case AMDGPUISD::MUL_LOHI_I24:
4006 case AMDGPUISD::MUL_LOHI_U24:
4007 return performMulLoHi24Combine(N, DCI);
4008 case ISD::SELECT:
4009 return performSelectCombine(N, DCI);
4010 case ISD::FNEG:
4011 return performFNegCombine(N, DCI);
4012 case ISD::FABS:
4013 return performFAbsCombine(N, DCI);
4014 case AMDGPUISD::BFE_I32:
4015 case AMDGPUISD::BFE_U32: {
4016 assert(!N->getValueType(0).isVector() &&((!N->getValueType(0).isVector() && "Vector handling of BFE not implemented"
) ? static_cast<void> (0) : __assert_fail ("!N->getValueType(0).isVector() && \"Vector handling of BFE not implemented\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4017, __PRETTY_FUNCTION__))
2
Assuming the condition is true
3
'?' condition is true
4017 "Vector handling of BFE not implemented")((!N->getValueType(0).isVector() && "Vector handling of BFE not implemented"
) ? static_cast<void> (0) : __assert_fail ("!N->getValueType(0).isVector() && \"Vector handling of BFE not implemented\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4017, __PRETTY_FUNCTION__))
;
4018 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
4019 if (!Width)
4
Assuming 'Width' is non-null
5
Taking false branch
4020 break;
4021
4022 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
4023 if (WidthVal == 0)
6
Assuming 'WidthVal' is not equal to 0
7
Taking false branch
4024 return DAG.getConstant(0, DL, MVT::i32);
4025
4026 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
4027 if (!Offset)
8
Assuming 'Offset' is non-null
9
Taking false branch
4028 break;
4029
4030 SDValue BitsFrom = N->getOperand(0);
10
Value assigned to 'BitsFrom.Node'
4031 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
4032
4033 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
4034
4035 if (OffsetVal == 0) {
11
Assuming 'OffsetVal' is not equal to 0
12
Taking false branch
4036 // This is already sign / zero extended, so try to fold away extra BFEs.
4037 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
4038
4039 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
4040 if (OpSignBits >= SignBits)
4041 return BitsFrom;
4042
4043 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
4044 if (Signed) {
4045 // This is a sign_extend_inreg. Replace it to take advantage of existing
4046 // DAG Combines. If not eliminated, we will match back to BFE during
4047 // selection.
4048
4049 // TODO: The sext_inreg of extended types ends, although we can could
4050 // handle them in a single BFE.
4051 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
4052 DAG.getValueType(SmallVT));
4053 }
4054
4055 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
4056 }
4057
4058 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
13
Calling 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
28
Returning from 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
29
Assuming 'CVal' is null
30
Taking false branch
4059 if (Signed) {
4060 return constantFoldBFE<int32_t>(DAG,
4061 CVal->getSExtValue(),
4062 OffsetVal,
4063 WidthVal,
4064 DL);
4065 }
4066
4067 return constantFoldBFE<uint32_t>(DAG,
4068 CVal->getZExtValue(),
4069 OffsetVal,
4070 WidthVal,
4071 DL);
4072 }
4073
4074 if ((OffsetVal + WidthVal) >= 32 &&
31
Assuming the condition is false
4075 !(Subtarget->hasSDWA() && OffsetVal == 16 && WidthVal == 16)) {
4076 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
4077 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
4078 BitsFrom, ShiftVal);
4079 }
4080
4081 if (BitsFrom.hasOneUse()) {
32
Calling 'SDValue::hasOneUse'
4082 APInt Demanded = APInt::getBitsSet(32,
4083 OffsetVal,
4084 OffsetVal + WidthVal);
4085
4086 KnownBits Known;
4087 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
4088 !DCI.isBeforeLegalizeOps());
4089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4090 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
4091 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
4092 DCI.CommitTargetLoweringOpt(TLO);
4093 }
4094 }
4095
4096 break;
4097 }
4098 case ISD::LOAD:
4099 return performLoadCombine(N, DCI);
4100 case ISD::STORE:
4101 return performStoreCombine(N, DCI);
4102 case AMDGPUISD::RCP:
4103 case AMDGPUISD::RCP_IFLAG:
4104 return performRcpCombine(N, DCI);
4105 case ISD::AssertZext:
4106 case ISD::AssertSext:
4107 return performAssertSZExtCombine(N, DCI);
4108 case ISD::INTRINSIC_WO_CHAIN:
4109 return performIntrinsicWOChainCombine(N, DCI);
4110 }
4111 return SDValue();
4112}
4113
4114//===----------------------------------------------------------------------===//
4115// Helper functions
4116//===----------------------------------------------------------------------===//
4117
4118SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4119 const TargetRegisterClass *RC,
4120 unsigned Reg, EVT VT,
4121 const SDLoc &SL,
4122 bool RawReg) const {
4123 MachineFunction &MF = DAG.getMachineFunction();
4124 MachineRegisterInfo &MRI = MF.getRegInfo();
4125 unsigned VReg;
4126
4127 if (!MRI.isLiveIn(Reg)) {
4128 VReg = MRI.createVirtualRegister(RC);
4129 MRI.addLiveIn(Reg, VReg);
4130 } else {
4131 VReg = MRI.getLiveInVirtReg(Reg);
4132 }
4133
4134 if (RawReg)
4135 return DAG.getRegister(VReg, VT);
4136
4137 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4138}
4139
4140// This may be called multiple times, and nothing prevents creating multiple
4141// objects at the same offset. See if we already defined this object.
4142static int getOrCreateFixedStackObject(MachineFrameInfo &MFI, unsigned Size,
4143 int64_t Offset) {
4144 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
4145 if (MFI.getObjectOffset(I) == Offset) {
4146 assert(MFI.getObjectSize(I) == Size)((MFI.getObjectSize(I) == Size) ? static_cast<void> (0)
: __assert_fail ("MFI.getObjectSize(I) == Size", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4146, __PRETTY_FUNCTION__))
;
4147 return I;
4148 }
4149 }
4150
4151 return MFI.CreateFixedObject(Size, Offset, true);
4152}
4153
4154SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
4155 EVT VT,
4156 const SDLoc &SL,
4157 int64_t Offset) const {
4158 MachineFunction &MF = DAG.getMachineFunction();
4159 MachineFrameInfo &MFI = MF.getFrameInfo();
4160 int FI = getOrCreateFixedStackObject(MFI, VT.getStoreSize(), Offset);
4161
4162 auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4163 SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4164
4165 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4,
4166 MachineMemOperand::MODereferenceable |
4167 MachineMemOperand::MOInvariant);
4168}
4169
4170SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
4171 const SDLoc &SL,
4172 SDValue Chain,
4173 SDValue ArgVal,
4174 int64_t Offset) const {
4175 MachineFunction &MF = DAG.getMachineFunction();
4176 MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4177
4178 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4179 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
4180 MachineMemOperand::MODereferenceable);
4181 return Store;
4182}
4183
4184SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
4185 const TargetRegisterClass *RC,
4186 EVT VT, const SDLoc &SL,
4187 const ArgDescriptor &Arg) const {
4188 assert(Arg && "Attempting to load missing argument")((Arg && "Attempting to load missing argument") ? static_cast
<void> (0) : __assert_fail ("Arg && \"Attempting to load missing argument\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4188, __PRETTY_FUNCTION__))
;
4189
4190 SDValue V = Arg.isRegister() ?
4191 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) :
4192 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset());
4193
4194 if (!Arg.isMasked())
4195 return V;
4196
4197 unsigned Mask = Arg.getMask();
4198 unsigned Shift = countTrailingZeros<unsigned>(Mask);
4199 V = DAG.getNode(ISD::SRL, SL, VT, V,
4200 DAG.getShiftAmountConstant(Shift, VT, SL));
4201 return DAG.getNode(ISD::AND, SL, VT, V,
4202 DAG.getConstant(Mask >> Shift, SL, VT));
4203}
4204
4205uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
4206 const MachineFunction &MF, const ImplicitParameter Param) const {
4207 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
4208 const AMDGPUSubtarget &ST =
4209 AMDGPUSubtarget::get(getTargetMachine(), MF.getFunction());
4210 unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4211 const Align Alignment = ST.getAlignmentForImplicitArgPtr();
4212 uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4213 ExplicitArgOffset;
4214 switch (Param) {
4215 case GRID_DIM:
4216 return ArgOffset;
4217 case GRID_OFFSET:
4218 return ArgOffset + 4;
4219 }
4220 llvm_unreachable("unexpected implicit parameter type")::llvm::llvm_unreachable_internal("unexpected implicit parameter type"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4220)
;
4221}
4222
4223#define NODE_NAME_CASE(node)case AMDGPUISD::node: return "node"; case AMDGPUISD::node: return #node;
4224
4225const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4226 switch ((AMDGPUISD::NodeType)Opcode) {
4227 case AMDGPUISD::FIRST_NUMBER: break;
4228 // AMDIL DAG nodes
4229 NODE_NAME_CASE(UMUL)case AMDGPUISD::UMUL: return "UMUL";;
4230 NODE_NAME_CASE(BRANCH_COND)case AMDGPUISD::BRANCH_COND: return "BRANCH_COND";;
4231
4232 // AMDGPU DAG nodes
4233 NODE_NAME_CASE(IF)case AMDGPUISD::IF: return "IF";
4234 NODE_NAME_CASE(ELSE)case AMDGPUISD::ELSE: return "ELSE";
4235 NODE_NAME_CASE(LOOP)case AMDGPUISD::LOOP: return "LOOP";
4236 NODE_NAME_CASE(CALL)case AMDGPUISD::CALL: return "CALL";
4237 NODE_NAME_CASE(TC_RETURN)case AMDGPUISD::TC_RETURN: return "TC_RETURN";
4238 NODE_NAME_CASE(TRAP)case AMDGPUISD::TRAP: return "TRAP";
4239 NODE_NAME_CASE(RET_FLAG)case AMDGPUISD::RET_FLAG: return "RET_FLAG";
4240 NODE_NAME_CASE(RETURN_TO_EPILOG)case AMDGPUISD::RETURN_TO_EPILOG: return "RETURN_TO_EPILOG";
4241 NODE_NAME_CASE(ENDPGM)case AMDGPUISD::ENDPGM: return "ENDPGM";
4242 NODE_NAME_CASE(DWORDADDR)case AMDGPUISD::DWORDADDR: return "DWORDADDR";
4243 NODE_NAME_CASE(FRACT)case AMDGPUISD::FRACT: return "FRACT";
4244 NODE_NAME_CASE(SETCC)case AMDGPUISD::SETCC: return "SETCC";
4245 NODE_NAME_CASE(SETREG)case AMDGPUISD::SETREG: return "SETREG";
4246 NODE_NAME_CASE(DENORM_MODE)case AMDGPUISD::DENORM_MODE: return "DENORM_MODE";
4247 NODE_NAME_CASE(FMA_W_CHAIN)case AMDGPUISD::FMA_W_CHAIN: return "FMA_W_CHAIN";
4248 NODE_NAME_CASE(FMUL_W_CHAIN)case AMDGPUISD::FMUL_W_CHAIN: return "FMUL_W_CHAIN";
4249 NODE_NAME_CASE(CLAMP)case AMDGPUISD::CLAMP: return "CLAMP";
4250 NODE_NAME_CASE(COS_HW)case AMDGPUISD::COS_HW: return "COS_HW";
4251 NODE_NAME_CASE(SIN_HW)case AMDGPUISD::SIN_HW: return "SIN_HW";
4252 NODE_NAME_CASE(FMAX_LEGACY)case AMDGPUISD::FMAX_LEGACY: return "FMAX_LEGACY";
4253 NODE_NAME_CASE(FMIN_LEGACY)case AMDGPUISD::FMIN_LEGACY: return "FMIN_LEGACY";
4254 NODE_NAME_CASE(FMAX3)case AMDGPUISD::FMAX3: return "FMAX3";
4255 NODE_NAME_CASE(SMAX3)case AMDGPUISD::SMAX3: return "SMAX3";
4256 NODE_NAME_CASE(UMAX3)case AMDGPUISD::UMAX3: return "UMAX3";
4257 NODE_NAME_CASE(FMIN3)case AMDGPUISD::FMIN3: return "FMIN3";
4258 NODE_NAME_CASE(SMIN3)case AMDGPUISD::SMIN3: return "SMIN3";
4259 NODE_NAME_CASE(UMIN3)case AMDGPUISD::UMIN3: return "UMIN3";
4260 NODE_NAME_CASE(FMED3)case AMDGPUISD::FMED3: return "FMED3";
4261 NODE_NAME_CASE(SMED3)case AMDGPUISD::SMED3: return "SMED3";
4262 NODE_NAME_CASE(UMED3)case AMDGPUISD::UMED3: return "UMED3";
4263 NODE_NAME_CASE(FDOT2)case AMDGPUISD::FDOT2: return "FDOT2";
4264 NODE_NAME_CASE(URECIP)case AMDGPUISD::URECIP: return "URECIP";
4265 NODE_NAME_CASE(DIV_SCALE)case AMDGPUISD::DIV_SCALE: return "DIV_SCALE";
4266 NODE_NAME_CASE(DIV_FMAS)case AMDGPUISD::DIV_FMAS: return "DIV_FMAS";
4267 NODE_NAME_CASE(DIV_FIXUP)case AMDGPUISD::DIV_FIXUP: return "DIV_FIXUP";
4268 NODE_NAME_CASE(FMAD_FTZ)case AMDGPUISD::FMAD_FTZ: return "FMAD_FTZ";
4269 NODE_NAME_CASE(TRIG_PREOP)case AMDGPUISD::TRIG_PREOP: return "TRIG_PREOP";
4270 NODE_NAME_CASE(RCP)case AMDGPUISD::RCP: return "RCP";
4271 NODE_NAME_CASE(RSQ)case AMDGPUISD::RSQ: return "RSQ";
4272 NODE_NAME_CASE(RCP_LEGACY)case AMDGPUISD::RCP_LEGACY: return "RCP_LEGACY";
4273 NODE_NAME_CASE(RSQ_LEGACY)case AMDGPUISD::RSQ_LEGACY: return "RSQ_LEGACY";
4274 NODE_NAME_CASE(RCP_IFLAG)case AMDGPUISD::RCP_IFLAG: return "RCP_IFLAG";
4275 NODE_NAME_CASE(FMUL_LEGACY)case AMDGPUISD::FMUL_LEGACY: return "FMUL_LEGACY";
4276 NODE_NAME_CASE(RSQ_CLAMP)case AMDGPUISD::RSQ_CLAMP: return "RSQ_CLAMP";
4277 NODE_NAME_CASE(LDEXP)case AMDGPUISD::LDEXP: return "LDEXP";
4278 NODE_NAME_CASE(FP_CLASS)case AMDGPUISD::FP_CLASS: return "FP_CLASS";
4279 NODE_NAME_CASE(DOT4)case AMDGPUISD::DOT4: return "DOT4";
4280 NODE_NAME_CASE(CARRY)case AMDGPUISD::CARRY: return "CARRY";
4281 NODE_NAME_CASE(BORROW)case AMDGPUISD::BORROW: return "BORROW";
4282 NODE_NAME_CASE(BFE_U32)case AMDGPUISD::BFE_U32: return "BFE_U32";
4283 NODE_NAME_CASE(BFE_I32)case AMDGPUISD::BFE_I32: return "BFE_I32";
4284 NODE_NAME_CASE(BFI)case AMDGPUISD::BFI: return "BFI";
4285 NODE_NAME_CASE(BFM)case AMDGPUISD::BFM: return "BFM";
4286 NODE_NAME_CASE(FFBH_U32)case AMDGPUISD::FFBH_U32: return "FFBH_U32";
4287 NODE_NAME_CASE(FFBH_I32)case AMDGPUISD::FFBH_I32: return "FFBH_I32";
4288 NODE_NAME_CASE(FFBL_B32)case AMDGPUISD::FFBL_B32: return "FFBL_B32";
4289 NODE_NAME_CASE(MUL_U24)case AMDGPUISD::MUL_U24: return "MUL_U24";
4290 NODE_NAME_CASE(MUL_I24)case AMDGPUISD::MUL_I24: return "MUL_I24";
4291 NODE_NAME_CASE(MULHI_U24)case AMDGPUISD::MULHI_U24: return "MULHI_U24";
4292 NODE_NAME_CASE(MULHI_I24)case AMDGPUISD::MULHI_I24: return "MULHI_I24";
4293 NODE_NAME_CASE(MUL_LOHI_U24)case AMDGPUISD::MUL_LOHI_U24: return "MUL_LOHI_U24";
4294 NODE_NAME_CASE(MUL_LOHI_I24)case AMDGPUISD::MUL_LOHI_I24: return "MUL_LOHI_I24";
4295 NODE_NAME_CASE(MAD_U24)case AMDGPUISD::MAD_U24: return "MAD_U24";
4296 NODE_NAME_CASE(MAD_I24)case AMDGPUISD::MAD_I24: return "MAD_I24";
4297 NODE_NAME_CASE(MAD_I64_I32)case AMDGPUISD::MAD_I64_I32: return "MAD_I64_I32";
4298 NODE_NAME_CASE(MAD_U64_U32)case AMDGPUISD::MAD_U64_U32: return "MAD_U64_U32";
4299 NODE_NAME_CASE(PERM)case AMDGPUISD::PERM: return "PERM";
4300 NODE_NAME_CASE(TEXTURE_FETCH)case AMDGPUISD::TEXTURE_FETCH: return "TEXTURE_FETCH";
4301 NODE_NAME_CASE(EXPORT)case AMDGPUISD::EXPORT: return "EXPORT";
4302 NODE_NAME_CASE(EXPORT_DONE)case AMDGPUISD::EXPORT_DONE: return "EXPORT_DONE";
4303 NODE_NAME_CASE(R600_EXPORT)case AMDGPUISD::R600_EXPORT: return "R600_EXPORT";
4304 NODE_NAME_CASE(CONST_ADDRESS)case AMDGPUISD::CONST_ADDRESS: return "CONST_ADDRESS";
4305 NODE_NAME_CASE(REGISTER_LOAD)case AMDGPUISD::REGISTER_LOAD: return "REGISTER_LOAD";
4306 NODE_NAME_CASE(REGISTER_STORE)case AMDGPUISD::REGISTER_STORE: return "REGISTER_STORE";
4307 NODE_NAME_CASE(SAMPLE)case AMDGPUISD::SAMPLE: return "SAMPLE";
4308 NODE_NAME_CASE(SAMPLEB)case AMDGPUISD::SAMPLEB: return "SAMPLEB";
4309 NODE_NAME_CASE(SAMPLED)case AMDGPUISD::SAMPLED: return "SAMPLED";
4310 NODE_NAME_CASE(SAMPLEL)case AMDGPUISD::SAMPLEL: return "SAMPLEL";
4311 NODE_NAME_CASE(CVT_F32_UBYTE0)case AMDGPUISD::CVT_F32_UBYTE0: return "CVT_F32_UBYTE0";
4312 NODE_NAME_CASE(CVT_F32_UBYTE1)case AMDGPUISD::CVT_F32_UBYTE1: return "CVT_F32_UBYTE1";
4313 NODE_NAME_CASE(CVT_F32_UBYTE2)case AMDGPUISD::CVT_F32_UBYTE2: return "CVT_F32_UBYTE2";
4314 NODE_NAME_CASE(CVT_F32_UBYTE3)case AMDGPUISD::CVT_F32_UBYTE3: return "CVT_F32_UBYTE3";
4315 NODE_NAME_CASE(CVT_PKRTZ_F16_F32)case AMDGPUISD::CVT_PKRTZ_F16_F32: return "CVT_PKRTZ_F16_F32"
;
4316 NODE_NAME_CASE(CVT_PKNORM_I16_F32)case AMDGPUISD::CVT_PKNORM_I16_F32: return "CVT_PKNORM_I16_F32"
;
4317 NODE_NAME_CASE(CVT_PKNORM_U16_F32)case AMDGPUISD::CVT_PKNORM_U16_F32: return "CVT_PKNORM_U16_F32"
;
4318 NODE_NAME_CASE(CVT_PK_I16_I32)case AMDGPUISD::CVT_PK_I16_I32: return "CVT_PK_I16_I32";
4319 NODE_NAME_CASE(CVT_PK_U16_U32)case AMDGPUISD::CVT_PK_U16_U32: return "CVT_PK_U16_U32";
4320 NODE_NAME_CASE(FP_TO_FP16)case AMDGPUISD::FP_TO_FP16: return "FP_TO_FP16";
4321 NODE_NAME_CASE(FP16_ZEXT)case AMDGPUISD::FP16_ZEXT: return "FP16_ZEXT";
4322 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)case AMDGPUISD::BUILD_VERTICAL_VECTOR: return "BUILD_VERTICAL_VECTOR"
;
4323 NODE_NAME_CASE(CONST_DATA_PTR)case AMDGPUISD::CONST_DATA_PTR: return "CONST_DATA_PTR";
4324 NODE_NAME_CASE(PC_ADD_REL_OFFSET)case AMDGPUISD::PC_ADD_REL_OFFSET: return "PC_ADD_REL_OFFSET"
;
4325 NODE_NAME_CASE(LDS)case AMDGPUISD::LDS: return "LDS";
4326 NODE_NAME_CASE(KILL)case AMDGPUISD::KILL: return "KILL";
4327 NODE_NAME_CASE(DUMMY_CHAIN)case AMDGPUISD::DUMMY_CHAIN: return "DUMMY_CHAIN";
4328 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
4329 NODE_NAME_CASE(INTERP_P1LL_F16)case AMDGPUISD::INTERP_P1LL_F16: return "INTERP_P1LL_F16";
4330 NODE_NAME_CASE(INTERP_P1LV_F16)case AMDGPUISD::INTERP_P1LV_F16: return "INTERP_P1LV_F16";
4331 NODE_NAME_CASE(INTERP_P2_F16)case AMDGPUISD::INTERP_P2_F16: return "INTERP_P2_F16";
4332 NODE_NAME_CASE(LOAD_D16_HI)case AMDGPUISD::LOAD_D16_HI: return "LOAD_D16_HI";
4333 NODE_NAME_CASE(LOAD_D16_LO)case AMDGPUISD::LOAD_D16_LO: return "LOAD_D16_LO";
4334 NODE_NAME_CASE(LOAD_D16_HI_I8)case AMDGPUISD::LOAD_D16_HI_I8: return "LOAD_D16_HI_I8";
4335 NODE_NAME_CASE(LOAD_D16_HI_U8)case AMDGPUISD::LOAD_D16_HI_U8: return "LOAD_D16_HI_U8";
4336 NODE_NAME_CASE(LOAD_D16_LO_I8)case AMDGPUISD::LOAD_D16_LO_I8: return "LOAD_D16_LO_I8";
4337 NODE_NAME_CASE(LOAD_D16_LO_U8)case AMDGPUISD::LOAD_D16_LO_U8: return "LOAD_D16_LO_U8";
4338 NODE_NAME_CASE(STORE_MSKOR)case AMDGPUISD::STORE_MSKOR: return "STORE_MSKOR";
4339 NODE_NAME_CASE(LOAD_CONSTANT)case AMDGPUISD::LOAD_CONSTANT: return "LOAD_CONSTANT";
4340 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)case AMDGPUISD::TBUFFER_STORE_FORMAT: return "TBUFFER_STORE_FORMAT"
;
4341 NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)case AMDGPUISD::TBUFFER_STORE_FORMAT_D16: return "TBUFFER_STORE_FORMAT_D16"
;
4342 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)case AMDGPUISD::TBUFFER_LOAD_FORMAT: return "TBUFFER_LOAD_FORMAT"
;
4343 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)case AMDGPUISD::TBUFFER_LOAD_FORMAT_D16: return "TBUFFER_LOAD_FORMAT_D16"
;
4344 NODE_NAME_CASE(DS_ORDERED_COUNT)case AMDGPUISD::DS_ORDERED_COUNT: return "DS_ORDERED_COUNT";
4345 NODE_NAME_CASE(ATOMIC_CMP_SWAP)case AMDGPUISD::ATOMIC_CMP_SWAP: return "ATOMIC_CMP_SWAP";
4346 NODE_NAME_CASE(ATOMIC_INC)case AMDGPUISD::ATOMIC_INC: return "ATOMIC_INC";
4347 NODE_NAME_CASE(ATOMIC_DEC)case AMDGPUISD::ATOMIC_DEC: return "ATOMIC_DEC";
4348 NODE_NAME_CASE(ATOMIC_LOAD_FMIN)case AMDGPUISD::ATOMIC_LOAD_FMIN: return "ATOMIC_LOAD_FMIN";
4349 NODE_NAME_CASE(ATOMIC_LOAD_FMAX)case AMDGPUISD::ATOMIC_LOAD_FMAX: return "ATOMIC_LOAD_FMAX";
4350 NODE_NAME_CASE(BUFFER_LOAD)case AMDGPUISD::BUFFER_LOAD: return "BUFFER_LOAD";
4351 NODE_NAME_CASE(BUFFER_LOAD_UBYTE)case AMDGPUISD::BUFFER_LOAD_UBYTE: return "BUFFER_LOAD_UBYTE"
;
4352 NODE_NAME_CASE(BUFFER_LOAD_USHORT)case AMDGPUISD::BUFFER_LOAD_USHORT: return "BUFFER_LOAD_USHORT"
;
4353 NODE_NAME_CASE(BUFFER_LOAD_BYTE)case AMDGPUISD::BUFFER_LOAD_BYTE: return "BUFFER_LOAD_BYTE";
4354 NODE_NAME_CASE(BUFFER_LOAD_SHORT)case AMDGPUISD::BUFFER_LOAD_SHORT: return "BUFFER_LOAD_SHORT"
;
4355 NODE_NAME_CASE(BUFFER_LOAD_FORMAT)case AMDGPUISD::BUFFER_LOAD_FORMAT: return "BUFFER_LOAD_FORMAT"
;
4356 NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)case AMDGPUISD::BUFFER_LOAD_FORMAT_D16: return "BUFFER_LOAD_FORMAT_D16"
;
4357 NODE_NAME_CASE(SBUFFER_LOAD)case AMDGPUISD::SBUFFER_LOAD: return "SBUFFER_LOAD";
4358 NODE_NAME_CASE(BUFFER_STORE)case AMDGPUISD::BUFFER_STORE: return "BUFFER_STORE";
4359 NODE_NAME_CASE(BUFFER_STORE_BYTE)case AMDGPUISD::BUFFER_STORE_BYTE: return "BUFFER_STORE_BYTE"
;
4360 NODE_NAME_CASE(BUFFER_STORE_SHORT)case AMDGPUISD::BUFFER_STORE_SHORT: return "BUFFER_STORE_SHORT"
;
4361 NODE_NAME_CASE(BUFFER_STORE_FORMAT)case AMDGPUISD::BUFFER_STORE_FORMAT: return "BUFFER_STORE_FORMAT"
;
4362 NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)case AMDGPUISD::BUFFER_STORE_FORMAT_D16: return "BUFFER_STORE_FORMAT_D16"
;
4363 NODE_NAME_CASE(BUFFER_ATOMIC_SWAP)case AMDGPUISD::BUFFER_ATOMIC_SWAP: return "BUFFER_ATOMIC_SWAP"
;
4364 NODE_NAME_CASE(BUFFER_ATOMIC_ADD)case AMDGPUISD::BUFFER_ATOMIC_ADD: return "BUFFER_ATOMIC_ADD"
;
4365 NODE_NAME_CASE(BUFFER_ATOMIC_SUB)case AMDGPUISD::BUFFER_ATOMIC_SUB: return "BUFFER_ATOMIC_SUB"
;
4366 NODE_NAME_CASE(BUFFER_ATOMIC_SMIN)case AMDGPUISD::BUFFER_ATOMIC_SMIN: return "BUFFER_ATOMIC_SMIN"
;
4367 NODE_NAME_CASE(BUFFER_ATOMIC_UMIN)case AMDGPUISD::BUFFER_ATOMIC_UMIN: return "BUFFER_ATOMIC_UMIN"
;
4368 NODE_NAME_CASE(BUFFER_ATOMIC_SMAX)case AMDGPUISD::BUFFER_ATOMIC_SMAX: return "BUFFER_ATOMIC_SMAX"
;
4369 NODE_NAME_CASE(BUFFER_ATOMIC_UMAX)case AMDGPUISD::BUFFER_ATOMIC_UMAX: return "BUFFER_ATOMIC_UMAX"
;
4370 NODE_NAME_CASE(BUFFER_ATOMIC_AND)case AMDGPUISD::BUFFER_ATOMIC_AND: return "BUFFER_ATOMIC_AND"
;
4371 NODE_NAME_CASE(BUFFER_ATOMIC_OR)case AMDGPUISD::BUFFER_ATOMIC_OR: return "BUFFER_ATOMIC_OR";
4372 NODE_NAME_CASE(BUFFER_ATOMIC_XOR)case AMDGPUISD::BUFFER_ATOMIC_XOR: return "BUFFER_ATOMIC_XOR"
;
4373 NODE_NAME_CASE(BUFFER_ATOMIC_INC)case AMDGPUISD::BUFFER_ATOMIC_INC: return "BUFFER_ATOMIC_INC"
;
4374 NODE_NAME_CASE(BUFFER_ATOMIC_DEC)case AMDGPUISD::BUFFER_ATOMIC_DEC: return "BUFFER_ATOMIC_DEC"
;
4375 NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP)case AMDGPUISD::BUFFER_ATOMIC_CMPSWAP: return "BUFFER_ATOMIC_CMPSWAP"
;
4376 NODE_NAME_CASE(BUFFER_ATOMIC_FADD)case AMDGPUISD::BUFFER_ATOMIC_FADD: return "BUFFER_ATOMIC_FADD"
;
4377 NODE_NAME_CASE(BUFFER_ATOMIC_PK_FADD)case AMDGPUISD::BUFFER_ATOMIC_PK_FADD: return "BUFFER_ATOMIC_PK_FADD"
;
4378 NODE_NAME_CASE(ATOMIC_PK_FADD)case AMDGPUISD::ATOMIC_PK_FADD: return "ATOMIC_PK_FADD";
4379
4380 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
4381 }
4382 return nullptr;
4383}
4384
4385SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4386 SelectionDAG &DAG, int Enabled,
4387 int &RefinementSteps,
4388 bool &UseOneConstNR,
4389 bool Reciprocal) const {
4390 EVT VT = Operand.getValueType();
4391
4392 if (VT == MVT::f32) {
4393 RefinementSteps = 0;
4394 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
4395 }
4396
4397 // TODO: There is also f64 rsq instruction, but the documentation is less
4398 // clear on its precision.
4399
4400 return SDValue();
4401}
4402
4403SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4404 SelectionDAG &DAG, int Enabled,
4405 int &RefinementSteps) const {
4406 EVT VT = Operand.getValueType();
4407
4408 if (VT == MVT::f32) {
4409 // Reciprocal, < 1 ulp error.
4410 //
4411 // This reciprocal approximation converges to < 0.5 ulp error with one
4412 // newton rhapson performed with two fused multiple adds (FMAs).
4413
4414 RefinementSteps = 0;
4415 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
4416 }
4417
4418 // TODO: There is also f64 rcp instruction, but the documentation is less
4419 // clear on its precision.
4420
4421 return SDValue();
4422}
4423
4424void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4425 const SDValue Op, KnownBits &Known,
4426 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
4427
4428 Known.resetAll(); // Don't know anything.
4429
4430 unsigned Opc = Op.getOpcode();
4431
4432 switch (Opc) {
4433 default:
4434 break;
4435 case AMDGPUISD::CARRY:
4436 case AMDGPUISD::BORROW: {
4437 Known.Zero = APInt::getHighBitsSet(32, 31);
4438 break;
4439 }
4440
4441 case AMDGPUISD::BFE_I32:
4442 case AMDGPUISD::BFE_U32: {
4443 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4444 if (!CWidth)
4445 return;
4446
4447 uint32_t Width = CWidth->getZExtValue() & 0x1f;
4448
4449 if (Opc == AMDGPUISD::BFE_U32)
4450 Known.Zero = APInt::getHighBitsSet(32, 32 - Width);
4451
4452 break;
4453 }
4454 case AMDGPUISD::FP_TO_FP16:
4455 case AMDGPUISD::FP16_ZEXT: {
4456 unsigned BitWidth = Known.getBitWidth();
4457
4458 // High bits are zero.
4459 Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
4460 break;
4461 }
4462 case AMDGPUISD::MUL_U24:
4463 case AMDGPUISD::MUL_I24: {
4464 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4465 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4466 unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
4467 RHSKnown.countMinTrailingZeros();
4468 Known.Zero.setLowBits(std::min(TrailZ, 32u));
4469 // Skip extra check if all bits are known zeros.
4470 if (TrailZ >= 32)
4471 break;
4472
4473 // Truncate to 24 bits.
4474 LHSKnown = LHSKnown.trunc(24);
4475 RHSKnown = RHSKnown.trunc(24);
4476
4477 if (Opc == AMDGPUISD::MUL_I24) {
4478 unsigned LHSValBits = 24 - LHSKnown.countMinSignBits();
4479 unsigned RHSValBits = 24 - RHSKnown.countMinSignBits();
4480 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4481 if (MaxValBits >= 32)
4482 break;
4483 bool LHSNegative = LHSKnown.isNegative();
4484 bool LHSNonNegative = LHSKnown.isNonNegative();
4485 bool LHSPositive = LHSKnown.isStrictlyPositive();
4486 bool RHSNegative = RHSKnown.isNegative();
4487 bool RHSNonNegative = RHSKnown.isNonNegative();
4488 bool RHSPositive = RHSKnown.isStrictlyPositive();
4489
4490 if ((LHSNonNegative && RHSNonNegative) || (LHSNegative && RHSNegative))
4491 Known.Zero.setHighBits(32 - MaxValBits);
4492 else if ((LHSNegative && RHSPositive) || (LHSPositive && RHSNegative))
4493 Known.One.setHighBits(32 - MaxValBits);
4494 } else {
4495 unsigned LHSValBits = 24 - LHSKnown.countMinLeadingZeros();
4496 unsigned RHSValBits = 24 - RHSKnown.countMinLeadingZeros();
4497 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4498 if (MaxValBits >= 32)
4499 break;
4500 Known.Zero.setHighBits(32 - MaxValBits);
4501 }
4502 break;
4503 }
4504 case AMDGPUISD::PERM: {
4505 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4506 if (!CMask)
4507 return;
4508
4509 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4510 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4511 unsigned Sel = CMask->getZExtValue();
4512
4513 for (unsigned I = 0; I < 32; I += 8) {
4514 unsigned SelBits = Sel & 0xff;
4515 if (SelBits < 4) {
4516 SelBits *= 8;
4517 Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4518 Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4519 } else if (SelBits < 7) {
4520 SelBits = (SelBits & 3) * 8;
4521 Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4522 Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4523 } else if (SelBits == 0x0c) {
4524 Known.Zero |= 0xFFull << I;
4525 } else if (SelBits > 0x0c) {
4526 Known.One |= 0xFFull << I;
4527 }
4528 Sel >>= 8;
4529 }
4530 break;
4531 }
4532 case AMDGPUISD::BUFFER_LOAD_UBYTE: {
4533 Known.Zero.setHighBits(24);
4534 break;
4535 }
4536 case AMDGPUISD::BUFFER_LOAD_USHORT: {
4537 Known.Zero.setHighBits(16);
4538 break;
4539 }
4540 case AMDGPUISD::LDS: {
4541 auto GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode());
4542 unsigned Align = GA->getGlobal()->getAlignment();
4543
4544 Known.Zero.setHighBits(16);
4545 if (Align)
4546 Known.Zero.setLowBits(Log2_32(Align));
4547 break;
4548 }
4549 case ISD::INTRINSIC_WO_CHAIN: {
4550 unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4551 switch (IID) {
4552 case Intrinsic::amdgcn_mbcnt_lo:
4553 case Intrinsic::amdgcn_mbcnt_hi: {
4554 const GCNSubtarget &ST =
4555 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
4556 // These return at most the wavefront size - 1.
4557 unsigned Size = Op.getValueType().getSizeInBits();
4558 Known.Zero.setHighBits(Size - ST.getWavefrontSizeLog2());
4559 break;
4560 }
4561 default:
4562 break;
4563 }
4564 }
4565 }
4566}
4567
4568unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
4569 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
4570 unsigned Depth) const {
4571 switch (Op.getOpcode()) {
4572 case AMDGPUISD::BFE_I32: {
4573 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4574 if (!Width)
4575 return 1;
4576
4577 unsigned SignBits = 32 - Width->getZExtValue() + 1;
4578 if (!isNullConstant(Op.getOperand(1)))
4579 return SignBits;
4580
4581 // TODO: Could probably figure something out with non-0 offsets.
4582 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4583 return std::max(SignBits, Op0SignBits);
4584 }
4585
4586 case AMDGPUISD::BFE_U32: {
4587 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4588 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
4589 }
4590
4591 case AMDGPUISD::CARRY:
4592 case AMDGPUISD::BORROW:
4593 return 31;
4594 case AMDGPUISD::BUFFER_LOAD_BYTE:
4595 return 25;
4596 case AMDGPUISD::BUFFER_LOAD_SHORT:
4597 return 17;
4598 case AMDGPUISD::BUFFER_LOAD_UBYTE:
4599 return 24;
4600 case AMDGPUISD::BUFFER_LOAD_USHORT:
4601 return 16;
4602 case AMDGPUISD::FP_TO_FP16:
4603 case AMDGPUISD::FP16_ZEXT:
4604 return 16;
4605 default:
4606 return 1;
4607 }
4608}
4609
4610bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
4611 const SelectionDAG &DAG,
4612 bool SNaN,
4613 unsigned Depth) const {
4614 unsigned Opcode = Op.getOpcode();
4615 switch (Opcode) {
4616 case AMDGPUISD::FMIN_LEGACY:
4617 case AMDGPUISD::FMAX_LEGACY: {
4618 if (SNaN)
4619 return true;
4620
4621 // TODO: Can check no nans on one of the operands for each one, but which
4622 // one?
4623 return false;
4624 }
4625 case AMDGPUISD::FMUL_LEGACY:
4626 case AMDGPUISD::CVT_PKRTZ_F16_F32: {
4627 if (SNaN)
4628 return true;
4629 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4630 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4631 }
4632 case AMDGPUISD::FMED3:
4633 case AMDGPUISD::FMIN3:
4634 case AMDGPUISD::FMAX3:
4635 case AMDGPUISD::FMAD_FTZ: {
4636 if (SNaN)
4637 return true;
4638 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4639 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4640 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4641 }
4642 case AMDGPUISD::CVT_F32_UBYTE0:
4643 case AMDGPUISD::CVT_F32_UBYTE1:
4644 case AMDGPUISD::CVT_F32_UBYTE2:
4645 case AMDGPUISD::CVT_F32_UBYTE3:
4646 return true;
4647
4648 case AMDGPUISD::RCP:
4649 case AMDGPUISD::RSQ:
4650 case AMDGPUISD::RCP_LEGACY:
4651 case AMDGPUISD::RSQ_LEGACY:
4652 case AMDGPUISD::RSQ_CLAMP: {
4653 if (SNaN)
4654 return true;
4655
4656 // TODO: Need is known positive check.
4657 return false;
4658 }
4659 case AMDGPUISD::LDEXP:
4660 case AMDGPUISD::FRACT: {
4661 if (SNaN)
4662 return true;
4663 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4664 }
4665 case AMDGPUISD::DIV_SCALE:
4666 case AMDGPUISD::DIV_FMAS:
4667 case AMDGPUISD::DIV_FIXUP:
4668 case AMDGPUISD::TRIG_PREOP:
4669 // TODO: Refine on operands.
4670 return SNaN;
4671 case AMDGPUISD::SIN_HW:
4672 case AMDGPUISD::COS_HW: {
4673 // TODO: Need check for infinity
4674 return SNaN;
4675 }
4676 case ISD::INTRINSIC_WO_CHAIN: {
4677 unsigned IntrinsicID
4678 = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4679 // TODO: Handle more intrinsics
4680 switch (IntrinsicID) {
4681 case Intrinsic::amdgcn_cubeid:
4682 return true;
4683
4684 case Intrinsic::amdgcn_frexp_mant: {
4685 if (SNaN)
4686 return true;
4687 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4688 }
4689 case Intrinsic::amdgcn_cvt_pkrtz: {
4690 if (SNaN)
4691 return true;
4692 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4693 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4694 }
4695 case Intrinsic::amdgcn_fdot2:
4696 // TODO: Refine on operand
4697 return SNaN;
4698 default:
4699 return false;
4700 }
4701 }
4702 default:
4703 return false;
4704 }
4705}
4706
4707TargetLowering::AtomicExpansionKind
4708AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
4709 switch (RMW->getOperation()) {
4710 case AtomicRMWInst::Nand:
4711 case AtomicRMWInst::FAdd:
4712 case AtomicRMWInst::FSub:
4713 return AtomicExpansionKind::CmpXChg;
4714 default:
4715 return AtomicExpansionKind::None;
4716 }
4717}

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h

1//===- llvm/Support/Casting.h - Allow flexible, checked, casts --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the isa<X>(), cast<X>(), dyn_cast<X>(), cast_or_null<X>(),
10// and dyn_cast_or_null<X>() templates.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_CASTING_H
15#define LLVM_SUPPORT_CASTING_H
16
17#include "llvm/Support/Compiler.h"
18#include "llvm/Support/type_traits.h"
19#include <cassert>
20#include <memory>
21#include <type_traits>
22
23namespace llvm {
24
25//===----------------------------------------------------------------------===//
26// isa<x> Support Templates
27//===----------------------------------------------------------------------===//
28
29// Define a template that can be specialized by smart pointers to reflect the
30// fact that they are automatically dereferenced, and are not involved with the
31// template selection process... the default implementation is a noop.
32//
33template<typename From> struct simplify_type {
34 using SimpleType = From; // The real type this represents...
35
36 // An accessor to get the real value...
37 static SimpleType &getSimplifiedValue(From &Val) { return Val; }
38};
39
40template<typename From> struct simplify_type<const From> {
41 using NonConstSimpleType = typename simplify_type<From>::SimpleType;
42 using SimpleType =
43 typename add_const_past_pointer<NonConstSimpleType>::type;
44 using RetType =
45 typename add_lvalue_reference_if_not_pointer<SimpleType>::type;
46
47 static RetType getSimplifiedValue(const From& Val) {
48 return simplify_type<From>::getSimplifiedValue(const_cast<From&>(Val));
49 }
50};
51
52// The core of the implementation of isa<X> is here; To and From should be
53// the names of classes. This template can be specialized to customize the
54// implementation of isa<> without rewriting it from scratch.
55template <typename To, typename From, typename Enabler = void>
56struct isa_impl {
57 static inline bool doit(const From &Val) {
58 return To::classof(&Val);
59 }
60};
61
62/// Always allow upcasts, and perform no dynamic check for them.
63template <typename To, typename From>
64struct isa_impl<
65 To, From, typename std::enable_if<std::is_base_of<To, From>::value>::type> {
66 static inline bool doit(const From &) { return true; }
67};
68
69template <typename To, typename From> struct isa_impl_cl {
70 static inline bool doit(const From &Val) {
71 return isa_impl<To, From>::doit(Val);
72 }
73};
74
75template <typename To, typename From> struct isa_impl_cl<To, const From> {
76 static inline bool doit(const From &Val) {
77 return isa_impl<To, From>::doit(Val);
78 }
79};
80
81template <typename To, typename From>
82struct isa_impl_cl<To, const std::unique_ptr<From>> {
83 static inline bool doit(const std::unique_ptr<From> &Val) {
84 assert(Val && "isa<> used on a null pointer")((Val && "isa<> used on a null pointer") ? static_cast
<void> (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 84, __PRETTY_FUNCTION__))
;
85 return isa_impl_cl<To, From>::doit(*Val);
86 }
87};
88
89template <typename To, typename From> struct isa_impl_cl<To, From*> {
90 static inline bool doit(const From *Val) {
91 assert(Val && "isa<> used on a null pointer")((Val && "isa<> used on a null pointer") ? static_cast
<void> (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 91, __PRETTY_FUNCTION__))
;
92 return isa_impl<To, From>::doit(*Val);
93 }
94};
95
96template <typename To, typename From> struct isa_impl_cl<To, From*const> {
97 static inline bool doit(const From *Val) {
98 assert(Val && "isa<> used on a null pointer")((Val && "isa<> used on a null pointer") ? static_cast
<void> (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 98, __PRETTY_FUNCTION__))
;
99 return isa_impl<To, From>::doit(*Val);
100 }
101};
102
103template <typename To, typename From> struct isa_impl_cl<To, const From*> {
104 static inline bool doit(const From *Val) {
105 assert(Val && "isa<> used on a null pointer")((Val && "isa<> used on a null pointer") ? static_cast
<void> (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 105, __PRETTY_FUNCTION__))
;
106 return isa_impl<To, From>::doit(*Val);
107 }
108};
109
110template <typename To, typename From> struct isa_impl_cl<To, const From*const> {
111 static inline bool doit(const From *Val) {
112 assert(Val && "isa<> used on a null pointer")((Val && "isa<> used on a null pointer") ? static_cast
<void> (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 112, __PRETTY_FUNCTION__))
;
113 return isa_impl<To, From>::doit(*Val);
114 }
115};
116
117template<typename To, typename From, typename SimpleFrom>
118struct isa_impl_wrap {
119 // When From != SimplifiedType, we can simplify the type some more by using
120 // the simplify_type template.
121 static bool doit(const From &Val) {
122 return isa_impl_wrap<To, SimpleFrom,
123 typename simplify_type<SimpleFrom>::SimpleType>::doit(
124 simplify_type<const From>::getSimplifiedValue(Val));
125 }
126};
127
128template<typename To, typename FromTy>
129struct isa_impl_wrap<To, FromTy, FromTy> {
130 // When From == SimpleType, we are as simple as we are going to get.
131 static bool doit(const FromTy &Val) {
132 return isa_impl_cl<To,FromTy>::doit(Val);
133 }
134};
135
136// isa<X> - Return true if the parameter to the template is an instance of the
137// template type argument. Used like this:
138//
139// if (isa<Type>(myVal)) { ... }
140//
141template <class X, class Y> LLVM_NODISCARD[[clang::warn_unused_result]] inline bool isa(const Y &Val) {
142 return isa_impl_wrap<X, const Y,
143 typename simplify_type<const Y>::SimpleType>::doit(Val);
144}
145
146// isa_and_nonnull<X> - Functionally identical to isa, except that a null value
147// is accepted.
148//
149template <class X, class Y>
150LLVM_NODISCARD[[clang::warn_unused_result]] inline bool isa_and_nonnull(const Y &Val) {
151 if (!Val)
152 return false;
153 return isa<X>(Val);
154}
155
156//===----------------------------------------------------------------------===//
157// cast<x> Support Templates
158//===----------------------------------------------------------------------===//
159
160template<class To, class From> struct cast_retty;
161
162// Calculate what type the 'cast' function should return, based on a requested
163// type of To and a source type of From.
164template<class To, class From> struct cast_retty_impl {
165 using ret_type = To &; // Normal case, return Ty&
166};
167template<class To, class From> struct cast_retty_impl<To, const From> {
168 using ret_type = const To &; // Normal case, return Ty&
169};
170
171template<class To, class From> struct cast_retty_impl<To, From*> {
172 using ret_type = To *; // Pointer arg case, return Ty*
173};
174
175template<class To, class From> struct cast_retty_impl<To, const From*> {
176 using ret_type = const To *; // Constant pointer arg case, return const Ty*
177};
178
179template<class To, class From> struct cast_retty_impl<To, const From*const> {
180 using ret_type = const To *; // Constant pointer arg case, return const Ty*
181};
182
183template <class To, class From>
184struct cast_retty_impl<To, std::unique_ptr<From>> {
185private:
186 using PointerType = typename cast_retty_impl<To, From *>::ret_type;
187 using ResultType = typename std::remove_pointer<PointerType>::type;
188
189public:
190 using ret_type = std::unique_ptr<ResultType>;
191};
192
193template<class To, class From, class SimpleFrom>
194struct cast_retty_wrap {
195 // When the simplified type and the from type are not the same, use the type
196 // simplifier to reduce the type, then reuse cast_retty_impl to get the
197 // resultant type.
198 using ret_type = typename cast_retty<To, SimpleFrom>::ret_type;
199};
200
201template<class To, class FromTy>
202struct cast_retty_wrap<To, FromTy, FromTy> {
203 // When the simplified type is equal to the from type, use it directly.
204 using ret_type = typename cast_retty_impl<To,FromTy>::ret_type;
205};
206
207template<class To, class From>
208struct cast_retty {
209 using ret_type = typename cast_retty_wrap<
210 To, From, typename simplify_type<From>::SimpleType>::ret_type;
211};
212
213// Ensure the non-simple values are converted using the simplify_type template
214// that may be specialized by smart pointers...
215//
216template<class To, class From, class SimpleFrom> struct cast_convert_val {
217 // This is not a simple type, use the template to simplify it...
218 static typename cast_retty<To, From>::ret_type doit(From &Val) {
219 return cast_convert_val<To, SimpleFrom,
23
Returning without writing to 'Val.Node'
220 typename simplify_type<SimpleFrom>::SimpleType>::doit(
221 simplify_type<From>::getSimplifiedValue(Val));
20
Calling 'simplify_type::getSimplifiedValue'
22
Returning from 'simplify_type::getSimplifiedValue'
222 }
223};
224
225template<class To, class FromTy> struct cast_convert_val<To,FromTy,FromTy> {
226 // This _is_ a simple type, just cast it.
227 static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {
228 typename cast_retty<To, FromTy>::ret_type Res2
229 = (typename cast_retty<To, FromTy>::ret_type)const_cast<FromTy&>(Val);
230 return Res2;
231 }
232};
233
234template <class X> struct is_simple_type {
235 static const bool value =
236 std::is_same<X, typename simplify_type<X>::SimpleType>::value;
237};
238
239// cast<X> - Return the argument parameter cast to the specified type. This
240// casting operator asserts that the type is correct, so it does not return null
241// on failure. It does not allow a null argument (use cast_or_null for that).
242// It is typically used like this:
243//
244// cast<Instruction>(myVal)->getParent()
245//
246template <class X, class Y>
247inline typename std::enable_if<!is_simple_type<Y>::value,
248 typename cast_retty<X, const Y>::ret_type>::type
249cast(const Y &Val) {
250 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 250, __PRETTY_FUNCTION__))
;
251 return cast_convert_val<
252 X, const Y, typename simplify_type<const Y>::SimpleType>::doit(Val);
253}
254
255template <class X, class Y>
256inline typename cast_retty<X, Y>::ret_type cast(Y &Val) {
257 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 257, __PRETTY_FUNCTION__))
;
17
'Val' is a 'ConstantSDNode'
18
'?' condition is true
258 return cast_convert_val<X, Y,
19
Calling 'cast_convert_val::doit'
24
Returning from 'cast_convert_val::doit'
25
Returning without writing to 'Val.Node'
259 typename simplify_type<Y>::SimpleType>::doit(Val);
260}
261
262template <class X, class Y>
263inline typename cast_retty<X, Y *>::ret_type cast(Y *Val) {
264 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 264, __PRETTY_FUNCTION__))
;
265 return cast_convert_val<X, Y*,
266 typename simplify_type<Y*>::SimpleType>::doit(Val);
267}
268
269template <class X, class Y>
270inline typename cast_retty<X, std::unique_ptr<Y>>::ret_type
271cast(std::unique_ptr<Y> &&Val) {
272 assert(isa<X>(Val.get()) && "cast<Ty>() argument of incompatible type!")((isa<X>(Val.get()) && "cast<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val.get()) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 272, __PRETTY_FUNCTION__))
;
273 using ret_type = typename cast_retty<X, std::unique_ptr<Y>>::ret_type;
274 return ret_type(
275 cast_convert_val<X, Y *, typename simplify_type<Y *>::SimpleType>::doit(
276 Val.release()));
277}
278
279// cast_or_null<X> - Functionally identical to cast, except that a null value is
280// accepted.
281//
282template <class X, class Y>
283LLVM_NODISCARD[[clang::warn_unused_result]] inline
284 typename std::enable_if<!is_simple_type<Y>::value,
285 typename cast_retty<X, const Y>::ret_type>::type
286 cast_or_null(const Y &Val) {
287 if (!Val)
288 return nullptr;
289 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 289, __PRETTY_FUNCTION__))
;
290 return cast<X>(Val);
291}
292
293template <class X, class Y>
294LLVM_NODISCARD[[clang::warn_unused_result]] inline
295 typename std::enable_if<!is_simple_type<Y>::value,
296 typename cast_retty<X, Y>::ret_type>::type
297 cast_or_null(Y &Val) {
298 if (!Val)
299 return nullptr;
300 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 300, __PRETTY_FUNCTION__))
;
301 return cast<X>(Val);
302}
303
304template <class X, class Y>
305LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type
306cast_or_null(Y *Val) {
307 if (!Val) return nullptr;
308 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")((isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? static_cast<void> (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/Casting.h"
, 308, __PRETTY_FUNCTION__))
;
309 return cast<X>(Val);
310}
311
312template <class X, class Y>
313inline typename cast_retty<X, std::unique_ptr<Y>>::ret_type
314cast_or_null(std::unique_ptr<Y> &&Val) {
315 if (!Val)
316 return nullptr;
317 return cast<X>(std::move(Val));
318}
319
320// dyn_cast<X> - Return the argument parameter cast to the specified type. This
321// casting operator returns null if the argument is of the wrong type, so it can
322// be used to test for a type as well as cast if successful. This should be
323// used in the context of an if statement like this:
324//
325// if (const Instruction *I = dyn_cast<Instruction>(myVal)) { ... }
326//
327
328template <class X, class Y>
329LLVM_NODISCARD[[clang::warn_unused_result]] inline
330 typename std::enable_if<!is_simple_type<Y>::value,
331 typename cast_retty<X, const Y>::ret_type>::type
332 dyn_cast(const Y &Val) {
333 return isa<X>(Val) ? cast<X>(Val) : nullptr;
334}
335
336template <class X, class Y>
337LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y>::ret_type dyn_cast(Y &Val) {
338 return isa<X>(Val) ? cast<X>(Val) : nullptr;
14
Assuming 'Val' is a 'ConstantSDNode'
15
'?' condition is true
16
Calling 'cast<llvm::ConstantSDNode, llvm::SDValue>'
26
Returning from 'cast<llvm::ConstantSDNode, llvm::SDValue>'
27
Returning without writing to 'Val.Node'
339}
340
341template <class X, class Y>
342LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type dyn_cast(Y *Val) {
343 return isa<X>(Val) ? cast<X>(Val) : nullptr;
344}
345
346// dyn_cast_or_null<X> - Functionally identical to dyn_cast, except that a null
347// value is accepted.
348//
349template <class X, class Y>
350LLVM_NODISCARD[[clang::warn_unused_result]] inline
351 typename std::enable_if<!is_simple_type<Y>::value,
352 typename cast_retty<X, const Y>::ret_type>::type
353 dyn_cast_or_null(const Y &Val) {
354 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
355}
356
357template <class X, class Y>
358LLVM_NODISCARD[[clang::warn_unused_result]] inline
359 typename std::enable_if<!is_simple_type<Y>::value,
360 typename cast_retty<X, Y>::ret_type>::type
361 dyn_cast_or_null(Y &Val) {
362 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
363}
364
365template <class X, class Y>
366LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type
367dyn_cast_or_null(Y *Val) {
368 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
369}
370
371// unique_dyn_cast<X> - Given a unique_ptr<Y>, try to return a unique_ptr<X>,
372// taking ownership of the input pointer iff isa<X>(Val) is true. If the
373// cast is successful, From refers to nullptr on exit and the casted value
374// is returned. If the cast is unsuccessful, the function returns nullptr
375// and From is unchanged.
376template <class X, class Y>
377LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast(std::unique_ptr<Y> &Val)
378 -> decltype(cast<X>(Val)) {
379 if (!isa<X>(Val))
380 return nullptr;
381 return cast<X>(std::move(Val));
382}
383
384template <class X, class Y>
385LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast(std::unique_ptr<Y> &&Val)
386 -> decltype(cast<X>(Val)) {
387 return unique_dyn_cast<X, Y>(Val);
388}
389
390// dyn_cast_or_null<X> - Functionally identical to unique_dyn_cast, except that
391// a null value is accepted.
392template <class X, class Y>
393LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast_or_null(std::unique_ptr<Y> &Val)
394 -> decltype(cast<X>(Val)) {
395 if (!Val)
396 return nullptr;
397 return unique_dyn_cast<X, Y>(Val);
398}
399
400template <class X, class Y>
401LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast_or_null(std::unique_ptr<Y> &&Val)
402 -> decltype(cast<X>(Val)) {
403 return unique_dyn_cast_or_null<X, Y>(Val);
404}
405
406} // end namespace llvm
407
408#endif // LLVM_SUPPORT_CASTING_H

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
21
Returning without writing to 'Val.Node'
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 bool isFast() const {
473 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
474 AllowContract && ApproximateFuncs && AllowReassociation;
475 }
476
477 /// Clear any flags in this flag set that aren't also set in Flags.
478 /// If the given Flags are undefined then don't do anything.
479 void intersectWith(const SDNodeFlags Flags) {
480 if (!Flags.isDefined())
481 return;
482 NoUnsignedWrap &= Flags.NoUnsignedWrap;
483 NoSignedWrap &= Flags.NoSignedWrap;
484 Exact &= Flags.Exact;
485 NoNaNs &= Flags.NoNaNs;
486 NoInfs &= Flags.NoInfs;
487 NoSignedZeros &= Flags.NoSignedZeros;
488 AllowReciprocal &= Flags.AllowReciprocal;
489 VectorReduction &= Flags.VectorReduction;
490 AllowContract &= Flags.AllowContract;
491 ApproximateFuncs &= Flags.ApproximateFuncs;
492 AllowReassociation &= Flags.AllowReassociation;
493 NoFPExcept &= Flags.NoFPExcept;
494 }
495};
496
497/// Represents one node in the SelectionDAG.
498///
499class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
500private:
501 /// The operation that this node performs.
502 int16_t NodeType;
503
504protected:
505 // We define a set of mini-helper classes to help us interpret the bits in our
506 // SubclassData. These are designed to fit within a uint16_t so they pack
507 // with NodeType.
508
509#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
510// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
511// and give the `pack` pragma push semantics.
512#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
513#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
514#else
515#define BEGIN_TWO_BYTE_PACK()
516#define END_TWO_BYTE_PACK()
517#endif
518
519BEGIN_TWO_BYTE_PACK()
520 class SDNodeBitfields {
521 friend class SDNode;
522 friend class MemIntrinsicSDNode;
523 friend class MemSDNode;
524 friend class SelectionDAG;
525
526 uint16_t HasDebugValue : 1;
527 uint16_t IsMemIntrinsic : 1;
528 uint16_t IsDivergent : 1;
529 };
530 enum { NumSDNodeBits = 3 };
531
532 class ConstantSDNodeBitfields {
533 friend class ConstantSDNode;
534
535 uint16_t : NumSDNodeBits;
536
537 uint16_t IsOpaque : 1;
538 };
539
540 class MemSDNodeBitfields {
541 friend class MemSDNode;
542 friend class MemIntrinsicSDNode;
543 friend class AtomicSDNode;
544
545 uint16_t : NumSDNodeBits;
546
547 uint16_t IsVolatile : 1;
548 uint16_t IsNonTemporal : 1;
549 uint16_t IsDereferenceable : 1;
550 uint16_t IsInvariant : 1;
551 };
552 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
553
554 class LSBaseSDNodeBitfields {
555 friend class LSBaseSDNode;
556 friend class MaskedLoadStoreSDNode;
557 friend class MaskedGatherScatterSDNode;
558
559 uint16_t : NumMemSDNodeBits;
560
561 // This storage is shared between disparate class hierarchies to hold an
562 // enumeration specific to the class hierarchy in use.
563 // LSBaseSDNode => enum ISD::MemIndexedMode
564 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
565 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
566 uint16_t AddressingMode : 3;
567 };
568 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
569
570 class LoadSDNodeBitfields {
571 friend class LoadSDNode;
572 friend class MaskedLoadSDNode;
573
574 uint16_t : NumLSBaseSDNodeBits;
575
576 uint16_t ExtTy : 2; // enum ISD::LoadExtType
577 uint16_t IsExpanding : 1;
578 };
579
580 class StoreSDNodeBitfields {
581 friend class StoreSDNode;
582 friend class MaskedStoreSDNode;
583
584 uint16_t : NumLSBaseSDNodeBits;
585
586 uint16_t IsTruncating : 1;
587 uint16_t IsCompressing : 1;
588 };
589
590 union {
591 char RawSDNodeBits[sizeof(uint16_t)];
592 SDNodeBitfields SDNodeBits;
593 ConstantSDNodeBitfields ConstantSDNodeBits;
594 MemSDNodeBitfields MemSDNodeBits;
595 LSBaseSDNodeBitfields LSBaseSDNodeBits;
596 LoadSDNodeBitfields LoadSDNodeBits;
597 StoreSDNodeBitfields StoreSDNodeBits;
598 };
599END_TWO_BYTE_PACK()
600#undef BEGIN_TWO_BYTE_PACK
601#undef END_TWO_BYTE_PACK
602
603 // RawSDNodeBits must cover the entirety of the union. This means that all of
604 // the union's members must have size <= RawSDNodeBits. We write the RHS as
605 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
606 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
607 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
608 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
609 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
610 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
611 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
612
613private:
614 friend class SelectionDAG;
615 // TODO: unfriend HandleSDNode once we fix its operand handling.
616 friend class HandleSDNode;
617
618 /// Unique id per SDNode in the DAG.
619 int NodeId = -1;
620
621 /// The values that are used by this operation.
622 SDUse *OperandList = nullptr;
623
624 /// The types of the values this node defines. SDNode's may
625 /// define multiple values simultaneously.
626 const EVT *ValueList;
627
628 /// List of uses for this SDNode.
629 SDUse *UseList = nullptr;
630
631 /// The number of entries in the Operand/Value list.
632 unsigned short NumOperands = 0;
633 unsigned short NumValues;
634
635 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
636 // original LLVM instructions.
637 // This is used for turning off scheduling, because we'll forgo
638 // the normal scheduling algorithms and output the instructions according to
639 // this ordering.
640 unsigned IROrder;
641
642 /// Source line information.
643 DebugLoc debugLoc;
644
645 /// Return a pointer to the specified value type.
646 static const EVT *getValueTypeList(EVT VT);
647
648 SDNodeFlags Flags;
649
650public:
651 /// Unique and persistent id per SDNode in the DAG.
652 /// Used for debug printing.
653 uint16_t PersistentId;
654
655 //===--------------------------------------------------------------------===//
656 // Accessors
657 //
658
659 /// Return the SelectionDAG opcode value for this node. For
660 /// pre-isel nodes (those for which isMachineOpcode returns false), these
661 /// are the opcode values in the ISD and <target>ISD namespaces. For
662 /// post-isel opcodes, see getMachineOpcode.
663 unsigned getOpcode() const { return (unsigned short)NodeType; }
664
665 /// Test if this node has a target-specific opcode (in the
666 /// \<target\>ISD namespace).
667 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
668
669 /// Test if this node has a target-specific opcode that may raise
670 /// FP exceptions (in the \<target\>ISD namespace and greater than
671 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
672 /// opcode are currently automatically considered to possibly raise
673 /// FP exceptions as well.
674 bool isTargetStrictFPOpcode() const {
675 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
676 }
677
678 /// Test if this node has a target-specific
679 /// memory-referencing opcode (in the \<target\>ISD namespace and
680 /// greater than FIRST_TARGET_MEMORY_OPCODE).
681 bool isTargetMemoryOpcode() const {
682 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
683 }
684
685 /// Return true if the type of the node type undefined.
686 bool isUndef() const { return NodeType == ISD::UNDEF; }
687
688 /// Test if this node is a memory intrinsic (with valid pointer information).
689 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
690 /// non-memory intrinsics (with chains) that are not really instances of
691 /// MemSDNode. For such nodes, we need some extra state to determine the
692 /// proper classof relationship.
693 bool isMemIntrinsic() const {
694 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
695 NodeType == ISD::INTRINSIC_VOID) &&
696 SDNodeBits.IsMemIntrinsic;
697 }
698
699 /// Test if this node is a strict floating point pseudo-op.
700 bool isStrictFPOpcode() {
701 switch (NodeType) {
702 default:
703 return false;
704#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
705 case ISD::STRICT_##DAGN:
706#include "llvm/IR/ConstrainedOps.def"
707 return true;
708 }
709 }
710
711 /// Test if this node has a post-isel opcode, directly
712 /// corresponding to a MachineInstr opcode.
713 bool isMachineOpcode() const { return NodeType < 0; }
714
715 /// This may only be called if isMachineOpcode returns
716 /// true. It returns the MachineInstr opcode value that the node's opcode
717 /// corresponds to.
718 unsigned getMachineOpcode() const {
719 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 719, __PRETTY_FUNCTION__))
;
720 return ~NodeType;
721 }
722
723 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
724 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
725
726 bool isDivergent() const { return SDNodeBits.IsDivergent; }
727
728 /// Return true if there are no uses of this node.
729 bool use_empty() const { return UseList == nullptr; }
730
731 /// Return true if there is exactly one use of this node.
732 bool hasOneUse() const {
733 return !use_empty() && std::next(use_begin()) == use_end();
734 }
735
736 /// Return the number of uses of this node. This method takes
737 /// time proportional to the number of uses.
738 size_t use_size() const { return std::distance(use_begin(), use_end()); }
739
740 /// Return the unique node id.
741 int getNodeId() const { return NodeId; }
742
743 /// Set unique node id.
744 void setNodeId(int Id) { NodeId = Id; }
745
746 /// Return the node ordering.
747 unsigned getIROrder() const { return IROrder; }
748
749 /// Set the node ordering.
750 void setIROrder(unsigned Order) { IROrder = Order; }
751
752 /// Return the source location info.
753 const DebugLoc &getDebugLoc() const { return debugLoc; }
754
755 /// Set source location info. Try to avoid this, putting
756 /// it in the constructor is preferable.
757 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
758
759 /// This class provides iterator support for SDUse
760 /// operands that use a specific SDNode.
761 class use_iterator
762 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
763 friend class SDNode;
764
765 SDUse *Op = nullptr;
766
767 explicit use_iterator(SDUse *op) : Op(op) {}
768
769 public:
770 using reference = std::iterator<std::forward_iterator_tag,
771 SDUse, ptrdiff_t>::reference;
772 using pointer = std::iterator<std::forward_iterator_tag,
773 SDUse, ptrdiff_t>::pointer;
774
775 use_iterator() = default;
776 use_iterator(const use_iterator &I) : Op(I.Op) {}
777
778 bool operator==(const use_iterator &x) const {
779 return Op == x.Op;
780 }
781 bool operator!=(const use_iterator &x) const {
782 return !operator==(x);
783 }
784
785 /// Return true if this iterator is at the end of uses list.
786 bool atEnd() const { return Op == nullptr; }
787
788 // Iterator traversal: forward iteration only.
789 use_iterator &operator++() { // Preincrement
790 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 790, __PRETTY_FUNCTION__))
;
791 Op = Op->getNext();
792 return *this;
793 }
794
795 use_iterator operator++(int) { // Postincrement
796 use_iterator tmp = *this; ++*this; return tmp;
797 }
798
799 /// Retrieve a pointer to the current user node.
800 SDNode *operator*() const {
801 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 801, __PRETTY_FUNCTION__))
;
802 return Op->getUser();
803 }
804
805 SDNode *operator->() const { return operator*(); }
806
807 SDUse &getUse() const { return *Op; }
808
809 /// Retrieve the operand # of this use in its user.
810 unsigned getOperandNo() const {
811 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 811, __PRETTY_FUNCTION__))
;
812 return (unsigned)(Op - Op->getUser()->OperandList);
813 }
814 };
815
816 /// Provide iteration support to walk over all uses of an SDNode.
817 use_iterator use_begin() const {
818 return use_iterator(UseList);
819 }
820
821 static use_iterator use_end() { return use_iterator(nullptr); }
822
823 inline iterator_range<use_iterator> uses() {
824 return make_range(use_begin(), use_end());
825 }
826 inline iterator_range<use_iterator> uses() const {
827 return make_range(use_begin(), use_end());
828 }
829
830 /// Return true if there are exactly NUSES uses of the indicated value.
831 /// This method ignores uses of other values defined by this operation.
832 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
833
834 /// Return true if there are any use of the indicated value.
835 /// This method ignores uses of other values defined by this operation.
836 bool hasAnyUseOfValue(unsigned Value) const;
837
838 /// Return true if this node is the only use of N.
839 bool isOnlyUserOf(const SDNode *N) const;
840
841 /// Return true if this node is an operand of N.
842 bool isOperandOf(const SDNode *N) const;
843
844 /// Return true if this node is a predecessor of N.
845 /// NOTE: Implemented on top of hasPredecessor and every bit as
846 /// expensive. Use carefully.
847 bool isPredecessorOf(const SDNode *N) const {
848 return N->hasPredecessor(this);
849 }
850
851 /// Return true if N is a predecessor of this node.
852 /// N is either an operand of this node, or can be reached by recursively
853 /// traversing up the operands.
854 /// NOTE: This is an expensive method. Use it carefully.
855 bool hasPredecessor(const SDNode *N) const;
856
857 /// Returns true if N is a predecessor of any node in Worklist. This
858 /// helper keeps Visited and Worklist sets externally to allow unions
859 /// searches to be performed in parallel, caching of results across
860 /// queries and incremental addition to Worklist. Stops early if N is
861 /// found but will resume. Remember to clear Visited and Worklists
862 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
863 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
864 /// topologically ordered (Operands have strictly smaller node id) and search
865 /// can be pruned leveraging this.
866 static bool hasPredecessorHelper(const SDNode *N,
867 SmallPtrSetImpl<const SDNode *> &Visited,
868 SmallVectorImpl<const SDNode *> &Worklist,
869 unsigned int MaxSteps = 0,
870 bool TopologicalPrune = false) {
871 SmallVector<const SDNode *, 8> DeferredNodes;
872 if (Visited.count(N))
873 return true;
874
875 // Node Id's are assigned in three places: As a topological
876 // ordering (> 0), during legalization (results in values set to
877 // 0), new nodes (set to -1). If N has a topolgical id then we
878 // know that all nodes with ids smaller than it cannot be
879 // successors and we need not check them. Filter out all node
880 // that can't be matches. We add them to the worklist before exit
881 // in case of multiple calls. Note that during selection the topological id
882 // may be violated if a node's predecessor is selected before it. We mark
883 // this at selection negating the id of unselected successors and
884 // restricting topological pruning to positive ids.
885
886 int NId = N->getNodeId();
887 // If we Invalidated the Id, reconstruct original NId.
888 if (NId < -1)
889 NId = -(NId + 1);
890
891 bool Found = false;
892 while (!Worklist.empty()) {
893 const SDNode *M = Worklist.pop_back_val();
894 int MId = M->getNodeId();
895 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
896 (MId > 0) && (MId < NId)) {
897 DeferredNodes.push_back(M);
898 continue;
899 }
900 for (const SDValue &OpV : M->op_values()) {
901 SDNode *Op = OpV.getNode();
902 if (Visited.insert(Op).second)
903 Worklist.push_back(Op);
904 if (Op == N)
905 Found = true;
906 }
907 if (Found)
908 break;
909 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
910 break;
911 }
912 // Push deferred nodes back on worklist.
913 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
914 // If we bailed early, conservatively return found.
915 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
916 return true;
917 return Found;
918 }
919
920 /// Return true if all the users of N are contained in Nodes.
921 /// NOTE: Requires at least one match, but doesn't require them all.
922 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
923
924 /// Return the number of values used by this operation.
925 unsigned getNumOperands() const { return NumOperands; }
926
927 /// Return the maximum number of operands that a SDNode can hold.
928 static constexpr size_t getMaxNumOperands() {
929 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
930 }
931
932 /// Helper method returns the integer value of a ConstantSDNode operand.
933 inline uint64_t getConstantOperandVal(unsigned Num) const;
934
935 /// Helper method returns the APInt of a ConstantSDNode operand.
936 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
937
938 const SDValue &getOperand(unsigned Num) const {
939 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 939, __PRETTY_FUNCTION__))
;
940 return OperandList[Num];
941 }
942
943 using op_iterator = SDUse *;
944
945 op_iterator op_begin() const { return OperandList; }
946 op_iterator op_end() const { return OperandList+NumOperands; }
947 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
948
949 /// Iterator for directly iterating over the operand SDValue's.
950 struct value_op_iterator
951 : iterator_adaptor_base<value_op_iterator, op_iterator,
952 std::random_access_iterator_tag, SDValue,
953 ptrdiff_t, value_op_iterator *,
954 value_op_iterator *> {
955 explicit value_op_iterator(SDUse *U = nullptr)
956 : iterator_adaptor_base(U) {}
957
958 const SDValue &operator*() const { return I->get(); }
959 };
960
961 iterator_range<value_op_iterator> op_values() const {
962 return make_range(value_op_iterator(op_begin()),
963 value_op_iterator(op_end()));
964 }
965
966 SDVTList getVTList() const {
967 SDVTList X = { ValueList, NumValues };
968 return X;
969 }
970