/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h

Bug Summary

File:	llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
Warning:	line 88, column 17 The result of the right shift is undefined due to shifting by '32', which is greater or equal to the width of type 'unsigned int'

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMAsmBackend.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/ARM/MCTargetDesc -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/ARM/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/ARM/MCTargetDesc -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

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1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//

9#include "MCTargetDesc/ARMAsmBackend.h"
10#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMAsmBackendDarwin.h"
12#include "MCTargetDesc/ARMAsmBackendELF.h"
13#include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
14#include "MCTargetDesc/ARMFixupKinds.h"
15#include "MCTargetDesc/ARMMCTargetDesc.h"
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/BinaryFormat/MachO.h"
19#include "llvm/MC/MCAsmBackend.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCDirectives.h"
23#include "llvm/MC/MCELFObjectWriter.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCFixupKindInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSectionELF.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/MC/MCSubtargetInfo.h"
31#include "llvm/MC/MCValue.h"
32#include "llvm/MC/MCAsmLayout.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/EndianStream.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/Format.h"
37#include "llvm/Support/TargetParser.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;

41namespace {
42class ARMELFObjectWriter : public MCELFObjectTargetWriter {
43public:
ARMELFObjectWriter(uint8_t OSABI)
    : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
                              /*HasRelocationAddend*/ false) {}
47};
48} // end anonymous namespace

50Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
if (!STI.getTargetTriple().isOSBinFormatELF())
  return None;

unsigned Type = llvm::StringSwitch<unsigned>(Name)
55#define ELF_RELOC(X, Y) .Case(#X, Y)
56#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
57#undef ELF_RELOC
                    .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
                    .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
                    .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
                    .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
                    .Default(-1u);
if (Type == -1u)
  return None;
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
66}

68const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
unsigned IsPCRelConstant =
    MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant;
const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
    // This table *must* be in the order that the fixup_* kinds are defined in
    // ARMFixupKinds.h.
    //
    // Name                      Offset (bits) Size (bits)     Flags
    {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
    {"fixup_t2_ldst_pcrel_12", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
    {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
    {"fixup_t2_pcrel_10", 0, 32,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_pcrel_9", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_ldst_abs_12", 0, 32, 0},
    {"fixup_thumb_adr_pcrel_10", 0, 8,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
    {"fixup_t2_adr_pcrel_12", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_blx", 0, 32,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_cp", 0, 8,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
    // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
    // - 19.
    {"fixup_arm_movt_hi16", 0, 20, 0},
    {"fixup_arm_movw_lo16", 0, 20, 0},
    {"fixup_t2_movt_hi16", 0, 20, 0},
    {"fixup_t2_movw_lo16", 0, 20, 0},
    {"fixup_arm_mod_imm", 0, 12, 0},
    {"fixup_t2_so_imm", 0, 26, 0},
    {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfcsel_else_target", 0, 32, 0},
    {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
    // This table *must* be in the order that the fixup_* kinds are defined in
    // ARMFixupKinds.h.
    //
    // Name                      Offset (bits) Size (bits)     Flags
    {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
    {"fixup_t2_ldst_pcrel_12", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
    {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
    {"fixup_t2_pcrel_10", 0, 32,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_pcrel_9", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_ldst_abs_12", 0, 32, 0},
    {"fixup_thumb_adr_pcrel_10", 8, 8,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
    {"fixup_t2_adr_pcrel_12", 0, 32,
     IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_blx", 0, 32,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_arm_thumb_cp", 8, 8,
     MCFixupKindInfo::FKF_IsPCRel |
         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
    {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
    // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
    // - 19.
    {"fixup_arm_movt_hi16", 12, 20, 0},
    {"fixup_arm_movw_lo16", 12, 20, 0},
    {"fixup_t2_movt_hi16", 12, 20, 0},
    {"fixup_t2_movw_lo16", 12, 20, 0},
    {"fixup_arm_mod_imm", 20, 12, 0},
    {"fixup_t2_so_imm", 26, 6, 0},
    {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_bfcsel_else_target", 0, 32, 0},
    {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
    {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};

// Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
// any extra processing.
if (Kind >= FirstLiteralRelocationKind)
  return MCAsmBackend::getFixupKindInfo(FK_NONE);

if (Kind < FirstTargetFixupKind)
  return MCAsmBackend::getFixupKindInfo(Kind);

assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&(static_cast<void> (0))
       "Invalid kind!")(static_cast<void> (0));
return (Endian == support::little ? InfosLE
                                  : InfosBE)[Kind - FirstTargetFixupKind];
192}

194void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
switch (Flag) {
default:
  break;
case MCAF_Code16:
  setIsThumb(true);
  break;
case MCAF_Code32:
  setIsThumb(false);
  break;
}
205}

207unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op,
                                       const MCSubtargetInfo &STI) const {
bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];

switch (Op) {
default:
  return Op;
case ARM::tBcc:
  return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
case ARM::tLDRpci:
  return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
case ARM::tADR:
  return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
case ARM::tB:
  return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
case ARM::tCBZ:
  return ARM::tHINT;
case ARM::tCBNZ:
  return ARM::tHINT;
}
228}

230bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                    const MCSubtargetInfo &STI) const {
if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
  return true;
return false;
235}

237static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
int64_t Offset = int64_t(Value) - 4;
if (Offset < Min || Offset > Max)
  return "out of range pc-relative fixup value";
return nullptr;
242}

244const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
                                                  uint64_t Value) const {
switch (Fixup.getTargetKind()) {
case ARM::fixup_arm_thumb_br: {
  // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
  // low bit being an implied zero. There's an implied +4 offset for the
  // branch, so we adjust the other way here to determine what's
  // encodable.
  //
  // Relax if the value is too big for a (signed) i8.
  int64_t Offset = int64_t(Value) - 4;
  if (Offset > 2046 || Offset < -2048)
    return "out of range pc-relative fixup value";
  break;
}
case ARM::fixup_arm_thumb_bcc: {
  // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
  // low bit being an implied zero. There's an implied +4 offset for the
  // branch, so we adjust the other way here to determine what's
  // encodable.
  //
  // Relax if the value is too big for a (signed) i8.
  int64_t Offset = int64_t(Value) - 4;
  if (Offset > 254 || Offset < -256)
    return "out of range pc-relative fixup value";
  break;
}
case ARM::fixup_thumb_adr_pcrel_10:
case ARM::fixup_arm_thumb_cp: {
  // If the immediate is negative, greater than 1020, or not a multiple
  // of four, the wide version of the instruction must be used.
  int64_t Offset = int64_t(Value) - 4;
  if (Offset & 3)
    return "misaligned pc-relative fixup value";
  else if (Offset > 1020 || Offset < 0)
    return "out of range pc-relative fixup value";
  break;
}
case ARM::fixup_arm_thumb_cb: {
  // If we have a Thumb CBZ or CBNZ instruction and its target is the next
  // instruction it is actually out of range for the instruction.
  // It will be changed to a NOP.
  int64_t Offset = (Value & ~1);
  if (Offset == 2)
    return "will be converted to nop";
  break;
}
case ARM::fixup_bf_branch:
  return checkPCRelOffset(Value, 0, 30);
case ARM::fixup_bf_target:
  return checkPCRelOffset(Value, -0x10000, +0xfffe);
case ARM::fixup_bfl_target:
  return checkPCRelOffset(Value, -0x40000, +0x3fffe);
case ARM::fixup_bfc_target:
  return checkPCRelOffset(Value, -0x1000, +0xffe);
case ARM::fixup_wls:
  return checkPCRelOffset(Value, 0, +0xffe);
case ARM::fixup_le:
  // The offset field in the LE and LETP instructions is an 11-bit
  // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
  // interpreted as a negative offset from the value read from pc,
  // i.e. from instruction_address+4.
  //
  // So an LE instruction can in principle address the instruction
  // immediately after itself, or (not very usefully) the address
  // half way through the 4-byte LE.
  return checkPCRelOffset(Value, -0xffe, 0);
case ARM::fixup_bfcsel_else_target: {
  if (Value != 2 && Value != 4)
    return "out of range label-relative fixup value";
  break;
}

default:
  llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!")__builtin_unreachable();
}
return nullptr;
321}

323bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                       const MCRelaxableFragment *DF,
                                       const MCAsmLayout &Layout) const {
return reasonForFixupRelaxation(Fixup, Value);
327}

329void ARMAsmBackend::relaxInstruction(MCInst &Inst,
                                   const MCSubtargetInfo &STI) const {
unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);

// Sanity check w/ diagnostic if we get here w/ a bogus instruction.
if (RelaxedOp == Inst.getOpcode()) {
  SmallString<256> Tmp;
  raw_svector_ostream OS(Tmp);
  Inst.dump_pretty(OS);
  OS << "\n";
  report_fatal_error("unexpected instruction to relax: " + OS.str());
}

// If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
// have to change the operands too.
if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
    RelaxedOp == ARM::tHINT) {
  MCInst Res;
  Res.setOpcode(RelaxedOp);
  Res.addOperand(MCOperand::createImm(0));
  Res.addOperand(MCOperand::createImm(14));
  Res.addOperand(MCOperand::createReg(0));
  Inst = std::move(Res);
  return;
}

// The rest of instructions we're relaxing have the same operands.
// We just need to update to the proper opcode.
Inst.setOpcode(RelaxedOp);
358}

360bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
if (isThumb()) {
  const uint16_t nopEncoding =
      hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
  uint64_t NumNops = Count / 2;
  for (uint64_t i = 0; i != NumNops; ++i)
    support::endian::write(OS, nopEncoding, Endian);
  if (Count & 1)
    OS << '\0';
  return true;
}
// ARM mode
const uint32_t nopEncoding =
    hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
  support::endian::write(OS, nopEncoding, Endian);
// FIXME: should this function return false when unable to write exactly
// 'Count' bytes with NOP encodings?
switch (Count % 4) {
default:
  break; // No leftover bytes to write
case 1:
  OS << '\0';
  break;
case 2:
  OS.write("\0\0", 2);
  break;
case 3:
  OS.write("\0\0\xa0", 3);
  break;
}

return true;
398}

400static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
if (IsLittleEndian) {
  // Note that the halfwords are stored high first and low second in thumb;
  // so we need to swap the fixup value here to map properly.
  uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
  Swapped |= (Value & 0x0000FFFF) << 16;
  return Swapped;
} else
  return Value;
409}

411static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
                            bool IsLittleEndian) {
uint32_t Value;

if (IsLittleEndian) {
  Value = (SecondHalf & 0xFFFF) << 16;
  Value |= (FirstHalf & 0xFFFF);
} else {
  Value = (SecondHalf & 0xFFFF);
  Value |= (FirstHalf & 0xFFFF) << 16;
}

return Value;
424}

426unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
                                       const MCFixup &Fixup,
                                       const MCValue &Target, uint64_t Value,
                                       bool IsResolved, MCContext &Ctx,
                                       const MCSubtargetInfo* STI) const {
unsigned Kind = Fixup.getKind();

// MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
// and .word relocations they put the Thumb bit into the addend if possible.
// Other relocation types don't want this bit though (branches couldn't encode
// it if it *was* present, and no other relocations exist) and it can
// interfere with checking valid expressions.
if (const MCSymbolRefExpr *A = Target.getSymA()) {
1
Assuming 'A' is null→
2
←
Taking false branch→
  if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
      A->getSymbol().isExternal() &&
      (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
       Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 ||
       Kind == ARM::fixup_t2_movt_hi16))
    Value |= 1;
}

switch (Kind) {
3
←
Control jumps to 'case fixup_arm_mod_imm:'  at line 798→
default:
  Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
  return 0;
case FK_Data_1:
case FK_Data_2:
case FK_Data_4:
  return Value;
case FK_SecRel_2:
  return Value;
case FK_SecRel_4:
  return Value;
case ARM::fixup_arm_movt_hi16:
  assert(STI != nullptr)(static_cast<void> (0));
  if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
    Value >>= 16;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_arm_movw_lo16: {
  unsigned Hi4 = (Value & 0xF000) >> 12;
  unsigned Lo12 = Value & 0x0FFF;
  // inst{19-16} = Hi4;
  // inst{11-0} = Lo12;
  Value = (Hi4 << 16) | (Lo12);
  return Value;
}
case ARM::fixup_t2_movt_hi16:
  assert(STI != nullptr)(static_cast<void> (0));
  if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
    Value >>= 16;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_t2_movw_lo16: {
  unsigned Hi4 = (Value & 0xF000) >> 12;
  unsigned i = (Value & 0x800) >> 11;
  unsigned Mid3 = (Value & 0x700) >> 8;
  unsigned Lo8 = Value & 0x0FF;
  // inst{19-16} = Hi4;
  // inst{26} = i;
  // inst{14-12} = Mid3;
  // inst{7-0} = Lo8;
  Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
  return swapHalfWords(Value, Endian == support::little);
}
case ARM::fixup_arm_ldst_pcrel_12:
  // ARM PC-relative values are offset by 8.
  Value -= 4;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_t2_ldst_pcrel_12:
  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
  Value -= 4;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_arm_ldst_abs_12: {
  bool isAdd = true;
  if ((int64_t)Value < 0) {
    Value = -Value;
    isAdd = false;
  }
  if (Value >= 4096) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  Value |= isAdd << 23;

  // Same addressing mode as fixup_arm_pcrel_10,
  // but with 16-bit halfwords swapped.
  if (Kind == ARM::fixup_t2_ldst_pcrel_12)
    return swapHalfWords(Value, Endian == support::little);

  return Value;
}
case ARM::fixup_arm_adr_pcrel_12: {
  // ARM PC-relative values are offset by 8.
  Value -= 8;
  unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
  if ((int64_t)Value < 0) {
    Value = -Value;
    opc = 2; // 0b0010
  }
  if (ARM_AM::getSOImmVal(Value) == -1) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  // Encode the immediate and shift the opcode into place.
  return ARM_AM::getSOImmVal(Value) | (opc << 21);
}

case ARM::fixup_t2_adr_pcrel_12: {
  Value -= 4;
  unsigned opc = 0;
  if ((int64_t)Value < 0) {
    Value = -Value;
    opc = 5;
  }

  uint32_t out = (opc << 21);
  out |= (Value & 0x800) << 15;
  out |= (Value & 0x700) << 4;
  out |= (Value & 0x0FF);

  return swapHalfWords(out, Endian == support::little);
}

case ARM::fixup_arm_condbranch:
case ARM::fixup_arm_uncondbranch:
case ARM::fixup_arm_uncondbl:
case ARM::fixup_arm_condbl:
case ARM::fixup_arm_blx:
  // These values don't encode the low two bits since they're always zero.
  // Offset by 8 just as above.
  if (const MCSymbolRefExpr *SRE =
          dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
    if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
      return 0;
  return 0xffffff & ((Value - 8) >> 2);
case ARM::fixup_t2_uncondbranch: {
  Value = Value - 4;
  if (!isInt<25>(Value)) {
    Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
    return 0;
  }

  Value >>= 1; // Low bit is not encoded.

  uint32_t out = 0;
  bool I = Value & 0x800000;
  bool J1 = Value & 0x400000;
  bool J2 = Value & 0x200000;
  J1 ^= I;
  J2 ^= I;

  out |= I << 26;                 // S bit
  out |= !J1 << 13;               // J1 bit
  out |= !J2 << 11;               // J2 bit
  out |= (Value & 0x1FF800) << 5; // imm6 field
  out |= (Value & 0x0007FF);      // imm11 field

  return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_t2_condbranch: {
  Value = Value - 4;
  if (!isInt<21>(Value)) {
    Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
    return 0;
  }

  Value >>= 1; // Low bit is not encoded.

  uint64_t out = 0;
  out |= (Value & 0x80000) << 7; // S bit
  out |= (Value & 0x40000) >> 7; // J2 bit
  out |= (Value & 0x20000) >> 4; // J1 bit
  out |= (Value & 0x1F800) << 5; // imm6 field
  out |= (Value & 0x007FF);      // imm11 field

  return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_arm_thumb_bl: {
  if (!isInt<25>(Value - 4) ||
      (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
       !STI->getFeatureBits()[ARM::HasV8MBaselineOps] &&
       !STI->getFeatureBits()[ARM::HasV6MOps] &&
       !isInt<23>(Value - 4))) {
    Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
    return 0;
  }

  // The value doesn't encode the low bit (always zero) and is offset by
  // four. The 32-bit immediate value is encoded as
  //   imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
  // The value is encoded into disjoint bit positions in the destination
  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
  // J = either J1 or J2 bit
  //
  //   BL:  xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
  //
  // Note that the halfwords are stored high first, low second; so we need
  // to transpose the fixup value here to map properly.
  uint32_t offset = (Value - 4) >> 1;
  uint32_t signBit = (offset & 0x800000) >> 23;
  uint32_t I1Bit = (offset & 0x400000) >> 22;
  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
  uint32_t I2Bit = (offset & 0x200000) >> 21;
  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
  uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
  uint32_t imm11Bits = (offset & 0x000007FF);

  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
                         (uint16_t)imm11Bits);
  return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
}
case ARM::fixup_arm_thumb_blx: {
  // The value doesn't encode the low two bits (always zero) and is offset by
  // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
  //   imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
  // The value is encoded into disjoint bit positions in the destination
  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
  // J = either J1 or J2 bit, 0 = zero.
  //
  //   BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
  //
  // Note that the halfwords are stored high first, low second; so we need
  // to transpose the fixup value here to map properly.
  if (Value % 4 != 0) {
    Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
    return 0;
  }

  uint32_t offset = (Value - 4) >> 2;
  if (const MCSymbolRefExpr *SRE =
          dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
    if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
      offset = 0;
  uint32_t signBit = (offset & 0x400000) >> 22;
  uint32_t I1Bit = (offset & 0x200000) >> 21;
  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
  uint32_t I2Bit = (offset & 0x100000) >> 20;
  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
  uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
  uint32_t imm10LBits = (offset & 0x3FF);

  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
                         ((uint16_t)imm10LBits) << 1);
  return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
}
case ARM::fixup_thumb_adr_pcrel_10:
case ARM::fixup_arm_thumb_cp:
  // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
  // could have an error on our hands.
  assert(STI != nullptr)(static_cast<void> (0));
  if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
    if (FixupDiagnostic) {
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
      return 0;
    }
  }
  // Offset by 4, and don't encode the low two bits.
  return ((Value - 4) >> 2) & 0xff;
case ARM::fixup_arm_thumb_cb: {
  // CB instructions can only branch to offsets in [4, 126] in multiples of 2
  // so ensure that the raw value LSB is zero and it lies in [2, 130].
  // An offset of 2 will be relaxed to a NOP.
  if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  // Offset by 4 and don't encode the lower bit, which is always 0.
  // FIXME: diagnose if no Thumb2
  uint32_t Binary = (Value - 4) >> 1;
  return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
}
case ARM::fixup_arm_thumb_br:
  // Offset by 4 and don't encode the lower bit, which is always 0.
  assert(STI != nullptr)(static_cast<void> (0));
  if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
      !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
    if (FixupDiagnostic) {
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
      return 0;
    }
  }
  return ((Value - 4) >> 1) & 0x7ff;
case ARM::fixup_arm_thumb_bcc:
  // Offset by 4 and don't encode the lower bit, which is always 0.
  assert(STI != nullptr)(static_cast<void> (0));
  if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
    if (FixupDiagnostic) {
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
      return 0;
    }
  }
  return ((Value - 4) >> 1) & 0xff;
case ARM::fixup_arm_pcrel_10_unscaled: {
  Value = Value - 8; // ARM fixups offset by an additional word and don't
                     // need to adjust for the half-word ordering.
  bool isAdd = true;
  if ((int64_t)Value < 0) {
    Value = -Value;
    isAdd = false;
  }
  // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
  if (Value >= 256) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  Value = (Value & 0xf) | ((Value & 0xf0) << 4);
  return Value | (isAdd << 23);
}
case ARM::fixup_arm_pcrel_10:
  Value = Value - 4; // ARM fixups offset by an additional word and don't
                     // need to adjust for the half-word ordering.
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_t2_pcrel_10: {
  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
  Value = Value - 4;
  bool isAdd = true;
  if ((int64_t)Value < 0) {
    Value = -Value;
    isAdd = false;
  }
  // These values don't encode the low two bits since they're always zero.
  Value >>= 2;
  if (Value >= 256) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  Value |= isAdd << 23;

  // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
  // swapped.
  if (Kind == ARM::fixup_t2_pcrel_10)
    return swapHalfWords(Value, Endian == support::little);

  return Value;
}
case ARM::fixup_arm_pcrel_9:
  Value = Value - 4; // ARM fixups offset by an additional word and don't
                     // need to adjust for the half-word ordering.
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ARM::fixup_t2_pcrel_9: {
  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
  Value = Value - 4;
  bool isAdd = true;
  if ((int64_t)Value < 0) {
    Value = -Value;
    isAdd = false;
  }
  // These values don't encode the low bit since it's always zero.
  if (Value & 1) {
    Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
    return 0;
  }
  Value >>= 1;
  if (Value >= 256) {
    Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
    return 0;
  }
  Value |= isAdd << 23;

  // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
  // swapped.
  if (Kind == ARM::fixup_t2_pcrel_9)
    return swapHalfWords(Value, Endian == support::little);

  return Value;
}
case ARM::fixup_arm_mod_imm:
  Value = ARM_AM::getSOImmVal(Value);
4
←
Calling 'getSOImmVal'→
  if (Value >> 12) {
    Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
    return 0;
  }
  return Value;
case ARM::fixup_t2_so_imm: {
  Value = ARM_AM::getT2SOImmVal(Value);
  if ((int64_t)Value < 0) {
    Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
    return 0;
  }
  // Value will contain a 12-bit value broken up into a 4-bit shift in bits
  // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
  // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
  // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
  // half-word.
  uint64_t EncValue = 0;
  EncValue |= (Value & 0x800) << 15;
  EncValue |= (Value & 0x700) << 4;
  EncValue |= (Value & 0xff);
  return swapHalfWords(EncValue, Endian == support::little);
}
case ARM::fixup_bf_branch: {
  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
  if (FixupDiagnostic) {
    Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
    return 0;
  }
  uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
  return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_bf_target:
case ARM::fixup_bfl_target:
case ARM::fixup_bfc_target: {
  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
  if (FixupDiagnostic) {
    Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
    return 0;
  }
  uint32_t out = 0;
  uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
                          Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
  out |= (((Value - 4) >> 1) & 0x1) << 11;
  out |= (((Value - 4) >> 1) & 0x7fe);
  out |= (((Value - 4) >> 1) & HighBitMask) << 5;
  return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_bfcsel_else_target: {
  // If this is a fixup of a branch future's else target then it should be a
  // constant MCExpr representing the distance between the branch targetted
  // and the instruction after that same branch.
  Value = Target.getConstant();

  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
  if (FixupDiagnostic) {
    Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
    return 0;
  }
  uint32_t out = ((Value >> 2) & 1) << 17;
  return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_wls:
case ARM::fixup_le: {
  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
  if (FixupDiagnostic) {
    Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
    return 0;
  }
  uint64_t real_value = Value - 4;
  uint32_t out = 0;
  if (Kind == ARM::fixup_le)
    real_value = -real_value;
  out |= ((real_value >> 1) & 0x1) << 11;
  out |= ((real_value >> 1) & 0x7fe);
  return swapHalfWords(out, Endian == support::little);
}
}
877}

879bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                        const MCFixup &Fixup,
                                        const MCValue &Target) {
const MCSymbolRefExpr *A = Target.getSymA();
const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
const unsigned FixupKind = Fixup.getKind();
if (FixupKind >= FirstLiteralRelocationKind)
  return true;
if (FixupKind == ARM::fixup_arm_thumb_bl) {
  assert(Sym && "How did we resolve this?")(static_cast<void> (0));

  // If the symbol is external the linker will handle it.
  // FIXME: Should we handle it as an optimization?

  // If the symbol is out of range, produce a relocation and hope the
  // linker can handle it. GNU AS produces an error in this case.
  if (Sym->isExternal())
    return true;
}
// Create relocations for unconditional branches to function symbols with
// different execution mode in ELF binaries.
if (Sym && Sym->isELF()) {
  unsigned Type = cast<MCSymbolELF>(Sym)->getType();
  if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
    if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
      return true;
    if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
                                  FixupKind == ARM::fixup_arm_thumb_bl ||
                                  FixupKind == ARM::fixup_t2_condbranch ||
                                  FixupKind == ARM::fixup_t2_uncondbranch))
      return true;
  }
}
// We must always generate a relocation for BL/BLX instructions if we have
// a symbol to reference, as the linker relies on knowing the destination
// symbol's thumb-ness to get interworking right.
if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
          FixupKind == ARM::fixup_arm_blx ||
          FixupKind == ARM::fixup_arm_uncondbl ||
          FixupKind == ARM::fixup_arm_condbl))
  return true;
return false;
921}

923/// getFixupKindNumBytes - The number of bytes the fixup may change.
924static unsigned getFixupKindNumBytes(unsigned Kind) {
switch (Kind) {
default:
  llvm_unreachable("Unknown fixup kind!")__builtin_unreachable();

case FK_Data_1:
case ARM::fixup_arm_thumb_bcc:
case ARM::fixup_arm_thumb_cp:
case ARM::fixup_thumb_adr_pcrel_10:
  return 1;

case FK_Data_2:
case ARM::fixup_arm_thumb_br:
case ARM::fixup_arm_thumb_cb:
case ARM::fixup_arm_mod_imm:
  return 2;

case ARM::fixup_arm_pcrel_10_unscaled:
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_pcrel_9:
case ARM::fixup_arm_ldst_abs_12:
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_uncondbl:
case ARM::fixup_arm_condbl:
case ARM::fixup_arm_blx:
case ARM::fixup_arm_condbranch:
case ARM::fixup_arm_uncondbranch:
  return 3;

case FK_Data_4:
case ARM::fixup_t2_ldst_pcrel_12:
case ARM::fixup_t2_condbranch:
case ARM::fixup_t2_uncondbranch:
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_t2_pcrel_9:
case ARM::fixup_t2_adr_pcrel_12:
case ARM::fixup_arm_thumb_bl:
case ARM::fixup_arm_thumb_blx:
case ARM::fixup_arm_movt_hi16:
case ARM::fixup_arm_movw_lo16:
case ARM::fixup_t2_movt_hi16:
case ARM::fixup_t2_movw_lo16:
case ARM::fixup_t2_so_imm:
case ARM::fixup_bf_branch:
case ARM::fixup_bf_target:
case ARM::fixup_bfl_target:
case ARM::fixup_bfc_target:
case ARM::fixup_bfcsel_else_target:
case ARM::fixup_wls:
case ARM::fixup_le:
  return 4;

case FK_SecRel_2:
  return 2;
case FK_SecRel_4:
  return 4;
}
982}

984/// getFixupKindContainerSizeBytes - The number of bytes of the
985/// container involved in big endian.
986static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
switch (Kind) {
default:
  llvm_unreachable("Unknown fixup kind!")__builtin_unreachable();

case FK_Data_1:
  return 1;
case FK_Data_2:
  return 2;
case FK_Data_4:
  return 4;

case ARM::fixup_arm_thumb_bcc:
case ARM::fixup_arm_thumb_cp:
case ARM::fixup_thumb_adr_pcrel_10:
case ARM::fixup_arm_thumb_br:
case ARM::fixup_arm_thumb_cb:
  // Instruction size is 2 bytes.
  return 2;

case ARM::fixup_arm_pcrel_10_unscaled:
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_pcrel_9:
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_uncondbl:
case ARM::fixup_arm_condbl:
case ARM::fixup_arm_blx:
case ARM::fixup_arm_condbranch:
case ARM::fixup_arm_uncondbranch:
case ARM::fixup_t2_ldst_pcrel_12:
case ARM::fixup_t2_condbranch:
case ARM::fixup_t2_uncondbranch:
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_t2_pcrel_9:
case ARM::fixup_t2_adr_pcrel_12:
case ARM::fixup_arm_thumb_bl:
case ARM::fixup_arm_thumb_blx:
case ARM::fixup_arm_movt_hi16:
case ARM::fixup_arm_movw_lo16:
case ARM::fixup_t2_movt_hi16:
case ARM::fixup_t2_movw_lo16:
case ARM::fixup_arm_mod_imm:
case ARM::fixup_t2_so_imm:
case ARM::fixup_bf_branch:
case ARM::fixup_bf_target:
case ARM::fixup_bfl_target:
case ARM::fixup_bfc_target:
case ARM::fixup_bfcsel_else_target:
case ARM::fixup_wls:
case ARM::fixup_le:
  // Instruction size is 4 bytes.
  return 4;
}
1040}

1042void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                             const MCValue &Target,
                             MutableArrayRef<char> Data, uint64_t Value,
                             bool IsResolved,
                             const MCSubtargetInfo* STI) const {
unsigned Kind = Fixup.getKind();
if (Kind >= FirstLiteralRelocationKind)
  return;
unsigned NumBytes = getFixupKindNumBytes(Kind);
MCContext &Ctx = Asm.getContext();
Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
if (!Value)
  return; // Doesn't change encoding.

unsigned Offset = Fixup.getOffset();
assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!")(static_cast<void> (0));

// Used to point to big endian bytes.
unsigned FullSizeBytes;
if (Endian == support::big) {
  FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
  assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!")(static_cast<void> (0));
  assert(NumBytes <= FullSizeBytes && "Invalid fixup size!")(static_cast<void> (0));
}

// For each byte of the fragment that the fixup touches, mask in the bits from
// the fixup value. The Value has been "split up" into the appropriate
// bitfields above.
for (unsigned i = 0; i != NumBytes; ++i) {
  unsigned Idx = Endian == support::little ? i : (FullSizeBytes - 1 - i);
  Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
}
1074}

1076namespace CU {

1078/// Compact unwind encoding values.
1079enum CompactUnwindEncodings {
UNWIND_ARM_MODE_MASK                         = 0x0F000000,
UNWIND_ARM_MODE_FRAME                        = 0x01000000,
UNWIND_ARM_MODE_FRAME_D                      = 0x02000000,
UNWIND_ARM_MODE_DWARF                        = 0x04000000,

UNWIND_ARM_FRAME_STACK_ADJUST_MASK           = 0x00C00000,

UNWIND_ARM_FRAME_FIRST_PUSH_R4               = 0x00000001,
UNWIND_ARM_FRAME_FIRST_PUSH_R5               = 0x00000002,
UNWIND_ARM_FRAME_FIRST_PUSH_R6               = 0x00000004,

UNWIND_ARM_FRAME_SECOND_PUSH_R8              = 0x00000008,
UNWIND_ARM_FRAME_SECOND_PUSH_R9              = 0x00000010,
UNWIND_ARM_FRAME_SECOND_PUSH_R10             = 0x00000020,
UNWIND_ARM_FRAME_SECOND_PUSH_R11             = 0x00000040,
UNWIND_ARM_FRAME_SECOND_PUSH_R12             = 0x00000080,

UNWIND_ARM_FRAME_D_REG_COUNT_MASK            = 0x00000F00,

UNWIND_ARM_DWARF_SECTION_OFFSET              = 0x00FFFFFF
1100};

1102} // end CU namespace

1104/// Generate compact unwind encoding for the function based on the CFI
1105/// instructions. If the CFI instructions describe a frame that cannot be
1106/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1107/// tells the runtime to fallback and unwind using dwarf.
1108uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
  ArrayRef<MCCFIInstruction> Instrs) const {
DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n")do { } while (false);
// Only armv7k uses CFI based unwinding.
if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
  return 0;
// No .cfi directives means no frame.
if (Instrs.empty())
  return 0;
// Start off assuming CFA is at SP+0.
unsigned CFARegister = ARM::SP;
int CFARegisterOffset = 0;
// Mark savable registers as initially unsaved
DenseMap<unsigned, int> RegOffsets;
int FloatRegCount = 0;
// Process each .cfi directive and build up compact unwind info.
for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
  unsigned Reg;
  const MCCFIInstruction &Inst = Instrs[i];
  switch (Inst.getOperation()) {
  case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
    CFARegisterOffset = Inst.getOffset();
    CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
    break;
  case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
    CFARegisterOffset = Inst.getOffset();
    break;
  case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
    CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
    break;
  case MCCFIInstruction::OpOffset: // DW_CFA_offset
    Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
    if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
      RegOffsets[Reg] = Inst.getOffset();
    else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
      RegOffsets[Reg] = Inst.getOffset();
      ++FloatRegCount;
    } else {
      DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                      llvm::dbgs() << ".cfi_offset on unknown register="do { } while (false)
                                   << Inst.getRegister() << "\n")do { } while (false);
      return CU::UNWIND_ARM_MODE_DWARF;
    }
    break;
  case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
    // Ignore
    break;
  default:
    // Directive not convertable to compact unwind, bail out.
    DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                    llvm::dbgs()do { } while (false)
                        << "CFI directive not compatiable with comact "do { } while (false)
                           "unwind encoding, opcode=" << Inst.getOperation()do { } while (false)
                        << "\n")do { } while (false);
    return CU::UNWIND_ARM_MODE_DWARF;
    break;
  }
}

// If no frame set up, return no unwind info.
if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
  return 0;

// Verify standard frame (lr/r7) was used.
if (CFARegister != ARM::R7) {
  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "do { } while (false)
                                                 << CFARegisterdo { } while (false)
                                                 << " instead of r7\n")do { } while (false);
  return CU::UNWIND_ARM_MODE_DWARF;
}
int StackAdjust = CFARegisterOffset - 8;
if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
  DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                  llvm::dbgs()do { } while (false)
                      << "LR not saved as standard frame, StackAdjust="do { } while (false)
                      << StackAdjustdo { } while (false)
                      << ", CFARegisterOffset=" << CFARegisterOffsetdo { } while (false)
                      << ", lr save at offset=" << RegOffsets[14] << "\n")do { } while (false);
  return CU::UNWIND_ARM_MODE_DWARF;
}
if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
  DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                  llvm::dbgs() << "r7 not saved as standard frame\n")do { } while (false);
  return CU::UNWIND_ARM_MODE_DWARF;
}
uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;

// If var-args are used, there may be a stack adjust required.
switch (StackAdjust) {
case 0:
  break;
case 4:
  CompactUnwindEncoding |= 0x00400000;
  break;
case 8:
  CompactUnwindEncoding |= 0x00800000;
  break;
case 12:
  CompactUnwindEncoding |= 0x00C00000;
  break;
default:
  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()do { } while (false)
                                        << ".cfi_def_cfa stack adjust ("do { } while (false)
                                        << StackAdjust << ") out of range\n")do { } while (false);
  return CU::UNWIND_ARM_MODE_DWARF;
}

// If r6 is saved, it must be right below r7.
static struct {
  unsigned Reg;
  unsigned Encoding;
} GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
                 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
                 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
                 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
                 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
                 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
                 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
                 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};

int CurOffset = -8 - StackAdjust;
for (auto CSReg : GPRCSRegs) {
  auto Offset = RegOffsets.find(CSReg.Reg);
  if (Offset == RegOffsets.end())
    continue;

  int RegOffset = Offset->second;
  if (RegOffset != CurOffset - 4) {
    DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                    llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "do { } while (false)
                                 << RegOffset << " but only supported at "do { } while (false)
                                 << CurOffset << "\n")do { } while (false);
    return CU::UNWIND_ARM_MODE_DWARF;
  }
  CompactUnwindEncoding |= CSReg.Encoding;
  CurOffset -= 4;
}

// If no floats saved, we are done.
if (FloatRegCount == 0)
  return CompactUnwindEncoding;

// Switch mode to include D register saving.
CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;

// FIXME: supporting more than 4 saved D-registers compactly would be trivial,
// but needs coordination with the linker and libunwind.
if (FloatRegCount > 4) {
  DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                  llvm::dbgs() << "unsupported number of D registers saved ("do { } while (false)
                               << FloatRegCount << ")\n")do { } while (false);
    return CU::UNWIND_ARM_MODE_DWARF;
}

// Floating point registers must either be saved sequentially, or we defer to
// DWARF. No gaps allowed here so check that each saved d-register is
// precisely where it should be.
static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
  auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
  if (Offset == RegOffsets.end()) {
    DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                    llvm::dbgs() << FloatRegCount << " D-regs saved, but "do { } while (false)
                                 << MRI.getName(FPRCSRegs[Idx])do { } while (false)
                                 << " not saved\n")do { } while (false);
    return CU::UNWIND_ARM_MODE_DWARF;
  } else if (Offset->second != CurOffset - 8) {
    DEBUG_WITH_TYPE("compact-unwind",do { } while (false)
                    llvm::dbgs() << FloatRegCount << " D-regs saved, but "do { } while (false)
                                 << MRI.getName(FPRCSRegs[Idx])do { } while (false)
                                 << " saved at " << Offset->seconddo { } while (false)
                                 << ", expected at " << CurOffset - 8do { } while (false)
                                 << "\n")do { } while (false);
    return CU::UNWIND_ARM_MODE_DWARF;
  }
  CurOffset -= 8;
}

return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1288}

1290static MCAsmBackend *createARMAsmBackend(const Target &T,
                                       const MCSubtargetInfo &STI,
                                       const MCRegisterInfo &MRI,
                                       const MCTargetOptions &Options,
                                       support::endianness Endian) {
const Triple &TheTriple = STI.getTargetTriple();
switch (TheTriple.getObjectFormat()) {
default:
  llvm_unreachable("unsupported object format")__builtin_unreachable();
case Triple::MachO:
  return new ARMAsmBackendDarwin(T, STI, MRI);
case Triple::COFF:
  assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported")(static_cast<void> (0));
  return new ARMAsmBackendWinCOFF(T, STI);
case Triple::ELF:
  assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target")(static_cast<void> (0));
  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
  return new ARMAsmBackendELF(T, STI, OSABI, Endian);
}
1309}

1311MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                        const MCSubtargetInfo &STI,
                                        const MCRegisterInfo &MRI,
                                        const MCTargetOptions &Options) {
return createARMAsmBackend(T, STI, MRI, Options, support::little);
1316}

1318MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                        const MCSubtargetInfo &STI,
                                        const MCRegisterInfo &MRI,
                                        const MCTargetOptions &Options) {
return createARMAsmBackend(T, STI, MRI, Options, support::big);
1323}

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h

1//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the ARM addressing mode implementation stuff.
10//
11//===----------------------------------------------------------------------===//

13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H

16#include "llvm/ADT/APFloat.h"
17#include "llvm/ADT/APInt.h"
18#include "llvm/ADT/bit.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/MathExtras.h"
21#include <cassert>

23namespace llvm {

25/// ARM_AM - ARM Addressing Mode Stuff
26namespace ARM_AM {
enum ShiftOpc {
  no_shift = 0,
  asr,
  lsl,
  lsr,
  ror,
  rrx,
  uxtw
};

enum AddrOpc {
  sub = 0,
  add
};

inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; }

inline const char *getShiftOpcStr(ShiftOpc Op) {
  switch (Op) {
  default: llvm_unreachable("Unknown shift opc!")__builtin_unreachable();
  case ARM_AM::asr: return "asr";
  case ARM_AM::lsl: return "lsl";
  case ARM_AM::lsr: return "lsr";
  case ARM_AM::ror: return "ror";
  case ARM_AM::rrx: return "rrx";
  case ARM_AM::uxtw: return "uxtw";
  }
}

inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
  switch (Op) {
  default: llvm_unreachable("Unknown shift opc!")__builtin_unreachable();
  case ARM_AM::asr: return 2;
  case ARM_AM::lsl: return 0;
  case ARM_AM::lsr: return 1;
  case ARM_AM::ror: return 3;
  }
}

enum AMSubMode {
  bad_am_submode = 0,
  ia,
  ib,
  da,
  db
};

inline const char *getAMSubModeStr(AMSubMode Mode) {
  switch (Mode) {
  default: llvm_unreachable("Unknown addressing sub-mode!")__builtin_unreachable();
  case ARM_AM::ia: return "ia";
  case ARM_AM::ib: return "ib";
  case ARM_AM::da: return "da";
  case ARM_AM::db: return "db";
  }
}

/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
///
inline unsigned rotr32(unsigned Val, unsigned Amt) {
  assert(Amt < 32 && "Invalid rotate amount")(static_cast<void> (0));
  return (Val >> Amt) | (Val << ((32-Amt)&31));
12
←
The result of the right shift is undefined due to shifting by '32', which is greater or equal to the width of type 'unsigned int'
}

/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
///
inline unsigned rotl32(unsigned Val, unsigned Amt) {
  assert(Amt < 32 && "Invalid rotate amount")(static_cast<void> (0));
  return (Val << Amt) | (Val >> ((32-Amt)&31));
}

//===--------------------------------------------------------------------===//
// Addressing Mode #1: shift_operand with registers
//===--------------------------------------------------------------------===//
//
// This 'addressing mode' is used for arithmetic instructions.  It can
// represent things like:
//   reg
//   reg [asr|lsl|lsr|ror|rrx] reg
//   reg [asr|lsl|lsr|ror|rrx] imm
//
// This is stored three operands [rega, regb, opc].  The first is the base
// reg, the second is the shift amount (or reg0 if not present or imm).  The
// third operand encodes the shift opcode and the imm if a reg isn't present.
//
inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
  return ShOp | (Imm << 3);
}
inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; }
inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); }

/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
/// the 8-bit imm value.
inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; }
/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
/// the rotate amount.
inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; }

/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
/// computing the rotate amount to use.  If this immediate value cannot be
/// handled with a single shifter-op, determine a good rotate amount that will
/// take a maximal chunk of bits out of the immediate.
inline unsigned getSOImmValRotate(unsigned Imm) {
  // 8-bit (or less) immediates are trivially shifter_operands with a rotate
  // of zero.
  if ((Imm & ~255U) == 0) return 0;
8
←
Taking false branch→

  // Use CTZ to compute the rotate amount.
  unsigned TZ = countTrailingZeros(Imm);

  // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
  // not 9.
  unsigned RotAmt = TZ & ~1;
9
←
'RotAmt' initialized to 32→

  // If we can handle this spread, return it.
  if ((rotr32(Imm, RotAmt) & ~255U) == 0)
10
←
Passing the value 32 via 2nd parameter 'Amt'→
11
←
Calling 'rotr32'→
    return (32-RotAmt)&31;  // HW rotates right, not left.

  // For values like 0xF000000F, we should ignore the low 6 bits, then
  // retry the hunt.
  if (Imm & 63U) {
    unsigned TZ2 = countTrailingZeros(Imm & ~63U);
    unsigned RotAmt2 = TZ2 & ~1;
    if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
      return (32-RotAmt2)&31;  // HW rotates right, not left.
  }

  // Otherwise, we have no way to cover this span of bits with a single
  // shifter_op immediate.  Return a chunk of bits that will be useful to
  // handle.
  return (32-RotAmt)&31;  // HW rotates right, not left.
}

/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into an shifter_operand immediate operand, return the 12-bit encoding for
/// it.  If not, return -1.
inline int getSOImmVal(unsigned Arg) {
  // 8-bit (or less) immediates are trivially shifter_operands with a rotate
  // of zero.
  if ((Arg & ~255U) == 0) return Arg;
5
←
Assuming the condition is false→
6
←
Taking false branch→

  unsigned RotAmt = getSOImmValRotate(Arg);
7
←
Calling 'getSOImmValRotate'→

  // If this cannot be handled with a single shifter_op, bail out.
  if (rotr32(~255U, RotAmt) & Arg)
    return -1;

  // Encode this correctly.
  return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
}

/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
/// or'ing together two SOImmVal's.
inline bool isSOImmTwoPartVal(unsigned V) {
  // If this can be handled with a single shifter_op, bail out.
  V = rotr32(~255U, getSOImmValRotate(V)) & V;
  if (V == 0)
    return false;

  // If this can be handled with two shifter_op's, accept.
  V = rotr32(~255U, getSOImmValRotate(V)) & V;
  return V == 0;
}

/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
/// return the first chunk of it.
inline unsigned getSOImmTwoPartFirst(unsigned V) {
  return rotr32(255U, getSOImmValRotate(V)) & V;
}

/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
/// return the second chunk of it.
inline unsigned getSOImmTwoPartSecond(unsigned V) {
  // Mask out the first hunk.
  V = rotr32(~255U, getSOImmValRotate(V)) & V;

  // Take what's left.
  assert(V == (rotr32(255U, getSOImmValRotate(V)) & V))(static_cast<void> (0));
  return V;
}

/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
/// by two SOImmVal, that -V = First + Second.
/// "R+V" can be optimized to (sub (sub R, First), Second).
/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
inline bool isSOImmTwoPartValNeg(unsigned V) {
  unsigned First;
  if (!isSOImmTwoPartVal(-V))
    return false;
  // Return false if ~(-First) is not a SoImmval.
  First = getSOImmTwoPartFirst(-V);
  First = ~(-First);
  return !(rotr32(~255U, getSOImmValRotate(First)) & First);
}

/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
/// by a left shift. Returns the shift amount to use.
inline unsigned getThumbImmValShift(unsigned Imm) {
  // 8-bit (or less) immediates are trivially immediate operand with a shift
  // of zero.
  if ((Imm & ~255U) == 0) return 0;

  // Use CTZ to compute the shift amount.
  return countTrailingZeros(Imm);
}

/// isThumbImmShiftedVal - Return true if the specified value can be obtained
/// by left shifting a 8-bit immediate.
inline bool isThumbImmShiftedVal(unsigned V) {
  // If this can be handled with
  V = (~255U << getThumbImmValShift(V)) & V;
  return V == 0;
}

/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
/// by a left shift. Returns the shift amount to use.
inline unsigned getThumbImm16ValShift(unsigned Imm) {
  // 16-bit (or less) immediates are trivially immediate operand with a shift
  // of zero.
  if ((Imm & ~65535U) == 0) return 0;

  // Use CTZ to compute the shift amount.
  return countTrailingZeros(Imm);
}

/// isThumbImm16ShiftedVal - Return true if the specified value can be
/// obtained by left shifting a 16-bit immediate.
inline bool isThumbImm16ShiftedVal(unsigned V) {
  // If this can be handled with
  V = (~65535U << getThumbImm16ValShift(V)) & V;
  return V == 0;
}

/// getThumbImmNonShiftedVal - If V is a value that satisfies
/// isThumbImmShiftedVal, return the non-shiftd value.
inline unsigned getThumbImmNonShiftedVal(unsigned V) {
  return V >> getThumbImmValShift(V);
}


/// getT2SOImmValSplat - Return the 12-bit encoded representation
/// if the specified value can be obtained by splatting the low 8 bits
/// into every other byte or every byte of a 32-bit value. i.e.,
///     00000000 00000000 00000000 abcdefgh    control = 0
///     00000000 abcdefgh 00000000 abcdefgh    control = 1
///     abcdefgh 00000000 abcdefgh 00000000    control = 2
///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
/// Return -1 if none of the above apply.
/// See ARM Reference Manual A6.3.2.
inline int getT2SOImmValSplatVal(unsigned V) {
  unsigned u, Vs, Imm;
  // control = 0
  if ((V & 0xffffff00) == 0)
    return V;

  // If the value is zeroes in the first byte, just shift those off
  Vs = ((V & 0xff) == 0) ? V >> 8 : V;
  // Any passing value only has 8 bits of payload, splatted across the word
  Imm = Vs & 0xff;
  // Likewise, any passing values have the payload splatted into the 3rd byte
  u = Imm | (Imm << 16);

  // control = 1 or 2
  if (Vs == u)
    return (((Vs == V) ? 1 : 2) << 8) | Imm;

  // control = 3
  if (Vs == (u | (u << 8)))
    return (3 << 8) | Imm;

  return -1;
}

/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
/// specified value is a rotated 8-bit value. Return -1 if no rotation
/// encoding is possible.
/// See ARM Reference Manual A6.3.2.
inline int getT2SOImmValRotateVal(unsigned V) {
  unsigned RotAmt = countLeadingZeros(V);
  if (RotAmt >= 24)
    return -1;

  // If 'Arg' can be handled with a single shifter_op return the value.
  if ((rotr32(0xff000000U, RotAmt) & V) == V)
    return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);

  return -1;
}

/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
/// encoding for it.  If not, return -1.
/// See ARM Reference Manual A6.3.2.
inline int getT2SOImmVal(unsigned Arg) {
  // If 'Arg' is an 8-bit splat, then get the encoded value.
  int Splat = getT2SOImmValSplatVal(Arg);
  if (Splat != -1)
    return Splat;

  // If 'Arg' can be handled with a single shifter_op return the value.
  int Rot = getT2SOImmValRotateVal(Arg);
  if (Rot != -1)
    return Rot;

  return -1;
}

inline unsigned getT2SOImmValRotate(unsigned V) {
  if ((V & ~255U) == 0) return 0;
  // Use CTZ to compute the rotate amount.
  unsigned RotAmt = countTrailingZeros(V);
  return (32 - RotAmt) & 31;
}

inline bool isT2SOImmTwoPartVal(unsigned Imm) {
  unsigned V = Imm;
  // Passing values can be any combination of splat values and shifter
  // values. If this can be handled with a single shifter or splat, bail
  // out. Those should be handled directly, not with a two-part val.
  if (getT2SOImmValSplatVal(V) != -1)
    return false;
  V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
  if (V == 0)
    return false;

  // If this can be handled as an immediate, accept.
  if (getT2SOImmVal(V) != -1) return true;

  // Likewise, try masking out a splat value first.
  V = Imm;
  if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
    V &= ~0xff00ff00U;
  else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
    V &= ~0x00ff00ffU;
  // If what's left can be handled as an immediate, accept.
  if (getT2SOImmVal(V) != -1) return true;

  // Otherwise, do not accept.
  return false;
}

inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
  assert (isT2SOImmTwoPartVal(Imm) &&(static_cast<void> (0))
          "Immedate cannot be encoded as two part immediate!")(static_cast<void> (0));
  // Try a shifter operand as one part
  unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
  // If the rest is encodable as an immediate, then return it.
  if (getT2SOImmVal(V) != -1) return V;

  // Try masking out a splat value first.
  if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
    return Imm & 0xff00ff00U;

  // The other splat is all that's left as an option.
  assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1)(static_cast<void> (0));
  return Imm & 0x00ff00ffU;
}

inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
  // Mask out the first hunk
  Imm ^= getT2SOImmTwoPartFirst(Imm);
  // Return what's left
  assert (getT2SOImmVal(Imm) != -1 &&(static_cast<void> (0))
          "Unable to encode second part of T2 two part SO immediate")(static_cast<void> (0));
  return Imm;
}


//===--------------------------------------------------------------------===//
// Addressing Mode #2
//===--------------------------------------------------------------------===//
//
// This is used for most simple load/store instructions.
//
// addrmode2 := reg +/- reg shop imm
// addrmode2 := reg +/- imm12
//
// The first operand is always a Reg.  The second operand is a reg if in
// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
// fourth operand 16-17 encodes the index mode.
//
// If this addressing mode is a frame index (before prolog/epilog insertion
// and code rewriting), this operand will have the form:  FI#, reg0, <offs>
// with no shift amount for the frame offset.
//
inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
                          unsigned IdxMode = 0) {
  assert(Imm12 < (1 << 12) && "Imm too large!")(static_cast<void> (0));
  bool isSub = Opc == sub;
  return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
}
inline unsigned getAM2Offset(unsigned AM2Opc) {
  return AM2Opc & ((1 << 12)-1);
}
inline AddrOpc getAM2Op(unsigned AM2Opc) {
  return ((AM2Opc >> 12) & 1) ? sub : add;
}
inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
  return (ShiftOpc)((AM2Opc >> 13) & 7);
}
inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); }

//===--------------------------------------------------------------------===//
// Addressing Mode #3
//===--------------------------------------------------------------------===//
//
// This is used for sign-extending loads, and load/store-pair instructions.
//
// addrmode3 := reg +/- reg
// addrmode3 := reg +/- imm8
//
// The first operand is always a Reg.  The second operand is a reg if in
// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
// index mode.

/// getAM3Opc - This function encodes the addrmode3 opc field.
inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
                          unsigned IdxMode = 0) {
  bool isSub = Opc == sub;
  return ((int)isSub << 8) | Offset | (IdxMode << 9);
}
inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; }
inline AddrOpc getAM3Op(unsigned AM3Opc) {
  return ((AM3Opc >> 8) & 1) ? sub : add;
}
inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); }

//===--------------------------------------------------------------------===//
// Addressing Mode #4
//===--------------------------------------------------------------------===//
//
// This is used for load / store multiple instructions.
//
// addrmode4 := reg, <mode>
//
// The four modes are:
//    IA - Increment after
//    IB - Increment before
//    DA - Decrement after
//    DB - Decrement before
// For VFP instructions, only the IA and DB modes are valid.

inline AMSubMode getAM4SubMode(unsigned Mode) {
  return (AMSubMode)(Mode & 0x7);
}

inline unsigned getAM4ModeImm(AMSubMode SubMode) { return (int)SubMode; }

//===--------------------------------------------------------------------===//
// Addressing Mode #5
//===--------------------------------------------------------------------===//
//
// This is used for coprocessor instructions, such as FP load/stores.
//
// addrmode5 := reg +/- imm8*4
//
// The first operand is always a Reg.  The second operand encodes the
// operation (add or subtract) in bit 8 and the immediate in bits 0-7.

/// getAM5Opc - This function encodes the addrmode5 opc field.
inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
  bool isSub = Opc == sub;
  return ((int)isSub << 8) | Offset;
}
inline unsigned char getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; }
inline AddrOpc getAM5Op(unsigned AM5Opc) {
  return ((AM5Opc >> 8) & 1) ? sub : add;
}

//===--------------------------------------------------------------------===//
// Addressing Mode #5 FP16
//===--------------------------------------------------------------------===//
//
// This is used for coprocessor instructions, such as 16-bit FP load/stores.
//
// addrmode5fp16 := reg +/- imm8*2
//
// The first operand is always a Reg.  The second operand encodes the
// operation (add or subtract) in bit 8 and the immediate in bits 0-7.

/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {
  bool isSub = Opc == sub;
  return ((int)isSub << 8) | Offset;
}
inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {
  return AM5Opc & 0xFF;
}
inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {
  return ((AM5Opc >> 8) & 1) ? sub : add;
}

//===--------------------------------------------------------------------===//
// Addressing Mode #6
//===--------------------------------------------------------------------===//
//
// This is used for NEON load / store instructions.
//
// addrmode6 := reg with optional alignment
//
// This is stored in two operands [regaddr, align].  The first is the
// address register.  The second operand is the value of the alignment
// specifier in bytes or zero if no explicit alignment.
// Valid alignments depend on the specific instruction.

//===--------------------------------------------------------------------===//
// NEON/MVE Modified Immediates
//===--------------------------------------------------------------------===//
//
// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
// vector operand, where a small immediate encoded in the instruction
// specifies a full NEON vector value.  These modified immediates are
// represented here as encoded integers.  The low 8 bits hold the immediate
// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
// the "Cmode" field of the instruction.  The interfaces below treat the
// Op and Cmode values as a single 5-bit value.

inline unsigned createVMOVModImm(unsigned OpCmode, unsigned Val) {
  return (OpCmode << 8) | Val;
}
inline unsigned getVMOVModImmOpCmode(unsigned ModImm) {
  return (ModImm >> 8) & 0x1f;
}
inline unsigned getVMOVModImmVal(unsigned ModImm) { return ModImm & 0xff; }

/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
/// element value and the element size in bits.  (If the element size is
/// smaller than the vector, it is splatted into all the elements.)
inline uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits) {
  unsigned OpCmode = getVMOVModImmOpCmode(ModImm);
  unsigned Imm8 = getVMOVModImmVal(ModImm);
  uint64_t Val = 0;

  if (OpCmode == 0xe) {
    // 8-bit vector elements
    Val = Imm8;
    EltBits = 8;
  } else if ((OpCmode & 0xc) == 0x8) {
    // 16-bit vector elements
    unsigned ByteNum = (OpCmode & 0x6) >> 1;
    Val = Imm8 << (8 * ByteNum);
    EltBits = 16;
  } else if ((OpCmode & 0x8) == 0) {
    // 32-bit vector elements, zero with one byte set
    unsigned ByteNum = (OpCmode & 0x6) >> 1;
    Val = Imm8 << (8 * ByteNum);
    EltBits = 32;
  } else if ((OpCmode & 0xe) == 0xc) {
    // 32-bit vector elements, one byte with low bits set
    unsigned ByteNum = 1 + (OpCmode & 0x1);
    Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
    EltBits = 32;
  } else if (OpCmode == 0x1e) {
    // 64-bit vector elements
    for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
      if ((ModImm >> ByteNum) & 1)
        Val |= (uint64_t)0xff << (8 * ByteNum);
    }
    EltBits = 64;
  } else {
    llvm_unreachable("Unsupported VMOV immediate")__builtin_unreachable();
  }
  return Val;
}

// Generic validation for single-byte immediate (0X00, 00X0, etc).
inline bool isNEONBytesplat(unsigned Value, unsigned Size) {
  assert(Size >= 1 && Size <= 4 && "Invalid size")(static_cast<void> (0));
  unsigned count = 0;
  for (unsigned i = 0; i < Size; ++i) {
    if (Value & 0xff) count++;
    Value >>= 8;
  }
  return count == 1;
}

/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
inline bool isNEONi16splat(unsigned Value) {
  if (Value > 0xffff)
    return false;
  // i16 value with set bits only in one byte X0 or 0X.
  return Value == 0 || isNEONBytesplat(Value, 2);
}

// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
inline unsigned encodeNEONi16splat(unsigned Value) {
  assert(isNEONi16splat(Value) && "Invalid NEON splat value")(static_cast<void> (0));
  if (Value >= 0x100)
    Value = (Value >> 8) | 0xa00;
  else
    Value |= 0x800;
  return Value;
}

/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
inline bool isNEONi32splat(unsigned Value) {
  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
  return Value == 0 || isNEONBytesplat(Value, 4);
}

/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
inline unsigned encodeNEONi32splat(unsigned Value) {
  assert(isNEONi32splat(Value) && "Invalid NEON splat value")(static_cast<void> (0));
  if (Value >= 0x100 && Value <= 0xff00)
    Value = (Value >> 8) | 0x200;
  else if (Value > 0xffff && Value <= 0xff0000)
    Value = (Value >> 16) | 0x400;
  else if (Value > 0xffffff)
    Value = (Value >> 24) | 0x600;
  return Value;
}

//===--------------------------------------------------------------------===//
// Floating-point Immediates
//
inline float getFPImmFloat(unsigned Imm) {
  // We expect an 8-bit binary encoding of a floating-point number here.

  uint8_t Sign = (Imm >> 7) & 0x1;
  uint8_t Exp = (Imm >> 4) & 0x7;
  uint8_t Mantissa = Imm & 0xf;

  //   8-bit FP    IEEE Float Encoding
  //   abcd efgh   aBbbbbbc defgh000 00000000 00000000
  //
  // where B = NOT(b);
  uint32_t I = 0;
  I |= Sign << 31;
  I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
  I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
  I |= (Exp & 0x3) << 23;
  I |= Mantissa << 19;
  return bit_cast<float>(I);
}

/// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
inline int getFP16Imm(const APInt &Imm) {
  uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
  int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15;  // -14 to 15
  int64_t Mantissa = Imm.getZExtValue() & 0x3ff;  // 10 bits

  // We can handle 4 bits of mantissa.
  // mantissa = (16+UInt(e:f:g:h))/16.
  if (Mantissa & 0x3f)
    return -1;
  Mantissa >>= 6;

  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
  if (Exp < -3 || Exp > 4)
    return -1;
  Exp = ((Exp+3) & 0x7) ^ 4;

  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
}

inline int getFP16Imm(const APFloat &FPImm) {
  return getFP16Imm(FPImm.bitcastToAPInt());
}

/// If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding
/// for it. Otherwise return -1 like getFP16Imm.
inline int getFP32FP16Imm(const APInt &Imm) {
  if (Imm.getActiveBits() > 16)
    return -1;
  return ARM_AM::getFP16Imm(Imm.trunc(16));
}

inline int getFP32FP16Imm(const APFloat &FPImm) {
  return getFP32FP16Imm(FPImm.bitcastToAPInt());
}

/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
inline int getFP32Imm(const APInt &Imm) {
  uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
  int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127;  // -126 to 127
  int64_t Mantissa = Imm.getZExtValue() & 0x7fffff;  // 23 bits

  // We can handle 4 bits of mantissa.
  // mantissa = (16+UInt(e:f:g:h))/16.
  if (Mantissa & 0x7ffff)
    return -1;
  Mantissa >>= 19;
  if ((Mantissa & 0xf) != Mantissa)
    return -1;

  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
  if (Exp < -3 || Exp > 4)
    return -1;
  Exp = ((Exp+3) & 0x7) ^ 4;

  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
}

inline int getFP32Imm(const APFloat &FPImm) {
  return getFP32Imm(FPImm.bitcastToAPInt());
}

/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
inline int getFP64Imm(const APInt &Imm) {
  uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
  int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
  uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;

  // We can handle 4 bits of mantissa.
  // mantissa = (16+UInt(e:f:g:h))/16.
  if (Mantissa & 0xffffffffffffULL)
    return -1;
  Mantissa >>= 48;
  if ((Mantissa & 0xf) != Mantissa)
    return -1;

  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
  if (Exp < -3 || Exp > 4)
    return -1;
  Exp = ((Exp+3) & 0x7) ^ 4;

  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
}

inline int getFP64Imm(const APFloat &FPImm) {
  return getFP64Imm(FPImm.bitcastToAPInt());
}

758} // end namespace ARM_AM
759} // end namespace llvm

761#endif
