Bug Summary

File:llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
Warning:line 1073, column 67
The left operand of '-' is a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMAsmBackend.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/llvm/lib/Target/ARM/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/llvm/lib/Target/ARM -I lib/Target/ARM -I include -I /build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-19-001817-16337-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220118101002+ec47dba1c8a2/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/ARMAsmBackend.h"
10#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMAsmBackendDarwin.h"
12#include "MCTargetDesc/ARMAsmBackendELF.h"
13#include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
14#include "MCTargetDesc/ARMFixupKinds.h"
15#include "MCTargetDesc/ARMMCTargetDesc.h"
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/BinaryFormat/MachO.h"
19#include "llvm/MC/MCAsmBackend.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCDirectives.h"
23#include "llvm/MC/MCELFObjectWriter.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCFixupKindInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSectionELF.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/MC/MCSubtargetInfo.h"
31#include "llvm/MC/MCValue.h"
32#include "llvm/MC/MCAsmLayout.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/EndianStream.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/Format.h"
37#include "llvm/Support/TargetParser.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41namespace {
42class ARMELFObjectWriter : public MCELFObjectTargetWriter {
43public:
44 ARMELFObjectWriter(uint8_t OSABI)
45 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
46 /*HasRelocationAddend*/ false) {}
47};
48} // end anonymous namespace
49
50Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
51 return None;
52}
53
54Optional<MCFixupKind> ARMAsmBackendELF::getFixupKind(StringRef Name) const {
55 unsigned Type = llvm::StringSwitch<unsigned>(Name)
56#define ELF_RELOC(X, Y) .Case(#X, Y)
57#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
58#undef ELF_RELOC
59 .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
60 .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
61 .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
62 .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
63 .Default(-1u);
64 if (Type == -1u)
65 return None;
66 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
67}
68
69const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
70 unsigned IsPCRelConstant =
71 MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant;
72 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
73 // This table *must* be in the order that the fixup_* kinds are defined in
74 // ARMFixupKinds.h.
75 //
76 // Name Offset (bits) Size (bits) Flags
77 {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
78 {"fixup_t2_ldst_pcrel_12", 0, 32,
79 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
80 {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
81 {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
82 {"fixup_t2_pcrel_10", 0, 32,
83 MCFixupKindInfo::FKF_IsPCRel |
84 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
85 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86 {"fixup_t2_pcrel_9", 0, 32,
87 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
88 {"fixup_arm_ldst_abs_12", 0, 32, 0},
89 {"fixup_thumb_adr_pcrel_10", 0, 8,
90 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
91 {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
92 {"fixup_t2_adr_pcrel_12", 0, 32,
93 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
94 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
95 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
96 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
97 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
98 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
103 {"fixup_arm_thumb_blx", 0, 32,
104 MCFixupKindInfo::FKF_IsPCRel |
105 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
106 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
107 {"fixup_arm_thumb_cp", 0, 8,
108 MCFixupKindInfo::FKF_IsPCRel |
109 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
110 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
111 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
112 // - 19.
113 {"fixup_arm_movt_hi16", 0, 20, 0},
114 {"fixup_arm_movw_lo16", 0, 20, 0},
115 {"fixup_t2_movt_hi16", 0, 20, 0},
116 {"fixup_t2_movw_lo16", 0, 20, 0},
117 {"fixup_arm_mod_imm", 0, 12, 0},
118 {"fixup_t2_so_imm", 0, 26, 0},
119 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
123 {"fixup_bfcsel_else_target", 0, 32, 0},
124 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
125 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
126 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
127 // This table *must* be in the order that the fixup_* kinds are defined in
128 // ARMFixupKinds.h.
129 //
130 // Name Offset (bits) Size (bits) Flags
131 {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
132 {"fixup_t2_ldst_pcrel_12", 0, 32,
133 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
134 {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
135 {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
136 {"fixup_t2_pcrel_10", 0, 32,
137 MCFixupKindInfo::FKF_IsPCRel |
138 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
139 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
140 {"fixup_t2_pcrel_9", 0, 32,
141 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
142 {"fixup_arm_ldst_abs_12", 0, 32, 0},
143 {"fixup_thumb_adr_pcrel_10", 8, 8,
144 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
145 {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
146 {"fixup_t2_adr_pcrel_12", 0, 32,
147 IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
148 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
149 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
150 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
151 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
152 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
153 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
154 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
155 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
156 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
157 {"fixup_arm_thumb_blx", 0, 32,
158 MCFixupKindInfo::FKF_IsPCRel |
159 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
160 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
161 {"fixup_arm_thumb_cp", 8, 8,
162 MCFixupKindInfo::FKF_IsPCRel |
163 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
164 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
165 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
166 // - 19.
167 {"fixup_arm_movt_hi16", 12, 20, 0},
168 {"fixup_arm_movw_lo16", 12, 20, 0},
169 {"fixup_t2_movt_hi16", 12, 20, 0},
170 {"fixup_t2_movw_lo16", 12, 20, 0},
171 {"fixup_arm_mod_imm", 20, 12, 0},
172 {"fixup_t2_so_imm", 26, 6, 0},
173 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
174 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
175 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
176 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
177 {"fixup_bfcsel_else_target", 0, 32, 0},
178 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
179 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
180
181 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
182 // any extra processing.
183 if (Kind >= FirstLiteralRelocationKind)
184 return MCAsmBackend::getFixupKindInfo(FK_NONE);
185
186 if (Kind < FirstTargetFixupKind)
187 return MCAsmBackend::getFixupKindInfo(Kind);
188
189 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&(static_cast <bool> (unsigned(Kind - FirstTargetFixupKind
) < getNumFixupKinds() && "Invalid kind!") ? void (
0) : __assert_fail ("unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && \"Invalid kind!\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 190, __extension__
__PRETTY_FUNCTION__))
190 "Invalid kind!")(static_cast <bool> (unsigned(Kind - FirstTargetFixupKind
) < getNumFixupKinds() && "Invalid kind!") ? void (
0) : __assert_fail ("unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && \"Invalid kind!\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 190, __extension__
__PRETTY_FUNCTION__))
;
191 return (Endian == support::little ? InfosLE
192 : InfosBE)[Kind - FirstTargetFixupKind];
193}
194
195void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
196 switch (Flag) {
197 default:
198 break;
199 case MCAF_Code16:
200 setIsThumb(true);
201 break;
202 case MCAF_Code32:
203 setIsThumb(false);
204 break;
205 }
206}
207
208unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op,
209 const MCSubtargetInfo &STI) const {
210 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
211 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
212
213 switch (Op) {
214 default:
215 return Op;
216 case ARM::tBcc:
217 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
218 case ARM::tLDRpci:
219 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
220 case ARM::tADR:
221 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
222 case ARM::tB:
223 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
224 case ARM::tCBZ:
225 return ARM::tHINT;
226 case ARM::tCBNZ:
227 return ARM::tHINT;
228 }
229}
230
231bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
232 const MCSubtargetInfo &STI) const {
233 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
234 return true;
235 return false;
236}
237
238static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
239 int64_t Offset = int64_t(Value) - 4;
240 if (Offset < Min || Offset > Max)
241 return "out of range pc-relative fixup value";
242 return nullptr;
243}
244
245const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
246 uint64_t Value) const {
247 switch (Fixup.getTargetKind()) {
248 case ARM::fixup_arm_thumb_br: {
249 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
250 // low bit being an implied zero. There's an implied +4 offset for the
251 // branch, so we adjust the other way here to determine what's
252 // encodable.
253 //
254 // Relax if the value is too big for a (signed) i8.
255 int64_t Offset = int64_t(Value) - 4;
256 if (Offset > 2046 || Offset < -2048)
257 return "out of range pc-relative fixup value";
258 break;
259 }
260 case ARM::fixup_arm_thumb_bcc: {
261 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
262 // low bit being an implied zero. There's an implied +4 offset for the
263 // branch, so we adjust the other way here to determine what's
264 // encodable.
265 //
266 // Relax if the value is too big for a (signed) i8.
267 int64_t Offset = int64_t(Value) - 4;
268 if (Offset > 254 || Offset < -256)
269 return "out of range pc-relative fixup value";
270 break;
271 }
272 case ARM::fixup_thumb_adr_pcrel_10:
273 case ARM::fixup_arm_thumb_cp: {
274 // If the immediate is negative, greater than 1020, or not a multiple
275 // of four, the wide version of the instruction must be used.
276 int64_t Offset = int64_t(Value) - 4;
277 if (Offset & 3)
278 return "misaligned pc-relative fixup value";
279 else if (Offset > 1020 || Offset < 0)
280 return "out of range pc-relative fixup value";
281 break;
282 }
283 case ARM::fixup_arm_thumb_cb: {
284 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
285 // instruction it is actually out of range for the instruction.
286 // It will be changed to a NOP.
287 int64_t Offset = (Value & ~1);
288 if (Offset == 2)
289 return "will be converted to nop";
290 break;
291 }
292 case ARM::fixup_bf_branch:
293 return checkPCRelOffset(Value, 0, 30);
294 case ARM::fixup_bf_target:
295 return checkPCRelOffset(Value, -0x10000, +0xfffe);
296 case ARM::fixup_bfl_target:
297 return checkPCRelOffset(Value, -0x40000, +0x3fffe);
298 case ARM::fixup_bfc_target:
299 return checkPCRelOffset(Value, -0x1000, +0xffe);
300 case ARM::fixup_wls:
301 return checkPCRelOffset(Value, 0, +0xffe);
302 case ARM::fixup_le:
303 // The offset field in the LE and LETP instructions is an 11-bit
304 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
305 // interpreted as a negative offset from the value read from pc,
306 // i.e. from instruction_address+4.
307 //
308 // So an LE instruction can in principle address the instruction
309 // immediately after itself, or (not very usefully) the address
310 // half way through the 4-byte LE.
311 return checkPCRelOffset(Value, -0xffe, 0);
312 case ARM::fixup_bfcsel_else_target: {
313 if (Value != 2 && Value != 4)
314 return "out of range label-relative fixup value";
315 break;
316 }
317
318 default:
319 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!")::llvm::llvm_unreachable_internal("Unexpected fixup kind in reasonForFixupRelaxation()!"
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 319)
;
320 }
321 return nullptr;
322}
323
324bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
325 const MCRelaxableFragment *DF,
326 const MCAsmLayout &Layout) const {
327 return reasonForFixupRelaxation(Fixup, Value);
328}
329
330void ARMAsmBackend::relaxInstruction(MCInst &Inst,
331 const MCSubtargetInfo &STI) const {
332 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
333
334 // Return a diagnostic if we get here w/ a bogus instruction.
335 if (RelaxedOp == Inst.getOpcode()) {
336 SmallString<256> Tmp;
337 raw_svector_ostream OS(Tmp);
338 Inst.dump_pretty(OS);
339 OS << "\n";
340 report_fatal_error("unexpected instruction to relax: " + OS.str());
341 }
342
343 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
344 // have to change the operands too.
345 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
346 RelaxedOp == ARM::tHINT) {
347 MCInst Res;
348 Res.setOpcode(RelaxedOp);
349 Res.addOperand(MCOperand::createImm(0));
350 Res.addOperand(MCOperand::createImm(14));
351 Res.addOperand(MCOperand::createReg(0));
352 Inst = std::move(Res);
353 return;
354 }
355
356 // The rest of instructions we're relaxing have the same operands.
357 // We just need to update to the proper opcode.
358 Inst.setOpcode(RelaxedOp);
359}
360
361bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
362 const MCSubtargetInfo *STI) const {
363 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
364 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
365 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
366 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
367 if (isThumb()) {
368 const uint16_t nopEncoding =
369 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
370 uint64_t NumNops = Count / 2;
371 for (uint64_t i = 0; i != NumNops; ++i)
372 support::endian::write(OS, nopEncoding, Endian);
373 if (Count & 1)
374 OS << '\0';
375 return true;
376 }
377 // ARM mode
378 const uint32_t nopEncoding =
379 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
380 uint64_t NumNops = Count / 4;
381 for (uint64_t i = 0; i != NumNops; ++i)
382 support::endian::write(OS, nopEncoding, Endian);
383 // FIXME: should this function return false when unable to write exactly
384 // 'Count' bytes with NOP encodings?
385 switch (Count % 4) {
386 default:
387 break; // No leftover bytes to write
388 case 1:
389 OS << '\0';
390 break;
391 case 2:
392 OS.write("\0\0", 2);
393 break;
394 case 3:
395 OS.write("\0\0\xa0", 3);
396 break;
397 }
398
399 return true;
400}
401
402static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
403 if (IsLittleEndian) {
404 // Note that the halfwords are stored high first and low second in thumb;
405 // so we need to swap the fixup value here to map properly.
406 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
407 Swapped |= (Value & 0x0000FFFF) << 16;
408 return Swapped;
409 } else
410 return Value;
411}
412
413static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
414 bool IsLittleEndian) {
415 uint32_t Value;
416
417 if (IsLittleEndian) {
418 Value = (SecondHalf & 0xFFFF) << 16;
419 Value |= (FirstHalf & 0xFFFF);
420 } else {
421 Value = (SecondHalf & 0xFFFF);
422 Value |= (FirstHalf & 0xFFFF) << 16;
423 }
424
425 return Value;
426}
427
428unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
429 const MCFixup &Fixup,
430 const MCValue &Target, uint64_t Value,
431 bool IsResolved, MCContext &Ctx,
432 const MCSubtargetInfo* STI) const {
433 unsigned Kind = Fixup.getKind();
434
435 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
436 // and .word relocations they put the Thumb bit into the addend if possible.
437 // Other relocation types don't want this bit though (branches couldn't encode
438 // it if it *was* present, and no other relocations exist) and it can
439 // interfere with checking valid expressions.
440 if (const MCSymbolRefExpr *A = Target.getSymA()) {
441 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
442 A->getSymbol().isExternal() &&
443 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
444 Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 ||
445 Kind == ARM::fixup_t2_movt_hi16))
446 Value |= 1;
447 }
448
449 switch (Kind) {
450 default:
451 Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
452 return 0;
453 case FK_Data_1:
454 case FK_Data_2:
455 case FK_Data_4:
456 return Value;
457 case FK_SecRel_2:
458 return Value;
459 case FK_SecRel_4:
460 return Value;
461 case ARM::fixup_arm_movt_hi16:
462 assert(STI != nullptr)(static_cast <bool> (STI != nullptr) ? void (0) : __assert_fail
("STI != nullptr", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 462, __extension__ __PRETTY_FUNCTION__))
;
463 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
464 Value >>= 16;
465 LLVM_FALLTHROUGH[[gnu::fallthrough]];
466 case ARM::fixup_arm_movw_lo16: {
467 unsigned Hi4 = (Value & 0xF000) >> 12;
468 unsigned Lo12 = Value & 0x0FFF;
469 // inst{19-16} = Hi4;
470 // inst{11-0} = Lo12;
471 Value = (Hi4 << 16) | (Lo12);
472 return Value;
473 }
474 case ARM::fixup_t2_movt_hi16:
475 assert(STI != nullptr)(static_cast <bool> (STI != nullptr) ? void (0) : __assert_fail
("STI != nullptr", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 475, __extension__ __PRETTY_FUNCTION__))
;
476 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
477 Value >>= 16;
478 LLVM_FALLTHROUGH[[gnu::fallthrough]];
479 case ARM::fixup_t2_movw_lo16: {
480 unsigned Hi4 = (Value & 0xF000) >> 12;
481 unsigned i = (Value & 0x800) >> 11;
482 unsigned Mid3 = (Value & 0x700) >> 8;
483 unsigned Lo8 = Value & 0x0FF;
484 // inst{19-16} = Hi4;
485 // inst{26} = i;
486 // inst{14-12} = Mid3;
487 // inst{7-0} = Lo8;
488 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
489 return swapHalfWords(Value, Endian == support::little);
490 }
491 case ARM::fixup_arm_ldst_pcrel_12:
492 // ARM PC-relative values are offset by 8.
493 Value -= 4;
494 LLVM_FALLTHROUGH[[gnu::fallthrough]];
495 case ARM::fixup_t2_ldst_pcrel_12:
496 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
497 Value -= 4;
498 LLVM_FALLTHROUGH[[gnu::fallthrough]];
499 case ARM::fixup_arm_ldst_abs_12: {
500 bool isAdd = true;
501 if ((int64_t)Value < 0) {
502 Value = -Value;
503 isAdd = false;
504 }
505 if (Value >= 4096) {
506 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
507 return 0;
508 }
509 Value |= isAdd << 23;
510
511 // Same addressing mode as fixup_arm_pcrel_10,
512 // but with 16-bit halfwords swapped.
513 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
514 return swapHalfWords(Value, Endian == support::little);
515
516 return Value;
517 }
518 case ARM::fixup_arm_adr_pcrel_12: {
519 // ARM PC-relative values are offset by 8.
520 Value -= 8;
521 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
522 if ((int64_t)Value < 0) {
523 Value = -Value;
524 opc = 2; // 0b0010
525 }
526 if (ARM_AM::getSOImmVal(Value) == -1) {
527 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
528 return 0;
529 }
530 // Encode the immediate and shift the opcode into place.
531 return ARM_AM::getSOImmVal(Value) | (opc << 21);
532 }
533
534 case ARM::fixup_t2_adr_pcrel_12: {
535 Value -= 4;
536 unsigned opc = 0;
537 if ((int64_t)Value < 0) {
538 Value = -Value;
539 opc = 5;
540 }
541
542 uint32_t out = (opc << 21);
543 out |= (Value & 0x800) << 15;
544 out |= (Value & 0x700) << 4;
545 out |= (Value & 0x0FF);
546
547 return swapHalfWords(out, Endian == support::little);
548 }
549
550 case ARM::fixup_arm_condbranch:
551 case ARM::fixup_arm_uncondbranch:
552 case ARM::fixup_arm_uncondbl:
553 case ARM::fixup_arm_condbl:
554 case ARM::fixup_arm_blx:
555 // These values don't encode the low two bits since they're always zero.
556 // Offset by 8 just as above.
557 if (const MCSymbolRefExpr *SRE =
558 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
559 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
560 return 0;
561 return 0xffffff & ((Value - 8) >> 2);
562 case ARM::fixup_t2_uncondbranch: {
563 Value = Value - 4;
564 if (!isInt<25>(Value)) {
565 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
566 return 0;
567 }
568
569 Value >>= 1; // Low bit is not encoded.
570
571 uint32_t out = 0;
572 bool I = Value & 0x800000;
573 bool J1 = Value & 0x400000;
574 bool J2 = Value & 0x200000;
575 J1 ^= I;
576 J2 ^= I;
577
578 out |= I << 26; // S bit
579 out |= !J1 << 13; // J1 bit
580 out |= !J2 << 11; // J2 bit
581 out |= (Value & 0x1FF800) << 5; // imm6 field
582 out |= (Value & 0x0007FF); // imm11 field
583
584 return swapHalfWords(out, Endian == support::little);
585 }
586 case ARM::fixup_t2_condbranch: {
587 Value = Value - 4;
588 if (!isInt<21>(Value)) {
589 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
590 return 0;
591 }
592
593 Value >>= 1; // Low bit is not encoded.
594
595 uint64_t out = 0;
596 out |= (Value & 0x80000) << 7; // S bit
597 out |= (Value & 0x40000) >> 7; // J2 bit
598 out |= (Value & 0x20000) >> 4; // J1 bit
599 out |= (Value & 0x1F800) << 5; // imm6 field
600 out |= (Value & 0x007FF); // imm11 field
601
602 return swapHalfWords(out, Endian == support::little);
603 }
604 case ARM::fixup_arm_thumb_bl: {
605 if (!isInt<25>(Value - 4) ||
606 (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
607 !STI->getFeatureBits()[ARM::HasV8MBaselineOps] &&
608 !STI->getFeatureBits()[ARM::HasV6MOps] &&
609 !isInt<23>(Value - 4))) {
610 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
611 return 0;
612 }
613
614 // The value doesn't encode the low bit (always zero) and is offset by
615 // four. The 32-bit immediate value is encoded as
616 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
617 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
618 // The value is encoded into disjoint bit positions in the destination
619 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
620 // J = either J1 or J2 bit
621 //
622 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
623 //
624 // Note that the halfwords are stored high first, low second; so we need
625 // to transpose the fixup value here to map properly.
626 uint32_t offset = (Value - 4) >> 1;
627 uint32_t signBit = (offset & 0x800000) >> 23;
628 uint32_t I1Bit = (offset & 0x400000) >> 22;
629 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
630 uint32_t I2Bit = (offset & 0x200000) >> 21;
631 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
632 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
633 uint32_t imm11Bits = (offset & 0x000007FF);
634
635 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
636 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
637 (uint16_t)imm11Bits);
638 return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
639 }
640 case ARM::fixup_arm_thumb_blx: {
641 // The value doesn't encode the low two bits (always zero) and is offset by
642 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
643 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
644 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
645 // The value is encoded into disjoint bit positions in the destination
646 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
647 // J = either J1 or J2 bit, 0 = zero.
648 //
649 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
650 //
651 // Note that the halfwords are stored high first, low second; so we need
652 // to transpose the fixup value here to map properly.
653 if (Value % 4 != 0) {
654 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
655 return 0;
656 }
657
658 uint32_t offset = (Value - 4) >> 2;
659 if (const MCSymbolRefExpr *SRE =
660 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
661 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
662 offset = 0;
663 uint32_t signBit = (offset & 0x400000) >> 22;
664 uint32_t I1Bit = (offset & 0x200000) >> 21;
665 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
666 uint32_t I2Bit = (offset & 0x100000) >> 20;
667 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
668 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
669 uint32_t imm10LBits = (offset & 0x3FF);
670
671 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
672 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
673 ((uint16_t)imm10LBits) << 1);
674 return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
675 }
676 case ARM::fixup_thumb_adr_pcrel_10:
677 case ARM::fixup_arm_thumb_cp:
678 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
679 // could have an error on our hands.
680 assert(STI != nullptr)(static_cast <bool> (STI != nullptr) ? void (0) : __assert_fail
("STI != nullptr", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 680, __extension__ __PRETTY_FUNCTION__))
;
681 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
682 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
683 if (FixupDiagnostic) {
684 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
685 return 0;
686 }
687 }
688 // Offset by 4, and don't encode the low two bits.
689 return ((Value - 4) >> 2) & 0xff;
690 case ARM::fixup_arm_thumb_cb: {
691 // CB instructions can only branch to offsets in [4, 126] in multiples of 2
692 // so ensure that the raw value LSB is zero and it lies in [2, 130].
693 // An offset of 2 will be relaxed to a NOP.
694 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
695 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
696 return 0;
697 }
698 // Offset by 4 and don't encode the lower bit, which is always 0.
699 // FIXME: diagnose if no Thumb2
700 uint32_t Binary = (Value - 4) >> 1;
701 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
702 }
703 case ARM::fixup_arm_thumb_br:
704 // Offset by 4 and don't encode the lower bit, which is always 0.
705 assert(STI != nullptr)(static_cast <bool> (STI != nullptr) ? void (0) : __assert_fail
("STI != nullptr", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 705, __extension__ __PRETTY_FUNCTION__))
;
706 if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
707 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
708 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
709 if (FixupDiagnostic) {
710 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
711 return 0;
712 }
713 }
714 return ((Value - 4) >> 1) & 0x7ff;
715 case ARM::fixup_arm_thumb_bcc:
716 // Offset by 4 and don't encode the lower bit, which is always 0.
717 assert(STI != nullptr)(static_cast <bool> (STI != nullptr) ? void (0) : __assert_fail
("STI != nullptr", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 717, __extension__ __PRETTY_FUNCTION__))
;
718 if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
719 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
720 if (FixupDiagnostic) {
721 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
722 return 0;
723 }
724 }
725 return ((Value - 4) >> 1) & 0xff;
726 case ARM::fixup_arm_pcrel_10_unscaled: {
727 Value = Value - 8; // ARM fixups offset by an additional word and don't
728 // need to adjust for the half-word ordering.
729 bool isAdd = true;
730 if ((int64_t)Value < 0) {
731 Value = -Value;
732 isAdd = false;
733 }
734 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
735 if (Value >= 256) {
736 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
737 return 0;
738 }
739 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
740 return Value | (isAdd << 23);
741 }
742 case ARM::fixup_arm_pcrel_10:
743 Value = Value - 4; // ARM fixups offset by an additional word and don't
744 // need to adjust for the half-word ordering.
745 LLVM_FALLTHROUGH[[gnu::fallthrough]];
746 case ARM::fixup_t2_pcrel_10: {
747 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
748 Value = Value - 4;
749 bool isAdd = true;
750 if ((int64_t)Value < 0) {
751 Value = -Value;
752 isAdd = false;
753 }
754 // These values don't encode the low two bits since they're always zero.
755 Value >>= 2;
756 if (Value >= 256) {
757 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
758 return 0;
759 }
760 Value |= isAdd << 23;
761
762 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
763 // swapped.
764 if (Kind == ARM::fixup_t2_pcrel_10)
765 return swapHalfWords(Value, Endian == support::little);
766
767 return Value;
768 }
769 case ARM::fixup_arm_pcrel_9:
770 Value = Value - 4; // ARM fixups offset by an additional word and don't
771 // need to adjust for the half-word ordering.
772 LLVM_FALLTHROUGH[[gnu::fallthrough]];
773 case ARM::fixup_t2_pcrel_9: {
774 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
775 Value = Value - 4;
776 bool isAdd = true;
777 if ((int64_t)Value < 0) {
778 Value = -Value;
779 isAdd = false;
780 }
781 // These values don't encode the low bit since it's always zero.
782 if (Value & 1) {
783 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
784 return 0;
785 }
786 Value >>= 1;
787 if (Value >= 256) {
788 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
789 return 0;
790 }
791 Value |= isAdd << 23;
792
793 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
794 // swapped.
795 if (Kind == ARM::fixup_t2_pcrel_9)
796 return swapHalfWords(Value, Endian == support::little);
797
798 return Value;
799 }
800 case ARM::fixup_arm_mod_imm:
801 Value = ARM_AM::getSOImmVal(Value);
802 if (Value >> 12) {
803 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
804 return 0;
805 }
806 return Value;
807 case ARM::fixup_t2_so_imm: {
808 Value = ARM_AM::getT2SOImmVal(Value);
809 if ((int64_t)Value < 0) {
810 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
811 return 0;
812 }
813 // Value will contain a 12-bit value broken up into a 4-bit shift in bits
814 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
815 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
816 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
817 // half-word.
818 uint64_t EncValue = 0;
819 EncValue |= (Value & 0x800) << 15;
820 EncValue |= (Value & 0x700) << 4;
821 EncValue |= (Value & 0xff);
822 return swapHalfWords(EncValue, Endian == support::little);
823 }
824 case ARM::fixup_bf_branch: {
825 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
826 if (FixupDiagnostic) {
827 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
828 return 0;
829 }
830 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
831 return swapHalfWords(out, Endian == support::little);
832 }
833 case ARM::fixup_bf_target:
834 case ARM::fixup_bfl_target:
835 case ARM::fixup_bfc_target: {
836 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
837 if (FixupDiagnostic) {
838 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
839 return 0;
840 }
841 uint32_t out = 0;
842 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
843 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
844 out |= (((Value - 4) >> 1) & 0x1) << 11;
845 out |= (((Value - 4) >> 1) & 0x7fe);
846 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
847 return swapHalfWords(out, Endian == support::little);
848 }
849 case ARM::fixup_bfcsel_else_target: {
850 // If this is a fixup of a branch future's else target then it should be a
851 // constant MCExpr representing the distance between the branch targetted
852 // and the instruction after that same branch.
853 Value = Target.getConstant();
854
855 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
856 if (FixupDiagnostic) {
857 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
858 return 0;
859 }
860 uint32_t out = ((Value >> 2) & 1) << 17;
861 return swapHalfWords(out, Endian == support::little);
862 }
863 case ARM::fixup_wls:
864 case ARM::fixup_le: {
865 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
866 if (FixupDiagnostic) {
867 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
868 return 0;
869 }
870 uint64_t real_value = Value - 4;
871 uint32_t out = 0;
872 if (Kind == ARM::fixup_le)
873 real_value = -real_value;
874 out |= ((real_value >> 1) & 0x1) << 11;
875 out |= ((real_value >> 1) & 0x7fe);
876 return swapHalfWords(out, Endian == support::little);
877 }
878 }
879}
880
881bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
882 const MCFixup &Fixup,
883 const MCValue &Target) {
884 const MCSymbolRefExpr *A = Target.getSymA();
885 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
886 const unsigned FixupKind = Fixup.getKind();
887 if (FixupKind >= FirstLiteralRelocationKind)
888 return true;
889 if (FixupKind == ARM::fixup_arm_thumb_bl) {
890 assert(Sym && "How did we resolve this?")(static_cast <bool> (Sym && "How did we resolve this?"
) ? void (0) : __assert_fail ("Sym && \"How did we resolve this?\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 890, __extension__
__PRETTY_FUNCTION__))
;
891
892 // If the symbol is external the linker will handle it.
893 // FIXME: Should we handle it as an optimization?
894
895 // If the symbol is out of range, produce a relocation and hope the
896 // linker can handle it. GNU AS produces an error in this case.
897 if (Sym->isExternal())
898 return true;
899 }
900 // Create relocations for unconditional branches to function symbols with
901 // different execution mode in ELF binaries.
902 if (Sym && Sym->isELF()) {
903 unsigned Type = cast<MCSymbolELF>(Sym)->getType();
904 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
905 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
906 return true;
907 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
908 FixupKind == ARM::fixup_arm_thumb_bl ||
909 FixupKind == ARM::fixup_t2_condbranch ||
910 FixupKind == ARM::fixup_t2_uncondbranch))
911 return true;
912 }
913 }
914 // We must always generate a relocation for BL/BLX instructions if we have
915 // a symbol to reference, as the linker relies on knowing the destination
916 // symbol's thumb-ness to get interworking right.
917 if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
918 FixupKind == ARM::fixup_arm_blx ||
919 FixupKind == ARM::fixup_arm_uncondbl ||
920 FixupKind == ARM::fixup_arm_condbl))
921 return true;
922 return false;
923}
924
925/// getFixupKindNumBytes - The number of bytes the fixup may change.
926static unsigned getFixupKindNumBytes(unsigned Kind) {
927 switch (Kind) {
928 default:
929 llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 929)
;
930
931 case FK_Data_1:
932 case ARM::fixup_arm_thumb_bcc:
933 case ARM::fixup_arm_thumb_cp:
934 case ARM::fixup_thumb_adr_pcrel_10:
935 return 1;
936
937 case FK_Data_2:
938 case ARM::fixup_arm_thumb_br:
939 case ARM::fixup_arm_thumb_cb:
940 case ARM::fixup_arm_mod_imm:
941 return 2;
942
943 case ARM::fixup_arm_pcrel_10_unscaled:
944 case ARM::fixup_arm_ldst_pcrel_12:
945 case ARM::fixup_arm_pcrel_10:
946 case ARM::fixup_arm_pcrel_9:
947 case ARM::fixup_arm_ldst_abs_12:
948 case ARM::fixup_arm_adr_pcrel_12:
949 case ARM::fixup_arm_uncondbl:
950 case ARM::fixup_arm_condbl:
951 case ARM::fixup_arm_blx:
952 case ARM::fixup_arm_condbranch:
953 case ARM::fixup_arm_uncondbranch:
954 return 3;
955
956 case FK_Data_4:
957 case ARM::fixup_t2_ldst_pcrel_12:
958 case ARM::fixup_t2_condbranch:
959 case ARM::fixup_t2_uncondbranch:
960 case ARM::fixup_t2_pcrel_10:
961 case ARM::fixup_t2_pcrel_9:
962 case ARM::fixup_t2_adr_pcrel_12:
963 case ARM::fixup_arm_thumb_bl:
964 case ARM::fixup_arm_thumb_blx:
965 case ARM::fixup_arm_movt_hi16:
966 case ARM::fixup_arm_movw_lo16:
967 case ARM::fixup_t2_movt_hi16:
968 case ARM::fixup_t2_movw_lo16:
969 case ARM::fixup_t2_so_imm:
970 case ARM::fixup_bf_branch:
971 case ARM::fixup_bf_target:
972 case ARM::fixup_bfl_target:
973 case ARM::fixup_bfc_target:
974 case ARM::fixup_bfcsel_else_target:
975 case ARM::fixup_wls:
976 case ARM::fixup_le:
977 return 4;
978
979 case FK_SecRel_2:
980 return 2;
981 case FK_SecRel_4:
982 return 4;
983 }
984}
985
986/// getFixupKindContainerSizeBytes - The number of bytes of the
987/// container involved in big endian.
988static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
989 switch (Kind) {
990 default:
991 llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp"
, 991)
;
992
993 case FK_Data_1:
994 return 1;
995 case FK_Data_2:
996 return 2;
997 case FK_Data_4:
998 return 4;
999
1000 case ARM::fixup_arm_thumb_bcc:
1001 case ARM::fixup_arm_thumb_cp:
1002 case ARM::fixup_thumb_adr_pcrel_10:
1003 case ARM::fixup_arm_thumb_br:
1004 case ARM::fixup_arm_thumb_cb:
1005 // Instruction size is 2 bytes.
1006 return 2;
1007
1008 case ARM::fixup_arm_pcrel_10_unscaled:
1009 case ARM::fixup_arm_ldst_pcrel_12:
1010 case ARM::fixup_arm_pcrel_10:
1011 case ARM::fixup_arm_pcrel_9:
1012 case ARM::fixup_arm_adr_pcrel_12:
1013 case ARM::fixup_arm_uncondbl:
1014 case ARM::fixup_arm_condbl:
1015 case ARM::fixup_arm_blx:
1016 case ARM::fixup_arm_condbranch:
1017 case ARM::fixup_arm_uncondbranch:
1018 case ARM::fixup_t2_ldst_pcrel_12:
1019 case ARM::fixup_t2_condbranch:
1020 case ARM::fixup_t2_uncondbranch:
1021 case ARM::fixup_t2_pcrel_10:
1022 case ARM::fixup_t2_pcrel_9:
1023 case ARM::fixup_t2_adr_pcrel_12:
1024 case ARM::fixup_arm_thumb_bl:
1025 case ARM::fixup_arm_thumb_blx:
1026 case ARM::fixup_arm_movt_hi16:
1027 case ARM::fixup_arm_movw_lo16:
1028 case ARM::fixup_t2_movt_hi16:
1029 case ARM::fixup_t2_movw_lo16:
1030 case ARM::fixup_arm_mod_imm:
1031 case ARM::fixup_t2_so_imm:
1032 case ARM::fixup_bf_branch:
1033 case ARM::fixup_bf_target:
1034 case ARM::fixup_bfl_target:
1035 case ARM::fixup_bfc_target:
1036 case ARM::fixup_bfcsel_else_target:
1037 case ARM::fixup_wls:
1038 case ARM::fixup_le:
1039 // Instruction size is 4 bytes.
1040 return 4;
1041 }
1042}
1043
1044void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
1045 const MCValue &Target,
1046 MutableArrayRef<char> Data, uint64_t Value,
1047 bool IsResolved,
1048 const MCSubtargetInfo* STI) const {
1049 unsigned Kind = Fixup.getKind();
1050 if (Kind >= FirstLiteralRelocationKind)
1
Assuming 'Kind' is < FirstLiteralRelocationKind
2
Taking false branch
1051 return;
1052 MCContext &Ctx = Asm.getContext();
1053 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
1054 if (!Value)
3
Assuming 'Value' is not equal to 0
4
Taking false branch
1055 return; // Doesn't change encoding.
1056 const unsigned NumBytes = getFixupKindNumBytes(Kind);
1057
1058 unsigned Offset = Fixup.getOffset();
1059 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!")(static_cast <bool> (Offset + NumBytes <= Data.size(
) && "Invalid fixup offset!") ? void (0) : __assert_fail
("Offset + NumBytes <= Data.size() && \"Invalid fixup offset!\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1059,
__extension__ __PRETTY_FUNCTION__))
;
5
Assuming the condition is true
6
'?' condition is true
1060
1061 // Used to point to big endian bytes.
1062 unsigned FullSizeBytes;
7
'FullSizeBytes' declared without an initial value
1063 if (Endian == support::big) {
8
Assuming field 'Endian' is not equal to big
9
Taking false branch
1064 FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
1065 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!")(static_cast <bool> ((Offset + FullSizeBytes) <= Data
.size() && "Invalid fixup size!") ? void (0) : __assert_fail
("(Offset + FullSizeBytes) <= Data.size() && \"Invalid fixup size!\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1065,
__extension__ __PRETTY_FUNCTION__))
;
1066 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!")(static_cast <bool> (NumBytes <= FullSizeBytes &&
"Invalid fixup size!") ? void (0) : __assert_fail ("NumBytes <= FullSizeBytes && \"Invalid fixup size!\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1066,
__extension__ __PRETTY_FUNCTION__))
;
1067 }
1068
1069 // For each byte of the fragment that the fixup touches, mask in the bits from
1070 // the fixup value. The Value has been "split up" into the appropriate
1071 // bitfields above.
1072 for (unsigned i = 0; i != NumBytes; ++i) {
1073 unsigned Idx = Endian == support::little ? i : (FullSizeBytes - 1 - i);
10
Loop condition is true. Entering loop body
11
Assuming field 'Endian' is not equal to little
12
'?' condition is false
13
The left operand of '-' is a garbage value
1074 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1075 }
1076}
1077
1078namespace CU {
1079
1080/// Compact unwind encoding values.
1081enum CompactUnwindEncodings {
1082 UNWIND_ARM_MODE_MASK = 0x0F000000,
1083 UNWIND_ARM_MODE_FRAME = 0x01000000,
1084 UNWIND_ARM_MODE_FRAME_D = 0x02000000,
1085 UNWIND_ARM_MODE_DWARF = 0x04000000,
1086
1087 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000,
1088
1089 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001,
1090 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002,
1091 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004,
1092
1093 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008,
1094 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010,
1095 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020,
1096 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040,
1097 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080,
1098
1099 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00,
1100
1101 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF
1102};
1103
1104} // end CU namespace
1105
1106/// Generate compact unwind encoding for the function based on the CFI
1107/// instructions. If the CFI instructions describe a frame that cannot be
1108/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1109/// tells the runtime to fallback and unwind using dwarf.
1110uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
1111 ArrayRef<MCCFIInstruction> Instrs) const {
1112 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "generateCU()\n";
} } while (false)
;
1113 // Only armv7k uses CFI based unwinding.
1114 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
1115 return 0;
1116 // No .cfi directives means no frame.
1117 if (Instrs.empty())
1118 return 0;
1119 // Start off assuming CFA is at SP+0.
1120 unsigned CFARegister = ARM::SP;
1121 int CFARegisterOffset = 0;
1122 // Mark savable registers as initially unsaved
1123 DenseMap<unsigned, int> RegOffsets;
1124 int FloatRegCount = 0;
1125 // Process each .cfi directive and build up compact unwind info.
1126 for (const MCCFIInstruction &Inst : Instrs) {
1127 unsigned Reg;
1128 switch (Inst.getOperation()) {
1129 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1130 CFARegisterOffset = Inst.getOffset();
1131 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1132 break;
1133 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1134 CFARegisterOffset = Inst.getOffset();
1135 break;
1136 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1137 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1138 break;
1139 case MCCFIInstruction::OpOffset: // DW_CFA_offset
1140 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1141 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1142 RegOffsets[Reg] = Inst.getOffset();
1143 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1144 RegOffsets[Reg] = Inst.getOffset();
1145 ++FloatRegCount;
1146 } else {
1147 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_offset on unknown register="
<< Inst.getRegister() << "\n"; } } while (false)
1148 llvm::dbgs() << ".cfi_offset on unknown register="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_offset on unknown register="
<< Inst.getRegister() << "\n"; } } while (false)
1149 << Inst.getRegister() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_offset on unknown register="
<< Inst.getRegister() << "\n"; } } while (false)
;
1150 return CU::UNWIND_ARM_MODE_DWARF;
1151 }
1152 break;
1153 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1154 // Ignore
1155 break;
1156 default:
1157 // Directive not convertable to compact unwind, bail out.
1158 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "CFI directive not compatiable with comact "
"unwind encoding, opcode=" << Inst.getOperation() <<
"\n"; } } while (false)
1159 llvm::dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "CFI directive not compatiable with comact "
"unwind encoding, opcode=" << Inst.getOperation() <<
"\n"; } } while (false)
1160 << "CFI directive not compatiable with comact "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "CFI directive not compatiable with comact "
"unwind encoding, opcode=" << Inst.getOperation() <<
"\n"; } } while (false)
1161 "unwind encoding, opcode=" << Inst.getOperation()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "CFI directive not compatiable with comact "
"unwind encoding, opcode=" << Inst.getOperation() <<
"\n"; } } while (false)
1162 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "CFI directive not compatiable with comact "
"unwind encoding, opcode=" << Inst.getOperation() <<
"\n"; } } while (false)
;
1163 return CU::UNWIND_ARM_MODE_DWARF;
1164 break;
1165 }
1166 }
1167
1168 // If no frame set up, return no unwind info.
1169 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1170 return 0;
1171
1172 // Verify standard frame (lr/r7) was used.
1173 if (CFARegister != ARM::R7) {
1174 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "frame register is "
<< CFARegister << " instead of r7\n"; } } while (
false)
1175 << CFARegisterdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "frame register is "
<< CFARegister << " instead of r7\n"; } } while (
false)
1176 << " instead of r7\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "frame register is "
<< CFARegister << " instead of r7\n"; } } while (
false)
;
1177 return CU::UNWIND_ARM_MODE_DWARF;
1178 }
1179 int StackAdjust = CFARegisterOffset - 8;
1180 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1181 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
1182 llvm::dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
1183 << "LR not saved as standard frame, StackAdjust="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
1184 << StackAdjustdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
1185 << ", CFARegisterOffset=" << CFARegisterOffsetdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
1186 << ", lr save at offset=" << RegOffsets[14] << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
<< StackAdjust << ", CFARegisterOffset=" <<
CFARegisterOffset << ", lr save at offset=" << RegOffsets
[14] << "\n"; } } while (false)
;
1187 return CU::UNWIND_ARM_MODE_DWARF;
1188 }
1189 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1190 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "r7 not saved as standard frame\n"
; } } while (false)
1191 llvm::dbgs() << "r7 not saved as standard frame\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "r7 not saved as standard frame\n"
; } } while (false)
;
1192 return CU::UNWIND_ARM_MODE_DWARF;
1193 }
1194 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1195
1196 // If var-args are used, there may be a stack adjust required.
1197 switch (StackAdjust) {
1198 case 0:
1199 break;
1200 case 4:
1201 CompactUnwindEncoding |= 0x00400000;
1202 break;
1203 case 8:
1204 CompactUnwindEncoding |= 0x00800000;
1205 break;
1206 case 12:
1207 CompactUnwindEncoding |= 0x00C00000;
1208 break;
1209 default:
1210 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_def_cfa stack adjust ("
<< StackAdjust << ") out of range\n"; } } while (
false)
1211 << ".cfi_def_cfa stack adjust ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_def_cfa stack adjust ("
<< StackAdjust << ") out of range\n"; } } while (
false)
1212 << StackAdjust << ") out of range\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << ".cfi_def_cfa stack adjust ("
<< StackAdjust << ") out of range\n"; } } while (
false)
;
1213 return CU::UNWIND_ARM_MODE_DWARF;
1214 }
1215
1216 // If r6 is saved, it must be right below r7.
1217 static struct {
1218 unsigned Reg;
1219 unsigned Encoding;
1220 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1221 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
1222 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
1223 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
1224 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
1225 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
1226 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
1227 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};
1228
1229 int CurOffset = -8 - StackAdjust;
1230 for (auto CSReg : GPRCSRegs) {
1231 auto Offset = RegOffsets.find(CSReg.Reg);
1232 if (Offset == RegOffsets.end())
1233 continue;
1234
1235 int RegOffset = Offset->second;
1236 if (RegOffset != CurOffset - 4) {
1237 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << MRI.getName(CSReg
.Reg) << " saved at " << RegOffset << " but only supported at "
<< CurOffset << "\n"; } } while (false)
1238 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << MRI.getName(CSReg
.Reg) << " saved at " << RegOffset << " but only supported at "
<< CurOffset << "\n"; } } while (false)
1239 << RegOffset << " but only supported at "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << MRI.getName(CSReg
.Reg) << " saved at " << RegOffset << " but only supported at "
<< CurOffset << "\n"; } } while (false)
1240 << CurOffset << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << MRI.getName(CSReg
.Reg) << " saved at " << RegOffset << " but only supported at "
<< CurOffset << "\n"; } } while (false)
;
1241 return CU::UNWIND_ARM_MODE_DWARF;
1242 }
1243 CompactUnwindEncoding |= CSReg.Encoding;
1244 CurOffset -= 4;
1245 }
1246
1247 // If no floats saved, we are done.
1248 if (FloatRegCount == 0)
1249 return CompactUnwindEncoding;
1250
1251 // Switch mode to include D register saving.
1252 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1253 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1254
1255 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1256 // but needs coordination with the linker and libunwind.
1257 if (FloatRegCount > 4) {
1258 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "unsupported number of D registers saved ("
<< FloatRegCount << ")\n"; } } while (false)
1259 llvm::dbgs() << "unsupported number of D registers saved ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "unsupported number of D registers saved ("
<< FloatRegCount << ")\n"; } } while (false)
1260 << FloatRegCount << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << "unsupported number of D registers saved ("
<< FloatRegCount << ")\n"; } } while (false)
;
1261 return CU::UNWIND_ARM_MODE_DWARF;
1262 }
1263
1264 // Floating point registers must either be saved sequentially, or we defer to
1265 // DWARF. No gaps allowed here so check that each saved d-register is
1266 // precisely where it should be.
1267 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1268 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1269 auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1270 if (Offset == RegOffsets.end()) {
1271 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" not saved\n"; } } while (false)
1272 llvm::dbgs() << FloatRegCount << " D-regs saved, but "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" not saved\n"; } } while (false)
1273 << MRI.getName(FPRCSRegs[Idx])do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" not saved\n"; } } while (false)
1274 << " not saved\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" not saved\n"; } } while (false)
;
1275 return CU::UNWIND_ARM_MODE_DWARF;
1276 } else if (Offset->second != CurOffset - 8) {
1277 DEBUG_WITH_TYPE("compact-unwind",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
1278 llvm::dbgs() << FloatRegCount << " D-regs saved, but "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
1279 << MRI.getName(FPRCSRegs[Idx])do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
1280 << " saved at " << Offset->seconddo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
1281 << ", expected at " << CurOffset - 8do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
1282 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("compact-unwind")) { llvm::dbgs() << FloatRegCount <<
" D-regs saved, but " << MRI.getName(FPRCSRegs[Idx]) <<
" saved at " << Offset->second << ", expected at "
<< CurOffset - 8 << "\n"; } } while (false)
;
1283 return CU::UNWIND_ARM_MODE_DWARF;
1284 }
1285 CurOffset -= 8;
1286 }
1287
1288 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1289}
1290
1291static MCAsmBackend *createARMAsmBackend(const Target &T,
1292 const MCSubtargetInfo &STI,
1293 const MCRegisterInfo &MRI,
1294 const MCTargetOptions &Options,
1295 support::endianness Endian) {
1296 const Triple &TheTriple = STI.getTargetTriple();
1297 switch (TheTriple.getObjectFormat()) {
1298 default:
1299 llvm_unreachable("unsupported object format")::llvm::llvm_unreachable_internal("unsupported object format"
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1299)
;
1300 case Triple::MachO:
1301 return new ARMAsmBackendDarwin(T, STI, MRI);
1302 case Triple::COFF:
1303 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported")(static_cast <bool> (TheTriple.isOSWindows() &&
"non-Windows ARM COFF is not supported") ? void (0) : __assert_fail
("TheTriple.isOSWindows() && \"non-Windows ARM COFF is not supported\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1303,
__extension__ __PRETTY_FUNCTION__))
;
1304 return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
1305 case Triple::ELF:
1306 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target")(static_cast <bool> (TheTriple.isOSBinFormatELF() &&
"using ELF for non-ELF target") ? void (0) : __assert_fail (
"TheTriple.isOSBinFormatELF() && \"using ELF for non-ELF target\""
, "llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp", 1306,
__extension__ __PRETTY_FUNCTION__))
;
1307 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1308 return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
1309 Endian);
1310 }
1311}
1312
1313MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
1314 const MCSubtargetInfo &STI,
1315 const MCRegisterInfo &MRI,
1316 const MCTargetOptions &Options) {
1317 return createARMAsmBackend(T, STI, MRI, Options, support::little);
1318}
1319
1320MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
1321 const MCSubtargetInfo &STI,
1322 const MCRegisterInfo &MRI,
1323 const MCTargetOptions &Options) {
1324 return createARMAsmBackend(T, STI, MRI, Options, support::big);
1325}