File: | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp |
Warning: | line 2977, column 19 Called C++ object pointer is null |
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1 | //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | ||||
9 | #include "ARMFeatures.h" | |||
10 | #include "ARMBaseInstrInfo.h" | |||
11 | #include "Utils/ARMBaseInfo.h" | |||
12 | #include "MCTargetDesc/ARMAddressingModes.h" | |||
13 | #include "MCTargetDesc/ARMBaseInfo.h" | |||
14 | #include "MCTargetDesc/ARMInstPrinter.h" | |||
15 | #include "MCTargetDesc/ARMMCExpr.h" | |||
16 | #include "MCTargetDesc/ARMMCTargetDesc.h" | |||
17 | #include "TargetInfo/ARMTargetInfo.h" | |||
18 | #include "llvm/ADT/APFloat.h" | |||
19 | #include "llvm/ADT/APInt.h" | |||
20 | #include "llvm/ADT/None.h" | |||
21 | #include "llvm/ADT/STLExtras.h" | |||
22 | #include "llvm/ADT/SmallSet.h" | |||
23 | #include "llvm/ADT/SmallVector.h" | |||
24 | #include "llvm/ADT/StringMap.h" | |||
25 | #include "llvm/ADT/StringSet.h" | |||
26 | #include "llvm/ADT/StringRef.h" | |||
27 | #include "llvm/ADT/StringSwitch.h" | |||
28 | #include "llvm/ADT/Triple.h" | |||
29 | #include "llvm/ADT/Twine.h" | |||
30 | #include "llvm/MC/MCContext.h" | |||
31 | #include "llvm/MC/MCExpr.h" | |||
32 | #include "llvm/MC/MCInst.h" | |||
33 | #include "llvm/MC/MCInstrDesc.h" | |||
34 | #include "llvm/MC/MCInstrInfo.h" | |||
35 | #include "llvm/MC/MCParser/MCAsmLexer.h" | |||
36 | #include "llvm/MC/MCParser/MCAsmParser.h" | |||
37 | #include "llvm/MC/MCParser/MCAsmParserExtension.h" | |||
38 | #include "llvm/MC/MCParser/MCAsmParserUtils.h" | |||
39 | #include "llvm/MC/MCParser/MCParsedAsmOperand.h" | |||
40 | #include "llvm/MC/MCParser/MCTargetAsmParser.h" | |||
41 | #include "llvm/MC/MCRegisterInfo.h" | |||
42 | #include "llvm/MC/MCSection.h" | |||
43 | #include "llvm/MC/MCStreamer.h" | |||
44 | #include "llvm/MC/MCSubtargetInfo.h" | |||
45 | #include "llvm/MC/MCSymbol.h" | |||
46 | #include "llvm/MC/SubtargetFeature.h" | |||
47 | #include "llvm/Support/ARMBuildAttributes.h" | |||
48 | #include "llvm/Support/ARMEHABI.h" | |||
49 | #include "llvm/Support/Casting.h" | |||
50 | #include "llvm/Support/CommandLine.h" | |||
51 | #include "llvm/Support/Compiler.h" | |||
52 | #include "llvm/Support/ErrorHandling.h" | |||
53 | #include "llvm/Support/MathExtras.h" | |||
54 | #include "llvm/Support/SMLoc.h" | |||
55 | #include "llvm/Support/TargetParser.h" | |||
56 | #include "llvm/Support/TargetRegistry.h" | |||
57 | #include "llvm/Support/raw_ostream.h" | |||
58 | #include <algorithm> | |||
59 | #include <cassert> | |||
60 | #include <cstddef> | |||
61 | #include <cstdint> | |||
62 | #include <iterator> | |||
63 | #include <limits> | |||
64 | #include <memory> | |||
65 | #include <string> | |||
66 | #include <utility> | |||
67 | #include <vector> | |||
68 | ||||
69 | #define DEBUG_TYPE"asm-parser" "asm-parser" | |||
70 | ||||
71 | using namespace llvm; | |||
72 | ||||
73 | namespace llvm { | |||
74 | extern const MCInstrDesc ARMInsts[]; | |||
75 | } // end namespace llvm | |||
76 | ||||
77 | namespace { | |||
78 | ||||
79 | enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly }; | |||
80 | ||||
81 | static cl::opt<ImplicitItModeTy> ImplicitItMode( | |||
82 | "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), | |||
83 | cl::desc("Allow conditional instructions outdside of an IT block"), | |||
84 | cl::values(clEnumValN(ImplicitItModeTy::Always, "always",llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always ), "Accept in both ISAs, emit implicit ITs in Thumb" } | |||
85 | "Accept in both ISAs, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always ), "Accept in both ISAs, emit implicit ITs in Thumb" }, | |||
86 | clEnumValN(ImplicitItModeTy::Never, "never",llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never ), "Warn in ARM, reject in Thumb" } | |||
87 | "Warn in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never ), "Warn in ARM, reject in Thumb" }, | |||
88 | clEnumValN(ImplicitItModeTy::ARMOnly, "arm",llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly ), "Accept in ARM, reject in Thumb" } | |||
89 | "Accept in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly ), "Accept in ARM, reject in Thumb" }, | |||
90 | clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly ), "Warn in ARM, emit implicit ITs in Thumb" } | |||
91 | "Warn in ARM, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly ), "Warn in ARM, emit implicit ITs in Thumb" })); | |||
92 | ||||
93 | static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes", | |||
94 | cl::init(false)); | |||
95 | ||||
96 | enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; | |||
97 | ||||
98 | static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { | |||
99 | // Position==0 means we're not in an IT block at all. Position==1 | |||
100 | // means we want the first state bit, which is always 0 (Then). | |||
101 | // Position==2 means we want the second state bit, stored at bit 3 | |||
102 | // of Mask, and so on downwards. So (5 - Position) will shift the | |||
103 | // right bit down to bit 0, including the always-0 bit at bit 4 for | |||
104 | // the mandatory initial Then. | |||
105 | return (Mask >> (5 - Position) & 1); | |||
106 | } | |||
107 | ||||
108 | class UnwindContext { | |||
109 | using Locs = SmallVector<SMLoc, 4>; | |||
110 | ||||
111 | MCAsmParser &Parser; | |||
112 | Locs FnStartLocs; | |||
113 | Locs CantUnwindLocs; | |||
114 | Locs PersonalityLocs; | |||
115 | Locs PersonalityIndexLocs; | |||
116 | Locs HandlerDataLocs; | |||
117 | int FPReg; | |||
118 | ||||
119 | public: | |||
120 | UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} | |||
121 | ||||
122 | bool hasFnStart() const { return !FnStartLocs.empty(); } | |||
123 | bool cantUnwind() const { return !CantUnwindLocs.empty(); } | |||
124 | bool hasHandlerData() const { return !HandlerDataLocs.empty(); } | |||
125 | ||||
126 | bool hasPersonality() const { | |||
127 | return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); | |||
128 | } | |||
129 | ||||
130 | void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } | |||
131 | void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } | |||
132 | void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } | |||
133 | void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } | |||
134 | void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } | |||
135 | ||||
136 | void saveFPReg(int Reg) { FPReg = Reg; } | |||
137 | int getFPReg() const { return FPReg; } | |||
138 | ||||
139 | void emitFnStartLocNotes() const { | |||
140 | for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); | |||
141 | FI != FE; ++FI) | |||
142 | Parser.Note(*FI, ".fnstart was specified here"); | |||
143 | } | |||
144 | ||||
145 | void emitCantUnwindLocNotes() const { | |||
146 | for (Locs::const_iterator UI = CantUnwindLocs.begin(), | |||
147 | UE = CantUnwindLocs.end(); UI != UE; ++UI) | |||
148 | Parser.Note(*UI, ".cantunwind was specified here"); | |||
149 | } | |||
150 | ||||
151 | void emitHandlerDataLocNotes() const { | |||
152 | for (Locs::const_iterator HI = HandlerDataLocs.begin(), | |||
153 | HE = HandlerDataLocs.end(); HI != HE; ++HI) | |||
154 | Parser.Note(*HI, ".handlerdata was specified here"); | |||
155 | } | |||
156 | ||||
157 | void emitPersonalityLocNotes() const { | |||
158 | for (Locs::const_iterator PI = PersonalityLocs.begin(), | |||
159 | PE = PersonalityLocs.end(), | |||
160 | PII = PersonalityIndexLocs.begin(), | |||
161 | PIE = PersonalityIndexLocs.end(); | |||
162 | PI != PE || PII != PIE;) { | |||
163 | if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) | |||
164 | Parser.Note(*PI++, ".personality was specified here"); | |||
165 | else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) | |||
166 | Parser.Note(*PII++, ".personalityindex was specified here"); | |||
167 | else | |||
168 | llvm_unreachable(".personality and .personalityindex cannot be "__builtin_unreachable() | |||
169 | "at the same location")__builtin_unreachable(); | |||
170 | } | |||
171 | } | |||
172 | ||||
173 | void reset() { | |||
174 | FnStartLocs = Locs(); | |||
175 | CantUnwindLocs = Locs(); | |||
176 | PersonalityLocs = Locs(); | |||
177 | HandlerDataLocs = Locs(); | |||
178 | PersonalityIndexLocs = Locs(); | |||
179 | FPReg = ARM::SP; | |||
180 | } | |||
181 | }; | |||
182 | ||||
183 | // Various sets of ARM instruction mnemonics which are used by the asm parser | |||
184 | class ARMMnemonicSets { | |||
185 | StringSet<> CDE; | |||
186 | StringSet<> CDEWithVPTSuffix; | |||
187 | public: | |||
188 | ARMMnemonicSets(const MCSubtargetInfo &STI); | |||
189 | ||||
190 | /// Returns true iff a given mnemonic is a CDE instruction | |||
191 | bool isCDEInstr(StringRef Mnemonic) { | |||
192 | // Quick check before searching the set | |||
193 | if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx")) | |||
194 | return false; | |||
195 | return CDE.count(Mnemonic); | |||
196 | } | |||
197 | ||||
198 | /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction | |||
199 | /// (possibly with a predication suffix "e" or "t") | |||
200 | bool isVPTPredicableCDEInstr(StringRef Mnemonic) { | |||
201 | if (!Mnemonic.startswith("vcx")) | |||
202 | return false; | |||
203 | return CDEWithVPTSuffix.count(Mnemonic); | |||
204 | } | |||
205 | ||||
206 | /// Returns true iff a given mnemonic is an IT-predicable CDE instruction | |||
207 | /// (possibly with a condition suffix) | |||
208 | bool isITPredicableCDEInstr(StringRef Mnemonic) { | |||
209 | if (!Mnemonic.startswith("cx")) | |||
210 | return false; | |||
211 | return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") || | |||
212 | Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") || | |||
213 | Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da"); | |||
214 | } | |||
215 | ||||
216 | /// Return true iff a given mnemonic is an integer CDE instruction with | |||
217 | /// dual-register destination | |||
218 | bool isCDEDualRegInstr(StringRef Mnemonic) { | |||
219 | if (!Mnemonic.startswith("cx")) | |||
220 | return false; | |||
221 | return Mnemonic == "cx1d" || Mnemonic == "cx1da" || | |||
222 | Mnemonic == "cx2d" || Mnemonic == "cx2da" || | |||
223 | Mnemonic == "cx3d" || Mnemonic == "cx3da"; | |||
224 | } | |||
225 | }; | |||
226 | ||||
227 | ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) { | |||
228 | for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da", | |||
229 | "cx2", "cx2a", "cx2d", "cx2da", | |||
230 | "cx3", "cx3a", "cx3d", "cx3da", }) | |||
231 | CDE.insert(Mnemonic); | |||
232 | for (StringRef Mnemonic : | |||
233 | {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) { | |||
234 | CDE.insert(Mnemonic); | |||
235 | CDEWithVPTSuffix.insert(Mnemonic); | |||
236 | CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t"); | |||
237 | CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e"); | |||
238 | } | |||
239 | } | |||
240 | ||||
241 | class ARMAsmParser : public MCTargetAsmParser { | |||
242 | const MCRegisterInfo *MRI; | |||
243 | UnwindContext UC; | |||
244 | ARMMnemonicSets MS; | |||
245 | ||||
246 | ARMTargetStreamer &getTargetStreamer() { | |||
247 | assert(getParser().getStreamer().getTargetStreamer() &&(static_cast<void> (0)) | |||
248 | "do not have a target streamer")(static_cast<void> (0)); | |||
249 | MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); | |||
250 | return static_cast<ARMTargetStreamer &>(TS); | |||
251 | } | |||
252 | ||||
253 | // Map of register aliases registers via the .req directive. | |||
254 | StringMap<unsigned> RegisterReqs; | |||
255 | ||||
256 | bool NextSymbolIsThumb; | |||
257 | ||||
258 | bool useImplicitITThumb() const { | |||
259 | return ImplicitItMode == ImplicitItModeTy::Always || | |||
260 | ImplicitItMode == ImplicitItModeTy::ThumbOnly; | |||
261 | } | |||
262 | ||||
263 | bool useImplicitITARM() const { | |||
264 | return ImplicitItMode == ImplicitItModeTy::Always || | |||
265 | ImplicitItMode == ImplicitItModeTy::ARMOnly; | |||
266 | } | |||
267 | ||||
268 | struct { | |||
269 | ARMCC::CondCodes Cond; // Condition for IT block. | |||
270 | unsigned Mask:4; // Condition mask for instructions. | |||
271 | // Starting at first 1 (from lsb). | |||
272 | // '1' condition as indicated in IT. | |||
273 | // '0' inverse of condition (else). | |||
274 | // Count of instructions in IT block is | |||
275 | // 4 - trailingzeroes(mask) | |||
276 | // Note that this does not have the same encoding | |||
277 | // as in the IT instruction, which also depends | |||
278 | // on the low bit of the condition code. | |||
279 | ||||
280 | unsigned CurPosition; // Current position in parsing of IT | |||
281 | // block. In range [0,4], with 0 being the IT | |||
282 | // instruction itself. Initialized according to | |||
283 | // count of instructions in block. ~0U if no | |||
284 | // active IT block. | |||
285 | ||||
286 | bool IsExplicit; // true - The IT instruction was present in the | |||
287 | // input, we should not modify it. | |||
288 | // false - The IT instruction was added | |||
289 | // implicitly, we can extend it if that | |||
290 | // would be legal. | |||
291 | } ITState; | |||
292 | ||||
293 | SmallVector<MCInst, 4> PendingConditionalInsts; | |||
294 | ||||
295 | void flushPendingInstructions(MCStreamer &Out) override { | |||
296 | if (!inImplicitITBlock()) { | |||
297 | assert(PendingConditionalInsts.size() == 0)(static_cast<void> (0)); | |||
298 | return; | |||
299 | } | |||
300 | ||||
301 | // Emit the IT instruction | |||
302 | MCInst ITInst; | |||
303 | ITInst.setOpcode(ARM::t2IT); | |||
304 | ITInst.addOperand(MCOperand::createImm(ITState.Cond)); | |||
305 | ITInst.addOperand(MCOperand::createImm(ITState.Mask)); | |||
306 | Out.emitInstruction(ITInst, getSTI()); | |||
307 | ||||
308 | // Emit the conditonal instructions | |||
309 | assert(PendingConditionalInsts.size() <= 4)(static_cast<void> (0)); | |||
310 | for (const MCInst &Inst : PendingConditionalInsts) { | |||
311 | Out.emitInstruction(Inst, getSTI()); | |||
312 | } | |||
313 | PendingConditionalInsts.clear(); | |||
314 | ||||
315 | // Clear the IT state | |||
316 | ITState.Mask = 0; | |||
317 | ITState.CurPosition = ~0U; | |||
318 | } | |||
319 | ||||
320 | bool inITBlock() { return ITState.CurPosition != ~0U; } | |||
321 | bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; } | |||
322 | bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; } | |||
323 | ||||
324 | bool lastInITBlock() { | |||
325 | return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); | |||
326 | } | |||
327 | ||||
328 | void forwardITPosition() { | |||
329 | if (!inITBlock()) return; | |||
330 | // Move to the next instruction in the IT block, if there is one. If not, | |||
331 | // mark the block as done, except for implicit IT blocks, which we leave | |||
332 | // open until we find an instruction that can't be added to it. | |||
333 | unsigned TZ = countTrailingZeros(ITState.Mask); | |||
334 | if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit) | |||
335 | ITState.CurPosition = ~0U; // Done with the IT block after this. | |||
336 | } | |||
337 | ||||
338 | // Rewind the state of the current IT block, removing the last slot from it. | |||
339 | void rewindImplicitITPosition() { | |||
340 | assert(inImplicitITBlock())(static_cast<void> (0)); | |||
341 | assert(ITState.CurPosition > 1)(static_cast<void> (0)); | |||
342 | ITState.CurPosition--; | |||
343 | unsigned TZ = countTrailingZeros(ITState.Mask); | |||
344 | unsigned NewMask = 0; | |||
345 | NewMask |= ITState.Mask & (0xC << TZ); | |||
346 | NewMask |= 0x2 << TZ; | |||
347 | ITState.Mask = NewMask; | |||
348 | } | |||
349 | ||||
350 | // Rewind the state of the current IT block, removing the last slot from it. | |||
351 | // If we were at the first slot, this closes the IT block. | |||
352 | void discardImplicitITBlock() { | |||
353 | assert(inImplicitITBlock())(static_cast<void> (0)); | |||
354 | assert(ITState.CurPosition == 1)(static_cast<void> (0)); | |||
355 | ITState.CurPosition = ~0U; | |||
356 | } | |||
357 | ||||
358 | // Return the low-subreg of a given Q register. | |||
359 | unsigned getDRegFromQReg(unsigned QReg) const { | |||
360 | return MRI->getSubReg(QReg, ARM::dsub_0); | |||
361 | } | |||
362 | ||||
363 | // Get the condition code corresponding to the current IT block slot. | |||
364 | ARMCC::CondCodes currentITCond() { | |||
365 | unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition); | |||
366 | return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond; | |||
367 | } | |||
368 | ||||
369 | // Invert the condition of the current IT block slot without changing any | |||
370 | // other slots in the same block. | |||
371 | void invertCurrentITCondition() { | |||
372 | if (ITState.CurPosition == 1) { | |||
373 | ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond); | |||
374 | } else { | |||
375 | ITState.Mask ^= 1 << (5 - ITState.CurPosition); | |||
376 | } | |||
377 | } | |||
378 | ||||
379 | // Returns true if the current IT block is full (all 4 slots used). | |||
380 | bool isITBlockFull() { | |||
381 | return inITBlock() && (ITState.Mask & 1); | |||
382 | } | |||
383 | ||||
384 | // Extend the current implicit IT block to have one more slot with the given | |||
385 | // condition code. | |||
386 | void extendImplicitITBlock(ARMCC::CondCodes Cond) { | |||
387 | assert(inImplicitITBlock())(static_cast<void> (0)); | |||
388 | assert(!isITBlockFull())(static_cast<void> (0)); | |||
389 | assert(Cond == ITState.Cond ||(static_cast<void> (0)) | |||
390 | Cond == ARMCC::getOppositeCondition(ITState.Cond))(static_cast<void> (0)); | |||
391 | unsigned TZ = countTrailingZeros(ITState.Mask); | |||
392 | unsigned NewMask = 0; | |||
393 | // Keep any existing condition bits. | |||
394 | NewMask |= ITState.Mask & (0xE << TZ); | |||
395 | // Insert the new condition bit. | |||
396 | NewMask |= (Cond != ITState.Cond) << TZ; | |||
397 | // Move the trailing 1 down one bit. | |||
398 | NewMask |= 1 << (TZ - 1); | |||
399 | ITState.Mask = NewMask; | |||
400 | } | |||
401 | ||||
402 | // Create a new implicit IT block with a dummy condition code. | |||
403 | void startImplicitITBlock() { | |||
404 | assert(!inITBlock())(static_cast<void> (0)); | |||
405 | ITState.Cond = ARMCC::AL; | |||
406 | ITState.Mask = 8; | |||
407 | ITState.CurPosition = 1; | |||
408 | ITState.IsExplicit = false; | |||
409 | } | |||
410 | ||||
411 | // Create a new explicit IT block with the given condition and mask. | |||
412 | // The mask should be in the format used in ARMOperand and | |||
413 | // MCOperand, with a 1 implying 'e', regardless of the low bit of | |||
414 | // the condition. | |||
415 | void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) { | |||
416 | assert(!inITBlock())(static_cast<void> (0)); | |||
417 | ITState.Cond = Cond; | |||
418 | ITState.Mask = Mask; | |||
419 | ITState.CurPosition = 0; | |||
420 | ITState.IsExplicit = true; | |||
421 | } | |||
422 | ||||
423 | struct { | |||
424 | unsigned Mask : 4; | |||
425 | unsigned CurPosition; | |||
426 | } VPTState; | |||
427 | bool inVPTBlock() { return VPTState.CurPosition != ~0U; } | |||
428 | void forwardVPTPosition() { | |||
429 | if (!inVPTBlock()) return; | |||
430 | unsigned TZ = countTrailingZeros(VPTState.Mask); | |||
431 | if (++VPTState.CurPosition == 5 - TZ) | |||
432 | VPTState.CurPosition = ~0U; | |||
433 | } | |||
434 | ||||
435 | void Note(SMLoc L, const Twine &Msg, SMRange Range = None) { | |||
436 | return getParser().Note(L, Msg, Range); | |||
437 | } | |||
438 | ||||
439 | bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) { | |||
440 | return getParser().Warning(L, Msg, Range); | |||
441 | } | |||
442 | ||||
443 | bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) { | |||
444 | return getParser().Error(L, Msg, Range); | |||
445 | } | |||
446 | ||||
447 | bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, | |||
448 | unsigned ListNo, bool IsARPop = false); | |||
449 | bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, | |||
450 | unsigned ListNo); | |||
451 | ||||
452 | int tryParseRegister(); | |||
453 | bool tryParseRegisterWithWriteBack(OperandVector &); | |||
454 | int tryParseShiftRegister(OperandVector &); | |||
455 | bool parseRegisterList(OperandVector &, bool EnforceOrder = true); | |||
456 | bool parseMemory(OperandVector &); | |||
457 | bool parseOperand(OperandVector &, StringRef Mnemonic); | |||
458 | bool parsePrefix(ARMMCExpr::VariantKind &RefKind); | |||
459 | bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, | |||
460 | unsigned &ShiftAmount); | |||
461 | bool parseLiteralValues(unsigned Size, SMLoc L); | |||
462 | bool parseDirectiveThumb(SMLoc L); | |||
463 | bool parseDirectiveARM(SMLoc L); | |||
464 | bool parseDirectiveThumbFunc(SMLoc L); | |||
465 | bool parseDirectiveCode(SMLoc L); | |||
466 | bool parseDirectiveSyntax(SMLoc L); | |||
467 | bool parseDirectiveReq(StringRef Name, SMLoc L); | |||
468 | bool parseDirectiveUnreq(SMLoc L); | |||
469 | bool parseDirectiveArch(SMLoc L); | |||
470 | bool parseDirectiveEabiAttr(SMLoc L); | |||
471 | bool parseDirectiveCPU(SMLoc L); | |||
472 | bool parseDirectiveFPU(SMLoc L); | |||
473 | bool parseDirectiveFnStart(SMLoc L); | |||
474 | bool parseDirectiveFnEnd(SMLoc L); | |||
475 | bool parseDirectiveCantUnwind(SMLoc L); | |||
476 | bool parseDirectivePersonality(SMLoc L); | |||
477 | bool parseDirectiveHandlerData(SMLoc L); | |||
478 | bool parseDirectiveSetFP(SMLoc L); | |||
479 | bool parseDirectivePad(SMLoc L); | |||
480 | bool parseDirectiveRegSave(SMLoc L, bool IsVector); | |||
481 | bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); | |||
482 | bool parseDirectiveLtorg(SMLoc L); | |||
483 | bool parseDirectiveEven(SMLoc L); | |||
484 | bool parseDirectivePersonalityIndex(SMLoc L); | |||
485 | bool parseDirectiveUnwindRaw(SMLoc L); | |||
486 | bool parseDirectiveTLSDescSeq(SMLoc L); | |||
487 | bool parseDirectiveMovSP(SMLoc L); | |||
488 | bool parseDirectiveObjectArch(SMLoc L); | |||
489 | bool parseDirectiveArchExtension(SMLoc L); | |||
490 | bool parseDirectiveAlign(SMLoc L); | |||
491 | bool parseDirectiveThumbSet(SMLoc L); | |||
492 | ||||
493 | bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken); | |||
494 | StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken, | |||
495 | unsigned &PredicationCode, | |||
496 | unsigned &VPTPredicationCode, bool &CarrySetting, | |||
497 | unsigned &ProcessorIMod, StringRef &ITMask); | |||
498 | void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken, | |||
499 | StringRef FullInst, bool &CanAcceptCarrySet, | |||
500 | bool &CanAcceptPredicationCode, | |||
501 | bool &CanAcceptVPTPredicationCode); | |||
502 | bool enableArchExtFeature(StringRef Name, SMLoc &ExtLoc); | |||
503 | ||||
504 | void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, | |||
505 | OperandVector &Operands); | |||
506 | bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands); | |||
507 | ||||
508 | bool isThumb() const { | |||
509 | // FIXME: Can tablegen auto-generate this? | |||
510 | return getSTI().getFeatureBits()[ARM::ModeThumb]; | |||
511 | } | |||
512 | ||||
513 | bool isThumbOne() const { | |||
514 | return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; | |||
515 | } | |||
516 | ||||
517 | bool isThumbTwo() const { | |||
518 | return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; | |||
519 | } | |||
520 | ||||
521 | bool hasThumb() const { | |||
522 | return getSTI().getFeatureBits()[ARM::HasV4TOps]; | |||
523 | } | |||
524 | ||||
525 | bool hasThumb2() const { | |||
526 | return getSTI().getFeatureBits()[ARM::FeatureThumb2]; | |||
527 | } | |||
528 | ||||
529 | bool hasV6Ops() const { | |||
530 | return getSTI().getFeatureBits()[ARM::HasV6Ops]; | |||
531 | } | |||
532 | ||||
533 | bool hasV6T2Ops() const { | |||
534 | return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; | |||
535 | } | |||
536 | ||||
537 | bool hasV6MOps() const { | |||
538 | return getSTI().getFeatureBits()[ARM::HasV6MOps]; | |||
539 | } | |||
540 | ||||
541 | bool hasV7Ops() const { | |||
542 | return getSTI().getFeatureBits()[ARM::HasV7Ops]; | |||
543 | } | |||
544 | ||||
545 | bool hasV8Ops() const { | |||
546 | return getSTI().getFeatureBits()[ARM::HasV8Ops]; | |||
547 | } | |||
548 | ||||
549 | bool hasV8MBaseline() const { | |||
550 | return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; | |||
551 | } | |||
552 | ||||
553 | bool hasV8MMainline() const { | |||
554 | return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; | |||
555 | } | |||
556 | bool hasV8_1MMainline() const { | |||
557 | return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps]; | |||
558 | } | |||
559 | bool hasMVE() const { | |||
560 | return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps]; | |||
561 | } | |||
562 | bool hasMVEFloat() const { | |||
563 | return getSTI().getFeatureBits()[ARM::HasMVEFloatOps]; | |||
564 | } | |||
565 | bool hasCDE() const { | |||
566 | return getSTI().getFeatureBits()[ARM::HasCDEOps]; | |||
567 | } | |||
568 | bool has8MSecExt() const { | |||
569 | return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; | |||
570 | } | |||
571 | ||||
572 | bool hasARM() const { | |||
573 | return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; | |||
574 | } | |||
575 | ||||
576 | bool hasDSP() const { | |||
577 | return getSTI().getFeatureBits()[ARM::FeatureDSP]; | |||
578 | } | |||
579 | ||||
580 | bool hasD32() const { | |||
581 | return getSTI().getFeatureBits()[ARM::FeatureD32]; | |||
582 | } | |||
583 | ||||
584 | bool hasV8_1aOps() const { | |||
585 | return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; | |||
586 | } | |||
587 | ||||
588 | bool hasRAS() const { | |||
589 | return getSTI().getFeatureBits()[ARM::FeatureRAS]; | |||
590 | } | |||
591 | ||||
592 | void SwitchMode() { | |||
593 | MCSubtargetInfo &STI = copySTI(); | |||
594 | auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); | |||
595 | setAvailableFeatures(FB); | |||
596 | } | |||
597 | ||||
598 | void FixModeAfterArchChange(bool WasThumb, SMLoc Loc); | |||
599 | ||||
600 | bool isMClass() const { | |||
601 | return getSTI().getFeatureBits()[ARM::FeatureMClass]; | |||
602 | } | |||
603 | ||||
604 | /// @name Auto-generated Match Functions | |||
605 | /// { | |||
606 | ||||
607 | #define GET_ASSEMBLER_HEADER | |||
608 | #include "ARMGenAsmMatcher.inc" | |||
609 | ||||
610 | /// } | |||
611 | ||||
612 | OperandMatchResultTy parseITCondCode(OperandVector &); | |||
613 | OperandMatchResultTy parseCoprocNumOperand(OperandVector &); | |||
614 | OperandMatchResultTy parseCoprocRegOperand(OperandVector &); | |||
615 | OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); | |||
616 | OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); | |||
617 | OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &); | |||
618 | OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); | |||
619 | OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); | |||
620 | OperandMatchResultTy parseMSRMaskOperand(OperandVector &); | |||
621 | OperandMatchResultTy parseBankedRegOperand(OperandVector &); | |||
622 | OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, | |||
623 | int High); | |||
624 | OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { | |||
625 | return parsePKHImm(O, "lsl", 0, 31); | |||
626 | } | |||
627 | OperandMatchResultTy parsePKHASRImm(OperandVector &O) { | |||
628 | return parsePKHImm(O, "asr", 1, 32); | |||
629 | } | |||
630 | OperandMatchResultTy parseSetEndImm(OperandVector &); | |||
631 | OperandMatchResultTy parseShifterImm(OperandVector &); | |||
632 | OperandMatchResultTy parseRotImm(OperandVector &); | |||
633 | OperandMatchResultTy parseModImm(OperandVector &); | |||
634 | OperandMatchResultTy parseBitfield(OperandVector &); | |||
635 | OperandMatchResultTy parsePostIdxReg(OperandVector &); | |||
636 | OperandMatchResultTy parseAM3Offset(OperandVector &); | |||
637 | OperandMatchResultTy parseFPImm(OperandVector &); | |||
638 | OperandMatchResultTy parseVectorList(OperandVector &); | |||
639 | OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, | |||
640 | SMLoc &EndLoc); | |||
641 | ||||
642 | // Asm Match Converter Methods | |||
643 | void cvtThumbMultiply(MCInst &Inst, const OperandVector &); | |||
644 | void cvtThumbBranches(MCInst &Inst, const OperandVector &); | |||
645 | void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &); | |||
646 | ||||
647 | bool validateInstruction(MCInst &Inst, const OperandVector &Ops); | |||
648 | bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); | |||
649 | bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); | |||
650 | bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); | |||
651 | bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands); | |||
652 | bool isITBlockTerminator(MCInst &Inst) const; | |||
653 | void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands); | |||
654 | bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, | |||
655 | bool Load, bool ARMMode, bool Writeback); | |||
656 | ||||
657 | public: | |||
658 | enum ARMMatchResultTy { | |||
659 | Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, | |||
660 | Match_RequiresNotITBlock, | |||
661 | Match_RequiresV6, | |||
662 | Match_RequiresThumb2, | |||
663 | Match_RequiresV8, | |||
664 | Match_RequiresFlagSetting, | |||
665 | #define GET_OPERAND_DIAGNOSTIC_TYPES | |||
666 | #include "ARMGenAsmMatcher.inc" | |||
667 | ||||
668 | }; | |||
669 | ||||
670 | ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, | |||
671 | const MCInstrInfo &MII, const MCTargetOptions &Options) | |||
672 | : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) { | |||
673 | MCAsmParserExtension::Initialize(Parser); | |||
674 | ||||
675 | // Cache the MCRegisterInfo. | |||
676 | MRI = getContext().getRegisterInfo(); | |||
677 | ||||
678 | // Initialize the set of available features. | |||
679 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); | |||
680 | ||||
681 | // Add build attributes based on the selected target. | |||
682 | if (AddBuildAttributes) | |||
683 | getTargetStreamer().emitTargetAttributes(STI); | |||
684 | ||||
685 | // Not in an ITBlock to start with. | |||
686 | ITState.CurPosition = ~0U; | |||
687 | ||||
688 | VPTState.CurPosition = ~0U; | |||
689 | ||||
690 | NextSymbolIsThumb = false; | |||
691 | } | |||
692 | ||||
693 | // Implementation of the MCTargetAsmParser interface: | |||
694 | bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; | |||
695 | OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, | |||
696 | SMLoc &EndLoc) override; | |||
697 | bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, | |||
698 | SMLoc NameLoc, OperandVector &Operands) override; | |||
699 | bool ParseDirective(AsmToken DirectiveID) override; | |||
700 | ||||
701 | unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, | |||
702 | unsigned Kind) override; | |||
703 | unsigned checkTargetMatchPredicate(MCInst &Inst) override; | |||
704 | ||||
705 | bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |||
706 | OperandVector &Operands, MCStreamer &Out, | |||
707 | uint64_t &ErrorInfo, | |||
708 | bool MatchingInlineAsm) override; | |||
709 | unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst, | |||
710 | SmallVectorImpl<NearMissInfo> &NearMisses, | |||
711 | bool MatchingInlineAsm, bool &EmitInITBlock, | |||
712 | MCStreamer &Out); | |||
713 | ||||
714 | struct NearMissMessage { | |||
715 | SMLoc Loc; | |||
716 | SmallString<128> Message; | |||
717 | }; | |||
718 | ||||
719 | const char *getCustomOperandDiag(ARMMatchResultTy MatchError); | |||
720 | ||||
721 | void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, | |||
722 | SmallVectorImpl<NearMissMessage> &NearMissesOut, | |||
723 | SMLoc IDLoc, OperandVector &Operands); | |||
724 | void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc, | |||
725 | OperandVector &Operands); | |||
726 | ||||
727 | void doBeforeLabelEmit(MCSymbol *Symbol) override; | |||
728 | ||||
729 | void onLabelParsed(MCSymbol *Symbol) override; | |||
730 | }; | |||
731 | ||||
732 | /// ARMOperand - Instances of this class represent a parsed ARM machine | |||
733 | /// operand. | |||
734 | class ARMOperand : public MCParsedAsmOperand { | |||
735 | enum KindTy { | |||
736 | k_CondCode, | |||
737 | k_VPTPred, | |||
738 | k_CCOut, | |||
739 | k_ITCondMask, | |||
740 | k_CoprocNum, | |||
741 | k_CoprocReg, | |||
742 | k_CoprocOption, | |||
743 | k_Immediate, | |||
744 | k_MemBarrierOpt, | |||
745 | k_InstSyncBarrierOpt, | |||
746 | k_TraceSyncBarrierOpt, | |||
747 | k_Memory, | |||
748 | k_PostIndexRegister, | |||
749 | k_MSRMask, | |||
750 | k_BankedReg, | |||
751 | k_ProcIFlags, | |||
752 | k_VectorIndex, | |||
753 | k_Register, | |||
754 | k_RegisterList, | |||
755 | k_RegisterListWithAPSR, | |||
756 | k_DPRRegisterList, | |||
757 | k_SPRRegisterList, | |||
758 | k_FPSRegisterListWithVPR, | |||
759 | k_FPDRegisterListWithVPR, | |||
760 | k_VectorList, | |||
761 | k_VectorListAllLanes, | |||
762 | k_VectorListIndexed, | |||
763 | k_ShiftedRegister, | |||
764 | k_ShiftedImmediate, | |||
765 | k_ShifterImmediate, | |||
766 | k_RotateImmediate, | |||
767 | k_ModifiedImmediate, | |||
768 | k_ConstantPoolImmediate, | |||
769 | k_BitfieldDescriptor, | |||
770 | k_Token, | |||
771 | } Kind; | |||
772 | ||||
773 | SMLoc StartLoc, EndLoc, AlignmentLoc; | |||
774 | SmallVector<unsigned, 8> Registers; | |||
775 | ||||
776 | struct CCOp { | |||
777 | ARMCC::CondCodes Val; | |||
778 | }; | |||
779 | ||||
780 | struct VCCOp { | |||
781 | ARMVCC::VPTCodes Val; | |||
782 | }; | |||
783 | ||||
784 | struct CopOp { | |||
785 | unsigned Val; | |||
786 | }; | |||
787 | ||||
788 | struct CoprocOptionOp { | |||
789 | unsigned Val; | |||
790 | }; | |||
791 | ||||
792 | struct ITMaskOp { | |||
793 | unsigned Mask:4; | |||
794 | }; | |||
795 | ||||
796 | struct MBOptOp { | |||
797 | ARM_MB::MemBOpt Val; | |||
798 | }; | |||
799 | ||||
800 | struct ISBOptOp { | |||
801 | ARM_ISB::InstSyncBOpt Val; | |||
802 | }; | |||
803 | ||||
804 | struct TSBOptOp { | |||
805 | ARM_TSB::TraceSyncBOpt Val; | |||
806 | }; | |||
807 | ||||
808 | struct IFlagsOp { | |||
809 | ARM_PROC::IFlags Val; | |||
810 | }; | |||
811 | ||||
812 | struct MMaskOp { | |||
813 | unsigned Val; | |||
814 | }; | |||
815 | ||||
816 | struct BankedRegOp { | |||
817 | unsigned Val; | |||
818 | }; | |||
819 | ||||
820 | struct TokOp { | |||
821 | const char *Data; | |||
822 | unsigned Length; | |||
823 | }; | |||
824 | ||||
825 | struct RegOp { | |||
826 | unsigned RegNum; | |||
827 | }; | |||
828 | ||||
829 | // A vector register list is a sequential list of 1 to 4 registers. | |||
830 | struct VectorListOp { | |||
831 | unsigned RegNum; | |||
832 | unsigned Count; | |||
833 | unsigned LaneIndex; | |||
834 | bool isDoubleSpaced; | |||
835 | }; | |||
836 | ||||
837 | struct VectorIndexOp { | |||
838 | unsigned Val; | |||
839 | }; | |||
840 | ||||
841 | struct ImmOp { | |||
842 | const MCExpr *Val; | |||
843 | }; | |||
844 | ||||
845 | /// Combined record for all forms of ARM address expressions. | |||
846 | struct MemoryOp { | |||
847 | unsigned BaseRegNum; | |||
848 | // Offset is in OffsetReg or OffsetImm. If both are zero, no offset | |||
849 | // was specified. | |||
850 | const MCExpr *OffsetImm; // Offset immediate value | |||
851 | unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL | |||
852 | ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg | |||
853 | unsigned ShiftImm; // shift for OffsetReg. | |||
854 | unsigned Alignment; // 0 = no alignment specified | |||
855 | // n = alignment in bytes (2, 4, 8, 16, or 32) | |||
856 | unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) | |||
857 | }; | |||
858 | ||||
859 | struct PostIdxRegOp { | |||
860 | unsigned RegNum; | |||
861 | bool isAdd; | |||
862 | ARM_AM::ShiftOpc ShiftTy; | |||
863 | unsigned ShiftImm; | |||
864 | }; | |||
865 | ||||
866 | struct ShifterImmOp { | |||
867 | bool isASR; | |||
868 | unsigned Imm; | |||
869 | }; | |||
870 | ||||
871 | struct RegShiftedRegOp { | |||
872 | ARM_AM::ShiftOpc ShiftTy; | |||
873 | unsigned SrcReg; | |||
874 | unsigned ShiftReg; | |||
875 | unsigned ShiftImm; | |||
876 | }; | |||
877 | ||||
878 | struct RegShiftedImmOp { | |||
879 | ARM_AM::ShiftOpc ShiftTy; | |||
880 | unsigned SrcReg; | |||
881 | unsigned ShiftImm; | |||
882 | }; | |||
883 | ||||
884 | struct RotImmOp { | |||
885 | unsigned Imm; | |||
886 | }; | |||
887 | ||||
888 | struct ModImmOp { | |||
889 | unsigned Bits; | |||
890 | unsigned Rot; | |||
891 | }; | |||
892 | ||||
893 | struct BitfieldOp { | |||
894 | unsigned LSB; | |||
895 | unsigned Width; | |||
896 | }; | |||
897 | ||||
898 | union { | |||
899 | struct CCOp CC; | |||
900 | struct VCCOp VCC; | |||
901 | struct CopOp Cop; | |||
902 | struct CoprocOptionOp CoprocOption; | |||
903 | struct MBOptOp MBOpt; | |||
904 | struct ISBOptOp ISBOpt; | |||
905 | struct TSBOptOp TSBOpt; | |||
906 | struct ITMaskOp ITMask; | |||
907 | struct IFlagsOp IFlags; | |||
908 | struct MMaskOp MMask; | |||
909 | struct BankedRegOp BankedReg; | |||
910 | struct TokOp Tok; | |||
911 | struct RegOp Reg; | |||
912 | struct VectorListOp VectorList; | |||
913 | struct VectorIndexOp VectorIndex; | |||
914 | struct ImmOp Imm; | |||
915 | struct MemoryOp Memory; | |||
916 | struct PostIdxRegOp PostIdxReg; | |||
917 | struct ShifterImmOp ShifterImm; | |||
918 | struct RegShiftedRegOp RegShiftedReg; | |||
919 | struct RegShiftedImmOp RegShiftedImm; | |||
920 | struct RotImmOp RotImm; | |||
921 | struct ModImmOp ModImm; | |||
922 | struct BitfieldOp Bitfield; | |||
923 | }; | |||
924 | ||||
925 | public: | |||
926 | ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} | |||
927 | ||||
928 | /// getStartLoc - Get the location of the first token of this operand. | |||
929 | SMLoc getStartLoc() const override { return StartLoc; } | |||
930 | ||||
931 | /// getEndLoc - Get the location of the last token of this operand. | |||
932 | SMLoc getEndLoc() const override { return EndLoc; } | |||
933 | ||||
934 | /// getLocRange - Get the range between the first and last token of this | |||
935 | /// operand. | |||
936 | SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } | |||
937 | ||||
938 | /// getAlignmentLoc - Get the location of the Alignment token of this operand. | |||
939 | SMLoc getAlignmentLoc() const { | |||
940 | assert(Kind == k_Memory && "Invalid access!")(static_cast<void> (0)); | |||
941 | return AlignmentLoc; | |||
942 | } | |||
943 | ||||
944 | ARMCC::CondCodes getCondCode() const { | |||
945 | assert(Kind == k_CondCode && "Invalid access!")(static_cast<void> (0)); | |||
946 | return CC.Val; | |||
947 | } | |||
948 | ||||
949 | ARMVCC::VPTCodes getVPTPred() const { | |||
950 | assert(isVPTPred() && "Invalid access!")(static_cast<void> (0)); | |||
951 | return VCC.Val; | |||
952 | } | |||
953 | ||||
954 | unsigned getCoproc() const { | |||
955 | assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!")(static_cast<void> (0)); | |||
956 | return Cop.Val; | |||
957 | } | |||
958 | ||||
959 | StringRef getToken() const { | |||
960 | assert(Kind == k_Token && "Invalid access!")(static_cast<void> (0)); | |||
961 | return StringRef(Tok.Data, Tok.Length); | |||
962 | } | |||
963 | ||||
964 | unsigned getReg() const override { | |||
965 | assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!")(static_cast<void> (0)); | |||
966 | return Reg.RegNum; | |||
967 | } | |||
968 | ||||
969 | const SmallVectorImpl<unsigned> &getRegList() const { | |||
970 | assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||(static_cast<void> (0)) | |||
971 | Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||(static_cast<void> (0)) | |||
972 | Kind == k_FPSRegisterListWithVPR ||(static_cast<void> (0)) | |||
973 | Kind == k_FPDRegisterListWithVPR) &&(static_cast<void> (0)) | |||
974 | "Invalid access!")(static_cast<void> (0)); | |||
975 | return Registers; | |||
976 | } | |||
977 | ||||
978 | const MCExpr *getImm() const { | |||
979 | assert(isImm() && "Invalid access!")(static_cast<void> (0)); | |||
980 | return Imm.Val; | |||
981 | } | |||
982 | ||||
983 | const MCExpr *getConstantPoolImm() const { | |||
984 | assert(isConstantPoolImm() && "Invalid access!")(static_cast<void> (0)); | |||
985 | return Imm.Val; | |||
986 | } | |||
987 | ||||
988 | unsigned getVectorIndex() const { | |||
989 | assert(Kind == k_VectorIndex && "Invalid access!")(static_cast<void> (0)); | |||
990 | return VectorIndex.Val; | |||
991 | } | |||
992 | ||||
993 | ARM_MB::MemBOpt getMemBarrierOpt() const { | |||
994 | assert(Kind == k_MemBarrierOpt && "Invalid access!")(static_cast<void> (0)); | |||
995 | return MBOpt.Val; | |||
996 | } | |||
997 | ||||
998 | ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { | |||
999 | assert(Kind == k_InstSyncBarrierOpt && "Invalid access!")(static_cast<void> (0)); | |||
1000 | return ISBOpt.Val; | |||
1001 | } | |||
1002 | ||||
1003 | ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const { | |||
1004 | assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!")(static_cast<void> (0)); | |||
1005 | return TSBOpt.Val; | |||
1006 | } | |||
1007 | ||||
1008 | ARM_PROC::IFlags getProcIFlags() const { | |||
1009 | assert(Kind == k_ProcIFlags && "Invalid access!")(static_cast<void> (0)); | |||
1010 | return IFlags.Val; | |||
1011 | } | |||
1012 | ||||
1013 | unsigned getMSRMask() const { | |||
1014 | assert(Kind == k_MSRMask && "Invalid access!")(static_cast<void> (0)); | |||
1015 | return MMask.Val; | |||
1016 | } | |||
1017 | ||||
1018 | unsigned getBankedReg() const { | |||
1019 | assert(Kind == k_BankedReg && "Invalid access!")(static_cast<void> (0)); | |||
1020 | return BankedReg.Val; | |||
1021 | } | |||
1022 | ||||
1023 | bool isCoprocNum() const { return Kind == k_CoprocNum; } | |||
1024 | bool isCoprocReg() const { return Kind == k_CoprocReg; } | |||
1025 | bool isCoprocOption() const { return Kind == k_CoprocOption; } | |||
1026 | bool isCondCode() const { return Kind == k_CondCode; } | |||
1027 | bool isVPTPred() const { return Kind == k_VPTPred; } | |||
1028 | bool isCCOut() const { return Kind == k_CCOut; } | |||
1029 | bool isITMask() const { return Kind == k_ITCondMask; } | |||
1030 | bool isITCondCode() const { return Kind == k_CondCode; } | |||
1031 | bool isImm() const override { | |||
1032 | return Kind == k_Immediate; | |||
1033 | } | |||
1034 | ||||
1035 | bool isARMBranchTarget() const { | |||
1036 | if (!isImm()) return false; | |||
1037 | ||||
1038 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) | |||
1039 | return CE->getValue() % 4 == 0; | |||
1040 | return true; | |||
1041 | } | |||
1042 | ||||
1043 | ||||
1044 | bool isThumbBranchTarget() const { | |||
1045 | if (!isImm()) return false; | |||
1046 | ||||
1047 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) | |||
1048 | return CE->getValue() % 2 == 0; | |||
1049 | return true; | |||
1050 | } | |||
1051 | ||||
1052 | // checks whether this operand is an unsigned offset which fits is a field | |||
1053 | // of specified width and scaled by a specific number of bits | |||
1054 | template<unsigned width, unsigned scale> | |||
1055 | bool isUnsignedOffset() const { | |||
1056 | if (!isImm()) return false; | |||
1057 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; | |||
1058 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { | |||
1059 | int64_t Val = CE->getValue(); | |||
1060 | int64_t Align = 1LL << scale; | |||
1061 | int64_t Max = Align * ((1LL << width) - 1); | |||
1062 | return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); | |||
1063 | } | |||
1064 | return false; | |||
1065 | } | |||
1066 | ||||
1067 | // checks whether this operand is an signed offset which fits is a field | |||
1068 | // of specified width and scaled by a specific number of bits | |||
1069 | template<unsigned width, unsigned scale> | |||
1070 | bool isSignedOffset() const { | |||
1071 | if (!isImm()) return false; | |||
1072 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; | |||
1073 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { | |||
1074 | int64_t Val = CE->getValue(); | |||
1075 | int64_t Align = 1LL << scale; | |||
1076 | int64_t Max = Align * ((1LL << (width-1)) - 1); | |||
1077 | int64_t Min = -Align * (1LL << (width-1)); | |||
1078 | return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); | |||
1079 | } | |||
1080 | return false; | |||
1081 | } | |||
1082 | ||||
1083 | // checks whether this operand is an offset suitable for the LE / | |||
1084 | // LETP instructions in Arm v8.1M | |||
1085 | bool isLEOffset() const { | |||
1086 | if (!isImm()) return false; | |||
1087 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; | |||
1088 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { | |||
1089 | int64_t Val = CE->getValue(); | |||
1090 | return Val < 0 && Val >= -4094 && (Val & 1) == 0; | |||
1091 | } | |||
1092 | return false; | |||
1093 | } | |||
1094 | ||||
1095 | // checks whether this operand is a memory operand computed as an offset | |||
1096 | // applied to PC. the offset may have 8 bits of magnitude and is represented | |||
1097 | // with two bits of shift. textually it may be either [pc, #imm], #imm or | |||
1098 | // relocable expression... | |||
1099 | bool isThumbMemPC() const { | |||
1100 | int64_t Val = 0; | |||
1101 | if (isImm()) { | |||
1102 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; | |||
1103 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); | |||
1104 | if (!CE) return false; | |||
1105 | Val = CE->getValue(); | |||
1106 | } | |||
1107 | else if (isGPRMem()) { | |||
1108 | if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; | |||
1109 | if(Memory.BaseRegNum != ARM::PC) return false; | |||
1110 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
1111 | Val = CE->getValue(); | |||
1112 | else | |||
1113 | return false; | |||
1114 | } | |||
1115 | else return false; | |||
1116 | return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); | |||
1117 | } | |||
1118 | ||||
1119 | bool isFPImm() const { | |||
1120 | if (!isImm()) return false; | |||
1121 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1122 | if (!CE) return false; | |||
1123 | int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); | |||
1124 | return Val != -1; | |||
1125 | } | |||
1126 | ||||
1127 | template<int64_t N, int64_t M> | |||
1128 | bool isImmediate() const { | |||
1129 | if (!isImm()) return false; | |||
1130 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1131 | if (!CE) return false; | |||
1132 | int64_t Value = CE->getValue(); | |||
1133 | return Value >= N && Value <= M; | |||
1134 | } | |||
1135 | ||||
1136 | template<int64_t N, int64_t M> | |||
1137 | bool isImmediateS4() const { | |||
1138 | if (!isImm()) return false; | |||
1139 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1140 | if (!CE) return false; | |||
1141 | int64_t Value = CE->getValue(); | |||
1142 | return ((Value & 3) == 0) && Value >= N && Value <= M; | |||
1143 | } | |||
1144 | template<int64_t N, int64_t M> | |||
1145 | bool isImmediateS2() const { | |||
1146 | if (!isImm()) return false; | |||
1147 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1148 | if (!CE) return false; | |||
1149 | int64_t Value = CE->getValue(); | |||
1150 | return ((Value & 1) == 0) && Value >= N && Value <= M; | |||
1151 | } | |||
1152 | bool isFBits16() const { | |||
1153 | return isImmediate<0, 17>(); | |||
1154 | } | |||
1155 | bool isFBits32() const { | |||
1156 | return isImmediate<1, 33>(); | |||
1157 | } | |||
1158 | bool isImm8s4() const { | |||
1159 | return isImmediateS4<-1020, 1020>(); | |||
1160 | } | |||
1161 | bool isImm7s4() const { | |||
1162 | return isImmediateS4<-508, 508>(); | |||
1163 | } | |||
1164 | bool isImm7Shift0() const { | |||
1165 | return isImmediate<-127, 127>(); | |||
1166 | } | |||
1167 | bool isImm7Shift1() const { | |||
1168 | return isImmediateS2<-255, 255>(); | |||
1169 | } | |||
1170 | bool isImm7Shift2() const { | |||
1171 | return isImmediateS4<-511, 511>(); | |||
1172 | } | |||
1173 | bool isImm7() const { | |||
1174 | return isImmediate<-127, 127>(); | |||
1175 | } | |||
1176 | bool isImm0_1020s4() const { | |||
1177 | return isImmediateS4<0, 1020>(); | |||
1178 | } | |||
1179 | bool isImm0_508s4() const { | |||
1180 | return isImmediateS4<0, 508>(); | |||
1181 | } | |||
1182 | bool isImm0_508s4Neg() const { | |||
1183 | if (!isImm()) return false; | |||
1184 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1185 | if (!CE) return false; | |||
1186 | int64_t Value = -CE->getValue(); | |||
1187 | // explicitly exclude zero. we want that to use the normal 0_508 version. | |||
1188 | return ((Value & 3) == 0) && Value > 0 && Value <= 508; | |||
1189 | } | |||
1190 | ||||
1191 | bool isImm0_4095Neg() const { | |||
1192 | if (!isImm()) return false; | |||
1193 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1194 | if (!CE) return false; | |||
1195 | // isImm0_4095Neg is used with 32-bit immediates only. | |||
1196 | // 32-bit immediates are zero extended to 64-bit when parsed, | |||
1197 | // thus simple -CE->getValue() results in a big negative number, | |||
1198 | // not a small positive number as intended | |||
1199 | if ((CE->getValue() >> 32) > 0) return false; | |||
1200 | uint32_t Value = -static_cast<uint32_t>(CE->getValue()); | |||
1201 | return Value > 0 && Value < 4096; | |||
1202 | } | |||
1203 | ||||
1204 | bool isImm0_7() const { | |||
1205 | return isImmediate<0, 7>(); | |||
1206 | } | |||
1207 | ||||
1208 | bool isImm1_16() const { | |||
1209 | return isImmediate<1, 16>(); | |||
1210 | } | |||
1211 | ||||
1212 | bool isImm1_32() const { | |||
1213 | return isImmediate<1, 32>(); | |||
1214 | } | |||
1215 | ||||
1216 | bool isImm8_255() const { | |||
1217 | return isImmediate<8, 255>(); | |||
1218 | } | |||
1219 | ||||
1220 | bool isImm256_65535Expr() const { | |||
1221 | if (!isImm()) return false; | |||
1222 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1223 | // If it's not a constant expression, it'll generate a fixup and be | |||
1224 | // handled later. | |||
1225 | if (!CE) return true; | |||
1226 | int64_t Value = CE->getValue(); | |||
1227 | return Value >= 256 && Value < 65536; | |||
1228 | } | |||
1229 | ||||
1230 | bool isImm0_65535Expr() const { | |||
1231 | if (!isImm()) return false; | |||
1232 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1233 | // If it's not a constant expression, it'll generate a fixup and be | |||
1234 | // handled later. | |||
1235 | if (!CE) return true; | |||
1236 | int64_t Value = CE->getValue(); | |||
1237 | return Value >= 0 && Value < 65536; | |||
1238 | } | |||
1239 | ||||
1240 | bool isImm24bit() const { | |||
1241 | return isImmediate<0, 0xffffff + 1>(); | |||
1242 | } | |||
1243 | ||||
1244 | bool isImmThumbSR() const { | |||
1245 | return isImmediate<1, 33>(); | |||
1246 | } | |||
1247 | ||||
1248 | template<int shift> | |||
1249 | bool isExpImmValue(uint64_t Value) const { | |||
1250 | uint64_t mask = (1 << shift) - 1; | |||
1251 | if ((Value & mask) != 0 || (Value >> shift) > 0xff) | |||
1252 | return false; | |||
1253 | return true; | |||
1254 | } | |||
1255 | ||||
1256 | template<int shift> | |||
1257 | bool isExpImm() const { | |||
1258 | if (!isImm()) return false; | |||
1259 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1260 | if (!CE) return false; | |||
1261 | ||||
1262 | return isExpImmValue<shift>(CE->getValue()); | |||
1263 | } | |||
1264 | ||||
1265 | template<int shift, int size> | |||
1266 | bool isInvertedExpImm() const { | |||
1267 | if (!isImm()) return false; | |||
1268 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1269 | if (!CE) return false; | |||
1270 | ||||
1271 | uint64_t OriginalValue = CE->getValue(); | |||
1272 | uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1); | |||
1273 | return isExpImmValue<shift>(InvertedValue); | |||
1274 | } | |||
1275 | ||||
1276 | bool isPKHLSLImm() const { | |||
1277 | return isImmediate<0, 32>(); | |||
1278 | } | |||
1279 | ||||
1280 | bool isPKHASRImm() const { | |||
1281 | return isImmediate<0, 33>(); | |||
1282 | } | |||
1283 | ||||
1284 | bool isAdrLabel() const { | |||
1285 | // If we have an immediate that's not a constant, treat it as a label | |||
1286 | // reference needing a fixup. | |||
1287 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1288 | return true; | |||
1289 | ||||
1290 | // If it is a constant, it must fit into a modified immediate encoding. | |||
1291 | if (!isImm()) return false; | |||
1292 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1293 | if (!CE) return false; | |||
1294 | int64_t Value = CE->getValue(); | |||
1295 | return (ARM_AM::getSOImmVal(Value) != -1 || | |||
1296 | ARM_AM::getSOImmVal(-Value) != -1); | |||
1297 | } | |||
1298 | ||||
1299 | bool isT2SOImm() const { | |||
1300 | // If we have an immediate that's not a constant, treat it as an expression | |||
1301 | // needing a fixup. | |||
1302 | if (isImm() && !isa<MCConstantExpr>(getImm())) { | |||
1303 | // We want to avoid matching :upper16: and :lower16: as we want these | |||
1304 | // expressions to match in isImm0_65535Expr() | |||
1305 | const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm()); | |||
1306 | return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && | |||
1307 | ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)); | |||
1308 | } | |||
1309 | if (!isImm()) return false; | |||
1310 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1311 | if (!CE) return false; | |||
1312 | int64_t Value = CE->getValue(); | |||
1313 | return ARM_AM::getT2SOImmVal(Value) != -1; | |||
1314 | } | |||
1315 | ||||
1316 | bool isT2SOImmNot() const { | |||
1317 | if (!isImm()) return false; | |||
1318 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1319 | if (!CE) return false; | |||
1320 | int64_t Value = CE->getValue(); | |||
1321 | return ARM_AM::getT2SOImmVal(Value) == -1 && | |||
1322 | ARM_AM::getT2SOImmVal(~Value) != -1; | |||
1323 | } | |||
1324 | ||||
1325 | bool isT2SOImmNeg() const { | |||
1326 | if (!isImm()) return false; | |||
1327 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1328 | if (!CE) return false; | |||
1329 | int64_t Value = CE->getValue(); | |||
1330 | // Only use this when not representable as a plain so_imm. | |||
1331 | return ARM_AM::getT2SOImmVal(Value) == -1 && | |||
1332 | ARM_AM::getT2SOImmVal(-Value) != -1; | |||
1333 | } | |||
1334 | ||||
1335 | bool isSetEndImm() const { | |||
1336 | if (!isImm()) return false; | |||
1337 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1338 | if (!CE) return false; | |||
1339 | int64_t Value = CE->getValue(); | |||
1340 | return Value == 1 || Value == 0; | |||
1341 | } | |||
1342 | ||||
1343 | bool isReg() const override { return Kind == k_Register; } | |||
1344 | bool isRegList() const { return Kind == k_RegisterList; } | |||
1345 | bool isRegListWithAPSR() const { | |||
1346 | return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList; | |||
1347 | } | |||
1348 | bool isDPRRegList() const { return Kind == k_DPRRegisterList; } | |||
1349 | bool isSPRRegList() const { return Kind == k_SPRRegisterList; } | |||
1350 | bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; } | |||
1351 | bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; } | |||
1352 | bool isToken() const override { return Kind == k_Token; } | |||
1353 | bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } | |||
1354 | bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } | |||
1355 | bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; } | |||
1356 | bool isMem() const override { | |||
1357 | return isGPRMem() || isMVEMem(); | |||
1358 | } | |||
1359 | bool isMVEMem() const { | |||
1360 | if (Kind != k_Memory) | |||
1361 | return false; | |||
1362 | if (Memory.BaseRegNum && | |||
1363 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && | |||
1364 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) | |||
1365 | return false; | |||
1366 | if (Memory.OffsetRegNum && | |||
1367 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( | |||
1368 | Memory.OffsetRegNum)) | |||
1369 | return false; | |||
1370 | return true; | |||
1371 | } | |||
1372 | bool isGPRMem() const { | |||
1373 | if (Kind != k_Memory) | |||
1374 | return false; | |||
1375 | if (Memory.BaseRegNum && | |||
1376 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) | |||
1377 | return false; | |||
1378 | if (Memory.OffsetRegNum && | |||
1379 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) | |||
1380 | return false; | |||
1381 | return true; | |||
1382 | } | |||
1383 | bool isShifterImm() const { return Kind == k_ShifterImmediate; } | |||
1384 | bool isRegShiftedReg() const { | |||
1385 | return Kind == k_ShiftedRegister && | |||
1386 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( | |||
1387 | RegShiftedReg.SrcReg) && | |||
1388 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( | |||
1389 | RegShiftedReg.ShiftReg); | |||
1390 | } | |||
1391 | bool isRegShiftedImm() const { | |||
1392 | return Kind == k_ShiftedImmediate && | |||
1393 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( | |||
1394 | RegShiftedImm.SrcReg); | |||
1395 | } | |||
1396 | bool isRotImm() const { return Kind == k_RotateImmediate; } | |||
1397 | ||||
1398 | template<unsigned Min, unsigned Max> | |||
1399 | bool isPowerTwoInRange() const { | |||
1400 | if (!isImm()) return false; | |||
1401 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1402 | if (!CE) return false; | |||
1403 | int64_t Value = CE->getValue(); | |||
1404 | return Value > 0 && countPopulation((uint64_t)Value) == 1 && | |||
1405 | Value >= Min && Value <= Max; | |||
1406 | } | |||
1407 | bool isModImm() const { return Kind == k_ModifiedImmediate; } | |||
1408 | ||||
1409 | bool isModImmNot() const { | |||
1410 | if (!isImm()) return false; | |||
1411 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1412 | if (!CE) return false; | |||
1413 | int64_t Value = CE->getValue(); | |||
1414 | return ARM_AM::getSOImmVal(~Value) != -1; | |||
1415 | } | |||
1416 | ||||
1417 | bool isModImmNeg() const { | |||
1418 | if (!isImm()) return false; | |||
1419 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1420 | if (!CE) return false; | |||
1421 | int64_t Value = CE->getValue(); | |||
1422 | return ARM_AM::getSOImmVal(Value) == -1 && | |||
1423 | ARM_AM::getSOImmVal(-Value) != -1; | |||
1424 | } | |||
1425 | ||||
1426 | bool isThumbModImmNeg1_7() const { | |||
1427 | if (!isImm()) return false; | |||
1428 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1429 | if (!CE) return false; | |||
1430 | int32_t Value = -(int32_t)CE->getValue(); | |||
1431 | return 0 < Value && Value < 8; | |||
1432 | } | |||
1433 | ||||
1434 | bool isThumbModImmNeg8_255() const { | |||
1435 | if (!isImm()) return false; | |||
1436 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1437 | if (!CE) return false; | |||
1438 | int32_t Value = -(int32_t)CE->getValue(); | |||
1439 | return 7 < Value && Value < 256; | |||
1440 | } | |||
1441 | ||||
1442 | bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; } | |||
1443 | bool isBitfield() const { return Kind == k_BitfieldDescriptor; } | |||
1444 | bool isPostIdxRegShifted() const { | |||
1445 | return Kind == k_PostIndexRegister && | |||
1446 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); | |||
1447 | } | |||
1448 | bool isPostIdxReg() const { | |||
1449 | return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; | |||
1450 | } | |||
1451 | bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { | |||
1452 | if (!isGPRMem()) | |||
1453 | return false; | |||
1454 | // No offset of any kind. | |||
1455 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && | |||
1456 | (alignOK || Memory.Alignment == Alignment); | |||
1457 | } | |||
1458 | bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const { | |||
1459 | if (!isGPRMem()) | |||
1460 | return false; | |||
1461 | ||||
1462 | if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( | |||
1463 | Memory.BaseRegNum)) | |||
1464 | return false; | |||
1465 | ||||
1466 | // No offset of any kind. | |||
1467 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && | |||
1468 | (alignOK || Memory.Alignment == Alignment); | |||
1469 | } | |||
1470 | bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const { | |||
1471 | if (!isGPRMem()) | |||
1472 | return false; | |||
1473 | ||||
1474 | if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( | |||
1475 | Memory.BaseRegNum)) | |||
1476 | return false; | |||
1477 | ||||
1478 | // No offset of any kind. | |||
1479 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && | |||
1480 | (alignOK || Memory.Alignment == Alignment); | |||
1481 | } | |||
1482 | bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const { | |||
1483 | if (!isGPRMem()) | |||
1484 | return false; | |||
1485 | ||||
1486 | if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( | |||
1487 | Memory.BaseRegNum)) | |||
1488 | return false; | |||
1489 | ||||
1490 | // No offset of any kind. | |||
1491 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && | |||
1492 | (alignOK || Memory.Alignment == Alignment); | |||
1493 | } | |||
1494 | bool isMemPCRelImm12() const { | |||
1495 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1496 | return false; | |||
1497 | // Base register must be PC. | |||
1498 | if (Memory.BaseRegNum != ARM::PC) | |||
1499 | return false; | |||
1500 | // Immediate offset in range [-4095, 4095]. | |||
1501 | if (!Memory.OffsetImm) return true; | |||
1502 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1503 | int64_t Val = CE->getValue(); | |||
1504 | return (Val > -4096 && Val < 4096) || | |||
1505 | (Val == std::numeric_limits<int32_t>::min()); | |||
1506 | } | |||
1507 | return false; | |||
1508 | } | |||
1509 | ||||
1510 | bool isAlignedMemory() const { | |||
1511 | return isMemNoOffset(true); | |||
1512 | } | |||
1513 | ||||
1514 | bool isAlignedMemoryNone() const { | |||
1515 | return isMemNoOffset(false, 0); | |||
1516 | } | |||
1517 | ||||
1518 | bool isDupAlignedMemoryNone() const { | |||
1519 | return isMemNoOffset(false, 0); | |||
1520 | } | |||
1521 | ||||
1522 | bool isAlignedMemory16() const { | |||
1523 | if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. | |||
1524 | return true; | |||
1525 | return isMemNoOffset(false, 0); | |||
1526 | } | |||
1527 | ||||
1528 | bool isDupAlignedMemory16() const { | |||
1529 | if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. | |||
1530 | return true; | |||
1531 | return isMemNoOffset(false, 0); | |||
1532 | } | |||
1533 | ||||
1534 | bool isAlignedMemory32() const { | |||
1535 | if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. | |||
1536 | return true; | |||
1537 | return isMemNoOffset(false, 0); | |||
1538 | } | |||
1539 | ||||
1540 | bool isDupAlignedMemory32() const { | |||
1541 | if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. | |||
1542 | return true; | |||
1543 | return isMemNoOffset(false, 0); | |||
1544 | } | |||
1545 | ||||
1546 | bool isAlignedMemory64() const { | |||
1547 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. | |||
1548 | return true; | |||
1549 | return isMemNoOffset(false, 0); | |||
1550 | } | |||
1551 | ||||
1552 | bool isDupAlignedMemory64() const { | |||
1553 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. | |||
1554 | return true; | |||
1555 | return isMemNoOffset(false, 0); | |||
1556 | } | |||
1557 | ||||
1558 | bool isAlignedMemory64or128() const { | |||
1559 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. | |||
1560 | return true; | |||
1561 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. | |||
1562 | return true; | |||
1563 | return isMemNoOffset(false, 0); | |||
1564 | } | |||
1565 | ||||
1566 | bool isDupAlignedMemory64or128() const { | |||
1567 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. | |||
1568 | return true; | |||
1569 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. | |||
1570 | return true; | |||
1571 | return isMemNoOffset(false, 0); | |||
1572 | } | |||
1573 | ||||
1574 | bool isAlignedMemory64or128or256() const { | |||
1575 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. | |||
1576 | return true; | |||
1577 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. | |||
1578 | return true; | |||
1579 | if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. | |||
1580 | return true; | |||
1581 | return isMemNoOffset(false, 0); | |||
1582 | } | |||
1583 | ||||
1584 | bool isAddrMode2() const { | |||
1585 | if (!isGPRMem() || Memory.Alignment != 0) return false; | |||
1586 | // Check for register offset. | |||
1587 | if (Memory.OffsetRegNum) return true; | |||
1588 | // Immediate offset in range [-4095, 4095]. | |||
1589 | if (!Memory.OffsetImm) return true; | |||
1590 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1591 | int64_t Val = CE->getValue(); | |||
1592 | return Val > -4096 && Val < 4096; | |||
1593 | } | |||
1594 | return false; | |||
1595 | } | |||
1596 | ||||
1597 | bool isAM2OffsetImm() const { | |||
1598 | if (!isImm()) return false; | |||
1599 | // Immediate offset in range [-4095, 4095]. | |||
1600 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1601 | if (!CE) return false; | |||
1602 | int64_t Val = CE->getValue(); | |||
1603 | return (Val == std::numeric_limits<int32_t>::min()) || | |||
1604 | (Val > -4096 && Val < 4096); | |||
1605 | } | |||
1606 | ||||
1607 | bool isAddrMode3() const { | |||
1608 | // If we have an immediate that's not a constant, treat it as a label | |||
1609 | // reference needing a fixup. If it is a constant, it's something else | |||
1610 | // and we reject it. | |||
1611 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1612 | return true; | |||
1613 | if (!isGPRMem() || Memory.Alignment != 0) return false; | |||
1614 | // No shifts are legal for AM3. | |||
1615 | if (Memory.ShiftType != ARM_AM::no_shift) return false; | |||
1616 | // Check for register offset. | |||
1617 | if (Memory.OffsetRegNum) return true; | |||
1618 | // Immediate offset in range [-255, 255]. | |||
1619 | if (!Memory.OffsetImm) return true; | |||
1620 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1621 | int64_t Val = CE->getValue(); | |||
1622 | // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and | |||
1623 | // we have to check for this too. | |||
1624 | return (Val > -256 && Val < 256) || | |||
1625 | Val == std::numeric_limits<int32_t>::min(); | |||
1626 | } | |||
1627 | return false; | |||
1628 | } | |||
1629 | ||||
1630 | bool isAM3Offset() const { | |||
1631 | if (isPostIdxReg()) | |||
1632 | return true; | |||
1633 | if (!isImm()) | |||
1634 | return false; | |||
1635 | // Immediate offset in range [-255, 255]. | |||
1636 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1637 | if (!CE) return false; | |||
1638 | int64_t Val = CE->getValue(); | |||
1639 | // Special case, #-0 is std::numeric_limits<int32_t>::min(). | |||
1640 | return (Val > -256 && Val < 256) || | |||
1641 | Val == std::numeric_limits<int32_t>::min(); | |||
1642 | } | |||
1643 | ||||
1644 | bool isAddrMode5() const { | |||
1645 | // If we have an immediate that's not a constant, treat it as a label | |||
1646 | // reference needing a fixup. If it is a constant, it's something else | |||
1647 | // and we reject it. | |||
1648 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1649 | return true; | |||
1650 | if (!isGPRMem() || Memory.Alignment != 0) return false; | |||
1651 | // Check for register offset. | |||
1652 | if (Memory.OffsetRegNum) return false; | |||
1653 | // Immediate offset in range [-1020, 1020] and a multiple of 4. | |||
1654 | if (!Memory.OffsetImm) return true; | |||
1655 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1656 | int64_t Val = CE->getValue(); | |||
1657 | return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || | |||
1658 | Val == std::numeric_limits<int32_t>::min(); | |||
1659 | } | |||
1660 | return false; | |||
1661 | } | |||
1662 | ||||
1663 | bool isAddrMode5FP16() const { | |||
1664 | // If we have an immediate that's not a constant, treat it as a label | |||
1665 | // reference needing a fixup. If it is a constant, it's something else | |||
1666 | // and we reject it. | |||
1667 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1668 | return true; | |||
1669 | if (!isGPRMem() || Memory.Alignment != 0) return false; | |||
1670 | // Check for register offset. | |||
1671 | if (Memory.OffsetRegNum) return false; | |||
1672 | // Immediate offset in range [-510, 510] and a multiple of 2. | |||
1673 | if (!Memory.OffsetImm) return true; | |||
1674 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1675 | int64_t Val = CE->getValue(); | |||
1676 | return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || | |||
1677 | Val == std::numeric_limits<int32_t>::min(); | |||
1678 | } | |||
1679 | return false; | |||
1680 | } | |||
1681 | ||||
1682 | bool isMemTBB() const { | |||
1683 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || | |||
1684 | Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) | |||
1685 | return false; | |||
1686 | return true; | |||
1687 | } | |||
1688 | ||||
1689 | bool isMemTBH() const { | |||
1690 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || | |||
1691 | Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || | |||
1692 | Memory.Alignment != 0 ) | |||
1693 | return false; | |||
1694 | return true; | |||
1695 | } | |||
1696 | ||||
1697 | bool isMemRegOffset() const { | |||
1698 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) | |||
1699 | return false; | |||
1700 | return true; | |||
1701 | } | |||
1702 | ||||
1703 | bool isT2MemRegOffset() const { | |||
1704 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || | |||
1705 | Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) | |||
1706 | return false; | |||
1707 | // Only lsl #{0, 1, 2, 3} allowed. | |||
1708 | if (Memory.ShiftType == ARM_AM::no_shift) | |||
1709 | return true; | |||
1710 | if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) | |||
1711 | return false; | |||
1712 | return true; | |||
1713 | } | |||
1714 | ||||
1715 | bool isMemThumbRR() const { | |||
1716 | // Thumb reg+reg addressing is simple. Just two registers, a base and | |||
1717 | // an offset. No shifts, negations or any other complicating factors. | |||
1718 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || | |||
1719 | Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) | |||
1720 | return false; | |||
1721 | return isARMLowRegister(Memory.BaseRegNum) && | |||
1722 | (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); | |||
1723 | } | |||
1724 | ||||
1725 | bool isMemThumbRIs4() const { | |||
1726 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || | |||
1727 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) | |||
1728 | return false; | |||
1729 | // Immediate offset, multiple of 4 in range [0, 124]. | |||
1730 | if (!Memory.OffsetImm) return true; | |||
1731 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1732 | int64_t Val = CE->getValue(); | |||
1733 | return Val >= 0 && Val <= 124 && (Val % 4) == 0; | |||
1734 | } | |||
1735 | return false; | |||
1736 | } | |||
1737 | ||||
1738 | bool isMemThumbRIs2() const { | |||
1739 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || | |||
1740 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) | |||
1741 | return false; | |||
1742 | // Immediate offset, multiple of 4 in range [0, 62]. | |||
1743 | if (!Memory.OffsetImm) return true; | |||
1744 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1745 | int64_t Val = CE->getValue(); | |||
1746 | return Val >= 0 && Val <= 62 && (Val % 2) == 0; | |||
1747 | } | |||
1748 | return false; | |||
1749 | } | |||
1750 | ||||
1751 | bool isMemThumbRIs1() const { | |||
1752 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || | |||
1753 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) | |||
1754 | return false; | |||
1755 | // Immediate offset in range [0, 31]. | |||
1756 | if (!Memory.OffsetImm) return true; | |||
1757 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1758 | int64_t Val = CE->getValue(); | |||
1759 | return Val >= 0 && Val <= 31; | |||
1760 | } | |||
1761 | return false; | |||
1762 | } | |||
1763 | ||||
1764 | bool isMemThumbSPI() const { | |||
1765 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || | |||
1766 | Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) | |||
1767 | return false; | |||
1768 | // Immediate offset, multiple of 4 in range [0, 1020]. | |||
1769 | if (!Memory.OffsetImm) return true; | |||
1770 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1771 | int64_t Val = CE->getValue(); | |||
1772 | return Val >= 0 && Val <= 1020 && (Val % 4) == 0; | |||
1773 | } | |||
1774 | return false; | |||
1775 | } | |||
1776 | ||||
1777 | bool isMemImm8s4Offset() const { | |||
1778 | // If we have an immediate that's not a constant, treat it as a label | |||
1779 | // reference needing a fixup. If it is a constant, it's something else | |||
1780 | // and we reject it. | |||
1781 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1782 | return true; | |||
1783 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1784 | return false; | |||
1785 | // Immediate offset a multiple of 4 in range [-1020, 1020]. | |||
1786 | if (!Memory.OffsetImm) return true; | |||
1787 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1788 | int64_t Val = CE->getValue(); | |||
1789 | // Special case, #-0 is std::numeric_limits<int32_t>::min(). | |||
1790 | return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || | |||
1791 | Val == std::numeric_limits<int32_t>::min(); | |||
1792 | } | |||
1793 | return false; | |||
1794 | } | |||
1795 | ||||
1796 | bool isMemImm7s4Offset() const { | |||
1797 | // If we have an immediate that's not a constant, treat it as a label | |||
1798 | // reference needing a fixup. If it is a constant, it's something else | |||
1799 | // and we reject it. | |||
1800 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1801 | return true; | |||
1802 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || | |||
1803 | !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( | |||
1804 | Memory.BaseRegNum)) | |||
1805 | return false; | |||
1806 | // Immediate offset a multiple of 4 in range [-508, 508]. | |||
1807 | if (!Memory.OffsetImm) return true; | |||
1808 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1809 | int64_t Val = CE->getValue(); | |||
1810 | // Special case, #-0 is INT32_MIN. | |||
1811 | return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN(-2147483647-1); | |||
1812 | } | |||
1813 | return false; | |||
1814 | } | |||
1815 | ||||
1816 | bool isMemImm0_1020s4Offset() const { | |||
1817 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1818 | return false; | |||
1819 | // Immediate offset a multiple of 4 in range [0, 1020]. | |||
1820 | if (!Memory.OffsetImm) return true; | |||
1821 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1822 | int64_t Val = CE->getValue(); | |||
1823 | return Val >= 0 && Val <= 1020 && (Val & 3) == 0; | |||
1824 | } | |||
1825 | return false; | |||
1826 | } | |||
1827 | ||||
1828 | bool isMemImm8Offset() const { | |||
1829 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1830 | return false; | |||
1831 | // Base reg of PC isn't allowed for these encodings. | |||
1832 | if (Memory.BaseRegNum == ARM::PC) return false; | |||
1833 | // Immediate offset in range [-255, 255]. | |||
1834 | if (!Memory.OffsetImm) return true; | |||
1835 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1836 | int64_t Val = CE->getValue(); | |||
1837 | return (Val == std::numeric_limits<int32_t>::min()) || | |||
1838 | (Val > -256 && Val < 256); | |||
1839 | } | |||
1840 | return false; | |||
1841 | } | |||
1842 | ||||
1843 | template<unsigned Bits, unsigned RegClassID> | |||
1844 | bool isMemImm7ShiftedOffset() const { | |||
1845 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || | |||
1846 | !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) | |||
1847 | return false; | |||
1848 | ||||
1849 | // Expect an immediate offset equal to an element of the range | |||
1850 | // [-127, 127], shifted left by Bits. | |||
1851 | ||||
1852 | if (!Memory.OffsetImm) return true; | |||
1853 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1854 | int64_t Val = CE->getValue(); | |||
1855 | ||||
1856 | // INT32_MIN is a special-case value (indicating the encoding with | |||
1857 | // zero offset and the subtract bit set) | |||
1858 | if (Val == INT32_MIN(-2147483647-1)) | |||
1859 | return true; | |||
1860 | ||||
1861 | unsigned Divisor = 1U << Bits; | |||
1862 | ||||
1863 | // Check that the low bits are zero | |||
1864 | if (Val % Divisor != 0) | |||
1865 | return false; | |||
1866 | ||||
1867 | // Check that the remaining offset is within range. | |||
1868 | Val /= Divisor; | |||
1869 | return (Val >= -127 && Val <= 127); | |||
1870 | } | |||
1871 | return false; | |||
1872 | } | |||
1873 | ||||
1874 | template <int shift> bool isMemRegRQOffset() const { | |||
1875 | if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0) | |||
1876 | return false; | |||
1877 | ||||
1878 | if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( | |||
1879 | Memory.BaseRegNum)) | |||
1880 | return false; | |||
1881 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( | |||
1882 | Memory.OffsetRegNum)) | |||
1883 | return false; | |||
1884 | ||||
1885 | if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) | |||
1886 | return false; | |||
1887 | ||||
1888 | if (shift > 0 && | |||
1889 | (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) | |||
1890 | return false; | |||
1891 | ||||
1892 | return true; | |||
1893 | } | |||
1894 | ||||
1895 | template <int shift> bool isMemRegQOffset() const { | |||
1896 | if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1897 | return false; | |||
1898 | ||||
1899 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( | |||
1900 | Memory.BaseRegNum)) | |||
1901 | return false; | |||
1902 | ||||
1903 | if (!Memory.OffsetImm) | |||
1904 | return true; | |||
1905 | static_assert(shift < 56, | |||
1906 | "Such that we dont shift by a value higher than 62"); | |||
1907 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1908 | int64_t Val = CE->getValue(); | |||
1909 | ||||
1910 | // The value must be a multiple of (1 << shift) | |||
1911 | if ((Val & ((1U << shift) - 1)) != 0) | |||
1912 | return false; | |||
1913 | ||||
1914 | // And be in the right range, depending on the amount that it is shifted | |||
1915 | // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set | |||
1916 | // separately. | |||
1917 | int64_t Range = (1U << (7 + shift)) - 1; | |||
1918 | return (Val == INT32_MIN(-2147483647-1)) || (Val > -Range && Val < Range); | |||
1919 | } | |||
1920 | return false; | |||
1921 | } | |||
1922 | ||||
1923 | bool isMemPosImm8Offset() const { | |||
1924 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1925 | return false; | |||
1926 | // Immediate offset in range [0, 255]. | |||
1927 | if (!Memory.OffsetImm) return true; | |||
1928 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1929 | int64_t Val = CE->getValue(); | |||
1930 | return Val >= 0 && Val < 256; | |||
1931 | } | |||
1932 | return false; | |||
1933 | } | |||
1934 | ||||
1935 | bool isMemNegImm8Offset() const { | |||
1936 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1937 | return false; | |||
1938 | // Base reg of PC isn't allowed for these encodings. | |||
1939 | if (Memory.BaseRegNum == ARM::PC) return false; | |||
1940 | // Immediate offset in range [-255, -1]. | |||
1941 | if (!Memory.OffsetImm) return false; | |||
1942 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1943 | int64_t Val = CE->getValue(); | |||
1944 | return (Val == std::numeric_limits<int32_t>::min()) || | |||
1945 | (Val > -256 && Val < 0); | |||
1946 | } | |||
1947 | return false; | |||
1948 | } | |||
1949 | ||||
1950 | bool isMemUImm12Offset() const { | |||
1951 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1952 | return false; | |||
1953 | // Immediate offset in range [0, 4095]. | |||
1954 | if (!Memory.OffsetImm) return true; | |||
1955 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1956 | int64_t Val = CE->getValue(); | |||
1957 | return (Val >= 0 && Val < 4096); | |||
1958 | } | |||
1959 | return false; | |||
1960 | } | |||
1961 | ||||
1962 | bool isMemImm12Offset() const { | |||
1963 | // If we have an immediate that's not a constant, treat it as a label | |||
1964 | // reference needing a fixup. If it is a constant, it's something else | |||
1965 | // and we reject it. | |||
1966 | ||||
1967 | if (isImm() && !isa<MCConstantExpr>(getImm())) | |||
1968 | return true; | |||
1969 | ||||
1970 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) | |||
1971 | return false; | |||
1972 | // Immediate offset in range [-4095, 4095]. | |||
1973 | if (!Memory.OffsetImm) return true; | |||
1974 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
1975 | int64_t Val = CE->getValue(); | |||
1976 | return (Val > -4096 && Val < 4096) || | |||
1977 | (Val == std::numeric_limits<int32_t>::min()); | |||
1978 | } | |||
1979 | // If we have an immediate that's not a constant, treat it as a | |||
1980 | // symbolic expression needing a fixup. | |||
1981 | return true; | |||
1982 | } | |||
1983 | ||||
1984 | bool isConstPoolAsmImm() const { | |||
1985 | // Delay processing of Constant Pool Immediate, this will turn into | |||
1986 | // a constant. Match no other operand | |||
1987 | return (isConstantPoolImm()); | |||
1988 | } | |||
1989 | ||||
1990 | bool isPostIdxImm8() const { | |||
1991 | if (!isImm()) return false; | |||
1992 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
1993 | if (!CE) return false; | |||
1994 | int64_t Val = CE->getValue(); | |||
1995 | return (Val > -256 && Val < 256) || | |||
1996 | (Val == std::numeric_limits<int32_t>::min()); | |||
1997 | } | |||
1998 | ||||
1999 | bool isPostIdxImm8s4() const { | |||
2000 | if (!isImm()) return false; | |||
2001 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2002 | if (!CE) return false; | |||
2003 | int64_t Val = CE->getValue(); | |||
2004 | return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || | |||
2005 | (Val == std::numeric_limits<int32_t>::min()); | |||
2006 | } | |||
2007 | ||||
2008 | bool isMSRMask() const { return Kind == k_MSRMask; } | |||
2009 | bool isBankedReg() const { return Kind == k_BankedReg; } | |||
2010 | bool isProcIFlags() const { return Kind == k_ProcIFlags; } | |||
2011 | ||||
2012 | // NEON operands. | |||
2013 | bool isSingleSpacedVectorList() const { | |||
2014 | return Kind == k_VectorList && !VectorList.isDoubleSpaced; | |||
2015 | } | |||
2016 | ||||
2017 | bool isDoubleSpacedVectorList() const { | |||
2018 | return Kind == k_VectorList && VectorList.isDoubleSpaced; | |||
2019 | } | |||
2020 | ||||
2021 | bool isVecListOneD() const { | |||
2022 | if (!isSingleSpacedVectorList()) return false; | |||
2023 | return VectorList.Count == 1; | |||
2024 | } | |||
2025 | ||||
2026 | bool isVecListTwoMQ() const { | |||
2027 | return isSingleSpacedVectorList() && VectorList.Count == 2 && | |||
2028 | ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( | |||
2029 | VectorList.RegNum); | |||
2030 | } | |||
2031 | ||||
2032 | bool isVecListDPair() const { | |||
2033 | if (!isSingleSpacedVectorList()) return false; | |||
2034 | return (ARMMCRegisterClasses[ARM::DPairRegClassID] | |||
2035 | .contains(VectorList.RegNum)); | |||
2036 | } | |||
2037 | ||||
2038 | bool isVecListThreeD() const { | |||
2039 | if (!isSingleSpacedVectorList()) return false; | |||
2040 | return VectorList.Count == 3; | |||
2041 | } | |||
2042 | ||||
2043 | bool isVecListFourD() const { | |||
2044 | if (!isSingleSpacedVectorList()) return false; | |||
2045 | return VectorList.Count == 4; | |||
2046 | } | |||
2047 | ||||
2048 | bool isVecListDPairSpaced() const { | |||
2049 | if (Kind != k_VectorList) return false; | |||
2050 | if (isSingleSpacedVectorList()) return false; | |||
2051 | return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] | |||
2052 | .contains(VectorList.RegNum)); | |||
2053 | } | |||
2054 | ||||
2055 | bool isVecListThreeQ() const { | |||
2056 | if (!isDoubleSpacedVectorList()) return false; | |||
2057 | return VectorList.Count == 3; | |||
2058 | } | |||
2059 | ||||
2060 | bool isVecListFourQ() const { | |||
2061 | if (!isDoubleSpacedVectorList()) return false; | |||
2062 | return VectorList.Count == 4; | |||
2063 | } | |||
2064 | ||||
2065 | bool isVecListFourMQ() const { | |||
2066 | return isSingleSpacedVectorList() && VectorList.Count == 4 && | |||
2067 | ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( | |||
2068 | VectorList.RegNum); | |||
2069 | } | |||
2070 | ||||
2071 | bool isSingleSpacedVectorAllLanes() const { | |||
2072 | return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; | |||
2073 | } | |||
2074 | ||||
2075 | bool isDoubleSpacedVectorAllLanes() const { | |||
2076 | return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; | |||
2077 | } | |||
2078 | ||||
2079 | bool isVecListOneDAllLanes() const { | |||
2080 | if (!isSingleSpacedVectorAllLanes()) return false; | |||
2081 | return VectorList.Count == 1; | |||
2082 | } | |||
2083 | ||||
2084 | bool isVecListDPairAllLanes() const { | |||
2085 | if (!isSingleSpacedVectorAllLanes()) return false; | |||
2086 | return (ARMMCRegisterClasses[ARM::DPairRegClassID] | |||
2087 | .contains(VectorList.RegNum)); | |||
2088 | } | |||
2089 | ||||
2090 | bool isVecListDPairSpacedAllLanes() const { | |||
2091 | if (!isDoubleSpacedVectorAllLanes()) return false; | |||
2092 | return VectorList.Count == 2; | |||
2093 | } | |||
2094 | ||||
2095 | bool isVecListThreeDAllLanes() const { | |||
2096 | if (!isSingleSpacedVectorAllLanes()) return false; | |||
2097 | return VectorList.Count == 3; | |||
2098 | } | |||
2099 | ||||
2100 | bool isVecListThreeQAllLanes() const { | |||
2101 | if (!isDoubleSpacedVectorAllLanes()) return false; | |||
2102 | return VectorList.Count == 3; | |||
2103 | } | |||
2104 | ||||
2105 | bool isVecListFourDAllLanes() const { | |||
2106 | if (!isSingleSpacedVectorAllLanes()) return false; | |||
2107 | return VectorList.Count == 4; | |||
2108 | } | |||
2109 | ||||
2110 | bool isVecListFourQAllLanes() const { | |||
2111 | if (!isDoubleSpacedVectorAllLanes()) return false; | |||
2112 | return VectorList.Count == 4; | |||
2113 | } | |||
2114 | ||||
2115 | bool isSingleSpacedVectorIndexed() const { | |||
2116 | return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; | |||
2117 | } | |||
2118 | ||||
2119 | bool isDoubleSpacedVectorIndexed() const { | |||
2120 | return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; | |||
2121 | } | |||
2122 | ||||
2123 | bool isVecListOneDByteIndexed() const { | |||
2124 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2125 | return VectorList.Count == 1 && VectorList.LaneIndex <= 7; | |||
2126 | } | |||
2127 | ||||
2128 | bool isVecListOneDHWordIndexed() const { | |||
2129 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2130 | return VectorList.Count == 1 && VectorList.LaneIndex <= 3; | |||
2131 | } | |||
2132 | ||||
2133 | bool isVecListOneDWordIndexed() const { | |||
2134 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2135 | return VectorList.Count == 1 && VectorList.LaneIndex <= 1; | |||
2136 | } | |||
2137 | ||||
2138 | bool isVecListTwoDByteIndexed() const { | |||
2139 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2140 | return VectorList.Count == 2 && VectorList.LaneIndex <= 7; | |||
2141 | } | |||
2142 | ||||
2143 | bool isVecListTwoDHWordIndexed() const { | |||
2144 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2145 | return VectorList.Count == 2 && VectorList.LaneIndex <= 3; | |||
2146 | } | |||
2147 | ||||
2148 | bool isVecListTwoQWordIndexed() const { | |||
2149 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2150 | return VectorList.Count == 2 && VectorList.LaneIndex <= 1; | |||
2151 | } | |||
2152 | ||||
2153 | bool isVecListTwoQHWordIndexed() const { | |||
2154 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2155 | return VectorList.Count == 2 && VectorList.LaneIndex <= 3; | |||
2156 | } | |||
2157 | ||||
2158 | bool isVecListTwoDWordIndexed() const { | |||
2159 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2160 | return VectorList.Count == 2 && VectorList.LaneIndex <= 1; | |||
2161 | } | |||
2162 | ||||
2163 | bool isVecListThreeDByteIndexed() const { | |||
2164 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2165 | return VectorList.Count == 3 && VectorList.LaneIndex <= 7; | |||
2166 | } | |||
2167 | ||||
2168 | bool isVecListThreeDHWordIndexed() const { | |||
2169 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2170 | return VectorList.Count == 3 && VectorList.LaneIndex <= 3; | |||
2171 | } | |||
2172 | ||||
2173 | bool isVecListThreeQWordIndexed() const { | |||
2174 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2175 | return VectorList.Count == 3 && VectorList.LaneIndex <= 1; | |||
2176 | } | |||
2177 | ||||
2178 | bool isVecListThreeQHWordIndexed() const { | |||
2179 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2180 | return VectorList.Count == 3 && VectorList.LaneIndex <= 3; | |||
2181 | } | |||
2182 | ||||
2183 | bool isVecListThreeDWordIndexed() const { | |||
2184 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2185 | return VectorList.Count == 3 && VectorList.LaneIndex <= 1; | |||
2186 | } | |||
2187 | ||||
2188 | bool isVecListFourDByteIndexed() const { | |||
2189 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2190 | return VectorList.Count == 4 && VectorList.LaneIndex <= 7; | |||
2191 | } | |||
2192 | ||||
2193 | bool isVecListFourDHWordIndexed() const { | |||
2194 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2195 | return VectorList.Count == 4 && VectorList.LaneIndex <= 3; | |||
2196 | } | |||
2197 | ||||
2198 | bool isVecListFourQWordIndexed() const { | |||
2199 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2200 | return VectorList.Count == 4 && VectorList.LaneIndex <= 1; | |||
2201 | } | |||
2202 | ||||
2203 | bool isVecListFourQHWordIndexed() const { | |||
2204 | if (!isDoubleSpacedVectorIndexed()) return false; | |||
2205 | return VectorList.Count == 4 && VectorList.LaneIndex <= 3; | |||
2206 | } | |||
2207 | ||||
2208 | bool isVecListFourDWordIndexed() const { | |||
2209 | if (!isSingleSpacedVectorIndexed()) return false; | |||
2210 | return VectorList.Count == 4 && VectorList.LaneIndex <= 1; | |||
2211 | } | |||
2212 | ||||
2213 | bool isVectorIndex() const { return Kind == k_VectorIndex; } | |||
2214 | ||||
2215 | template <unsigned NumLanes> | |||
2216 | bool isVectorIndexInRange() const { | |||
2217 | if (Kind != k_VectorIndex) return false; | |||
2218 | return VectorIndex.Val < NumLanes; | |||
2219 | } | |||
2220 | ||||
2221 | bool isVectorIndex8() const { return isVectorIndexInRange<8>(); } | |||
2222 | bool isVectorIndex16() const { return isVectorIndexInRange<4>(); } | |||
2223 | bool isVectorIndex32() const { return isVectorIndexInRange<2>(); } | |||
2224 | bool isVectorIndex64() const { return isVectorIndexInRange<1>(); } | |||
2225 | ||||
2226 | template<int PermittedValue, int OtherPermittedValue> | |||
2227 | bool isMVEPairVectorIndex() const { | |||
2228 | if (Kind != k_VectorIndex) return false; | |||
2229 | return VectorIndex.Val == PermittedValue || | |||
2230 | VectorIndex.Val == OtherPermittedValue; | |||
2231 | } | |||
2232 | ||||
2233 | bool isNEONi8splat() const { | |||
2234 | if (!isImm()) return false; | |||
2235 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2236 | // Must be a constant. | |||
2237 | if (!CE) return false; | |||
2238 | int64_t Value = CE->getValue(); | |||
2239 | // i8 value splatted across 8 bytes. The immediate is just the 8 byte | |||
2240 | // value. | |||
2241 | return Value >= 0 && Value < 256; | |||
2242 | } | |||
2243 | ||||
2244 | bool isNEONi16splat() const { | |||
2245 | if (isNEONByteReplicate(2)) | |||
2246 | return false; // Leave that for bytes replication and forbid by default. | |||
2247 | if (!isImm()) | |||
2248 | return false; | |||
2249 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2250 | // Must be a constant. | |||
2251 | if (!CE) return false; | |||
2252 | unsigned Value = CE->getValue(); | |||
2253 | return ARM_AM::isNEONi16splat(Value); | |||
2254 | } | |||
2255 | ||||
2256 | bool isNEONi16splatNot() const { | |||
2257 | if (!isImm()) | |||
2258 | return false; | |||
2259 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2260 | // Must be a constant. | |||
2261 | if (!CE) return false; | |||
2262 | unsigned Value = CE->getValue(); | |||
2263 | return ARM_AM::isNEONi16splat(~Value & 0xffff); | |||
2264 | } | |||
2265 | ||||
2266 | bool isNEONi32splat() const { | |||
2267 | if (isNEONByteReplicate(4)) | |||
2268 | return false; // Leave that for bytes replication and forbid by default. | |||
2269 | if (!isImm()) | |||
2270 | return false; | |||
2271 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2272 | // Must be a constant. | |||
2273 | if (!CE) return false; | |||
2274 | unsigned Value = CE->getValue(); | |||
2275 | return ARM_AM::isNEONi32splat(Value); | |||
2276 | } | |||
2277 | ||||
2278 | bool isNEONi32splatNot() const { | |||
2279 | if (!isImm()) | |||
2280 | return false; | |||
2281 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2282 | // Must be a constant. | |||
2283 | if (!CE) return false; | |||
2284 | unsigned Value = CE->getValue(); | |||
2285 | return ARM_AM::isNEONi32splat(~Value); | |||
2286 | } | |||
2287 | ||||
2288 | static bool isValidNEONi32vmovImm(int64_t Value) { | |||
2289 | // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, | |||
2290 | // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. | |||
2291 | return ((Value & 0xffffffffffffff00) == 0) || | |||
2292 | ((Value & 0xffffffffffff00ff) == 0) || | |||
2293 | ((Value & 0xffffffffff00ffff) == 0) || | |||
2294 | ((Value & 0xffffffff00ffffff) == 0) || | |||
2295 | ((Value & 0xffffffffffff00ff) == 0xff) || | |||
2296 | ((Value & 0xffffffffff00ffff) == 0xffff); | |||
2297 | } | |||
2298 | ||||
2299 | bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const { | |||
2300 | assert((Width == 8 || Width == 16 || Width == 32) &&(static_cast<void> (0)) | |||
2301 | "Invalid element width")(static_cast<void> (0)); | |||
2302 | assert(NumElems * Width <= 64 && "Invalid result width")(static_cast<void> (0)); | |||
2303 | ||||
2304 | if (!isImm()) | |||
2305 | return false; | |||
2306 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2307 | // Must be a constant. | |||
2308 | if (!CE) | |||
2309 | return false; | |||
2310 | int64_t Value = CE->getValue(); | |||
2311 | if (!Value) | |||
2312 | return false; // Don't bother with zero. | |||
2313 | if (Inv) | |||
2314 | Value = ~Value; | |||
2315 | ||||
2316 | uint64_t Mask = (1ull << Width) - 1; | |||
2317 | uint64_t Elem = Value & Mask; | |||
2318 | if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0) | |||
2319 | return false; | |||
2320 | if (Width == 32 && !isValidNEONi32vmovImm(Elem)) | |||
2321 | return false; | |||
2322 | ||||
2323 | for (unsigned i = 1; i < NumElems; ++i) { | |||
2324 | Value >>= Width; | |||
2325 | if ((Value & Mask) != Elem) | |||
2326 | return false; | |||
2327 | } | |||
2328 | return true; | |||
2329 | } | |||
2330 | ||||
2331 | bool isNEONByteReplicate(unsigned NumBytes) const { | |||
2332 | return isNEONReplicate(8, NumBytes, false); | |||
2333 | } | |||
2334 | ||||
2335 | static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) { | |||
2336 | assert((FromW == 8 || FromW == 16 || FromW == 32) &&(static_cast<void> (0)) | |||
2337 | "Invalid source width")(static_cast<void> (0)); | |||
2338 | assert((ToW == 16 || ToW == 32 || ToW == 64) &&(static_cast<void> (0)) | |||
2339 | "Invalid destination width")(static_cast<void> (0)); | |||
2340 | assert(FromW < ToW && "ToW is not less than FromW")(static_cast<void> (0)); | |||
2341 | } | |||
2342 | ||||
2343 | template<unsigned FromW, unsigned ToW> | |||
2344 | bool isNEONmovReplicate() const { | |||
2345 | checkNeonReplicateArgs(FromW, ToW); | |||
2346 | if (ToW == 64 && isNEONi64splat()) | |||
2347 | return false; | |||
2348 | return isNEONReplicate(FromW, ToW / FromW, false); | |||
2349 | } | |||
2350 | ||||
2351 | template<unsigned FromW, unsigned ToW> | |||
2352 | bool isNEONinvReplicate() const { | |||
2353 | checkNeonReplicateArgs(FromW, ToW); | |||
2354 | return isNEONReplicate(FromW, ToW / FromW, true); | |||
2355 | } | |||
2356 | ||||
2357 | bool isNEONi32vmov() const { | |||
2358 | if (isNEONByteReplicate(4)) | |||
2359 | return false; // Let it to be classified as byte-replicate case. | |||
2360 | if (!isImm()) | |||
2361 | return false; | |||
2362 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2363 | // Must be a constant. | |||
2364 | if (!CE) | |||
2365 | return false; | |||
2366 | return isValidNEONi32vmovImm(CE->getValue()); | |||
2367 | } | |||
2368 | ||||
2369 | bool isNEONi32vmovNeg() const { | |||
2370 | if (!isImm()) return false; | |||
2371 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2372 | // Must be a constant. | |||
2373 | if (!CE) return false; | |||
2374 | return isValidNEONi32vmovImm(~CE->getValue()); | |||
2375 | } | |||
2376 | ||||
2377 | bool isNEONi64splat() const { | |||
2378 | if (!isImm()) return false; | |||
2379 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2380 | // Must be a constant. | |||
2381 | if (!CE) return false; | |||
2382 | uint64_t Value = CE->getValue(); | |||
2383 | // i64 value with each byte being either 0 or 0xff. | |||
2384 | for (unsigned i = 0; i < 8; ++i, Value >>= 8) | |||
2385 | if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; | |||
2386 | return true; | |||
2387 | } | |||
2388 | ||||
2389 | template<int64_t Angle, int64_t Remainder> | |||
2390 | bool isComplexRotation() const { | |||
2391 | if (!isImm()) return false; | |||
2392 | ||||
2393 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2394 | if (!CE) return false; | |||
2395 | uint64_t Value = CE->getValue(); | |||
2396 | ||||
2397 | return (Value % Angle == Remainder && Value <= 270); | |||
2398 | } | |||
2399 | ||||
2400 | bool isMVELongShift() const { | |||
2401 | if (!isImm()) return false; | |||
2402 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2403 | // Must be a constant. | |||
2404 | if (!CE) return false; | |||
2405 | uint64_t Value = CE->getValue(); | |||
2406 | return Value >= 1 && Value <= 32; | |||
2407 | } | |||
2408 | ||||
2409 | bool isMveSaturateOp() const { | |||
2410 | if (!isImm()) return false; | |||
2411 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2412 | if (!CE) return false; | |||
2413 | uint64_t Value = CE->getValue(); | |||
2414 | return Value == 48 || Value == 64; | |||
2415 | } | |||
2416 | ||||
2417 | bool isITCondCodeNoAL() const { | |||
2418 | if (!isITCondCode()) return false; | |||
2419 | ARMCC::CondCodes CC = getCondCode(); | |||
2420 | return CC != ARMCC::AL; | |||
2421 | } | |||
2422 | ||||
2423 | bool isITCondCodeRestrictedI() const { | |||
2424 | if (!isITCondCode()) | |||
2425 | return false; | |||
2426 | ARMCC::CondCodes CC = getCondCode(); | |||
2427 | return CC == ARMCC::EQ || CC == ARMCC::NE; | |||
2428 | } | |||
2429 | ||||
2430 | bool isITCondCodeRestrictedS() const { | |||
2431 | if (!isITCondCode()) | |||
2432 | return false; | |||
2433 | ARMCC::CondCodes CC = getCondCode(); | |||
2434 | return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE || | |||
2435 | CC == ARMCC::GE; | |||
2436 | } | |||
2437 | ||||
2438 | bool isITCondCodeRestrictedU() const { | |||
2439 | if (!isITCondCode()) | |||
2440 | return false; | |||
2441 | ARMCC::CondCodes CC = getCondCode(); | |||
2442 | return CC == ARMCC::HS || CC == ARMCC::HI; | |||
2443 | } | |||
2444 | ||||
2445 | bool isITCondCodeRestrictedFP() const { | |||
2446 | if (!isITCondCode()) | |||
2447 | return false; | |||
2448 | ARMCC::CondCodes CC = getCondCode(); | |||
2449 | return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT || | |||
2450 | CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE; | |||
2451 | } | |||
2452 | ||||
2453 | void addExpr(MCInst &Inst, const MCExpr *Expr) const { | |||
2454 | // Add as immediates when possible. Null MCExpr = 0. | |||
2455 | if (!Expr) | |||
2456 | Inst.addOperand(MCOperand::createImm(0)); | |||
2457 | else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) | |||
2458 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2459 | else | |||
2460 | Inst.addOperand(MCOperand::createExpr(Expr)); | |||
2461 | } | |||
2462 | ||||
2463 | void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const { | |||
2464 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2465 | addExpr(Inst, getImm()); | |||
2466 | } | |||
2467 | ||||
2468 | void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const { | |||
2469 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2470 | addExpr(Inst, getImm()); | |||
2471 | } | |||
2472 | ||||
2473 | void addCondCodeOperands(MCInst &Inst, unsigned N) const { | |||
2474 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2475 | Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); | |||
2476 | unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; | |||
2477 | Inst.addOperand(MCOperand::createReg(RegNum)); | |||
2478 | } | |||
2479 | ||||
2480 | void addVPTPredNOperands(MCInst &Inst, unsigned N) const { | |||
2481 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2482 | Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); | |||
2483 | unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; | |||
2484 | Inst.addOperand(MCOperand::createReg(RegNum)); | |||
2485 | Inst.addOperand(MCOperand::createReg(0)); | |||
2486 | } | |||
2487 | ||||
2488 | void addVPTPredROperands(MCInst &Inst, unsigned N) const { | |||
2489 | assert(N == 4 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2490 | addVPTPredNOperands(Inst, N-1); | |||
2491 | unsigned RegNum; | |||
2492 | if (getVPTPred() == ARMVCC::None) { | |||
2493 | RegNum = 0; | |||
2494 | } else { | |||
2495 | unsigned NextOpIndex = Inst.getNumOperands(); | |||
2496 | const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()]; | |||
2497 | int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); | |||
2498 | assert(TiedOp >= 0 &&(static_cast<void> (0)) | |||
2499 | "Inactive register in vpred_r is not tied to an output!")(static_cast<void> (0)); | |||
2500 | RegNum = Inst.getOperand(TiedOp).getReg(); | |||
2501 | } | |||
2502 | Inst.addOperand(MCOperand::createReg(RegNum)); | |||
2503 | } | |||
2504 | ||||
2505 | void addCoprocNumOperands(MCInst &Inst, unsigned N) const { | |||
2506 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2507 | Inst.addOperand(MCOperand::createImm(getCoproc())); | |||
2508 | } | |||
2509 | ||||
2510 | void addCoprocRegOperands(MCInst &Inst, unsigned N) const { | |||
2511 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2512 | Inst.addOperand(MCOperand::createImm(getCoproc())); | |||
2513 | } | |||
2514 | ||||
2515 | void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { | |||
2516 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2517 | Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); | |||
2518 | } | |||
2519 | ||||
2520 | void addITMaskOperands(MCInst &Inst, unsigned N) const { | |||
2521 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2522 | Inst.addOperand(MCOperand::createImm(ITMask.Mask)); | |||
2523 | } | |||
2524 | ||||
2525 | void addITCondCodeOperands(MCInst &Inst, unsigned N) const { | |||
2526 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2527 | Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); | |||
2528 | } | |||
2529 | ||||
2530 | void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const { | |||
2531 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2532 | Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); | |||
2533 | } | |||
2534 | ||||
2535 | void addCCOutOperands(MCInst &Inst, unsigned N) const { | |||
2536 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2537 | Inst.addOperand(MCOperand::createReg(getReg())); | |||
2538 | } | |||
2539 | ||||
2540 | void addRegOperands(MCInst &Inst, unsigned N) const { | |||
2541 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2542 | Inst.addOperand(MCOperand::createReg(getReg())); | |||
2543 | } | |||
2544 | ||||
2545 | void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { | |||
2546 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2547 | assert(isRegShiftedReg() &&(static_cast<void> (0)) | |||
2548 | "addRegShiftedRegOperands() on non-RegShiftedReg!")(static_cast<void> (0)); | |||
2549 | Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); | |||
2550 | Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); | |||
2551 | Inst.addOperand(MCOperand::createImm( | |||
2552 | ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); | |||
2553 | } | |||
2554 | ||||
2555 | void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { | |||
2556 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2557 | assert(isRegShiftedImm() &&(static_cast<void> (0)) | |||
2558 | "addRegShiftedImmOperands() on non-RegShiftedImm!")(static_cast<void> (0)); | |||
2559 | Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); | |||
2560 | // Shift of #32 is encoded as 0 where permitted | |||
2561 | unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); | |||
2562 | Inst.addOperand(MCOperand::createImm( | |||
2563 | ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); | |||
2564 | } | |||
2565 | ||||
2566 | void addShifterImmOperands(MCInst &Inst, unsigned N) const { | |||
2567 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2568 | Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | | |||
2569 | ShifterImm.Imm)); | |||
2570 | } | |||
2571 | ||||
2572 | void addRegListOperands(MCInst &Inst, unsigned N) const { | |||
2573 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2574 | const SmallVectorImpl<unsigned> &RegList = getRegList(); | |||
2575 | for (SmallVectorImpl<unsigned>::const_iterator | |||
2576 | I = RegList.begin(), E = RegList.end(); I != E; ++I) | |||
2577 | Inst.addOperand(MCOperand::createReg(*I)); | |||
2578 | } | |||
2579 | ||||
2580 | void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const { | |||
2581 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2582 | const SmallVectorImpl<unsigned> &RegList = getRegList(); | |||
2583 | for (SmallVectorImpl<unsigned>::const_iterator | |||
2584 | I = RegList.begin(), E = RegList.end(); I != E; ++I) | |||
2585 | Inst.addOperand(MCOperand::createReg(*I)); | |||
2586 | } | |||
2587 | ||||
2588 | void addDPRRegListOperands(MCInst &Inst, unsigned N) const { | |||
2589 | addRegListOperands(Inst, N); | |||
2590 | } | |||
2591 | ||||
2592 | void addSPRRegListOperands(MCInst &Inst, unsigned N) const { | |||
2593 | addRegListOperands(Inst, N); | |||
2594 | } | |||
2595 | ||||
2596 | void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const { | |||
2597 | addRegListOperands(Inst, N); | |||
2598 | } | |||
2599 | ||||
2600 | void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const { | |||
2601 | addRegListOperands(Inst, N); | |||
2602 | } | |||
2603 | ||||
2604 | void addRotImmOperands(MCInst &Inst, unsigned N) const { | |||
2605 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2606 | // Encoded as val>>3. The printer handles display as 8, 16, 24. | |||
2607 | Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); | |||
2608 | } | |||
2609 | ||||
2610 | void addModImmOperands(MCInst &Inst, unsigned N) const { | |||
2611 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2612 | ||||
2613 | // Support for fixups (MCFixup) | |||
2614 | if (isImm()) | |||
2615 | return addImmOperands(Inst, N); | |||
2616 | ||||
2617 | Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); | |||
2618 | } | |||
2619 | ||||
2620 | void addModImmNotOperands(MCInst &Inst, unsigned N) const { | |||
2621 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2622 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2623 | uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); | |||
2624 | Inst.addOperand(MCOperand::createImm(Enc)); | |||
2625 | } | |||
2626 | ||||
2627 | void addModImmNegOperands(MCInst &Inst, unsigned N) const { | |||
2628 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2629 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2630 | uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); | |||
2631 | Inst.addOperand(MCOperand::createImm(Enc)); | |||
2632 | } | |||
2633 | ||||
2634 | void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const { | |||
2635 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2636 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2637 | uint32_t Val = -CE->getValue(); | |||
2638 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2639 | } | |||
2640 | ||||
2641 | void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const { | |||
2642 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2643 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2644 | uint32_t Val = -CE->getValue(); | |||
2645 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2646 | } | |||
2647 | ||||
2648 | void addBitfieldOperands(MCInst &Inst, unsigned N) const { | |||
2649 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2650 | // Munge the lsb/width into a bitfield mask. | |||
2651 | unsigned lsb = Bitfield.LSB; | |||
2652 | unsigned width = Bitfield.Width; | |||
2653 | // Make a 32-bit mask w/ the referenced bits clear and all other bits set. | |||
2654 | uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> | |||
2655 | (32 - (lsb + width))); | |||
2656 | Inst.addOperand(MCOperand::createImm(Mask)); | |||
2657 | } | |||
2658 | ||||
2659 | void addImmOperands(MCInst &Inst, unsigned N) const { | |||
2660 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2661 | addExpr(Inst, getImm()); | |||
2662 | } | |||
2663 | ||||
2664 | void addFBits16Operands(MCInst &Inst, unsigned N) const { | |||
2665 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2666 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2667 | Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); | |||
2668 | } | |||
2669 | ||||
2670 | void addFBits32Operands(MCInst &Inst, unsigned N) const { | |||
2671 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2672 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2673 | Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); | |||
2674 | } | |||
2675 | ||||
2676 | void addFPImmOperands(MCInst &Inst, unsigned N) const { | |||
2677 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2678 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2679 | int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); | |||
2680 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2681 | } | |||
2682 | ||||
2683 | void addImm8s4Operands(MCInst &Inst, unsigned N) const { | |||
2684 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2685 | // FIXME: We really want to scale the value here, but the LDRD/STRD | |||
2686 | // instruction don't encode operands that way yet. | |||
2687 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2688 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2689 | } | |||
2690 | ||||
2691 | void addImm7s4Operands(MCInst &Inst, unsigned N) const { | |||
2692 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2693 | // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR | |||
2694 | // instruction don't encode operands that way yet. | |||
2695 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2696 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2697 | } | |||
2698 | ||||
2699 | void addImm7Shift0Operands(MCInst &Inst, unsigned N) const { | |||
2700 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2701 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2702 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2703 | } | |||
2704 | ||||
2705 | void addImm7Shift1Operands(MCInst &Inst, unsigned N) const { | |||
2706 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2707 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2708 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2709 | } | |||
2710 | ||||
2711 | void addImm7Shift2Operands(MCInst &Inst, unsigned N) const { | |||
2712 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2713 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2714 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2715 | } | |||
2716 | ||||
2717 | void addImm7Operands(MCInst &Inst, unsigned N) const { | |||
2718 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2719 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2720 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2721 | } | |||
2722 | ||||
2723 | void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { | |||
2724 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2725 | // The immediate is scaled by four in the encoding and is stored | |||
2726 | // in the MCInst as such. Lop off the low two bits here. | |||
2727 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2728 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); | |||
2729 | } | |||
2730 | ||||
2731 | void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { | |||
2732 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2733 | // The immediate is scaled by four in the encoding and is stored | |||
2734 | // in the MCInst as such. Lop off the low two bits here. | |||
2735 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2736 | Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); | |||
2737 | } | |||
2738 | ||||
2739 | void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { | |||
2740 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2741 | // The immediate is scaled by four in the encoding and is stored | |||
2742 | // in the MCInst as such. Lop off the low two bits here. | |||
2743 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2744 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); | |||
2745 | } | |||
2746 | ||||
2747 | void addImm1_16Operands(MCInst &Inst, unsigned N) const { | |||
2748 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2749 | // The constant encodes as the immediate-1, and we store in the instruction | |||
2750 | // the bits as encoded, so subtract off one here. | |||
2751 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2752 | Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); | |||
2753 | } | |||
2754 | ||||
2755 | void addImm1_32Operands(MCInst &Inst, unsigned N) const { | |||
2756 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2757 | // The constant encodes as the immediate-1, and we store in the instruction | |||
2758 | // the bits as encoded, so subtract off one here. | |||
2759 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2760 | Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); | |||
2761 | } | |||
2762 | ||||
2763 | void addImmThumbSROperands(MCInst &Inst, unsigned N) const { | |||
2764 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2765 | // The constant encodes as the immediate, except for 32, which encodes as | |||
2766 | // zero. | |||
2767 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2768 | unsigned Imm = CE->getValue(); | |||
2769 | Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); | |||
2770 | } | |||
2771 | ||||
2772 | void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { | |||
2773 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2774 | // An ASR value of 32 encodes as 0, so that's how we want to add it to | |||
2775 | // the instruction as well. | |||
2776 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2777 | int Val = CE->getValue(); | |||
2778 | Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); | |||
2779 | } | |||
2780 | ||||
2781 | void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { | |||
2782 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2783 | // The operand is actually a t2_so_imm, but we have its bitwise | |||
2784 | // negation in the assembly source, so twiddle it here. | |||
2785 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2786 | Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue())); | |||
2787 | } | |||
2788 | ||||
2789 | void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { | |||
2790 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2791 | // The operand is actually a t2_so_imm, but we have its | |||
2792 | // negation in the assembly source, so twiddle it here. | |||
2793 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2794 | Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); | |||
2795 | } | |||
2796 | ||||
2797 | void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { | |||
2798 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2799 | // The operand is actually an imm0_4095, but we have its | |||
2800 | // negation in the assembly source, so twiddle it here. | |||
2801 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2802 | Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); | |||
2803 | } | |||
2804 | ||||
2805 | void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { | |||
2806 | if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { | |||
2807 | Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); | |||
2808 | return; | |||
2809 | } | |||
2810 | const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val); | |||
2811 | Inst.addOperand(MCOperand::createExpr(SR)); | |||
2812 | } | |||
2813 | ||||
2814 | void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { | |||
2815 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2816 | if (isImm()) { | |||
2817 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
2818 | if (CE) { | |||
2819 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2820 | return; | |||
2821 | } | |||
2822 | const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val); | |||
2823 | Inst.addOperand(MCOperand::createExpr(SR)); | |||
2824 | return; | |||
2825 | } | |||
2826 | ||||
2827 | assert(isGPRMem() && "Unknown value type!")(static_cast<void> (0)); | |||
2828 | assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!")(static_cast<void> (0)); | |||
2829 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
2830 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2831 | else | |||
2832 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
2833 | } | |||
2834 | ||||
2835 | void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { | |||
2836 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2837 | Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); | |||
2838 | } | |||
2839 | ||||
2840 | void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { | |||
2841 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2842 | Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); | |||
2843 | } | |||
2844 | ||||
2845 | void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { | |||
2846 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2847 | Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt()))); | |||
2848 | } | |||
2849 | ||||
2850 | void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { | |||
2851 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2852 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2853 | } | |||
2854 | ||||
2855 | void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const { | |||
2856 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2857 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2858 | } | |||
2859 | ||||
2860 | void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const { | |||
2861 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2862 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2863 | } | |||
2864 | ||||
2865 | void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const { | |||
2866 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2867 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2868 | } | |||
2869 | ||||
2870 | void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { | |||
2871 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2872 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
2873 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
2874 | else | |||
2875 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
2876 | } | |||
2877 | ||||
2878 | void addAdrLabelOperands(MCInst &Inst, unsigned N) const { | |||
2879 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2880 | assert(isImm() && "Not an immediate!")(static_cast<void> (0)); | |||
2881 | ||||
2882 | // If we have an immediate that's not a constant, treat it as a label | |||
2883 | // reference needing a fixup. | |||
2884 | if (!isa<MCConstantExpr>(getImm())) { | |||
2885 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
2886 | return; | |||
2887 | } | |||
2888 | ||||
2889 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
2890 | int Val = CE->getValue(); | |||
2891 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2892 | } | |||
2893 | ||||
2894 | void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { | |||
2895 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2896 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2897 | Inst.addOperand(MCOperand::createImm(Memory.Alignment)); | |||
2898 | } | |||
2899 | ||||
2900 | void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { | |||
2901 | addAlignedMemoryOperands(Inst, N); | |||
2902 | } | |||
2903 | ||||
2904 | void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { | |||
2905 | addAlignedMemoryOperands(Inst, N); | |||
2906 | } | |||
2907 | ||||
2908 | void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { | |||
2909 | addAlignedMemoryOperands(Inst, N); | |||
2910 | } | |||
2911 | ||||
2912 | void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { | |||
2913 | addAlignedMemoryOperands(Inst, N); | |||
2914 | } | |||
2915 | ||||
2916 | void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { | |||
2917 | addAlignedMemoryOperands(Inst, N); | |||
2918 | } | |||
2919 | ||||
2920 | void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { | |||
2921 | addAlignedMemoryOperands(Inst, N); | |||
2922 | } | |||
2923 | ||||
2924 | void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { | |||
2925 | addAlignedMemoryOperands(Inst, N); | |||
2926 | } | |||
2927 | ||||
2928 | void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { | |||
2929 | addAlignedMemoryOperands(Inst, N); | |||
2930 | } | |||
2931 | ||||
2932 | void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { | |||
2933 | addAlignedMemoryOperands(Inst, N); | |||
2934 | } | |||
2935 | ||||
2936 | void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { | |||
2937 | addAlignedMemoryOperands(Inst, N); | |||
2938 | } | |||
2939 | ||||
2940 | void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { | |||
2941 | addAlignedMemoryOperands(Inst, N); | |||
2942 | } | |||
2943 | ||||
2944 | void addAddrMode2Operands(MCInst &Inst, unsigned N) const { | |||
2945 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2946 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
2947 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
2948 | if (!Memory.OffsetRegNum) { | |||
2949 | if (!Memory.OffsetImm) | |||
2950 | Inst.addOperand(MCOperand::createImm(0)); | |||
2951 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
2952 | int32_t Val = CE->getValue(); | |||
2953 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
2954 | // Special case for #-0 | |||
2955 | if (Val == std::numeric_limits<int32_t>::min()) | |||
2956 | Val = 0; | |||
2957 | if (Val < 0) | |||
2958 | Val = -Val; | |||
2959 | Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); | |||
2960 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2961 | } else | |||
2962 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
2963 | } else { | |||
2964 | // For register offset, we encode the shift type and negation flag | |||
2965 | // here. | |||
2966 | int32_t Val = | |||
2967 | ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, | |||
2968 | Memory.ShiftImm, Memory.ShiftType); | |||
2969 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2970 | } | |||
2971 | } | |||
2972 | ||||
2973 | void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { | |||
2974 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2975 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
| ||||
2976 | assert(CE && "non-constant AM2OffsetImm operand!")(static_cast<void> (0)); | |||
2977 | int32_t Val = CE->getValue(); | |||
| ||||
2978 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
2979 | // Special case for #-0 | |||
2980 | if (Val == std::numeric_limits<int32_t>::min()) Val = 0; | |||
2981 | if (Val < 0) Val = -Val; | |||
2982 | Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); | |||
2983 | Inst.addOperand(MCOperand::createReg(0)); | |||
2984 | Inst.addOperand(MCOperand::createImm(Val)); | |||
2985 | } | |||
2986 | ||||
2987 | void addAddrMode3Operands(MCInst &Inst, unsigned N) const { | |||
2988 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
2989 | // If we have an immediate that's not a constant, treat it as a label | |||
2990 | // reference needing a fixup. If it is a constant, it's something else | |||
2991 | // and we reject it. | |||
2992 | if (isImm()) { | |||
2993 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
2994 | Inst.addOperand(MCOperand::createReg(0)); | |||
2995 | Inst.addOperand(MCOperand::createImm(0)); | |||
2996 | return; | |||
2997 | } | |||
2998 | ||||
2999 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3000 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3001 | if (!Memory.OffsetRegNum) { | |||
3002 | if (!Memory.OffsetImm) | |||
3003 | Inst.addOperand(MCOperand::createImm(0)); | |||
3004 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
3005 | int32_t Val = CE->getValue(); | |||
3006 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
3007 | // Special case for #-0 | |||
3008 | if (Val == std::numeric_limits<int32_t>::min()) | |||
3009 | Val = 0; | |||
3010 | if (Val < 0) | |||
3011 | Val = -Val; | |||
3012 | Val = ARM_AM::getAM3Opc(AddSub, Val); | |||
3013 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3014 | } else | |||
3015 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3016 | } else { | |||
3017 | // For register offset, we encode the shift type and negation flag | |||
3018 | // here. | |||
3019 | int32_t Val = | |||
3020 | ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); | |||
3021 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3022 | } | |||
3023 | } | |||
3024 | ||||
3025 | void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3026 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3027 | if (Kind == k_PostIndexRegister) { | |||
3028 | int32_t Val = | |||
3029 | ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); | |||
3030 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); | |||
3031 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3032 | return; | |||
3033 | } | |||
3034 | ||||
3035 | // Constant offset. | |||
3036 | const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); | |||
3037 | int32_t Val = CE->getValue(); | |||
3038 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
3039 | // Special case for #-0 | |||
3040 | if (Val == std::numeric_limits<int32_t>::min()) Val = 0; | |||
3041 | if (Val < 0) Val = -Val; | |||
3042 | Val = ARM_AM::getAM3Opc(AddSub, Val); | |||
3043 | Inst.addOperand(MCOperand::createReg(0)); | |||
3044 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3045 | } | |||
3046 | ||||
3047 | void addAddrMode5Operands(MCInst &Inst, unsigned N) const { | |||
3048 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3049 | // If we have an immediate that's not a constant, treat it as a label | |||
3050 | // reference needing a fixup. If it is a constant, it's something else | |||
3051 | // and we reject it. | |||
3052 | if (isImm()) { | |||
3053 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
3054 | Inst.addOperand(MCOperand::createImm(0)); | |||
3055 | return; | |||
3056 | } | |||
3057 | ||||
3058 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3059 | if (!Memory.OffsetImm) | |||
3060 | Inst.addOperand(MCOperand::createImm(0)); | |||
3061 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
3062 | // The lower two bits are always zero and as such are not encoded. | |||
3063 | int32_t Val = CE->getValue() / 4; | |||
3064 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
3065 | // Special case for #-0 | |||
3066 | if (Val == std::numeric_limits<int32_t>::min()) | |||
3067 | Val = 0; | |||
3068 | if (Val < 0) | |||
3069 | Val = -Val; | |||
3070 | Val = ARM_AM::getAM5Opc(AddSub, Val); | |||
3071 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3072 | } else | |||
3073 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3074 | } | |||
3075 | ||||
3076 | void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const { | |||
3077 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3078 | // If we have an immediate that's not a constant, treat it as a label | |||
3079 | // reference needing a fixup. If it is a constant, it's something else | |||
3080 | // and we reject it. | |||
3081 | if (isImm()) { | |||
3082 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
3083 | Inst.addOperand(MCOperand::createImm(0)); | |||
3084 | return; | |||
3085 | } | |||
3086 | ||||
3087 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3088 | // The lower bit is always zero and as such is not encoded. | |||
3089 | if (!Memory.OffsetImm) | |||
3090 | Inst.addOperand(MCOperand::createImm(0)); | |||
3091 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { | |||
3092 | int32_t Val = CE->getValue() / 2; | |||
3093 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; | |||
3094 | // Special case for #-0 | |||
3095 | if (Val == std::numeric_limits<int32_t>::min()) | |||
3096 | Val = 0; | |||
3097 | if (Val < 0) | |||
3098 | Val = -Val; | |||
3099 | Val = ARM_AM::getAM5FP16Opc(AddSub, Val); | |||
3100 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3101 | } else | |||
3102 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3103 | } | |||
3104 | ||||
3105 | void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3106 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3107 | // If we have an immediate that's not a constant, treat it as a label | |||
3108 | // reference needing a fixup. If it is a constant, it's something else | |||
3109 | // and we reject it. | |||
3110 | if (isImm()) { | |||
3111 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
3112 | Inst.addOperand(MCOperand::createImm(0)); | |||
3113 | return; | |||
3114 | } | |||
3115 | ||||
3116 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3117 | addExpr(Inst, Memory.OffsetImm); | |||
3118 | } | |||
3119 | ||||
3120 | void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3121 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3122 | // If we have an immediate that's not a constant, treat it as a label | |||
3123 | // reference needing a fixup. If it is a constant, it's something else | |||
3124 | // and we reject it. | |||
3125 | if (isImm()) { | |||
3126 | Inst.addOperand(MCOperand::createExpr(getImm())); | |||
3127 | Inst.addOperand(MCOperand::createImm(0)); | |||
3128 | return; | |||
3129 | } | |||
3130 | ||||
3131 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3132 | addExpr(Inst, Memory.OffsetImm); | |||
3133 | } | |||
3134 | ||||
3135 | void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3136 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3137 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3138 | if (!Memory.OffsetImm) | |||
3139 | Inst.addOperand(MCOperand::createImm(0)); | |||
3140 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
3141 | // The lower two bits are always zero and as such are not encoded. | |||
3142 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); | |||
3143 | else | |||
3144 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3145 | } | |||
3146 | ||||
3147 | void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const { | |||
3148 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3149 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3150 | addExpr(Inst, Memory.OffsetImm); | |||
3151 | } | |||
3152 | ||||
3153 | void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const { | |||
3154 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3155 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3156 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3157 | } | |||
3158 | ||||
3159 | void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3160 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3161 | // If this is an immediate, it's a label reference. | |||
3162 | if (isImm()) { | |||
3163 | addExpr(Inst, getImm()); | |||
3164 | Inst.addOperand(MCOperand::createImm(0)); | |||
3165 | return; | |||
3166 | } | |||
3167 | ||||
3168 | // Otherwise, it's a normal memory reg+offset. | |||
3169 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3170 | addExpr(Inst, Memory.OffsetImm); | |||
3171 | } | |||
3172 | ||||
3173 | void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { | |||
3174 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3175 | // If this is an immediate, it's a label reference. | |||
3176 | if (isImm()) { | |||
3177 | addExpr(Inst, getImm()); | |||
3178 | Inst.addOperand(MCOperand::createImm(0)); | |||
3179 | return; | |||
3180 | } | |||
3181 | ||||
3182 | // Otherwise, it's a normal memory reg+offset. | |||
3183 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3184 | addExpr(Inst, Memory.OffsetImm); | |||
3185 | } | |||
3186 | ||||
3187 | void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const { | |||
3188 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3189 | // This is container for the immediate that we will create the constant | |||
3190 | // pool from | |||
3191 | addExpr(Inst, getConstantPoolImm()); | |||
3192 | } | |||
3193 | ||||
3194 | void addMemTBBOperands(MCInst &Inst, unsigned N) const { | |||
3195 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3196 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3197 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3198 | } | |||
3199 | ||||
3200 | void addMemTBHOperands(MCInst &Inst, unsigned N) const { | |||
3201 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3202 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3203 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3204 | } | |||
3205 | ||||
3206 | void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { | |||
3207 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3208 | unsigned Val = | |||
3209 | ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, | |||
3210 | Memory.ShiftImm, Memory.ShiftType); | |||
3211 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3212 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3213 | Inst.addOperand(MCOperand::createImm(Val)); | |||
3214 | } | |||
3215 | ||||
3216 | void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { | |||
3217 | assert(N == 3 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3218 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3219 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3220 | Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); | |||
3221 | } | |||
3222 | ||||
3223 | void addMemThumbRROperands(MCInst &Inst, unsigned N) const { | |||
3224 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3225 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3226 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); | |||
3227 | } | |||
3228 | ||||
3229 | void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { | |||
3230 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3231 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3232 | if (!Memory.OffsetImm) | |||
3233 | Inst.addOperand(MCOperand::createImm(0)); | |||
3234 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
3235 | // The lower two bits are always zero and as such are not encoded. | |||
3236 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); | |||
3237 | else | |||
3238 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3239 | } | |||
3240 | ||||
3241 | void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { | |||
3242 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3243 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3244 | if (!Memory.OffsetImm) | |||
3245 | Inst.addOperand(MCOperand::createImm(0)); | |||
3246 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
3247 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 2)); | |||
3248 | else | |||
3249 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3250 | } | |||
3251 | ||||
3252 | void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { | |||
3253 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3254 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3255 | addExpr(Inst, Memory.OffsetImm); | |||
3256 | } | |||
3257 | ||||
3258 | void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { | |||
3259 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3260 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); | |||
3261 | if (!Memory.OffsetImm) | |||
3262 | Inst.addOperand(MCOperand::createImm(0)); | |||
3263 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) | |||
3264 | // The lower two bits are always zero and as such are not encoded. | |||
3265 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); | |||
3266 | else | |||
3267 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); | |||
3268 | } | |||
3269 | ||||
3270 | void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { | |||
3271 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3272 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
3273 | assert(CE && "non-constant post-idx-imm8 operand!")(static_cast<void> (0)); | |||
3274 | int Imm = CE->getValue(); | |||
3275 | bool isAdd = Imm >= 0; | |||
3276 | if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; | |||
3277 | Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; | |||
3278 | Inst.addOperand(MCOperand::createImm(Imm)); | |||
3279 | } | |||
3280 | ||||
3281 | void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { | |||
3282 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3283 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); | |||
3284 | assert(CE && "non-constant post-idx-imm8s4 operand!")(static_cast<void> (0)); | |||
3285 | int Imm = CE->getValue(); | |||
3286 | bool isAdd = Imm >= 0; | |||
3287 | if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; | |||
3288 | // Immediate is scaled by 4. | |||
3289 | Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; | |||
3290 | Inst.addOperand(MCOperand::createImm(Imm)); | |||
3291 | } | |||
3292 | ||||
3293 | void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { | |||
3294 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3295 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); | |||
3296 | Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); | |||
3297 | } | |||
3298 | ||||
3299 | void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { | |||
3300 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3301 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); | |||
3302 | // The sign, shift type, and shift amount are encoded in a single operand | |||
3303 | // using the AM2 encoding helpers. | |||
3304 | ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; | |||
3305 | unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, | |||
3306 | PostIdxReg.ShiftTy); | |||
3307 | Inst.addOperand(MCOperand::createImm(Imm)); | |||
3308 | } | |||
3309 | ||||
3310 | void addPowerTwoOperands(MCInst &Inst, unsigned N) const { | |||
3311 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3312 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3313 | Inst.addOperand(MCOperand::createImm(CE->getValue())); | |||
3314 | } | |||
3315 | ||||
3316 | void addMSRMaskOperands(MCInst &Inst, unsigned N) const { | |||
3317 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3318 | Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); | |||
3319 | } | |||
3320 | ||||
3321 | void addBankedRegOperands(MCInst &Inst, unsigned N) const { | |||
3322 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3323 | Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); | |||
3324 | } | |||
3325 | ||||
3326 | void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { | |||
3327 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3328 | Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); | |||
3329 | } | |||
3330 | ||||
3331 | void addVecListOperands(MCInst &Inst, unsigned N) const { | |||
3332 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3333 | Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); | |||
3334 | } | |||
3335 | ||||
3336 | void addMVEVecListOperands(MCInst &Inst, unsigned N) const { | |||
3337 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3338 | ||||
3339 | // When we come here, the VectorList field will identify a range | |||
3340 | // of q-registers by its base register and length, and it will | |||
3341 | // have already been error-checked to be the expected length of | |||
3342 | // range and contain only q-regs in the range q0-q7. So we can | |||
3343 | // count on the base register being in the range q0-q6 (for 2 | |||
3344 | // regs) or q0-q4 (for 4) | |||
3345 | // | |||
3346 | // The MVE instructions taking a register range of this kind will | |||
3347 | // need an operand in the MQQPR or MQQQQPR class, representing the | |||
3348 | // entire range as a unit. So we must translate into that class, | |||
3349 | // by finding the index of the base register in the MQPR reg | |||
3350 | // class, and returning the super-register at the corresponding | |||
3351 | // index in the target class. | |||
3352 | ||||
3353 | const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; | |||
3354 | const MCRegisterClass *RC_out = | |||
3355 | (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID] | |||
3356 | : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID]; | |||
3357 | ||||
3358 | unsigned I, E = RC_out->getNumRegs(); | |||
3359 | for (I = 0; I < E; I++) | |||
3360 | if (RC_in->getRegister(I) == VectorList.RegNum) | |||
3361 | break; | |||
3362 | assert(I < E && "Invalid vector list start register!")(static_cast<void> (0)); | |||
3363 | ||||
3364 | Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I))); | |||
3365 | } | |||
3366 | ||||
3367 | void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { | |||
3368 | assert(N == 2 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3369 | Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); | |||
3370 | Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); | |||
3371 | } | |||
3372 | ||||
3373 | void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { | |||
3374 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3375 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3376 | } | |||
3377 | ||||
3378 | void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { | |||
3379 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3380 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3381 | } | |||
3382 | ||||
3383 | void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { | |||
3384 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3385 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3386 | } | |||
3387 | ||||
3388 | void addVectorIndex64Operands(MCInst &Inst, unsigned N) const { | |||
3389 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3390 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3391 | } | |||
3392 | ||||
3393 | void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const { | |||
3394 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3395 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3396 | } | |||
3397 | ||||
3398 | void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const { | |||
3399 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3400 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); | |||
3401 | } | |||
3402 | ||||
3403 | void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { | |||
3404 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3405 | // The immediate encodes the type of constant as well as the value. | |||
3406 | // Mask in that this is an i8 splat. | |||
3407 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3408 | Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); | |||
3409 | } | |||
3410 | ||||
3411 | void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { | |||
3412 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3413 | // The immediate encodes the type of constant as well as the value. | |||
3414 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3415 | unsigned Value = CE->getValue(); | |||
3416 | Value = ARM_AM::encodeNEONi16splat(Value); | |||
3417 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3418 | } | |||
3419 | ||||
3420 | void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { | |||
3421 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3422 | // The immediate encodes the type of constant as well as the value. | |||
3423 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3424 | unsigned Value = CE->getValue(); | |||
3425 | Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); | |||
3426 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3427 | } | |||
3428 | ||||
3429 | void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { | |||
3430 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3431 | // The immediate encodes the type of constant as well as the value. | |||
3432 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3433 | unsigned Value = CE->getValue(); | |||
3434 | Value = ARM_AM::encodeNEONi32splat(Value); | |||
3435 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3436 | } | |||
3437 | ||||
3438 | void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { | |||
3439 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3440 | // The immediate encodes the type of constant as well as the value. | |||
3441 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3442 | unsigned Value = CE->getValue(); | |||
3443 | Value = ARM_AM::encodeNEONi32splat(~Value); | |||
3444 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3445 | } | |||
3446 | ||||
3447 | void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const { | |||
3448 | // The immediate encodes the type of constant as well as the value. | |||
3449 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3450 | assert((Inst.getOpcode() == ARM::VMOVv8i8 ||(static_cast<void> (0)) | |||
3451 | Inst.getOpcode() == ARM::VMOVv16i8) &&(static_cast<void> (0)) | |||
3452 | "All instructions that wants to replicate non-zero byte "(static_cast<void> (0)) | |||
3453 | "always must be replaced with VMOVv8i8 or VMOVv16i8.")(static_cast<void> (0)); | |||
3454 | unsigned Value = CE->getValue(); | |||
3455 | if (Inv) | |||
3456 | Value = ~Value; | |||
3457 | unsigned B = Value & 0xff; | |||
3458 | B |= 0xe00; // cmode = 0b1110 | |||
3459 | Inst.addOperand(MCOperand::createImm(B)); | |||
3460 | } | |||
3461 | ||||
3462 | void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const { | |||
3463 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3464 | addNEONi8ReplicateOperands(Inst, true); | |||
3465 | } | |||
3466 | ||||
3467 | static unsigned encodeNeonVMOVImmediate(unsigned Value) { | |||
3468 | if (Value >= 256 && Value <= 0xffff) | |||
3469 | Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); | |||
3470 | else if (Value > 0xffff && Value <= 0xffffff) | |||
3471 | Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); | |||
3472 | else if (Value > 0xffffff) | |||
3473 | Value = (Value >> 24) | 0x600; | |||
3474 | return Value; | |||
3475 | } | |||
3476 | ||||
3477 | void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { | |||
3478 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3479 | // The immediate encodes the type of constant as well as the value. | |||
3480 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3481 | unsigned Value = encodeNeonVMOVImmediate(CE->getValue()); | |||
3482 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3483 | } | |||
3484 | ||||
3485 | void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const { | |||
3486 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3487 | addNEONi8ReplicateOperands(Inst, false); | |||
3488 | } | |||
3489 | ||||
3490 | void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const { | |||
3491 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3492 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3493 | assert((Inst.getOpcode() == ARM::VMOVv4i16 ||(static_cast<void> (0)) | |||
3494 | Inst.getOpcode() == ARM::VMOVv8i16 ||(static_cast<void> (0)) | |||
3495 | Inst.getOpcode() == ARM::VMVNv4i16 ||(static_cast<void> (0)) | |||
3496 | Inst.getOpcode() == ARM::VMVNv8i16) &&(static_cast<void> (0)) | |||
3497 | "All instructions that want to replicate non-zero half-word "(static_cast<void> (0)) | |||
3498 | "always must be replaced with V{MOV,MVN}v{4,8}i16.")(static_cast<void> (0)); | |||
3499 | uint64_t Value = CE->getValue(); | |||
3500 | unsigned Elem = Value & 0xffff; | |||
3501 | if (Elem >= 256) | |||
3502 | Elem = (Elem >> 8) | 0x200; | |||
3503 | Inst.addOperand(MCOperand::createImm(Elem)); | |||
3504 | } | |||
3505 | ||||
3506 | void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { | |||
3507 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3508 | // The immediate encodes the type of constant as well as the value. | |||
3509 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3510 | unsigned Value = encodeNeonVMOVImmediate(~CE->getValue()); | |||
3511 | Inst.addOperand(MCOperand::createImm(Value)); | |||
3512 | } | |||
3513 | ||||
3514 | void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const { | |||
3515 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3516 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3517 | assert((Inst.getOpcode() == ARM::VMOVv2i32 ||(static_cast<void> (0)) | |||
3518 | Inst.getOpcode() == ARM::VMOVv4i32 ||(static_cast<void> (0)) | |||
3519 | Inst.getOpcode() == ARM::VMVNv2i32 ||(static_cast<void> (0)) | |||
3520 | Inst.getOpcode() == ARM::VMVNv4i32) &&(static_cast<void> (0)) | |||
3521 | "All instructions that want to replicate non-zero word "(static_cast<void> (0)) | |||
3522 | "always must be replaced with V{MOV,MVN}v{2,4}i32.")(static_cast<void> (0)); | |||
3523 | uint64_t Value = CE->getValue(); | |||
3524 | unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff); | |||
3525 | Inst.addOperand(MCOperand::createImm(Elem)); | |||
3526 | } | |||
3527 | ||||
3528 | void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { | |||
3529 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3530 | // The immediate encodes the type of constant as well as the value. | |||
3531 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3532 | uint64_t Value = CE->getValue(); | |||
3533 | unsigned Imm = 0; | |||
3534 | for (unsigned i = 0; i < 8; ++i, Value >>= 8) { | |||
3535 | Imm |= (Value & 1) << i; | |||
3536 | } | |||
3537 | Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); | |||
3538 | } | |||
3539 | ||||
3540 | void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const { | |||
3541 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3542 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3543 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 90)); | |||
3544 | } | |||
3545 | ||||
3546 | void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const { | |||
3547 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3548 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3549 | Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180)); | |||
3550 | } | |||
3551 | ||||
3552 | void addMveSaturateOperands(MCInst &Inst, unsigned N) const { | |||
3553 | assert(N == 1 && "Invalid number of operands!")(static_cast<void> (0)); | |||
3554 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); | |||
3555 | unsigned Imm = CE->getValue(); | |||
3556 | assert((Imm == 48 || Imm == 64) && "Invalid saturate operand")(static_cast<void> (0)); | |||
3557 | Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0)); | |||
3558 | } | |||
3559 | ||||
3560 | void print(raw_ostream &OS) const override; | |||
3561 | ||||
3562 | static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { | |||
3563 | auto Op = std::make_unique<ARMOperand>(k_ITCondMask); | |||
3564 | Op->ITMask.Mask = Mask; | |||
3565 | Op->StartLoc = S; | |||
3566 | Op->EndLoc = S; | |||
3567 | return Op; | |||
3568 | } | |||
3569 | ||||
3570 | static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, | |||
3571 | SMLoc S) { | |||
3572 | auto Op = std::make_unique<ARMOperand>(k_CondCode); | |||
3573 | Op->CC.Val = CC; | |||
3574 | Op->StartLoc = S; | |||
3575 | Op->EndLoc = S; | |||
3576 | return Op; | |||
3577 | } | |||
3578 | ||||
3579 | static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC, | |||
3580 | SMLoc S) { | |||
3581 | auto Op = std::make_unique<ARMOperand>(k_VPTPred); | |||
3582 | Op->VCC.Val = CC; | |||
3583 | Op->StartLoc = S; | |||
3584 | Op->EndLoc = S; | |||
3585 | return Op; | |||
3586 | } | |||
3587 | ||||
3588 | static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { | |||
3589 | auto Op = std::make_unique<ARMOperand>(k_CoprocNum); | |||
3590 | Op->Cop.Val = CopVal; | |||
3591 | Op->StartLoc = S; | |||
3592 | Op->EndLoc = S; | |||
3593 | return Op; | |||
3594 | } | |||
3595 | ||||
3596 | static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { | |||
3597 | auto Op = std::make_unique<ARMOperand>(k_CoprocReg); | |||
3598 | Op->Cop.Val = CopVal; | |||
3599 | Op->StartLoc = S; | |||
3600 | Op->EndLoc = S; | |||
3601 | return Op; | |||
3602 | } | |||
3603 | ||||
3604 | static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, | |||
3605 | SMLoc E) { | |||
3606 | auto Op = std::make_unique<ARMOperand>(k_CoprocOption); | |||
3607 | Op->Cop.Val = Val; | |||
3608 | Op->StartLoc = S; | |||
3609 | Op->EndLoc = E; | |||
3610 | return Op; | |||
3611 | } | |||
3612 | ||||
3613 | static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { | |||
3614 | auto Op = std::make_unique<ARMOperand>(k_CCOut); | |||
3615 | Op->Reg.RegNum = RegNum; | |||
3616 | Op->StartLoc = S; | |||
3617 | Op->EndLoc = S; | |||
3618 | return Op; | |||
3619 | } | |||
3620 | ||||
3621 | static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { | |||
3622 | auto Op = std::make_unique<ARMOperand>(k_Token); | |||
3623 | Op->Tok.Data = Str.data(); | |||
3624 | Op->Tok.Length = Str.size(); | |||
3625 | Op->StartLoc = S; | |||
3626 | Op->EndLoc = S; | |||
3627 | return Op; | |||
3628 | } | |||
3629 | ||||
3630 | static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, | |||
3631 | SMLoc E) { | |||
3632 | auto Op = std::make_unique<ARMOperand>(k_Register); | |||
3633 | Op->Reg.RegNum = RegNum; | |||
3634 | Op->StartLoc = S; | |||
3635 | Op->EndLoc = E; | |||
3636 | return Op; | |||
3637 | } | |||
3638 | ||||
3639 | static std::unique_ptr<ARMOperand> | |||
3640 | CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, | |||
3641 | unsigned ShiftReg, unsigned ShiftImm, SMLoc S, | |||
3642 | SMLoc E) { | |||
3643 | auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister); | |||
3644 | Op->RegShiftedReg.ShiftTy = ShTy; | |||
3645 | Op->RegShiftedReg.SrcReg = SrcReg; | |||
3646 | Op->RegShiftedReg.ShiftReg = ShiftReg; | |||
3647 | Op->RegShiftedReg.ShiftImm = ShiftImm; | |||
3648 | Op->StartLoc = S; | |||
3649 | Op->EndLoc = E; | |||
3650 | return Op; | |||
3651 | } | |||
3652 | ||||
3653 | static std::unique_ptr<ARMOperand> | |||
3654 | CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, | |||
3655 | unsigned ShiftImm, SMLoc S, SMLoc E) { | |||
3656 | auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate); | |||
3657 | Op->RegShiftedImm.ShiftTy = ShTy; | |||
3658 | Op->RegShiftedImm.SrcReg = SrcReg; | |||
3659 | Op->RegShiftedImm.ShiftImm = ShiftImm; | |||
3660 | Op->StartLoc = S; | |||
3661 | Op->EndLoc = E; | |||
3662 | return Op; | |||
3663 | } | |||
3664 | ||||
3665 | static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, | |||
3666 | SMLoc S, SMLoc E) { | |||
3667 | auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate); | |||
3668 | Op->ShifterImm.isASR = isASR; | |||
3669 | Op->ShifterImm.Imm = Imm; | |||
3670 | Op->StartLoc = S; | |||
3671 | Op->EndLoc = E; | |||
3672 | return Op; | |||
3673 | } | |||
3674 | ||||
3675 | static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, | |||
3676 | SMLoc E) { | |||
3677 | auto Op = std::make_unique<ARMOperand>(k_RotateImmediate); | |||
3678 | Op->RotImm.Imm = Imm; | |||
3679 | Op->StartLoc = S; | |||
3680 | Op->EndLoc = E; | |||
3681 | return Op; | |||
3682 | } | |||
3683 | ||||
3684 | static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, | |||
3685 | SMLoc S, SMLoc E) { | |||
3686 | auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate); | |||
3687 | Op->ModImm.Bits = Bits; | |||
3688 | Op->ModImm.Rot = Rot; | |||
3689 | Op->StartLoc = S; | |||
3690 | Op->EndLoc = E; | |||
3691 | return Op; | |||
3692 | } | |||
3693 | ||||
3694 | static std::unique_ptr<ARMOperand> | |||
3695 | CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) { | |||
3696 | auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate); | |||
3697 | Op->Imm.Val = Val; | |||
3698 | Op->StartLoc = S; | |||
3699 | Op->EndLoc = E; | |||
3700 | return Op; | |||
3701 | } | |||
3702 | ||||
3703 | static std::unique_ptr<ARMOperand> | |||
3704 | CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { | |||
3705 | auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor); | |||
3706 | Op->Bitfield.LSB = LSB; | |||
3707 | Op->Bitfield.Width = Width; | |||
3708 | Op->StartLoc = S; | |||
3709 | Op->EndLoc = E; | |||
3710 | return Op; | |||
3711 | } | |||
3712 | ||||
3713 | static std::unique_ptr<ARMOperand> | |||
3714 | CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, | |||
3715 | SMLoc StartLoc, SMLoc EndLoc) { | |||
3716 | assert(Regs.size() > 0 && "RegList contains no registers?")(static_cast<void> (0)); | |||
3717 | KindTy Kind = k_RegisterList; | |||
3718 | ||||
3719 | if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( | |||
3720 | Regs.front().second)) { | |||
3721 | if (Regs.back().second == ARM::VPR) | |||
3722 | Kind = k_FPDRegisterListWithVPR; | |||
3723 | else | |||
3724 | Kind = k_DPRRegisterList; | |||
3725 | } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( | |||
3726 | Regs.front().second)) { | |||
3727 | if (Regs.back().second == ARM::VPR) | |||
3728 | Kind = k_FPSRegisterListWithVPR; | |||
3729 | else | |||
3730 | Kind = k_SPRRegisterList; | |||
3731 | } | |||
3732 | ||||
3733 | if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) | |||
3734 | Kind = k_RegisterListWithAPSR; | |||
3735 | ||||
3736 | assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding")(static_cast<void> (0)); | |||
3737 | ||||
3738 | auto Op = std::make_unique<ARMOperand>(Kind); | |||
3739 | for (const auto &P : Regs) | |||
3740 | Op->Registers.push_back(P.second); | |||
3741 | ||||
3742 | Op->StartLoc = StartLoc; | |||
3743 | Op->EndLoc = EndLoc; | |||
3744 | return Op; | |||
3745 | } | |||
3746 | ||||
3747 | static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, | |||
3748 | unsigned Count, | |||
3749 | bool isDoubleSpaced, | |||
3750 | SMLoc S, SMLoc E) { | |||
3751 | auto Op = std::make_unique<ARMOperand>(k_VectorList); | |||
3752 | Op->VectorList.RegNum = RegNum; | |||
3753 | Op->VectorList.Count = Count; | |||
3754 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; | |||
3755 | Op->StartLoc = S; | |||
3756 | Op->EndLoc = E; | |||
3757 | return Op; | |||
3758 | } | |||
3759 | ||||
3760 | static std::unique_ptr<ARMOperand> | |||
3761 | CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, | |||
3762 | SMLoc S, SMLoc E) { | |||
3763 | auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes); | |||
3764 | Op->VectorList.RegNum = RegNum; | |||
3765 | Op->VectorList.Count = Count; | |||
3766 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; | |||
3767 | Op->StartLoc = S; | |||
3768 | Op->EndLoc = E; | |||
3769 | return Op; | |||
3770 | } | |||
3771 | ||||
3772 | static std::unique_ptr<ARMOperand> | |||
3773 | CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, | |||
3774 | bool isDoubleSpaced, SMLoc S, SMLoc E) { | |||
3775 | auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed); | |||
3776 | Op->VectorList.RegNum = RegNum; | |||
3777 | Op->VectorList.Count = Count; | |||
3778 | Op->VectorList.LaneIndex = Index; | |||
3779 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; | |||
3780 | Op->StartLoc = S; | |||
3781 | Op->EndLoc = E; | |||
3782 | return Op; | |||
3783 | } | |||
3784 | ||||
3785 | static std::unique_ptr<ARMOperand> | |||
3786 | CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { | |||
3787 | auto Op = std::make_unique<ARMOperand>(k_VectorIndex); | |||
3788 | Op->VectorIndex.Val = Idx; | |||
3789 | Op->StartLoc = S; | |||
3790 | Op->EndLoc = E; | |||
3791 | return Op; | |||
3792 | } | |||
3793 | ||||
3794 | static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, | |||
3795 | SMLoc E) { | |||
3796 | auto Op = std::make_unique<ARMOperand>(k_Immediate); | |||
3797 | Op->Imm.Val = Val; | |||
3798 | Op->StartLoc = S; | |||
3799 | Op->EndLoc = E; | |||
3800 | return Op; | |||
3801 | } | |||
3802 | ||||
3803 | static std::unique_ptr<ARMOperand> | |||
3804 | CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum, | |||
3805 | ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, | |||
3806 | bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) { | |||
3807 | auto Op = std::make_unique<ARMOperand>(k_Memory); | |||
3808 | Op->Memory.BaseRegNum = BaseRegNum; | |||
3809 | Op->Memory.OffsetImm = OffsetImm; | |||
3810 | Op->Memory.OffsetRegNum = OffsetRegNum; | |||
3811 | Op->Memory.ShiftType = ShiftType; | |||
3812 | Op->Memory.ShiftImm = ShiftImm; | |||
3813 | Op->Memory.Alignment = Alignment; | |||
3814 | Op->Memory.isNegative = isNegative; | |||
3815 | Op->StartLoc = S; | |||
3816 | Op->EndLoc = E; | |||
3817 | Op->AlignmentLoc = AlignmentLoc; | |||
3818 | return Op; | |||
3819 | } | |||
3820 | ||||
3821 | static std::unique_ptr<ARMOperand> | |||
3822 | CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, | |||
3823 | unsigned ShiftImm, SMLoc S, SMLoc E) { | |||
3824 | auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister); | |||
3825 | Op->PostIdxReg.RegNum = RegNum; | |||
3826 | Op->PostIdxReg.isAdd = isAdd; | |||
3827 | Op->PostIdxReg.ShiftTy = ShiftTy; | |||
3828 | Op->PostIdxReg.ShiftImm = ShiftImm; | |||
3829 | Op->StartLoc = S; | |||
3830 | Op->EndLoc = E; | |||
3831 | return Op; | |||
3832 | } | |||
3833 | ||||
3834 | static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, | |||
3835 | SMLoc S) { | |||
3836 | auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt); | |||
3837 | Op->MBOpt.Val = Opt; | |||
3838 | Op->StartLoc = S; | |||
3839 | Op->EndLoc = S; | |||
3840 | return Op; | |||
3841 | } | |||
3842 | ||||
3843 | static std::unique_ptr<ARMOperand> | |||
3844 | CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { | |||
3845 | auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt); | |||
3846 | Op->ISBOpt.Val = Opt; | |||
3847 | Op->StartLoc = S; | |||
3848 | Op->EndLoc = S; | |||
3849 | return Op; | |||
3850 | } | |||
3851 | ||||
3852 | static std::unique_ptr<ARMOperand> | |||
3853 | CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) { | |||
3854 | auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt); | |||
3855 | Op->TSBOpt.Val = Opt; | |||
3856 | Op->StartLoc = S; | |||
3857 | Op->EndLoc = S; | |||
3858 | return Op; | |||
3859 | } | |||
3860 | ||||
3861 | static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, | |||
3862 | SMLoc S) { | |||
3863 | auto Op = std::make_unique<ARMOperand>(k_ProcIFlags); | |||
3864 | Op->IFlags.Val = IFlags; | |||
3865 | Op->StartLoc = S; | |||
3866 | Op->EndLoc = S; | |||
3867 | return Op; | |||
3868 | } | |||
3869 | ||||
3870 | static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { | |||
3871 | auto Op = std::make_unique<ARMOperand>(k_MSRMask); | |||
3872 | Op->MMask.Val = MMask; | |||
3873 | Op->StartLoc = S; | |||
3874 | Op->EndLoc = S; | |||
3875 | return Op; | |||
3876 | } | |||
3877 | ||||
3878 | static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { | |||
3879 | auto Op = std::make_unique<ARMOperand>(k_BankedReg); | |||
3880 | Op->BankedReg.Val = Reg; | |||
3881 | Op->StartLoc = S; | |||
3882 | Op->EndLoc = S; | |||
3883 | return Op; | |||
3884 | } | |||
3885 | }; | |||
3886 | ||||
3887 | } // end anonymous namespace. | |||
3888 | ||||
3889 | void ARMOperand::print(raw_ostream &OS) const { | |||
3890 | auto RegName = [](unsigned Reg) { | |||
3891 | if (Reg) | |||
3892 | return ARMInstPrinter::getRegisterName(Reg); | |||
3893 | else | |||
3894 | return "noreg"; | |||
3895 | }; | |||
3896 | ||||
3897 | switch (Kind) { | |||
3898 | case k_CondCode: | |||
3899 | OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; | |||
3900 | break; | |||
3901 | case k_VPTPred: | |||
3902 | OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">"; | |||
3903 | break; | |||
3904 | case k_CCOut: | |||
3905 | OS << "<ccout " << RegName(getReg()) << ">"; | |||
3906 | break; | |||
3907 | case k_ITCondMask: { | |||
3908 | static const char *const MaskStr[] = { | |||
3909 | "(invalid)", "(tttt)", "(ttt)", "(ttte)", | |||
3910 | "(tt)", "(ttet)", "(tte)", "(ttee)", | |||
3911 | "(t)", "(tett)", "(tet)", "(tete)", | |||
3912 | "(te)", "(teet)", "(tee)", "(teee)", | |||
3913 | }; | |||
3914 | assert((ITMask.Mask & 0xf) == ITMask.Mask)(static_cast<void> (0)); | |||
3915 | OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; | |||
3916 | break; | |||
3917 | } | |||
3918 | case k_CoprocNum: | |||
3919 | OS << "<coprocessor number: " << getCoproc() << ">"; | |||
3920 | break; | |||
3921 | case k_CoprocReg: | |||
3922 | OS << "<coprocessor register: " << getCoproc() << ">"; | |||
3923 | break; | |||
3924 | case k_CoprocOption: | |||
3925 | OS << "<coprocessor option: " << CoprocOption.Val << ">"; | |||
3926 | break; | |||
3927 | case k_MSRMask: | |||
3928 | OS << "<mask: " << getMSRMask() << ">"; | |||
3929 | break; | |||
3930 | case k_BankedReg: | |||
3931 | OS << "<banked reg: " << getBankedReg() << ">"; | |||
3932 | break; | |||
3933 | case k_Immediate: | |||
3934 | OS << *getImm(); | |||
3935 | break; | |||
3936 | case k_MemBarrierOpt: | |||
3937 | OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; | |||
3938 | break; | |||
3939 | case k_InstSyncBarrierOpt: | |||
3940 | OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; | |||
3941 | break; | |||
3942 | case k_TraceSyncBarrierOpt: | |||
3943 | OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">"; | |||
3944 | break; | |||
3945 | case k_Memory: | |||
3946 | OS << "<memory"; | |||
3947 | if (Memory.BaseRegNum) | |||
3948 | OS << " base:" << RegName(Memory.BaseRegNum); | |||
3949 | if (Memory.OffsetImm) | |||
3950 | OS << " offset-imm:" << *Memory.OffsetImm; | |||
3951 | if (Memory.OffsetRegNum) | |||
3952 | OS << " offset-reg:" << (Memory.isNegative ? "-" : "") | |||
3953 | << RegName(Memory.OffsetRegNum); | |||
3954 | if (Memory.ShiftType != ARM_AM::no_shift) { | |||
3955 | OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType); | |||
3956 | OS << " shift-imm:" << Memory.ShiftImm; | |||
3957 | } | |||
3958 | if (Memory.Alignment) | |||
3959 | OS << " alignment:" << Memory.Alignment; | |||
3960 | OS << ">"; | |||
3961 | break; | |||
3962 | case k_PostIndexRegister: | |||
3963 | OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") | |||
3964 | << RegName(PostIdxReg.RegNum); | |||
3965 | if (PostIdxReg.ShiftTy != ARM_AM::no_shift) | |||
3966 | OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " | |||
3967 | << PostIdxReg.ShiftImm; | |||
3968 | OS << ">"; | |||
3969 | break; | |||
3970 | case k_ProcIFlags: { | |||
3971 | OS << "<ARM_PROC::"; | |||
3972 | unsigned IFlags = getProcIFlags(); | |||
3973 | for (int i=2; i >= 0; --i) | |||
3974 | if (IFlags & (1 << i)) | |||
3975 | OS << ARM_PROC::IFlagsToString(1 << i); | |||
3976 | OS << ">"; | |||
3977 | break; | |||
3978 | } | |||
3979 | case k_Register: | |||
3980 | OS << "<register " << RegName(getReg()) << ">"; | |||
3981 | break; | |||
3982 | case k_ShifterImmediate: | |||
3983 | OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") | |||
3984 | << " #" << ShifterImm.Imm << ">"; | |||
3985 | break; | |||
3986 | case k_ShiftedRegister: | |||
3987 | OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " " | |||
3988 | << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " " | |||
3989 | << RegName(RegShiftedReg.ShiftReg) << ">"; | |||
3990 | break; | |||
3991 | case k_ShiftedImmediate: | |||
3992 | OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " " | |||
3993 | << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #" | |||
3994 | << RegShiftedImm.ShiftImm << ">"; | |||
3995 | break; | |||
3996 | case k_RotateImmediate: | |||
3997 | OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; | |||
3998 | break; | |||
3999 | case k_ModifiedImmediate: | |||
4000 | OS << "<mod_imm #" << ModImm.Bits << ", #" | |||
4001 | << ModImm.Rot << ")>"; | |||
4002 | break; | |||
4003 | case k_ConstantPoolImmediate: | |||
4004 | OS << "<constant_pool_imm #" << *getConstantPoolImm(); | |||
4005 | break; | |||
4006 | case k_BitfieldDescriptor: | |||
4007 | OS << "<bitfield " << "lsb: " << Bitfield.LSB | |||
4008 | << ", width: " << Bitfield.Width << ">"; | |||
4009 | break; | |||
4010 | case k_RegisterList: | |||
4011 | case k_RegisterListWithAPSR: | |||
4012 | case k_DPRRegisterList: | |||
4013 | case k_SPRRegisterList: | |||
4014 | case k_FPSRegisterListWithVPR: | |||
4015 | case k_FPDRegisterListWithVPR: { | |||
4016 | OS << "<register_list "; | |||
4017 | ||||
4018 | const SmallVectorImpl<unsigned> &RegList = getRegList(); | |||
4019 | for (SmallVectorImpl<unsigned>::const_iterator | |||
4020 | I = RegList.begin(), E = RegList.end(); I != E; ) { | |||
4021 | OS << RegName(*I); | |||
4022 | if (++I < E) OS << ", "; | |||
4023 | } | |||
4024 | ||||
4025 | OS << ">"; | |||
4026 | break; | |||
4027 | } | |||
4028 | case k_VectorList: | |||
4029 | OS << "<vector_list " << VectorList.Count << " * " | |||
4030 | << RegName(VectorList.RegNum) << ">"; | |||
4031 | break; | |||
4032 | case k_VectorListAllLanes: | |||
4033 | OS << "<vector_list(all lanes) " << VectorList.Count << " * " | |||
4034 | << RegName(VectorList.RegNum) << ">"; | |||
4035 | break; | |||
4036 | case k_VectorListIndexed: | |||
4037 | OS << "<vector_list(lane " << VectorList.LaneIndex << ") " | |||
4038 | << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">"; | |||
4039 | break; | |||
4040 | case k_Token: | |||
4041 | OS << "'" << getToken() << "'"; | |||
4042 | break; | |||
4043 | case k_VectorIndex: | |||
4044 | OS << "<vectorindex " << getVectorIndex() << ">"; | |||
4045 | break; | |||
4046 | } | |||
4047 | } | |||
4048 | ||||
4049 | /// @name Auto-generated Match Functions | |||
4050 | /// { | |||
4051 | ||||
4052 | static unsigned MatchRegisterName(StringRef Name); | |||
4053 | ||||
4054 | /// } | |||
4055 | ||||
4056 | bool ARMAsmParser::ParseRegister(unsigned &RegNo, | |||
4057 | SMLoc &StartLoc, SMLoc &EndLoc) { | |||
4058 | const AsmToken &Tok = getParser().getTok(); | |||
4059 | StartLoc = Tok.getLoc(); | |||
4060 | EndLoc = Tok.getEndLoc(); | |||
4061 | RegNo = tryParseRegister(); | |||
4062 | ||||
4063 | return (RegNo == (unsigned)-1); | |||
4064 | } | |||
4065 | ||||
4066 | OperandMatchResultTy ARMAsmParser::tryParseRegister(unsigned &RegNo, | |||
4067 | SMLoc &StartLoc, | |||
4068 | SMLoc &EndLoc) { | |||
4069 | if (ParseRegister(RegNo, StartLoc, EndLoc)) | |||
4070 | return MatchOperand_NoMatch; | |||
4071 | return MatchOperand_Success; | |||
4072 | } | |||
4073 | ||||
4074 | /// Try to parse a register name. The token must be an Identifier when called, | |||
4075 | /// and if it is a register name the token is eaten and the register number is | |||
4076 | /// returned. Otherwise return -1. | |||
4077 | int ARMAsmParser::tryParseRegister() { | |||
4078 | MCAsmParser &Parser = getParser(); | |||
4079 | const AsmToken &Tok = Parser.getTok(); | |||
4080 | if (Tok.isNot(AsmToken::Identifier)) return -1; | |||
4081 | ||||
4082 | std::string lowerCase = Tok.getString().lower(); | |||
4083 | unsigned RegNum = MatchRegisterName(lowerCase); | |||
4084 | if (!RegNum) { | |||
4085 | RegNum = StringSwitch<unsigned>(lowerCase) | |||
4086 | .Case("r13", ARM::SP) | |||
4087 | .Case("r14", ARM::LR) | |||
4088 | .Case("r15", ARM::PC) | |||
4089 | .Case("ip", ARM::R12) | |||
4090 | // Additional register name aliases for 'gas' compatibility. | |||
4091 | .Case("a1", ARM::R0) | |||
4092 | .Case("a2", ARM::R1) | |||
4093 | .Case("a3", ARM::R2) | |||
4094 | .Case("a4", ARM::R3) | |||
4095 | .Case("v1", ARM::R4) | |||
4096 | .Case("v2", ARM::R5) | |||
4097 | .Case("v3", ARM::R6) | |||
4098 | .Case("v4", ARM::R7) | |||
4099 | .Case("v5", ARM::R8) | |||
4100 | .Case("v6", ARM::R9) | |||
4101 | .Case("v7", ARM::R10) | |||
4102 | .Case("v8", ARM::R11) | |||
4103 | .Case("sb", ARM::R9) | |||
4104 | .Case("sl", ARM::R10) | |||
4105 | .Case("fp", ARM::R11) | |||
4106 | .Default(0); | |||
4107 | } | |||
4108 | if (!RegNum) { | |||
4109 | // Check for aliases registered via .req. Canonicalize to lower case. | |||
4110 | // That's more consistent since register names are case insensitive, and | |||
4111 | // it's how the original entry was passed in from MC/MCParser/AsmParser. | |||
4112 | StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); | |||
4113 | // If no match, return failure. | |||
4114 | if (Entry == RegisterReqs.end()) | |||
4115 | return -1; | |||
4116 | Parser.Lex(); // Eat identifier token. | |||
4117 | return Entry->getValue(); | |||
4118 | } | |||
4119 | ||||
4120 | // Some FPUs only have 16 D registers, so D16-D31 are invalid | |||
4121 | if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) | |||
4122 | return -1; | |||
4123 | ||||
4124 | Parser.Lex(); // Eat identifier token. | |||
4125 | ||||
4126 | return RegNum; | |||
4127 | } | |||
4128 | ||||
4129 | // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. | |||
4130 | // If a recoverable error occurs, return 1. If an irrecoverable error | |||
4131 | // occurs, return -1. An irrecoverable error is one where tokens have been | |||
4132 | // consumed in the process of trying to parse the shifter (i.e., when it is | |||
4133 | // indeed a shifter operand, but malformed). | |||
4134 | int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { | |||
4135 | MCAsmParser &Parser = getParser(); | |||
4136 | SMLoc S = Parser.getTok().getLoc(); | |||
4137 | const AsmToken &Tok = Parser.getTok(); | |||
4138 | if (Tok.isNot(AsmToken::Identifier)) | |||
4139 | return -1; | |||
4140 | ||||
4141 | std::string lowerCase = Tok.getString().lower(); | |||
4142 | ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) | |||
4143 | .Case("asl", ARM_AM::lsl) | |||
4144 | .Case("lsl", ARM_AM::lsl) | |||
4145 | .Case("lsr", ARM_AM::lsr) | |||
4146 | .Case("asr", ARM_AM::asr) | |||
4147 | .Case("ror", ARM_AM::ror) | |||
4148 | .Case("rrx", ARM_AM::rrx) | |||
4149 | .Default(ARM_AM::no_shift); | |||
4150 | ||||
4151 | if (ShiftTy == ARM_AM::no_shift) | |||
4152 | return 1; | |||
4153 | ||||
4154 | Parser.Lex(); // Eat the operator. | |||
4155 | ||||
4156 | // The source register for the shift has already been added to the | |||
4157 | // operand list, so we need to pop it off and combine it into the shifted | |||
4158 | // register operand instead. | |||
4159 | std::unique_ptr<ARMOperand> PrevOp( | |||
4160 | (ARMOperand *)Operands.pop_back_val().release()); | |||
4161 | if (!PrevOp->isReg()) | |||
4162 | return Error(PrevOp->getStartLoc(), "shift must be of a register"); | |||
4163 | int SrcReg = PrevOp->getReg(); | |||
4164 | ||||
4165 | SMLoc EndLoc; | |||
4166 | int64_t Imm = 0; | |||
4167 | int ShiftReg = 0; | |||
4168 | if (ShiftTy == ARM_AM::rrx) { | |||
4169 | // RRX Doesn't have an explicit shift amount. The encoder expects | |||
4170 | // the shift register to be the same as the source register. Seems odd, | |||
4171 | // but OK. | |||
4172 | ShiftReg = SrcReg; | |||
4173 | } else { | |||
4174 | // Figure out if this is shifted by a constant or a register (for non-RRX). | |||
4175 | if (Parser.getTok().is(AsmToken::Hash) || | |||
4176 | Parser.getTok().is(AsmToken::Dollar)) { | |||
4177 | Parser.Lex(); // Eat hash. | |||
4178 | SMLoc ImmLoc = Parser.getTok().getLoc(); | |||
4179 | const MCExpr *ShiftExpr = nullptr; | |||
4180 | if (getParser().parseExpression(ShiftExpr, EndLoc)) { | |||
4181 | Error(ImmLoc, "invalid immediate shift value"); | |||
4182 | return -1; | |||
4183 | } | |||
4184 | // The expression must be evaluatable as an immediate. | |||
4185 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); | |||
4186 | if (!CE) { | |||
4187 | Error(ImmLoc, "invalid immediate shift value"); | |||
4188 | return -1; | |||
4189 | } | |||
4190 | // Range check the immediate. | |||
4191 | // lsl, ror: 0 <= imm <= 31 | |||
4192 | // lsr, asr: 0 <= imm <= 32 | |||
4193 | Imm = CE->getValue(); | |||
4194 | if (Imm < 0 || | |||
4195 | ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || | |||
4196 | ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { | |||
4197 | Error(ImmLoc, "immediate shift value out of range"); | |||
4198 | return -1; | |||
4199 | } | |||
4200 | // shift by zero is a nop. Always send it through as lsl. | |||
4201 | // ('as' compatibility) | |||
4202 | if (Imm == 0) | |||
4203 | ShiftTy = ARM_AM::lsl; | |||
4204 | } else if (Parser.getTok().is(AsmToken::Identifier)) { | |||
4205 | SMLoc L = Parser.getTok().getLoc(); | |||
4206 | EndLoc = Parser.getTok().getEndLoc(); | |||
4207 | ShiftReg = tryParseRegister(); | |||
4208 | if (ShiftReg == -1) { | |||
4209 | Error(L, "expected immediate or register in shift operand"); | |||
4210 | return -1; | |||
4211 | } | |||
4212 | } else { | |||
4213 | Error(Parser.getTok().getLoc(), | |||
4214 | "expected immediate or register in shift operand"); | |||
4215 | return -1; | |||
4216 | } | |||
4217 | } | |||
4218 | ||||
4219 | if (ShiftReg && ShiftTy != ARM_AM::rrx) | |||
4220 | Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, | |||
4221 | ShiftReg, Imm, | |||
4222 | S, EndLoc)); | |||
4223 | else | |||
4224 | Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, | |||
4225 | S, EndLoc)); | |||
4226 | ||||
4227 | return 0; | |||
4228 | } | |||
4229 | ||||
4230 | /// Try to parse a register name. The token must be an Identifier when called. | |||
4231 | /// If it's a register, an AsmOperand is created. Another AsmOperand is created | |||
4232 | /// if there is a "writeback". 'true' if it's not a register. | |||
4233 | /// | |||
4234 | /// TODO this is likely to change to allow different register types and or to | |||
4235 | /// parse for a specific register type. | |||
4236 | bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { | |||
4237 | MCAsmParser &Parser = getParser(); | |||
4238 | SMLoc RegStartLoc = Parser.getTok().getLoc(); | |||
4239 | SMLoc RegEndLoc = Parser.getTok().getEndLoc(); | |||
4240 | int RegNo = tryParseRegister(); | |||
4241 | if (RegNo == -1) | |||
4242 | return true; | |||
4243 | ||||
4244 | Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); | |||
4245 | ||||
4246 | const AsmToken &ExclaimTok = Parser.getTok(); | |||
4247 | if (ExclaimTok.is(AsmToken::Exclaim)) { | |||
4248 | Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), | |||
4249 | ExclaimTok.getLoc())); | |||
4250 | Parser.Lex(); // Eat exclaim token | |||
4251 | return false; | |||
4252 | } | |||
4253 | ||||
4254 | // Also check for an index operand. This is only legal for vector registers, | |||
4255 | // but that'll get caught OK in operand matching, so we don't need to | |||
4256 | // explicitly filter everything else out here. | |||
4257 | if (Parser.getTok().is(AsmToken::LBrac)) { | |||
4258 | SMLoc SIdx = Parser.getTok().getLoc(); | |||
4259 | Parser.Lex(); // Eat left bracket token. | |||
4260 | ||||
4261 | const MCExpr *ImmVal; | |||
4262 | if (getParser().parseExpression(ImmVal)) | |||
4263 | return true; | |||
4264 | const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); | |||
4265 | if (!MCE) | |||
4266 | return TokError("immediate value expected for vector index"); | |||
4267 | ||||
4268 | if (Parser.getTok().isNot(AsmToken::RBrac)) | |||
4269 | return Error(Parser.getTok().getLoc(), "']' expected"); | |||
4270 | ||||
4271 | SMLoc E = Parser.getTok().getEndLoc(); | |||
4272 | Parser.Lex(); // Eat right bracket token. | |||
4273 | ||||
4274 | Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), | |||
4275 | SIdx, E, | |||
4276 | getContext())); | |||
4277 | } | |||
4278 | ||||
4279 | return false; | |||
4280 | } | |||
4281 | ||||
4282 | /// MatchCoprocessorOperandName - Try to parse an coprocessor related | |||
4283 | /// instruction with a symbolic operand name. | |||
4284 | /// We accept "crN" syntax for GAS compatibility. | |||
4285 | /// <operand-name> ::= <prefix><number> | |||
4286 | /// If CoprocOp is 'c', then: | |||
4287 | /// <prefix> ::= c | cr | |||
4288 | /// If CoprocOp is 'p', then : | |||
4289 | /// <prefix> ::= p | |||
4290 | /// <number> ::= integer in range [0, 15] | |||
4291 | static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { | |||
4292 | // Use the same layout as the tablegen'erated register name matcher. Ugly, | |||
4293 | // but efficient. | |||
4294 | if (Name.size() < 2 || Name[0] != CoprocOp) | |||
4295 | return -1; | |||
4296 | Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); | |||
4297 | ||||
4298 | switch (Name.size()) { | |||
4299 | default: return -1; | |||
4300 | case 1: | |||
4301 | switch (Name[0]) { | |||
4302 | default: return -1; | |||
4303 | case '0': return 0; | |||
4304 | case '1': return 1; | |||
4305 | case '2': return 2; | |||
4306 | case '3': return 3; | |||
4307 | case '4': return 4; | |||
4308 | case '5': return 5; | |||
4309 | case '6': return 6; | |||
4310 | case '7': return 7; | |||
4311 | case '8': return 8; | |||
4312 | case '9': return 9; | |||
4313 | } | |||
4314 | case 2: | |||
4315 | if (Name[0] != '1') | |||
4316 | return -1; | |||
4317 | switch (Name[1]) { | |||
4318 | default: return -1; | |||
4319 | // CP10 and CP11 are VFP/NEON and so vector instructions should be used. | |||
4320 | // However, old cores (v5/v6) did use them in that way. | |||
4321 | case '0': return 10; | |||
4322 | case '1': return 11; | |||
4323 | case '2': return 12; | |||
4324 | case '3': return 13; | |||
4325 | case '4': return 14; | |||
4326 | case '5': return 15; | |||
4327 | } | |||
4328 | } | |||
4329 | } | |||
4330 | ||||
4331 | /// parseITCondCode - Try to parse a condition code for an IT instruction. | |||
4332 | OperandMatchResultTy | |||
4333 | ARMAsmParser::parseITCondCode(OperandVector &Operands) { | |||
4334 | MCAsmParser &Parser = getParser(); | |||
4335 | SMLoc S = Parser.getTok().getLoc(); | |||
4336 | const AsmToken &Tok = Parser.getTok(); | |||
4337 | if (!Tok.is(AsmToken::Identifier)) | |||
4338 | return MatchOperand_NoMatch; | |||
4339 | unsigned CC = ARMCondCodeFromString(Tok.getString()); | |||
4340 | if (CC == ~0U) | |||
4341 | return MatchOperand_NoMatch; | |||
4342 | Parser.Lex(); // Eat the token. | |||
4343 | ||||
4344 | Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); | |||
4345 | ||||
4346 | return MatchOperand_Success; | |||
4347 | } | |||
4348 | ||||
4349 | /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The | |||
4350 | /// token must be an Identifier when called, and if it is a coprocessor | |||
4351 | /// number, the token is eaten and the operand is added to the operand list. | |||
4352 | OperandMatchResultTy | |||
4353 | ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { | |||
4354 | MCAsmParser &Parser = getParser(); | |||
4355 | SMLoc S = Parser.getTok().getLoc(); | |||
4356 | const AsmToken &Tok = Parser.getTok(); | |||
4357 | if (Tok.isNot(AsmToken::Identifier)) | |||
4358 | return MatchOperand_NoMatch; | |||
4359 | ||||
4360 | int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p'); | |||
4361 | if (Num == -1) | |||
4362 | return MatchOperand_NoMatch; | |||
4363 | if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits())) | |||
4364 | return MatchOperand_NoMatch; | |||
4365 | ||||
4366 | Parser.Lex(); // Eat identifier token. | |||
4367 | Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); | |||
4368 | return MatchOperand_Success; | |||
4369 | } | |||
4370 | ||||
4371 | /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The | |||
4372 | /// token must be an Identifier when called, and if it is a coprocessor | |||
4373 | /// number, the token is eaten and the operand is added to the operand list. | |||
4374 | OperandMatchResultTy | |||
4375 | ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { | |||
4376 | MCAsmParser &Parser = getParser(); | |||
4377 | SMLoc S = Parser.getTok().getLoc(); | |||
4378 | const AsmToken &Tok = Parser.getTok(); | |||
4379 | if (Tok.isNot(AsmToken::Identifier)) | |||
4380 | return MatchOperand_NoMatch; | |||
4381 | ||||
4382 | int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c'); | |||
4383 | if (Reg == -1) | |||
4384 | return MatchOperand_NoMatch; | |||
4385 | ||||
4386 | Parser.Lex(); // Eat identifier token. | |||
4387 | Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); | |||
4388 | return MatchOperand_Success; | |||
4389 | } | |||
4390 | ||||
4391 | /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. | |||
4392 | /// coproc_option : '{' imm0_255 '}' | |||
4393 | OperandMatchResultTy | |||
4394 | ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { | |||
4395 | MCAsmParser &Parser = getParser(); | |||
4396 | SMLoc S = Parser.getTok().getLoc(); | |||
4397 | ||||
4398 | // If this isn't a '{', this isn't a coprocessor immediate operand. | |||
4399 | if (Parser.getTok().isNot(AsmToken::LCurly)) | |||
4400 | return MatchOperand_NoMatch; | |||
4401 | Parser.Lex(); // Eat the '{' | |||
4402 | ||||
4403 | const MCExpr *Expr; | |||
4404 | SMLoc Loc = Parser.getTok().getLoc(); | |||
4405 | if (getParser().parseExpression(Expr)) { | |||
4406 | Error(Loc, "illegal expression"); | |||
4407 | return MatchOperand_ParseFail; | |||
4408 | } | |||
4409 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); | |||
4410 | if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { | |||
4411 | Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); | |||
4412 | return MatchOperand_ParseFail; | |||
4413 | } | |||
4414 | int Val = CE->getValue(); | |||
4415 | ||||
4416 | // Check for and consume the closing '}' | |||
4417 | if (Parser.getTok().isNot(AsmToken::RCurly)) | |||
4418 | return MatchOperand_ParseFail; | |||
4419 | SMLoc E = Parser.getTok().getEndLoc(); | |||
4420 | Parser.Lex(); // Eat the '}' | |||
4421 | ||||
4422 | Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); | |||
4423 | return MatchOperand_Success; | |||
4424 | } | |||
4425 | ||||
4426 | // For register list parsing, we need to map from raw GPR register numbering | |||
4427 | // to the enumeration values. The enumeration values aren't sorted by | |||
4428 | // register number due to our using "sp", "lr" and "pc" as canonical names. | |||
4429 | static unsigned getNextRegister(unsigned Reg) { | |||
4430 | // If this is a GPR, we need to do it manually, otherwise we can rely | |||
4431 | // on the sort ordering of the enumeration since the other reg-classes | |||
4432 | // are sane. | |||
4433 | if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) | |||
4434 | return Reg + 1; | |||
4435 | switch(Reg) { | |||
4436 | default: llvm_unreachable("Invalid GPR number!")__builtin_unreachable(); | |||
4437 | case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; | |||
4438 | case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; | |||
4439 | case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; | |||
4440 | case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; | |||
4441 | case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; | |||
4442 | case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; | |||
4443 | case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; | |||
4444 | case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; | |||
4445 | } | |||
4446 | } | |||
4447 | ||||
4448 | // Insert an <Encoding, Register> pair in an ordered vector. Return true on | |||
4449 | // success, or false, if duplicate encoding found. | |||
4450 | static bool | |||
4451 | insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, | |||
4452 | unsigned Enc, unsigned Reg) { | |||
4453 | Regs.emplace_back(Enc, Reg); | |||
4454 | for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) { | |||
4455 | if (J->first == Enc) { | |||
4456 | Regs.erase(J.base()); | |||
4457 | return false; | |||
4458 | } | |||
4459 | if (J->first < Enc) | |||
4460 | break; | |||
4461 | std::swap(*I, *J); | |||
4462 | } | |||
4463 | return true; | |||
4464 | } | |||
4465 | ||||
4466 | /// Parse a register list. | |||
4467 | bool ARMAsmParser::parseRegisterList(OperandVector &Operands, | |||
4468 | bool EnforceOrder) { | |||
4469 | MCAsmParser &Parser = getParser(); | |||
4470 | if (Parser.getTok().isNot(AsmToken::LCurly)) | |||
4471 | return TokError("Token is not a Left Curly Brace"); | |||
4472 | SMLoc S = Parser.getTok().getLoc(); | |||
4473 | Parser.Lex(); // Eat '{' token. | |||
4474 | SMLoc RegLoc = Parser.getTok().getLoc(); | |||
4475 | ||||
4476 | // Check the first register in the list to see what register class | |||
4477 | // this is a list of. | |||
4478 | int Reg = tryParseRegister(); | |||
4479 | if (Reg == -1) | |||
4480 | return Error(RegLoc, "register expected"); | |||
4481 | ||||
4482 | // The reglist instructions have at most 16 registers, so reserve | |||
4483 | // space for that many. | |||
4484 | int EReg = 0; | |||
4485 | SmallVector<std::pair<unsigned, unsigned>, 16> Registers; | |||
4486 | ||||
4487 | // Allow Q regs and just interpret them as the two D sub-registers. | |||
4488 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { | |||
4489 | Reg = getDRegFromQReg(Reg); | |||
4490 | EReg = MRI->getEncodingValue(Reg); | |||
4491 | Registers.emplace_back(EReg, Reg); | |||
4492 | ++Reg; | |||
4493 | } | |||
4494 | const MCRegisterClass *RC; | |||
4495 | if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) | |||
4496 | RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; | |||
4497 | else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) | |||
4498 | RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; | |||
4499 | else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) | |||
4500 | RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; | |||
4501 | else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) | |||
4502 | RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; | |||
4503 | else | |||
4504 | return Error(RegLoc, "invalid register in register list"); | |||
4505 | ||||
4506 | // Store the register. | |||
4507 | EReg = MRI->getEncodingValue(Reg); | |||
4508 | Registers.emplace_back(EReg, Reg); | |||
4509 | ||||
4510 | // This starts immediately after the first register token in the list, | |||
4511 | // so we can see either a comma or a minus (range separator) as a legal | |||
4512 | // next token. | |||
4513 | while (Parser.getTok().is(AsmToken::Comma) || | |||
4514 | Parser.getTok().is(AsmToken::Minus)) { | |||
4515 | if (Parser.getTok().is(AsmToken::Minus)) { | |||
4516 | Parser.Lex(); // Eat the minus. | |||
4517 | SMLoc AfterMinusLoc = Parser.getTok().getLoc(); | |||
4518 | int EndReg = tryParseRegister(); | |||
4519 | if (EndReg == -1) | |||
4520 | return Error(AfterMinusLoc, "register expected"); | |||
4521 | // Allow Q regs and just interpret them as the two D sub-registers. | |||
4522 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) | |||
4523 | EndReg = getDRegFromQReg(EndReg) + 1; | |||
4524 | // If the register is the same as the start reg, there's nothing | |||
4525 | // more to do. | |||
4526 | if (Reg == EndReg) | |||
4527 | continue; | |||
4528 | // The register must be in the same register class as the first. | |||
4529 | if (!RC->contains(EndReg)) | |||
4530 | return Error(AfterMinusLoc, "invalid register in register list"); | |||
4531 | // Ranges must go from low to high. | |||
4532 | if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) | |||
4533 | return Error(AfterMinusLoc, "bad range in register list"); | |||
4534 | ||||
4535 | // Add all the registers in the range to the register list. | |||
4536 | while (Reg != EndReg) { | |||
4537 | Reg = getNextRegister(Reg); | |||
4538 | EReg = MRI->getEncodingValue(Reg); | |||
4539 | if (!insertNoDuplicates(Registers, EReg, Reg)) { | |||
4540 | Warning(AfterMinusLoc, StringRef("duplicated register (") + | |||
4541 | ARMInstPrinter::getRegisterName(Reg) + | |||
4542 | ") in register list"); | |||
4543 | } | |||
4544 | } | |||
4545 | continue; | |||
4546 | } | |||
4547 | Parser.Lex(); // Eat the comma. | |||
4548 | RegLoc = Parser.getTok().getLoc(); | |||
4549 | int OldReg = Reg; | |||
4550 | const AsmToken RegTok = Parser.getTok(); | |||
4551 | Reg = tryParseRegister(); | |||
4552 | if (Reg == -1) | |||
4553 | return Error(RegLoc, "register expected"); | |||
4554 | // Allow Q regs and just interpret them as the two D sub-registers. | |||
4555 | bool isQReg = false; | |||
4556 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { | |||
4557 | Reg = getDRegFromQReg(Reg); | |||
4558 | isQReg = true; | |||
4559 | } | |||
4560 | if (!RC->contains(Reg) && | |||
4561 | RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && | |||
4562 | ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { | |||
4563 | // switch the register classes, as GPRwithAPSRnospRegClassID is a partial | |||
4564 | // subset of GPRRegClassId except it contains APSR as well. | |||
4565 | RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; | |||
4566 | } | |||
4567 | if (Reg == ARM::VPR && | |||
4568 | (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || | |||
4569 | RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || | |||
4570 | RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { | |||
4571 | RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; | |||
4572 | EReg = MRI->getEncodingValue(Reg); | |||
4573 | if (!insertNoDuplicates(Registers, EReg, Reg)) { | |||
4574 | Warning(RegLoc, "duplicated register (" + RegTok.getString() + | |||
4575 | ") in register list"); | |||
4576 | } | |||
4577 | continue; | |||
4578 | } | |||
4579 | // The register must be in the same register class as the first. | |||
4580 | if (!RC->contains(Reg)) | |||
4581 | return Error(RegLoc, "invalid register in register list"); | |||
4582 | // In most cases, the list must be monotonically increasing. An | |||
4583 | // exception is CLRM, which is order-independent anyway, so | |||
4584 | // there's no potential for confusion if you write clrm {r2,r1} | |||
4585 | // instead of clrm {r1,r2}. | |||
4586 | if (EnforceOrder && | |||
4587 | MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { | |||
4588 | if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) | |||
4589 | Warning(RegLoc, "register list not in ascending order"); | |||
4590 | else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) | |||
4591 | return Error(RegLoc, "register list not in ascending order"); | |||
4592 | } | |||
4593 | // VFP register lists must also be contiguous. | |||
4594 | if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && | |||
4595 | RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && | |||
4596 | Reg != OldReg + 1) | |||
4597 | return Error(RegLoc, "non-contiguous register range"); | |||
4598 | EReg = MRI->getEncodingValue(Reg); | |||
4599 | if (!insertNoDuplicates(Registers, EReg, Reg)) { | |||
4600 | Warning(RegLoc, "duplicated register (" + RegTok.getString() + | |||
4601 | ") in register list"); | |||
4602 | } | |||
4603 | if (isQReg) { | |||
4604 | EReg = MRI->getEncodingValue(++Reg); | |||
4605 | Registers.emplace_back(EReg, Reg); | |||
4606 | } | |||
4607 | } | |||
4608 | ||||
4609 | if (Parser.getTok().isNot(AsmToken::RCurly)) | |||
4610 | return Error(Parser.getTok().getLoc(), "'}' expected"); | |||
4611 | SMLoc E = Parser.getTok().getEndLoc(); | |||
4612 | Parser.Lex(); // Eat '}' token. | |||
4613 | ||||
4614 | // Push the register list operand. | |||
4615 | Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); | |||
4616 | ||||
4617 | // The ARM system instruction variants for LDM/STM have a '^' token here. | |||
4618 | if (Parser.getTok().is(AsmToken::Caret)) { | |||
4619 | Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); | |||
4620 | Parser.Lex(); // Eat '^' token. | |||
4621 | } | |||
4622 | ||||
4623 | return false; | |||
4624 | } | |||
4625 | ||||
4626 | // Helper function to parse the lane index for vector lists. | |||
4627 | OperandMatchResultTy ARMAsmParser:: | |||
4628 | parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { | |||
4629 | MCAsmParser &Parser = getParser(); | |||
4630 | Index = 0; // Always return a defined index value. | |||
4631 | if (Parser.getTok().is(AsmToken::LBrac)) { | |||
4632 | Parser.Lex(); // Eat the '['. | |||
4633 | if (Parser.getTok().is(AsmToken::RBrac)) { | |||
4634 | // "Dn[]" is the 'all lanes' syntax. | |||
4635 | LaneKind = AllLanes; | |||
4636 | EndLoc = Parser.getTok().getEndLoc(); | |||
4637 | Parser.Lex(); // Eat the ']'. | |||
4638 | return MatchOperand_Success; | |||
4639 | } | |||
4640 | ||||
4641 | // There's an optional '#' token here. Normally there wouldn't be, but | |||
4642 | // inline assemble puts one in, and it's friendly to accept that. | |||
4643 | if (Parser.getTok().is(AsmToken::Hash)) | |||
4644 | Parser.Lex(); // Eat '#' or '$'. | |||
4645 | ||||
4646 | const MCExpr *LaneIndex; | |||
4647 | SMLoc Loc = Parser.getTok().getLoc(); | |||
4648 | if (getParser().parseExpression(LaneIndex)) { | |||
4649 | Error(Loc, "illegal expression"); | |||
4650 | return MatchOperand_ParseFail; | |||
4651 | } | |||
4652 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); | |||
4653 | if (!CE) { | |||
4654 | Error(Loc, "lane index must be empty or an integer"); | |||
4655 | return MatchOperand_ParseFail; | |||
4656 | } | |||
4657 | if (Parser.getTok().isNot(AsmToken::RBrac)) { | |||
4658 | Error(Parser.getTok().getLoc(), "']' expected"); | |||
4659 | return MatchOperand_ParseFail; | |||
4660 | } | |||
4661 | EndLoc = Parser.getTok().getEndLoc(); | |||
4662 | Parser.Lex(); // Eat the ']'. | |||
4663 | int64_t Val = CE->getValue(); | |||
4664 | ||||
4665 | // FIXME: Make this range check context sensitive for .8, .16, .32. | |||
4666 | if (Val < 0 || Val > 7) { | |||
4667 | Error(Parser.getTok().getLoc(), "lane index out of range"); | |||
4668 | return MatchOperand_ParseFail; | |||
4669 | } | |||
4670 | Index = Val; | |||
4671 | LaneKind = IndexedLane; | |||
4672 | return MatchOperand_Success; | |||
4673 | } | |||
4674 | LaneKind = NoLanes; | |||
4675 | return MatchOperand_Success; | |||
4676 | } | |||
4677 | ||||
4678 | // parse a vector register list | |||
4679 | OperandMatchResultTy | |||
4680 | ARMAsmParser::parseVectorList(OperandVector &Operands) { | |||
4681 | MCAsmParser &Parser = getParser(); | |||
4682 | VectorLaneTy LaneKind; | |||
4683 | unsigned LaneIndex; | |||
4684 | SMLoc S = Parser.getTok().getLoc(); | |||
4685 | // As an extension (to match gas), support a plain D register or Q register | |||
4686 | // (without encosing curly braces) as a single or double entry list, | |||
4687 | // respectively. | |||
4688 | if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) { | |||
4689 | SMLoc E = Parser.getTok().getEndLoc(); | |||
4690 | int Reg = tryParseRegister(); | |||
4691 | if (Reg == -1) | |||
4692 | return MatchOperand_NoMatch; | |||
4693 | if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { | |||
4694 | OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); | |||
4695 | if (Res != MatchOperand_Success) | |||
4696 | return Res; | |||
4697 | switch (LaneKind) { | |||
4698 | case NoLanes: | |||
4699 | Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); | |||
4700 | break; | |||
4701 | case AllLanes: | |||
4702 | Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, | |||
4703 | S, E)); | |||
4704 | break; | |||
4705 | case IndexedLane: | |||
4706 | Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, | |||
4707 | LaneIndex, | |||
4708 | false, S, E)); | |||
4709 | break; | |||
4710 | } | |||
4711 | return MatchOperand_Success; | |||
4712 | } | |||
4713 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { | |||
4714 | Reg = getDRegFromQReg(Reg); | |||
4715 | OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); | |||
4716 | if (Res != MatchOperand_Success) | |||
4717 | return Res; | |||
4718 | switch (LaneKind) { | |||
4719 | case NoLanes: | |||
4720 | Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, | |||
4721 | &ARMMCRegisterClasses[ARM::DPairRegClassID]); | |||
4722 | Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); | |||
4723 | break; | |||
4724 | case AllLanes: | |||
4725 | Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, | |||
4726 | &ARMMCRegisterClasses[ARM::DPairRegClassID]); | |||
4727 | Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, | |||
4728 | S, E)); | |||
4729 | break; | |||
4730 | case IndexedLane: | |||
4731 | Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, | |||
4732 | LaneIndex, | |||
4733 | false, S, E)); | |||
4734 | break; | |||
4735 | } | |||
4736 | return MatchOperand_Success; | |||
4737 | } | |||
4738 | Error(S, "vector register expected"); | |||
4739 | return MatchOperand_ParseFail; | |||
4740 | } | |||
4741 | ||||
4742 | if (Parser.getTok().isNot(AsmToken::LCurly)) | |||
4743 | return MatchOperand_NoMatch; | |||
4744 | ||||
4745 | Parser.Lex(); // Eat '{' token. | |||
4746 | SMLoc RegLoc = Parser.getTok().getLoc(); | |||
4747 | ||||
4748 | int Reg = tryParseRegister(); | |||
4749 | if (Reg == -1) { | |||
4750 | Error(RegLoc, "register expected"); | |||
4751 | return MatchOperand_ParseFail; | |||
4752 | } | |||
4753 | unsigned Count = 1; | |||
4754 | int Spacing = 0; | |||
4755 | unsigned FirstReg = Reg; | |||
4756 | ||||
4757 | if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { | |||
4758 | Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected"); | |||
4759 | return MatchOperand_ParseFail; | |||
4760 | } | |||
4761 | // The list is of D registers, but we also allow Q regs and just interpret | |||
4762 | // them as the two D sub-registers. | |||
4763 | else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { | |||
4764 | FirstReg = Reg = getDRegFromQReg(Reg); | |||
4765 | Spacing = 1; // double-spacing requires explicit D registers, otherwise | |||
4766 | // it's ambiguous with four-register single spaced. | |||
4767 | ++Reg; | |||
4768 | ++Count; | |||
4769 | } | |||
4770 | ||||
4771 | SMLoc E; | |||
4772 | if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) | |||
4773 | return MatchOperand_ParseFail; | |||
4774 | ||||
4775 | while (Parser.getTok().is(AsmToken::Comma) || | |||
4776 | Parser.getTok().is(AsmToken::Minus)) { | |||
4777 | if (Parser.getTok().is(AsmToken::Minus)) { | |||
4778 | if (!Spacing) | |||
4779 | Spacing = 1; // Register range implies a single spaced list. | |||
4780 | else if (Spacing == 2) { | |||
4781 | Error(Parser.getTok().getLoc(), | |||
4782 | "sequential registers in double spaced list"); | |||
4783 | return MatchOperand_ParseFail; | |||
4784 | } | |||
4785 | Parser.Lex(); // Eat the minus. | |||
4786 | SMLoc AfterMinusLoc = Parser.getTok().getLoc(); | |||
4787 | int EndReg = tryParseRegister(); | |||
4788 | if (EndReg == -1) { | |||
4789 | Error(AfterMinusLoc, "register expected"); | |||
4790 | return MatchOperand_ParseFail; | |||
4791 | } | |||
4792 | // Allow Q regs and just interpret them as the two D sub-registers. | |||
4793 | if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) | |||
4794 | EndReg = getDRegFromQReg(EndReg) + 1; | |||
4795 | // If the register is the same as the start reg, there's nothing | |||
4796 | // more to do. | |||
4797 | if (Reg == EndReg) | |||
4798 | continue; | |||
4799 | // The register must be in the same register class as the first. | |||
4800 | if ((hasMVE() && | |||
4801 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || | |||
4802 | (!hasMVE() && | |||
4803 | !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { | |||
4804 | Error(AfterMinusLoc, "invalid register in register list"); | |||
4805 | return MatchOperand_ParseFail; | |||
4806 | } | |||
4807 | // Ranges must go from low to high. | |||
4808 | if (Reg > EndReg) { | |||
4809 | Error(AfterMinusLoc, "bad range in register list"); | |||
4810 | return MatchOperand_ParseFail; | |||
4811 | } | |||
4812 | // Parse the lane specifier if present. | |||
4813 | VectorLaneTy NextLaneKind; | |||
4814 | unsigned NextLaneIndex; | |||
4815 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != | |||
4816 | MatchOperand_Success) | |||
4817 | return MatchOperand_ParseFail; | |||
4818 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { | |||
4819 | Error(AfterMinusLoc, "mismatched lane index in register list"); | |||
4820 | return MatchOperand_ParseFail; | |||
4821 | } | |||
4822 | ||||
4823 | // Add all the registers in the range to the register list. | |||
4824 | Count += EndReg - Reg; | |||
4825 | Reg = EndReg; | |||
4826 | continue; | |||
4827 | } | |||
4828 | Parser.Lex(); // Eat the comma. | |||
4829 | RegLoc = Parser.getTok().getLoc(); | |||
4830 | int OldReg = Reg; | |||
4831 | Reg = tryParseRegister(); | |||
4832 | if (Reg == -1) { | |||
4833 | Error(RegLoc, "register expected"); | |||
4834 | return MatchOperand_ParseFail; | |||
4835 | } | |||
4836 | ||||
4837 | if (hasMVE()) { | |||
4838 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { | |||
4839 | Error(RegLoc, "vector register in range Q0-Q7 expected"); | |||
4840 | return MatchOperand_ParseFail; | |||
4841 | } | |||
4842 | Spacing = 1; | |||
4843 | } | |||
4844 | // vector register lists must be contiguous. | |||
4845 | // It's OK to use the enumeration values directly here rather, as the | |||
4846 | // VFP register classes have the enum sorted properly. | |||
4847 | // | |||
4848 | // The list is of D registers, but we also allow Q regs and just interpret | |||
4849 | // them as the two D sub-registers. | |||
4850 | else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { | |||
4851 | if (!Spacing) | |||
4852 | Spacing = 1; // Register range implies a single spaced list. | |||
4853 | else if (Spacing == 2) { | |||
4854 | Error(RegLoc, | |||
4855 | "invalid register in double-spaced list (must be 'D' register')"); | |||
4856 | return MatchOperand_ParseFail; | |||
4857 | } | |||
4858 | Reg = getDRegFromQReg(Reg); | |||
4859 | if (Reg != OldReg + 1) { | |||
4860 | Error(RegLoc, "non-contiguous register range"); | |||
4861 | return MatchOperand_ParseFail; | |||
4862 | } | |||
4863 | ++Reg; | |||
4864 | Count += 2; | |||
4865 | // Parse the lane specifier if present. | |||
4866 | VectorLaneTy NextLaneKind; | |||
4867 | unsigned NextLaneIndex; | |||
4868 | SMLoc LaneLoc = Parser.getTok().getLoc(); | |||
4869 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != | |||
4870 | MatchOperand_Success) | |||
4871 | return MatchOperand_ParseFail; | |||
4872 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { | |||
4873 | Error(LaneLoc, "mismatched lane index in register list"); | |||
4874 | return MatchOperand_ParseFail; | |||
4875 | } | |||
4876 | continue; | |||
4877 | } | |||
4878 | // Normal D register. | |||
4879 | // Figure out the register spacing (single or double) of the list if | |||
4880 | // we don't know it already. | |||
4881 | if (!Spacing) | |||
4882 | Spacing = 1 + (Reg == OldReg + 2); | |||
4883 | ||||
4884 | // Just check that it's contiguous and keep going. | |||
4885 | if (Reg != OldReg + Spacing) { | |||
4886 | Error(RegLoc, "non-contiguous register range"); | |||
4887 | return MatchOperand_ParseFail; | |||
4888 | } | |||
4889 | ++Count; | |||
4890 | // Parse the lane specifier if present. | |||
4891 | VectorLaneTy NextLaneKind; | |||
4892 | unsigned NextLaneIndex; | |||
4893 | SMLoc EndLoc = Parser.getTok().getLoc(); | |||
4894 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) | |||
4895 | return MatchOperand_ParseFail; | |||
4896 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { | |||
4897 | Error(EndLoc, "mismatched lane index in register list"); | |||
4898 | return MatchOperand_ParseFail; | |||
4899 | } | |||
4900 | } | |||
4901 | ||||
4902 | if (Parser.getTok().isNot(AsmToken::RCurly)) { | |||
4903 | Error(Parser.getTok().getLoc(), "'}' expected"); | |||
4904 | return MatchOperand_ParseFail; | |||
4905 | } | |||
4906 | E = Parser.getTok().getEndLoc(); | |||
4907 | Parser.Lex(); // Eat '}' token. | |||
4908 | ||||
4909 | switch (LaneKind) { | |||
4910 | case NoLanes: | |||
4911 | case AllLanes: { | |||
4912 | // Two-register operands have been converted to the | |||
4913 | // composite register classes. | |||
4914 | if (Count == 2 && !hasMVE()) { | |||
4915 | const MCRegisterClass *RC = (Spacing == 1) ? | |||
4916 | &ARMMCRegisterClasses[ARM::DPairRegClassID] : | |||
4917 | &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; | |||
4918 | FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); | |||
4919 | } | |||
4920 | auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : | |||
4921 | ARMOperand::CreateVectorListAllLanes); | |||
4922 | Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); | |||
4923 | break; | |||
4924 | } | |||
4925 | case IndexedLane: | |||
4926 | Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, | |||
4927 | LaneIndex, | |||
4928 | (Spacing == 2), | |||
4929 | S, E)); | |||
4930 | break; | |||
4931 | } | |||
4932 | return MatchOperand_Success; | |||
4933 | } | |||
4934 | ||||
4935 | /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. | |||
4936 | OperandMatchResultTy | |||
4937 | ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { | |||
4938 | MCAsmParser &Parser = getParser(); | |||
4939 | SMLoc S = Parser.getTok().getLoc(); | |||
4940 | const AsmToken &Tok = Parser.getTok(); | |||
4941 | unsigned Opt; | |||
4942 | ||||
4943 | if (Tok.is(AsmToken::Identifier)) { | |||
4944 | StringRef OptStr = Tok.getString(); | |||
4945 | ||||
4946 | Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) | |||
4947 | .Case("sy", ARM_MB::SY) | |||
4948 | .Case("st", ARM_MB::ST) | |||
4949 | .Case("ld", ARM_MB::LD) | |||
4950 | .Case("sh", ARM_MB::ISH) | |||
4951 | .Case("ish", ARM_MB::ISH) | |||
4952 | .Case("shst", ARM_MB::ISHST) | |||
4953 | .Case("ishst", ARM_MB::ISHST) | |||
4954 | .Case("ishld", ARM_MB::ISHLD) | |||
4955 | .Case("nsh", ARM_MB::NSH) | |||
4956 | .Case("un", ARM_MB::NSH) | |||
4957 | .Case("nshst", ARM_MB::NSHST) | |||
4958 | .Case("nshld", ARM_MB::NSHLD) | |||
4959 | .Case("unst", ARM_MB::NSHST) | |||
4960 | .Case("osh", ARM_MB::OSH) | |||
4961 | .Case("oshst", ARM_MB::OSHST) | |||
4962 | .Case("oshld", ARM_MB::OSHLD) | |||
4963 | .Default(~0U); | |||
4964 | ||||
4965 | // ishld, oshld, nshld and ld are only available from ARMv8. | |||
4966 | if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || | |||
4967 | Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) | |||
4968 | Opt = ~0U; | |||
4969 | ||||
4970 | if (Opt == ~0U) | |||
4971 | return MatchOperand_NoMatch; | |||
4972 | ||||
4973 | Parser.Lex(); // Eat identifier token. | |||
4974 | } else if (Tok.is(AsmToken::Hash) || | |||
4975 | Tok.is(AsmToken::Dollar) || | |||
4976 | Tok.is(AsmToken::Integer)) { | |||
4977 | if (Parser.getTok().isNot(AsmToken::Integer)) | |||
4978 | Parser.Lex(); // Eat '#' or '$'. | |||
4979 | SMLoc Loc = Parser.getTok().getLoc(); | |||
4980 | ||||
4981 | const MCExpr *MemBarrierID; | |||
4982 | if (getParser().parseExpression(MemBarrierID)) { | |||
4983 | Error(Loc, "illegal expression"); | |||
4984 | return MatchOperand_ParseFail; | |||
4985 | } | |||
4986 | ||||
4987 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); | |||
4988 | if (!CE) { | |||
4989 | Error(Loc, "constant expression expected"); | |||
4990 | return MatchOperand_ParseFail; | |||
4991 | } | |||
4992 | ||||
4993 | int Val = CE->getValue(); | |||
4994 | if (Val & ~0xf) { | |||
4995 | Error(Loc, "immediate value out of range"); | |||
4996 | return MatchOperand_ParseFail; | |||
4997 | } | |||
4998 | ||||
4999 | Opt = ARM_MB::RESERVED_0 + Val; | |||
5000 | } else | |||
5001 | return MatchOperand_ParseFail; | |||
5002 | ||||
5003 | Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); | |||
5004 | return MatchOperand_Success; | |||
5005 | } | |||
5006 | ||||
5007 | OperandMatchResultTy | |||
5008 | ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { | |||
5009 | MCAsmParser &Parser = getParser(); | |||
5010 | SMLoc S = Parser.getTok().getLoc(); | |||
5011 | const AsmToken &Tok = Parser.getTok(); | |||
5012 | ||||
5013 | if (Tok.isNot(AsmToken::Identifier)) | |||
5014 | return MatchOperand_NoMatch; | |||
5015 | ||||
5016 | if (!Tok.getString().equals_insensitive("csync")) | |||
5017 | return MatchOperand_NoMatch; | |||
5018 | ||||
5019 | Parser.Lex(); // Eat identifier token. | |||
5020 | ||||
5021 | Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); | |||
5022 | return MatchOperand_Success; | |||
5023 | } | |||
5024 | ||||
5025 | /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. | |||
5026 | OperandMatchResultTy | |||
5027 | ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { | |||
5028 | MCAsmParser &Parser = getParser(); | |||
5029 | SMLoc S = Parser.getTok().getLoc(); | |||
5030 | const AsmToken &Tok = Parser.getTok(); | |||
5031 | unsigned Opt; | |||
5032 | ||||
5033 | if (Tok.is(AsmToken::Identifier)) { | |||
5034 | StringRef OptStr = Tok.getString(); | |||
5035 | ||||
5036 | if (OptStr.equals_insensitive("sy")) | |||
5037 | Opt = ARM_ISB::SY; | |||
5038 | else | |||
5039 | return MatchOperand_NoMatch; | |||
5040 | ||||
5041 | Parser.Lex(); // Eat identifier token. | |||
5042 | } else if (Tok.is(AsmToken::Hash) || | |||
5043 | Tok.is(AsmToken::Dollar) || | |||
5044 | Tok.is(AsmToken::Integer)) { | |||
5045 | if (Parser.getTok().isNot(AsmToken::Integer)) | |||
5046 | Parser.Lex(); // Eat '#' or '$'. | |||
5047 | SMLoc Loc = Parser.getTok().getLoc(); | |||
5048 | ||||
5049 | const MCExpr *ISBarrierID; | |||
5050 | if (getParser().parseExpression(ISBarrierID)) { | |||
5051 | Error(Loc, "illegal expression"); | |||
5052 | return MatchOperand_ParseFail; | |||
5053 | } | |||
5054 | ||||
5055 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); | |||
5056 | if (!CE) { | |||
5057 | Error(Loc, "constant expression expected"); | |||
5058 | return MatchOperand_ParseFail; | |||
5059 | } | |||
5060 | ||||
5061 | int Val = CE->getValue(); | |||
5062 | if (Val & ~0xf) { | |||
5063 | Error(Loc, "immediate value out of range"); | |||
5064 | return MatchOperand_ParseFail; | |||
5065 | } | |||
5066 | ||||
5067 | Opt = ARM_ISB::RESERVED_0 + Val; | |||
5068 | } else | |||
5069 | return MatchOperand_ParseFail; | |||
5070 | ||||
5071 | Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( | |||
5072 | (ARM_ISB::InstSyncBOpt)Opt, S)); | |||
5073 | return MatchOperand_Success; | |||
5074 | } | |||
5075 | ||||
5076 | ||||
5077 | /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. | |||
5078 | OperandMatchResultTy | |||
5079 | ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { | |||
5080 | MCAsmParser &Parser = getParser(); | |||
5081 | SMLoc S = Parser.getTok().getLoc(); | |||
5082 | const AsmToken &Tok = Parser.getTok(); | |||
5083 | if (!Tok.is(AsmToken::Identifier)) | |||
5084 | return MatchOperand_NoMatch; | |||
5085 | StringRef IFlagsStr = Tok.getString(); | |||
5086 | ||||
5087 | // An iflags string of "none" is interpreted to mean that none of the AIF | |||
5088 | // bits are set. Not a terribly useful instruction, but a valid encoding. | |||
5089 | unsigned IFlags = 0; | |||
5090 | if (IFlagsStr != "none") { | |||
5091 | for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { | |||
5092 | unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower()) | |||
5093 | .Case("a", ARM_PROC::A) | |||
5094 | .Case("i", ARM_PROC::I) | |||
5095 | .Case("f", ARM_PROC::F) | |||
5096 | .Default(~0U); | |||
5097 | ||||
5098 | // If some specific iflag is already set, it means that some letter is | |||
5099 | // present more than once, this is not acceptable. | |||
5100 | if (Flag == ~0U || (IFlags & Flag)) | |||
5101 | return MatchOperand_NoMatch; | |||
5102 | ||||
5103 | IFlags |= Flag; | |||
5104 | } | |||
5105 | } | |||
5106 | ||||
5107 | Parser.Lex(); // Eat identifier token. | |||
5108 | Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); | |||
5109 | return MatchOperand_Success; | |||
5110 | } | |||
5111 | ||||
5112 | /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. | |||
5113 | OperandMatchResultTy | |||
5114 | ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { | |||
5115 | MCAsmParser &Parser = getParser(); | |||
5116 | SMLoc S = Parser.getTok().getLoc(); | |||
5117 | const AsmToken &Tok = Parser.getTok(); | |||
5118 | ||||
5119 | if (Tok.is(AsmToken::Integer)) { | |||
5120 | int64_t Val = Tok.getIntVal(); | |||
5121 | if (Val > 255 || Val < 0) { | |||
5122 | return MatchOperand_NoMatch; | |||
5123 | } | |||
5124 | unsigned SYSmvalue = Val & 0xFF; | |||
5125 | Parser.Lex(); | |||
5126 | Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); | |||
5127 | return MatchOperand_Success; | |||
5128 | } | |||
5129 | ||||
5130 | if (!Tok.is(AsmToken::Identifier)) | |||
5131 | return MatchOperand_NoMatch; | |||
5132 | StringRef Mask = Tok.getString(); | |||
5133 | ||||
5134 | if (isMClass()) { | |||
5135 | auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower()); | |||
5136 | if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits())) | |||
5137 | return MatchOperand_NoMatch; | |||
5138 | ||||
5139 | unsigned SYSmvalue = TheReg->Encoding & 0xFFF; | |||
5140 | ||||
5141 | Parser.Lex(); // Eat identifier token. | |||
5142 | Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); | |||
5143 | return MatchOperand_Success; | |||
5144 | } | |||
5145 | ||||
5146 | // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" | |||
5147 | size_t Start = 0, Next = Mask.find('_'); | |||
5148 | StringRef Flags = ""; | |||
5149 | std::string SpecReg = Mask.slice(Start, Next).lower(); | |||
5150 | if (Next != StringRef::npos) | |||
5151 | Flags = Mask.slice(Next+1, Mask.size()); | |||
5152 | ||||
5153 | // FlagsVal contains the complete mask: | |||
5154 | // 3-0: Mask | |||
5155 | // 4: Special Reg (cpsr, apsr => 0; spsr => 1) | |||
5156 | unsigned FlagsVal = 0; | |||
5157 | ||||
5158 | if (SpecReg == "apsr") { | |||
5159 | FlagsVal = StringSwitch<unsigned>(Flags) | |||
5160 | .Case("nzcvq", 0x8) // same as CPSR_f | |||
5161 | .Case("g", 0x4) // same as CPSR_s | |||
5162 | .Case("nzcvqg", 0xc) // same as CPSR_fs | |||
5163 | .Default(~0U); | |||
5164 | ||||
5165 | if (FlagsVal == ~0U) { | |||
5166 | if (!Flags.empty()) | |||
5167 | return MatchOperand_NoMatch; | |||
5168 | else | |||
5169 | FlagsVal = 8; // No flag | |||
5170 | } | |||
5171 | } else if (SpecReg == "cpsr" || SpecReg == "spsr") { | |||
5172 | // cpsr_all is an alias for cpsr_fc, as is plain cpsr. | |||
5173 | if (Flags == "all" || Flags == "") | |||
5174 | Flags = "fc"; | |||
5175 | for (int i = 0, e = Flags.size(); i != e; ++i) { | |||
5176 | unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) | |||
5177 | .Case("c", 1) | |||
5178 | .Case("x", 2) | |||
5179 | .Case("s", 4) | |||
5180 | .Case("f", 8) | |||
5181 | .Default(~0U); | |||
5182 | ||||
5183 | // If some specific flag is already set, it means that some letter is | |||
5184 | // present more than once, this is not acceptable. | |||
5185 | if (Flag == ~0U || (FlagsVal & Flag)) | |||
5186 | return MatchOperand_NoMatch; | |||
5187 | FlagsVal |= Flag; | |||
5188 | } | |||
5189 | } else // No match for special register. | |||
5190 | return MatchOperand_NoMatch; | |||
5191 | ||||
5192 | // Special register without flags is NOT equivalent to "fc" flags. | |||
5193 | // NOTE: This is a divergence from gas' behavior. Uncommenting the following | |||
5194 | // two lines would enable gas compatibility at the expense of breaking | |||
5195 | // round-tripping. | |||
5196 | // | |||
5197 | // if (!FlagsVal) | |||
5198 | // FlagsVal = 0x9; | |||
5199 | ||||
5200 | // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) | |||
5201 | if (SpecReg == "spsr") | |||
5202 | FlagsVal |= 16; | |||
5203 | ||||
5204 | Parser.Lex(); // Eat identifier token. | |||
5205 | Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); | |||
5206 | return MatchOperand_Success; | |||
5207 | } | |||
5208 | ||||
5209 | /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for | |||
5210 | /// use in the MRS/MSR instructions added to support virtualization. | |||
5211 | OperandMatchResultTy | |||
5212 | ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { | |||
5213 | MCAsmParser &Parser = getParser(); | |||
5214 | SMLoc S = Parser.getTok().getLoc(); | |||
5215 | const AsmToken &Tok = Parser.getTok(); | |||
5216 | if (!Tok.is(AsmToken::Identifier)) | |||
5217 | return MatchOperand_NoMatch; | |||
5218 | StringRef RegName = Tok.getString(); | |||
5219 | ||||
5220 | auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower()); | |||
5221 | if (!TheReg) | |||
5222 | return MatchOperand_NoMatch; | |||
5223 | unsigned Encoding = TheReg->Encoding; | |||
5224 | ||||
5225 | Parser.Lex(); // Eat identifier token. | |||
5226 | Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); | |||
5227 | return MatchOperand_Success; | |||
5228 | } | |||
5229 | ||||
5230 | OperandMatchResultTy | |||
5231 | ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, | |||
5232 | int High) { | |||
5233 | MCAsmParser &Parser = getParser(); | |||
5234 | const AsmToken &Tok = Parser.getTok(); | |||
5235 | if (Tok.isNot(AsmToken::Identifier)) { | |||
5236 | Error(Parser.getTok().getLoc(), Op + " operand expected."); | |||
5237 | return MatchOperand_ParseFail; | |||
5238 | } | |||
5239 | StringRef ShiftName = Tok.getString(); | |||
5240 | std::string LowerOp = Op.lower(); | |||
5241 | std::string UpperOp = Op.upper(); | |||
5242 | if (ShiftName != LowerOp && ShiftName != UpperOp) { | |||
5243 | Error(Parser.getTok().getLoc(), Op + " operand expected."); | |||
5244 | return MatchOperand_ParseFail; | |||
5245 | } | |||
5246 | Parser.Lex(); // Eat shift type token. | |||
5247 | ||||
5248 | // There must be a '#' and a shift amount. | |||
5249 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
5250 | Parser.getTok().isNot(AsmToken::Dollar)) { | |||
5251 | Error(Parser.getTok().getLoc(), "'#' expected"); | |||
5252 | return MatchOperand_ParseFail; | |||
5253 | } | |||
5254 | Parser.Lex(); // Eat hash token. | |||
5255 | ||||
5256 | const MCExpr *ShiftAmount; | |||
5257 | SMLoc Loc = Parser.getTok().getLoc(); | |||
5258 | SMLoc EndLoc; | |||
5259 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { | |||
5260 | Error(Loc, "illegal expression"); | |||
5261 | return MatchOperand_ParseFail; | |||
5262 | } | |||
5263 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); | |||
5264 | if (!CE) { | |||
5265 | Error(Loc, "constant expression expected"); | |||
5266 | return MatchOperand_ParseFail; | |||
5267 | } | |||
5268 | int Val = CE->getValue(); | |||
5269 | if (Val < Low || Val > High) { | |||
5270 | Error(Loc, "immediate value out of range"); | |||
5271 | return MatchOperand_ParseFail; | |||
5272 | } | |||
5273 | ||||
5274 | Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); | |||
5275 | ||||
5276 | return MatchOperand_Success; | |||
5277 | } | |||
5278 | ||||
5279 | OperandMatchResultTy | |||
5280 | ARMAsmParser::parseSetEndImm(OperandVector &Operands) { | |||
5281 | MCAsmParser &Parser = getParser(); | |||
5282 | const AsmToken &Tok = Parser.getTok(); | |||
5283 | SMLoc S = Tok.getLoc(); | |||
5284 | if (Tok.isNot(AsmToken::Identifier)) { | |||
5285 | Error(S, "'be' or 'le' operand expected"); | |||
5286 | return MatchOperand_ParseFail; | |||
5287 | } | |||
5288 | int Val = StringSwitch<int>(Tok.getString().lower()) | |||
5289 | .Case("be", 1) | |||
5290 | .Case("le", 0) | |||
5291 | .Default(-1); | |||
5292 | Parser.Lex(); // Eat the token. | |||
5293 | ||||
5294 | if (Val == -1) { | |||
5295 | Error(S, "'be' or 'le' operand expected"); | |||
5296 | return MatchOperand_ParseFail; | |||
5297 | } | |||
5298 | Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, | |||
5299 | getContext()), | |||
5300 | S, Tok.getEndLoc())); | |||
5301 | return MatchOperand_Success; | |||
5302 | } | |||
5303 | ||||
5304 | /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT | |||
5305 | /// instructions. Legal values are: | |||
5306 | /// lsl #n 'n' in [0,31] | |||
5307 | /// asr #n 'n' in [1,32] | |||
5308 | /// n == 32 encoded as n == 0. | |||
5309 | OperandMatchResultTy | |||
5310 | ARMAsmParser::parseShifterImm(OperandVector &Operands) { | |||
5311 | MCAsmParser &Parser = getParser(); | |||
5312 | const AsmToken &Tok = Parser.getTok(); | |||
5313 | SMLoc S = Tok.getLoc(); | |||
5314 | if (Tok.isNot(AsmToken::Identifier)) { | |||
5315 | Error(S, "shift operator 'asr' or 'lsl' expected"); | |||
5316 | return MatchOperand_ParseFail; | |||
5317 | } | |||
5318 | StringRef ShiftName = Tok.getString(); | |||
5319 | bool isASR; | |||
5320 | if (ShiftName == "lsl" || ShiftName == "LSL") | |||
5321 | isASR = false; | |||
5322 | else if (ShiftName == "asr" || ShiftName == "ASR") | |||
5323 | isASR = true; | |||
5324 | else { | |||
5325 | Error(S, "shift operator 'asr' or 'lsl' expected"); | |||
5326 | return MatchOperand_ParseFail; | |||
5327 | } | |||
5328 | Parser.Lex(); // Eat the operator. | |||
5329 | ||||
5330 | // A '#' and a shift amount. | |||
5331 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
5332 | Parser.getTok().isNot(AsmToken::Dollar)) { | |||
5333 | Error(Parser.getTok().getLoc(), "'#' expected"); | |||
5334 | return MatchOperand_ParseFail; | |||
5335 | } | |||
5336 | Parser.Lex(); // Eat hash token. | |||
5337 | SMLoc ExLoc = Parser.getTok().getLoc(); | |||
5338 | ||||
5339 | const MCExpr *ShiftAmount; | |||
5340 | SMLoc EndLoc; | |||
5341 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { | |||
5342 | Error(ExLoc, "malformed shift expression"); | |||
5343 | return MatchOperand_ParseFail; | |||
5344 | } | |||
5345 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); | |||
5346 | if (!CE) { | |||
5347 | Error(ExLoc, "shift amount must be an immediate"); | |||
5348 | return MatchOperand_ParseFail; | |||
5349 | } | |||
5350 | ||||
5351 | int64_t Val = CE->getValue(); | |||
5352 | if (isASR) { | |||
5353 | // Shift amount must be in [1,32] | |||
5354 | if (Val < 1 || Val > 32) { | |||
5355 | Error(ExLoc, "'asr' shift amount must be in range [1,32]"); | |||
5356 | return MatchOperand_ParseFail; | |||
5357 | } | |||
5358 | // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. | |||
5359 | if (isThumb() && Val == 32) { | |||
5360 | Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); | |||
5361 | return MatchOperand_ParseFail; | |||
5362 | } | |||
5363 | if (Val == 32) Val = 0; | |||
5364 | } else { | |||
5365 | // Shift amount must be in [1,32] | |||
5366 | if (Val < 0 || Val > 31) { | |||
5367 | Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); | |||
5368 | return MatchOperand_ParseFail; | |||
5369 | } | |||
5370 | } | |||
5371 | ||||
5372 | Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); | |||
5373 | ||||
5374 | return MatchOperand_Success; | |||
5375 | } | |||
5376 | ||||
5377 | /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family | |||
5378 | /// of instructions. Legal values are: | |||
5379 | /// ror #n 'n' in {0, 8, 16, 24} | |||
5380 | OperandMatchResultTy | |||
5381 | ARMAsmParser::parseRotImm(OperandVector &Operands) { | |||
5382 | MCAsmParser &Parser = getParser(); | |||
5383 | const AsmToken &Tok = Parser.getTok(); | |||
5384 | SMLoc S = Tok.getLoc(); | |||
5385 | if (Tok.isNot(AsmToken::Identifier)) | |||
5386 | return MatchOperand_NoMatch; | |||
5387 | StringRef ShiftName = Tok.getString(); | |||
5388 | if (ShiftName != "ror" && ShiftName != "ROR") | |||
5389 | return MatchOperand_NoMatch; | |||
5390 | Parser.Lex(); // Eat the operator. | |||
5391 | ||||
5392 | // A '#' and a rotate amount. | |||
5393 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
5394 | Parser.getTok().isNot(AsmToken::Dollar)) { | |||
5395 | Error(Parser.getTok().getLoc(), "'#' expected"); | |||
5396 | return MatchOperand_ParseFail; | |||
5397 | } | |||
5398 | Parser.Lex(); // Eat hash token. | |||
5399 | SMLoc ExLoc = Parser.getTok().getLoc(); | |||
5400 | ||||
5401 | const MCExpr *ShiftAmount; | |||
5402 | SMLoc EndLoc; | |||
5403 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { | |||
5404 | Error(ExLoc, "malformed rotate expression"); | |||
5405 | return MatchOperand_ParseFail; | |||
5406 | } | |||
5407 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); | |||
5408 | if (!CE) { | |||
5409 | Error(ExLoc, "rotate amount must be an immediate"); | |||
5410 | return MatchOperand_ParseFail; | |||
5411 | } | |||
5412 | ||||
5413 | int64_t Val = CE->getValue(); | |||
5414 | // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) | |||
5415 | // normally, zero is represented in asm by omitting the rotate operand | |||
5416 | // entirely. | |||
5417 | if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { | |||
5418 | Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); | |||
5419 | return MatchOperand_ParseFail; | |||
5420 | } | |||
5421 | ||||
5422 | Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); | |||
5423 | ||||
5424 | return MatchOperand_Success; | |||
5425 | } | |||
5426 | ||||
5427 | OperandMatchResultTy | |||
5428 | ARMAsmParser::parseModImm(OperandVector &Operands) { | |||
5429 | MCAsmParser &Parser = getParser(); | |||
5430 | MCAsmLexer &Lexer = getLexer(); | |||
5431 | int64_t Imm1, Imm2; | |||
5432 | ||||
5433 | SMLoc S = Parser.getTok().getLoc(); | |||
5434 | ||||
5435 | // 1) A mod_imm operand can appear in the place of a register name: | |||
5436 | // add r0, #mod_imm | |||
5437 | // add r0, r0, #mod_imm | |||
5438 | // to correctly handle the latter, we bail out as soon as we see an | |||
5439 | // identifier. | |||
5440 | // | |||
5441 | // 2) Similarly, we do not want to parse into complex operands: | |||
5442 | // mov r0, #mod_imm | |||
5443 | // mov r0, :lower16:(_foo) | |||
5444 | if (Parser.getTok().is(AsmToken::Identifier) || | |||
5445 | Parser.getTok().is(AsmToken::Colon)) | |||
5446 | return MatchOperand_NoMatch; | |||
5447 | ||||
5448 | // Hash (dollar) is optional as per the ARMARM | |||
5449 | if (Parser.getTok().is(AsmToken::Hash) || | |||
5450 | Parser.getTok().is(AsmToken::Dollar)) { | |||
5451 | // Avoid parsing into complex operands (#:) | |||
5452 | if (Lexer.peekTok().is(AsmToken::Colon)) | |||
5453 | return MatchOperand_NoMatch; | |||
5454 | ||||
5455 | // Eat the hash (dollar) | |||
5456 | Parser.Lex(); | |||
5457 | } | |||
5458 | ||||
5459 | SMLoc Sx1, Ex1; | |||
5460 | Sx1 = Parser.getTok().getLoc(); | |||
5461 | const MCExpr *Imm1Exp; | |||
5462 | if (getParser().parseExpression(Imm1Exp, Ex1)) { | |||
5463 | Error(Sx1, "malformed expression"); | |||
5464 | return MatchOperand_ParseFail; | |||
5465 | } | |||
5466 | ||||
5467 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp); | |||
5468 | ||||
5469 | if (CE) { | |||
5470 | // Immediate must fit within 32-bits | |||
5471 | Imm1 = CE->getValue(); | |||
5472 | int Enc = ARM_AM::getSOImmVal(Imm1); | |||
5473 | if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { | |||
5474 | // We have a match! | |||
5475 | Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), | |||
5476 | (Enc & 0xF00) >> 7, | |||
5477 | Sx1, Ex1)); | |||
5478 | return MatchOperand_Success; | |||
5479 | } | |||
5480 | ||||
5481 | // We have parsed an immediate which is not for us, fallback to a plain | |||
5482 | // immediate. This can happen for instruction aliases. For an example, | |||
5483 | // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform | |||
5484 | // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite | |||
5485 | // instruction with a mod_imm operand. The alias is defined such that the | |||
5486 | // parser method is shared, that's why we have to do this here. | |||
5487 | if (Parser.getTok().is(AsmToken::EndOfStatement)) { | |||
5488 | Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); | |||
5489 | return MatchOperand_Success; | |||
5490 | } | |||
5491 | } else { | |||
5492 | // Operands like #(l1 - l2) can only be evaluated at a later stage (via an | |||
5493 | // MCFixup). Fallback to a plain immediate. | |||
5494 | Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); | |||
5495 | return MatchOperand_Success; | |||
5496 | } | |||
5497 | ||||
5498 | // From this point onward, we expect the input to be a (#bits, #rot) pair | |||
5499 | if (Parser.getTok().isNot(AsmToken::Comma)) { | |||
5500 | Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); | |||
5501 | return MatchOperand_ParseFail; | |||
5502 | } | |||
5503 | ||||
5504 | if (Imm1 & ~0xFF) { | |||
5505 | Error(Sx1, "immediate operand must a number in the range [0, 255]"); | |||
5506 | return MatchOperand_ParseFail; | |||
5507 | } | |||
5508 | ||||
5509 | // Eat the comma | |||
5510 | Parser.Lex(); | |||
5511 | ||||
5512 | // Repeat for #rot | |||
5513 | SMLoc Sx2, Ex2; | |||
5514 | Sx2 = Parser.getTok().getLoc(); | |||
5515 | ||||
5516 | // Eat the optional hash (dollar) | |||
5517 | if (Parser.getTok().is(AsmToken::Hash) || | |||
5518 | Parser.getTok().is(AsmToken::Dollar)) | |||
5519 | Parser.Lex(); | |||
5520 | ||||
5521 | const MCExpr *Imm2Exp; | |||
5522 | if (getParser().parseExpression(Imm2Exp, Ex2)) { | |||
5523 | Error(Sx2, "malformed expression"); | |||
5524 | return MatchOperand_ParseFail; | |||
5525 | } | |||
5526 | ||||
5527 | CE = dyn_cast<MCConstantExpr>(Imm2Exp); | |||
5528 | ||||
5529 | if (CE) { | |||
5530 | Imm2 = CE->getValue(); | |||
5531 | if (!(Imm2 & ~0x1E)) { | |||
5532 | // We have a match! | |||
5533 | Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); | |||
5534 | return MatchOperand_Success; | |||
5535 | } | |||
5536 | Error(Sx2, "immediate operand must an even number in the range [0, 30]"); | |||
5537 | return MatchOperand_ParseFail; | |||
5538 | } else { | |||
5539 | Error(Sx2, "constant expression expected"); | |||
5540 | return MatchOperand_ParseFail; | |||
5541 | } | |||
5542 | } | |||
5543 | ||||
5544 | OperandMatchResultTy | |||
5545 | ARMAsmParser::parseBitfield(OperandVector &Operands) { | |||
5546 | MCAsmParser &Parser = getParser(); | |||
5547 | SMLoc S = Parser.getTok().getLoc(); | |||
5548 | // The bitfield descriptor is really two operands, the LSB and the width. | |||
5549 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
5550 | Parser.getTok().isNot(AsmToken::Dollar)) { | |||
5551 | Error(Parser.getTok().getLoc(), "'#' expected"); | |||
5552 | return MatchOperand_ParseFail; | |||
5553 | } | |||
5554 | Parser.Lex(); // Eat hash token. | |||
5555 | ||||
5556 | const MCExpr *LSBExpr; | |||
5557 | SMLoc E = Parser.getTok().getLoc(); | |||
5558 | if (getParser().parseExpression(LSBExpr)) { | |||
5559 | Error(E, "malformed immediate expression"); | |||
5560 | return MatchOperand_ParseFail; | |||
5561 | } | |||
5562 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); | |||
5563 | if (!CE) { | |||
5564 | Error(E, "'lsb' operand must be an immediate"); | |||
5565 | return MatchOperand_ParseFail; | |||
5566 | } | |||
5567 | ||||
5568 | int64_t LSB = CE->getValue(); | |||
5569 | // The LSB must be in the range [0,31] | |||
5570 | if (LSB < 0 || LSB > 31) { | |||
5571 | Error(E, "'lsb' operand must be in the range [0,31]"); | |||
5572 | return MatchOperand_ParseFail; | |||
5573 | } | |||
5574 | E = Parser.getTok().getLoc(); | |||
5575 | ||||
5576 | // Expect another immediate operand. | |||
5577 | if (Parser.getTok().isNot(AsmToken::Comma)) { | |||
5578 | Error(Parser.getTok().getLoc(), "too few operands"); | |||
5579 | return MatchOperand_ParseFail; | |||
5580 | } | |||
5581 | Parser.Lex(); // Eat hash token. | |||
5582 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
5583 | Parser.getTok().isNot(AsmToken::Dollar)) { | |||
5584 | Error(Parser.getTok().getLoc(), "'#' expected"); | |||
5585 | return MatchOperand_ParseFail; | |||
5586 | } | |||
5587 | Parser.Lex(); // Eat hash token. | |||
5588 | ||||
5589 | const MCExpr *WidthExpr; | |||
5590 | SMLoc EndLoc; | |||
5591 | if (getParser().parseExpression(WidthExpr, EndLoc)) { | |||
5592 | Error(E, "malformed immediate expression"); | |||
5593 | return MatchOperand_ParseFail; | |||
5594 | } | |||
5595 | CE = dyn_cast<MCConstantExpr>(WidthExpr); | |||
5596 | if (!CE) { | |||
5597 | Error(E, "'width' operand must be an immediate"); | |||
5598 | return MatchOperand_ParseFail; | |||
5599 | } | |||
5600 | ||||
5601 | int64_t Width = CE->getValue(); | |||
5602 | // The LSB must be in the range [1,32-lsb] | |||
5603 | if (Width < 1 || Width > 32 - LSB) { | |||
5604 | Error(E, "'width' operand must be in the range [1,32-lsb]"); | |||
5605 | return MatchOperand_ParseFail; | |||
5606 | } | |||
5607 | ||||
5608 | Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); | |||
5609 | ||||
5610 | return MatchOperand_Success; | |||
5611 | } | |||
5612 | ||||
5613 | OperandMatchResultTy | |||
5614 | ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { | |||
5615 | // Check for a post-index addressing register operand. Specifically: | |||
5616 | // postidx_reg := '+' register {, shift} | |||
5617 | // | '-' register {, shift} | |||
5618 | // | register {, shift} | |||
5619 | ||||
5620 | // This method must return MatchOperand_NoMatch without consuming any tokens | |||
5621 | // in the case where there is no match, as other alternatives take other | |||
5622 | // parse methods. | |||
5623 | MCAsmParser &Parser = getParser(); | |||
5624 | AsmToken Tok = Parser.getTok(); | |||
5625 | SMLoc S = Tok.getLoc(); | |||
5626 | bool haveEaten = false; | |||
5627 | bool isAdd = true; | |||
5628 | if (Tok.is(AsmToken::Plus)) { | |||
5629 | Parser.Lex(); // Eat the '+' token. | |||
5630 | haveEaten = true; | |||
5631 | } else if (Tok.is(AsmToken::Minus)) { | |||
5632 | Parser.Lex(); // Eat the '-' token. | |||
5633 | isAdd = false; | |||
5634 | haveEaten = true; | |||
5635 | } | |||
5636 | ||||
5637 | SMLoc E = Parser.getTok().getEndLoc(); | |||
5638 | int Reg = tryParseRegister(); | |||
5639 | if (Reg == -1) { | |||
5640 | if (!haveEaten) | |||
5641 | return MatchOperand_NoMatch; | |||
5642 | Error(Parser.getTok().getLoc(), "register expected"); | |||
5643 | return MatchOperand_ParseFail; | |||
5644 | } | |||
5645 | ||||
5646 | ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; | |||
5647 | unsigned ShiftImm = 0; | |||
5648 | if (Parser.getTok().is(AsmToken::Comma)) { | |||
5649 | Parser.Lex(); // Eat the ','. | |||
5650 | if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) | |||
5651 | return MatchOperand_ParseFail; | |||
5652 | ||||
5653 | // FIXME: Only approximates end...may include intervening whitespace. | |||
5654 | E = Parser.getTok().getLoc(); | |||
5655 | } | |||
5656 | ||||
5657 | Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, | |||
5658 | ShiftImm, S, E)); | |||
5659 | ||||
5660 | return MatchOperand_Success; | |||
5661 | } | |||
5662 | ||||
5663 | OperandMatchResultTy | |||
5664 | ARMAsmParser::parseAM3Offset(OperandVector &Operands) { | |||
5665 | // Check for a post-index addressing register operand. Specifically: | |||
5666 | // am3offset := '+' register | |||
5667 | // | '-' register | |||
5668 | // | register | |||
5669 | // | # imm | |||
5670 | // | # + imm | |||
5671 | // | # - imm | |||
5672 | ||||
5673 | // This method must return MatchOperand_NoMatch without consuming any tokens | |||
5674 | // in the case where there is no match, as other alternatives take other | |||
5675 | // parse methods. | |||
5676 | MCAsmParser &Parser = getParser(); | |||
5677 | AsmToken Tok = Parser.getTok(); | |||
5678 | SMLoc S = Tok.getLoc(); | |||
5679 | ||||
5680 | // Do immediates first, as we always parse those if we have a '#'. | |||
5681 | if (Parser.getTok().is(AsmToken::Hash) || | |||
5682 | Parser.getTok().is(AsmToken::Dollar)) { | |||
5683 | Parser.Lex(); // Eat '#' or '$'. | |||
5684 | // Explicitly look for a '-', as we need to encode negative zero | |||
5685 | // differently. | |||
5686 | bool isNegative = Parser.getTok().is(AsmToken::Minus); | |||
5687 | const MCExpr *Offset; | |||
5688 | SMLoc E; | |||
5689 | if (getParser().parseExpression(Offset, E)) | |||
5690 | return MatchOperand_ParseFail; | |||
5691 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); | |||
5692 | if (!CE) { | |||
5693 | Error(S, "constant expression expected"); | |||
5694 | return MatchOperand_ParseFail; | |||
5695 | } | |||
5696 | // Negative zero is encoded as the flag value | |||
5697 | // std::numeric_limits<int32_t>::min(). | |||
5698 | int32_t Val = CE->getValue(); | |||
5699 | if (isNegative && Val == 0) | |||
5700 | Val = std::numeric_limits<int32_t>::min(); | |||
5701 | ||||
5702 | Operands.push_back( | |||
5703 | ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E)); | |||
5704 | ||||
5705 | return MatchOperand_Success; | |||
5706 | } | |||
5707 | ||||
5708 | bool haveEaten = false; | |||
5709 | bool isAdd = true; | |||
5710 | if (Tok.is(AsmToken::Plus)) { | |||
5711 | Parser.Lex(); // Eat the '+' token. | |||
5712 | haveEaten = true; | |||
5713 | } else if (Tok.is(AsmToken::Minus)) { | |||
5714 | Parser.Lex(); // Eat the '-' token. | |||
5715 | isAdd = false; | |||
5716 | haveEaten = true; | |||
5717 | } | |||
5718 | ||||
5719 | Tok = Parser.getTok(); | |||
5720 | int Reg = tryParseRegister(); | |||
5721 | if (Reg == -1) { | |||
5722 | if (!haveEaten) | |||
5723 | return MatchOperand_NoMatch; | |||
5724 | Error(Tok.getLoc(), "register expected"); | |||
5725 | return MatchOperand_ParseFail; | |||
5726 | } | |||
5727 | ||||
5728 | Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, | |||
5729 | 0, S, Tok.getEndLoc())); | |||
5730 | ||||
5731 | return MatchOperand_Success; | |||
5732 | } | |||
5733 | ||||
5734 | /// Convert parsed operands to MCInst. Needed here because this instruction | |||
5735 | /// only has two register operands, but multiplication is commutative so | |||
5736 | /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". | |||
5737 | void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, | |||
5738 | const OperandVector &Operands) { | |||
5739 | ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); | |||
5740 | ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); | |||
5741 | // If we have a three-operand form, make sure to set Rn to be the operand | |||
5742 | // that isn't the same as Rd. | |||
5743 | unsigned RegOp = 4; | |||
5744 | if (Operands.size() == 6 && | |||
5745 | ((ARMOperand &)*Operands[4]).getReg() == | |||
5746 | ((ARMOperand &)*Operands[3]).getReg()) | |||
5747 | RegOp = 5; | |||
5748 | ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); | |||
5749 | Inst.addOperand(Inst.getOperand(0)); | |||
5750 | ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); | |||
5751 | } | |||
5752 | ||||
5753 | void ARMAsmParser::cvtThumbBranches(MCInst &Inst, | |||
5754 | const OperandVector &Operands) { | |||
5755 | int CondOp = -1, ImmOp = -1; | |||
5756 | switch(Inst.getOpcode()) { | |||
5757 | case ARM::tB: | |||
5758 | case ARM::tBcc: CondOp = 1; ImmOp = 2; break; | |||
5759 | ||||
5760 | case ARM::t2B: | |||
5761 | case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; | |||
5762 | ||||
5763 | default: llvm_unreachable("Unexpected instruction in cvtThumbBranches")__builtin_unreachable(); | |||
5764 | } | |||
5765 | // first decide whether or not the branch should be conditional | |||
5766 | // by looking at it's location relative to an IT block | |||
5767 | if(inITBlock()) { | |||
5768 | // inside an IT block we cannot have any conditional branches. any | |||
5769 | // such instructions needs to be converted to unconditional form | |||
5770 | switch(Inst.getOpcode()) { | |||
5771 | case ARM::tBcc: Inst.setOpcode(ARM::tB); break; | |||
5772 | case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; | |||
5773 | } | |||
5774 | } else { | |||
5775 | // outside IT blocks we can only have unconditional branches with AL | |||
5776 | // condition code or conditional branches with non-AL condition code | |||
5777 | unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); | |||
5778 | switch(Inst.getOpcode()) { | |||
5779 | case ARM::tB: | |||
5780 | case ARM::tBcc: | |||
5781 | Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); | |||
5782 | break; | |||
5783 | case ARM::t2B: | |||
5784 | case ARM::t2Bcc: | |||
5785 | Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); | |||
5786 | break; | |||
5787 | } | |||
5788 | } | |||
5789 | ||||
5790 | // now decide on encoding size based on branch target range | |||
5791 | switch(Inst.getOpcode()) { | |||
5792 | // classify tB as either t2B or t1B based on range of immediate operand | |||
5793 | case ARM::tB: { | |||
5794 | ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); | |||
5795 | if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline()) | |||
5796 | Inst.setOpcode(ARM::t2B); | |||
5797 | break; | |||
5798 | } | |||
5799 | // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand | |||
5800 | case ARM::tBcc: { | |||
5801 | ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); | |||
5802 | if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline()) | |||
5803 | Inst.setOpcode(ARM::t2Bcc); | |||
5804 | break; | |||
5805 | } | |||
5806 | } | |||
5807 | ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); | |||
5808 | ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); | |||
5809 | } | |||
5810 | ||||
5811 | void ARMAsmParser::cvtMVEVMOVQtoDReg( | |||
5812 | MCInst &Inst, const OperandVector &Operands) { | |||
5813 | ||||
5814 | // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2 | |||
5815 | assert(Operands.size() == 8)(static_cast<void> (0)); | |||
5816 | ||||
5817 | ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt | |||
5818 | ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 | |||
5819 | ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd | |||
5820 | ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx | |||
5821 | // skip second copy of Qd in Operands[6] | |||
5822 | ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 | |||
5823 | ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code | |||
5824 | } | |||
5825 | ||||
5826 | /// Parse an ARM memory expression, return false if successful else return true | |||
5827 | /// or an error. The first token must be a '[' when called. | |||
5828 | bool ARMAsmParser::parseMemory(OperandVector &Operands) { | |||
5829 | MCAsmParser &Parser = getParser(); | |||
5830 | SMLoc S, E; | |||
5831 | if (Parser.getTok().isNot(AsmToken::LBrac)) | |||
5832 | return TokError("Token is not a Left Bracket"); | |||
5833 | S = Parser.getTok().getLoc(); | |||
5834 | Parser.Lex(); // Eat left bracket token. | |||
5835 | ||||
5836 | const AsmToken &BaseRegTok = Parser.getTok(); | |||
5837 | int BaseRegNum = tryParseRegister(); | |||
5838 | if (BaseRegNum == -1) | |||
5839 | return Error(BaseRegTok.getLoc(), "register expected"); | |||
5840 | ||||
5841 | // The next token must either be a comma, a colon or a closing bracket. | |||
5842 | const AsmToken &Tok = Parser.getTok(); | |||
5843 | if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && | |||
5844 | !Tok.is(AsmToken::RBrac)) | |||
5845 | return Error(Tok.getLoc(), "malformed memory operand"); | |||
5846 | ||||
5847 | if (Tok.is(AsmToken::RBrac)) { | |||
5848 | E = Tok.getEndLoc(); | |||
5849 | Parser.Lex(); // Eat right bracket token. | |||
5850 | ||||
5851 | Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, | |||
5852 | ARM_AM::no_shift, 0, 0, false, | |||
5853 | S, E)); | |||
5854 | ||||
5855 | // If there's a pre-indexing writeback marker, '!', just add it as a token | |||
5856 | // operand. It's rather odd, but syntactically valid. | |||
5857 | if (Parser.getTok().is(AsmToken::Exclaim)) { | |||
5858 | Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); | |||
5859 | Parser.Lex(); // Eat the '!'. | |||
5860 | } | |||
5861 | ||||
5862 | return false; | |||
5863 | } | |||
5864 | ||||
5865 | assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&(static_cast<void> (0)) | |||
5866 | "Lost colon or comma in memory operand?!")(static_cast<void> (0)); | |||
5867 | if (Tok.is(AsmToken::Comma)) { | |||
5868 | Parser.Lex(); // Eat the comma. | |||
5869 | } | |||
5870 | ||||
5871 | // If we have a ':', it's an alignment specifier. | |||
5872 | if (Parser.getTok().is(AsmToken::Colon)) { | |||
5873 | Parser.Lex(); // Eat the ':'. | |||
5874 | E = Parser.getTok().getLoc(); | |||
5875 | SMLoc AlignmentLoc = Tok.getLoc(); | |||
5876 | ||||
5877 | const MCExpr *Expr; | |||
5878 | if (getParser().parseExpression(Expr)) | |||
5879 | return true; | |||
5880 | ||||
5881 | // The expression has to be a constant. Memory references with relocations | |||
5882 | // don't come through here, as they use the <label> forms of the relevant | |||
5883 | // instructions. | |||
5884 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); | |||
5885 | if (!CE) | |||
5886 | return Error (E, "constant expression expected"); | |||
5887 | ||||
5888 | unsigned Align = 0; | |||
5889 | switch (CE->getValue()) { | |||
5890 | default: | |||
5891 | return Error(E, | |||
5892 | "alignment specifier must be 16, 32, 64, 128, or 256 bits"); | |||
5893 | case 16: Align = 2; break; | |||
5894 | case 32: Align = 4; break; | |||
5895 | case 64: Align = 8; break; | |||
5896 | case 128: Align = 16; break; | |||
5897 | case 256: Align = 32; break; | |||
5898 | } | |||
5899 | ||||
5900 | // Now we should have the closing ']' | |||
5901 | if (Parser.getTok().isNot(AsmToken::RBrac)) | |||
5902 | return Error(Parser.getTok().getLoc(), "']' expected"); | |||
5903 | E = Parser.getTok().getEndLoc(); | |||
5904 | Parser.Lex(); // Eat right bracket token. | |||
5905 | ||||
5906 | // Don't worry about range checking the value here. That's handled by | |||
5907 | // the is*() predicates. | |||
5908 | Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, | |||
5909 | ARM_AM::no_shift, 0, Align, | |||
5910 | false, S, E, AlignmentLoc)); | |||
5911 | ||||
5912 | // If there's a pre-indexing writeback marker, '!', just add it as a token | |||
5913 | // operand. | |||
5914 | if (Parser.getTok().is(AsmToken::Exclaim)) { | |||
5915 | Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); | |||
5916 | Parser.Lex(); // Eat the '!'. | |||
5917 | } | |||
5918 | ||||
5919 | return false; | |||
5920 | } | |||
5921 | ||||
5922 | // If we have a '#' or '$', it's an immediate offset, else assume it's a | |||
5923 | // register offset. Be friendly and also accept a plain integer or expression | |||
5924 | // (without a leading hash) for gas compatibility. | |||
5925 | if (Parser.getTok().is(AsmToken::Hash) || | |||
5926 | Parser.getTok().is(AsmToken::Dollar) || | |||
5927 | Parser.getTok().is(AsmToken::LParen) || | |||
5928 | Parser.getTok().is(AsmToken::Integer)) { | |||
5929 | if (Parser.getTok().is(AsmToken::Hash) || | |||
5930 | Parser.getTok().is(AsmToken::Dollar)) | |||
5931 | Parser.Lex(); // Eat '#' or '$' | |||
5932 | E = Parser.getTok().getLoc(); | |||
5933 | ||||
5934 | bool isNegative = getParser().getTok().is(AsmToken::Minus); | |||
5935 | const MCExpr *Offset, *AdjustedOffset; | |||
5936 | if (getParser().parseExpression(Offset)) | |||
5937 | return true; | |||
5938 | ||||
5939 | if (const auto *CE = dyn_cast<MCConstantExpr>(Offset)) { | |||
5940 | // If the constant was #-0, represent it as | |||
5941 | // std::numeric_limits<int32_t>::min(). | |||
5942 | int32_t Val = CE->getValue(); | |||
5943 | if (isNegative && Val == 0) | |||
5944 | CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(), | |||
5945 | getContext()); | |||
5946 | // Don't worry about range checking the value here. That's handled by | |||
5947 | // the is*() predicates. | |||
5948 | AdjustedOffset = CE; | |||
5949 | } else | |||
5950 | AdjustedOffset = Offset; | |||
5951 | Operands.push_back(ARMOperand::CreateMem( | |||
5952 | BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E)); | |||
5953 | ||||
5954 | // Now we should have the closing ']' | |||
5955 | if (Parser.getTok().isNot(AsmToken::RBrac)) | |||
5956 | return Error(Parser.getTok().getLoc(), "']' expected"); | |||
5957 | E = Parser.getTok().getEndLoc(); | |||
5958 | Parser.Lex(); // Eat right bracket token. | |||
5959 | ||||
5960 | // If there's a pre-indexing writeback marker, '!', just add it as a token | |||
5961 | // operand. | |||
5962 | if (Parser.getTok().is(AsmToken::Exclaim)) { | |||
5963 | Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); | |||
5964 | Parser.Lex(); // Eat the '!'. | |||
5965 | } | |||
5966 | ||||
5967 | return false; | |||
5968 | } | |||
5969 | ||||
5970 | // The register offset is optionally preceded by a '+' or '-' | |||
5971 | bool isNegative = false; | |||
5972 | if (Parser.getTok().is(AsmToken::Minus)) { | |||
5973 | isNegative = true; | |||
5974 | Parser.Lex(); // Eat the '-'. | |||
5975 | } else if (Parser.getTok().is(AsmToken::Plus)) { | |||
5976 | // Nothing to do. | |||
5977 | Parser.Lex(); // Eat the '+'. | |||
5978 | } | |||
5979 | ||||
5980 | E = Parser.getTok().getLoc(); | |||
5981 | int OffsetRegNum = tryParseRegister(); | |||
5982 | if (OffsetRegNum == -1) | |||
5983 | return Error(E, "register expected"); | |||
5984 | ||||
5985 | // If there's a shift operator, handle it. | |||
5986 | ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; | |||
5987 | unsigned ShiftImm = 0; | |||
5988 | if (Parser.getTok().is(AsmToken::Comma)) { | |||
5989 | Parser.Lex(); // Eat the ','. | |||
5990 | if (parseMemRegOffsetShift(ShiftType, ShiftImm)) | |||
5991 | return true; | |||
5992 | } | |||
5993 | ||||
5994 | // Now we should have the closing ']' | |||
5995 | if (Parser.getTok().isNot(AsmToken::RBrac)) | |||
5996 | return Error(Parser.getTok().getLoc(), "']' expected"); | |||
5997 | E = Parser.getTok().getEndLoc(); | |||
5998 | Parser.Lex(); // Eat right bracket token. | |||
5999 | ||||
6000 | Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, | |||
6001 | ShiftType, ShiftImm, 0, isNegative, | |||
6002 | S, E)); | |||
6003 | ||||
6004 | // If there's a pre-indexing writeback marker, '!', just add it as a token | |||
6005 | // operand. | |||
6006 | if (Parser.getTok().is(AsmToken::Exclaim)) { | |||
6007 | Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); | |||
6008 | Parser.Lex(); // Eat the '!'. | |||
6009 | } | |||
6010 | ||||
6011 | return false; | |||
6012 | } | |||
6013 | ||||
6014 | /// parseMemRegOffsetShift - one of these two: | |||
6015 | /// ( lsl | lsr | asr | ror ) , # shift_amount | |||
6016 | /// rrx | |||
6017 | /// return true if it parses a shift otherwise it returns false. | |||
6018 | bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, | |||
6019 | unsigned &Amount) { | |||
6020 | MCAsmParser &Parser = getParser(); | |||
6021 | SMLoc Loc = Parser.getTok().getLoc(); | |||
6022 | const AsmToken &Tok = Parser.getTok(); | |||
6023 | if (Tok.isNot(AsmToken::Identifier)) | |||
6024 | return Error(Loc, "illegal shift operator"); | |||
6025 | StringRef ShiftName = Tok.getString(); | |||
6026 | if (ShiftName == "lsl" || ShiftName == "LSL" || | |||
6027 | ShiftName == "asl" || ShiftName == "ASL") | |||
6028 | St = ARM_AM::lsl; | |||
6029 | else if (ShiftName == "lsr" || ShiftName == "LSR") | |||
6030 | St = ARM_AM::lsr; | |||
6031 | else if (ShiftName == "asr" || ShiftName == "ASR") | |||
6032 | St = ARM_AM::asr; | |||
6033 | else if (ShiftName == "ror" || ShiftName == "ROR") | |||
6034 | St = ARM_AM::ror; | |||
6035 | else if (ShiftName == "rrx" || ShiftName == "RRX") | |||
6036 | St = ARM_AM::rrx; | |||
6037 | else if (ShiftName == "uxtw" || ShiftName == "UXTW") | |||
6038 | St = ARM_AM::uxtw; | |||
6039 | else | |||
6040 | return Error(Loc, "illegal shift operator"); | |||
6041 | Parser.Lex(); // Eat shift type token. | |||
6042 | ||||
6043 | // rrx stands alone. | |||
6044 | Amount = 0; | |||
6045 | if (St != ARM_AM::rrx) { | |||
6046 | Loc = Parser.getTok().getLoc(); | |||
6047 | // A '#' and a shift amount. | |||
6048 | const AsmToken &HashTok = Parser.getTok(); | |||
6049 | if (HashTok.isNot(AsmToken::Hash) && | |||
6050 | HashTok.isNot(AsmToken::Dollar)) | |||
6051 | return Error(HashTok.getLoc(), "'#' expected"); | |||
6052 | Parser.Lex(); // Eat hash token. | |||
6053 | ||||
6054 | const MCExpr *Expr; | |||
6055 | if (getParser().parseExpression(Expr)) | |||
6056 | return true; | |||
6057 | // Range check the immediate. | |||
6058 | // lsl, ror: 0 <= imm <= 31 | |||
6059 | // lsr, asr: 0 <= imm <= 32 | |||
6060 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); | |||
6061 | if (!CE) | |||
6062 | return Error(Loc, "shift amount must be an immediate"); | |||
6063 | int64_t Imm = CE->getValue(); | |||
6064 | if (Imm < 0 || | |||
6065 | ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || | |||
6066 | ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) | |||
6067 | return Error(Loc, "immediate shift value out of range"); | |||
6068 | // If <ShiftTy> #0, turn it into a no_shift. | |||
6069 | if (Imm == 0) | |||
6070 | St = ARM_AM::lsl; | |||
6071 | // For consistency, treat lsr #32 and asr #32 as having immediate value 0. | |||
6072 | if (Imm == 32) | |||
6073 | Imm = 0; | |||
6074 | Amount = Imm; | |||
6075 | } | |||
6076 | ||||
6077 | return false; | |||
6078 | } | |||
6079 | ||||
6080 | /// parseFPImm - A floating point immediate expression operand. | |||
6081 | OperandMatchResultTy | |||
6082 | ARMAsmParser::parseFPImm(OperandVector &Operands) { | |||
6083 | MCAsmParser &Parser = getParser(); | |||
6084 | // Anything that can accept a floating point constant as an operand | |||
6085 | // needs to go through here, as the regular parseExpression is | |||
6086 | // integer only. | |||
6087 | // | |||
6088 | // This routine still creates a generic Immediate operand, containing | |||
6089 | // a bitcast of the 64-bit floating point value. The various operands | |||
6090 | // that accept floats can check whether the value is valid for them | |||
6091 | // via the standard is*() predicates. | |||
6092 | ||||
6093 | SMLoc S = Parser.getTok().getLoc(); | |||
6094 | ||||
6095 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
6096 | Parser.getTok().isNot(AsmToken::Dollar)) | |||
6097 | return MatchOperand_NoMatch; | |||
6098 | ||||
6099 | // Disambiguate the VMOV forms that can accept an FP immediate. | |||
6100 | // vmov.f32 <sreg>, #imm | |||
6101 | // vmov.f64 <dreg>, #imm | |||
6102 | // vmov.f32 <dreg>, #imm @ vector f32x2 | |||
6103 | // vmov.f32 <qreg>, #imm @ vector f32x4 | |||
6104 | // | |||
6105 | // There are also the NEON VMOV instructions which expect an | |||
6106 | // integer constant. Make sure we don't try to parse an FPImm | |||
6107 | // for these: | |||
6108 | // vmov.i{8|16|32|64} <dreg|qreg>, #imm | |||
6109 | ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); | |||
6110 | bool isVmovf = TyOp.isToken() && | |||
6111 | (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" || | |||
6112 | TyOp.getToken() == ".f16"); | |||
6113 | ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); | |||
6114 | bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || | |||
6115 | Mnemonic.getToken() == "fconsts"); | |||
6116 | if (!(isVmovf || isFconst)) | |||
6117 | return MatchOperand_NoMatch; | |||
6118 | ||||
6119 | Parser.Lex(); // Eat '#' or '$'. | |||
6120 | ||||
6121 | // Handle negation, as that still comes through as a separate token. | |||
6122 | bool isNegative = false; | |||
6123 | if (Parser.getTok().is(AsmToken::Minus)) { | |||
6124 | isNegative = true; | |||
6125 | Parser.Lex(); | |||
6126 | } | |||
6127 | const AsmToken &Tok = Parser.getTok(); | |||
6128 | SMLoc Loc = Tok.getLoc(); | |||
6129 | if (Tok.is(AsmToken::Real) && isVmovf) { | |||
6130 | APFloat RealVal(APFloat::IEEEsingle(), Tok.getString()); | |||
6131 | uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); | |||
6132 | // If we had a '-' in front, toggle the sign bit. | |||
6133 | IntVal ^= (uint64_t)isNegative << 31; | |||
6134 | Parser.Lex(); // Eat the token. | |||
6135 | Operands.push_back(ARMOperand::CreateImm( | |||
6136 | MCConstantExpr::create(IntVal, getContext()), | |||
6137 | S, Parser.getTok().getLoc())); | |||
6138 | return MatchOperand_Success; | |||
6139 | } | |||
6140 | // Also handle plain integers. Instructions which allow floating point | |||
6141 | // immediates also allow a raw encoded 8-bit value. | |||
6142 | if (Tok.is(AsmToken::Integer) && isFconst) { | |||
6143 | int64_t Val = Tok.getIntVal(); | |||
6144 | Parser.Lex(); // Eat the token. | |||
6145 | if (Val > 255 || Val < 0) { | |||
6146 | Error(Loc, "encoded floating point value out of range"); | |||
6147 | return MatchOperand_ParseFail; | |||
6148 | } | |||
6149 | float RealVal = ARM_AM::getFPImmFloat(Val); | |||
6150 | Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); | |||
6151 | ||||
6152 | Operands.push_back(ARMOperand::CreateImm( | |||
6153 | MCConstantExpr::create(Val, getContext()), S, | |||
6154 | Parser.getTok().getLoc())); | |||
6155 | return MatchOperand_Success; | |||
6156 | } | |||
6157 | ||||
6158 | Error(Loc, "invalid floating point immediate"); | |||
6159 | return MatchOperand_ParseFail; | |||
6160 | } | |||
6161 | ||||
6162 | /// Parse a arm instruction operand. For now this parses the operand regardless | |||
6163 | /// of the mnemonic. | |||
6164 | bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { | |||
6165 | MCAsmParser &Parser = getParser(); | |||
6166 | SMLoc S, E; | |||
6167 | ||||
6168 | // Check if the current operand has a custom associated parser, if so, try to | |||
6169 | // custom parse the operand, or fallback to the general approach. | |||
6170 | OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); | |||
6171 | if (ResTy == MatchOperand_Success) | |||
6172 | return false; | |||
6173 | // If there wasn't a custom match, try the generic matcher below. Otherwise, | |||
6174 | // there was a match, but an error occurred, in which case, just return that | |||
6175 | // the operand parsing failed. | |||
6176 | if (ResTy == MatchOperand_ParseFail) | |||
6177 | return true; | |||
6178 | ||||
6179 | switch (getLexer().getKind()) { | |||
6180 | default: | |||
6181 | Error(Parser.getTok().getLoc(), "unexpected token in operand"); | |||
6182 | return true; | |||
6183 | case AsmToken::Identifier: { | |||
6184 | // If we've seen a branch mnemonic, the next operand must be a label. This | |||
6185 | // is true even if the label is a register name. So "br r1" means branch to | |||
6186 | // label "r1". | |||
6187 | bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; | |||
6188 | if (!ExpectLabel) { | |||
6189 | if (!tryParseRegisterWithWriteBack(Operands)) | |||
6190 | return false; | |||
6191 | int Res = tryParseShiftRegister(Operands); | |||
6192 | if (Res == 0) // success | |||
6193 | return false; | |||
6194 | else if (Res == -1) // irrecoverable error | |||
6195 | return true; | |||
6196 | // If this is VMRS, check for the apsr_nzcv operand. | |||
6197 | if (Mnemonic == "vmrs" && | |||
6198 | Parser.getTok().getString().equals_insensitive("apsr_nzcv")) { | |||
6199 | S = Parser.getTok().getLoc(); | |||
6200 | Parser.Lex(); | |||
6201 | Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); | |||
6202 | return false; | |||
6203 | } | |||
6204 | } | |||
6205 | ||||
6206 | // Fall though for the Identifier case that is not a register or a | |||
6207 | // special name. | |||
6208 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | |||
6209 | } | |||
6210 | case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) | |||
6211 | case AsmToken::Integer: // things like 1f and 2b as a branch targets | |||
6212 | case AsmToken::String: // quoted label names. | |||
6213 | case AsmToken::Dot: { // . as a branch target | |||
6214 | // This was not a register so parse other operands that start with an | |||
6215 | // identifier (like labels) as expressions and create them as immediates. | |||
6216 | const MCExpr *IdVal; | |||
6217 | S = Parser.getTok().getLoc(); | |||
6218 | if (getParser().parseExpression(IdVal)) | |||
6219 | return true; | |||
6220 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); | |||
6221 | Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); | |||
6222 | return false; | |||
6223 | } | |||
6224 | case AsmToken::LBrac: | |||
6225 | return parseMemory(Operands); | |||
6226 | case AsmToken::LCurly: | |||
6227 | return parseRegisterList(Operands, !Mnemonic.startswith("clr")); | |||
6228 | case AsmToken::Dollar: | |||
6229 | case AsmToken::Hash: { | |||
6230 | // #42 -> immediate | |||
6231 | // $ 42 -> immediate | |||
6232 | // $foo -> symbol name | |||
6233 | // $42 -> symbol name | |||
6234 | S = Parser.getTok().getLoc(); | |||
6235 | ||||
6236 | // Favor the interpretation of $-prefixed operands as symbol names. | |||
6237 | // Cases where immediates are explicitly expected are handled by their | |||
6238 | // specific ParseMethod implementations. | |||
6239 | auto AdjacentToken = getLexer().peekTok(/*ShouldSkipSpace=*/false); | |||
6240 | bool ExpectIdentifier = Parser.getTok().is(AsmToken::Dollar) && | |||
6241 | (AdjacentToken.is(AsmToken::Identifier) || | |||
6242 | AdjacentToken.is(AsmToken::Integer)); | |||
6243 | if (!ExpectIdentifier) { | |||
6244 | // Token is not part of identifier. Drop leading $ or # before parsing | |||
6245 | // expression. | |||
6246 | Parser.Lex(); | |||
6247 | } | |||
6248 | ||||
6249 | if (Parser.getTok().isNot(AsmToken::Colon)) { | |||
6250 | bool IsNegative = Parser.getTok().is(AsmToken::Minus); | |||
6251 | const MCExpr *ImmVal; | |||
6252 | if (getParser().parseExpression(ImmVal)) | |||
6253 | return true; | |||
6254 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); | |||
6255 | if (CE) { | |||
6256 | int32_t Val = CE->getValue(); | |||
6257 | if (IsNegative && Val == 0) | |||
6258 | ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(), | |||
6259 | getContext()); | |||
6260 | } | |||
6261 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); | |||
6262 | Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); | |||
6263 | ||||
6264 | // There can be a trailing '!' on operands that we want as a separate | |||
6265 | // '!' Token operand. Handle that here. For example, the compatibility | |||
6266 | // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. | |||
6267 | if (Parser.getTok().is(AsmToken::Exclaim)) { | |||
6268 | Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), | |||
6269 | Parser.getTok().getLoc())); | |||
6270 | Parser.Lex(); // Eat exclaim token | |||
6271 | } | |||
6272 | return false; | |||
6273 | } | |||
6274 | // w/ a ':' after the '#', it's just like a plain ':'. | |||
6275 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | |||
6276 | } | |||
6277 | case AsmToken::Colon: { | |||
6278 | S = Parser.getTok().getLoc(); | |||
6279 | // ":lower16:" and ":upper16:" expression prefixes | |||
6280 | // FIXME: Check it's an expression prefix, | |||
6281 | // e.g. (FOO - :lower16:BAR) isn't legal. | |||
6282 | ARMMCExpr::VariantKind RefKind; | |||
6283 | if (parsePrefix(RefKind)) | |||
6284 | return true; | |||
6285 | ||||
6286 | const MCExpr *SubExprVal; | |||
6287 | if (getParser().parseExpression(SubExprVal)) | |||
6288 | return true; | |||
6289 | ||||
6290 | const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal, | |||
6291 | getContext()); | |||
6292 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); | |||
6293 | Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); | |||
6294 | return false; | |||
6295 | } | |||
6296 | case AsmToken::Equal: { | |||
6297 | S = Parser.getTok().getLoc(); | |||
6298 | if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) | |||
6299 | return Error(S, "unexpected token in operand"); | |||
6300 | Parser.Lex(); // Eat '=' | |||
6301 | const MCExpr *SubExprVal; | |||
6302 | if (getParser().parseExpression(SubExprVal)) | |||
6303 | return true; | |||
6304 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); | |||
6305 | ||||
6306 | // execute-only: we assume that assembly programmers know what they are | |||
6307 | // doing and allow literal pool creation here | |||
6308 | Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); | |||
6309 | return false; | |||
6310 | } | |||
6311 | } | |||
6312 | } | |||
6313 | ||||
6314 | // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. | |||
6315 | // :lower16: and :upper16:. | |||
6316 | bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { | |||
6317 | MCAsmParser &Parser = getParser(); | |||
6318 | RefKind = ARMMCExpr::VK_ARM_None; | |||
6319 | ||||
6320 | // consume an optional '#' (GNU compatibility) | |||
6321 | if (getLexer().is(AsmToken::Hash)) | |||
6322 | Parser.Lex(); | |||
6323 | ||||
6324 | // :lower16: and :upper16: modifiers | |||
6325 | assert(getLexer().is(AsmToken::Colon) && "expected a :")(static_cast<void> (0)); | |||
6326 | Parser.Lex(); // Eat ':' | |||
6327 | ||||
6328 | if (getLexer().isNot(AsmToken::Identifier)) { | |||
6329 | Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); | |||
6330 | return true; | |||
6331 | } | |||
6332 | ||||
6333 | enum { | |||
6334 | COFF = (1 << MCContext::IsCOFF), | |||
6335 | ELF = (1 << MCContext::IsELF), | |||
6336 | MACHO = (1 << MCContext::IsMachO), | |||
6337 | WASM = (1 << MCContext::IsWasm), | |||
6338 | }; | |||
6339 | static const struct PrefixEntry { | |||
6340 | const char *Spelling; | |||
6341 | ARMMCExpr::VariantKind VariantKind; | |||
6342 | uint8_t SupportedFormats; | |||
6343 | } PrefixEntries[] = { | |||
6344 | { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO }, | |||
6345 | { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO }, | |||
6346 | }; | |||
6347 | ||||
6348 | StringRef IDVal = Parser.getTok().getIdentifier(); | |||
6349 | ||||
6350 | const auto &Prefix = | |||
6351 | llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) { | |||
6352 | return PE.Spelling == IDVal; | |||
6353 | }); | |||
6354 | if (Prefix == std::end(PrefixEntries)) { | |||
6355 | Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); | |||
6356 | return true; | |||
6357 | } | |||
6358 | ||||
6359 | uint8_t CurrentFormat; | |||
6360 | switch (getContext().getObjectFileType()) { | |||
6361 | case MCContext::IsMachO: | |||
6362 | CurrentFormat = MACHO; | |||
6363 | break; | |||
6364 | case MCContext::IsELF: | |||
6365 | CurrentFormat = ELF; | |||
6366 | break; | |||
6367 | case MCContext::IsCOFF: | |||
6368 | CurrentFormat = COFF; | |||
6369 | break; | |||
6370 | case MCContext::IsWasm: | |||
6371 | CurrentFormat = WASM; | |||
6372 | break; | |||
6373 | case MCContext::IsGOFF: | |||
6374 | case MCContext::IsXCOFF: | |||
6375 | llvm_unreachable("unexpected object format")__builtin_unreachable(); | |||
6376 | break; | |||
6377 | } | |||
6378 | ||||
6379 | if (~Prefix->SupportedFormats & CurrentFormat) { | |||
6380 | Error(Parser.getTok().getLoc(), | |||
6381 | "cannot represent relocation in the current file format"); | |||
6382 | return true; | |||
6383 | } | |||
6384 | ||||
6385 | RefKind = Prefix->VariantKind; | |||
6386 | Parser.Lex(); | |||
6387 | ||||
6388 | if (getLexer().isNot(AsmToken::Colon)) { | |||
6389 | Error(Parser.getTok().getLoc(), "unexpected token after prefix"); | |||
6390 | return true; | |||
6391 | } | |||
6392 | Parser.Lex(); // Eat the last ':' | |||
6393 | ||||
6394 | return false; | |||
6395 | } | |||
6396 | ||||
6397 | /// Given a mnemonic, split out possible predication code and carry | |||
6398 | /// setting letters to form a canonical mnemonic and flags. | |||
6399 | // | |||
6400 | // FIXME: Would be nice to autogen this. | |||
6401 | // FIXME: This is a bit of a maze of special cases. | |||
6402 | StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, | |||
6403 | StringRef ExtraToken, | |||
6404 | unsigned &PredicationCode, | |||
6405 | unsigned &VPTPredicationCode, | |||
6406 | bool &CarrySetting, | |||
6407 | unsigned &ProcessorIMod, | |||
6408 | StringRef &ITMask) { | |||
6409 | PredicationCode = ARMCC::AL; | |||
6410 | VPTPredicationCode = ARMVCC::None; | |||
6411 | CarrySetting = false; | |||
6412 | ProcessorIMod = 0; | |||
6413 | ||||
6414 | // Ignore some mnemonics we know aren't predicated forms. | |||
6415 | // | |||
6416 | // FIXME: Would be nice to autogen this. | |||
6417 | if ((Mnemonic == "movs" && isThumb()) || | |||
6418 | Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || | |||
6419 | Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || | |||
6420 | Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || | |||
6421 | Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || | |||
6422 | Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || | |||
6423 | Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || | |||
6424 | Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || | |||
6425 | Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || | |||
6426 | Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || | |||
6427 | Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || | |||
6428 | Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || | |||
6429 | Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" || | |||
6430 | Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" || | |||
6431 | Mnemonic == "bxns" || Mnemonic == "blxns" || | |||
6432 | Mnemonic == "vdot" || Mnemonic == "vmmla" || | |||
6433 | Mnemonic == "vudot" || Mnemonic == "vsdot" || | |||
6434 | Mnemonic == "vcmla" || Mnemonic == "vcadd" || | |||
6435 | Mnemonic == "vfmal" || Mnemonic == "vfmsl" || | |||
6436 | Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" || | |||
6437 | Mnemonic == "csel" || Mnemonic == "csinc" || | |||
6438 | Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" || | |||
6439 | Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" || | |||
6440 | Mnemonic == "csetm") | |||
6441 | return Mnemonic; | |||
6442 | ||||
6443 | // First, split out any predication code. Ignore mnemonics we know aren't | |||
6444 | // predicated but do have a carry-set and so weren't caught above. | |||
6445 | if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && | |||
6446 | Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && | |||
6447 | Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && | |||
6448 | Mnemonic != "sbcs" && Mnemonic != "rscs" && | |||
6449 | !(hasMVE() && | |||
6450 | (Mnemonic == "vmine" || | |||
6451 | Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" || | |||
6452 | Mnemonic == "vrshle" || Mnemonic == "vrshlt" || | |||
6453 | Mnemonic == "vmvne" || Mnemonic == "vorne" || | |||
6454 | Mnemonic == "vnege" || Mnemonic == "vnegt" || | |||
6455 | Mnemonic == "vmule" || Mnemonic == "vmult" || | |||
6456 | Mnemonic == "vrintne" || | |||
6457 | Mnemonic == "vcmult" || Mnemonic == "vcmule" || | |||
6458 | Mnemonic == "vpsele" || Mnemonic == "vpselt" || | |||
6459 | Mnemonic.startswith("vq")))) { | |||
6460 | unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2)); | |||
6461 | if (CC != ~0U) { | |||
6462 | Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); | |||
6463 | PredicationCode = CC; | |||
6464 | } | |||
6465 | } | |||
6466 | ||||
6467 | // Next, determine if we have a carry setting bit. We explicitly ignore all | |||
6468 | // the instructions we know end in 's'. | |||
6469 | if (Mnemonic.endswith("s") && | |||
6470 | !(Mnemonic == "cps" || Mnemonic == "mls" || | |||
6471 | Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || | |||
6472 | Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || | |||
6473 | Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || | |||
6474 | Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || | |||
6475 | Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || | |||
6476 | Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || | |||
6477 | Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || | |||
6478 | Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || | |||
6479 | Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" || | |||
6480 | Mnemonic == "vmlas" || | |||
6481 | (Mnemonic == "movs" && isThumb()))) { | |||
6482 | Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); | |||
6483 | CarrySetting = true; | |||
6484 | } | |||
6485 | ||||
6486 | // The "cps" instruction can have a interrupt mode operand which is glued into | |||
6487 | // the mnemonic. Check if this is the case, split it and parse the imod op | |||
6488 | if (Mnemonic.startswith("cps")) { | |||
6489 | // Split out any imod code. | |||
6490 | unsigned IMod = | |||
6491 | StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) | |||
6492 | .Case("ie", ARM_PROC::IE) | |||
6493 | .Case("id", ARM_PROC::ID) | |||
6494 | .Default(~0U); | |||
6495 | if (IMod != ~0U) { | |||
6496 | Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); | |||
6497 | ProcessorIMod = IMod; | |||
6498 | } | |||
6499 | } | |||
6500 | ||||
6501 | if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" && | |||
6502 | Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" && | |||
6503 | Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" && | |||
6504 | Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" && | |||
6505 | Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" && | |||
6506 | Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" && | |||
6507 | Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") { | |||
6508 | unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1)); | |||
6509 | if (CC != ~0U) { | |||
6510 | Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1); | |||
6511 | VPTPredicationCode = CC; | |||
6512 | } | |||
6513 | return Mnemonic; | |||
6514 | } | |||
6515 | ||||
6516 | // The "it" instruction has the condition mask on the end of the mnemonic. | |||
6517 | if (Mnemonic.startswith("it")) { | |||
6518 | ITMask = Mnemonic.slice(2, Mnemonic.size()); | |||
6519 | Mnemonic = Mnemonic.slice(0, 2); | |||
6520 | } | |||
6521 | ||||
6522 | if (Mnemonic.startswith("vpst")) { | |||
6523 | ITMask = Mnemonic.slice(4, Mnemonic.size()); | |||
6524 | Mnemonic = Mnemonic.slice(0, 4); | |||
6525 | } | |||
6526 | else if (Mnemonic.startswith("vpt")) { | |||
6527 | ITMask = Mnemonic.slice(3, Mnemonic.size()); | |||
6528 | Mnemonic = Mnemonic.slice(0, 3); | |||
6529 | } | |||
6530 | ||||
6531 | return Mnemonic; | |||
6532 | } | |||
6533 | ||||
6534 | /// Given a canonical mnemonic, determine if the instruction ever allows | |||
6535 | /// inclusion of carry set or predication code operands. | |||
6536 | // | |||
6537 | // FIXME: It would be nice to autogen this. | |||
6538 | void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, | |||
6539 | StringRef ExtraToken, | |||
6540 | StringRef FullInst, | |||
6541 | bool &CanAcceptCarrySet, | |||
6542 | bool &CanAcceptPredicationCode, | |||
6543 | bool &CanAcceptVPTPredicationCode) { | |||
6544 | CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken); | |||
6545 | ||||
6546 | CanAcceptCarrySet = | |||
6547 | Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || | |||
6548 | Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || | |||
6549 | Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" || | |||
6550 | Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" || | |||
6551 | Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" || | |||
6552 | Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" || | |||
6553 | Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" || | |||
6554 | (!isThumb() && | |||
6555 | (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" || | |||
6556 | Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull")); | |||
6557 | ||||
6558 | if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || | |||
6559 | Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || | |||
6560 | Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || | |||
6561 | Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || | |||
6562 | Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || | |||
6563 | Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || | |||
6564 | Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || | |||
6565 | Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" || | |||
6566 | Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" || | |||
6567 | Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || | |||
6568 | (FullInst.startswith("vmull") && FullInst.endswith(".p64")) || | |||
6569 | Mnemonic == "vmovx" || Mnemonic == "vins" || | |||
6570 | Mnemonic == "vudot" || Mnemonic == "vsdot" || | |||
6571 | Mnemonic == "vcmla" || Mnemonic == "vcadd" || | |||
6572 | Mnemonic == "vfmal" || Mnemonic == "vfmsl" || | |||
6573 | Mnemonic == "vfmat" || Mnemonic == "vfmab" || | |||
6574 | Mnemonic == "vdot" || Mnemonic == "vmmla" || | |||
6575 | Mnemonic == "sb" || Mnemonic == "ssbb" || | |||
6576 | Mnemonic == "pssbb" || Mnemonic == "vsmmla" || | |||
6577 | Mnemonic == "vummla" || Mnemonic == "vusmmla" || | |||
6578 | Mnemonic == "vusdot" || Mnemonic == "vsudot" || | |||
6579 | Mnemonic == "bfcsel" || Mnemonic == "wls" || | |||
6580 | Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" || | |||
6581 | Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" || | |||
6582 | Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" || | |||
6583 | Mnemonic == "cset" || Mnemonic == "csetm" || | |||
6584 | Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") || | |||
6585 | (hasCDE() && MS.isCDEInstr(Mnemonic) && | |||
6586 | !MS.isITPredicableCDEInstr(Mnemonic)) || | |||
6587 | (hasMVE() && | |||
6588 | (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") || | |||
6589 | Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") || | |||
6590 | Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") || | |||
6591 | Mnemonic.startswith("letp")))) { | |||
6592 | // These mnemonics are never predicable | |||
6593 | CanAcceptPredicationCode = false; | |||
6594 | } else if (!isThumb()) { | |||
6595 | // Some instructions are only predicable in Thumb mode | |||
6596 | CanAcceptPredicationCode = | |||
6597 | Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && | |||
6598 | Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && | |||
6599 | Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" && | |||
6600 | Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" && | |||
6601 | Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" && | |||
6602 | Mnemonic != "stc2" && Mnemonic != "stc2l" && | |||
6603 | Mnemonic != "tsb" && | |||
6604 | !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); | |||
6605 | } else if (isThumbOne()) { | |||
6606 | if (hasV6MOps()) | |||
6607 | CanAcceptPredicationCode = Mnemonic != "movs"; | |||
6608 | else | |||
6609 | CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; | |||
6610 | } else | |||
6611 | CanAcceptPredicationCode = true; | |||
6612 | } | |||
6613 | ||||
6614 | // Some Thumb instructions have two operand forms that are not | |||
6615 | // available as three operand, convert to two operand form if possible. | |||
6616 | // | |||
6617 | // FIXME: We would really like to be able to tablegen'erate this. | |||
6618 | void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic, | |||
6619 | bool CarrySetting, | |||
6620 | OperandVector &Operands) { | |||
6621 | if (Operands.size() != 6) | |||
6622 | return; | |||
6623 | ||||
6624 | const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); | |||
6625 | auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); | |||
6626 | if (!Op3.isReg() || !Op4.isReg()) | |||
6627 | return; | |||
6628 | ||||
6629 | auto Op3Reg = Op3.getReg(); | |||
6630 | auto Op4Reg = Op4.getReg(); | |||
6631 | ||||
6632 | // For most Thumb2 cases we just generate the 3 operand form and reduce | |||
6633 | // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr) | |||
6634 | // won't accept SP or PC so we do the transformation here taking care | |||
6635 | // with immediate range in the 'add sp, sp #imm' case. | |||
6636 | auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); | |||
6637 | if (isThumbTwo()) { | |||
6638 | if (Mnemonic != "add") | |||
6639 | return; | |||
6640 | bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || | |||
6641 | (Op5.isReg() && Op5.getReg() == ARM::PC); | |||
6642 | if (!TryTransform) { | |||
6643 | TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || | |||
6644 | (Op5.isReg() && Op5.getReg() == ARM::SP)) && | |||
6645 | !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && | |||
6646 | Op5.isImm() && !Op5.isImm0_508s4()); | |||
6647 | } | |||
6648 | if (!TryTransform) | |||
6649 | return; | |||
6650 | } else if (!isThumbOne()) | |||
6651 | return; | |||
6652 | ||||
6653 | if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" || | |||
6654 | Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" || | |||
6655 | Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" || | |||
6656 | Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) | |||
6657 | return; | |||
6658 | ||||
6659 | // If first 2 operands of a 3 operand instruction are the same | |||
6660 | // then transform to 2 operand version of the same instruction | |||
6661 | // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' | |||
6662 | bool Transform = Op3Reg == Op4Reg; | |||
6663 | ||||
6664 | // For communtative operations, we might be able to transform if we swap | |||
6665 | // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially | |||
6666 | // as tADDrsp. | |||
6667 | const ARMOperand *LastOp = &Op5; | |||
6668 | bool Swap = false; | |||
6669 | if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && | |||
6670 | ((Mnemonic == "add" && Op4Reg != ARM::SP) || | |||
6671 | Mnemonic == "and" || Mnemonic == "eor" || | |||
6672 | Mnemonic == "adc" || Mnemonic == "orr")) { | |||
6673 | Swap = true; | |||
6674 | LastOp = &Op4; | |||
6675 | Transform = true; | |||
6676 | } | |||
6677 | ||||
6678 | // If both registers are the same then remove one of them from | |||
6679 | // the operand list, with certain exceptions. | |||
6680 | if (Transform) { | |||
6681 | // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the | |||
6682 | // 2 operand forms don't exist. | |||
6683 | if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") && | |||
6684 | LastOp->isReg()) | |||
6685 | Transform = false; | |||
6686 | ||||
6687 | // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into | |||
6688 | // 3-bits because the ARMARM says not to. | |||
6689 | if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7()) | |||
6690 | Transform = false; | |||
6691 | } | |||
6692 | ||||
6693 | if (Transform) { | |||
6694 | if (Swap) | |||
6695 | std::swap(Op4, Op5); | |||
6696 | Operands.erase(Operands.begin() + 3); | |||
6697 | } | |||
6698 | } | |||
6699 | ||||
6700 | bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, | |||
6701 | OperandVector &Operands) { | |||
6702 | // FIXME: This is all horribly hacky. We really need a better way to deal | |||
6703 | // with optional operands like this in the matcher table. | |||
6704 | ||||
6705 | // The 'mov' mnemonic is special. One variant has a cc_out operand, while | |||
6706 | // another does not. Specifically, the MOVW instruction does not. So we | |||
6707 | // special case it here and remove the defaulted (non-setting) cc_out | |||
6708 | // operand if that's the instruction we're trying to match. | |||
6709 | // | |||
6710 | // We do this as post-processing of the explicit operands rather than just | |||
6711 | // conditionally adding the cc_out in the first place because we need | |||
6712 | // to check the type of the parsed immediate operand. | |||
6713 | if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && | |||
6714 | !static_cast<ARMOperand &>(*Operands[4]).isModImm() && | |||
6715 | static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && | |||
6716 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) | |||
6717 | return true; | |||
6718 | ||||
6719 | // Register-register 'add' for thumb does not have a cc_out operand | |||
6720 | // when there are only two register operands. | |||
6721 | if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && | |||
6722 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6723 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
6724 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) | |||
6725 | return true; | |||
6726 | // Register-register 'add' for thumb does not have a cc_out operand | |||
6727 | // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do | |||
6728 | // have to check the immediate range here since Thumb2 has a variant | |||
6729 | // that can handle a different range and has a cc_out operand. | |||
6730 | if (((isThumb() && Mnemonic == "add") || | |||
6731 | (isThumbTwo() && Mnemonic == "sub")) && | |||
6732 | Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6733 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
6734 | static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && | |||
6735 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && | |||
6736 | ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || | |||
6737 | static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) | |||
6738 | return true; | |||
6739 | // For Thumb2, add/sub immediate does not have a cc_out operand for the | |||
6740 | // imm0_4095 variant. That's the least-preferred variant when | |||
6741 | // selecting via the generic "add" mnemonic, so to know that we | |||
6742 | // should remove the cc_out operand, we have to explicitly check that | |||
6743 | // it's not one of the other variants. Ugh. | |||
6744 | if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && | |||
6745 | Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6746 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
6747 | static_cast<ARMOperand &>(*Operands[5]).isImm()) { | |||
6748 | // Nest conditions rather than one big 'if' statement for readability. | |||
6749 | // | |||
6750 | // If both registers are low, we're in an IT block, and the immediate is | |||
6751 | // in range, we should use encoding T1 instead, which has a cc_out. | |||
6752 | if (inITBlock() && | |||
6753 | isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && | |||
6754 | isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && | |||
6755 | static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) | |||
6756 | return false; | |||
6757 | // Check against T3. If the second register is the PC, this is an | |||
6758 | // alternate form of ADR, which uses encoding T4, so check for that too. | |||
6759 | if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && | |||
6760 | (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() || | |||
6761 | static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg())) | |||
6762 | return false; | |||
6763 | ||||
6764 | // Otherwise, we use encoding T4, which does not have a cc_out | |||
6765 | // operand. | |||
6766 | return true; | |||
6767 | } | |||
6768 | ||||
6769 | // The thumb2 multiply instruction doesn't have a CCOut register, so | |||
6770 | // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to | |||
6771 | // use the 16-bit encoding or not. | |||
6772 | if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && | |||
6773 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && | |||
6774 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6775 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
6776 | static_cast<ARMOperand &>(*Operands[5]).isReg() && | |||
6777 | // If the registers aren't low regs, the destination reg isn't the | |||
6778 | // same as one of the source regs, or the cc_out operand is zero | |||
6779 | // outside of an IT block, we have to use the 32-bit encoding, so | |||
6780 | // remove the cc_out operand. | |||
6781 | (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || | |||
6782 | !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || | |||
6783 | !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || | |||
6784 | !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != | |||
6785 | static_cast<ARMOperand &>(*Operands[5]).getReg() && | |||
6786 | static_cast<ARMOperand &>(*Operands[3]).getReg() != | |||
6787 | static_cast<ARMOperand &>(*Operands[4]).getReg()))) | |||
6788 | return true; | |||
6789 | ||||
6790 | // Also check the 'mul' syntax variant that doesn't specify an explicit | |||
6791 | // destination register. | |||
6792 | if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && | |||
6793 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && | |||
6794 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6795 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
6796 | // If the registers aren't low regs or the cc_out operand is zero | |||
6797 | // outside of an IT block, we have to use the 32-bit encoding, so | |||
6798 | // remove the cc_out operand. | |||
6799 | (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || | |||
6800 | !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || | |||
6801 | !inITBlock())) | |||
6802 | return true; | |||
6803 | ||||
6804 | // Register-register 'add/sub' for thumb does not have a cc_out operand | |||
6805 | // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also | |||
6806 | // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't | |||
6807 | // right, this will result in better diagnostics (which operand is off) | |||
6808 | // anyway. | |||
6809 | if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && | |||
6810 | (Operands.size() == 5 || Operands.size() == 6) && | |||
6811 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6812 | static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && | |||
6813 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && | |||
6814 | (static_cast<ARMOperand &>(*Operands[4]).isImm() || | |||
6815 | (Operands.size() == 6 && | |||
6816 | static_cast<ARMOperand &>(*Operands[5]).isImm()))) { | |||
6817 | // Thumb2 (add|sub){s}{p}.w GPRnopc, sp, #{T2SOImm} has cc_out | |||
6818 | return (!(isThumbTwo() && | |||
6819 | (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() || | |||
6820 | static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg()))); | |||
6821 | } | |||
6822 | // Fixme: Should join all the thumb+thumb2 (add|sub) in a single if case | |||
6823 | // Thumb2 ADD r0, #4095 -> ADDW r0, r0, #4095 (T4) | |||
6824 | // Thumb2 SUB r0, #4095 -> SUBW r0, r0, #4095 | |||
6825 | if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && | |||
6826 | (Operands.size() == 5) && | |||
6827 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
6828 | static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && | |||
6829 | static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && | |||
6830 | static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && | |||
6831 | static_cast<ARMOperand &>(*Operands[4]).isImm()) { | |||
6832 | const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]); | |||
6833 | if (IMM.isT2SOImm() || IMM.isT2SOImmNeg()) | |||
6834 | return false; // add.w / sub.w | |||
6835 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) { | |||
6836 | const int64_t Value = CE->getValue(); | |||
6837 | // Thumb1 imm8 sub / add | |||
6838 | if ((Value < ((1 << 7) - 1) << 2) && inITBlock() && (!(Value & 3)) && | |||
6839 | isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg())) | |||
6840 | return false; | |||
6841 | return true; // Thumb2 T4 addw / subw | |||
6842 | } | |||
6843 | } | |||
6844 | return false; | |||
6845 | } | |||
6846 | ||||
6847 | bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, | |||
6848 | OperandVector &Operands) { | |||
6849 | // VRINT{Z, X} have a predicate operand in VFP, but not in NEON | |||
6850 | unsigned RegIdx = 3; | |||
6851 | if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) || | |||
6852 | Mnemonic == "vrintr") && | |||
6853 | (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || | |||
6854 | static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { | |||
6855 | if (static_cast<ARMOperand &>(*Operands[3]).isToken() && | |||
6856 | (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || | |||
6857 | static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) | |||
6858 | RegIdx = 4; | |||
6859 | ||||
6860 | if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && | |||
6861 | (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( | |||
6862 | static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || | |||
6863 | ARMMCRegisterClasses[ARM::QPRRegClassID].contains( | |||
6864 | static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) | |||
6865 | return true; | |||
6866 | } | |||
6867 | return false; | |||
6868 | } | |||
6869 | ||||
6870 | bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic, | |||
6871 | OperandVector &Operands) { | |||
6872 | if (!hasMVE() || Operands.size() < 3) | |||
6873 | return true; | |||
6874 | ||||
6875 | if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") || | |||
6876 | Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4")) | |||
6877 | return true; | |||
6878 | ||||
6879 | if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot")) | |||
6880 | return false; | |||
6881 | ||||
6882 | if (Mnemonic.startswith("vmov") && | |||
6883 | !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") || | |||
6884 | Mnemonic.startswith("vmovx"))) { | |||
6885 | for (auto &Operand : Operands) { | |||
6886 | if (static_cast<ARMOperand &>(*Operand).isVectorIndex() || | |||
6887 | ((*Operand).isReg() && | |||
6888 | (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( | |||
6889 | (*Operand).getReg()) || | |||
6890 | ARMMCRegisterClasses[ARM::DPRRegClassID].contains( | |||
6891 | (*Operand).getReg())))) { | |||
6892 | return true; | |||
6893 | } | |||
6894 | } | |||
6895 | return false; | |||
6896 | } else { | |||
6897 | for (auto &Operand : Operands) { | |||
6898 | // We check the larger class QPR instead of just the legal class | |||
6899 | // MQPR, to more accurately report errors when using Q registers | |||
6900 | // outside of the allowed range. | |||
6901 | if (static_cast<ARMOperand &>(*Operand).isVectorIndex() || | |||
6902 | (Operand->isReg() && | |||
6903 | (ARMMCRegisterClasses[ARM::QPRRegClassID].contains( | |||
6904 | Operand->getReg())))) | |||
6905 | return false; | |||
6906 | } | |||
6907 | return true; | |||
6908 | } | |||
6909 | } | |||
6910 | ||||
6911 | static bool isDataTypeToken(StringRef Tok) { | |||
6912 | return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || | |||
6913 | Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || | |||
6914 | Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || | |||
6915 | Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || | |||
6916 | Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || | |||
6917 | Tok == ".f" || Tok == ".d"; | |||
6918 | } | |||
6919 | ||||
6920 | // FIXME: This bit should probably be handled via an explicit match class | |||
6921 | // in the .td files that matches the suffix instead of having it be | |||
6922 | // a literal string token the way it is now. | |||
6923 | static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { | |||
6924 | return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); | |||
6925 | } | |||
6926 | ||||
6927 | static void applyMnemonicAliases(StringRef &Mnemonic, | |||
6928 | const FeatureBitset &Features, | |||
6929 | unsigned VariantID); | |||
6930 | ||||
6931 | // The GNU assembler has aliases of ldrd and strd with the second register | |||
6932 | // omitted. We don't have a way to do that in tablegen, so fix it up here. | |||
6933 | // | |||
6934 | // We have to be careful to not emit an invalid Rt2 here, because the rest of | |||
6935 | // the assembly parser could then generate confusing diagnostics refering to | |||
6936 | // it. If we do find anything that prevents us from doing the transformation we | |||
6937 | // bail out, and let the assembly parser report an error on the instruction as | |||
6938 | // it is written. | |||
6939 | void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic, | |||
6940 | OperandVector &Operands) { | |||
6941 | if (Mnemonic != "ldrd" && Mnemonic != "strd") | |||
6942 | return; | |||
6943 | if (Operands.size() < 4) | |||
6944 | return; | |||
6945 | ||||
6946 | ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); | |||
6947 | ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); | |||
6948 | ||||
6949 | if (!Op2.isReg()) | |||
6950 | return; | |||
6951 | if (!Op3.isGPRMem()) | |||
6952 | return; | |||
6953 | ||||
6954 | const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); | |||
6955 | if (!GPR.contains(Op2.getReg())) | |||
6956 | return; | |||
6957 | ||||
6958 | unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg()); | |||
6959 | if (!isThumb() && (RtEncoding & 1)) { | |||
6960 | // In ARM mode, the registers must be from an aligned pair, this | |||
6961 | // restriction does not apply in Thumb mode. | |||
6962 | return; | |||
6963 | } | |||
6964 | if (Op2.getReg() == ARM::PC) | |||
6965 | return; | |||
6966 | unsigned PairedReg = GPR.getRegister(RtEncoding + 1); | |||
6967 | if (!PairedReg || PairedReg == ARM::PC || | |||
6968 | (PairedReg == ARM::SP && !hasV8Ops())) | |||
6969 | return; | |||
6970 | ||||
6971 | Operands.insert( | |||
6972 | Operands.begin() + 3, | |||
6973 | ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); | |||
6974 | } | |||
6975 | ||||
6976 | // Dual-register instruction have the following syntax: | |||
6977 | // <mnemonic> <predicate>? <coproc>, <Rdest>, <Rdest+1>, <Rsrc>, ..., #imm | |||
6978 | // This function tries to remove <Rdest+1> and replace <Rdest> with a pair | |||
6979 | // operand. If the conversion fails an error is diagnosed, and the function | |||
6980 | // returns true. | |||
6981 | bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic, | |||
6982 | OperandVector &Operands) { | |||
6983 | assert(MS.isCDEDualRegInstr(Mnemonic))(static_cast<void> (0)); | |||
6984 | bool isPredicable = | |||
6985 | Mnemonic == "cx1da" || Mnemonic == "cx2da" || Mnemonic == "cx3da"; | |||
6986 | size_t NumPredOps = isPredicable ? 1 : 0; | |||
6987 | ||||
6988 | if (Operands.size() <= 3 + NumPredOps) | |||
6989 | return false; | |||
6990 | ||||
6991 | StringRef Op2Diag( | |||
6992 | "operand must be an even-numbered register in the range [r0, r10]"); | |||
6993 | ||||
6994 | const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps]; | |||
6995 | if (!Op2.isReg()) | |||
6996 | return Error(Op2.getStartLoc(), Op2Diag); | |||
6997 | ||||
6998 | unsigned RNext; | |||
6999 | unsigned RPair; | |||
7000 | switch (Op2.getReg()) { | |||
7001 | default: | |||
7002 | return Error(Op2.getStartLoc(), Op2Diag); | |||
7003 | case ARM::R0: | |||
7004 | RNext = ARM::R1; | |||
7005 | RPair = ARM::R0_R1; | |||
7006 | break; | |||
7007 | case ARM::R2: | |||
7008 | RNext = ARM::R3; | |||
7009 | RPair = ARM::R2_R3; | |||
7010 | break; | |||
7011 | case ARM::R4: | |||
7012 | RNext = ARM::R5; | |||
7013 | RPair = ARM::R4_R5; | |||
7014 | break; | |||
7015 | case ARM::R6: | |||
7016 | RNext = ARM::R7; | |||
7017 | RPair = ARM::R6_R7; | |||
7018 | break; | |||
7019 | case ARM::R8: | |||
7020 | RNext = ARM::R9; | |||
7021 | RPair = ARM::R8_R9; | |||
7022 | break; | |||
7023 | case ARM::R10: | |||
7024 | RNext = ARM::R11; | |||
7025 | RPair = ARM::R10_R11; | |||
7026 | break; | |||
7027 | } | |||
7028 | ||||
7029 | const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; | |||
7030 | if (!Op3.isReg() || Op3.getReg() != RNext) | |||
7031 | return Error(Op3.getStartLoc(), "operand must be a consecutive register"); | |||
7032 | ||||
7033 | Operands.erase(Operands.begin() + 3 + NumPredOps); | |||
7034 | Operands[2 + NumPredOps] = | |||
7035 | ARMOperand::CreateReg(RPair, Op2.getStartLoc(), Op2.getEndLoc()); | |||
7036 | return false; | |||
7037 | } | |||
7038 | ||||
7039 | /// Parse an arm instruction mnemonic followed by its operands. | |||
7040 | bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, | |||
7041 | SMLoc NameLoc, OperandVector &Operands) { | |||
7042 | MCAsmParser &Parser = getParser(); | |||
7043 | ||||
7044 | // Apply mnemonic aliases before doing anything else, as the destination | |||
7045 | // mnemonic may include suffices and we want to handle them normally. | |||
7046 | // The generic tblgen'erated code does this later, at the start of | |||
7047 | // MatchInstructionImpl(), but that's too late for aliases that include | |||
7048 | // any sort of suffix. | |||
7049 | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); | |||
7050 | unsigned AssemblerDialect = getParser().getAssemblerDialect(); | |||
7051 | applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); | |||
7052 | ||||
7053 | // First check for the ARM-specific .req directive. | |||
7054 | if (Parser.getTok().is(AsmToken::Identifier) && | |||
7055 | Parser.getTok().getIdentifier().lower() == ".req") { | |||
7056 | parseDirectiveReq(Name, NameLoc); | |||
7057 | // We always return 'error' for this, as we're done with this | |||
7058 | // statement and don't need to match the 'instruction." | |||
7059 | return true; | |||
7060 | } | |||
7061 | ||||
7062 | // Create the leading tokens for the mnemonic, split by '.' characters. | |||
7063 | size_t Start = 0, Next = Name.find('.'); | |||
7064 | StringRef Mnemonic = Name.slice(Start, Next); | |||
7065 | StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1)); | |||
7066 | ||||
7067 | // Split out the predication code and carry setting flag from the mnemonic. | |||
7068 | unsigned PredicationCode; | |||
7069 | unsigned VPTPredicationCode; | |||
7070 | unsigned ProcessorIMod; | |||
7071 | bool CarrySetting; | |||
7072 | StringRef ITMask; | |||
7073 | Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode, | |||
7074 | CarrySetting, ProcessorIMod, ITMask); | |||
7075 | ||||
7076 | // In Thumb1, only the branch (B) instruction can be predicated. | |||
7077 | if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { | |||
7078 | return Error(NameLoc, "conditional execution not supported in Thumb1"); | |||
7079 | } | |||
7080 | ||||
7081 | Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); | |||
7082 | ||||
7083 | // Handle the mask for IT and VPT instructions. In ARMOperand and | |||
7084 | // MCOperand, this is stored in a format independent of the | |||
7085 | // condition code: the lowest set bit indicates the end of the | |||
7086 | // encoding, and above that, a 1 bit indicates 'else', and an 0 | |||
7087 | // indicates 'then'. E.g. | |||
7088 | // IT -> 1000 | |||
7089 | // ITx -> x100 (ITT -> 0100, ITE -> 1100) | |||
7090 | // ITxy -> xy10 (e.g. ITET -> 1010) | |||
7091 | // ITxyz -> xyz1 (e.g. ITEET -> 1101) | |||
7092 | // Note: See the ARM::PredBlockMask enum in | |||
7093 | // /lib/Target/ARM/Utils/ARMBaseInfo.h | |||
7094 | if (Mnemonic == "it" || Mnemonic.startswith("vpt") || | |||
7095 | Mnemonic.startswith("vpst")) { | |||
7096 | SMLoc Loc = Mnemonic == "it" ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) : | |||
7097 | Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) : | |||
7098 | SMLoc::getFromPointer(NameLoc.getPointer() + 4); | |||
7099 | if (ITMask.size() > 3) { | |||
7100 | if (Mnemonic == "it") | |||
7101 | return Error(Loc, "too many conditions on IT instruction"); | |||
7102 | return Error(Loc, "too many conditions on VPT instruction"); | |||
7103 | } | |||
7104 | unsigned Mask = 8; | |||
7105 | for (unsigned i = ITMask.size(); i != 0; --i) { | |||
7106 | char pos = ITMask[i - 1]; | |||
7107 | if (pos != 't' && pos != 'e') { | |||
7108 | return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); | |||
7109 | } | |||
7110 | Mask >>= 1; | |||
7111 | if (ITMask[i - 1] == 'e') | |||
7112 | Mask |= 8; | |||
7113 | } | |||
7114 | Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); | |||
7115 | } | |||
7116 | ||||
7117 | // FIXME: This is all a pretty gross hack. We should automatically handle | |||
7118 | // optional operands like this via tblgen. | |||
7119 | ||||
7120 | // Next, add the CCOut and ConditionCode operands, if needed. | |||
7121 | // | |||
7122 | // For mnemonics which can ever incorporate a carry setting bit or predication | |||
7123 | // code, our matching model involves us always generating CCOut and | |||
7124 | // ConditionCode operands to match the mnemonic "as written" and then we let | |||
7125 | // the matcher deal with finding the right instruction or generating an | |||
7126 | // appropriate error. | |||
7127 | bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode; | |||
7128 | getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet, | |||
7129 | CanAcceptPredicationCode, CanAcceptVPTPredicationCode); | |||
7130 | ||||
7131 | // If we had a carry-set on an instruction that can't do that, issue an | |||
7132 | // error. | |||
7133 | if (!CanAcceptCarrySet && CarrySetting) { | |||
7134 | return Error(NameLoc, "instruction '" + Mnemonic + | |||
7135 | "' can not set flags, but 's' suffix specified"); | |||
7136 | } | |||
7137 | // If we had a predication code on an instruction that can't do that, issue an | |||
7138 | // error. | |||
7139 | if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { | |||
7140 | return Error(NameLoc, "instruction '" + Mnemonic + | |||
7141 | "' is not predicable, but condition code specified"); | |||
7142 | } | |||
7143 | ||||
7144 | // If we had a VPT predication code on an instruction that can't do that, issue an | |||
7145 | // error. | |||
7146 | if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) { | |||
7147 | return Error(NameLoc, "instruction '" + Mnemonic + | |||
7148 | "' is not VPT predicable, but VPT code T/E is specified"); | |||
7149 | } | |||
7150 | ||||
7151 | // Add the carry setting operand, if necessary. | |||
7152 | if (CanAcceptCarrySet) { | |||
7153 | SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); | |||
7154 | Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, | |||
7155 | Loc)); | |||
7156 | } | |||
7157 | ||||
7158 | // Add the predication code operand, if necessary. | |||
7159 | if (CanAcceptPredicationCode) { | |||
7160 | SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + | |||
7161 | CarrySetting); | |||
7162 | Operands.push_back(ARMOperand::CreateCondCode( | |||
7163 | ARMCC::CondCodes(PredicationCode), Loc)); | |||
7164 | } | |||
7165 | ||||
7166 | // Add the VPT predication code operand, if necessary. | |||
7167 | // FIXME: We don't add them for the instructions filtered below as these can | |||
7168 | // have custom operands which need special parsing. This parsing requires | |||
7169 | // the operand to be in the same place in the OperandVector as their | |||
7170 | // definition in tblgen. Since these instructions may also have the | |||
7171 | // scalar predication operand we do not add the vector one and leave until | |||
7172 | // now to fix it up. | |||
7173 | if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" && | |||
7174 | !Mnemonic.startswith("vcmp") && | |||
7175 | !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" && | |||
7176 | Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) { | |||
7177 | SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + | |||
7178 | CarrySetting); | |||
7179 | Operands.push_back(ARMOperand::CreateVPTPred( | |||
7180 | ARMVCC::VPTCodes(VPTPredicationCode), Loc)); | |||
7181 | } | |||
7182 | ||||
7183 | // Add the processor imod operand, if necessary. | |||
7184 | if (ProcessorIMod) { | |||
7185 | Operands.push_back(ARMOperand::CreateImm( | |||
7186 | MCConstantExpr::create(ProcessorIMod, getContext()), | |||
7187 | NameLoc, NameLoc)); | |||
7188 | } else if (Mnemonic == "cps" && isMClass()) { | |||
7189 | return Error(NameLoc, "instruction 'cps' requires effect for M-class"); | |||
7190 | } | |||
7191 | ||||
7192 | // Add the remaining tokens in the mnemonic. | |||
7193 | while (Next != StringRef::npos) { | |||
7194 | Start = Next; | |||
7195 | Next = Name.find('.', Start + 1); | |||
7196 | ExtraToken = Name.slice(Start, Next); | |||
7197 | ||||
7198 | // Some NEON instructions have an optional datatype suffix that is | |||
7199 | // completely ignored. Check for that. | |||
7200 | if (isDataTypeToken(ExtraToken) && | |||
7201 | doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) | |||
7202 | continue; | |||
7203 | ||||
7204 | // For for ARM mode generate an error if the .n qualifier is used. | |||
7205 | if (ExtraToken == ".n" && !isThumb()) { | |||
7206 | SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); | |||
7207 | return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " | |||
7208 | "arm mode"); | |||
7209 | } | |||
7210 | ||||
7211 | // The .n qualifier is always discarded as that is what the tables | |||
7212 | // and matcher expect. In ARM mode the .w qualifier has no effect, | |||
7213 | // so discard it to avoid errors that can be caused by the matcher. | |||
7214 | if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { | |||
7215 | SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); | |||
7216 | Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); | |||
7217 | } | |||
7218 | } | |||
7219 | ||||
7220 | // Read the remaining operands. | |||
7221 | if (getLexer().isNot(AsmToken::EndOfStatement)) { | |||
7222 | // Read the first operand. | |||
7223 | if (parseOperand(Operands, Mnemonic)) { | |||
7224 | return true; | |||
7225 | } | |||
7226 | ||||
7227 | while (parseOptionalToken(AsmToken::Comma)) { | |||
7228 | // Parse and remember the operand. | |||
7229 | if (parseOperand(Operands, Mnemonic)) { | |||
7230 | return true; | |||
7231 | } | |||
7232 | } | |||
7233 | } | |||
7234 | ||||
7235 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list")) | |||
7236 | return true; | |||
7237 | ||||
7238 | tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); | |||
7239 | ||||
7240 | if (hasCDE() && MS.isCDEInstr(Mnemonic)) { | |||
7241 | // Dual-register instructions use even-odd register pairs as their | |||
7242 | // destination operand, in assembly such pair is spelled as two | |||
7243 | // consecutive registers, without any special syntax. ConvertDualRegOperand | |||
7244 | // tries to convert such operand into register pair, e.g. r2, r3 -> r2_r3. | |||
7245 | // It returns true, if an error message has been emitted. If the function | |||
7246 | // returns false, the function either succeeded or an error (e.g. missing | |||
7247 | // operand) will be diagnosed elsewhere. | |||
7248 | if (MS.isCDEDualRegInstr(Mnemonic)) { | |||
7249 | bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands); | |||
7250 | if (GotError) | |||
7251 | return GotError; | |||
7252 | } | |||
7253 | } | |||
7254 | ||||
7255 | // Some instructions, mostly Thumb, have forms for the same mnemonic that | |||
7256 | // do and don't have a cc_out optional-def operand. With some spot-checks | |||
7257 | // of the operand list, we can figure out which variant we're trying to | |||
7258 | // parse and adjust accordingly before actually matching. We shouldn't ever | |||
7259 | // try to remove a cc_out operand that was explicitly set on the | |||
7260 | // mnemonic, of course (CarrySetting == true). Reason number #317 the | |||
7261 | // table driven matcher doesn't fit well with the ARM instruction set. | |||
7262 | if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) | |||
7263 | Operands.erase(Operands.begin() + 1); | |||
7264 | ||||
7265 | // Some instructions have the same mnemonic, but don't always | |||
7266 | // have a predicate. Distinguish them here and delete the | |||
7267 | // appropriate predicate if needed. This could be either the scalar | |||
7268 | // predication code or the vector predication code. | |||
7269 | if (PredicationCode == ARMCC::AL && | |||
7270 | shouldOmitPredicateOperand(Mnemonic, Operands)) | |||
7271 | Operands.erase(Operands.begin() + 1); | |||
7272 | ||||
7273 | ||||
7274 | if (hasMVE()) { | |||
7275 | if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) && | |||
7276 | Mnemonic == "vmov" && PredicationCode == ARMCC::LT) { | |||
7277 | // Very nasty hack to deal with the vector predicated variant of vmovlt | |||
7278 | // the scalar predicated vmov with condition 'lt'. We can not tell them | |||
7279 | // apart until we have parsed their operands. | |||
7280 | Operands.erase(Operands.begin() + 1); | |||
7281 | Operands.erase(Operands.begin()); | |||
7282 | SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); | |||
7283 | SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + | |||
7284 | Mnemonic.size() - 1 + CarrySetting); | |||
7285 | Operands.insert(Operands.begin(), | |||
7286 | ARMOperand::CreateVPTPred(ARMVCC::None, PLoc)); | |||
7287 | Operands.insert(Operands.begin(), | |||
7288 | ARMOperand::CreateToken(StringRef("vmovlt"), MLoc)); | |||
7289 | } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE && | |||
7290 | !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { | |||
7291 | // Another nasty hack to deal with the ambiguity between vcvt with scalar | |||
7292 | // predication 'ne' and vcvtn with vector predication 'e'. As above we | |||
7293 | // can only distinguish between the two after we have parsed their | |||
7294 | // operands. | |||
7295 | Operands.erase(Operands.begin() + 1); | |||
7296 | Operands.erase(Operands.begin()); | |||
7297 | SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); | |||
7298 | SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + | |||
7299 | Mnemonic.size() - 1 + CarrySetting); | |||
7300 | Operands.insert(Operands.begin(), | |||
7301 | ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc)); | |||
7302 | Operands.insert(Operands.begin(), | |||
7303 | ARMOperand::CreateToken(StringRef("vcvtn"), MLoc)); | |||
7304 | } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT && | |||
7305 | !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { | |||
7306 | // Another hack, this time to distinguish between scalar predicated vmul | |||
7307 | // with 'lt' predication code and the vector instruction vmullt with | |||
7308 | // vector predication code "none" | |||
7309 | Operands.erase(Operands.begin() + 1); | |||
7310 | Operands.erase(Operands.begin()); | |||
7311 | SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); | |||
7312 | Operands.insert(Operands.begin(), | |||
7313 | ARMOperand::CreateToken(StringRef("vmullt"), MLoc)); | |||
7314 | } | |||
7315 | // For vmov and vcmp, as mentioned earlier, we did not add the vector | |||
7316 | // predication code, since these may contain operands that require | |||
7317 | // special parsing. So now we have to see if they require vector | |||
7318 | // predication and replace the scalar one with the vector predication | |||
7319 | // operand if that is the case. | |||
7320 | else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") || | |||
7321 | (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") && | |||
7322 | !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") && | |||
7323 | !Mnemonic.startswith("vcvtm"))) { | |||
7324 | if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { | |||
7325 | // We could not split the vector predicate off vcvt because it might | |||
7326 | // have been the scalar vcvtt instruction. Now we know its a vector | |||
7327 | // instruction, we still need to check whether its the vector | |||
7328 | // predicated vcvt with 'Then' predication or the vector vcvtt. We can | |||
7329 | // distinguish the two based on the suffixes, if it is any of | |||
7330 | // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt. | |||
7331 | if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) { | |||
7332 | auto Sz1 = static_cast<ARMOperand &>(*Operands[2]); | |||
7333 | auto Sz2 = static_cast<ARMOperand &>(*Operands[3]); | |||
7334 | if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") && | |||
7335 | Sz2.isToken() && Sz2.getToken().startswith(".f"))) { | |||
7336 | Operands.erase(Operands.begin()); | |||
7337 | SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); | |||
7338 | VPTPredicationCode = ARMVCC::Then; | |||
7339 | ||||
7340 | Mnemonic = Mnemonic.substr(0, 4); | |||
7341 | Operands.insert(Operands.begin(), | |||
7342 | ARMOperand::CreateToken(Mnemonic, MLoc)); | |||
7343 | } | |||
7344 | } | |||
7345 | Operands.erase(Operands.begin() + 1); | |||
7346 | SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + | |||
7347 | Mnemonic.size() + CarrySetting); | |||
7348 | Operands.insert(Operands.begin() + 1, | |||
7349 | ARMOperand::CreateVPTPred( | |||
7350 | ARMVCC::VPTCodes(VPTPredicationCode), PLoc)); | |||
7351 | } | |||
7352 | } else if (CanAcceptVPTPredicationCode) { | |||
7353 | // For all other instructions, make sure only one of the two | |||
7354 | // predication operands is left behind, depending on whether we should | |||
7355 | // use the vector predication. | |||
7356 | if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { | |||
7357 | if (CanAcceptPredicationCode) | |||
7358 | Operands.erase(Operands.begin() + 2); | |||
7359 | else | |||
7360 | Operands.erase(Operands.begin() + 1); | |||
7361 | } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) { | |||
7362 | Operands.erase(Operands.begin() + 1); | |||
7363 | } | |||
7364 | } | |||
7365 | } | |||
7366 | ||||
7367 | if (VPTPredicationCode != ARMVCC::None) { | |||
7368 | bool usedVPTPredicationCode = false; | |||
7369 | for (unsigned I = 1; I < Operands.size(); ++I) | |||
7370 | if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) | |||
7371 | usedVPTPredicationCode = true; | |||
7372 | if (!usedVPTPredicationCode) { | |||
7373 | // If we have a VPT predication code and we haven't just turned it | |||
7374 | // into an operand, then it was a mistake for splitMnemonic to | |||
7375 | // separate it from the rest of the mnemonic in the first place, | |||
7376 | // and this may lead to wrong disassembly (e.g. scalar floating | |||
7377 | // point VCMPE is actually a different instruction from VCMP, so | |||
7378 | // we mustn't treat them the same). In that situation, glue it | |||
7379 | // back on. | |||
7380 | Mnemonic = Name.slice(0, Mnemonic.size() + 1); | |||
7381 | Operands.erase(Operands.begin()); | |||
7382 | Operands.insert(Operands.begin(), | |||
7383 | ARMOperand::CreateToken(Mnemonic, NameLoc)); | |||
7384 | } | |||
7385 | } | |||
7386 | ||||
7387 | // ARM mode 'blx' need special handling, as the register operand version | |||
7388 | // is predicable, but the label operand version is not. So, we can't rely | |||
7389 | // on the Mnemonic based checking to correctly figure out when to put | |||
7390 | // a k_CondCode operand in the list. If we're trying to match the label | |||
7391 | // version, remove the k_CondCode operand here. | |||
7392 | if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && | |||
7393 | static_cast<ARMOperand &>(*Operands[2]).isImm()) | |||
7394 | Operands.erase(Operands.begin() + 1); | |||
7395 | ||||
7396 | // Adjust operands of ldrexd/strexd to MCK_GPRPair. | |||
7397 | // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, | |||
7398 | // a single GPRPair reg operand is used in the .td file to replace the two | |||
7399 | // GPRs. However, when parsing from asm, the two GRPs cannot be | |||
7400 | // automatically | |||
7401 | // expressed as a GPRPair, so we have to manually merge them. | |||
7402 | // FIXME: We would really like to be able to tablegen'erate this. | |||
7403 | if (!isThumb() && Operands.size() > 4 && | |||
7404 | (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || | |||
7405 | Mnemonic == "stlexd")) { | |||
7406 | bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); | |||
7407 | unsigned Idx = isLoad ? 2 : 3; | |||
7408 | ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); | |||
7409 | ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); | |||
7410 | ||||
7411 | const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); | |||
7412 | // Adjust only if Op1 and Op2 are GPRs. | |||
7413 | if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && | |||
7414 | MRC.contains(Op2.getReg())) { | |||
7415 | unsigned Reg1 = Op1.getReg(); | |||
7416 | unsigned Reg2 = Op2.getReg(); | |||
7417 | unsigned Rt = MRI->getEncodingValue(Reg1); | |||
7418 | unsigned Rt2 = MRI->getEncodingValue(Reg2); | |||
7419 | ||||
7420 | // Rt2 must be Rt + 1 and Rt must be even. | |||
7421 | if (Rt + 1 != Rt2 || (Rt & 1)) { | |||
7422 | return Error(Op2.getStartLoc(), | |||
7423 | isLoad ? "destination operands must be sequential" | |||
7424 | : "source operands must be sequential"); | |||
7425 | } | |||
7426 | unsigned NewReg = MRI->getMatchingSuperReg( | |||
7427 | Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); | |||
7428 | Operands[Idx] = | |||
7429 | ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); | |||
7430 | Operands.erase(Operands.begin() + Idx + 1); | |||
7431 | } | |||
7432 | } | |||
7433 | ||||
7434 | // GNU Assembler extension (compatibility). | |||
7435 | fixupGNULDRDAlias(Mnemonic, Operands); | |||
7436 | ||||
7437 | // FIXME: As said above, this is all a pretty gross hack. This instruction | |||
7438 | // does not fit with other "subs" and tblgen. | |||
7439 | // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction | |||
7440 | // so the Mnemonic is the original name "subs" and delete the predicate | |||
7441 | // operand so it will match the table entry. | |||
7442 | if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && | |||
7443 | static_cast<ARMOperand &>(*Operands[3]).isReg() && | |||
7444 | static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && | |||
7445 | static_cast<ARMOperand &>(*Operands[4]).isReg() && | |||
7446 | static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && | |||
7447 | static_cast<ARMOperand &>(*Operands[5]).isImm()) { | |||
7448 | Operands.front() = ARMOperand::CreateToken(Name, NameLoc); | |||
7449 | Operands.erase(Operands.begin() + 1); | |||
7450 | } | |||
7451 | return false; | |||
7452 | } | |||
7453 | ||||
7454 | // Validate context-sensitive operand constraints. | |||
7455 | ||||
7456 | // return 'true' if register list contains non-low GPR registers, | |||
7457 | // 'false' otherwise. If Reg is in the register list or is HiReg, set | |||
7458 | // 'containsReg' to true. | |||
7459 | static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, | |||
7460 | unsigned Reg, unsigned HiReg, | |||
7461 | bool &containsReg) { | |||
7462 | containsReg = false; | |||
7463 | for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { | |||
7464 | unsigned OpReg = Inst.getOperand(i).getReg(); | |||
7465 | if (OpReg == Reg) | |||
7466 | containsReg = true; | |||
7467 | // Anything other than a low register isn't legal here. | |||
7468 | if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) | |||
7469 | return true; | |||
7470 | } | |||
7471 | return false; | |||
7472 | } | |||
7473 | ||||
7474 | // Check if the specified regisgter is in the register list of the inst, | |||
7475 | // starting at the indicated operand number. | |||
7476 | static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { | |||
7477 | for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) { | |||
7478 | unsigned OpReg = Inst.getOperand(i).getReg(); | |||
7479 | if (OpReg == Reg) | |||
7480 | return true; | |||
7481 | } | |||
7482 | return false; | |||
7483 | } | |||
7484 | ||||
7485 | // Return true if instruction has the interesting property of being | |||
7486 | // allowed in IT blocks, but not being predicable. | |||
7487 | static bool instIsBreakpoint(const MCInst &Inst) { | |||
7488 | return Inst.getOpcode() == ARM::tBKPT || | |||
7489 | Inst.getOpcode() == ARM::BKPT || | |||
7490 | Inst.getOpcode() == ARM::tHLT || | |||
7491 | Inst.getOpcode() == ARM::HLT; | |||
7492 | } | |||
7493 | ||||
7494 | bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, | |||
7495 | const OperandVector &Operands, | |||
7496 | unsigned ListNo, bool IsARPop) { | |||
7497 | const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); | |||
7498 | bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; | |||
7499 | ||||
7500 | bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); | |||
7501 | bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); | |||
7502 | bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); | |||
7503 | ||||
7504 | if (!IsARPop && ListContainsSP) | |||
7505 | return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), | |||
7506 | "SP may not be in the register list"); | |||
7507 | else if (ListContainsPC && ListContainsLR) | |||
7508 | return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), | |||
7509 | "PC and LR may not be in the register list simultaneously"); | |||
7510 | return false; | |||
7511 | } | |||
7512 | ||||
7513 | bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, | |||
7514 | const OperandVector &Operands, | |||
7515 | unsigned ListNo) { | |||
7516 | const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); | |||
7517 | bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; | |||
7518 | ||||
7519 | bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); | |||
7520 | bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); | |||
7521 | ||||
7522 | if (ListContainsSP && ListContainsPC) | |||
7523 | return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), | |||
7524 | "SP and PC may not be in the register list"); | |||
7525 | else if (ListContainsSP) | |||
7526 | return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), | |||
7527 | "SP may not be in the register list"); | |||
7528 | else if (ListContainsPC) | |||
7529 | return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), | |||
7530 | "PC may not be in the register list"); | |||
7531 | return false; | |||
7532 | } | |||
7533 | ||||
7534 | bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, | |||
7535 | const OperandVector &Operands, | |||
7536 | bool Load, bool ARMMode, bool Writeback) { | |||
7537 | unsigned RtIndex = Load || !Writeback ? 0 : 1; | |||
7538 | unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); | |||
7539 | unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); | |||
7540 | ||||
7541 | if (ARMMode) { | |||
7542 | // Rt can't be R14. | |||
7543 | if (Rt == 14) | |||
7544 | return Error(Operands[3]->getStartLoc(), | |||
7545 | "Rt can't be R14"); | |||
7546 | ||||
7547 | // Rt must be even-numbered. | |||
7548 | if ((Rt & 1) == 1) | |||
7549 | return Error(Operands[3]->getStartLoc(), | |||
7550 | "Rt must be even-numbered"); | |||
7551 | ||||
7552 | // Rt2 must be Rt + 1. | |||
7553 | if (Rt2 != Rt + 1) { | |||
7554 | if (Load) | |||
7555 | return Error(Operands[3]->getStartLoc(), | |||
7556 | "destination operands must be sequential"); | |||
7557 | else | |||
7558 | return Error(Operands[3]->getStartLoc(), | |||
7559 | "source operands must be sequential"); | |||
7560 | } | |||
7561 | ||||
7562 | // FIXME: Diagnose m == 15 | |||
7563 | // FIXME: Diagnose ldrd with m == t || m == t2. | |||
7564 | } | |||
7565 | ||||
7566 | if (!ARMMode && Load) { | |||
7567 | if (Rt2 == Rt) | |||
7568 | return Error(Operands[3]->getStartLoc(), | |||
7569 | "destination operands can't be identical"); | |||
7570 | } | |||
7571 | ||||
7572 | if (Writeback) { | |||
7573 | unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); | |||
7574 | ||||
7575 | if (Rn == Rt || Rn == Rt2) { | |||
7576 | if (Load) | |||
7577 | return Error(Operands[3]->getStartLoc(), | |||
7578 | "base register needs to be different from destination " | |||
7579 | "registers"); | |||
7580 | else | |||
7581 | return Error(Operands[3]->getStartLoc(), | |||
7582 | "source register and base register can't be identical"); | |||
7583 | } | |||
7584 | ||||
7585 | // FIXME: Diagnose ldrd/strd with writeback and n == 15. | |||
7586 | // (Except the immediate form of ldrd?) | |||
7587 | } | |||
7588 | ||||
7589 | return false; | |||
7590 | } | |||
7591 | ||||
7592 | static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) { | |||
7593 | for (unsigned i = 0; i < MCID.NumOperands; ++i) { | |||
7594 | if (ARM::isVpred(MCID.OpInfo[i].OperandType)) | |||
7595 | return i; | |||
7596 | } | |||
7597 | return -1; | |||
7598 | } | |||
7599 | ||||
7600 | static bool isVectorPredicable(const MCInstrDesc &MCID) { | |||
7601 | return findFirstVectorPredOperandIdx(MCID) != -1; | |||
7602 | } | |||
7603 | ||||
7604 | // FIXME: We would really like to be able to tablegen'erate this. | |||
7605 | bool ARMAsmParser::validateInstruction(MCInst &Inst, | |||
7606 | const OperandVector &Operands) { | |||
7607 | const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); | |||
7608 | SMLoc Loc = Operands[0]->getStartLoc(); | |||
7609 | ||||
7610 | // Check the IT block state first. | |||
7611 | // NOTE: BKPT and HLT instructions have the interesting property of being | |||
7612 | // allowed in IT blocks, but not being predicable. They just always execute. | |||
7613 | if (inITBlock() && !instIsBreakpoint(Inst)) { | |||
7614 | // The instruction must be predicable. | |||
7615 | if (!MCID.isPredicable()) | |||
7616 | return Error(Loc, "instructions in IT block must be predicable"); | |||
7617 | ARMCC::CondCodes Cond = ARMCC::CondCodes( | |||
7618 | Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm()); | |||
7619 | if (Cond != currentITCond()) { | |||
7620 | // Find the condition code Operand to get its SMLoc information. | |||
7621 | SMLoc CondLoc; | |||
7622 | for (unsigned I = 1; I < Operands.size(); ++I) | |||
7623 | if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) | |||
7624 | CondLoc = Operands[I]->getStartLoc(); | |||
7625 | return Error(CondLoc, "incorrect condition in IT block; got '" + | |||
7626 | StringRef(ARMCondCodeToString(Cond)) + | |||
7627 | "', but expected '" + | |||
7628 | ARMCondCodeToString(currentITCond()) + "'"); | |||
7629 | } | |||
7630 | // Check for non-'al' condition codes outside of the IT block. | |||
7631 | } else if (isThumbTwo() && MCID.isPredicable() && | |||
7632 | Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != | |||
7633 | ARMCC::AL && Inst.getOpcode() != ARM::tBcc && | |||
7634 | Inst.getOpcode() != ARM::t2Bcc && | |||
7635 | Inst.getOpcode() != ARM::t2BFic) { | |||
7636 | return Error(Loc, "predicated instructions must be in IT block"); | |||
7637 | } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() && | |||
7638 | Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != | |||
7639 | ARMCC::AL) { | |||
7640 | return Warning(Loc, "predicated instructions should be in IT block"); | |||
7641 | } else if (!MCID.isPredicable()) { | |||
7642 | // Check the instruction doesn't have a predicate operand anyway | |||
7643 | // that it's not allowed to use. Sometimes this happens in order | |||
7644 | // to keep instructions the same shape even though one cannot | |||
7645 | // legally be predicated, e.g. vmul.f16 vs vmul.f32. | |||
7646 | for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { | |||
7647 | if (MCID.OpInfo[i].isPredicate()) { | |||
7648 | if (Inst.getOperand(i).getImm() != ARMCC::AL) | |||
7649 | return Error(Loc, "instruction is not predicable"); | |||
7650 | break; | |||
7651 | } | |||
7652 | } | |||
7653 | } | |||
7654 | ||||
7655 | // PC-setting instructions in an IT block, but not the last instruction of | |||
7656 | // the block, are UNPREDICTABLE. | |||
7657 | if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) { | |||
7658 | return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block"); | |||
7659 | } | |||
7660 | ||||
7661 | if (inVPTBlock() && !instIsBreakpoint(Inst)) { | |||
7662 | unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition); | |||
7663 | if (!isVectorPredicable(MCID)) | |||
7664 | return Error(Loc, "instruction in VPT block must be predicable"); | |||
7665 | unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm(); | |||
7666 | unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then; | |||
7667 | if (Pred != VPTPred) { | |||
7668 | SMLoc PredLoc; | |||
7669 | for (unsigned I = 1; I < Operands.size(); ++I) | |||
7670 | if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) | |||
7671 | PredLoc = Operands[I]->getStartLoc(); | |||
7672 | return Error(PredLoc, "incorrect predication in VPT block; got '" + | |||
7673 | StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) + | |||
7674 | "', but expected '" + | |||
7675 | ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'"); | |||
7676 | } | |||
7677 | } | |||
7678 | else if (isVectorPredicable(MCID) && | |||
7679 | Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() != | |||
7680 | ARMVCC::None) | |||
7681 | return Error(Loc, "VPT predicated instructions must be in VPT block"); | |||
7682 | ||||
7683 | const unsigned Opcode = Inst.getOpcode(); | |||
7684 | switch (Opcode) { | |||
7685 | case ARM::t2IT: { | |||
7686 | // Encoding is unpredictable if it ever results in a notional 'NV' | |||
7687 | // predicate. Since we don't parse 'NV' directly this means an 'AL' | |||
7688 | // predicate with an "else" mask bit. | |||
7689 | unsigned Cond = Inst.getOperand(0).getImm(); | |||
7690 | unsigned Mask = Inst.getOperand(1).getImm(); | |||
7691 | ||||
7692 | // Conditions only allowing a 't' are those with no set bit except | |||
7693 | // the lowest-order one that indicates the end of the sequence. In | |||
7694 | // other words, powers of 2. | |||
7695 | if (Cond == ARMCC::AL && countPopulation(Mask) != 1) | |||
7696 | return Error(Loc, "unpredictable IT predicate sequence"); | |||
7697 | break; | |||
7698 | } | |||
7699 | case ARM::LDRD: | |||
7700 | if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, | |||
7701 | /*Writeback*/false)) | |||
7702 | return true; | |||
7703 | break; | |||
7704 | case ARM::LDRD_PRE: | |||
7705 | case ARM::LDRD_POST: | |||
7706 | if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, | |||
7707 | /*Writeback*/true)) | |||
7708 | return true; | |||
7709 | break; | |||
7710 | case ARM::t2LDRDi8: | |||
7711 | if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, | |||
7712 | /*Writeback*/false)) | |||
7713 | return true; | |||
7714 | break; | |||
7715 | case ARM::t2LDRD_PRE: | |||
7716 | case ARM::t2LDRD_POST: | |||
7717 | if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, | |||
7718 | /*Writeback*/true)) | |||
7719 | return true; | |||
7720 | break; | |||
7721 | case ARM::t2BXJ: { | |||
7722 | const unsigned RmReg = Inst.getOperand(0).getReg(); | |||
7723 | // Rm = SP is no longer unpredictable in v8-A | |||
7724 | if (RmReg == ARM::SP && !hasV8Ops()) | |||
7725 | return Error(Operands[2]->getStartLoc(), | |||
7726 | "r13 (SP) is an unpredictable operand to BXJ"); | |||
7727 | return false; | |||
7728 | } | |||
7729 | case ARM::STRD: | |||
7730 | if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, | |||
7731 | /*Writeback*/false)) | |||
7732 | return true; | |||
7733 | break; | |||
7734 | case ARM::STRD_PRE: | |||
7735 | case ARM::STRD_POST: | |||
7736 | if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, | |||
7737 | /*Writeback*/true)) | |||
7738 | return true; | |||
7739 | break; | |||
7740 | case ARM::t2STRD_PRE: | |||
7741 | case ARM::t2STRD_POST: | |||
7742 | if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, | |||
7743 | /*Writeback*/true)) | |||
7744 | return true; | |||
7745 | break; | |||
7746 | case ARM::STR_PRE_IMM: | |||
7747 | case ARM::STR_PRE_REG: | |||
7748 | case ARM::t2STR_PRE: | |||
7749 | case ARM::STR_POST_IMM: | |||
7750 | case ARM::STR_POST_REG: | |||
7751 | case ARM::t2STR_POST: | |||
7752 | case ARM::STRH_PRE: | |||
7753 | case ARM::t2STRH_PRE: | |||
7754 | case ARM::STRH_POST: | |||
7755 | case ARM::t2STRH_POST: | |||
7756 | case ARM::STRB_PRE_IMM: | |||
7757 | case ARM::STRB_PRE_REG: | |||
7758 | case ARM::t2STRB_PRE: | |||
7759 | case ARM::STRB_POST_IMM: | |||
7760 | case ARM::STRB_POST_REG: | |||
7761 | case ARM::t2STRB_POST: { | |||
7762 | // Rt must be different from Rn. | |||
7763 | const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); | |||
7764 | const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); | |||
7765 | ||||
7766 | if (Rt == Rn) | |||
7767 | return Error(Operands[3]->getStartLoc(), | |||
7768 | "source register and base register can't be identical"); | |||
7769 | return false; | |||
7770 | } | |||
7771 | case ARM::t2LDR_PRE_imm: | |||
7772 | case ARM::t2LDR_POST_imm: | |||
7773 | case ARM::t2STR_PRE_imm: | |||
7774 | case ARM::t2STR_POST_imm: { | |||
7775 | // Rt must be different from Rn. | |||
7776 | const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); | |||
7777 | const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg()); | |||
7778 | ||||
7779 | if (Rt == Rn) | |||
7780 | return Error(Operands[3]->getStartLoc(), | |||
7781 | "destination register and base register can't be identical"); | |||
7782 | if (Inst.getOpcode() == ARM::t2LDR_POST_imm || | |||
7783 | Inst.getOpcode() == ARM::t2STR_POST_imm) { | |||
7784 | int Imm = Inst.getOperand(2).getImm(); | |||
7785 | if (Imm > 255 || Imm < -255) | |||
7786 | return Error(Operands[5]->getStartLoc(), | |||
7787 | "operand must be in range [-255, 255]"); | |||
7788 | } | |||
7789 | if (Inst.getOpcode() == ARM::t2STR_PRE_imm || | |||
7790 | Inst.getOpcode() == ARM::t2STR_POST_imm) { | |||
7791 | if (Inst.getOperand(0).getReg() == ARM::PC) { | |||
7792 | return Error(Operands[3]->getStartLoc(), | |||
7793 | "operand must be a register in range [r0, r14]"); | |||
7794 | } | |||
7795 | } | |||
7796 | return false; | |||
7797 | } | |||
7798 | case ARM::LDR_PRE_IMM: | |||
7799 | case ARM::LDR_PRE_REG: | |||
7800 | case ARM::t2LDR_PRE: | |||
7801 | case ARM::LDR_POST_IMM: | |||
7802 | case ARM::LDR_POST_REG: | |||
7803 | case ARM::t2LDR_POST: | |||
7804 | case ARM::LDRH_PRE: | |||
7805 | case ARM::t2LDRH_PRE: | |||
7806 | case ARM::LDRH_POST: | |||
7807 | case ARM::t2LDRH_POST: | |||
7808 | case ARM::LDRSH_PRE: | |||
7809 | case ARM::t2LDRSH_PRE: | |||
7810 | case ARM::LDRSH_POST: | |||
7811 | case ARM::t2LDRSH_POST: | |||
7812 | case ARM::LDRB_PRE_IMM: | |||
7813 | case ARM::LDRB_PRE_REG: | |||
7814 | case ARM::t2LDRB_PRE: | |||
7815 | case ARM::LDRB_POST_IMM: | |||
7816 | case ARM::LDRB_POST_REG: | |||
7817 | case ARM::t2LDRB_POST: | |||
7818 | case ARM::LDRSB_PRE: | |||
7819 | case ARM::t2LDRSB_PRE: | |||
7820 | case ARM::LDRSB_POST: | |||
7821 | case ARM::t2LDRSB_POST: { | |||
7822 | // Rt must be different from Rn. | |||
7823 | const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); | |||
7824 | const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); | |||
7825 | ||||
7826 | if (Rt == Rn) | |||
7827 | return Error(Operands[3]->getStartLoc(), | |||
7828 | "destination register and base register can't be identical"); | |||
7829 | return false; | |||
7830 | } | |||
7831 | ||||
7832 | case ARM::MVE_VLDRBU8_rq: | |||
7833 | case ARM::MVE_VLDRBU16_rq: | |||
7834 | case ARM::MVE_VLDRBS16_rq: | |||
7835 | case ARM::MVE_VLDRBU32_rq: | |||
7836 | case ARM::MVE_VLDRBS32_rq: | |||
7837 | case ARM::MVE_VLDRHU16_rq: | |||
7838 | case ARM::MVE_VLDRHU16_rq_u: | |||
7839 | case ARM::MVE_VLDRHU32_rq: | |||
7840 | case ARM::MVE_VLDRHU32_rq_u: | |||
7841 | case ARM::MVE_VLDRHS32_rq: | |||
7842 | case ARM::MVE_VLDRHS32_rq_u: | |||
7843 | case ARM::MVE_VLDRWU32_rq: | |||
7844 | case ARM::MVE_VLDRWU32_rq_u: | |||
7845 | case ARM::MVE_VLDRDU64_rq: | |||
7846 | case ARM::MVE_VLDRDU64_rq_u: | |||
7847 | case ARM::MVE_VLDRWU32_qi: | |||
7848 | case ARM::MVE_VLDRWU32_qi_pre: | |||
7849 | case ARM::MVE_VLDRDU64_qi: | |||
7850 | case ARM::MVE_VLDRDU64_qi_pre: { | |||
7851 | // Qd must be different from Qm. | |||
7852 | unsigned QdIdx = 0, QmIdx = 2; | |||
7853 | bool QmIsPointer = false; | |||
7854 | switch (Opcode) { | |||
7855 | case ARM::MVE_VLDRWU32_qi: | |||
7856 | case ARM::MVE_VLDRDU64_qi: | |||
7857 | QmIdx = 1; | |||
7858 | QmIsPointer = true; | |||
7859 | break; | |||
7860 | case ARM::MVE_VLDRWU32_qi_pre: | |||
7861 | case ARM::MVE_VLDRDU64_qi_pre: | |||
7862 | QdIdx = 1; | |||
7863 | QmIsPointer = true; | |||
7864 | break; | |||
7865 | } | |||
7866 | ||||
7867 | const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); | |||
7868 | const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); | |||
7869 | ||||
7870 | if (Qd == Qm) { | |||
7871 | return Error(Operands[3]->getStartLoc(), | |||
7872 | Twine("destination vector register and vector ") + | |||
7873 | (QmIsPointer ? "pointer" : "offset") + | |||
7874 | " register can't be identical"); | |||
7875 | } | |||
7876 | return false; | |||
7877 | } | |||
7878 | ||||
7879 | case ARM::SBFX: | |||
7880 | case ARM::t2SBFX: | |||
7881 | case ARM::UBFX: | |||
7882 | case ARM::t2UBFX: { | |||
7883 | // Width must be in range [1, 32-lsb]. | |||
7884 | unsigned LSB = Inst.getOperand(2).getImm(); | |||
7885 | unsigned Widthm1 = Inst.getOperand(3).getImm(); | |||
7886 | if (Widthm1 >= 32 - LSB) | |||
7887 | return Error(Operands[5]->getStartLoc(), | |||
7888 | "bitfield width must be in range [1,32-lsb]"); | |||
7889 | return false; | |||
7890 | } | |||
7891 | // Notionally handles ARM::tLDMIA_UPD too. | |||
7892 | case ARM::tLDMIA: { | |||
7893 | // If we're parsing Thumb2, the .w variant is available and handles | |||
7894 | // most cases that are normally illegal for a Thumb1 LDM instruction. | |||
7895 | // We'll make the transformation in processInstruction() if necessary. | |||
7896 | // | |||
7897 | // Thumb LDM instructions are writeback iff the base register is not | |||
7898 | // in the register list. | |||
7899 | unsigned Rn = Inst.getOperand(0).getReg(); | |||
7900 | bool HasWritebackToken = | |||
7901 | (static_cast<ARMOperand &>(*Operands[3]).isToken() && | |||
7902 | static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); | |||
7903 | bool ListContainsBase; | |||
7904 | if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) | |||
7905 | return Error(Operands[3 + HasWritebackToken]->getStartLoc(), | |||
7906 | "registers must be in range r0-r7"); | |||
7907 | // If we should have writeback, then there should be a '!' token. | |||
7908 | if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) | |||
7909 | return Error(Operands[2]->getStartLoc(), | |||
7910 | "writeback operator '!' expected"); | |||
7911 | // If we should not have writeback, there must not be a '!'. This is | |||
7912 | // true even for the 32-bit wide encodings. | |||
7913 | if (ListContainsBase && HasWritebackToken) | |||
7914 | return Error(Operands[3]->getStartLoc(), | |||
7915 | "writeback operator '!' not allowed when base register " | |||
7916 | "in register list"); | |||
7917 | ||||
7918 | if (validatetLDMRegList(Inst, Operands, 3)) | |||
7919 | return true; | |||
7920 | break; | |||
7921 | } | |||
7922 | case ARM::LDMIA_UPD: | |||
7923 | case ARM::LDMDB_UPD: | |||
7924 | case ARM::LDMIB_UPD: | |||
7925 | case ARM::LDMDA_UPD: | |||
7926 | // ARM variants loading and updating the same register are only officially | |||
7927 | // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. | |||
7928 | if (!hasV7Ops()) | |||
7929 | break; | |||
7930 | if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) | |||
7931 | return Error(Operands.back()->getStartLoc(), | |||
7932 | "writeback register not allowed in register list"); | |||
7933 | break; | |||
7934 | case ARM::t2LDMIA: | |||
7935 | case ARM::t2LDMDB: | |||
7936 | if (validatetLDMRegList(Inst, Operands, 3)) | |||
7937 | return true; | |||
7938 | break; | |||
7939 | case ARM::t2STMIA: | |||
7940 | case ARM::t2STMDB: | |||
7941 | if (validatetSTMRegList(Inst, Operands, 3)) | |||
7942 | return true; | |||
7943 | break; | |||
7944 | case ARM::t2LDMIA_UPD: | |||
7945 | case ARM::t2LDMDB_UPD: | |||
7946 | case ARM::t2STMIA_UPD: | |||
7947 | case ARM::t2STMDB_UPD: | |||
7948 | if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) | |||
7949 | return Error(Operands.back()->getStartLoc(), | |||
7950 | "writeback register not allowed in register list"); | |||
7951 | ||||
7952 | if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { | |||
7953 | if (validatetLDMRegList(Inst, Operands, 3)) | |||
7954 | return true; | |||
7955 | } else { | |||
7956 | if (validatetSTMRegList(Inst, Operands, 3)) | |||
7957 | return true; | |||
7958 | } | |||
7959 | break; | |||
7960 | ||||
7961 | case ARM::sysLDMIA_UPD: | |||
7962 | case ARM::sysLDMDA_UPD: | |||
7963 | case ARM::sysLDMDB_UPD: | |||
7964 | case ARM::sysLDMIB_UPD: | |||
7965 | if (!listContainsReg(Inst, 3, ARM::PC)) | |||
7966 | return Error(Operands[4]->getStartLoc(), | |||
7967 | "writeback register only allowed on system LDM " | |||
7968 | "if PC in register-list"); | |||
7969 | break; | |||
7970 | case ARM::sysSTMIA_UPD: | |||
7971 | case ARM::sysSTMDA_UPD: | |||
7972 | case ARM::sysSTMDB_UPD: | |||
7973 | case ARM::sysSTMIB_UPD: | |||
7974 | return Error(Operands[2]->getStartLoc(), | |||
7975 | "system STM cannot have writeback register"); | |||
7976 | case ARM::tMUL: | |||
7977 | // The second source operand must be the same register as the destination | |||
7978 | // operand. | |||
7979 | // | |||
7980 | // In this case, we must directly check the parsed operands because the | |||
7981 | // cvtThumbMultiply() function is written in such a way that it guarantees | |||
7982 | // this first statement is always true for the new Inst. Essentially, the | |||
7983 | // destination is unconditionally copied into the second source operand | |||
7984 | // without checking to see if it matches what we actually parsed. | |||
7985 | if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != | |||
7986 | ((ARMOperand &)*Operands[5]).getReg()) && | |||
7987 | (((ARMOperand &)*Operands[3]).getReg() != | |||
7988 | ((ARMOperand &)*Operands[4]).getReg())) { | |||
7989 | return Error(Operands[3]->getStartLoc(), | |||
7990 | "destination register must match source register"); | |||
7991 | } | |||
7992 | break; | |||
7993 | ||||
7994 | // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, | |||
7995 | // so only issue a diagnostic for thumb1. The instructions will be | |||
7996 | // switched to the t2 encodings in processInstruction() if necessary. | |||
7997 | case ARM::tPOP: { | |||
7998 | bool ListContainsBase; | |||
7999 | if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && | |||
8000 | !isThumbTwo()) | |||
8001 | return Error(Operands[2]->getStartLoc(), | |||
8002 | "registers must be in range r0-r7 or pc"); | |||
8003 | if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) | |||
8004 | return true; | |||
8005 | break; | |||
8006 | } | |||
8007 | case ARM::tPUSH: { | |||
8008 | bool ListContainsBase; | |||
8009 | if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && | |||
8010 | !isThumbTwo()) | |||
8011 | return Error(Operands[2]->getStartLoc(), | |||
8012 | "registers must be in range r0-r7 or lr"); | |||
8013 | if (validatetSTMRegList(Inst, Operands, 2)) | |||
8014 | return true; | |||
8015 | break; | |||
8016 | } | |||
8017 | case ARM::tSTMIA_UPD: { | |||
8018 | bool ListContainsBase, InvalidLowList; | |||
8019 | InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), | |||
8020 | 0, ListContainsBase); | |||
8021 | if (InvalidLowList && !isThumbTwo()) | |||
8022 | return Error(Operands[4]->getStartLoc(), | |||
8023 | "registers must be in range r0-r7"); | |||
8024 | ||||
8025 | // This would be converted to a 32-bit stm, but that's not valid if the | |||
8026 | // writeback register is in the list. | |||
8027 | if (InvalidLowList && ListContainsBase) | |||
8028 | return Error(Operands[4]->getStartLoc(), | |||
8029 | "writeback operator '!' not allowed when base register " | |||
8030 | "in register list"); | |||
8031 | ||||
8032 | if (validatetSTMRegList(Inst, Operands, 4)) | |||
8033 | return true; | |||
8034 | break; | |||
8035 | } | |||
8036 | case ARM::tADDrSP: | |||
8037 | // If the non-SP source operand and the destination operand are not the | |||
8038 | // same, we need thumb2 (for the wide encoding), or we have an error. | |||
8039 | if (!isThumbTwo() && | |||
8040 | Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { | |||
8041 | return Error(Operands[4]->getStartLoc(), | |||
8042 | "source register must be the same as destination"); | |||
8043 | } | |||
8044 | break; | |||
8045 | ||||
8046 | case ARM::t2ADDrr: | |||
8047 | case ARM::t2ADDrs: | |||
8048 | case ARM::t2SUBrr: | |||
8049 | case ARM::t2SUBrs: | |||
8050 | if (Inst.getOperand(0).getReg() == ARM::SP && | |||
8051 | Inst.getOperand(1).getReg() != ARM::SP) | |||
8052 | return Error(Operands[4]->getStartLoc(), | |||
8053 | "source register must be sp if destination is sp"); | |||
8054 | break; | |||
8055 | ||||
8056 | // Final range checking for Thumb unconditional branch instructions. | |||
8057 | case ARM::tB: | |||
8058 | if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) | |||
8059 | return Error(Operands[2]->getStartLoc(), "branch target out of range"); | |||
8060 | break; | |||
8061 | case ARM::t2B: { | |||
8062 | int op = (Operands[2]->isImm()) ? 2 : 3; | |||
8063 | ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]); | |||
8064 | // Delay the checks of symbolic expressions until they are resolved. | |||
8065 | if (!isa<MCBinaryExpr>(Operand.getImm()) && | |||
8066 | !Operand.isSignedOffset<24, 1>()) | |||
8067 | return Error(Operands[op]->getStartLoc(), "branch target out of range"); | |||
8068 | break; | |||
8069 | } | |||
8070 | // Final range checking for Thumb conditional branch instructions. | |||
8071 | case ARM::tBcc: | |||
8072 | if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) | |||
8073 | return Error(Operands[2]->getStartLoc(), "branch target out of range"); | |||
8074 | break; | |||
8075 | case ARM::t2Bcc: { | |||
8076 | int Op = (Operands[2]->isImm()) ? 2 : 3; | |||
8077 | if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) | |||
8078 | return Error(Operands[Op]->getStartLoc(), "branch target out of range"); | |||
8079 | break; | |||
8080 | } | |||
8081 | case ARM::tCBZ: | |||
8082 | case ARM::tCBNZ: { | |||
8083 | if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) | |||
8084 | return Error(Operands[2]->getStartLoc(), "branch target out of range"); | |||
8085 | break; | |||
8086 | } | |||
8087 | case ARM::MOVi16: | |||
8088 | case ARM::MOVTi16: | |||
8089 | case ARM::t2MOVi16: | |||
8090 | case ARM::t2MOVTi16: | |||
8091 | { | |||
8092 | // We want to avoid misleadingly allowing something like "mov r0, <symbol>" | |||
8093 | // especially when we turn it into a movw and the expression <symbol> does | |||
8094 | // not have a :lower16: or :upper16 as part of the expression. We don't | |||
8095 | // want the behavior of silently truncating, which can be unexpected and | |||
8096 | // lead to bugs that are difficult to find since this is an easy mistake | |||
8097 | // to make. | |||
8098 | int i = (Operands[3]->isImm()) ? 3 : 4; | |||
8099 | ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); | |||
8100 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()); | |||
8101 | if (CE) break; | |||
8102 | const MCExpr *E = dyn_cast<MCExpr>(Op.getImm()); | |||
8103 | if (!E) break; | |||
8104 | const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E); | |||
8105 | if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && | |||
8106 | ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) | |||
8107 | return Error( | |||
8108 | Op.getStartLoc(), | |||
8109 | "immediate expression for mov requires :lower16: or :upper16"); | |||
8110 | break; | |||
8111 | } | |||
8112 | case ARM::HINT: | |||
8113 | case ARM::t2HINT: { | |||
8114 | unsigned Imm8 = Inst.getOperand(0).getImm(); | |||
8115 | unsigned Pred = Inst.getOperand(1).getImm(); | |||
8116 | // ESB is not predicable (pred must be AL). Without the RAS extension, this | |||
8117 | // behaves as any other unallocated hint. | |||
8118 | if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS()) | |||
8119 | return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " | |||
8120 | "predicable, but condition " | |||
8121 | "code specified"); | |||
8122 | if (Imm8 == 0x14 && Pred != ARMCC::AL) | |||
8123 | return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " | |||
8124 | "predicable, but condition " | |||
8125 | "code specified"); | |||
8126 | break; | |||
8127 | } | |||
8128 | case ARM::t2BFi: | |||
8129 | case ARM::t2BFr: | |||
8130 | case ARM::t2BFLi: | |||
8131 | case ARM::t2BFLr: { | |||
8132 | if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || | |||
8133 | (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) | |||
8134 | return Error(Operands[2]->getStartLoc(), | |||
8135 | "branch location out of range or not a multiple of 2"); | |||
8136 | ||||
8137 | if (Opcode == ARM::t2BFi) { | |||
8138 | if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) | |||
8139 | return Error(Operands[3]->getStartLoc(), | |||
8140 | "branch target out of range or not a multiple of 2"); | |||
8141 | } else if (Opcode == ARM::t2BFLi) { | |||
8142 | if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) | |||
8143 | return Error(Operands[3]->getStartLoc(), | |||
8144 | "branch target out of range or not a multiple of 2"); | |||
8145 | } | |||
8146 | break; | |||
8147 | } | |||
8148 | case ARM::t2BFic: { | |||
8149 | if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || | |||
8150 | (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) | |||
8151 | return Error(Operands[1]->getStartLoc(), | |||
8152 | "branch location out of range or not a multiple of 2"); | |||
8153 | ||||
8154 | if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) | |||
8155 | return Error(Operands[2]->getStartLoc(), | |||
8156 | "branch target out of range or not a multiple of 2"); | |||
8157 | ||||
8158 | assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&(static_cast<void> (0)) | |||
8159 | "branch location and else branch target should either both be "(static_cast<void> (0)) | |||
8160 | "immediates or both labels")(static_cast<void> (0)); | |||
8161 | ||||
8162 | if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) { | |||
8163 | int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm(); | |||
8164 | if (Diff != 4 && Diff != 2) | |||
8165 | return Error( | |||
8166 | Operands[3]->getStartLoc(), | |||
8167 | "else branch target must be 2 or 4 greater than the branch location"); | |||
8168 | } | |||
8169 | break; | |||
8170 | } | |||
8171 | case ARM::t2CLRM: { | |||
8172 | for (unsigned i = 2; i < Inst.getNumOperands(); i++) { | |||
8173 | if (Inst.getOperand(i).isReg() && | |||
8174 | !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains( | |||
8175 | Inst.getOperand(i).getReg())) { | |||
8176 | return Error(Operands[2]->getStartLoc(), | |||
8177 | "invalid register in register list. Valid registers are " | |||
8178 | "r0-r12, lr/r14 and APSR."); | |||
8179 | } | |||
8180 | } | |||
8181 | break; | |||
8182 | } | |||
8183 | case ARM::DSB: | |||
8184 | case ARM::t2DSB: { | |||
8185 | ||||
8186 | if (Inst.getNumOperands() < 2) | |||
8187 | break; | |||
8188 | ||||
8189 | unsigned Option = Inst.getOperand(0).getImm(); | |||
8190 | unsigned Pred = Inst.getOperand(1).getImm(); | |||
8191 | ||||
8192 | // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL). | |||
8193 | if (Option == 0 && Pred != ARMCC::AL) | |||
8194 | return Error(Operands[1]->getStartLoc(), | |||
8195 | "instruction 'ssbb' is not predicable, but condition code " | |||
8196 | "specified"); | |||
8197 | if (Option == 4 && Pred != ARMCC::AL) | |||
8198 | return Error(Operands[1]->getStartLoc(), | |||
8199 | "instruction 'pssbb' is not predicable, but condition code " | |||
8200 | "specified"); | |||
8201 | break; | |||
8202 | } | |||
8203 | case ARM::VMOVRRS: { | |||
8204 | // Source registers must be sequential. | |||
8205 | const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); | |||
8206 | const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); | |||
8207 | if (Sm1 != Sm + 1) | |||
8208 | return Error(Operands[5]->getStartLoc(), | |||
8209 | "source operands must be sequential"); | |||
8210 | break; | |||
8211 | } | |||
8212 | case ARM::VMOVSRR: { | |||
8213 | // Destination registers must be sequential. | |||
8214 | const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); | |||
8215 | const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); | |||
8216 | if (Sm1 != Sm + 1) | |||
8217 | return Error(Operands[3]->getStartLoc(), | |||
8218 | "destination operands must be sequential"); | |||
8219 | break; | |||
8220 | } | |||
8221 | case ARM::VLDMDIA: | |||
8222 | case ARM::VSTMDIA: { | |||
8223 | ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); | |||
8224 | auto &RegList = Op.getRegList(); | |||
8225 | if (RegList.size() < 1 || RegList.size() > 16) | |||
8226 | return Error(Operands[3]->getStartLoc(), | |||
8227 | "list of registers must be at least 1 and at most 16"); | |||
8228 | break; | |||
8229 | } | |||
8230 | case ARM::MVE_VQDMULLs32bh: | |||
8231 | case ARM::MVE_VQDMULLs32th: | |||
8232 | case ARM::MVE_VCMULf32: | |||
8233 | case ARM::MVE_VMULLBs32: | |||
8234 | case ARM::MVE_VMULLTs32: | |||
8235 | case ARM::MVE_VMULLBu32: | |||
8236 | case ARM::MVE_VMULLTu32: { | |||
8237 | if (Operands[3]->getReg() == Operands[4]->getReg()) { | |||
8238 | return Error (Operands[3]->getStartLoc(), | |||
8239 | "Qd register and Qn register can't be identical"); | |||
8240 | } | |||
8241 | if (Operands[3]->getReg() == Operands[5]->getReg()) { | |||
8242 | return Error (Operands[3]->getStartLoc(), | |||
8243 | "Qd register and Qm register can't be identical"); | |||
8244 | } | |||
8245 | break; | |||
8246 | } | |||
8247 | case ARM::MVE_VMOV_rr_q: { | |||
8248 | if (Operands[4]->getReg() != Operands[6]->getReg()) | |||
8249 | return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); | |||
8250 | if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != | |||
8251 | static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) | |||
8252 | return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); | |||
8253 | break; | |||
8254 | } | |||
8255 | case ARM::MVE_VMOV_q_rr: { | |||
8256 | if (Operands[2]->getReg() != Operands[4]->getReg()) | |||
8257 | return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); | |||
8258 | if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != | |||
8259 | static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) | |||
8260 | return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); | |||
8261 | break; | |||
8262 | } | |||
8263 | case ARM::UMAAL: | |||
8264 | case ARM::UMLAL: | |||
8265 | case ARM::UMULL: | |||
8266 | case ARM::t2UMAAL: | |||
8267 | case ARM::t2UMLAL: | |||
8268 | case ARM::t2UMULL: | |||
8269 | case ARM::SMLAL: | |||
8270 | case ARM::SMLALBB: | |||
8271 | case ARM::SMLALBT: | |||
8272 | case ARM::SMLALD: | |||
8273 | case ARM::SMLALDX: | |||
8274 | case ARM::SMLALTB: | |||
8275 | case ARM::SMLALTT: | |||
8276 | case ARM::SMLSLD: | |||
8277 | case ARM::SMLSLDX: | |||
8278 | case ARM::SMULL: | |||
8279 | case ARM::t2SMLAL: | |||
8280 | case ARM::t2SMLALBB: | |||
8281 | case ARM::t2SMLALBT: | |||
8282 | case ARM::t2SMLALD: | |||
8283 | case ARM::t2SMLALDX: | |||
8284 | case ARM::t2SMLALTB: | |||
8285 | case ARM::t2SMLALTT: | |||
8286 | case ARM::t2SMLSLD: | |||
8287 | case ARM::t2SMLSLDX: | |||
8288 | case ARM::t2SMULL: { | |||
8289 | unsigned RdHi = Inst.getOperand(0).getReg(); | |||
8290 | unsigned RdLo = Inst.getOperand(1).getReg(); | |||
8291 | if(RdHi == RdLo) { | |||
8292 | return Error(Loc, | |||
8293 | "unpredictable instruction, RdHi and RdLo must be different"); | |||
8294 | } | |||
8295 | break; | |||
8296 | } | |||
8297 | ||||
8298 | case ARM::CDE_CX1: | |||
8299 | case ARM::CDE_CX1A: | |||
8300 | case ARM::CDE_CX1D: | |||
8301 | case ARM::CDE_CX1DA: | |||
8302 | case ARM::CDE_CX2: | |||
8303 | case ARM::CDE_CX2A: | |||
8304 | case ARM::CDE_CX2D: | |||
8305 | case ARM::CDE_CX2DA: | |||
8306 | case ARM::CDE_CX3: | |||
8307 | case ARM::CDE_CX3A: | |||
8308 | case ARM::CDE_CX3D: | |||
8309 | case ARM::CDE_CX3DA: | |||
8310 | case ARM::CDE_VCX1_vec: | |||
8311 | case ARM::CDE_VCX1_fpsp: | |||
8312 | case ARM::CDE_VCX1_fpdp: | |||
8313 | case ARM::CDE_VCX1A_vec: | |||
8314 | case ARM::CDE_VCX1A_fpsp: | |||
8315 | case ARM::CDE_VCX1A_fpdp: | |||
8316 | case ARM::CDE_VCX2_vec: | |||
8317 | case ARM::CDE_VCX2_fpsp: | |||
8318 | case ARM::CDE_VCX2_fpdp: | |||
8319 | case ARM::CDE_VCX2A_vec: | |||
8320 | case ARM::CDE_VCX2A_fpsp: | |||
8321 | case ARM::CDE_VCX2A_fpdp: | |||
8322 | case ARM::CDE_VCX3_vec: | |||
8323 | case ARM::CDE_VCX3_fpsp: | |||
8324 | case ARM::CDE_VCX3_fpdp: | |||
8325 | case ARM::CDE_VCX3A_vec: | |||
8326 | case ARM::CDE_VCX3A_fpsp: | |||
8327 | case ARM::CDE_VCX3A_fpdp: { | |||
8328 | assert(Inst.getOperand(1).isImm() &&(static_cast<void> (0)) | |||
8329 | "CDE operand 1 must be a coprocessor ID")(static_cast<void> (0)); | |||
8330 | int64_t Coproc = Inst.getOperand(1).getImm(); | |||
8331 | if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI)) | |||
8332 | return Error(Operands[1]->getStartLoc(), | |||
8333 | "coprocessor must be configured as CDE"); | |||
8334 | else if (Coproc >= 8) | |||
8335 | return Error(Operands[1]->getStartLoc(), | |||
8336 | "coprocessor must be in the range [p0, p7]"); | |||
8337 | break; | |||
8338 | } | |||
8339 | ||||
8340 | case ARM::t2CDP: | |||
8341 | case ARM::t2CDP2: | |||
8342 | case ARM::t2LDC2L_OFFSET: | |||
8343 | case ARM::t2LDC2L_OPTION: | |||
8344 | case ARM::t2LDC2L_POST: | |||
8345 | case ARM::t2LDC2L_PRE: | |||
8346 | case ARM::t2LDC2_OFFSET: | |||
8347 | case ARM::t2LDC2_OPTION: | |||
8348 | case ARM::t2LDC2_POST: | |||
8349 | case ARM::t2LDC2_PRE: | |||
8350 | case ARM::t2LDCL_OFFSET: | |||
8351 | case ARM::t2LDCL_OPTION: | |||
8352 | case ARM::t2LDCL_POST: | |||
8353 | case ARM::t2LDCL_PRE: | |||
8354 | case ARM::t2LDC_OFFSET: | |||
8355 | case ARM::t2LDC_OPTION: | |||
8356 | case ARM::t2LDC_POST: | |||
8357 | case ARM::t2LDC_PRE: | |||
8358 | case ARM::t2MCR: | |||
8359 | case ARM::t2MCR2: | |||
8360 | case ARM::t2MCRR: | |||
8361 | case ARM::t2MCRR2: | |||
8362 | case ARM::t2MRC: | |||
8363 | case ARM::t2MRC2: | |||
8364 | case ARM::t2MRRC: | |||
8365 | case ARM::t2MRRC2: | |||
8366 | case ARM::t2STC2L_OFFSET: | |||
8367 | case ARM::t2STC2L_OPTION: | |||
8368 | case ARM::t2STC2L_POST: | |||
8369 | case ARM::t2STC2L_PRE: | |||
8370 | case ARM::t2STC2_OFFSET: | |||
8371 | case ARM::t2STC2_OPTION: | |||
8372 | case ARM::t2STC2_POST: | |||
8373 | case ARM::t2STC2_PRE: | |||
8374 | case ARM::t2STCL_OFFSET: | |||
8375 | case ARM::t2STCL_OPTION: | |||
8376 | case ARM::t2STCL_POST: | |||
8377 | case ARM::t2STCL_PRE: | |||
8378 | case ARM::t2STC_OFFSET: | |||
8379 | case ARM::t2STC_OPTION: | |||
8380 | case ARM::t2STC_POST: | |||
8381 | case ARM::t2STC_PRE: { | |||
8382 | unsigned Opcode = Inst.getOpcode(); | |||
8383 | // Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags, | |||
8384 | // CopInd is the index of the coprocessor operand. | |||
8385 | size_t CopInd = 0; | |||
8386 | if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2) | |||
8387 | CopInd = 2; | |||
8388 | else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2) | |||
8389 | CopInd = 1; | |||
8390 | assert(Inst.getOperand(CopInd).isImm() &&(static_cast<void> (0)) | |||
8391 | "Operand must be a coprocessor ID")(static_cast<void> (0)); | |||
8392 | int64_t Coproc = Inst.getOperand(CopInd).getImm(); | |||
8393 | // Operands[2] is the coprocessor operand at syntactic level | |||
8394 | if (ARM::isCDECoproc(Coproc, *STI)) | |||
8395 | return Error(Operands[2]->getStartLoc(), | |||
8396 | "coprocessor must be configured as GCP"); | |||
8397 | break; | |||
8398 | } | |||
8399 | } | |||
8400 | ||||
8401 | return false; | |||
8402 | } | |||
8403 | ||||
8404 | static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { | |||
8405 | switch(Opc) { | |||
8406 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
8407 | // VST1LN | |||
8408 | case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; | |||
8409 | case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; | |||
8410 | case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; | |||
8411 | case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; | |||
8412 | case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; | |||
8413 | case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; | |||
8414 | case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; | |||
8415 | case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; | |||
8416 | case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; | |||
8417 | ||||
8418 | // VST2LN | |||
8419 | case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; | |||
8420 | case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; | |||
8421 | case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; | |||
8422 | case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; | |||
8423 | case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; | |||
8424 | ||||
8425 | case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; | |||
8426 | case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; | |||
8427 | case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; | |||
8428 | case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; | |||
8429 | case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; | |||
8430 | ||||
8431 | case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; | |||
8432 | case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; | |||
8433 | case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; | |||
8434 | case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; | |||
8435 | case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; | |||
8436 | ||||
8437 | // VST3LN | |||
8438 | case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; | |||
8439 | case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; | |||
8440 | case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; | |||
8441 | case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; | |||
8442 | case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; | |||
8443 | case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; | |||
8444 | case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; | |||
8445 | case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; | |||
8446 | case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; | |||
8447 | case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; | |||
8448 | case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; | |||
8449 | case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; | |||
8450 | case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; | |||
8451 | case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; | |||
8452 | case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; | |||
8453 | ||||
8454 | // VST3 | |||
8455 | case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; | |||
8456 | case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; | |||
8457 | case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; | |||
8458 | case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; | |||
8459 | case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; | |||
8460 | case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; | |||
8461 | case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; | |||
8462 | case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; | |||
8463 | case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; | |||
8464 | case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; | |||
8465 | case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; | |||
8466 | case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; | |||
8467 | case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; | |||
8468 | case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; | |||
8469 | case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; | |||
8470 | case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; | |||
8471 | case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; | |||
8472 | case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; | |||
8473 | ||||
8474 | // VST4LN | |||
8475 | case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; | |||
8476 | case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; | |||
8477 | case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; | |||
8478 | case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; | |||
8479 | case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; | |||
8480 | case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; | |||
8481 | case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; | |||
8482 | case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; | |||
8483 | case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; | |||
8484 | case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; | |||
8485 | case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; | |||
8486 | case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; | |||
8487 | case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; | |||
8488 | case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; | |||
8489 | case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; | |||
8490 | ||||
8491 | // VST4 | |||
8492 | case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; | |||
8493 | case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; | |||
8494 | case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; | |||
8495 | case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; | |||
8496 | case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; | |||
8497 | case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; | |||
8498 | case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; | |||
8499 | case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; | |||
8500 | case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; | |||
8501 | case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; | |||
8502 | case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; | |||
8503 | case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; | |||
8504 | case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; | |||
8505 | case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; | |||
8506 | case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; | |||
8507 | case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; | |||
8508 | case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; | |||
8509 | case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; | |||
8510 | } | |||
8511 | } | |||
8512 | ||||
8513 | static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { | |||
8514 | switch(Opc) { | |||
8515 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
8516 | // VLD1LN | |||
8517 | case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; | |||
8518 | case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; | |||
8519 | case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; | |||
8520 | case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; | |||
8521 | case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; | |||
8522 | case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; | |||
8523 | case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; | |||
8524 | case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; | |||
8525 | case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; | |||
8526 | ||||
8527 | // VLD2LN | |||
8528 | case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; | |||
8529 | case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; | |||
8530 | case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; | |||
8531 | case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; | |||
8532 | case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; | |||
8533 | case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; | |||
8534 | case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; | |||
8535 | case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; | |||
8536 | case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; | |||
8537 | case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; | |||
8538 | case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; | |||
8539 | case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; | |||
8540 | case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; | |||
8541 | case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; | |||
8542 | case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; | |||
8543 | ||||
8544 | // VLD3DUP | |||
8545 | case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; | |||
8546 | case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; | |||
8547 | case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; | |||
8548 | case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; | |||
8549 | case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; | |||
8550 | case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; | |||
8551 | case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; | |||
8552 | case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; | |||
8553 | case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; | |||
8554 | case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; | |||
8555 | case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; | |||
8556 | case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; | |||
8557 | case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; | |||
8558 | case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; | |||
8559 | case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; | |||
8560 | case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; | |||
8561 | case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; | |||
8562 | case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; | |||
8563 | ||||
8564 | // VLD3LN | |||
8565 | case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; | |||
8566 | case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; | |||
8567 | case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; | |||
8568 | case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; | |||
8569 | case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; | |||
8570 | case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; | |||
8571 | case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; | |||
8572 | case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; | |||
8573 | case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; | |||
8574 | case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; | |||
8575 | case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; | |||
8576 | case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; | |||
8577 | case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; | |||
8578 | case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; | |||
8579 | case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; | |||
8580 | ||||
8581 | // VLD3 | |||
8582 | case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; | |||
8583 | case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; | |||
8584 | case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; | |||
8585 | case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; | |||
8586 | case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; | |||
8587 | case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; | |||
8588 | case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; | |||
8589 | case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; | |||
8590 | case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; | |||
8591 | case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; | |||
8592 | case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; | |||
8593 | case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; | |||
8594 | case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; | |||
8595 | case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; | |||
8596 | case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; | |||
8597 | case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; | |||
8598 | case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; | |||
8599 | case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; | |||
8600 | ||||
8601 | // VLD4LN | |||
8602 | case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; | |||
8603 | case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; | |||
8604 | case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; | |||
8605 | case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; | |||
8606 | case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; | |||
8607 | case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; | |||
8608 | case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; | |||
8609 | case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; | |||
8610 | case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; | |||
8611 | case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; | |||
8612 | case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; | |||
8613 | case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; | |||
8614 | case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; | |||
8615 | case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; | |||
8616 | case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; | |||
8617 | ||||
8618 | // VLD4DUP | |||
8619 | case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; | |||
8620 | case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; | |||
8621 | case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; | |||
8622 | case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; | |||
8623 | case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; | |||
8624 | case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; | |||
8625 | case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; | |||
8626 | case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; | |||
8627 | case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; | |||
8628 | case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; | |||
8629 | case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; | |||
8630 | case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; | |||
8631 | case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; | |||
8632 | case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; | |||
8633 | case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; | |||
8634 | case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; | |||
8635 | case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; | |||
8636 | case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; | |||
8637 | ||||
8638 | // VLD4 | |||
8639 | case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; | |||
8640 | case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; | |||
8641 | case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; | |||
8642 | case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; | |||
8643 | case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; | |||
8644 | case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; | |||
8645 | case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; | |||
8646 | case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; | |||
8647 | case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; | |||
8648 | case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; | |||
8649 | case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; | |||
8650 | case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; | |||
8651 | case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; | |||
8652 | case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; | |||
8653 | case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; | |||
8654 | case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; | |||
8655 | case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; | |||
8656 | case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; | |||
8657 | } | |||
8658 | } | |||
8659 | ||||
8660 | bool ARMAsmParser::processInstruction(MCInst &Inst, | |||
8661 | const OperandVector &Operands, | |||
8662 | MCStreamer &Out) { | |||
8663 | // Check if we have the wide qualifier, because if it's present we | |||
8664 | // must avoid selecting a 16-bit thumb instruction. | |||
8665 | bool HasWideQualifier = false; | |||
8666 | for (auto &Op : Operands) { | |||
8667 | ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op); | |||
8668 | if (ARMOp.isToken() && ARMOp.getToken() == ".w") { | |||
8669 | HasWideQualifier = true; | |||
8670 | break; | |||
8671 | } | |||
8672 | } | |||
8673 | ||||
8674 | switch (Inst.getOpcode()) { | |||
8675 | // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. | |||
8676 | case ARM::LDRT_POST: | |||
8677 | case ARM::LDRBT_POST: { | |||
8678 | const unsigned Opcode = | |||
8679 | (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM | |||
8680 | : ARM::LDRBT_POST_IMM; | |||
8681 | MCInst TmpInst; | |||
8682 | TmpInst.setOpcode(Opcode); | |||
8683 | TmpInst.addOperand(Inst.getOperand(0)); | |||
8684 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8685 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8686 | TmpInst.addOperand(MCOperand::createReg(0)); | |||
8687 | TmpInst.addOperand(MCOperand::createImm(0)); | |||
8688 | TmpInst.addOperand(Inst.getOperand(2)); | |||
8689 | TmpInst.addOperand(Inst.getOperand(3)); | |||
8690 | Inst = TmpInst; | |||
8691 | return true; | |||
8692 | } | |||
8693 | // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate. | |||
8694 | case ARM::LDRSBTii: | |||
8695 | case ARM::LDRHTii: | |||
8696 | case ARM::LDRSHTii: { | |||
8697 | MCInst TmpInst; | |||
8698 | ||||
8699 | if (Inst.getOpcode() == ARM::LDRSBTii) | |||
8700 | TmpInst.setOpcode(ARM::LDRSBTi); | |||
8701 | else if (Inst.getOpcode() == ARM::LDRHTii) | |||
8702 | TmpInst.setOpcode(ARM::LDRHTi); | |||
8703 | else if (Inst.getOpcode() == ARM::LDRSHTii) | |||
8704 | TmpInst.setOpcode(ARM::LDRSHTi); | |||
8705 | TmpInst.addOperand(Inst.getOperand(0)); | |||
8706 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8707 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8708 | TmpInst.addOperand(MCOperand::createImm(256)); | |||
8709 | TmpInst.addOperand(Inst.getOperand(2)); | |||
8710 | Inst = TmpInst; | |||
8711 | return true; | |||
8712 | } | |||
8713 | // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. | |||
8714 | case ARM::STRT_POST: | |||
8715 | case ARM::STRBT_POST: { | |||
8716 | const unsigned Opcode = | |||
8717 | (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM | |||
8718 | : ARM::STRBT_POST_IMM; | |||
8719 | MCInst TmpInst; | |||
8720 | TmpInst.setOpcode(Opcode); | |||
8721 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8722 | TmpInst.addOperand(Inst.getOperand(0)); | |||
8723 | TmpInst.addOperand(Inst.getOperand(1)); | |||
8724 | TmpInst.addOperand(MCOperand::createReg(0)); | |||
8725 | TmpInst.addOperand(MCOperand::createImm(0)); | |||
8726 | TmpInst.addOperand(Inst.getOperand(2)); | |||
8727 | TmpInst.addOperand(Inst.getOperand(3)); | |||
8728 | Inst = TmpInst; | |||
8729 | return true; | |||
8730 | } | |||
8731 | // Alias for alternate form of 'ADR Rd, #imm' instruction. | |||
8732 | case ARM::ADDri: { | |||
8733 | if (Inst.getOperand(1).getReg() != ARM::PC || | |||
8734 | Inst.getOperand(5).getReg() != 0 || | |||
8735 | !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) | |||
8736 | return false; | |||
8737 | MCInst TmpInst; | |||
8738 | TmpInst.setOpcode(ARM::ADR); | |||
8739 | TmpInst.addOperand(Inst.getOperand(0)); | |||
8740 | if (Inst.getOperand(2).isImm()) { | |||
8741 | // Immediate (mod_imm) will be in its encoded form, we must unencode it | |||
8742 | // before passing it to the ADR instruction. | |||
8743 | unsigned Enc = Inst.getOperand(2).getImm(); | |||
8744 | TmpInst.addOperand(MCOperand::createImm( | |||
8745 | ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); | |||
8746 | } else { | |||
8747 | // Turn PC-relative expression into absolute expression. | |||
8748 | // Reading PC provides the start of the current instruction + 8 and | |||
8749 | // the transform to adr is biased by that. | |||
8750 | MCSymbol *Dot = getContext().createTempSymbol(); | |||
8751 | Out.emitLabel(Dot); | |||
8752 | const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); | |||
8753 | const MCExpr *InstPC = MCSymbolRefExpr::create(Dot, | |||
8754 | MCSymbolRefExpr::VK_None, | |||
8755 | getContext()); | |||
8756 | const MCExpr *Const8 = MCConstantExpr::create(8, getContext()); | |||
8757 | const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8, | |||
8758 | getContext()); | |||
8759 | const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr, | |||
8760 | getContext()); | |||
8761 | TmpInst.addOperand(MCOperand::createExpr(FixupAddr)); | |||
8762 | } | |||
8763 | TmpInst.addOperand(Inst.getOperand(3)); | |||
8764 | TmpInst.addOperand(Inst.getOperand(4)); | |||
8765 | Inst = TmpInst; | |||
8766 | return true; | |||
8767 | } | |||
8768 | // Aliases for imm syntax of LDR instructions. | |||
8769 | case ARM::t2LDR_PRE_imm: | |||
8770 | case ARM::t2LDR_POST_imm: { | |||
8771 | MCInst TmpInst; | |||
8772 | TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE | |||
8773 | : ARM::t2LDR_POST); | |||
8774 | TmpInst.addOperand(Inst.getOperand(0)); // Rt | |||
8775 | TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb | |||
8776 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
8777 | TmpInst.addOperand(Inst.getOperand(2)); // imm | |||
8778 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
8779 | Inst = TmpInst; | |||
8780 | return true; | |||
8781 | } | |||
8782 | // Aliases for imm syntax of STR instructions. | |||
8783 | case ARM::t2STR_PRE_imm: | |||
8784 | case ARM::t2STR_POST_imm: { | |||
8785 | MCInst TmpInst; | |||
8786 | TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE | |||
8787 | : ARM::t2STR_POST); | |||
8788 | TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb | |||
8789 | TmpInst.addOperand(Inst.getOperand(0)); // Rt | |||
8790 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
8791 | TmpInst.addOperand(Inst.getOperand(2)); // imm | |||
8792 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
8793 | Inst = TmpInst; | |||
8794 | return true; | |||
8795 | } | |||
8796 | // Aliases for alternate PC+imm syntax of LDR instructions. | |||
8797 | case ARM::t2LDRpcrel: | |||
8798 | // Select the narrow version if the immediate will fit. | |||
8799 | if (Inst.getOperand(1).getImm() > 0 && | |||
8800 | Inst.getOperand(1).getImm() <= 0xff && | |||
8801 | !HasWideQualifier) | |||
8802 | Inst.setOpcode(ARM::tLDRpci); | |||
8803 | else | |||
8804 | Inst.setOpcode(ARM::t2LDRpci); | |||
8805 | return true; | |||
8806 | case ARM::t2LDRBpcrel: | |||
8807 | Inst.setOpcode(ARM::t2LDRBpci); | |||
8808 | return true; | |||
8809 | case ARM::t2LDRHpcrel: | |||
8810 | Inst.setOpcode(ARM::t2LDRHpci); | |||
8811 | return true; | |||
8812 | case ARM::t2LDRSBpcrel: | |||
8813 | Inst.setOpcode(ARM::t2LDRSBpci); | |||
8814 | return true; | |||
8815 | case ARM::t2LDRSHpcrel: | |||
8816 | Inst.setOpcode(ARM::t2LDRSHpci); | |||
8817 | return true; | |||
8818 | case ARM::LDRConstPool: | |||
8819 | case ARM::tLDRConstPool: | |||
8820 | case ARM::t2LDRConstPool: { | |||
8821 | // Pseudo instruction ldr rt, =immediate is converted to a | |||
8822 | // MOV rt, immediate if immediate is known and representable | |||
8823 | // otherwise we create a constant pool entry that we load from. | |||
8824 | MCInst TmpInst; | |||
8825 | if (Inst.getOpcode() == ARM::LDRConstPool) | |||
8826 | TmpInst.setOpcode(ARM::LDRi12); | |||
8827 | else if (Inst.getOpcode() == ARM::tLDRConstPool) | |||
8828 | TmpInst.setOpcode(ARM::tLDRpci); | |||
8829 | else if (Inst.getOpcode() == ARM::t2LDRConstPool) | |||
8830 | TmpInst.setOpcode(ARM::t2LDRpci); | |||
8831 | const ARMOperand &PoolOperand = | |||
8832 | (HasWideQualifier ? | |||
8833 | static_cast<ARMOperand &>(*Operands[4]) : | |||
8834 | static_cast<ARMOperand &>(*Operands[3])); | |||
8835 | const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm(); | |||
8836 | // If SubExprVal is a constant we may be able to use a MOV | |||
8837 | if (isa<MCConstantExpr>(SubExprVal) && | |||
8838 | Inst.getOperand(0).getReg() != ARM::PC && | |||
8839 | Inst.getOperand(0).getReg() != ARM::SP) { | |||
8840 | int64_t Value = | |||
8841 | (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue(); | |||
8842 | bool UseMov = true; | |||
8843 | bool MovHasS = true; | |||
8844 | if (Inst.getOpcode() == ARM::LDRConstPool) { | |||
8845 | // ARM Constant | |||
8846 | if (ARM_AM::getSOImmVal(Value) != -1) { | |||
8847 | Value = ARM_AM::getSOImmVal(Value); | |||
8848 | TmpInst.setOpcode(ARM::MOVi); | |||
8849 | } | |||
8850 | else if (ARM_AM::getSOImmVal(~Value) != -1) { | |||
8851 | Value = ARM_AM::getSOImmVal(~Value); | |||
8852 | TmpInst.setOpcode(ARM::MVNi); | |||
8853 | } | |||
8854 | else if (hasV6T2Ops() && | |||
8855 | Value >=0 && Value < 65536) { | |||
8856 | TmpInst.setOpcode(ARM::MOVi16); | |||
8857 | MovHasS = false; | |||
8858 | } | |||
8859 | else | |||
8860 | UseMov = false; | |||
8861 | } | |||
8862 | else { | |||
8863 | // Thumb/Thumb2 Constant | |||
8864 | if (hasThumb2() && | |||
8865 | ARM_AM::getT2SOImmVal(Value) != -1) | |||
8866 | TmpInst.setOpcode(ARM::t2MOVi); | |||
8867 | else if (hasThumb2() && | |||
8868 | ARM_AM::getT2SOImmVal(~Value) != -1) { | |||
8869 | TmpInst.setOpcode(ARM::t2MVNi); | |||
8870 | Value = ~Value; | |||
8871 | } | |||
8872 | else if (hasV8MBaseline() && | |||
8873 | Value >=0 && Value < 65536) { | |||
8874 | TmpInst.setOpcode(ARM::t2MOVi16); | |||
8875 | MovHasS = false; | |||
8876 | } | |||
8877 | else | |||
8878 | UseMov = false; | |||
8879 | } | |||
8880 | if (UseMov) { | |||
8881 | TmpInst.addOperand(Inst.getOperand(0)); // Rt | |||
8882 | TmpInst.addOperand(MCOperand::createImm(Value)); // Immediate | |||
8883 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
8884 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
8885 | if (MovHasS) | |||
8886 | TmpInst.addOperand(MCOperand::createReg(0)); // S | |||
8887 | Inst = TmpInst; | |||
8888 | return true; | |||
8889 | } | |||
8890 | } | |||
8891 | // No opportunity to use MOV/MVN create constant pool | |||
8892 | const MCExpr *CPLoc = | |||
8893 | getTargetStreamer().addConstantPoolEntry(SubExprVal, | |||
8894 | PoolOperand.getStartLoc()); | |||
8895 | TmpInst.addOperand(Inst.getOperand(0)); // Rt | |||
8896 | TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool | |||
8897 | if (TmpInst.getOpcode() == ARM::LDRi12) | |||
8898 | TmpInst.addOperand(MCOperand::createImm(0)); // unused offset | |||
8899 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
8900 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
8901 | Inst = TmpInst; | |||
8902 | return true; | |||
8903 | } | |||
8904 | // Handle NEON VST complex aliases. | |||
8905 | case ARM::VST1LNdWB_register_Asm_8: | |||
8906 | case ARM::VST1LNdWB_register_Asm_16: | |||
8907 | case ARM::VST1LNdWB_register_Asm_32: { | |||
8908 | MCInst TmpInst; | |||
8909 | // Shuffle the operands around so the lane index operand is in the | |||
8910 | // right place. | |||
8911 | unsigned Spacing; | |||
8912 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
8913 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
8914 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
8915 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
8916 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
8917 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
8918 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
8919 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
8920 | TmpInst.addOperand(Inst.getOperand(6)); | |||
8921 | Inst = TmpInst; | |||
8922 | return true; | |||
8923 | } | |||
8924 | ||||
8925 | case ARM::VST2LNdWB_register_Asm_8: | |||
8926 | case ARM::VST2LNdWB_register_Asm_16: | |||
8927 | case ARM::VST2LNdWB_register_Asm_32: | |||
8928 | case ARM::VST2LNqWB_register_Asm_16: | |||
8929 | case ARM::VST2LNqWB_register_Asm_32: { | |||
8930 | MCInst TmpInst; | |||
8931 | // Shuffle the operands around so the lane index operand is in the | |||
8932 | // right place. | |||
8933 | unsigned Spacing; | |||
8934 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
8935 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
8936 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
8937 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
8938 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
8939 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
8940 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8941 | Spacing)); | |||
8942 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
8943 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
8944 | TmpInst.addOperand(Inst.getOperand(6)); | |||
8945 | Inst = TmpInst; | |||
8946 | return true; | |||
8947 | } | |||
8948 | ||||
8949 | case ARM::VST3LNdWB_register_Asm_8: | |||
8950 | case ARM::VST3LNdWB_register_Asm_16: | |||
8951 | case ARM::VST3LNdWB_register_Asm_32: | |||
8952 | case ARM::VST3LNqWB_register_Asm_16: | |||
8953 | case ARM::VST3LNqWB_register_Asm_32: { | |||
8954 | MCInst TmpInst; | |||
8955 | // Shuffle the operands around so the lane index operand is in the | |||
8956 | // right place. | |||
8957 | unsigned Spacing; | |||
8958 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
8959 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
8960 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
8961 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
8962 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
8963 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
8964 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8965 | Spacing)); | |||
8966 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8967 | Spacing * 2)); | |||
8968 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
8969 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
8970 | TmpInst.addOperand(Inst.getOperand(6)); | |||
8971 | Inst = TmpInst; | |||
8972 | return true; | |||
8973 | } | |||
8974 | ||||
8975 | case ARM::VST4LNdWB_register_Asm_8: | |||
8976 | case ARM::VST4LNdWB_register_Asm_16: | |||
8977 | case ARM::VST4LNdWB_register_Asm_32: | |||
8978 | case ARM::VST4LNqWB_register_Asm_16: | |||
8979 | case ARM::VST4LNqWB_register_Asm_32: { | |||
8980 | MCInst TmpInst; | |||
8981 | // Shuffle the operands around so the lane index operand is in the | |||
8982 | // right place. | |||
8983 | unsigned Spacing; | |||
8984 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
8985 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
8986 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
8987 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
8988 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
8989 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
8990 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8991 | Spacing)); | |||
8992 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8993 | Spacing * 2)); | |||
8994 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
8995 | Spacing * 3)); | |||
8996 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
8997 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
8998 | TmpInst.addOperand(Inst.getOperand(6)); | |||
8999 | Inst = TmpInst; | |||
9000 | return true; | |||
9001 | } | |||
9002 | ||||
9003 | case ARM::VST1LNdWB_fixed_Asm_8: | |||
9004 | case ARM::VST1LNdWB_fixed_Asm_16: | |||
9005 | case ARM::VST1LNdWB_fixed_Asm_32: { | |||
9006 | MCInst TmpInst; | |||
9007 | // Shuffle the operands around so the lane index operand is in the | |||
9008 | // right place. | |||
9009 | unsigned Spacing; | |||
9010 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9011 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9012 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9013 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9014 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9015 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9016 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9017 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9018 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9019 | Inst = TmpInst; | |||
9020 | return true; | |||
9021 | } | |||
9022 | ||||
9023 | case ARM::VST2LNdWB_fixed_Asm_8: | |||
9024 | case ARM::VST2LNdWB_fixed_Asm_16: | |||
9025 | case ARM::VST2LNdWB_fixed_Asm_32: | |||
9026 | case ARM::VST2LNqWB_fixed_Asm_16: | |||
9027 | case ARM::VST2LNqWB_fixed_Asm_32: { | |||
9028 | MCInst TmpInst; | |||
9029 | // Shuffle the operands around so the lane index operand is in the | |||
9030 | // right place. | |||
9031 | unsigned Spacing; | |||
9032 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9033 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9034 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9035 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9036 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9037 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9038 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9039 | Spacing)); | |||
9040 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9041 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9042 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9043 | Inst = TmpInst; | |||
9044 | return true; | |||
9045 | } | |||
9046 | ||||
9047 | case ARM::VST3LNdWB_fixed_Asm_8: | |||
9048 | case ARM::VST3LNdWB_fixed_Asm_16: | |||
9049 | case ARM::VST3LNdWB_fixed_Asm_32: | |||
9050 | case ARM::VST3LNqWB_fixed_Asm_16: | |||
9051 | case ARM::VST3LNqWB_fixed_Asm_32: { | |||
9052 | MCInst TmpInst; | |||
9053 | // Shuffle the operands around so the lane index operand is in the | |||
9054 | // right place. | |||
9055 | unsigned Spacing; | |||
9056 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9057 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9058 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9059 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9060 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9061 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9062 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9063 | Spacing)); | |||
9064 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9065 | Spacing * 2)); | |||
9066 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9067 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9068 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9069 | Inst = TmpInst; | |||
9070 | return true; | |||
9071 | } | |||
9072 | ||||
9073 | case ARM::VST4LNdWB_fixed_Asm_8: | |||
9074 | case ARM::VST4LNdWB_fixed_Asm_16: | |||
9075 | case ARM::VST4LNdWB_fixed_Asm_32: | |||
9076 | case ARM::VST4LNqWB_fixed_Asm_16: | |||
9077 | case ARM::VST4LNqWB_fixed_Asm_32: { | |||
9078 | MCInst TmpInst; | |||
9079 | // Shuffle the operands around so the lane index operand is in the | |||
9080 | // right place. | |||
9081 | unsigned Spacing; | |||
9082 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9083 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9084 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9085 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9086 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9087 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9088 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9089 | Spacing)); | |||
9090 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9091 | Spacing * 2)); | |||
9092 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9093 | Spacing * 3)); | |||
9094 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9095 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9096 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9097 | Inst = TmpInst; | |||
9098 | return true; | |||
9099 | } | |||
9100 | ||||
9101 | case ARM::VST1LNdAsm_8: | |||
9102 | case ARM::VST1LNdAsm_16: | |||
9103 | case ARM::VST1LNdAsm_32: { | |||
9104 | MCInst TmpInst; | |||
9105 | // Shuffle the operands around so the lane index operand is in the | |||
9106 | // right place. | |||
9107 | unsigned Spacing; | |||
9108 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9109 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9110 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9111 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9112 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9113 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9114 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9115 | Inst = TmpInst; | |||
9116 | return true; | |||
9117 | } | |||
9118 | ||||
9119 | case ARM::VST2LNdAsm_8: | |||
9120 | case ARM::VST2LNdAsm_16: | |||
9121 | case ARM::VST2LNdAsm_32: | |||
9122 | case ARM::VST2LNqAsm_16: | |||
9123 | case ARM::VST2LNqAsm_32: { | |||
9124 | MCInst TmpInst; | |||
9125 | // Shuffle the operands around so the lane index operand is in the | |||
9126 | // right place. | |||
9127 | unsigned Spacing; | |||
9128 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9129 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9130 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9131 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9132 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9133 | Spacing)); | |||
9134 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9135 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9136 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9137 | Inst = TmpInst; | |||
9138 | return true; | |||
9139 | } | |||
9140 | ||||
9141 | case ARM::VST3LNdAsm_8: | |||
9142 | case ARM::VST3LNdAsm_16: | |||
9143 | case ARM::VST3LNdAsm_32: | |||
9144 | case ARM::VST3LNqAsm_16: | |||
9145 | case ARM::VST3LNqAsm_32: { | |||
9146 | MCInst TmpInst; | |||
9147 | // Shuffle the operands around so the lane index operand is in the | |||
9148 | // right place. | |||
9149 | unsigned Spacing; | |||
9150 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9151 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9152 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9153 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9154 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9155 | Spacing)); | |||
9156 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9157 | Spacing * 2)); | |||
9158 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9159 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9160 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9161 | Inst = TmpInst; | |||
9162 | return true; | |||
9163 | } | |||
9164 | ||||
9165 | case ARM::VST4LNdAsm_8: | |||
9166 | case ARM::VST4LNdAsm_16: | |||
9167 | case ARM::VST4LNdAsm_32: | |||
9168 | case ARM::VST4LNqAsm_16: | |||
9169 | case ARM::VST4LNqAsm_32: { | |||
9170 | MCInst TmpInst; | |||
9171 | // Shuffle the operands around so the lane index operand is in the | |||
9172 | // right place. | |||
9173 | unsigned Spacing; | |||
9174 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9175 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9176 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9177 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9178 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9179 | Spacing)); | |||
9180 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9181 | Spacing * 2)); | |||
9182 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9183 | Spacing * 3)); | |||
9184 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9185 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9186 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9187 | Inst = TmpInst; | |||
9188 | return true; | |||
9189 | } | |||
9190 | ||||
9191 | // Handle NEON VLD complex aliases. | |||
9192 | case ARM::VLD1LNdWB_register_Asm_8: | |||
9193 | case ARM::VLD1LNdWB_register_Asm_16: | |||
9194 | case ARM::VLD1LNdWB_register_Asm_32: { | |||
9195 | MCInst TmpInst; | |||
9196 | // Shuffle the operands around so the lane index operand is in the | |||
9197 | // right place. | |||
9198 | unsigned Spacing; | |||
9199 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9200 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9201 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9202 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9203 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9204 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
9205 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9206 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9207 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
9208 | TmpInst.addOperand(Inst.getOperand(6)); | |||
9209 | Inst = TmpInst; | |||
9210 | return true; | |||
9211 | } | |||
9212 | ||||
9213 | case ARM::VLD2LNdWB_register_Asm_8: | |||
9214 | case ARM::VLD2LNdWB_register_Asm_16: | |||
9215 | case ARM::VLD2LNdWB_register_Asm_32: | |||
9216 | case ARM::VLD2LNqWB_register_Asm_16: | |||
9217 | case ARM::VLD2LNqWB_register_Asm_32: { | |||
9218 | MCInst TmpInst; | |||
9219 | // Shuffle the operands around so the lane index operand is in the | |||
9220 | // right place. | |||
9221 | unsigned Spacing; | |||
9222 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9223 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9224 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9225 | Spacing)); | |||
9226 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9227 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9228 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9229 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
9230 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9231 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9232 | Spacing)); | |||
9233 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9234 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
9235 | TmpInst.addOperand(Inst.getOperand(6)); | |||
9236 | Inst = TmpInst; | |||
9237 | return true; | |||
9238 | } | |||
9239 | ||||
9240 | case ARM::VLD3LNdWB_register_Asm_8: | |||
9241 | case ARM::VLD3LNdWB_register_Asm_16: | |||
9242 | case ARM::VLD3LNdWB_register_Asm_32: | |||
9243 | case ARM::VLD3LNqWB_register_Asm_16: | |||
9244 | case ARM::VLD3LNqWB_register_Asm_32: { | |||
9245 | MCInst TmpInst; | |||
9246 | // Shuffle the operands around so the lane index operand is in the | |||
9247 | // right place. | |||
9248 | unsigned Spacing; | |||
9249 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9250 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9251 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9252 | Spacing)); | |||
9253 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9254 | Spacing * 2)); | |||
9255 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9256 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9257 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9258 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
9259 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9260 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9261 | Spacing)); | |||
9262 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9263 | Spacing * 2)); | |||
9264 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9265 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
9266 | TmpInst.addOperand(Inst.getOperand(6)); | |||
9267 | Inst = TmpInst; | |||
9268 | return true; | |||
9269 | } | |||
9270 | ||||
9271 | case ARM::VLD4LNdWB_register_Asm_8: | |||
9272 | case ARM::VLD4LNdWB_register_Asm_16: | |||
9273 | case ARM::VLD4LNdWB_register_Asm_32: | |||
9274 | case ARM::VLD4LNqWB_register_Asm_16: | |||
9275 | case ARM::VLD4LNqWB_register_Asm_32: { | |||
9276 | MCInst TmpInst; | |||
9277 | // Shuffle the operands around so the lane index operand is in the | |||
9278 | // right place. | |||
9279 | unsigned Spacing; | |||
9280 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9281 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9282 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9283 | Spacing)); | |||
9284 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9285 | Spacing * 2)); | |||
9286 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9287 | Spacing * 3)); | |||
9288 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9289 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9290 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9291 | TmpInst.addOperand(Inst.getOperand(4)); // Rm | |||
9292 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9293 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9294 | Spacing)); | |||
9295 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9296 | Spacing * 2)); | |||
9297 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9298 | Spacing * 3)); | |||
9299 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9300 | TmpInst.addOperand(Inst.getOperand(5)); // CondCode | |||
9301 | TmpInst.addOperand(Inst.getOperand(6)); | |||
9302 | Inst = TmpInst; | |||
9303 | return true; | |||
9304 | } | |||
9305 | ||||
9306 | case ARM::VLD1LNdWB_fixed_Asm_8: | |||
9307 | case ARM::VLD1LNdWB_fixed_Asm_16: | |||
9308 | case ARM::VLD1LNdWB_fixed_Asm_32: { | |||
9309 | MCInst TmpInst; | |||
9310 | // Shuffle the operands around so the lane index operand is in the | |||
9311 | // right place. | |||
9312 | unsigned Spacing; | |||
9313 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9314 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9315 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9316 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9317 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9318 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9319 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9320 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9321 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9322 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9323 | Inst = TmpInst; | |||
9324 | return true; | |||
9325 | } | |||
9326 | ||||
9327 | case ARM::VLD2LNdWB_fixed_Asm_8: | |||
9328 | case ARM::VLD2LNdWB_fixed_Asm_16: | |||
9329 | case ARM::VLD2LNdWB_fixed_Asm_32: | |||
9330 | case ARM::VLD2LNqWB_fixed_Asm_16: | |||
9331 | case ARM::VLD2LNqWB_fixed_Asm_32: { | |||
9332 | MCInst TmpInst; | |||
9333 | // Shuffle the operands around so the lane index operand is in the | |||
9334 | // right place. | |||
9335 | unsigned Spacing; | |||
9336 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9337 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9338 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9339 | Spacing)); | |||
9340 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9341 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9342 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9343 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9344 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9345 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9346 | Spacing)); | |||
9347 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9348 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9349 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9350 | Inst = TmpInst; | |||
9351 | return true; | |||
9352 | } | |||
9353 | ||||
9354 | case ARM::VLD3LNdWB_fixed_Asm_8: | |||
9355 | case ARM::VLD3LNdWB_fixed_Asm_16: | |||
9356 | case ARM::VLD3LNdWB_fixed_Asm_32: | |||
9357 | case ARM::VLD3LNqWB_fixed_Asm_16: | |||
9358 | case ARM::VLD3LNqWB_fixed_Asm_32: { | |||
9359 | MCInst TmpInst; | |||
9360 | // Shuffle the operands around so the lane index operand is in the | |||
9361 | // right place. | |||
9362 | unsigned Spacing; | |||
9363 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9364 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9365 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9366 | Spacing)); | |||
9367 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9368 | Spacing * 2)); | |||
9369 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9370 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9371 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9372 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9373 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9374 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9375 | Spacing)); | |||
9376 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9377 | Spacing * 2)); | |||
9378 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9379 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9380 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9381 | Inst = TmpInst; | |||
9382 | return true; | |||
9383 | } | |||
9384 | ||||
9385 | case ARM::VLD4LNdWB_fixed_Asm_8: | |||
9386 | case ARM::VLD4LNdWB_fixed_Asm_16: | |||
9387 | case ARM::VLD4LNdWB_fixed_Asm_32: | |||
9388 | case ARM::VLD4LNqWB_fixed_Asm_16: | |||
9389 | case ARM::VLD4LNqWB_fixed_Asm_32: { | |||
9390 | MCInst TmpInst; | |||
9391 | // Shuffle the operands around so the lane index operand is in the | |||
9392 | // right place. | |||
9393 | unsigned Spacing; | |||
9394 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9395 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9396 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9397 | Spacing)); | |||
9398 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9399 | Spacing * 2)); | |||
9400 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9401 | Spacing * 3)); | |||
9402 | TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb | |||
9403 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9404 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9405 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9406 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9407 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9408 | Spacing)); | |||
9409 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9410 | Spacing * 2)); | |||
9411 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9412 | Spacing * 3)); | |||
9413 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9414 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9415 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9416 | Inst = TmpInst; | |||
9417 | return true; | |||
9418 | } | |||
9419 | ||||
9420 | case ARM::VLD1LNdAsm_8: | |||
9421 | case ARM::VLD1LNdAsm_16: | |||
9422 | case ARM::VLD1LNdAsm_32: { | |||
9423 | MCInst TmpInst; | |||
9424 | // Shuffle the operands around so the lane index operand is in the | |||
9425 | // right place. | |||
9426 | unsigned Spacing; | |||
9427 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9428 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9429 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9430 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9431 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9432 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9433 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9434 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9435 | Inst = TmpInst; | |||
9436 | return true; | |||
9437 | } | |||
9438 | ||||
9439 | case ARM::VLD2LNdAsm_8: | |||
9440 | case ARM::VLD2LNdAsm_16: | |||
9441 | case ARM::VLD2LNdAsm_32: | |||
9442 | case ARM::VLD2LNqAsm_16: | |||
9443 | case ARM::VLD2LNqAsm_32: { | |||
9444 | MCInst TmpInst; | |||
9445 | // Shuffle the operands around so the lane index operand is in the | |||
9446 | // right place. | |||
9447 | unsigned Spacing; | |||
9448 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9449 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9450 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9451 | Spacing)); | |||
9452 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9453 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9454 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9455 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9456 | Spacing)); | |||
9457 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9458 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9459 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9460 | Inst = TmpInst; | |||
9461 | return true; | |||
9462 | } | |||
9463 | ||||
9464 | case ARM::VLD3LNdAsm_8: | |||
9465 | case ARM::VLD3LNdAsm_16: | |||
9466 | case ARM::VLD3LNdAsm_32: | |||
9467 | case ARM::VLD3LNqAsm_16: | |||
9468 | case ARM::VLD3LNqAsm_32: { | |||
9469 | MCInst TmpInst; | |||
9470 | // Shuffle the operands around so the lane index operand is in the | |||
9471 | // right place. | |||
9472 | unsigned Spacing; | |||
9473 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9474 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9475 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9476 | Spacing)); | |||
9477 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9478 | Spacing * 2)); | |||
9479 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9480 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9481 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9482 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9483 | Spacing)); | |||
9484 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9485 | Spacing * 2)); | |||
9486 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9487 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9488 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9489 | Inst = TmpInst; | |||
9490 | return true; | |||
9491 | } | |||
9492 | ||||
9493 | case ARM::VLD4LNdAsm_8: | |||
9494 | case ARM::VLD4LNdAsm_16: | |||
9495 | case ARM::VLD4LNdAsm_32: | |||
9496 | case ARM::VLD4LNqAsm_16: | |||
9497 | case ARM::VLD4LNqAsm_32: { | |||
9498 | MCInst TmpInst; | |||
9499 | // Shuffle the operands around so the lane index operand is in the | |||
9500 | // right place. | |||
9501 | unsigned Spacing; | |||
9502 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9503 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9504 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9505 | Spacing)); | |||
9506 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9507 | Spacing * 2)); | |||
9508 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9509 | Spacing * 3)); | |||
9510 | TmpInst.addOperand(Inst.getOperand(2)); // Rn | |||
9511 | TmpInst.addOperand(Inst.getOperand(3)); // alignment | |||
9512 | TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) | |||
9513 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9514 | Spacing)); | |||
9515 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9516 | Spacing * 2)); | |||
9517 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9518 | Spacing * 3)); | |||
9519 | TmpInst.addOperand(Inst.getOperand(1)); // lane | |||
9520 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9521 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9522 | Inst = TmpInst; | |||
9523 | return true; | |||
9524 | } | |||
9525 | ||||
9526 | // VLD3DUP single 3-element structure to all lanes instructions. | |||
9527 | case ARM::VLD3DUPdAsm_8: | |||
9528 | case ARM::VLD3DUPdAsm_16: | |||
9529 | case ARM::VLD3DUPdAsm_32: | |||
9530 | case ARM::VLD3DUPqAsm_8: | |||
9531 | case ARM::VLD3DUPqAsm_16: | |||
9532 | case ARM::VLD3DUPqAsm_32: { | |||
9533 | MCInst TmpInst; | |||
9534 | unsigned Spacing; | |||
9535 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9536 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9537 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9538 | Spacing)); | |||
9539 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9540 | Spacing * 2)); | |||
9541 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9542 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9543 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9544 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9545 | Inst = TmpInst; | |||
9546 | return true; | |||
9547 | } | |||
9548 | ||||
9549 | case ARM::VLD3DUPdWB_fixed_Asm_8: | |||
9550 | case ARM::VLD3DUPdWB_fixed_Asm_16: | |||
9551 | case ARM::VLD3DUPdWB_fixed_Asm_32: | |||
9552 | case ARM::VLD3DUPqWB_fixed_Asm_8: | |||
9553 | case ARM::VLD3DUPqWB_fixed_Asm_16: | |||
9554 | case ARM::VLD3DUPqWB_fixed_Asm_32: { | |||
9555 | MCInst TmpInst; | |||
9556 | unsigned Spacing; | |||
9557 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9558 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9559 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9560 | Spacing)); | |||
9561 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9562 | Spacing * 2)); | |||
9563 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9564 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9565 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9566 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9567 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9568 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9569 | Inst = TmpInst; | |||
9570 | return true; | |||
9571 | } | |||
9572 | ||||
9573 | case ARM::VLD3DUPdWB_register_Asm_8: | |||
9574 | case ARM::VLD3DUPdWB_register_Asm_16: | |||
9575 | case ARM::VLD3DUPdWB_register_Asm_32: | |||
9576 | case ARM::VLD3DUPqWB_register_Asm_8: | |||
9577 | case ARM::VLD3DUPqWB_register_Asm_16: | |||
9578 | case ARM::VLD3DUPqWB_register_Asm_32: { | |||
9579 | MCInst TmpInst; | |||
9580 | unsigned Spacing; | |||
9581 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9582 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9583 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9584 | Spacing)); | |||
9585 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9586 | Spacing * 2)); | |||
9587 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9588 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9589 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9590 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9591 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9592 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9593 | Inst = TmpInst; | |||
9594 | return true; | |||
9595 | } | |||
9596 | ||||
9597 | // VLD3 multiple 3-element structure instructions. | |||
9598 | case ARM::VLD3dAsm_8: | |||
9599 | case ARM::VLD3dAsm_16: | |||
9600 | case ARM::VLD3dAsm_32: | |||
9601 | case ARM::VLD3qAsm_8: | |||
9602 | case ARM::VLD3qAsm_16: | |||
9603 | case ARM::VLD3qAsm_32: { | |||
9604 | MCInst TmpInst; | |||
9605 | unsigned Spacing; | |||
9606 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9607 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9608 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9609 | Spacing)); | |||
9610 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9611 | Spacing * 2)); | |||
9612 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9613 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9614 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9615 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9616 | Inst = TmpInst; | |||
9617 | return true; | |||
9618 | } | |||
9619 | ||||
9620 | case ARM::VLD3dWB_fixed_Asm_8: | |||
9621 | case ARM::VLD3dWB_fixed_Asm_16: | |||
9622 | case ARM::VLD3dWB_fixed_Asm_32: | |||
9623 | case ARM::VLD3qWB_fixed_Asm_8: | |||
9624 | case ARM::VLD3qWB_fixed_Asm_16: | |||
9625 | case ARM::VLD3qWB_fixed_Asm_32: { | |||
9626 | MCInst TmpInst; | |||
9627 | unsigned Spacing; | |||
9628 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9629 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9630 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9631 | Spacing)); | |||
9632 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9633 | Spacing * 2)); | |||
9634 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9635 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9636 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9637 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9638 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9639 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9640 | Inst = TmpInst; | |||
9641 | return true; | |||
9642 | } | |||
9643 | ||||
9644 | case ARM::VLD3dWB_register_Asm_8: | |||
9645 | case ARM::VLD3dWB_register_Asm_16: | |||
9646 | case ARM::VLD3dWB_register_Asm_32: | |||
9647 | case ARM::VLD3qWB_register_Asm_8: | |||
9648 | case ARM::VLD3qWB_register_Asm_16: | |||
9649 | case ARM::VLD3qWB_register_Asm_32: { | |||
9650 | MCInst TmpInst; | |||
9651 | unsigned Spacing; | |||
9652 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9653 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9654 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9655 | Spacing)); | |||
9656 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9657 | Spacing * 2)); | |||
9658 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9659 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9660 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9661 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9662 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9663 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9664 | Inst = TmpInst; | |||
9665 | return true; | |||
9666 | } | |||
9667 | ||||
9668 | // VLD4DUP single 3-element structure to all lanes instructions. | |||
9669 | case ARM::VLD4DUPdAsm_8: | |||
9670 | case ARM::VLD4DUPdAsm_16: | |||
9671 | case ARM::VLD4DUPdAsm_32: | |||
9672 | case ARM::VLD4DUPqAsm_8: | |||
9673 | case ARM::VLD4DUPqAsm_16: | |||
9674 | case ARM::VLD4DUPqAsm_32: { | |||
9675 | MCInst TmpInst; | |||
9676 | unsigned Spacing; | |||
9677 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9678 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9679 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9680 | Spacing)); | |||
9681 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9682 | Spacing * 2)); | |||
9683 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9684 | Spacing * 3)); | |||
9685 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9686 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9687 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9688 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9689 | Inst = TmpInst; | |||
9690 | return true; | |||
9691 | } | |||
9692 | ||||
9693 | case ARM::VLD4DUPdWB_fixed_Asm_8: | |||
9694 | case ARM::VLD4DUPdWB_fixed_Asm_16: | |||
9695 | case ARM::VLD4DUPdWB_fixed_Asm_32: | |||
9696 | case ARM::VLD4DUPqWB_fixed_Asm_8: | |||
9697 | case ARM::VLD4DUPqWB_fixed_Asm_16: | |||
9698 | case ARM::VLD4DUPqWB_fixed_Asm_32: { | |||
9699 | MCInst TmpInst; | |||
9700 | unsigned Spacing; | |||
9701 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9702 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9703 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9704 | Spacing)); | |||
9705 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9706 | Spacing * 2)); | |||
9707 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9708 | Spacing * 3)); | |||
9709 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9710 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9711 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9712 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9713 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9714 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9715 | Inst = TmpInst; | |||
9716 | return true; | |||
9717 | } | |||
9718 | ||||
9719 | case ARM::VLD4DUPdWB_register_Asm_8: | |||
9720 | case ARM::VLD4DUPdWB_register_Asm_16: | |||
9721 | case ARM::VLD4DUPdWB_register_Asm_32: | |||
9722 | case ARM::VLD4DUPqWB_register_Asm_8: | |||
9723 | case ARM::VLD4DUPqWB_register_Asm_16: | |||
9724 | case ARM::VLD4DUPqWB_register_Asm_32: { | |||
9725 | MCInst TmpInst; | |||
9726 | unsigned Spacing; | |||
9727 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9728 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9729 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9730 | Spacing)); | |||
9731 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9732 | Spacing * 2)); | |||
9733 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9734 | Spacing * 3)); | |||
9735 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9736 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9737 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9738 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9739 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9740 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9741 | Inst = TmpInst; | |||
9742 | return true; | |||
9743 | } | |||
9744 | ||||
9745 | // VLD4 multiple 4-element structure instructions. | |||
9746 | case ARM::VLD4dAsm_8: | |||
9747 | case ARM::VLD4dAsm_16: | |||
9748 | case ARM::VLD4dAsm_32: | |||
9749 | case ARM::VLD4qAsm_8: | |||
9750 | case ARM::VLD4qAsm_16: | |||
9751 | case ARM::VLD4qAsm_32: { | |||
9752 | MCInst TmpInst; | |||
9753 | unsigned Spacing; | |||
9754 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9755 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9756 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9757 | Spacing)); | |||
9758 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9759 | Spacing * 2)); | |||
9760 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9761 | Spacing * 3)); | |||
9762 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9763 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9764 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9765 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9766 | Inst = TmpInst; | |||
9767 | return true; | |||
9768 | } | |||
9769 | ||||
9770 | case ARM::VLD4dWB_fixed_Asm_8: | |||
9771 | case ARM::VLD4dWB_fixed_Asm_16: | |||
9772 | case ARM::VLD4dWB_fixed_Asm_32: | |||
9773 | case ARM::VLD4qWB_fixed_Asm_8: | |||
9774 | case ARM::VLD4qWB_fixed_Asm_16: | |||
9775 | case ARM::VLD4qWB_fixed_Asm_32: { | |||
9776 | MCInst TmpInst; | |||
9777 | unsigned Spacing; | |||
9778 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9779 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9780 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9781 | Spacing)); | |||
9782 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9783 | Spacing * 2)); | |||
9784 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9785 | Spacing * 3)); | |||
9786 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9787 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9788 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9789 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9790 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9791 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9792 | Inst = TmpInst; | |||
9793 | return true; | |||
9794 | } | |||
9795 | ||||
9796 | case ARM::VLD4dWB_register_Asm_8: | |||
9797 | case ARM::VLD4dWB_register_Asm_16: | |||
9798 | case ARM::VLD4dWB_register_Asm_32: | |||
9799 | case ARM::VLD4qWB_register_Asm_8: | |||
9800 | case ARM::VLD4qWB_register_Asm_16: | |||
9801 | case ARM::VLD4qWB_register_Asm_32: { | |||
9802 | MCInst TmpInst; | |||
9803 | unsigned Spacing; | |||
9804 | TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); | |||
9805 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9806 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9807 | Spacing)); | |||
9808 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9809 | Spacing * 2)); | |||
9810 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9811 | Spacing * 3)); | |||
9812 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9813 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9814 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9815 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9816 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9817 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9818 | Inst = TmpInst; | |||
9819 | return true; | |||
9820 | } | |||
9821 | ||||
9822 | // VST3 multiple 3-element structure instructions. | |||
9823 | case ARM::VST3dAsm_8: | |||
9824 | case ARM::VST3dAsm_16: | |||
9825 | case ARM::VST3dAsm_32: | |||
9826 | case ARM::VST3qAsm_8: | |||
9827 | case ARM::VST3qAsm_16: | |||
9828 | case ARM::VST3qAsm_32: { | |||
9829 | MCInst TmpInst; | |||
9830 | unsigned Spacing; | |||
9831 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9832 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9833 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9834 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9835 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9836 | Spacing)); | |||
9837 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9838 | Spacing * 2)); | |||
9839 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9840 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9841 | Inst = TmpInst; | |||
9842 | return true; | |||
9843 | } | |||
9844 | ||||
9845 | case ARM::VST3dWB_fixed_Asm_8: | |||
9846 | case ARM::VST3dWB_fixed_Asm_16: | |||
9847 | case ARM::VST3dWB_fixed_Asm_32: | |||
9848 | case ARM::VST3qWB_fixed_Asm_8: | |||
9849 | case ARM::VST3qWB_fixed_Asm_16: | |||
9850 | case ARM::VST3qWB_fixed_Asm_32: { | |||
9851 | MCInst TmpInst; | |||
9852 | unsigned Spacing; | |||
9853 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9854 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9855 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9856 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9857 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9858 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9859 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9860 | Spacing)); | |||
9861 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9862 | Spacing * 2)); | |||
9863 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9864 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9865 | Inst = TmpInst; | |||
9866 | return true; | |||
9867 | } | |||
9868 | ||||
9869 | case ARM::VST3dWB_register_Asm_8: | |||
9870 | case ARM::VST3dWB_register_Asm_16: | |||
9871 | case ARM::VST3dWB_register_Asm_32: | |||
9872 | case ARM::VST3qWB_register_Asm_8: | |||
9873 | case ARM::VST3qWB_register_Asm_16: | |||
9874 | case ARM::VST3qWB_register_Asm_32: { | |||
9875 | MCInst TmpInst; | |||
9876 | unsigned Spacing; | |||
9877 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9878 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9879 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9880 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9881 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9882 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9883 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9884 | Spacing)); | |||
9885 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9886 | Spacing * 2)); | |||
9887 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9888 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9889 | Inst = TmpInst; | |||
9890 | return true; | |||
9891 | } | |||
9892 | ||||
9893 | // VST4 multiple 3-element structure instructions. | |||
9894 | case ARM::VST4dAsm_8: | |||
9895 | case ARM::VST4dAsm_16: | |||
9896 | case ARM::VST4dAsm_32: | |||
9897 | case ARM::VST4qAsm_8: | |||
9898 | case ARM::VST4qAsm_16: | |||
9899 | case ARM::VST4qAsm_32: { | |||
9900 | MCInst TmpInst; | |||
9901 | unsigned Spacing; | |||
9902 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9903 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9904 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9905 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9906 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9907 | Spacing)); | |||
9908 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9909 | Spacing * 2)); | |||
9910 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9911 | Spacing * 3)); | |||
9912 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9913 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9914 | Inst = TmpInst; | |||
9915 | return true; | |||
9916 | } | |||
9917 | ||||
9918 | case ARM::VST4dWB_fixed_Asm_8: | |||
9919 | case ARM::VST4dWB_fixed_Asm_16: | |||
9920 | case ARM::VST4dWB_fixed_Asm_32: | |||
9921 | case ARM::VST4qWB_fixed_Asm_8: | |||
9922 | case ARM::VST4qWB_fixed_Asm_16: | |||
9923 | case ARM::VST4qWB_fixed_Asm_32: { | |||
9924 | MCInst TmpInst; | |||
9925 | unsigned Spacing; | |||
9926 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9927 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9928 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9929 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9930 | TmpInst.addOperand(MCOperand::createReg(0)); // Rm | |||
9931 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9932 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9933 | Spacing)); | |||
9934 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9935 | Spacing * 2)); | |||
9936 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9937 | Spacing * 3)); | |||
9938 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
9939 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9940 | Inst = TmpInst; | |||
9941 | return true; | |||
9942 | } | |||
9943 | ||||
9944 | case ARM::VST4dWB_register_Asm_8: | |||
9945 | case ARM::VST4dWB_register_Asm_16: | |||
9946 | case ARM::VST4dWB_register_Asm_32: | |||
9947 | case ARM::VST4qWB_register_Asm_8: | |||
9948 | case ARM::VST4qWB_register_Asm_16: | |||
9949 | case ARM::VST4qWB_register_Asm_32: { | |||
9950 | MCInst TmpInst; | |||
9951 | unsigned Spacing; | |||
9952 | TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); | |||
9953 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
9954 | TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn | |||
9955 | TmpInst.addOperand(Inst.getOperand(2)); // alignment | |||
9956 | TmpInst.addOperand(Inst.getOperand(3)); // Rm | |||
9957 | TmpInst.addOperand(Inst.getOperand(0)); // Vd | |||
9958 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9959 | Spacing)); | |||
9960 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9961 | Spacing * 2)); | |||
9962 | TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + | |||
9963 | Spacing * 3)); | |||
9964 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
9965 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9966 | Inst = TmpInst; | |||
9967 | return true; | |||
9968 | } | |||
9969 | ||||
9970 | // Handle encoding choice for the shift-immediate instructions. | |||
9971 | case ARM::t2LSLri: | |||
9972 | case ARM::t2LSRri: | |||
9973 | case ARM::t2ASRri: | |||
9974 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
9975 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
9976 | Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && | |||
9977 | !HasWideQualifier) { | |||
9978 | unsigned NewOpc; | |||
9979 | switch (Inst.getOpcode()) { | |||
9980 | default: llvm_unreachable("unexpected opcode")__builtin_unreachable(); | |||
9981 | case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; | |||
9982 | case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; | |||
9983 | case ARM::t2ASRri: NewOpc = ARM::tASRri; break; | |||
9984 | } | |||
9985 | // The Thumb1 operands aren't in the same order. Awesome, eh? | |||
9986 | MCInst TmpInst; | |||
9987 | TmpInst.setOpcode(NewOpc); | |||
9988 | TmpInst.addOperand(Inst.getOperand(0)); | |||
9989 | TmpInst.addOperand(Inst.getOperand(5)); | |||
9990 | TmpInst.addOperand(Inst.getOperand(1)); | |||
9991 | TmpInst.addOperand(Inst.getOperand(2)); | |||
9992 | TmpInst.addOperand(Inst.getOperand(3)); | |||
9993 | TmpInst.addOperand(Inst.getOperand(4)); | |||
9994 | Inst = TmpInst; | |||
9995 | return true; | |||
9996 | } | |||
9997 | return false; | |||
9998 | ||||
9999 | // Handle the Thumb2 mode MOV complex aliases. | |||
10000 | case ARM::t2MOVsr: | |||
10001 | case ARM::t2MOVSsr: { | |||
10002 | // Which instruction to expand to depends on the CCOut operand and | |||
10003 | // whether we're in an IT block if the register operands are low | |||
10004 | // registers. | |||
10005 | bool isNarrow = false; | |||
10006 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10007 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10008 | isARMLowRegister(Inst.getOperand(2).getReg()) && | |||
10009 | Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && | |||
10010 | inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && | |||
10011 | !HasWideQualifier) | |||
10012 | isNarrow = true; | |||
10013 | MCInst TmpInst; | |||
10014 | unsigned newOpc; | |||
10015 | switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { | |||
10016 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
10017 | case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; | |||
10018 | case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; | |||
10019 | case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; | |||
10020 | case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; | |||
10021 | } | |||
10022 | TmpInst.setOpcode(newOpc); | |||
10023 | TmpInst.addOperand(Inst.getOperand(0)); // Rd | |||
10024 | if (isNarrow) | |||
10025 | TmpInst.addOperand(MCOperand::createReg( | |||
10026 | Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); | |||
10027 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10028 | TmpInst.addOperand(Inst.getOperand(2)); // Rm | |||
10029 | TmpInst.addOperand(Inst.getOperand(4)); // CondCode | |||
10030 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10031 | if (!isNarrow) | |||
10032 | TmpInst.addOperand(MCOperand::createReg( | |||
10033 | Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); | |||
10034 | Inst = TmpInst; | |||
10035 | return true; | |||
10036 | } | |||
10037 | case ARM::t2MOVsi: | |||
10038 | case ARM::t2MOVSsi: { | |||
10039 | // Which instruction to expand to depends on the CCOut operand and | |||
10040 | // whether we're in an IT block if the register operands are low | |||
10041 | // registers. | |||
10042 | bool isNarrow = false; | |||
10043 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10044 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10045 | inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && | |||
10046 | !HasWideQualifier) | |||
10047 | isNarrow = true; | |||
10048 | MCInst TmpInst; | |||
10049 | unsigned newOpc; | |||
10050 | unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); | |||
10051 | unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); | |||
10052 | bool isMov = false; | |||
10053 | // MOV rd, rm, LSL #0 is actually a MOV instruction | |||
10054 | if (Shift == ARM_AM::lsl && Amount == 0) { | |||
10055 | isMov = true; | |||
10056 | // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of | |||
10057 | // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is | |||
10058 | // unpredictable in an IT block so the 32-bit encoding T3 has to be used | |||
10059 | // instead. | |||
10060 | if (inITBlock()) { | |||
10061 | isNarrow = false; | |||
10062 | } | |||
10063 | newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; | |||
10064 | } else { | |||
10065 | switch(Shift) { | |||
10066 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
10067 | case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; | |||
10068 | case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; | |||
10069 | case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; | |||
10070 | case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; | |||
10071 | case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; | |||
10072 | } | |||
10073 | } | |||
10074 | if (Amount == 32) Amount = 0; | |||
10075 | TmpInst.setOpcode(newOpc); | |||
10076 | TmpInst.addOperand(Inst.getOperand(0)); // Rd | |||
10077 | if (isNarrow && !isMov) | |||
10078 | TmpInst.addOperand(MCOperand::createReg( | |||
10079 | Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); | |||
10080 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10081 | if (newOpc != ARM::t2RRX && !isMov) | |||
10082 | TmpInst.addOperand(MCOperand::createImm(Amount)); | |||
10083 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
10084 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10085 | if (!isNarrow) | |||
10086 | TmpInst.addOperand(MCOperand::createReg( | |||
10087 | Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); | |||
10088 | Inst = TmpInst; | |||
10089 | return true; | |||
10090 | } | |||
10091 | // Handle the ARM mode MOV complex aliases. | |||
10092 | case ARM::ASRr: | |||
10093 | case ARM::LSRr: | |||
10094 | case ARM::LSLr: | |||
10095 | case ARM::RORr: { | |||
10096 | ARM_AM::ShiftOpc ShiftTy; | |||
10097 | switch(Inst.getOpcode()) { | |||
10098 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
10099 | case ARM::ASRr: ShiftTy = ARM_AM::asr; break; | |||
10100 | case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; | |||
10101 | case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; | |||
10102 | case ARM::RORr: ShiftTy = ARM_AM::ror; break; | |||
10103 | } | |||
10104 | unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); | |||
10105 | MCInst TmpInst; | |||
10106 | TmpInst.setOpcode(ARM::MOVsr); | |||
10107 | TmpInst.addOperand(Inst.getOperand(0)); // Rd | |||
10108 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10109 | TmpInst.addOperand(Inst.getOperand(2)); // Rm | |||
10110 | TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty | |||
10111 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
10112 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10113 | TmpInst.addOperand(Inst.getOperand(5)); // cc_out | |||
10114 | Inst = TmpInst; | |||
10115 | return true; | |||
10116 | } | |||
10117 | case ARM::ASRi: | |||
10118 | case ARM::LSRi: | |||
10119 | case ARM::LSLi: | |||
10120 | case ARM::RORi: { | |||
10121 | ARM_AM::ShiftOpc ShiftTy; | |||
10122 | switch(Inst.getOpcode()) { | |||
10123 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
10124 | case ARM::ASRi: ShiftTy = ARM_AM::asr; break; | |||
10125 | case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; | |||
10126 | case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; | |||
10127 | case ARM::RORi: ShiftTy = ARM_AM::ror; break; | |||
10128 | } | |||
10129 | // A shift by zero is a plain MOVr, not a MOVsi. | |||
10130 | unsigned Amt = Inst.getOperand(2).getImm(); | |||
10131 | unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; | |||
10132 | // A shift by 32 should be encoded as 0 when permitted | |||
10133 | if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) | |||
10134 | Amt = 0; | |||
10135 | unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); | |||
10136 | MCInst TmpInst; | |||
10137 | TmpInst.setOpcode(Opc); | |||
10138 | TmpInst.addOperand(Inst.getOperand(0)); // Rd | |||
10139 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10140 | if (Opc == ARM::MOVsi) | |||
10141 | TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty | |||
10142 | TmpInst.addOperand(Inst.getOperand(3)); // CondCode | |||
10143 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10144 | TmpInst.addOperand(Inst.getOperand(5)); // cc_out | |||
10145 | Inst = TmpInst; | |||
10146 | return true; | |||
10147 | } | |||
10148 | case ARM::RRXi: { | |||
10149 | unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); | |||
10150 | MCInst TmpInst; | |||
10151 | TmpInst.setOpcode(ARM::MOVsi); | |||
10152 | TmpInst.addOperand(Inst.getOperand(0)); // Rd | |||
10153 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10154 | TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty | |||
10155 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
10156 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10157 | TmpInst.addOperand(Inst.getOperand(4)); // cc_out | |||
10158 | Inst = TmpInst; | |||
10159 | return true; | |||
10160 | } | |||
10161 | case ARM::t2LDMIA_UPD: { | |||
10162 | // If this is a load of a single register, then we should use | |||
10163 | // a post-indexed LDR instruction instead, per the ARM ARM. | |||
10164 | if (Inst.getNumOperands() != 5) | |||
10165 | return false; | |||
10166 | MCInst TmpInst; | |||
10167 | TmpInst.setOpcode(ARM::t2LDR_POST); | |||
10168 | TmpInst.addOperand(Inst.getOperand(4)); // Rt | |||
10169 | TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb | |||
10170 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10171 | TmpInst.addOperand(MCOperand::createImm(4)); | |||
10172 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
10173 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10174 | Inst = TmpInst; | |||
10175 | return true; | |||
10176 | } | |||
10177 | case ARM::t2STMDB_UPD: { | |||
10178 | // If this is a store of a single register, then we should use | |||
10179 | // a pre-indexed STR instruction instead, per the ARM ARM. | |||
10180 | if (Inst.getNumOperands() != 5) | |||
10181 | return false; | |||
10182 | MCInst TmpInst; | |||
10183 | TmpInst.setOpcode(ARM::t2STR_PRE); | |||
10184 | TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb | |||
10185 | TmpInst.addOperand(Inst.getOperand(4)); // Rt | |||
10186 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10187 | TmpInst.addOperand(MCOperand::createImm(-4)); | |||
10188 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
10189 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10190 | Inst = TmpInst; | |||
10191 | return true; | |||
10192 | } | |||
10193 | case ARM::LDMIA_UPD: | |||
10194 | // If this is a load of a single register via a 'pop', then we should use | |||
10195 | // a post-indexed LDR instruction instead, per the ARM ARM. | |||
10196 | if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && | |||
10197 | Inst.getNumOperands() == 5) { | |||
10198 | MCInst TmpInst; | |||
10199 | TmpInst.setOpcode(ARM::LDR_POST_IMM); | |||
10200 | TmpInst.addOperand(Inst.getOperand(4)); // Rt | |||
10201 | TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb | |||
10202 | TmpInst.addOperand(Inst.getOperand(1)); // Rn | |||
10203 | TmpInst.addOperand(MCOperand::createReg(0)); // am2offset | |||
10204 | TmpInst.addOperand(MCOperand::createImm(4)); | |||
10205 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
10206 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10207 | Inst = TmpInst; | |||
10208 | return true; | |||
10209 | } | |||
10210 | break; | |||
10211 | case ARM::STMDB_UPD: | |||
10212 | // If this is a store of a single register via a 'push', then we should use | |||
10213 | // a pre-indexed STR instruction instead, per the ARM ARM. | |||
10214 | if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && | |||
10215 | Inst.getNumOperands() == 5) { | |||
10216 | MCInst TmpInst; | |||
10217 | TmpInst.setOpcode(ARM::STR_PRE_IMM); | |||
10218 | TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb | |||
10219 | TmpInst.addOperand(Inst.getOperand(4)); // Rt | |||
10220 | TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 | |||
10221 | TmpInst.addOperand(MCOperand::createImm(-4)); | |||
10222 | TmpInst.addOperand(Inst.getOperand(2)); // CondCode | |||
10223 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10224 | Inst = TmpInst; | |||
10225 | } | |||
10226 | break; | |||
10227 | case ARM::t2ADDri12: | |||
10228 | case ARM::t2SUBri12: | |||
10229 | case ARM::t2ADDspImm12: | |||
10230 | case ARM::t2SUBspImm12: { | |||
10231 | // If the immediate fits for encoding T3 and the generic | |||
10232 | // mnemonic was used, encoding T3 is preferred. | |||
10233 | const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken(); | |||
10234 | if ((Token != "add" && Token != "sub") || | |||
10235 | ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) | |||
10236 | break; | |||
10237 | switch (Inst.getOpcode()) { | |||
10238 | case ARM::t2ADDri12: | |||
10239 | Inst.setOpcode(ARM::t2ADDri); | |||
10240 | break; | |||
10241 | case ARM::t2SUBri12: | |||
10242 | Inst.setOpcode(ARM::t2SUBri); | |||
10243 | break; | |||
10244 | case ARM::t2ADDspImm12: | |||
10245 | Inst.setOpcode(ARM::t2ADDspImm); | |||
10246 | break; | |||
10247 | case ARM::t2SUBspImm12: | |||
10248 | Inst.setOpcode(ARM::t2SUBspImm); | |||
10249 | break; | |||
10250 | } | |||
10251 | ||||
10252 | Inst.addOperand(MCOperand::createReg(0)); // cc_out | |||
10253 | return true; | |||
10254 | } | |||
10255 | case ARM::tADDi8: | |||
10256 | // If the immediate is in the range 0-7, we want tADDi3 iff Rd was | |||
10257 | // explicitly specified. From the ARM ARM: "Encoding T1 is preferred | |||
10258 | // to encoding T2 if <Rd> is specified and encoding T2 is preferred | |||
10259 | // to encoding T1 if <Rd> is omitted." | |||
10260 | if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { | |||
10261 | Inst.setOpcode(ARM::tADDi3); | |||
10262 | return true; | |||
10263 | } | |||
10264 | break; | |||
10265 | case ARM::tSUBi8: | |||
10266 | // If the immediate is in the range 0-7, we want tADDi3 iff Rd was | |||
10267 | // explicitly specified. From the ARM ARM: "Encoding T1 is preferred | |||
10268 | // to encoding T2 if <Rd> is specified and encoding T2 is preferred | |||
10269 | // to encoding T1 if <Rd> is omitted." | |||
10270 | if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { | |||
10271 | Inst.setOpcode(ARM::tSUBi3); | |||
10272 | return true; | |||
10273 | } | |||
10274 | break; | |||
10275 | case ARM::t2ADDri: | |||
10276 | case ARM::t2SUBri: { | |||
10277 | // If the destination and first source operand are the same, and | |||
10278 | // the flags are compatible with the current IT status, use encoding T2 | |||
10279 | // instead of T3. For compatibility with the system 'as'. Make sure the | |||
10280 | // wide encoding wasn't explicit. | |||
10281 | if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || | |||
10282 | !isARMLowRegister(Inst.getOperand(0).getReg()) || | |||
10283 | (Inst.getOperand(2).isImm() && | |||
10284 | (unsigned)Inst.getOperand(2).getImm() > 255) || | |||
10285 | Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || | |||
10286 | HasWideQualifier) | |||
10287 | break; | |||
10288 | MCInst TmpInst; | |||
10289 | TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? | |||
10290 | ARM::tADDi8 : ARM::tSUBi8); | |||
10291 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10292 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10293 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10294 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10295 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10296 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10297 | Inst = TmpInst; | |||
10298 | return true; | |||
10299 | } | |||
10300 | case ARM::t2ADDspImm: | |||
10301 | case ARM::t2SUBspImm: { | |||
10302 | // Prefer T1 encoding if possible | |||
10303 | if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier) | |||
10304 | break; | |||
10305 | unsigned V = Inst.getOperand(2).getImm(); | |||
10306 | if (V & 3 || V > ((1 << 7) - 1) << 2) | |||
10307 | break; | |||
10308 | MCInst TmpInst; | |||
10309 | TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi | |||
10310 | : ARM::tSUBspi); | |||
10311 | TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg | |||
10312 | TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg | |||
10313 | TmpInst.addOperand(MCOperand::createImm(V / 4)); // immediate | |||
10314 | TmpInst.addOperand(Inst.getOperand(3)); // pred | |||
10315 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10316 | Inst = TmpInst; | |||
10317 | return true; | |||
10318 | } | |||
10319 | case ARM::t2ADDrr: { | |||
10320 | // If the destination and first source operand are the same, and | |||
10321 | // there's no setting of the flags, use encoding T2 instead of T3. | |||
10322 | // Note that this is only for ADD, not SUB. This mirrors the system | |||
10323 | // 'as' behaviour. Also take advantage of ADD being commutative. | |||
10324 | // Make sure the wide encoding wasn't explicit. | |||
10325 | bool Swap = false; | |||
10326 | auto DestReg = Inst.getOperand(0).getReg(); | |||
10327 | bool Transform = DestReg == Inst.getOperand(1).getReg(); | |||
10328 | if (!Transform && DestReg == Inst.getOperand(2).getReg()) { | |||
10329 | Transform = true; | |||
10330 | Swap = true; | |||
10331 | } | |||
10332 | if (!Transform || | |||
10333 | Inst.getOperand(5).getReg() != 0 || | |||
10334 | HasWideQualifier) | |||
10335 | break; | |||
10336 | MCInst TmpInst; | |||
10337 | TmpInst.setOpcode(ARM::tADDhirr); | |||
10338 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10339 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10340 | TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); | |||
10341 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10342 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10343 | Inst = TmpInst; | |||
10344 | return true; | |||
10345 | } | |||
10346 | case ARM::tADDrSP: | |||
10347 | // If the non-SP source operand and the destination operand are not the | |||
10348 | // same, we need to use the 32-bit encoding if it's available. | |||
10349 | if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { | |||
10350 | Inst.setOpcode(ARM::t2ADDrr); | |||
10351 | Inst.addOperand(MCOperand::createReg(0)); // cc_out | |||
10352 | return true; | |||
10353 | } | |||
10354 | break; | |||
10355 | case ARM::tB: | |||
10356 | // A Thumb conditional branch outside of an IT block is a tBcc. | |||
10357 | if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { | |||
10358 | Inst.setOpcode(ARM::tBcc); | |||
10359 | return true; | |||
10360 | } | |||
10361 | break; | |||
10362 | case ARM::t2B: | |||
10363 | // A Thumb2 conditional branch outside of an IT block is a t2Bcc. | |||
10364 | if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ | |||
10365 | Inst.setOpcode(ARM::t2Bcc); | |||
10366 | return true; | |||
10367 | } | |||
10368 | break; | |||
10369 | case ARM::t2Bcc: | |||
10370 | // If the conditional is AL or we're in an IT block, we really want t2B. | |||
10371 | if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { | |||
10372 | Inst.setOpcode(ARM::t2B); | |||
10373 | return true; | |||
10374 | } | |||
10375 | break; | |||
10376 | case ARM::tBcc: | |||
10377 | // If the conditional is AL, we really want tB. | |||
10378 | if (Inst.getOperand(1).getImm() == ARMCC::AL) { | |||
10379 | Inst.setOpcode(ARM::tB); | |||
10380 | return true; | |||
10381 | } | |||
10382 | break; | |||
10383 | case ARM::tLDMIA: { | |||
10384 | // If the register list contains any high registers, or if the writeback | |||
10385 | // doesn't match what tLDMIA can do, we need to use the 32-bit encoding | |||
10386 | // instead if we're in Thumb2. Otherwise, this should have generated | |||
10387 | // an error in validateInstruction(). | |||
10388 | unsigned Rn = Inst.getOperand(0).getReg(); | |||
10389 | bool hasWritebackToken = | |||
10390 | (static_cast<ARMOperand &>(*Operands[3]).isToken() && | |||
10391 | static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); | |||
10392 | bool listContainsBase; | |||
10393 | if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || | |||
10394 | (!listContainsBase && !hasWritebackToken) || | |||
10395 | (listContainsBase && hasWritebackToken)) { | |||
10396 | // 16-bit encoding isn't sufficient. Switch to the 32-bit version. | |||
10397 | assert(isThumbTwo())(static_cast<void> (0)); | |||
10398 | Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); | |||
10399 | // If we're switching to the updating version, we need to insert | |||
10400 | // the writeback tied operand. | |||
10401 | if (hasWritebackToken) | |||
10402 | Inst.insert(Inst.begin(), | |||
10403 | MCOperand::createReg(Inst.getOperand(0).getReg())); | |||
10404 | return true; | |||
10405 | } | |||
10406 | break; | |||
10407 | } | |||
10408 | case ARM::tSTMIA_UPD: { | |||
10409 | // If the register list contains any high registers, we need to use | |||
10410 | // the 32-bit encoding instead if we're in Thumb2. Otherwise, this | |||
10411 | // should have generated an error in validateInstruction(). | |||
10412 | unsigned Rn = Inst.getOperand(0).getReg(); | |||
10413 | bool listContainsBase; | |||
10414 | if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { | |||
10415 | // 16-bit encoding isn't sufficient. Switch to the 32-bit version. | |||
10416 | assert(isThumbTwo())(static_cast<void> (0)); | |||
10417 | Inst.setOpcode(ARM::t2STMIA_UPD); | |||
10418 | return true; | |||
10419 | } | |||
10420 | break; | |||
10421 | } | |||
10422 | case ARM::tPOP: { | |||
10423 | bool listContainsBase; | |||
10424 | // If the register list contains any high registers, we need to use | |||
10425 | // the 32-bit encoding instead if we're in Thumb2. Otherwise, this | |||
10426 | // should have generated an error in validateInstruction(). | |||
10427 | if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) | |||
10428 | return false; | |||
10429 | assert(isThumbTwo())(static_cast<void> (0)); | |||
10430 | Inst.setOpcode(ARM::t2LDMIA_UPD); | |||
10431 | // Add the base register and writeback operands. | |||
10432 | Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); | |||
10433 | Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); | |||
10434 | return true; | |||
10435 | } | |||
10436 | case ARM::tPUSH: { | |||
10437 | bool listContainsBase; | |||
10438 | if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) | |||
10439 | return false; | |||
10440 | assert(isThumbTwo())(static_cast<void> (0)); | |||
10441 | Inst.setOpcode(ARM::t2STMDB_UPD); | |||
10442 | // Add the base register and writeback operands. | |||
10443 | Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); | |||
10444 | Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); | |||
10445 | return true; | |||
10446 | } | |||
10447 | case ARM::t2MOVi: | |||
10448 | // If we can use the 16-bit encoding and the user didn't explicitly | |||
10449 | // request the 32-bit variant, transform it here. | |||
10450 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10451 | (Inst.getOperand(1).isImm() && | |||
10452 | (unsigned)Inst.getOperand(1).getImm() <= 255) && | |||
10453 | Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && | |||
10454 | !HasWideQualifier) { | |||
10455 | // The operands aren't in the same order for tMOVi8... | |||
10456 | MCInst TmpInst; | |||
10457 | TmpInst.setOpcode(ARM::tMOVi8); | |||
10458 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10459 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10460 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10461 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10462 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10463 | Inst = TmpInst; | |||
10464 | return true; | |||
10465 | } | |||
10466 | break; | |||
10467 | ||||
10468 | case ARM::t2MOVr: | |||
10469 | // If we can use the 16-bit encoding and the user didn't explicitly | |||
10470 | // request the 32-bit variant, transform it here. | |||
10471 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10472 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10473 | Inst.getOperand(2).getImm() == ARMCC::AL && | |||
10474 | Inst.getOperand(4).getReg() == ARM::CPSR && | |||
10475 | !HasWideQualifier) { | |||
10476 | // The operands aren't the same for tMOV[S]r... (no cc_out) | |||
10477 | MCInst TmpInst; | |||
10478 | unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr; | |||
10479 | TmpInst.setOpcode(Op); | |||
10480 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10481 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10482 | if (Op == ARM::tMOVr) { | |||
10483 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10484 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10485 | } | |||
10486 | Inst = TmpInst; | |||
10487 | return true; | |||
10488 | } | |||
10489 | break; | |||
10490 | ||||
10491 | case ARM::t2SXTH: | |||
10492 | case ARM::t2SXTB: | |||
10493 | case ARM::t2UXTH: | |||
10494 | case ARM::t2UXTB: | |||
10495 | // If we can use the 16-bit encoding and the user didn't explicitly | |||
10496 | // request the 32-bit variant, transform it here. | |||
10497 | if (isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10498 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10499 | Inst.getOperand(2).getImm() == 0 && | |||
10500 | !HasWideQualifier) { | |||
10501 | unsigned NewOpc; | |||
10502 | switch (Inst.getOpcode()) { | |||
10503 | default: llvm_unreachable("Illegal opcode!")__builtin_unreachable(); | |||
10504 | case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; | |||
10505 | case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; | |||
10506 | case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; | |||
10507 | case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; | |||
10508 | } | |||
10509 | // The operands aren't the same for thumb1 (no rotate operand). | |||
10510 | MCInst TmpInst; | |||
10511 | TmpInst.setOpcode(NewOpc); | |||
10512 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10513 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10514 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10515 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10516 | Inst = TmpInst; | |||
10517 | return true; | |||
10518 | } | |||
10519 | break; | |||
10520 | ||||
10521 | case ARM::MOVsi: { | |||
10522 | ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); | |||
10523 | // rrx shifts and asr/lsr of #32 is encoded as 0 | |||
10524 | if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) | |||
10525 | return false; | |||
10526 | if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { | |||
10527 | // Shifting by zero is accepted as a vanilla 'MOVr' | |||
10528 | MCInst TmpInst; | |||
10529 | TmpInst.setOpcode(ARM::MOVr); | |||
10530 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10531 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10532 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10533 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10534 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10535 | Inst = TmpInst; | |||
10536 | return true; | |||
10537 | } | |||
10538 | return false; | |||
10539 | } | |||
10540 | case ARM::ANDrsi: | |||
10541 | case ARM::ORRrsi: | |||
10542 | case ARM::EORrsi: | |||
10543 | case ARM::BICrsi: | |||
10544 | case ARM::SUBrsi: | |||
10545 | case ARM::ADDrsi: { | |||
10546 | unsigned newOpc; | |||
10547 | ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); | |||
10548 | if (SOpc == ARM_AM::rrx) return false; | |||
10549 | switch (Inst.getOpcode()) { | |||
10550 | default: llvm_unreachable("unexpected opcode!")__builtin_unreachable(); | |||
10551 | case ARM::ANDrsi: newOpc = ARM::ANDrr; break; | |||
10552 | case ARM::ORRrsi: newOpc = ARM::ORRrr; break; | |||
10553 | case ARM::EORrsi: newOpc = ARM::EORrr; break; | |||
10554 | case ARM::BICrsi: newOpc = ARM::BICrr; break; | |||
10555 | case ARM::SUBrsi: newOpc = ARM::SUBrr; break; | |||
10556 | case ARM::ADDrsi: newOpc = ARM::ADDrr; break; | |||
10557 | } | |||
10558 | // If the shift is by zero, use the non-shifted instruction definition. | |||
10559 | // The exception is for right shifts, where 0 == 32 | |||
10560 | if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && | |||
10561 | !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { | |||
10562 | MCInst TmpInst; | |||
10563 | TmpInst.setOpcode(newOpc); | |||
10564 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10565 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10566 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10567 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10568 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10569 | TmpInst.addOperand(Inst.getOperand(6)); | |||
10570 | Inst = TmpInst; | |||
10571 | return true; | |||
10572 | } | |||
10573 | return false; | |||
10574 | } | |||
10575 | case ARM::ITasm: | |||
10576 | case ARM::t2IT: { | |||
10577 | // Set up the IT block state according to the IT instruction we just | |||
10578 | // matched. | |||
10579 | assert(!inITBlock() && "nested IT blocks?!")(static_cast<void> (0)); | |||
10580 | startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()), | |||
10581 | Inst.getOperand(1).getImm()); | |||
10582 | break; | |||
10583 | } | |||
10584 | case ARM::t2LSLrr: | |||
10585 | case ARM::t2LSRrr: | |||
10586 | case ARM::t2ASRrr: | |||
10587 | case ARM::t2SBCrr: | |||
10588 | case ARM::t2RORrr: | |||
10589 | case ARM::t2BICrr: | |||
10590 | // Assemblers should use the narrow encodings of these instructions when permissible. | |||
10591 | if ((isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10592 | isARMLowRegister(Inst.getOperand(2).getReg())) && | |||
10593 | Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && | |||
10594 | Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && | |||
10595 | !HasWideQualifier) { | |||
10596 | unsigned NewOpc; | |||
10597 | switch (Inst.getOpcode()) { | |||
10598 | default: llvm_unreachable("unexpected opcode")__builtin_unreachable(); | |||
10599 | case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; | |||
10600 | case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; | |||
10601 | case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; | |||
10602 | case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; | |||
10603 | case ARM::t2RORrr: NewOpc = ARM::tROR; break; | |||
10604 | case ARM::t2BICrr: NewOpc = ARM::tBIC; break; | |||
10605 | } | |||
10606 | MCInst TmpInst; | |||
10607 | TmpInst.setOpcode(NewOpc); | |||
10608 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10609 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10610 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10611 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10612 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10613 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10614 | Inst = TmpInst; | |||
10615 | return true; | |||
10616 | } | |||
10617 | return false; | |||
10618 | ||||
10619 | case ARM::t2ANDrr: | |||
10620 | case ARM::t2EORrr: | |||
10621 | case ARM::t2ADCrr: | |||
10622 | case ARM::t2ORRrr: | |||
10623 | // Assemblers should use the narrow encodings of these instructions when permissible. | |||
10624 | // These instructions are special in that they are commutable, so shorter encodings | |||
10625 | // are available more often. | |||
10626 | if ((isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10627 | isARMLowRegister(Inst.getOperand(2).getReg())) && | |||
10628 | (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || | |||
10629 | Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && | |||
10630 | Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && | |||
10631 | !HasWideQualifier) { | |||
10632 | unsigned NewOpc; | |||
10633 | switch (Inst.getOpcode()) { | |||
10634 | default: llvm_unreachable("unexpected opcode")__builtin_unreachable(); | |||
10635 | case ARM::t2ADCrr: NewOpc = ARM::tADC; break; | |||
10636 | case ARM::t2ANDrr: NewOpc = ARM::tAND; break; | |||
10637 | case ARM::t2EORrr: NewOpc = ARM::tEOR; break; | |||
10638 | case ARM::t2ORRrr: NewOpc = ARM::tORR; break; | |||
10639 | } | |||
10640 | MCInst TmpInst; | |||
10641 | TmpInst.setOpcode(NewOpc); | |||
10642 | TmpInst.addOperand(Inst.getOperand(0)); | |||
10643 | TmpInst.addOperand(Inst.getOperand(5)); | |||
10644 | if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { | |||
10645 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10646 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10647 | } else { | |||
10648 | TmpInst.addOperand(Inst.getOperand(2)); | |||
10649 | TmpInst.addOperand(Inst.getOperand(1)); | |||
10650 | } | |||
10651 | TmpInst.addOperand(Inst.getOperand(3)); | |||
10652 | TmpInst.addOperand(Inst.getOperand(4)); | |||
10653 | Inst = TmpInst; | |||
10654 | return true; | |||
10655 | } | |||
10656 | return false; | |||
10657 | case ARM::MVE_VPST: | |||
10658 | case ARM::MVE_VPTv16i8: | |||
10659 | case ARM::MVE_VPTv8i16: | |||
10660 | case ARM::MVE_VPTv4i32: | |||
10661 | case ARM::MVE_VPTv16u8: | |||
10662 | case ARM::MVE_VPTv8u16: | |||
10663 | case ARM::MVE_VPTv4u32: | |||
10664 | case ARM::MVE_VPTv16s8: | |||
10665 | case ARM::MVE_VPTv8s16: | |||
10666 | case ARM::MVE_VPTv4s32: | |||
10667 | case ARM::MVE_VPTv4f32: | |||
10668 | case ARM::MVE_VPTv8f16: | |||
10669 | case ARM::MVE_VPTv16i8r: | |||
10670 | case ARM::MVE_VPTv8i16r: | |||
10671 | case ARM::MVE_VPTv4i32r: | |||
10672 | case ARM::MVE_VPTv16u8r: | |||
10673 | case ARM::MVE_VPTv8u16r: | |||
10674 | case ARM::MVE_VPTv4u32r: | |||
10675 | case ARM::MVE_VPTv16s8r: | |||
10676 | case ARM::MVE_VPTv8s16r: | |||
10677 | case ARM::MVE_VPTv4s32r: | |||
10678 | case ARM::MVE_VPTv4f32r: | |||
10679 | case ARM::MVE_VPTv8f16r: { | |||
10680 | assert(!inVPTBlock() && "Nested VPT blocks are not allowed")(static_cast<void> (0)); | |||
10681 | MCOperand &MO = Inst.getOperand(0); | |||
10682 | VPTState.Mask = MO.getImm(); | |||
10683 | VPTState.CurPosition = 0; | |||
10684 | break; | |||
10685 | } | |||
10686 | } | |||
10687 | return false; | |||
10688 | } | |||
10689 | ||||
10690 | unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { | |||
10691 | // 16-bit thumb arithmetic instructions either require or preclude the 'S' | |||
10692 | // suffix depending on whether they're in an IT block or not. | |||
10693 | unsigned Opc = Inst.getOpcode(); | |||
10694 | const MCInstrDesc &MCID = MII.get(Opc); | |||
10695 | if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { | |||
10696 | assert(MCID.hasOptionalDef() &&(static_cast<void> (0)) | |||
10697 | "optionally flag setting instruction missing optional def operand")(static_cast<void> (0)); | |||
10698 | assert(MCID.NumOperands == Inst.getNumOperands() &&(static_cast<void> (0)) | |||
10699 | "operand count mismatch!")(static_cast<void> (0)); | |||
10700 | // Find the optional-def operand (cc_out). | |||
10701 | unsigned OpNo; | |||
10702 | for (OpNo = 0; | |||
10703 | !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; | |||
10704 | ++OpNo) | |||
10705 | ; | |||
10706 | // If we're parsing Thumb1, reject it completely. | |||
10707 | if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) | |||
10708 | return Match_RequiresFlagSetting; | |||
10709 | // If we're parsing Thumb2, which form is legal depends on whether we're | |||
10710 | // in an IT block. | |||
10711 | if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && | |||
10712 | !inITBlock()) | |||
10713 | return Match_RequiresITBlock; | |||
10714 | if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && | |||
10715 | inITBlock()) | |||
10716 | return Match_RequiresNotITBlock; | |||
10717 | // LSL with zero immediate is not allowed in an IT block | |||
10718 | if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) | |||
10719 | return Match_RequiresNotITBlock; | |||
10720 | } else if (isThumbOne()) { | |||
10721 | // Some high-register supporting Thumb1 encodings only allow both registers | |||
10722 | // to be from r0-r7 when in Thumb2. | |||
10723 | if (Opc == ARM::tADDhirr && !hasV6MOps() && | |||
10724 | isARMLowRegister(Inst.getOperand(1).getReg()) && | |||
10725 | isARMLowRegister(Inst.getOperand(2).getReg())) | |||
10726 | return Match_RequiresThumb2; | |||
10727 | // Others only require ARMv6 or later. | |||
10728 | else if (Opc == ARM::tMOVr && !hasV6Ops() && | |||
10729 | isARMLowRegister(Inst.getOperand(0).getReg()) && | |||
10730 | isARMLowRegister(Inst.getOperand(1).getReg())) | |||
10731 | return Match_RequiresV6; | |||
10732 | } | |||
10733 | ||||
10734 | // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex | |||
10735 | // than the loop below can handle, so it uses the GPRnopc register class and | |||
10736 | // we do SP handling here. | |||
10737 | if (Opc == ARM::t2MOVr && !hasV8Ops()) | |||
10738 | { | |||
10739 | // SP as both source and destination is not allowed | |||
10740 | if (Inst.getOperand(0).getReg() == ARM::SP && | |||
10741 | Inst.getOperand(1).getReg() == ARM::SP) | |||
10742 | return Match_RequiresV8; | |||
10743 | // When flags-setting SP as either source or destination is not allowed | |||
10744 | if (Inst.getOperand(4).getReg() == ARM::CPSR && | |||
10745 | (Inst.getOperand(0).getReg() == ARM::SP || | |||
10746 | Inst.getOperand(1).getReg() == ARM::SP)) | |||
10747 | return Match_RequiresV8; | |||
10748 | } | |||
10749 | ||||
10750 | switch (Inst.getOpcode()) { | |||
10751 | case ARM::VMRS: | |||
10752 | case ARM::VMSR: | |||
10753 | case ARM::VMRS_FPCXTS: | |||
10754 | case ARM::VMRS_FPCXTNS: | |||
10755 | case ARM::VMSR_FPCXTS: | |||
10756 | case ARM::VMSR_FPCXTNS: | |||
10757 | case ARM::VMRS_FPSCR_NZCVQC: | |||
10758 | case ARM::VMSR_FPSCR_NZCVQC: | |||
10759 | case ARM::FMSTAT: | |||
10760 | case ARM::VMRS_VPR: | |||
10761 | case ARM::VMRS_P0: | |||
10762 | case ARM::VMSR_VPR: | |||
10763 | case ARM::VMSR_P0: | |||
10764 | // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of | |||
10765 | // ARMv8-A. | |||
10766 | if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && | |||
10767 | (isThumb() && !hasV8Ops())) | |||
10768 | return Match_InvalidOperand; | |||
10769 | break; | |||
10770 | case ARM::t2TBB: | |||
10771 | case ARM::t2TBH: | |||
10772 | // Rn = sp is only allowed with ARMv8-A | |||
10773 | if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP)) | |||
10774 | return Match_RequiresV8; | |||
10775 | break; | |||
10776 | default: | |||
10777 | break; | |||
10778 | } | |||
10779 | ||||
10780 | for (unsigned I = 0; I < MCID.NumOperands; ++I) | |||
10781 | if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { | |||
10782 | // rGPRRegClass excludes PC, and also excluded SP before ARMv8 | |||
10783 | const auto &Op = Inst.getOperand(I); | |||
10784 | if (!Op.isReg()) { | |||
10785 | // This can happen in awkward cases with tied operands, e.g. a | |||
10786 | // writeback load/store with a complex addressing mode in | |||
10787 | // which there's an output operand corresponding to the | |||
10788 | // updated written-back base register: the Tablegen-generated | |||
10789 | // AsmMatcher will have written a placeholder operand to that | |||
10790 | // slot in the form of an immediate 0, because it can't | |||
10791 | // generate the register part of the complex addressing-mode | |||
10792 | // operand ahead of time. | |||
10793 | continue; | |||
10794 | } | |||
10795 | ||||
10796 | unsigned Reg = Op.getReg(); | |||
10797 | if ((Reg == ARM::SP) && !hasV8Ops()) | |||
10798 | return Match_RequiresV8; | |||
10799 | else if (Reg == ARM::PC) | |||
10800 | return Match_InvalidOperand; | |||
10801 | } | |||
10802 | ||||
10803 | return Match_Success; | |||
10804 | } | |||
10805 | ||||
10806 | namespace llvm { | |||
10807 | ||||
10808 | template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) { | |||
10809 | return true; // In an assembly source, no need to second-guess | |||
10810 | } | |||
10811 | ||||
10812 | } // end namespace llvm | |||
10813 | ||||
10814 | // Returns true if Inst is unpredictable if it is in and IT block, but is not | |||
10815 | // the last instruction in the block. | |||
10816 | bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const { | |||
10817 | const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); | |||
10818 | ||||
10819 | // All branch & call instructions terminate IT blocks with the exception of | |||
10820 | // SVC. | |||
10821 | if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || | |||
10822 | MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch()) | |||
10823 | return true; | |||
10824 | ||||
10825 | // Any arithmetic instruction which writes to the PC also terminates the IT | |||
10826 | // block. | |||
10827 | if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) | |||
10828 | return true; | |||
10829 | ||||
10830 | return false; | |||
10831 | } | |||
10832 | ||||
10833 | unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, | |||
10834 | SmallVectorImpl<NearMissInfo> &NearMisses, | |||
10835 | bool MatchingInlineAsm, | |||
10836 | bool &EmitInITBlock, | |||
10837 | MCStreamer &Out) { | |||
10838 | // If we can't use an implicit IT block here, just match as normal. | |||
10839 | if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb()) | |||
10840 | return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); | |||
10841 | ||||
10842 | // Try to match the instruction in an extension of the current IT block (if | |||
10843 | // there is one). | |||
10844 | if (inImplicitITBlock()) { | |||
10845 | extendImplicitITBlock(ITState.Cond); | |||
10846 | if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == | |||
10847 | Match_Success) { | |||
10848 | // The match succeded, but we still have to check that the instruction is | |||
10849 | // valid in this implicit IT block. | |||
10850 | const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); | |||
10851 | if (MCID.isPredicable()) { | |||
10852 | ARMCC::CondCodes InstCond = | |||
10853 | (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) | |||
10854 | .getImm(); | |||
10855 | ARMCC::CondCodes ITCond = currentITCond(); | |||
10856 | if (InstCond == ITCond) { | |||
10857 | EmitInITBlock = true; | |||
10858 | return Match_Success; | |||
10859 | } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) { | |||
10860 | invertCurrentITCondition(); | |||
10861 | EmitInITBlock = true; | |||
10862 | return Match_Success; | |||
10863 | } | |||
10864 | } | |||
10865 | } | |||
10866 | rewindImplicitITPosition(); | |||
10867 | } | |||
10868 | ||||
10869 | // Finish the current IT block, and try to match outside any IT block. | |||
10870 | flushPendingInstructions(Out); | |||
10871 | unsigned PlainMatchResult = | |||
10872 | MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); | |||
10873 | if (PlainMatchResult == Match_Success) { | |||
10874 | const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); | |||
10875 | if (MCID.isPredicable()) { | |||
10876 | ARMCC::CondCodes InstCond = | |||
10877 | (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) | |||
10878 | .getImm(); | |||
10879 | // Some forms of the branch instruction have their own condition code | |||
10880 | // fields, so can be conditionally executed without an IT block. | |||
10881 | if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { | |||
10882 | EmitInITBlock = false; | |||
10883 | return Match_Success; | |||
10884 | } | |||
10885 | if (InstCond == ARMCC::AL) { | |||
10886 | EmitInITBlock = false; | |||
10887 | return Match_Success; | |||
10888 | } | |||
10889 | } else { | |||
10890 | EmitInITBlock = false; | |||
10891 | return Match_Success; | |||
10892 | } | |||
10893 | } | |||
10894 | ||||
10895 | // Try to match in a new IT block. The matcher doesn't check the actual | |||
10896 | // condition, so we create an IT block with a dummy condition, and fix it up | |||
10897 | // once we know the actual condition. | |||
10898 | startImplicitITBlock(); | |||
10899 | if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == | |||
10900 | Match_Success) { | |||
10901 | const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); | |||
10902 | if (MCID.isPredicable()) { | |||
10903 | ITState.Cond = | |||
10904 | (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) | |||
10905 | .getImm(); | |||
10906 | EmitInITBlock = true; | |||
10907 | return Match_Success; | |||
10908 | } | |||
10909 | } | |||
10910 | discardImplicitITBlock(); | |||
10911 | ||||
10912 | // If none of these succeed, return the error we got when trying to match | |||
10913 | // outside any IT blocks. | |||
10914 | EmitInITBlock = false; | |||
10915 | return PlainMatchResult; | |||
10916 | } | |||
10917 | ||||
10918 | static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, | |||
10919 | unsigned VariantID = 0); | |||
10920 | ||||
10921 | static const char *getSubtargetFeatureName(uint64_t Val); | |||
10922 | bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |||
10923 | OperandVector &Operands, | |||
10924 | MCStreamer &Out, uint64_t &ErrorInfo, | |||
10925 | bool MatchingInlineAsm) { | |||
10926 | MCInst Inst; | |||
10927 | unsigned MatchResult; | |||
10928 | bool PendConditionalInstruction = false; | |||
10929 | ||||
10930 | SmallVector<NearMissInfo, 4> NearMisses; | |||
10931 | MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, | |||
10932 | PendConditionalInstruction, Out); | |||
10933 | ||||
10934 | switch (MatchResult) { | |||
10935 | case Match_Success: | |||
10936 | LLVM_DEBUG(dbgs() << "Parsed as: ";do { } while (false) | |||
10937 | Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { } while (false) | |||
10938 | dbgs() << "\n")do { } while (false); | |||
10939 | ||||
10940 | // Context sensitive operand constraints aren't handled by the matcher, | |||
10941 | // so check them here. | |||
10942 | if (validateInstruction(Inst, Operands)) { | |||
10943 | // Still progress the IT block, otherwise one wrong condition causes | |||
10944 | // nasty cascading errors. | |||
10945 | forwardITPosition(); | |||
10946 | forwardVPTPosition(); | |||
10947 | return true; | |||
10948 | } | |||
10949 | ||||
10950 | { // processInstruction() updates inITBlock state, we need to save it away | |||
10951 | bool wasInITBlock = inITBlock(); | |||
10952 | ||||
10953 | // Some instructions need post-processing to, for example, tweak which | |||
10954 | // encoding is selected. Loop on it while changes happen so the | |||
10955 | // individual transformations can chain off each other. E.g., | |||
10956 | // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) | |||
10957 | while (processInstruction(Inst, Operands, Out)) | |||
10958 | LLVM_DEBUG(dbgs() << "Changed to: ";do { } while (false) | |||
10959 | Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { } while (false) | |||
10960 | dbgs() << "\n")do { } while (false); | |||
10961 | ||||
10962 | // Only after the instruction is fully processed, we can validate it | |||
10963 | if (wasInITBlock && hasV8Ops() && isThumb() && | |||
10964 | !isV8EligibleForIT(&Inst)) { | |||
10965 | Warning(IDLoc, "deprecated instruction in IT block"); | |||
10966 | } | |||
10967 | } | |||
10968 | ||||
10969 | // Only move forward at the very end so that everything in validate | |||
10970 | // and process gets a consistent answer about whether we're in an IT | |||
10971 | // block. | |||
10972 | forwardITPosition(); | |||
10973 | forwardVPTPosition(); | |||
10974 | ||||
10975 | // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and | |||
10976 | // doesn't actually encode. | |||
10977 | if (Inst.getOpcode() == ARM::ITasm) | |||
10978 | return false; | |||
10979 | ||||
10980 | Inst.setLoc(IDLoc); | |||
10981 | if (PendConditionalInstruction) { | |||
10982 | PendingConditionalInsts.push_back(Inst); | |||
10983 | if (isITBlockFull() || isITBlockTerminator(Inst)) | |||
10984 | flushPendingInstructions(Out); | |||
10985 | } else { | |||
10986 | Out.emitInstruction(Inst, getSTI()); | |||
10987 | } | |||
10988 | return false; | |||
10989 | case Match_NearMisses: | |||
10990 | ReportNearMisses(NearMisses, IDLoc, Operands); | |||
10991 | return true; | |||
10992 | case Match_MnemonicFail: { | |||
10993 | FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); | |||
10994 | std::string Suggestion = ARMMnemonicSpellCheck( | |||
10995 | ((ARMOperand &)*Operands[0]).getToken(), FBS); | |||
10996 | return Error(IDLoc, "invalid instruction" + Suggestion, | |||
10997 | ((ARMOperand &)*Operands[0]).getLocRange()); | |||
10998 | } | |||
10999 | } | |||
11000 | ||||
11001 | llvm_unreachable("Implement any new match types added!")__builtin_unreachable(); | |||
11002 | } | |||
11003 | ||||
11004 | /// parseDirective parses the arm specific directives | |||
11005 | bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { | |||
11006 | const MCContext::Environment Format = getContext().getObjectFileType(); | |||
11007 | bool IsMachO = Format == MCContext::IsMachO; | |||
11008 | bool IsCOFF = Format == MCContext::IsCOFF; | |||
11009 | ||||
11010 | std::string IDVal = DirectiveID.getIdentifier().lower(); | |||
11011 | if (IDVal == ".word") | |||
11012 | parseLiteralValues(4, DirectiveID.getLoc()); | |||
11013 | else if (IDVal == ".short" || IDVal == ".hword") | |||
11014 | parseLiteralValues(2, DirectiveID.getLoc()); | |||
11015 | else if (IDVal == ".thumb") | |||
11016 | parseDirectiveThumb(DirectiveID.getLoc()); | |||
11017 | else if (IDVal == ".arm") | |||
11018 | parseDirectiveARM(DirectiveID.getLoc()); | |||
11019 | else if (IDVal == ".thumb_func") | |||
11020 | parseDirectiveThumbFunc(DirectiveID.getLoc()); | |||
11021 | else if (IDVal == ".code") | |||
11022 | parseDirectiveCode(DirectiveID.getLoc()); | |||
11023 | else if (IDVal == ".syntax") | |||
11024 | parseDirectiveSyntax(DirectiveID.getLoc()); | |||
11025 | else if (IDVal == ".unreq") | |||
11026 | parseDirectiveUnreq(DirectiveID.getLoc()); | |||
11027 | else if (IDVal == ".fnend") | |||
11028 | parseDirectiveFnEnd(DirectiveID.getLoc()); | |||
11029 | else if (IDVal == ".cantunwind") | |||
11030 | parseDirectiveCantUnwind(DirectiveID.getLoc()); | |||
11031 | else if (IDVal == ".personality") | |||
11032 | parseDirectivePersonality(DirectiveID.getLoc()); | |||
11033 | else if (IDVal == ".handlerdata") | |||
11034 | parseDirectiveHandlerData(DirectiveID.getLoc()); | |||
11035 | else if (IDVal == ".setfp") | |||
11036 | parseDirectiveSetFP(DirectiveID.getLoc()); | |||
11037 | else if (IDVal == ".pad") | |||
11038 | parseDirectivePad(DirectiveID.getLoc()); | |||
11039 | else if (IDVal == ".save") | |||
11040 | parseDirectiveRegSave(DirectiveID.getLoc(), false); | |||
11041 | else if (IDVal == ".vsave") | |||
11042 | parseDirectiveRegSave(DirectiveID.getLoc(), true); | |||
11043 | else if (IDVal == ".ltorg" || IDVal == ".pool") | |||
11044 | parseDirectiveLtorg(DirectiveID.getLoc()); | |||
11045 | else if (IDVal == ".even") | |||
11046 | parseDirectiveEven(DirectiveID.getLoc()); | |||
11047 | else if (IDVal == ".personalityindex") | |||
11048 | parseDirectivePersonalityIndex(DirectiveID.getLoc()); | |||
11049 | else if (IDVal == ".unwind_raw") | |||
11050 | parseDirectiveUnwindRaw(DirectiveID.getLoc()); | |||
11051 | else if (IDVal == ".movsp") | |||
11052 | parseDirectiveMovSP(DirectiveID.getLoc()); | |||
11053 | else if (IDVal == ".arch_extension") | |||
11054 | parseDirectiveArchExtension(DirectiveID.getLoc()); | |||
11055 | else if (IDVal == ".align") | |||
11056 | return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure. | |||
11057 | else if (IDVal == ".thumb_set") | |||
11058 | parseDirectiveThumbSet(DirectiveID.getLoc()); | |||
11059 | else if (IDVal == ".inst") | |||
11060 | parseDirectiveInst(DirectiveID.getLoc()); | |||
11061 | else if (IDVal == ".inst.n") | |||
11062 | parseDirectiveInst(DirectiveID.getLoc(), 'n'); | |||
11063 | else if (IDVal == ".inst.w") | |||
11064 | parseDirectiveInst(DirectiveID.getLoc(), 'w'); | |||
11065 | else if (!IsMachO && !IsCOFF) { | |||
11066 | if (IDVal == ".arch") | |||
11067 | parseDirectiveArch(DirectiveID.getLoc()); | |||
11068 | else if (IDVal == ".cpu") | |||
11069 | parseDirectiveCPU(DirectiveID.getLoc()); | |||
11070 | else if (IDVal == ".eabi_attribute") | |||
11071 | parseDirectiveEabiAttr(DirectiveID.getLoc()); | |||
11072 | else if (IDVal == ".fpu") | |||
11073 | parseDirectiveFPU(DirectiveID.getLoc()); | |||
11074 | else if (IDVal == ".fnstart") | |||
11075 | parseDirectiveFnStart(DirectiveID.getLoc()); | |||
11076 | else if (IDVal == ".object_arch") | |||
11077 | parseDirectiveObjectArch(DirectiveID.getLoc()); | |||
11078 | else if (IDVal == ".tlsdescseq") | |||
11079 | parseDirectiveTLSDescSeq(DirectiveID.getLoc()); | |||
11080 | else | |||
11081 | return true; | |||
11082 | } else | |||
11083 | return true; | |||
11084 | return false; | |||
11085 | } | |||
11086 | ||||
11087 | /// parseLiteralValues | |||
11088 | /// ::= .hword expression [, expression]* | |||
11089 | /// ::= .short expression [, expression]* | |||
11090 | /// ::= .word expression [, expression]* | |||
11091 | bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { | |||
11092 | auto parseOne = [&]() -> bool { | |||
11093 | const MCExpr *Value; | |||
11094 | if (getParser().parseExpression(Value)) | |||
11095 | return true; | |||
11096 | getParser().getStreamer().emitValue(Value, Size, L); | |||
11097 | return false; | |||
11098 | }; | |||
11099 | return (parseMany(parseOne)); | |||
11100 | } | |||
11101 | ||||
11102 | /// parseDirectiveThumb | |||
11103 | /// ::= .thumb | |||
11104 | bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { | |||
11105 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") || | |||
11106 | check(!hasThumb(), L, "target does not support Thumb mode")) | |||
11107 | return true; | |||
11108 | ||||
11109 | if (!isThumb()) | |||
11110 | SwitchMode(); | |||
11111 | ||||
11112 | getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); | |||
11113 | return false; | |||
11114 | } | |||
11115 | ||||
11116 | /// parseDirectiveARM | |||
11117 | /// ::= .arm | |||
11118 | bool ARMAsmParser::parseDirectiveARM(SMLoc L) { | |||
11119 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") || | |||
11120 | check(!hasARM(), L, "target does not support ARM mode")) | |||
11121 | return true; | |||
11122 | ||||
11123 | if (isThumb()) | |||
11124 | SwitchMode(); | |||
11125 | getParser().getStreamer().emitAssemblerFlag(MCAF_Code32); | |||
11126 | return false; | |||
11127 | } | |||
11128 | ||||
11129 | void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) { | |||
11130 | // We need to flush the current implicit IT block on a label, because it is | |||
11131 | // not legal to branch into an IT block. | |||
11132 | flushPendingInstructions(getStreamer()); | |||
11133 | } | |||
11134 | ||||
11135 | void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { | |||
11136 | if (NextSymbolIsThumb) { | |||
11137 | getParser().getStreamer().emitThumbFunc(Symbol); | |||
11138 | NextSymbolIsThumb = false; | |||
11139 | } | |||
11140 | } | |||
11141 | ||||
11142 | /// parseDirectiveThumbFunc | |||
11143 | /// ::= .thumbfunc symbol_name | |||
11144 | bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { | |||
11145 | MCAsmParser &Parser = getParser(); | |||
11146 | const auto Format = getContext().getObjectFileType(); | |||
11147 | bool IsMachO = Format == MCContext::IsMachO; | |||
11148 | ||||
11149 | // Darwin asm has (optionally) function name after .thumb_func direction | |||
11150 | // ELF doesn't | |||
11151 | ||||
11152 | if (IsMachO) { | |||
11153 | if (Parser.getTok().is(AsmToken::Identifier) || | |||
11154 | Parser.getTok().is(AsmToken::String)) { | |||
11155 | MCSymbol *Func = getParser().getContext().getOrCreateSymbol( | |||
11156 | Parser.getTok().getIdentifier()); | |||
11157 | getParser().getStreamer().emitThumbFunc(Func); | |||
11158 | Parser.Lex(); | |||
11159 | if (parseToken(AsmToken::EndOfStatement, | |||
11160 | "unexpected token in '.thumb_func' directive")) | |||
11161 | return true; | |||
11162 | return false; | |||
11163 | } | |||
11164 | } | |||
11165 | ||||
11166 | if (parseToken(AsmToken::EndOfStatement, | |||
11167 | "unexpected token in '.thumb_func' directive")) | |||
11168 | return true; | |||
11169 | ||||
11170 | // .thumb_func implies .thumb | |||
11171 | if (!isThumb()) | |||
11172 | SwitchMode(); | |||
11173 | ||||
11174 | getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); | |||
11175 | ||||
11176 | NextSymbolIsThumb = true; | |||
11177 | return false; | |||
11178 | } | |||
11179 | ||||
11180 | /// parseDirectiveSyntax | |||
11181 | /// ::= .syntax unified | divided | |||
11182 | bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { | |||
11183 | MCAsmParser &Parser = getParser(); | |||
11184 | const AsmToken &Tok = Parser.getTok(); | |||
11185 | if (Tok.isNot(AsmToken::Identifier)) { | |||
11186 | Error(L, "unexpected token in .syntax directive"); | |||
11187 | return false; | |||
11188 | } | |||
11189 | ||||
11190 | StringRef Mode = Tok.getString(); | |||
11191 | Parser.Lex(); | |||
11192 | if (check(Mode == "divided" || Mode == "DIVIDED", L, | |||
11193 | "'.syntax divided' arm assembly not supported") || | |||
11194 | check(Mode != "unified" && Mode != "UNIFIED", L, | |||
11195 | "unrecognized syntax mode in .syntax directive") || | |||
11196 | parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) | |||
11197 | return true; | |||
11198 | ||||
11199 | // TODO tell the MC streamer the mode | |||
11200 | // getParser().getStreamer().Emit???(); | |||
11201 | return false; | |||
11202 | } | |||
11203 | ||||
11204 | /// parseDirectiveCode | |||
11205 | /// ::= .code 16 | 32 | |||
11206 | bool ARMAsmParser::parseDirectiveCode(SMLoc L) { | |||
11207 | MCAsmParser &Parser = getParser(); | |||
11208 | const AsmToken &Tok = Parser.getTok(); | |||
11209 | if (Tok.isNot(AsmToken::Integer)) | |||
11210 | return Error(L, "unexpected token in .code directive"); | |||
11211 | int64_t Val = Parser.getTok().getIntVal(); | |||
11212 | if (Val != 16 && Val != 32) { | |||
11213 | Error(L, "invalid operand to .code directive"); | |||
11214 | return false; | |||
11215 | } | |||
11216 | Parser.Lex(); | |||
11217 | ||||
11218 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) | |||
11219 | return true; | |||
11220 | ||||
11221 | if (Val == 16) { | |||
11222 | if (!hasThumb()) | |||
11223 | return Error(L, "target does not support Thumb mode"); | |||
11224 | ||||
11225 | if (!isThumb()) | |||
11226 | SwitchMode(); | |||
11227 | getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); | |||
11228 | } else { | |||
11229 | if (!hasARM()) | |||
11230 | return Error(L, "target does not support ARM mode"); | |||
11231 | ||||
11232 | if (isThumb()) | |||
11233 | SwitchMode(); | |||
11234 | getParser().getStreamer().emitAssemblerFlag(MCAF_Code32); | |||
11235 | } | |||
11236 | ||||
11237 | return false; | |||
11238 | } | |||
11239 | ||||
11240 | /// parseDirectiveReq | |||
11241 | /// ::= name .req registername | |||
11242 | bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { | |||
11243 | MCAsmParser &Parser = getParser(); | |||
11244 | Parser.Lex(); // Eat the '.req' token. | |||
11245 | unsigned Reg; | |||
11246 | SMLoc SRegLoc, ERegLoc; | |||
11247 | if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc, | |||
11248 | "register name expected") || | |||
11249 | parseToken(AsmToken::EndOfStatement, | |||
11250 | "unexpected input in .req directive.")) | |||
11251 | return true; | |||
11252 | ||||
11253 | if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) | |||
11254 | return Error(SRegLoc, | |||
11255 | "redefinition of '" + Name + "' does not match original."); | |||
11256 | ||||
11257 | return false; | |||
11258 | } | |||
11259 | ||||
11260 | /// parseDirectiveUneq | |||
11261 | /// ::= .unreq registername | |||
11262 | bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { | |||
11263 | MCAsmParser &Parser = getParser(); | |||
11264 | if (Parser.getTok().isNot(AsmToken::Identifier)) | |||
11265 | return Error(L, "unexpected input in .unreq directive."); | |||
11266 | RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); | |||
11267 | Parser.Lex(); // Eat the identifier. | |||
11268 | if (parseToken(AsmToken::EndOfStatement, | |||
11269 | "unexpected input in '.unreq' directive")) | |||
11270 | return true; | |||
11271 | return false; | |||
11272 | } | |||
11273 | ||||
11274 | // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was | |||
11275 | // before, if supported by the new target, or emit mapping symbols for the mode | |||
11276 | // switch. | |||
11277 | void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) { | |||
11278 | if (WasThumb != isThumb()) { | |||
11279 | if (WasThumb && hasThumb()) { | |||
11280 | // Stay in Thumb mode | |||
11281 | SwitchMode(); | |||
11282 | } else if (!WasThumb && hasARM()) { | |||
11283 | // Stay in ARM mode | |||
11284 | SwitchMode(); | |||
11285 | } else { | |||
11286 | // Mode switch forced, because the new arch doesn't support the old mode. | |||
11287 | getParser().getStreamer().emitAssemblerFlag(isThumb() ? MCAF_Code16 | |||
11288 | : MCAF_Code32); | |||
11289 | // Warn about the implcit mode switch. GAS does not switch modes here, | |||
11290 | // but instead stays in the old mode, reporting an error on any following | |||
11291 | // instructions as the mode does not exist on the target. | |||
11292 | Warning(Loc, Twine("new target does not support ") + | |||
11293 | (WasThumb ? "thumb" : "arm") + " mode, switching to " + | |||
11294 | (!WasThumb ? "thumb" : "arm") + " mode"); | |||
11295 | } | |||
11296 | } | |||
11297 | } | |||
11298 | ||||
11299 | /// parseDirectiveArch | |||
11300 | /// ::= .arch token | |||
11301 | bool ARMAsmParser::parseDirectiveArch(SMLoc L) { | |||
11302 | StringRef Arch = getParser().parseStringToEndOfStatement().trim(); | |||
11303 | ARM::ArchKind ID = ARM::parseArch(Arch); | |||
11304 | ||||
11305 | if (ID == ARM::ArchKind::INVALID) | |||
11306 | return Error(L, "Unknown arch name"); | |||
11307 | ||||
11308 | bool WasThumb = isThumb(); | |||
11309 | Triple T; | |||
11310 | MCSubtargetInfo &STI = copySTI(); | |||
11311 | STI.setDefaultFeatures("", /*TuneCPU*/ "", | |||
11312 | ("+" + ARM::getArchName(ID)).str()); | |||
11313 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); | |||
11314 | FixModeAfterArchChange(WasThumb, L); | |||
11315 | ||||
11316 | getTargetStreamer().emitArch(ID); | |||
11317 | return false; | |||
11318 | } | |||
11319 | ||||
11320 | /// parseDirectiveEabiAttr | |||
11321 | /// ::= .eabi_attribute int, int [, "str"] | |||
11322 | /// ::= .eabi_attribute Tag_name, int [, "str"] | |||
11323 | bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { | |||
11324 | MCAsmParser &Parser = getParser(); | |||
11325 | int64_t Tag; | |||
11326 | SMLoc TagLoc; | |||
11327 | TagLoc = Parser.getTok().getLoc(); | |||
11328 | if (Parser.getTok().is(AsmToken::Identifier)) { | |||
11329 | StringRef Name = Parser.getTok().getIdentifier(); | |||
11330 | Optional<unsigned> Ret = ELFAttrs::attrTypeFromString( | |||
11331 | Name, ARMBuildAttrs::getARMAttributeTags()); | |||
11332 | if (!Ret.hasValue()) { | |||
11333 | Error(TagLoc, "attribute name not recognised: " + Name); | |||
11334 | return false; | |||
11335 | } | |||
11336 | Tag = Ret.getValue(); | |||
11337 | Parser.Lex(); | |||
11338 | } else { | |||
11339 | const MCExpr *AttrExpr; | |||
11340 | ||||
11341 | TagLoc = Parser.getTok().getLoc(); | |||
11342 | if (Parser.parseExpression(AttrExpr)) | |||
11343 | return true; | |||
11344 | ||||
11345 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); | |||
11346 | if (check(!CE, TagLoc, "expected numeric constant")) | |||
11347 | return true; | |||
11348 | ||||
11349 | Tag = CE->getValue(); | |||
11350 | } | |||
11351 | ||||
11352 | if (Parser.parseToken(AsmToken::Comma, "comma expected")) | |||
11353 | return true; | |||
11354 | ||||
11355 | StringRef StringValue = ""; | |||
11356 | bool IsStringValue = false; | |||
11357 | ||||
11358 | int64_t IntegerValue = 0; | |||
11359 | bool IsIntegerValue = false; | |||
11360 | ||||
11361 | if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) | |||
11362 | IsStringValue = true; | |||
11363 | else if (Tag == ARMBuildAttrs::compatibility) { | |||
11364 | IsStringValue = true; | |||
11365 | IsIntegerValue = true; | |||
11366 | } else if (Tag < 32 || Tag % 2 == 0) | |||
11367 | IsIntegerValue = true; | |||
11368 | else if (Tag % 2 == 1) | |||
11369 | IsStringValue = true; | |||
11370 | else | |||
11371 | llvm_unreachable("invalid tag type")__builtin_unreachable(); | |||
11372 | ||||
11373 | if (IsIntegerValue) { | |||
11374 | const MCExpr *ValueExpr; | |||
11375 | SMLoc ValueExprLoc = Parser.getTok().getLoc(); | |||
11376 | if (Parser.parseExpression(ValueExpr)) | |||
11377 | return true; | |||
11378 | ||||
11379 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); | |||
11380 | if (!CE) | |||
11381 | return Error(ValueExprLoc, "expected numeric constant"); | |||
11382 | IntegerValue = CE->getValue(); | |||
11383 | } | |||
11384 | ||||
11385 | if (Tag == ARMBuildAttrs::compatibility) { | |||
11386 | if (Parser.parseToken(AsmToken::Comma, "comma expected")) | |||
11387 | return true; | |||
11388 | } | |||
11389 | ||||
11390 | if (IsStringValue) { | |||
11391 | if (Parser.getTok().isNot(AsmToken::String)) | |||
11392 | return Error(Parser.getTok().getLoc(), "bad string constant"); | |||
11393 | ||||
11394 | StringValue = Parser.getTok().getStringContents(); | |||
11395 | Parser.Lex(); | |||
11396 | } | |||
11397 | ||||
11398 | if (Parser.parseToken(AsmToken::EndOfStatement, | |||
11399 | "unexpected token in '.eabi_attribute' directive")) | |||
11400 | return true; | |||
11401 | ||||
11402 | if (IsIntegerValue && IsStringValue) { | |||
11403 | assert(Tag == ARMBuildAttrs::compatibility)(static_cast<void> (0)); | |||
11404 | getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); | |||
11405 | } else if (IsIntegerValue) | |||
11406 | getTargetStreamer().emitAttribute(Tag, IntegerValue); | |||
11407 | else if (IsStringValue) | |||
11408 | getTargetStreamer().emitTextAttribute(Tag, StringValue); | |||
11409 | return false; | |||
11410 | } | |||
11411 | ||||
11412 | /// parseDirectiveCPU | |||
11413 | /// ::= .cpu str | |||
11414 | bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { | |||
11415 | StringRef CPU = getParser().parseStringToEndOfStatement().trim(); | |||
11416 | getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); | |||
11417 | ||||
11418 | // FIXME: This is using table-gen data, but should be moved to | |||
11419 | // ARMTargetParser once that is table-gen'd. | |||
11420 | if (!getSTI().isCPUStringValid(CPU)) | |||
11421 | return Error(L, "Unknown CPU name"); | |||
11422 | ||||
11423 | bool WasThumb = isThumb(); | |||
11424 | MCSubtargetInfo &STI = copySTI(); | |||
11425 | STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, ""); | |||
11426 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); | |||
11427 | FixModeAfterArchChange(WasThumb, L); | |||
11428 | ||||
11429 | return false; | |||
11430 | } | |||
11431 | ||||
11432 | /// parseDirectiveFPU | |||
11433 | /// ::= .fpu str | |||
11434 | bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { | |||
11435 | SMLoc FPUNameLoc = getTok().getLoc(); | |||
11436 | StringRef FPU = getParser().parseStringToEndOfStatement().trim(); | |||
11437 | ||||
11438 | unsigned ID = ARM::parseFPU(FPU); | |||
11439 | std::vector<StringRef> Features; | |||
11440 | if (!ARM::getFPUFeatures(ID, Features)) | |||
11441 | return Error(FPUNameLoc, "Unknown FPU name"); | |||
11442 | ||||
11443 | MCSubtargetInfo &STI = copySTI(); | |||
11444 | for (auto Feature : Features) | |||
11445 | STI.ApplyFeatureFlag(Feature); | |||
11446 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); | |||
11447 | ||||
11448 | getTargetStreamer().emitFPU(ID); | |||
11449 | return false; | |||
11450 | } | |||
11451 | ||||
11452 | /// parseDirectiveFnStart | |||
11453 | /// ::= .fnstart | |||
11454 | bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { | |||
11455 | if (parseToken(AsmToken::EndOfStatement, | |||
11456 | "unexpected token in '.fnstart' directive")) | |||
11457 | return true; | |||
11458 | ||||
11459 | if (UC.hasFnStart()) { | |||
11460 | Error(L, ".fnstart starts before the end of previous one"); | |||
11461 | UC.emitFnStartLocNotes(); | |||
11462 | return true; | |||
11463 | } | |||
11464 | ||||
11465 | // Reset the unwind directives parser state | |||
11466 | UC.reset(); | |||
11467 | ||||
11468 | getTargetStreamer().emitFnStart(); | |||
11469 | ||||
11470 | UC.recordFnStart(L); | |||
11471 | return false; | |||
11472 | } | |||
11473 | ||||
11474 | /// parseDirectiveFnEnd | |||
11475 | /// ::= .fnend | |||
11476 | bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { | |||
11477 | if (parseToken(AsmToken::EndOfStatement, | |||
11478 | "unexpected token in '.fnend' directive")) | |||
11479 | return true; | |||
11480 | // Check the ordering of unwind directives | |||
11481 | if (!UC.hasFnStart()) | |||
11482 | return Error(L, ".fnstart must precede .fnend directive"); | |||
11483 | ||||
11484 | // Reset the unwind directives parser state | |||
11485 | getTargetStreamer().emitFnEnd(); | |||
11486 | ||||
11487 | UC.reset(); | |||
11488 | return false; | |||
11489 | } | |||
11490 | ||||
11491 | /// parseDirectiveCantUnwind | |||
11492 | /// ::= .cantunwind | |||
11493 | bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { | |||
11494 | if (parseToken(AsmToken::EndOfStatement, | |||
11495 | "unexpected token in '.cantunwind' directive")) | |||
11496 | return true; | |||
11497 | ||||
11498 | UC.recordCantUnwind(L); | |||
11499 | // Check the ordering of unwind directives | |||
11500 | if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive")) | |||
11501 | return true; | |||
11502 | ||||
11503 | if (UC.hasHandlerData()) { | |||
11504 | Error(L, ".cantunwind can't be used with .handlerdata directive"); | |||
11505 | UC.emitHandlerDataLocNotes(); | |||
11506 | return true; | |||
11507 | } | |||
11508 | if (UC.hasPersonality()) { | |||
11509 | Error(L, ".cantunwind can't be used with .personality directive"); | |||
11510 | UC.emitPersonalityLocNotes(); | |||
11511 | return true; | |||
11512 | } | |||
11513 | ||||
11514 | getTargetStreamer().emitCantUnwind(); | |||
11515 | return false; | |||
11516 | } | |||
11517 | ||||
11518 | /// parseDirectivePersonality | |||
11519 | /// ::= .personality name | |||
11520 | bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { | |||
11521 | MCAsmParser &Parser = getParser(); | |||
11522 | bool HasExistingPersonality = UC.hasPersonality(); | |||
11523 | ||||
11524 | // Parse the name of the personality routine | |||
11525 | if (Parser.getTok().isNot(AsmToken::Identifier)) | |||
11526 | return Error(L, "unexpected input in .personality directive."); | |||
11527 | StringRef Name(Parser.getTok().getIdentifier()); | |||
11528 | Parser.Lex(); | |||
11529 | ||||
11530 | if (parseToken(AsmToken::EndOfStatement, | |||
11531 | "unexpected token in '.personality' directive")) | |||
11532 | return true; | |||
11533 | ||||
11534 | UC.recordPersonality(L); | |||
11535 | ||||
11536 | // Check the ordering of unwind directives | |||
11537 | if (!UC.hasFnStart()) | |||
11538 | return Error(L, ".fnstart must precede .personality directive"); | |||
11539 | if (UC.cantUnwind()) { | |||
11540 | Error(L, ".personality can't be used with .cantunwind directive"); | |||
11541 | UC.emitCantUnwindLocNotes(); | |||
11542 | return true; | |||
11543 | } | |||
11544 | if (UC.hasHandlerData()) { | |||
11545 | Error(L, ".personality must precede .handlerdata directive"); | |||
11546 | UC.emitHandlerDataLocNotes(); | |||
11547 | return true; | |||
11548 | } | |||
11549 | if (HasExistingPersonality) { | |||
11550 | Error(L, "multiple personality directives"); | |||
11551 | UC.emitPersonalityLocNotes(); | |||
11552 | return true; | |||
11553 | } | |||
11554 | ||||
11555 | MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name); | |||
11556 | getTargetStreamer().emitPersonality(PR); | |||
11557 | return false; | |||
11558 | } | |||
11559 | ||||
11560 | /// parseDirectiveHandlerData | |||
11561 | /// ::= .handlerdata | |||
11562 | bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { | |||
11563 | if (parseToken(AsmToken::EndOfStatement, | |||
11564 | "unexpected token in '.handlerdata' directive")) | |||
11565 | return true; | |||
11566 | ||||
11567 | UC.recordHandlerData(L); | |||
11568 | // Check the ordering of unwind directives | |||
11569 | if (!UC.hasFnStart()) | |||
11570 | return Error(L, ".fnstart must precede .personality directive"); | |||
11571 | if (UC.cantUnwind()) { | |||
11572 | Error(L, ".handlerdata can't be used with .cantunwind directive"); | |||
11573 | UC.emitCantUnwindLocNotes(); | |||
11574 | return true; | |||
11575 | } | |||
11576 | ||||
11577 | getTargetStreamer().emitHandlerData(); | |||
11578 | return false; | |||
11579 | } | |||
11580 | ||||
11581 | /// parseDirectiveSetFP | |||
11582 | /// ::= .setfp fpreg, spreg [, offset] | |||
11583 | bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { | |||
11584 | MCAsmParser &Parser = getParser(); | |||
11585 | // Check the ordering of unwind directives | |||
11586 | if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") || | |||
11587 | check(UC.hasHandlerData(), L, | |||
11588 | ".setfp must precede .handlerdata directive")) | |||
11589 | return true; | |||
11590 | ||||
11591 | // Parse fpreg | |||
11592 | SMLoc FPRegLoc = Parser.getTok().getLoc(); | |||
11593 | int FPReg = tryParseRegister(); | |||
11594 | ||||
11595 | if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") || | |||
11596 | Parser.parseToken(AsmToken::Comma, "comma expected")) | |||
11597 | return true; | |||
11598 | ||||
11599 | // Parse spreg | |||
11600 | SMLoc SPRegLoc = Parser.getTok().getLoc(); | |||
11601 | int SPReg = tryParseRegister(); | |||
11602 | if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") || | |||
11603 | check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, | |||
11604 | "register should be either $sp or the latest fp register")) | |||
11605 | return true; | |||
11606 | ||||
11607 | // Update the frame pointer register | |||
11608 | UC.saveFPReg(FPReg); | |||
11609 | ||||
11610 | // Parse offset | |||
11611 | int64_t Offset = 0; | |||
11612 | if (Parser.parseOptionalToken(AsmToken::Comma)) { | |||
11613 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
11614 | Parser.getTok().isNot(AsmToken::Dollar)) | |||
11615 | return Error(Parser.getTok().getLoc(), "'#' expected"); | |||
11616 | Parser.Lex(); // skip hash token. | |||
11617 | ||||
11618 | const MCExpr *OffsetExpr; | |||
11619 | SMLoc ExLoc = Parser.getTok().getLoc(); | |||
11620 | SMLoc EndLoc; | |||
11621 | if (getParser().parseExpression(OffsetExpr, EndLoc)) | |||
11622 | return Error(ExLoc, "malformed setfp offset"); | |||
11623 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); | |||
11624 | if (check(!CE, ExLoc, "setfp offset must be an immediate")) | |||
11625 | return true; | |||
11626 | Offset = CE->getValue(); | |||
11627 | } | |||
11628 | ||||
11629 | if (Parser.parseToken(AsmToken::EndOfStatement)) | |||
11630 | return true; | |||
11631 | ||||
11632 | getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), | |||
11633 | static_cast<unsigned>(SPReg), Offset); | |||
11634 | return false; | |||
11635 | } | |||
11636 | ||||
11637 | /// parseDirective | |||
11638 | /// ::= .pad offset | |||
11639 | bool ARMAsmParser::parseDirectivePad(SMLoc L) { | |||
11640 | MCAsmParser &Parser = getParser(); | |||
11641 | // Check the ordering of unwind directives | |||
11642 | if (!UC.hasFnStart()) | |||
11643 | return Error(L, ".fnstart must precede .pad directive"); | |||
11644 | if (UC.hasHandlerData()) | |||
11645 | return Error(L, ".pad must precede .handlerdata directive"); | |||
11646 | ||||
11647 | // Parse the offset | |||
11648 | if (Parser.getTok().isNot(AsmToken::Hash) && | |||
11649 | Parser.getTok().isNot(AsmToken::Dollar)) | |||
11650 | return Error(Parser.getTok().getLoc(), "'#' expected"); | |||
11651 | Parser.Lex(); // skip hash token. | |||
11652 | ||||
11653 | const MCExpr *OffsetExpr; | |||
11654 | SMLoc ExLoc = Parser.getTok().getLoc(); | |||
11655 | SMLoc EndLoc; | |||
11656 | if (getParser().parseExpression(OffsetExpr, EndLoc)) | |||
11657 | return Error(ExLoc, "malformed pad offset"); | |||
11658 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); | |||
11659 | if (!CE) | |||
11660 | return Error(ExLoc, "pad offset must be an immediate"); | |||
11661 | ||||
11662 | if (parseToken(AsmToken::EndOfStatement, | |||
11663 | "unexpected token in '.pad' directive")) | |||
11664 | return true; | |||
11665 | ||||
11666 | getTargetStreamer().emitPad(CE->getValue()); | |||
11667 | return false; | |||
11668 | } | |||
11669 | ||||
11670 | /// parseDirectiveRegSave | |||
11671 | /// ::= .save { registers } | |||
11672 | /// ::= .vsave { registers } | |||
11673 | bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { | |||
11674 | // Check the ordering of unwind directives | |||
11675 | if (!UC.hasFnStart()) | |||
11676 | return Error(L, ".fnstart must precede .save or .vsave directives"); | |||
11677 | if (UC.hasHandlerData()) | |||
11678 | return Error(L, ".save or .vsave must precede .handlerdata directive"); | |||
11679 | ||||
11680 | // RAII object to make sure parsed operands are deleted. | |||
11681 | SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; | |||
11682 | ||||
11683 | // Parse the register list | |||
11684 | if (parseRegisterList(Operands) || | |||
11685 | parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) | |||
11686 | return true; | |||
11687 | ARMOperand &Op = (ARMOperand &)*Operands[0]; | |||
11688 | if (!IsVector && !Op.isRegList()) | |||
11689 | return Error(L, ".save expects GPR registers"); | |||
11690 | if (IsVector && !Op.isDPRRegList()) | |||
11691 | return Error(L, ".vsave expects DPR registers"); | |||
11692 | ||||
11693 | getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); | |||
11694 | return false; | |||
11695 | } | |||
11696 | ||||
11697 | /// parseDirectiveInst | |||
11698 | /// ::= .inst opcode [, ...] | |||
11699 | /// ::= .inst.n opcode [, ...] | |||
11700 | /// ::= .inst.w opcode [, ...] | |||
11701 | bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { | |||
11702 | int Width = 4; | |||
11703 | ||||
11704 | if (isThumb()) { | |||
11705 | switch (Suffix) { | |||
11706 | case 'n': | |||
11707 | Width = 2; | |||
11708 | break; | |||
11709 | case 'w': | |||
11710 | break; | |||
11711 | default: | |||
11712 | Width = 0; | |||
11713 | break; | |||
11714 | } | |||
11715 | } else { | |||
11716 | if (Suffix) | |||
11717 | return Error(Loc, "width suffixes are invalid in ARM mode"); | |||
11718 | } | |||
11719 | ||||
11720 | auto parseOne = [&]() -> bool { | |||
11721 | const MCExpr *Expr; | |||
11722 | if (getParser().parseExpression(Expr)) | |||
11723 | return true; | |||
11724 | const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); | |||
11725 | if (!Value) { | |||
11726 | return Error(Loc, "expected constant expression"); | |||
11727 | } | |||
11728 | ||||
11729 | char CurSuffix = Suffix; | |||
11730 | switch (Width) { | |||
11731 | case 2: | |||
11732 | if (Value->getValue() > 0xffff) | |||
11733 | return Error(Loc, "inst.n operand is too big, use inst.w instead"); | |||
11734 | break; | |||
11735 | case 4: | |||
11736 | if (Value->getValue() > 0xffffffff) | |||
11737 | return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") + | |||
11738 | " operand is too big"); | |||
11739 | break; | |||
11740 | case 0: | |||
11741 | // Thumb mode, no width indicated. Guess from the opcode, if possible. | |||
11742 | if (Value->getValue() < 0xe800) | |||
11743 | CurSuffix = 'n'; | |||
11744 | else if (Value->getValue() >= 0xe8000000) | |||
11745 | CurSuffix = 'w'; | |||
11746 | else | |||
11747 | return Error(Loc, "cannot determine Thumb instruction size, " | |||
11748 | "use inst.n/inst.w instead"); | |||
11749 | break; | |||
11750 | default: | |||
11751 | llvm_unreachable("only supported widths are 2 and 4")__builtin_unreachable(); | |||
11752 | } | |||
11753 | ||||
11754 | getTargetStreamer().emitInst(Value->getValue(), CurSuffix); | |||
11755 | return false; | |||
11756 | }; | |||
11757 | ||||
11758 | if (parseOptionalToken(AsmToken::EndOfStatement)) | |||
11759 | return Error(Loc, "expected expression following directive"); | |||
11760 | if (parseMany(parseOne)) | |||
11761 | return true; | |||
11762 | return false; | |||
11763 | } | |||
11764 | ||||
11765 | /// parseDirectiveLtorg | |||
11766 | /// ::= .ltorg | .pool | |||
11767 | bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { | |||
11768 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) | |||
11769 | return true; | |||
11770 | getTargetStreamer().emitCurrentConstantPool(); | |||
11771 | return false; | |||
11772 | } | |||
11773 | ||||
11774 | bool ARMAsmParser::parseDirectiveEven(SMLoc L) { | |||
11775 | const MCSection *Section = getStreamer().getCurrentSectionOnly(); | |||
11776 | ||||
11777 | if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) | |||
11778 | return true; | |||
11779 | ||||
11780 | if (!Section) { | |||
11781 | getStreamer().InitSections(false); | |||
11782 | Section = getStreamer().getCurrentSectionOnly(); | |||
11783 | } | |||
11784 | ||||
11785 | assert(Section && "must have section to emit alignment")(static_cast<void> (0)); | |||
11786 | if (Section->UseCodeAlign()) | |||
11787 | getStreamer().emitCodeAlignment(2); | |||
11788 | else | |||
11789 | getStreamer().emitValueToAlignment(2); | |||
11790 | ||||
11791 | return false; | |||
11792 | } | |||
11793 | ||||
11794 | /// parseDirectivePersonalityIndex | |||
11795 | /// ::= .personalityindex index | |||
11796 | bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { | |||
11797 | MCAsmParser &Parser = getParser(); | |||
11798 | bool HasExistingPersonality = UC.hasPersonality(); | |||
11799 | ||||
11800 | const MCExpr *IndexExpression; | |||
11801 | SMLoc IndexLoc = Parser.getTok().getLoc(); | |||
11802 | if (Parser.parseExpression(IndexExpression) || | |||
11803 | parseToken(AsmToken::EndOfStatement, | |||
11804 | "unexpected token in '.personalityindex' directive")) { | |||
11805 | return true; | |||
11806 | } | |||
11807 | ||||
11808 | UC.recordPersonalityIndex(L); | |||
11809 | ||||
11810 | if (!UC.hasFnStart()) { | |||
11811 | return Error(L, ".fnstart must precede .personalityindex directive"); | |||
11812 | } | |||
11813 | if (UC.cantUnwind()) { | |||
11814 | Error(L, ".personalityindex cannot be used with .cantunwind"); | |||
11815 | UC.emitCantUnwindLocNotes(); | |||
11816 | return true; | |||
11817 | } | |||
11818 | if (UC.hasHandlerData()) { | |||
11819 | Error(L, ".personalityindex must precede .handlerdata directive"); | |||
11820 | UC.emitHandlerDataLocNotes(); | |||
11821 | return true; | |||
11822 | } | |||
11823 | if (HasExistingPersonality) { | |||
11824 | Error(L, "multiple personality directives"); | |||
11825 | UC.emitPersonalityLocNotes(); | |||
11826 | return true; | |||
11827 | } | |||
11828 | ||||
11829 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); | |||
11830 | if (!CE) | |||
11831 | return Error(IndexLoc, "index must be a constant number"); | |||
11832 | if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) | |||
11833 | return Error(IndexLoc, | |||
11834 | "personality routine index should be in range [0-3]"); | |||
11835 | ||||
11836 | getTargetStreamer().emitPersonalityIndex(CE->getValue()); | |||
11837 | return false; | |||
11838 | } | |||
11839 | ||||
11840 | /// parseDirectiveUnwindRaw | |||
11841 | /// ::= .unwind_raw offset, opcode [, opcode...] | |||
11842 | bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { | |||
11843 | MCAsmParser &Parser = getParser(); | |||
11844 | int64_t StackOffset; | |||
11845 | const MCExpr *OffsetExpr; | |||
11846 | SMLoc OffsetLoc = getLexer().getLoc(); | |||
11847 | ||||
11848 | if (!UC.hasFnStart()) | |||
11849 | return Error(L, ".fnstart must precede .unwind_raw directives"); | |||
11850 | if (getParser().parseExpression(OffsetExpr)) | |||
11851 | return Error(OffsetLoc, "expected expression"); | |||
11852 | ||||
11853 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); | |||
11854 | if (!CE) | |||
11855 | return Error(OffsetLoc, "offset must be a constant"); | |||
11856 | ||||
11857 | StackOffset = CE->getValue(); | |||
11858 | ||||
11859 | if (Parser.parseToken(AsmToken::Comma, "expected comma")) | |||
11860 | return true; | |||
11861 | ||||
11862 | SmallVector<uint8_t, 16> Opcodes; | |||
11863 | ||||
11864 | auto parseOne = [&]() -> bool { | |||
11865 | const MCExpr *OE = nullptr; | |||
11866 | SMLoc OpcodeLoc = getLexer().getLoc(); | |||
11867 | if (check(getLexer().is(AsmToken::EndOfStatement) || | |||
11868 | Parser.parseExpression(OE), | |||
11869 | OpcodeLoc, "expected opcode expression")) | |||
11870 | return true; | |||
11871 | const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); | |||
11872 | if (!OC) | |||
11873 | return Error(OpcodeLoc, "opcode value must be a constant"); | |||
11874 | const int64_t Opcode = OC->getValue(); | |||
11875 | if (Opcode & ~0xff) | |||
11876 | return Error(OpcodeLoc, "invalid opcode"); | |||
11877 | Opcodes.push_back(uint8_t(Opcode)); | |||
11878 | return false; | |||
11879 | }; | |||
11880 | ||||
11881 | // Must have at least 1 element | |||
11882 | SMLoc OpcodeLoc = getLexer().getLoc(); | |||
11883 | if (parseOptionalToken(AsmToken::EndOfStatement)) | |||
11884 | return Error(OpcodeLoc, "expected opcode expression"); | |||
11885 | if (parseMany(parseOne)) | |||
11886 | return true; | |||
11887 | ||||
11888 | getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); | |||
11889 | return false; | |||
11890 | } | |||
11891 | ||||
11892 | /// parseDirectiveTLSDescSeq | |||
11893 | /// ::= .tlsdescseq tls-variable | |||
11894 | bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { | |||
11895 | MCAsmParser &Parser = getParser(); | |||
11896 | ||||
11897 | if (getLexer().isNot(AsmToken::Identifier)) | |||
11898 | return TokError("expected variable after '.tlsdescseq' directive"); | |||
11899 | ||||
11900 | const MCSymbolRefExpr *SRE = | |||
11901 | MCSymbolRefExpr::create(Parser.getTok().getIdentifier(), | |||
11902 | MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); | |||
11903 | Lex(); | |||
11904 | ||||
11905 | if (parseToken(AsmToken::EndOfStatement, | |||
11906 | "unexpected token in '.tlsdescseq' directive")) | |||
11907 | return true; | |||
11908 | ||||
11909 | getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); | |||
11910 | return false; | |||
11911 | } | |||
11912 | ||||
11913 | /// parseDirectiveMovSP | |||
11914 | /// ::= .movsp reg [, #offset] | |||
11915 | bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { | |||
11916 | MCAsmParser &Parser = getParser(); | |||
11917 | if (!UC.hasFnStart()) | |||
11918 | return Error(L, ".fnstart must precede .movsp directives"); | |||
11919 | if (UC.getFPReg() != ARM::SP) | |||
11920 | return Error(L, "unexpected .movsp directive"); | |||
11921 | ||||
11922 | SMLoc SPRegLoc = Parser.getTok().getLoc(); | |||
11923 | int SPReg = tryParseRegister(); | |||
11924 | if (SPReg == -1) | |||
11925 | return Error(SPRegLoc, "register expected"); | |||
11926 | if (SPReg == ARM::SP || SPReg == ARM::PC) | |||
11927 | return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); | |||
11928 | ||||
11929 | int64_t Offset = 0; | |||
11930 | if (Parser.parseOptionalToken(AsmToken::Comma)) { | |||
11931 | if (Parser.parseToken(AsmToken::Hash, "expected #constant")) | |||
11932 | return true; | |||
11933 | ||||
11934 | const MCExpr *OffsetExpr; | |||
11935 | SMLoc OffsetLoc = Parser.getTok().getLoc(); | |||
11936 | ||||
11937 | if (Parser.parseExpression(OffsetExpr)) | |||
11938 | return Error(OffsetLoc, "malformed offset expression"); | |||
11939 | ||||
11940 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); | |||
11941 | if (!CE) | |||
11942 | return Error(OffsetLoc, "offset must be an immediate constant"); | |||
11943 | ||||
11944 | Offset = CE->getValue(); | |||
11945 | } | |||
11946 | ||||
11947 | if (parseToken(AsmToken::EndOfStatement, | |||
11948 | "unexpected token in '.movsp' directive")) | |||
11949 | return true; | |||
11950 | ||||
11951 | getTargetStreamer().emitMovSP(SPReg, Offset); | |||
11952 | UC.saveFPReg(SPReg); | |||
11953 | ||||
11954 | return false; | |||
11955 | } | |||
11956 | ||||
11957 | /// parseDirectiveObjectArch | |||
11958 | /// ::= .object_arch name | |||
11959 | bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { | |||
11960 | MCAsmParser &Parser = getParser(); | |||
11961 | if (getLexer().isNot(AsmToken::Identifier)) | |||
11962 | return Error(getLexer().getLoc(), "unexpected token"); | |||
11963 | ||||
11964 | StringRef Arch = Parser.getTok().getString(); | |||
11965 | SMLoc ArchLoc = Parser.getTok().getLoc(); | |||
11966 | Lex(); | |||
11967 | ||||
11968 | ARM::ArchKind ID = ARM::parseArch(Arch); | |||
11969 | ||||
11970 | if (ID == ARM::ArchKind::INVALID) | |||
11971 | return Error(ArchLoc, "unknown architecture '" + Arch + "'"); | |||
11972 | if (parseToken(AsmToken::EndOfStatement)) | |||
11973 | return true; | |||
11974 | ||||
11975 | getTargetStreamer().emitObjectArch(ID); | |||
11976 | return false; | |||
11977 | } | |||
11978 | ||||
11979 | /// parseDirectiveAlign | |||
11980 | /// ::= .align | |||
11981 | bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { | |||
11982 | // NOTE: if this is not the end of the statement, fall back to the target | |||
11983 | // agnostic handling for this directive which will correctly handle this. | |||
11984 | if (parseOptionalToken(AsmToken::EndOfStatement)) { | |||
11985 | // '.align' is target specifically handled to mean 2**2 byte alignment. | |||
11986 | const MCSection *Section = getStreamer().getCurrentSectionOnly(); | |||
11987 | assert(Section && "must have section to emit alignment")(static_cast<void> (0)); | |||
11988 | if (Section->UseCodeAlign()) | |||
11989 | getStreamer().emitCodeAlignment(4, 0); | |||
11990 | else | |||
11991 | getStreamer().emitValueToAlignment(4, 0, 1, 0); | |||
11992 | return false; | |||
11993 | } | |||
11994 | return true; | |||
11995 | } | |||
11996 | ||||
11997 | /// parseDirectiveThumbSet | |||
11998 | /// ::= .thumb_set name, value | |||
11999 | bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { | |||
12000 | MCAsmParser &Parser = getParser(); | |||
12001 | ||||
12002 | StringRef Name; | |||
12003 | if (check(Parser.parseIdentifier(Name), | |||
12004 | "expected identifier after '.thumb_set'") || | |||
12005 | parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'")) | |||
12006 | return true; | |||
12007 | ||||
12008 | MCSymbol *Sym; | |||
12009 | const MCExpr *Value; | |||
12010 | if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, | |||
12011 | Parser, Sym, Value)) | |||
12012 | return true; | |||
12013 | ||||
12014 | getTargetStreamer().emitThumbSet(Sym, Value); | |||
12015 | return false; | |||
12016 | } | |||
12017 | ||||
12018 | /// Force static initialization. | |||
12019 | extern "C" LLVM_EXTERNAL_VISIBILITY__attribute__ ((visibility("default"))) void LLVMInitializeARMAsmParser() { | |||
12020 | RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget()); | |||
12021 | RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget()); | |||
12022 | RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget()); | |||
12023 | RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget()); | |||
12024 | } | |||
12025 | ||||
12026 | #define GET_REGISTER_MATCHER | |||
12027 | #define GET_SUBTARGET_FEATURE_NAME | |||
12028 | #define GET_MATCHER_IMPLEMENTATION | |||
12029 | #define GET_MNEMONIC_SPELL_CHECKER | |||
12030 | #include "ARMGenAsmMatcher.inc" | |||
12031 | ||||
12032 | // Some diagnostics need to vary with subtarget features, so they are handled | |||
12033 | // here. For example, the DPR class has either 16 or 32 registers, depending | |||
12034 | // on the FPU available. | |||
12035 | const char * | |||
12036 | ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) { | |||
12037 | switch (MatchError) { | |||
12038 | // rGPR contains sp starting with ARMv8. | |||
12039 | case Match_rGPR: | |||
12040 | return hasV8Ops() ? "operand must be a register in range [r0, r14]" | |||
12041 | : "operand must be a register in range [r0, r12] or r14"; | |||
12042 | // DPR contains 16 registers for some FPUs, and 32 for others. | |||
12043 | case Match_DPR: | |||
12044 | return hasD32() ? "operand must be a register in range [d0, d31]" | |||
12045 | : "operand must be a register in range [d0, d15]"; | |||
12046 | case Match_DPR_RegList: | |||
12047 | return hasD32() ? "operand must be a list of registers in range [d0, d31]" | |||
12048 | : "operand must be a list of registers in range [d0, d15]"; | |||
12049 | ||||
12050 | // For all other diags, use the static string from tablegen. | |||
12051 | default: | |||
12052 | return getMatchKindDiag(MatchError); | |||
12053 | } | |||
12054 | } | |||
12055 | ||||
12056 | // Process the list of near-misses, throwing away ones we don't want to report | |||
12057 | // to the user, and converting the rest to a source location and string that | |||
12058 | // should be reported. | |||
12059 | void | |||
12060 | ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, | |||
12061 | SmallVectorImpl<NearMissMessage> &NearMissesOut, | |||
12062 | SMLoc IDLoc, OperandVector &Operands) { | |||
12063 | // TODO: If operand didn't match, sub in a dummy one and run target | |||
12064 | // predicate, so that we can avoid reporting near-misses that are invalid? | |||
12065 | // TODO: Many operand types dont have SuperClasses set, so we report | |||
12066 | // redundant ones. | |||
12067 | // TODO: Some operands are superclasses of registers (e.g. | |||
12068 | // MCK_RegShiftedImm), we don't have any way to represent that currently. | |||
12069 | // TODO: This is not all ARM-specific, can some of it be factored out? | |||
12070 | ||||
12071 | // Record some information about near-misses that we have already seen, so | |||
12072 | // that we can avoid reporting redundant ones. For example, if there are | |||
12073 | // variants of an instruction that take 8- and 16-bit immediates, we want | |||
12074 | // to only report the widest one. | |||
12075 | std::multimap<unsigned, unsigned> OperandMissesSeen; | |||
12076 | SmallSet<FeatureBitset, 4> FeatureMissesSeen; | |||
12077 | bool ReportedTooFewOperands = false; | |||
12078 | ||||
12079 | // Process the near-misses in reverse order, so that we see more general ones | |||
12080 | // first, and so can avoid emitting more specific ones. | |||
12081 | for (NearMissInfo &I : reverse(NearMissesIn)) { | |||
12082 | switch (I.getKind()) { | |||
12083 | case NearMissInfo::NearMissOperand: { | |||
12084 | SMLoc OperandLoc = | |||
12085 | ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); | |||
12086 | const char *OperandDiag = | |||
12087 | getCustomOperandDiag((ARMMatchResultTy)I.getOperandError()); | |||
12088 | ||||
12089 | // If we have already emitted a message for a superclass, don't also report | |||
12090 | // the sub-class. We consider all operand classes that we don't have a | |||
12091 | // specialised diagnostic for to be equal for the propose of this check, | |||
12092 | // so that we don't report the generic error multiple times on the same | |||
12093 | // operand. | |||
12094 | unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U; | |||
12095 | auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex()); | |||
12096 | if (std::any_of(PrevReports.first, PrevReports.second, | |||
12097 | [DupCheckMatchClass]( | |||
12098 | const std::pair<unsigned, unsigned> Pair) { | |||
12099 | if (DupCheckMatchClass == ~0U || Pair.second == ~0U) | |||
12100 | return Pair.second == DupCheckMatchClass; | |||
12101 | else | |||
12102 | return isSubclass((MatchClassKind)DupCheckMatchClass, | |||
12103 | (MatchClassKind)Pair.second); | |||
12104 | })) | |||
12105 | break; | |||
12106 | OperandMissesSeen.insert( | |||
12107 | std::make_pair(I.getOperandIndex(), DupCheckMatchClass)); | |||
12108 | ||||
12109 | NearMissMessage Message; | |||
12110 | Message.Loc = OperandLoc; | |||
12111 | if (OperandDiag) { | |||
12112 | Message.Message = OperandDiag; | |||
12113 | } else if (I.getOperandClass() == InvalidMatchClass) { | |||
12114 | Message.Message = "too many operands for instruction"; | |||
12115 | } else { | |||
12116 | Message.Message = "invalid operand for instruction"; | |||
12117 | LLVM_DEBUG(do { } while (false) | |||
12118 | dbgs() << "Missing diagnostic string for operand class "do { } while (false) | |||
12119 | << getMatchClassName((MatchClassKind)I.getOperandClass())do { } while (false) | |||
12120 | << I.getOperandClass() << ", error " << I.getOperandError()do { } while (false) | |||
12121 | << ", opcode " << MII.getName(I.getOpcode()) << "\n")do { } while (false); | |||
12122 | } | |||
12123 | NearMissesOut.emplace_back(Message); | |||
12124 | break; | |||
12125 | } | |||
12126 | case NearMissInfo::NearMissFeature: { | |||
12127 | const FeatureBitset &MissingFeatures = I.getFeatures(); | |||
12128 | // Don't report the same set of features twice. | |||
12129 | if (FeatureMissesSeen.count(MissingFeatures)) | |||
12130 | break; | |||
12131 | FeatureMissesSeen.insert(MissingFeatures); | |||
12132 | ||||
12133 | // Special case: don't report a feature set which includes arm-mode for | |||
12134 | // targets that don't have ARM mode. | |||
12135 | if (MissingFeatures.test(Feature_IsARMBit) && !hasARM()) | |||
12136 | break; | |||
12137 | // Don't report any near-misses that both require switching instruction | |||
12138 | // set, and adding other subtarget features. | |||
12139 | if (isThumb() && MissingFeatures.test(Feature_IsARMBit) && | |||
12140 | MissingFeatures.count() > 1) | |||
12141 | break; | |||
12142 | if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) && | |||
12143 | MissingFeatures.count() > 1) | |||
12144 | break; | |||
12145 | if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) && | |||
12146 | (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit, | |||
12147 | Feature_IsThumbBit})).any()) | |||
12148 | break; | |||
12149 | if (isMClass() && MissingFeatures.test(Feature_HasNEONBit)) | |||
12150 | break; | |||
12151 | ||||
12152 | NearMissMessage Message; | |||
12153 | Message.Loc = IDLoc; | |||
12154 | raw_svector_ostream OS(Message.Message); | |||
12155 | ||||
12156 | OS << "instruction requires:"; | |||
12157 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) | |||
12158 | if (MissingFeatures.test(i)) | |||
12159 | OS << ' ' << getSubtargetFeatureName(i); | |||
12160 | ||||
12161 | NearMissesOut.emplace_back(Message); | |||
12162 | ||||
12163 | break; | |||
12164 | } | |||
12165 | case NearMissInfo::NearMissPredicate: { | |||
12166 | NearMissMessage Message; | |||
12167 | Message.Loc = IDLoc; | |||
12168 | switch (I.getPredicateError()) { | |||
12169 | case Match_RequiresNotITBlock: | |||
12170 | Message.Message = "flag setting instruction only valid outside IT block"; | |||
12171 | break; | |||
12172 | case Match_RequiresITBlock: | |||
12173 | Message.Message = "instruction only valid inside IT block"; | |||
12174 | break; | |||
12175 | case Match_RequiresV6: | |||
12176 | Message.Message = "instruction variant requires ARMv6 or later"; | |||
12177 | break; | |||
12178 | case Match_RequiresThumb2: | |||
12179 | Message.Message = "instruction variant requires Thumb2"; | |||
12180 | break; | |||
12181 | case Match_RequiresV8: | |||
12182 | Message.Message = "instruction variant requires ARMv8 or later"; | |||
12183 | break; | |||
12184 | case Match_RequiresFlagSetting: | |||
12185 | Message.Message = "no flag-preserving variant of this instruction available"; | |||
12186 | break; | |||
12187 | case Match_InvalidOperand: | |||
12188 | Message.Message = "invalid operand for instruction"; | |||
12189 | break; | |||
12190 | default: | |||
12191 | llvm_unreachable("Unhandled target predicate error")__builtin_unreachable(); | |||
12192 | break; | |||
12193 | } | |||
12194 | NearMissesOut.emplace_back(Message); | |||
12195 | break; | |||
12196 | } | |||
12197 | case NearMissInfo::NearMissTooFewOperands: { | |||
12198 | if (!ReportedTooFewOperands) { | |||
12199 | SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); | |||
12200 | NearMissesOut.emplace_back(NearMissMessage{ | |||
12201 | EndLoc, StringRef("too few operands for instruction")}); | |||
12202 | ReportedTooFewOperands = true; | |||
12203 | } | |||
12204 | break; | |||
12205 | } | |||
12206 | case NearMissInfo::NoNearMiss: | |||
12207 | // This should never leave the matcher. | |||
12208 | llvm_unreachable("not a near-miss")__builtin_unreachable(); | |||
12209 | break; | |||
12210 | } | |||
12211 | } | |||
12212 | } | |||
12213 | ||||
12214 | void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, | |||
12215 | SMLoc IDLoc, OperandVector &Operands) { | |||
12216 | SmallVector<NearMissMessage, 4> Messages; | |||
12217 | FilterNearMisses(NearMisses, Messages, IDLoc, Operands); | |||
12218 | ||||
12219 | if (Messages.size() == 0) { | |||
12220 | // No near-misses were found, so the best we can do is "invalid | |||
12221 | // instruction". | |||
12222 | Error(IDLoc, "invalid instruction"); | |||
12223 | } else if (Messages.size() == 1) { | |||
12224 | // One near miss was found, report it as the sole error. | |||
12225 | Error(Messages[0].Loc, Messages[0].Message); | |||
12226 | } else { | |||
12227 | // More than one near miss, so report a generic "invalid instruction" | |||
12228 | // error, followed by notes for each of the near-misses. | |||
12229 | Error(IDLoc, "invalid instruction, any one of the following would fix this:"); | |||
12230 | for (auto &M : Messages) { | |||
12231 | Note(M.Loc, M.Message); | |||
12232 | } | |||
12233 | } | |||
12234 | } | |||
12235 | ||||
12236 | bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) { | |||
12237 | // FIXME: This structure should be moved inside ARMTargetParser | |||
12238 | // when we start to table-generate them, and we can use the ARM | |||
12239 | // flags below, that were generated by table-gen. | |||
12240 | static const struct { | |||
12241 | const uint64_t Kind; | |||
12242 | const FeatureBitset ArchCheck; | |||
12243 | const FeatureBitset Features; | |||
12244 | } Extensions[] = { | |||
12245 | {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}}, | |||
12246 | {ARM::AEK_AES, | |||
12247 | {Feature_HasV8Bit}, | |||
12248 | {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, | |||
12249 | {ARM::AEK_SHA2, | |||
12250 | {Feature_HasV8Bit}, | |||
12251 | {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, | |||
12252 | {ARM::AEK_CRYPTO, | |||
12253 | {Feature_HasV8Bit}, | |||
12254 | {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, | |||
12255 | {ARM::AEK_FP, | |||
12256 | {Feature_HasV8Bit}, | |||
12257 | {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, | |||
12258 | {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), | |||
12259 | {Feature_HasV7Bit, Feature_IsNotMClassBit}, | |||
12260 | {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}}, | |||
12261 | {ARM::AEK_MP, | |||
12262 | {Feature_HasV7Bit, Feature_IsNotMClassBit}, | |||
12263 | {ARM::FeatureMP}}, | |||
12264 | {ARM::AEK_SIMD, | |||
12265 | {Feature_HasV8Bit}, | |||
12266 | {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, | |||
12267 | {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}}, | |||
12268 | // FIXME: Only available in A-class, isel not predicated | |||
12269 | {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}}, | |||
12270 | {ARM::AEK_FP16, | |||
12271 | {Feature_HasV8_2aBit}, | |||
12272 | {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}}, | |||
12273 | {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}}, | |||
12274 | {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}}, | |||
12275 | // FIXME: Unsupported extensions. | |||
12276 | {ARM::AEK_OS, {}, {}}, | |||
12277 | {ARM::AEK_IWMMXT, {}, {}}, | |||
12278 | {ARM::AEK_IWMMXT2, {}, {}}, | |||
12279 | {ARM::AEK_MAVERICK, {}, {}}, | |||
12280 | {ARM::AEK_XSCALE, {}, {}}, | |||
12281 | }; | |||
12282 | bool EnableFeature = true; | |||
12283 | if (Name.startswith_insensitive("no")) { | |||
12284 | EnableFeature = false; | |||
12285 | Name = Name.substr(2); | |||
12286 | } | |||
12287 | uint64_t FeatureKind = ARM::parseArchExt(Name); | |||
12288 | if (FeatureKind == ARM::AEK_INVALID) | |||
12289 | return Error(ExtLoc, "unknown architectural extension: " + Name); | |||
12290 | ||||
12291 | for (const auto &Extension : Extensions) { | |||
12292 | if (Extension.Kind != FeatureKind) | |||
12293 | continue; | |||
12294 | ||||
12295 | if (Extension.Features.none()) | |||
12296 | return Error(ExtLoc, "unsupported architectural extension: " + Name); | |||
12297 | ||||
12298 | if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) | |||
12299 | return Error(ExtLoc, "architectural extension '" + Name + | |||
12300 | "' is not " | |||
12301 | "allowed for the current base architecture"); | |||
12302 | ||||
12303 | MCSubtargetInfo &STI = copySTI(); | |||
12304 | if (EnableFeature) { | |||
12305 | STI.SetFeatureBitsTransitively(Extension.Features); | |||
12306 | } else { | |||
12307 | STI.ClearFeatureBitsTransitively(Extension.Features); | |||
12308 | } | |||
12309 | FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits()); | |||
12310 | setAvailableFeatures(Features); | |||
12311 | return true; | |||
12312 | } | |||
12313 | return false; | |||
12314 | } | |||
12315 | ||||
12316 | /// parseDirectiveArchExtension | |||
12317 | /// ::= .arch_extension [no]feature | |||
12318 | bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { | |||
12319 | ||||
12320 | MCAsmParser &Parser = getParser(); | |||
12321 | ||||
12322 | if (getLexer().isNot(AsmToken::Identifier)) | |||
12323 | return Error(getLexer().getLoc(), "expected architecture extension name"); | |||
12324 | ||||
12325 | StringRef Name = Parser.getTok().getString(); | |||
12326 | SMLoc ExtLoc = Parser.getTok().getLoc(); | |||
12327 | Lex(); | |||
12328 | ||||
12329 | if (parseToken(AsmToken::EndOfStatement, | |||
12330 | "unexpected token in '.arch_extension' directive")) | |||
12331 | return true; | |||
12332 | ||||
12333 | if (Name == "nocrypto") { | |||
12334 | enableArchExtFeature("nosha2", ExtLoc); | |||
12335 | enableArchExtFeature("noaes", ExtLoc); | |||
12336 | } | |||
12337 | ||||
12338 | if (enableArchExtFeature(Name, ExtLoc)) | |||
12339 | return false; | |||
12340 | ||||
12341 | return Error(ExtLoc, "unknown architectural extension: " + Name); | |||
12342 | } | |||
12343 | ||||
12344 | // Define this matcher function after the auto-generated include so we | |||
12345 | // have the match class enum definitions. | |||
12346 | unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, | |||
12347 | unsigned Kind) { | |||
12348 | ARMOperand &Op = static_cast<ARMOperand &>(AsmOp); | |||
12349 | // If the kind is a token for a literal immediate, check if our asm | |||
12350 | // operand matches. This is for InstAliases which have a fixed-value | |||
12351 | // immediate in the syntax. | |||
12352 | switch (Kind) { | |||
12353 | default: break; | |||
12354 | case MCK__HASH_0: | |||
12355 | if (Op.isImm()) | |||
12356 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) | |||
12357 | if (CE->getValue() == 0) | |||
12358 | return Match_Success; | |||
12359 | break; | |||
12360 | case MCK__HASH_8: | |||
12361 | if (Op.isImm()) | |||
12362 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) | |||
12363 | if (CE->getValue() == 8) | |||
12364 | return Match_Success; | |||
12365 | break; | |||
12366 | case MCK__HASH_16: | |||
12367 | if (Op.isImm()) | |||
12368 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) | |||
12369 | if (CE->getValue() == 16) | |||
12370 | return Match_Success; | |||
12371 | break; | |||
12372 | case MCK_ModImm: | |||
12373 | if (Op.isImm()) { | |||
12374 | const MCExpr *SOExpr = Op.getImm(); | |||
12375 | int64_t Value; | |||
12376 | if (!SOExpr->evaluateAsAbsolute(Value)) | |||
12377 | return Match_Success; | |||
12378 | assert((Value >= std::numeric_limits<int32_t>::min() &&(static_cast<void> (0)) | |||
12379 | Value <= std::numeric_limits<uint32_t>::max()) &&(static_cast<void> (0)) | |||
12380 | "expression value must be representable in 32 bits")(static_cast<void> (0)); | |||
12381 | } | |||
12382 | break; | |||
12383 | case MCK_rGPR: | |||
12384 | if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) | |||
12385 | return Match_Success; | |||
12386 | return Match_rGPR; | |||
12387 | case MCK_GPRPair: | |||
12388 | if (Op.isReg() && | |||
12389 | MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) | |||
12390 | return Match_Success; | |||
12391 | break; | |||
12392 | } | |||
12393 | return Match_InvalidOperand; | |||
12394 | } | |||
12395 | ||||
12396 | bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic, | |||
12397 | StringRef ExtraToken) { | |||
12398 | if (!hasMVE()) | |||
12399 | return false; | |||
12400 | ||||
12401 | return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") || | |||
12402 | Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") || | |||
12403 | Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") || | |||
12404 | Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") || | |||
12405 | Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") || | |||
12406 | Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") || | |||
12407 | Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") || | |||
12408 | Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") || | |||
12409 | Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") || | |||
12410 | Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") || | |||
12411 | Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") || | |||
12412 | Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") || | |||
12413 | Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") || | |||
12414 | Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") || | |||
12415 | Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") || | |||
12416 | Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") || | |||
12417 | Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") || | |||
12418 | Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") || | |||
12419 | Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") || | |||
12420 | Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") || | |||
12421 | Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") || | |||
12422 | Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") || | |||
12423 | Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") || | |||
12424 | Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") || | |||
12425 | Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") || | |||
12426 | Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") || | |||
12427 | Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") || | |||
12428 | Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") || | |||
12429 | Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") || | |||
12430 | Mnemonic.startswith("vqabs") || | |||
12431 | (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") || | |||
12432 | Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") || | |||
12433 | Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") || | |||
12434 | Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") || | |||
12435 | Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") || | |||
12436 | Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") || | |||
12437 | Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") || | |||
12438 | Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") || | |||
12439 | Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") || | |||
12440 | Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") || | |||
12441 | Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") || | |||
12442 | Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") || | |||
12443 | Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") || | |||
12444 | Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") || | |||
12445 | Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") || | |||
12446 | Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") || | |||
12447 | Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") || | |||
12448 | Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") || | |||
12449 | Mnemonic.startswith("vldrb") || | |||
12450 | (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") || | |||
12451 | (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") || | |||
12452 | Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") || | |||
12453 | Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") || | |||
12454 | Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") || | |||
12455 | Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") || | |||
12456 | Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") || | |||
12457 | Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") || | |||
12458 | Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") || | |||
12459 | Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") || | |||
12460 | Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") || | |||
12461 | Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") || | |||
12462 | Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") || | |||
12463 | Mnemonic.startswith("vcvt") || | |||
12464 | MS.isVPTPredicableCDEInstr(Mnemonic) || | |||
12465 | (Mnemonic.startswith("vmov") && | |||
12466 | !(ExtraToken == ".f16" || ExtraToken == ".32" || | |||
12467 | ExtraToken == ".16" || ExtraToken == ".8")); | |||
12468 | } |