Bug Summary

File:build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Warning:line 11352, column 11
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMAsmParser.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-15/lib/clang/15.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM/AsmParser -I /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/ARM/AsmParser -I /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/ARM -I lib/Target/ARM -I include -I /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-15/lib/clang/15.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-04-20-140412-16051-1 -x c++ /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
1//===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
10#include "ARMFeatures.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMInstPrinter.h"
14#include "MCTargetDesc/ARMMCExpr.h"
15#include "MCTargetDesc/ARMMCTargetDesc.h"
16#include "TargetInfo/ARMTargetInfo.h"
17#include "Utils/ARMBaseInfo.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/None.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/StringMap.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSet.h"
27#include "llvm/ADT/StringSwitch.h"
28#include "llvm/ADT/Triple.h"
29#include "llvm/ADT/Twine.h"
30#include "llvm/MC/MCContext.h"
31#include "llvm/MC/MCExpr.h"
32#include "llvm/MC/MCInst.h"
33#include "llvm/MC/MCInstrDesc.h"
34#include "llvm/MC/MCInstrInfo.h"
35#include "llvm/MC/MCParser/MCAsmLexer.h"
36#include "llvm/MC/MCParser/MCAsmParser.h"
37#include "llvm/MC/MCParser/MCAsmParserExtension.h"
38#include "llvm/MC/MCParser/MCAsmParserUtils.h"
39#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
40#include "llvm/MC/MCParser/MCTargetAsmParser.h"
41#include "llvm/MC/MCRegisterInfo.h"
42#include "llvm/MC/MCSection.h"
43#include "llvm/MC/MCStreamer.h"
44#include "llvm/MC/MCSubtargetInfo.h"
45#include "llvm/MC/MCSymbol.h"
46#include "llvm/MC/SubtargetFeature.h"
47#include "llvm/MC/TargetRegistry.h"
48#include "llvm/Support/ARMBuildAttributes.h"
49#include "llvm/Support/ARMEHABI.h"
50#include "llvm/Support/Casting.h"
51#include "llvm/Support/CommandLine.h"
52#include "llvm/Support/Compiler.h"
53#include "llvm/Support/ErrorHandling.h"
54#include "llvm/Support/MathExtras.h"
55#include "llvm/Support/SMLoc.h"
56#include "llvm/Support/TargetParser.h"
57#include "llvm/Support/raw_ostream.h"
58#include <algorithm>
59#include <cassert>
60#include <cstddef>
61#include <cstdint>
62#include <iterator>
63#include <limits>
64#include <memory>
65#include <string>
66#include <utility>
67#include <vector>
68
69#define DEBUG_TYPE"asm-parser" "asm-parser"
70
71using namespace llvm;
72
73namespace llvm {
74extern const MCInstrDesc ARMInsts[];
75} // end namespace llvm
76
77namespace {
78
79enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
80
81static cl::opt<ImplicitItModeTy> ImplicitItMode(
82 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
83 cl::desc("Allow conditional instructions outdside of an IT block"),
84 cl::values(clEnumValN(ImplicitItModeTy::Always, "always",llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always
), "Accept in both ISAs, emit implicit ITs in Thumb" }
85 "Accept in both ISAs, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always
), "Accept in both ISAs, emit implicit ITs in Thumb" }
,
86 clEnumValN(ImplicitItModeTy::Never, "never",llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never
), "Warn in ARM, reject in Thumb" }
87 "Warn in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never
), "Warn in ARM, reject in Thumb" }
,
88 clEnumValN(ImplicitItModeTy::ARMOnly, "arm",llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly
), "Accept in ARM, reject in Thumb" }
89 "Accept in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly
), "Accept in ARM, reject in Thumb" }
,
90 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly
), "Warn in ARM, emit implicit ITs in Thumb" }
91 "Warn in ARM, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly
), "Warn in ARM, emit implicit ITs in Thumb" }
));
92
93static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
94 cl::init(false));
95
96enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
97
98static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
99 // Position==0 means we're not in an IT block at all. Position==1
100 // means we want the first state bit, which is always 0 (Then).
101 // Position==2 means we want the second state bit, stored at bit 3
102 // of Mask, and so on downwards. So (5 - Position) will shift the
103 // right bit down to bit 0, including the always-0 bit at bit 4 for
104 // the mandatory initial Then.
105 return (Mask >> (5 - Position) & 1);
106}
107
108class UnwindContext {
109 using Locs = SmallVector<SMLoc, 4>;
110
111 MCAsmParser &Parser;
112 Locs FnStartLocs;
113 Locs CantUnwindLocs;
114 Locs PersonalityLocs;
115 Locs PersonalityIndexLocs;
116 Locs HandlerDataLocs;
117 int FPReg;
118
119public:
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
121
122 bool hasFnStart() const { return !FnStartLocs.empty(); }
123 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
124 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
125
126 bool hasPersonality() const {
127 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
128 }
129
130 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
131 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
132 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
133 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
134 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
135
136 void saveFPReg(int Reg) { FPReg = Reg; }
137 int getFPReg() const { return FPReg; }
138
139 void emitFnStartLocNotes() const {
140 for (const SMLoc &Loc : FnStartLocs)
141 Parser.Note(Loc, ".fnstart was specified here");
142 }
143
144 void emitCantUnwindLocNotes() const {
145 for (const SMLoc &Loc : CantUnwindLocs)
146 Parser.Note(Loc, ".cantunwind was specified here");
147 }
148
149 void emitHandlerDataLocNotes() const {
150 for (const SMLoc &Loc : HandlerDataLocs)
151 Parser.Note(Loc, ".handlerdata was specified here");
152 }
153
154 void emitPersonalityLocNotes() const {
155 for (Locs::const_iterator PI = PersonalityLocs.begin(),
156 PE = PersonalityLocs.end(),
157 PII = PersonalityIndexLocs.begin(),
158 PIE = PersonalityIndexLocs.end();
159 PI != PE || PII != PIE;) {
160 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
161 Parser.Note(*PI++, ".personality was specified here");
162 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
163 Parser.Note(*PII++, ".personalityindex was specified here");
164 else
165 llvm_unreachable(".personality and .personalityindex cannot be "::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be "
"at the same location", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 166)
166 "at the same location")::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be "
"at the same location", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 166)
;
167 }
168 }
169
170 void reset() {
171 FnStartLocs = Locs();
172 CantUnwindLocs = Locs();
173 PersonalityLocs = Locs();
174 HandlerDataLocs = Locs();
175 PersonalityIndexLocs = Locs();
176 FPReg = ARM::SP;
177 }
178};
179
180// Various sets of ARM instruction mnemonics which are used by the asm parser
181class ARMMnemonicSets {
182 StringSet<> CDE;
183 StringSet<> CDEWithVPTSuffix;
184public:
185 ARMMnemonicSets(const MCSubtargetInfo &STI);
186
187 /// Returns true iff a given mnemonic is a CDE instruction
188 bool isCDEInstr(StringRef Mnemonic) {
189 // Quick check before searching the set
190 if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx"))
191 return false;
192 return CDE.count(Mnemonic);
193 }
194
195 /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction
196 /// (possibly with a predication suffix "e" or "t")
197 bool isVPTPredicableCDEInstr(StringRef Mnemonic) {
198 if (!Mnemonic.startswith("vcx"))
199 return false;
200 return CDEWithVPTSuffix.count(Mnemonic);
201 }
202
203 /// Returns true iff a given mnemonic is an IT-predicable CDE instruction
204 /// (possibly with a condition suffix)
205 bool isITPredicableCDEInstr(StringRef Mnemonic) {
206 if (!Mnemonic.startswith("cx"))
207 return false;
208 return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") ||
209 Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") ||
210 Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da");
211 }
212
213 /// Return true iff a given mnemonic is an integer CDE instruction with
214 /// dual-register destination
215 bool isCDEDualRegInstr(StringRef Mnemonic) {
216 if (!Mnemonic.startswith("cx"))
217 return false;
218 return Mnemonic == "cx1d" || Mnemonic == "cx1da" ||
219 Mnemonic == "cx2d" || Mnemonic == "cx2da" ||
220 Mnemonic == "cx3d" || Mnemonic == "cx3da";
221 }
222};
223
224ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) {
225 for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da",
226 "cx2", "cx2a", "cx2d", "cx2da",
227 "cx3", "cx3a", "cx3d", "cx3da", })
228 CDE.insert(Mnemonic);
229 for (StringRef Mnemonic :
230 {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) {
231 CDE.insert(Mnemonic);
232 CDEWithVPTSuffix.insert(Mnemonic);
233 CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t");
234 CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e");
235 }
236}
237
238class ARMAsmParser : public MCTargetAsmParser {
239 const MCRegisterInfo *MRI;
240 UnwindContext UC;
241 ARMMnemonicSets MS;
242
243 ARMTargetStreamer &getTargetStreamer() {
244 assert(getParser().getStreamer().getTargetStreamer() &&(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 245, __extension__
__PRETTY_FUNCTION__))
245 "do not have a target streamer")(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 245, __extension__
__PRETTY_FUNCTION__))
;
246 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
247 return static_cast<ARMTargetStreamer &>(TS);
248 }
249
250 // Map of register aliases registers via the .req directive.
251 StringMap<unsigned> RegisterReqs;
252
253 bool NextSymbolIsThumb;
254
255 bool useImplicitITThumb() const {
256 return ImplicitItMode == ImplicitItModeTy::Always ||
257 ImplicitItMode == ImplicitItModeTy::ThumbOnly;
258 }
259
260 bool useImplicitITARM() const {
261 return ImplicitItMode == ImplicitItModeTy::Always ||
262 ImplicitItMode == ImplicitItModeTy::ARMOnly;
263 }
264
265 struct {
266 ARMCC::CondCodes Cond; // Condition for IT block.
267 unsigned Mask:4; // Condition mask for instructions.
268 // Starting at first 1 (from lsb).
269 // '1' condition as indicated in IT.
270 // '0' inverse of condition (else).
271 // Count of instructions in IT block is
272 // 4 - trailingzeroes(mask)
273 // Note that this does not have the same encoding
274 // as in the IT instruction, which also depends
275 // on the low bit of the condition code.
276
277 unsigned CurPosition; // Current position in parsing of IT
278 // block. In range [0,4], with 0 being the IT
279 // instruction itself. Initialized according to
280 // count of instructions in block. ~0U if no
281 // active IT block.
282
283 bool IsExplicit; // true - The IT instruction was present in the
284 // input, we should not modify it.
285 // false - The IT instruction was added
286 // implicitly, we can extend it if that
287 // would be legal.
288 } ITState;
289
290 SmallVector<MCInst, 4> PendingConditionalInsts;
291
292 void flushPendingInstructions(MCStreamer &Out) override {
293 if (!inImplicitITBlock()) {
294 assert(PendingConditionalInsts.size() == 0)(static_cast <bool> (PendingConditionalInsts.size() == 0
) ? void (0) : __assert_fail ("PendingConditionalInsts.size() == 0"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 294, __extension__
__PRETTY_FUNCTION__))
;
295 return;
296 }
297
298 // Emit the IT instruction
299 MCInst ITInst;
300 ITInst.setOpcode(ARM::t2IT);
301 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
302 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
303 Out.emitInstruction(ITInst, getSTI());
304
305 // Emit the conditonal instructions
306 assert(PendingConditionalInsts.size() <= 4)(static_cast <bool> (PendingConditionalInsts.size() <=
4) ? void (0) : __assert_fail ("PendingConditionalInsts.size() <= 4"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 306, __extension__
__PRETTY_FUNCTION__))
;
307 for (const MCInst &Inst : PendingConditionalInsts) {
308 Out.emitInstruction(Inst, getSTI());
309 }
310 PendingConditionalInsts.clear();
311
312 // Clear the IT state
313 ITState.Mask = 0;
314 ITState.CurPosition = ~0U;
315 }
316
317 bool inITBlock() { return ITState.CurPosition != ~0U; }
318 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
319 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
320
321 bool lastInITBlock() {
322 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
323 }
324
325 void forwardITPosition() {
326 if (!inITBlock()) return;
327 // Move to the next instruction in the IT block, if there is one. If not,
328 // mark the block as done, except for implicit IT blocks, which we leave
329 // open until we find an instruction that can't be added to it.
330 unsigned TZ = countTrailingZeros(ITState.Mask);
331 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
332 ITState.CurPosition = ~0U; // Done with the IT block after this.
333 }
334
335 // Rewind the state of the current IT block, removing the last slot from it.
336 void rewindImplicitITPosition() {
337 assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail
("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 337, __extension__ __PRETTY_FUNCTION__))
;
338 assert(ITState.CurPosition > 1)(static_cast <bool> (ITState.CurPosition > 1) ? void
(0) : __assert_fail ("ITState.CurPosition > 1", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 338, __extension__ __PRETTY_FUNCTION__))
;
339 ITState.CurPosition--;
340 unsigned TZ = countTrailingZeros(ITState.Mask);
341 unsigned NewMask = 0;
342 NewMask |= ITState.Mask & (0xC << TZ);
343 NewMask |= 0x2 << TZ;
344 ITState.Mask = NewMask;
345 }
346
347 // Rewind the state of the current IT block, removing the last slot from it.
348 // If we were at the first slot, this closes the IT block.
349 void discardImplicitITBlock() {
350 assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail
("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 350, __extension__ __PRETTY_FUNCTION__))
;
351 assert(ITState.CurPosition == 1)(static_cast <bool> (ITState.CurPosition == 1) ? void (
0) : __assert_fail ("ITState.CurPosition == 1", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 351, __extension__ __PRETTY_FUNCTION__))
;
352 ITState.CurPosition = ~0U;
353 }
354
355 // Return the low-subreg of a given Q register.
356 unsigned getDRegFromQReg(unsigned QReg) const {
357 return MRI->getSubReg(QReg, ARM::dsub_0);
358 }
359
360 // Get the condition code corresponding to the current IT block slot.
361 ARMCC::CondCodes currentITCond() {
362 unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
363 return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
364 }
365
366 // Invert the condition of the current IT block slot without changing any
367 // other slots in the same block.
368 void invertCurrentITCondition() {
369 if (ITState.CurPosition == 1) {
370 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
371 } else {
372 ITState.Mask ^= 1 << (5 - ITState.CurPosition);
373 }
374 }
375
376 // Returns true if the current IT block is full (all 4 slots used).
377 bool isITBlockFull() {
378 return inITBlock() && (ITState.Mask & 1);
379 }
380
381 // Extend the current implicit IT block to have one more slot with the given
382 // condition code.
383 void extendImplicitITBlock(ARMCC::CondCodes Cond) {
384 assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail
("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 384, __extension__ __PRETTY_FUNCTION__))
;
385 assert(!isITBlockFull())(static_cast <bool> (!isITBlockFull()) ? void (0) : __assert_fail
("!isITBlockFull()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 385, __extension__ __PRETTY_FUNCTION__))
;
386 assert(Cond == ITState.Cond ||(static_cast <bool> (Cond == ITState.Cond || Cond == ARMCC
::getOppositeCondition(ITState.Cond)) ? void (0) : __assert_fail
("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 387, __extension__
__PRETTY_FUNCTION__))
387 Cond == ARMCC::getOppositeCondition(ITState.Cond))(static_cast <bool> (Cond == ITState.Cond || Cond == ARMCC
::getOppositeCondition(ITState.Cond)) ? void (0) : __assert_fail
("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 387, __extension__
__PRETTY_FUNCTION__))
;
388 unsigned TZ = countTrailingZeros(ITState.Mask);
389 unsigned NewMask = 0;
390 // Keep any existing condition bits.
391 NewMask |= ITState.Mask & (0xE << TZ);
392 // Insert the new condition bit.
393 NewMask |= (Cond != ITState.Cond) << TZ;
394 // Move the trailing 1 down one bit.
395 NewMask |= 1 << (TZ - 1);
396 ITState.Mask = NewMask;
397 }
398
399 // Create a new implicit IT block with a dummy condition code.
400 void startImplicitITBlock() {
401 assert(!inITBlock())(static_cast <bool> (!inITBlock()) ? void (0) : __assert_fail
("!inITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
;
402 ITState.Cond = ARMCC::AL;
403 ITState.Mask = 8;
404 ITState.CurPosition = 1;
405 ITState.IsExplicit = false;
406 }
407
408 // Create a new explicit IT block with the given condition and mask.
409 // The mask should be in the format used in ARMOperand and
410 // MCOperand, with a 1 implying 'e', regardless of the low bit of
411 // the condition.
412 void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
413 assert(!inITBlock())(static_cast <bool> (!inITBlock()) ? void (0) : __assert_fail
("!inITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 413, __extension__ __PRETTY_FUNCTION__))
;
414 ITState.Cond = Cond;
415 ITState.Mask = Mask;
416 ITState.CurPosition = 0;
417 ITState.IsExplicit = true;
418 }
419
420 struct {
421 unsigned Mask : 4;
422 unsigned CurPosition;
423 } VPTState;
424 bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
425 void forwardVPTPosition() {
426 if (!inVPTBlock()) return;
427 unsigned TZ = countTrailingZeros(VPTState.Mask);
428 if (++VPTState.CurPosition == 5 - TZ)
429 VPTState.CurPosition = ~0U;
430 }
431
432 void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
433 return getParser().Note(L, Msg, Range);
434 }
435
436 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
437 return getParser().Warning(L, Msg, Range);
438 }
439
440 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
441 return getParser().Error(L, Msg, Range);
442 }
443
444 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
445 unsigned ListNo, bool IsARPop = false);
446 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
447 unsigned ListNo);
448
449 int tryParseRegister();
450 bool tryParseRegisterWithWriteBack(OperandVector &);
451 int tryParseShiftRegister(OperandVector &);
452 bool parseRegisterList(OperandVector &, bool EnforceOrder = true,
453 bool AllowRAAC = false);
454 bool parseMemory(OperandVector &);
455 bool parseOperand(OperandVector &, StringRef Mnemonic);
456 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
457 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
458 unsigned &ShiftAmount);
459 bool parseLiteralValues(unsigned Size, SMLoc L);
460 bool parseDirectiveThumb(SMLoc L);
461 bool parseDirectiveARM(SMLoc L);
462 bool parseDirectiveThumbFunc(SMLoc L);
463 bool parseDirectiveCode(SMLoc L);
464 bool parseDirectiveSyntax(SMLoc L);
465 bool parseDirectiveReq(StringRef Name, SMLoc L);
466 bool parseDirectiveUnreq(SMLoc L);
467 bool parseDirectiveArch(SMLoc L);
468 bool parseDirectiveEabiAttr(SMLoc L);
469 bool parseDirectiveCPU(SMLoc L);
470 bool parseDirectiveFPU(SMLoc L);
471 bool parseDirectiveFnStart(SMLoc L);
472 bool parseDirectiveFnEnd(SMLoc L);
473 bool parseDirectiveCantUnwind(SMLoc L);
474 bool parseDirectivePersonality(SMLoc L);
475 bool parseDirectiveHandlerData(SMLoc L);
476 bool parseDirectiveSetFP(SMLoc L);
477 bool parseDirectivePad(SMLoc L);
478 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
479 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
480 bool parseDirectiveLtorg(SMLoc L);
481 bool parseDirectiveEven(SMLoc L);
482 bool parseDirectivePersonalityIndex(SMLoc L);
483 bool parseDirectiveUnwindRaw(SMLoc L);
484 bool parseDirectiveTLSDescSeq(SMLoc L);
485 bool parseDirectiveMovSP(SMLoc L);
486 bool parseDirectiveObjectArch(SMLoc L);
487 bool parseDirectiveArchExtension(SMLoc L);
488 bool parseDirectiveAlign(SMLoc L);
489 bool parseDirectiveThumbSet(SMLoc L);
490
491 bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
492 StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
493 unsigned &PredicationCode,
494 unsigned &VPTPredicationCode, bool &CarrySetting,
495 unsigned &ProcessorIMod, StringRef &ITMask);
496 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
497 StringRef FullInst, bool &CanAcceptCarrySet,
498 bool &CanAcceptPredicationCode,
499 bool &CanAcceptVPTPredicationCode);
500 bool enableArchExtFeature(StringRef Name, SMLoc &ExtLoc);
501
502 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
503 OperandVector &Operands);
504 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
505
506 bool isThumb() const {
507 // FIXME: Can tablegen auto-generate this?
508 return getSTI().getFeatureBits()[ARM::ModeThumb];
509 }
510
511 bool isThumbOne() const {
512 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
513 }
514
515 bool isThumbTwo() const {
516 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
517 }
518
519 bool hasThumb() const {
520 return getSTI().getFeatureBits()[ARM::HasV4TOps];
521 }
522
523 bool hasThumb2() const {
524 return getSTI().getFeatureBits()[ARM::FeatureThumb2];
525 }
526
527 bool hasV6Ops() const {
528 return getSTI().getFeatureBits()[ARM::HasV6Ops];
529 }
530
531 bool hasV6T2Ops() const {
532 return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
533 }
534
535 bool hasV6MOps() const {
536 return getSTI().getFeatureBits()[ARM::HasV6MOps];
537 }
538
539 bool hasV7Ops() const {
540 return getSTI().getFeatureBits()[ARM::HasV7Ops];
541 }
542
543 bool hasV8Ops() const {
544 return getSTI().getFeatureBits()[ARM::HasV8Ops];
545 }
546
547 bool hasV8MBaseline() const {
548 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
549 }
550
551 bool hasV8MMainline() const {
552 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
553 }
554 bool hasV8_1MMainline() const {
555 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
556 }
557 bool hasMVE() const {
558 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
559 }
560 bool hasMVEFloat() const {
561 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
562 }
563 bool hasCDE() const {
564 return getSTI().getFeatureBits()[ARM::HasCDEOps];
565 }
566 bool has8MSecExt() const {
567 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
568 }
569
570 bool hasARM() const {
571 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
572 }
573
574 bool hasDSP() const {
575 return getSTI().getFeatureBits()[ARM::FeatureDSP];
576 }
577
578 bool hasD32() const {
579 return getSTI().getFeatureBits()[ARM::FeatureD32];
580 }
581
582 bool hasV8_1aOps() const {
583 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
584 }
585
586 bool hasRAS() const {
587 return getSTI().getFeatureBits()[ARM::FeatureRAS];
588 }
589
590 void SwitchMode() {
591 MCSubtargetInfo &STI = copySTI();
592 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
593 setAvailableFeatures(FB);
594 }
595
596 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
597
598 bool isMClass() const {
599 return getSTI().getFeatureBits()[ARM::FeatureMClass];
600 }
601
602 /// @name Auto-generated Match Functions
603 /// {
604
605#define GET_ASSEMBLER_HEADER
606#include "ARMGenAsmMatcher.inc"
607
608 /// }
609
610 OperandMatchResultTy parseITCondCode(OperandVector &);
611 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
612 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
613 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
614 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
615 OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
616 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
617 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
618 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
619 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
620 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
621 int High);
622 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
623 return parsePKHImm(O, "lsl", 0, 31);
624 }
625 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
626 return parsePKHImm(O, "asr", 1, 32);
627 }
628 OperandMatchResultTy parseSetEndImm(OperandVector &);
629 OperandMatchResultTy parseShifterImm(OperandVector &);
630 OperandMatchResultTy parseRotImm(OperandVector &);
631 OperandMatchResultTy parseModImm(OperandVector &);
632 OperandMatchResultTy parseBitfield(OperandVector &);
633 OperandMatchResultTy parsePostIdxReg(OperandVector &);
634 OperandMatchResultTy parseAM3Offset(OperandVector &);
635 OperandMatchResultTy parseFPImm(OperandVector &);
636 OperandMatchResultTy parseVectorList(OperandVector &);
637 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
638 SMLoc &EndLoc);
639
640 // Asm Match Converter Methods
641 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
642 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
643 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
644
645 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
646 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
647 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
648 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
649 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
650 bool isITBlockTerminator(MCInst &Inst) const;
651 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
652 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
653 bool Load, bool ARMMode, bool Writeback);
654
655public:
656 enum ARMMatchResultTy {
657 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
658 Match_RequiresNotITBlock,
659 Match_RequiresV6,
660 Match_RequiresThumb2,
661 Match_RequiresV8,
662 Match_RequiresFlagSetting,
663#define GET_OPERAND_DIAGNOSTIC_TYPES
664#include "ARMGenAsmMatcher.inc"
665
666 };
667
668 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
669 const MCInstrInfo &MII, const MCTargetOptions &Options)
670 : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) {
671 MCAsmParserExtension::Initialize(Parser);
672
673 // Cache the MCRegisterInfo.
674 MRI = getContext().getRegisterInfo();
675
676 // Initialize the set of available features.
677 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
678
679 // Add build attributes based on the selected target.
680 if (AddBuildAttributes)
681 getTargetStreamer().emitTargetAttributes(STI);
682
683 // Not in an ITBlock to start with.
684 ITState.CurPosition = ~0U;
685
686 VPTState.CurPosition = ~0U;
687
688 NextSymbolIsThumb = false;
689 }
690
691 // Implementation of the MCTargetAsmParser interface:
692 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
693 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
694 SMLoc &EndLoc) override;
695 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
696 SMLoc NameLoc, OperandVector &Operands) override;
697 bool ParseDirective(AsmToken DirectiveID) override;
698
699 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
700 unsigned Kind) override;
701 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
702
703 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
704 OperandVector &Operands, MCStreamer &Out,
705 uint64_t &ErrorInfo,
706 bool MatchingInlineAsm) override;
707 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
708 SmallVectorImpl<NearMissInfo> &NearMisses,
709 bool MatchingInlineAsm, bool &EmitInITBlock,
710 MCStreamer &Out);
711
712 struct NearMissMessage {
713 SMLoc Loc;
714 SmallString<128> Message;
715 };
716
717 const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
718
719 void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
720 SmallVectorImpl<NearMissMessage> &NearMissesOut,
721 SMLoc IDLoc, OperandVector &Operands);
722 void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
723 OperandVector &Operands);
724
725 void doBeforeLabelEmit(MCSymbol *Symbol) override;
726
727 void onLabelParsed(MCSymbol *Symbol) override;
728};
729
730/// ARMOperand - Instances of this class represent a parsed ARM machine
731/// operand.
732class ARMOperand : public MCParsedAsmOperand {
733 enum KindTy {
734 k_CondCode,
735 k_VPTPred,
736 k_CCOut,
737 k_ITCondMask,
738 k_CoprocNum,
739 k_CoprocReg,
740 k_CoprocOption,
741 k_Immediate,
742 k_MemBarrierOpt,
743 k_InstSyncBarrierOpt,
744 k_TraceSyncBarrierOpt,
745 k_Memory,
746 k_PostIndexRegister,
747 k_MSRMask,
748 k_BankedReg,
749 k_ProcIFlags,
750 k_VectorIndex,
751 k_Register,
752 k_RegisterList,
753 k_RegisterListWithAPSR,
754 k_DPRRegisterList,
755 k_SPRRegisterList,
756 k_FPSRegisterListWithVPR,
757 k_FPDRegisterListWithVPR,
758 k_VectorList,
759 k_VectorListAllLanes,
760 k_VectorListIndexed,
761 k_ShiftedRegister,
762 k_ShiftedImmediate,
763 k_ShifterImmediate,
764 k_RotateImmediate,
765 k_ModifiedImmediate,
766 k_ConstantPoolImmediate,
767 k_BitfieldDescriptor,
768 k_Token,
769 } Kind;
770
771 SMLoc StartLoc, EndLoc, AlignmentLoc;
772 SmallVector<unsigned, 8> Registers;
773
774 struct CCOp {
775 ARMCC::CondCodes Val;
776 };
777
778 struct VCCOp {
779 ARMVCC::VPTCodes Val;
780 };
781
782 struct CopOp {
783 unsigned Val;
784 };
785
786 struct CoprocOptionOp {
787 unsigned Val;
788 };
789
790 struct ITMaskOp {
791 unsigned Mask:4;
792 };
793
794 struct MBOptOp {
795 ARM_MB::MemBOpt Val;
796 };
797
798 struct ISBOptOp {
799 ARM_ISB::InstSyncBOpt Val;
800 };
801
802 struct TSBOptOp {
803 ARM_TSB::TraceSyncBOpt Val;
804 };
805
806 struct IFlagsOp {
807 ARM_PROC::IFlags Val;
808 };
809
810 struct MMaskOp {
811 unsigned Val;
812 };
813
814 struct BankedRegOp {
815 unsigned Val;
816 };
817
818 struct TokOp {
819 const char *Data;
820 unsigned Length;
821 };
822
823 struct RegOp {
824 unsigned RegNum;
825 };
826
827 // A vector register list is a sequential list of 1 to 4 registers.
828 struct VectorListOp {
829 unsigned RegNum;
830 unsigned Count;
831 unsigned LaneIndex;
832 bool isDoubleSpaced;
833 };
834
835 struct VectorIndexOp {
836 unsigned Val;
837 };
838
839 struct ImmOp {
840 const MCExpr *Val;
841 };
842
843 /// Combined record for all forms of ARM address expressions.
844 struct MemoryOp {
845 unsigned BaseRegNum;
846 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
847 // was specified.
848 const MCExpr *OffsetImm; // Offset immediate value
849 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
850 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
851 unsigned ShiftImm; // shift for OffsetReg.
852 unsigned Alignment; // 0 = no alignment specified
853 // n = alignment in bytes (2, 4, 8, 16, or 32)
854 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
855 };
856
857 struct PostIdxRegOp {
858 unsigned RegNum;
859 bool isAdd;
860 ARM_AM::ShiftOpc ShiftTy;
861 unsigned ShiftImm;
862 };
863
864 struct ShifterImmOp {
865 bool isASR;
866 unsigned Imm;
867 };
868
869 struct RegShiftedRegOp {
870 ARM_AM::ShiftOpc ShiftTy;
871 unsigned SrcReg;
872 unsigned ShiftReg;
873 unsigned ShiftImm;
874 };
875
876 struct RegShiftedImmOp {
877 ARM_AM::ShiftOpc ShiftTy;
878 unsigned SrcReg;
879 unsigned ShiftImm;
880 };
881
882 struct RotImmOp {
883 unsigned Imm;
884 };
885
886 struct ModImmOp {
887 unsigned Bits;
888 unsigned Rot;
889 };
890
891 struct BitfieldOp {
892 unsigned LSB;
893 unsigned Width;
894 };
895
896 union {
897 struct CCOp CC;
898 struct VCCOp VCC;
899 struct CopOp Cop;
900 struct CoprocOptionOp CoprocOption;
901 struct MBOptOp MBOpt;
902 struct ISBOptOp ISBOpt;
903 struct TSBOptOp TSBOpt;
904 struct ITMaskOp ITMask;
905 struct IFlagsOp IFlags;
906 struct MMaskOp MMask;
907 struct BankedRegOp BankedReg;
908 struct TokOp Tok;
909 struct RegOp Reg;
910 struct VectorListOp VectorList;
911 struct VectorIndexOp VectorIndex;
912 struct ImmOp Imm;
913 struct MemoryOp Memory;
914 struct PostIdxRegOp PostIdxReg;
915 struct ShifterImmOp ShifterImm;
916 struct RegShiftedRegOp RegShiftedReg;
917 struct RegShiftedImmOp RegShiftedImm;
918 struct RotImmOp RotImm;
919 struct ModImmOp ModImm;
920 struct BitfieldOp Bitfield;
921 };
922
923public:
924 ARMOperand(KindTy K) : Kind(K) {}
925
926 /// getStartLoc - Get the location of the first token of this operand.
927 SMLoc getStartLoc() const override { return StartLoc; }
928
929 /// getEndLoc - Get the location of the last token of this operand.
930 SMLoc getEndLoc() const override { return EndLoc; }
931
932 /// getLocRange - Get the range between the first and last token of this
933 /// operand.
934 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
935
936 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
937 SMLoc getAlignmentLoc() const {
938 assert(Kind == k_Memory && "Invalid access!")(static_cast <bool> (Kind == k_Memory && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_Memory && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 938, __extension__
__PRETTY_FUNCTION__))
;
939 return AlignmentLoc;
940 }
941
942 ARMCC::CondCodes getCondCode() const {
943 assert(Kind == k_CondCode && "Invalid access!")(static_cast <bool> (Kind == k_CondCode && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_CondCode && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 943, __extension__
__PRETTY_FUNCTION__))
;
944 return CC.Val;
945 }
946
947 ARMVCC::VPTCodes getVPTPred() const {
948 assert(isVPTPred() && "Invalid access!")(static_cast <bool> (isVPTPred() && "Invalid access!"
) ? void (0) : __assert_fail ("isVPTPred() && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 948, __extension__
__PRETTY_FUNCTION__))
;
949 return VCC.Val;
950 }
951
952 unsigned getCoproc() const {
953 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!")(static_cast <bool> ((Kind == k_CoprocNum || Kind == k_CoprocReg
) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_CoprocNum || Kind == k_CoprocReg) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 953, __extension__
__PRETTY_FUNCTION__))
;
954 return Cop.Val;
955 }
956
957 StringRef getToken() const {
958 assert(Kind == k_Token && "Invalid access!")(static_cast <bool> (Kind == k_Token && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_Token && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 958, __extension__
__PRETTY_FUNCTION__))
;
959 return StringRef(Tok.Data, Tok.Length);
960 }
961
962 unsigned getReg() const override {
963 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!")(static_cast <bool> ((Kind == k_Register || Kind == k_CCOut
) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_Register || Kind == k_CCOut) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 963, __extension__
__PRETTY_FUNCTION__))
;
964 return Reg.RegNum;
965 }
966
967 const SmallVectorImpl<unsigned> &getRegList() const {
968 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||(static_cast <bool> ((Kind == k_RegisterList || Kind ==
k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind ==
k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind
== k_FPDRegisterListWithVPR) && "Invalid access!") ?
void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 972, __extension__
__PRETTY_FUNCTION__))
969 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||(static_cast <bool> ((Kind == k_RegisterList || Kind ==
k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind ==
k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind
== k_FPDRegisterListWithVPR) && "Invalid access!") ?
void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 972, __extension__
__PRETTY_FUNCTION__))
970 Kind == k_FPSRegisterListWithVPR ||(static_cast <bool> ((Kind == k_RegisterList || Kind ==
k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind ==
k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind
== k_FPDRegisterListWithVPR) && "Invalid access!") ?
void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 972, __extension__
__PRETTY_FUNCTION__))
971 Kind == k_FPDRegisterListWithVPR) &&(static_cast <bool> ((Kind == k_RegisterList || Kind ==
k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind ==
k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind
== k_FPDRegisterListWithVPR) && "Invalid access!") ?
void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 972, __extension__
__PRETTY_FUNCTION__))
972 "Invalid access!")(static_cast <bool> ((Kind == k_RegisterList || Kind ==
k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind ==
k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind
== k_FPDRegisterListWithVPR) && "Invalid access!") ?
void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 972, __extension__
__PRETTY_FUNCTION__))
;
973 return Registers;
974 }
975
976 const MCExpr *getImm() const {
977 assert(isImm() && "Invalid access!")(static_cast <bool> (isImm() && "Invalid access!"
) ? void (0) : __assert_fail ("isImm() && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 977, __extension__
__PRETTY_FUNCTION__))
;
978 return Imm.Val;
979 }
980
981 const MCExpr *getConstantPoolImm() const {
982 assert(isConstantPoolImm() && "Invalid access!")(static_cast <bool> (isConstantPoolImm() && "Invalid access!"
) ? void (0) : __assert_fail ("isConstantPoolImm() && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 982, __extension__
__PRETTY_FUNCTION__))
;
983 return Imm.Val;
984 }
985
986 unsigned getVectorIndex() const {
987 assert(Kind == k_VectorIndex && "Invalid access!")(static_cast <bool> (Kind == k_VectorIndex && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_VectorIndex && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 987, __extension__
__PRETTY_FUNCTION__))
;
988 return VectorIndex.Val;
989 }
990
991 ARM_MB::MemBOpt getMemBarrierOpt() const {
992 assert(Kind == k_MemBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_MemBarrierOpt &&
"Invalid access!") ? void (0) : __assert_fail ("Kind == k_MemBarrierOpt && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 992, __extension__
__PRETTY_FUNCTION__))
;
993 return MBOpt.Val;
994 }
995
996 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
997 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_InstSyncBarrierOpt &&
"Invalid access!") ? void (0) : __assert_fail ("Kind == k_InstSyncBarrierOpt && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 997, __extension__
__PRETTY_FUNCTION__))
;
998 return ISBOpt.Val;
999 }
1000
1001 ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
1002 assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_TraceSyncBarrierOpt &&
"Invalid access!") ? void (0) : __assert_fail ("Kind == k_TraceSyncBarrierOpt && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1002, __extension__
__PRETTY_FUNCTION__))
;
1003 return TSBOpt.Val;
1004 }
1005
1006 ARM_PROC::IFlags getProcIFlags() const {
1007 assert(Kind == k_ProcIFlags && "Invalid access!")(static_cast <bool> (Kind == k_ProcIFlags && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_ProcIFlags && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1007, __extension__
__PRETTY_FUNCTION__))
;
1008 return IFlags.Val;
1009 }
1010
1011 unsigned getMSRMask() const {
1012 assert(Kind == k_MSRMask && "Invalid access!")(static_cast <bool> (Kind == k_MSRMask && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_MSRMask && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1012, __extension__
__PRETTY_FUNCTION__))
;
1013 return MMask.Val;
1014 }
1015
1016 unsigned getBankedReg() const {
1017 assert(Kind == k_BankedReg && "Invalid access!")(static_cast <bool> (Kind == k_BankedReg && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_BankedReg && \"Invalid access!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1017, __extension__
__PRETTY_FUNCTION__))
;
1018 return BankedReg.Val;
1019 }
1020
1021 bool isCoprocNum() const { return Kind == k_CoprocNum; }
1022 bool isCoprocReg() const { return Kind == k_CoprocReg; }
1023 bool isCoprocOption() const { return Kind == k_CoprocOption; }
1024 bool isCondCode() const { return Kind == k_CondCode; }
1025 bool isVPTPred() const { return Kind == k_VPTPred; }
1026 bool isCCOut() const { return Kind == k_CCOut; }
1027 bool isITMask() const { return Kind == k_ITCondMask; }
1028 bool isITCondCode() const { return Kind == k_CondCode; }
1029 bool isImm() const override {
1030 return Kind == k_Immediate;
1031 }
1032
1033 bool isARMBranchTarget() const {
1034 if (!isImm()) return false;
1035
1036 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1037 return CE->getValue() % 4 == 0;
1038 return true;
1039 }
1040
1041
1042 bool isThumbBranchTarget() const {
1043 if (!isImm()) return false;
1044
1045 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1046 return CE->getValue() % 2 == 0;
1047 return true;
1048 }
1049
1050 // checks whether this operand is an unsigned offset which fits is a field
1051 // of specified width and scaled by a specific number of bits
1052 template<unsigned width, unsigned scale>
1053 bool isUnsignedOffset() const {
1054 if (!isImm()) return false;
1055 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1056 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1057 int64_t Val = CE->getValue();
1058 int64_t Align = 1LL << scale;
1059 int64_t Max = Align * ((1LL << width) - 1);
1060 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
1061 }
1062 return false;
1063 }
1064
1065 // checks whether this operand is an signed offset which fits is a field
1066 // of specified width and scaled by a specific number of bits
1067 template<unsigned width, unsigned scale>
1068 bool isSignedOffset() const {
1069 if (!isImm()) return false;
1070 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1071 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1072 int64_t Val = CE->getValue();
1073 int64_t Align = 1LL << scale;
1074 int64_t Max = Align * ((1LL << (width-1)) - 1);
1075 int64_t Min = -Align * (1LL << (width-1));
1076 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1077 }
1078 return false;
1079 }
1080
1081 // checks whether this operand is an offset suitable for the LE /
1082 // LETP instructions in Arm v8.1M
1083 bool isLEOffset() const {
1084 if (!isImm()) return false;
1085 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1086 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1087 int64_t Val = CE->getValue();
1088 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1089 }
1090 return false;
1091 }
1092
1093 // checks whether this operand is a memory operand computed as an offset
1094 // applied to PC. the offset may have 8 bits of magnitude and is represented
1095 // with two bits of shift. textually it may be either [pc, #imm], #imm or
1096 // relocable expression...
1097 bool isThumbMemPC() const {
1098 int64_t Val = 0;
1099 if (isImm()) {
1100 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1101 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1102 if (!CE) return false;
1103 Val = CE->getValue();
1104 }
1105 else if (isGPRMem()) {
1106 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1107 if(Memory.BaseRegNum != ARM::PC) return false;
1108 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
1109 Val = CE->getValue();
1110 else
1111 return false;
1112 }
1113 else return false;
1114 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1115 }
1116
1117 bool isFPImm() const {
1118 if (!isImm()) return false;
1119 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1120 if (!CE) return false;
1121 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1122 return Val != -1;
1123 }
1124
1125 template<int64_t N, int64_t M>
1126 bool isImmediate() const {
1127 if (!isImm()) return false;
1128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1129 if (!CE) return false;
1130 int64_t Value = CE->getValue();
1131 return Value >= N && Value <= M;
1132 }
1133
1134 template<int64_t N, int64_t M>
1135 bool isImmediateS4() const {
1136 if (!isImm()) return false;
1137 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1138 if (!CE) return false;
1139 int64_t Value = CE->getValue();
1140 return ((Value & 3) == 0) && Value >= N && Value <= M;
1141 }
1142 template<int64_t N, int64_t M>
1143 bool isImmediateS2() const {
1144 if (!isImm()) return false;
1145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1146 if (!CE) return false;
1147 int64_t Value = CE->getValue();
1148 return ((Value & 1) == 0) && Value >= N && Value <= M;
1149 }
1150 bool isFBits16() const {
1151 return isImmediate<0, 17>();
1152 }
1153 bool isFBits32() const {
1154 return isImmediate<1, 33>();
1155 }
1156 bool isImm8s4() const {
1157 return isImmediateS4<-1020, 1020>();
1158 }
1159 bool isImm7s4() const {
1160 return isImmediateS4<-508, 508>();
1161 }
1162 bool isImm7Shift0() const {
1163 return isImmediate<-127, 127>();
1164 }
1165 bool isImm7Shift1() const {
1166 return isImmediateS2<-255, 255>();
1167 }
1168 bool isImm7Shift2() const {
1169 return isImmediateS4<-511, 511>();
1170 }
1171 bool isImm7() const {
1172 return isImmediate<-127, 127>();
1173 }
1174 bool isImm0_1020s4() const {
1175 return isImmediateS4<0, 1020>();
1176 }
1177 bool isImm0_508s4() const {
1178 return isImmediateS4<0, 508>();
1179 }
1180 bool isImm0_508s4Neg() const {
1181 if (!isImm()) return false;
1182 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1183 if (!CE) return false;
1184 int64_t Value = -CE->getValue();
1185 // explicitly exclude zero. we want that to use the normal 0_508 version.
1186 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1187 }
1188
1189 bool isImm0_4095Neg() const {
1190 if (!isImm()) return false;
1191 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1192 if (!CE) return false;
1193 // isImm0_4095Neg is used with 32-bit immediates only.
1194 // 32-bit immediates are zero extended to 64-bit when parsed,
1195 // thus simple -CE->getValue() results in a big negative number,
1196 // not a small positive number as intended
1197 if ((CE->getValue() >> 32) > 0) return false;
1198 uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1199 return Value > 0 && Value < 4096;
1200 }
1201
1202 bool isImm0_7() const {
1203 return isImmediate<0, 7>();
1204 }
1205
1206 bool isImm1_16() const {
1207 return isImmediate<1, 16>();
1208 }
1209
1210 bool isImm1_32() const {
1211 return isImmediate<1, 32>();
1212 }
1213
1214 bool isImm8_255() const {
1215 return isImmediate<8, 255>();
1216 }
1217
1218 bool isImm256_65535Expr() const {
1219 if (!isImm()) return false;
1220 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1221 // If it's not a constant expression, it'll generate a fixup and be
1222 // handled later.
1223 if (!CE) return true;
1224 int64_t Value = CE->getValue();
1225 return Value >= 256 && Value < 65536;
1226 }
1227
1228 bool isImm0_65535Expr() const {
1229 if (!isImm()) return false;
1230 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1231 // If it's not a constant expression, it'll generate a fixup and be
1232 // handled later.
1233 if (!CE) return true;
1234 int64_t Value = CE->getValue();
1235 return Value >= 0 && Value < 65536;
1236 }
1237
1238 bool isImm24bit() const {
1239 return isImmediate<0, 0xffffff + 1>();
1240 }
1241
1242 bool isImmThumbSR() const {
1243 return isImmediate<1, 33>();
1244 }
1245
1246 template<int shift>
1247 bool isExpImmValue(uint64_t Value) const {
1248 uint64_t mask = (1 << shift) - 1;
1249 if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1250 return false;
1251 return true;
1252 }
1253
1254 template<int shift>
1255 bool isExpImm() const {
1256 if (!isImm()) return false;
1257 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1258 if (!CE) return false;
1259
1260 return isExpImmValue<shift>(CE->getValue());
1261 }
1262
1263 template<int shift, int size>
1264 bool isInvertedExpImm() const {
1265 if (!isImm()) return false;
1266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1267 if (!CE) return false;
1268
1269 uint64_t OriginalValue = CE->getValue();
1270 uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1271 return isExpImmValue<shift>(InvertedValue);
1272 }
1273
1274 bool isPKHLSLImm() const {
1275 return isImmediate<0, 32>();
1276 }
1277
1278 bool isPKHASRImm() const {
1279 return isImmediate<0, 33>();
1280 }
1281
1282 bool isAdrLabel() const {
1283 // If we have an immediate that's not a constant, treat it as a label
1284 // reference needing a fixup.
1285 if (isImm() && !isa<MCConstantExpr>(getImm()))
1286 return true;
1287
1288 // If it is a constant, it must fit into a modified immediate encoding.
1289 if (!isImm()) return false;
1290 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1291 if (!CE) return false;
1292 int64_t Value = CE->getValue();
1293 return (ARM_AM::getSOImmVal(Value) != -1 ||
1294 ARM_AM::getSOImmVal(-Value) != -1);
1295 }
1296
1297 bool isT2SOImm() const {
1298 // If we have an immediate that's not a constant, treat it as an expression
1299 // needing a fixup.
1300 if (isImm() && !isa<MCConstantExpr>(getImm())) {
1301 // We want to avoid matching :upper16: and :lower16: as we want these
1302 // expressions to match in isImm0_65535Expr()
1303 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1304 return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1305 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1306 }
1307 if (!isImm()) return false;
1308 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1309 if (!CE) return false;
1310 int64_t Value = CE->getValue();
1311 return ARM_AM::getT2SOImmVal(Value) != -1;
1312 }
1313
1314 bool isT2SOImmNot() const {
1315 if (!isImm()) return false;
1316 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1317 if (!CE) return false;
1318 int64_t Value = CE->getValue();
1319 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1320 ARM_AM::getT2SOImmVal(~Value) != -1;
1321 }
1322
1323 bool isT2SOImmNeg() const {
1324 if (!isImm()) return false;
1325 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1326 if (!CE) return false;
1327 int64_t Value = CE->getValue();
1328 // Only use this when not representable as a plain so_imm.
1329 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1330 ARM_AM::getT2SOImmVal(-Value) != -1;
1331 }
1332
1333 bool isSetEndImm() const {
1334 if (!isImm()) return false;
1335 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1336 if (!CE) return false;
1337 int64_t Value = CE->getValue();
1338 return Value == 1 || Value == 0;
1339 }
1340
1341 bool isReg() const override { return Kind == k_Register; }
1342 bool isRegList() const { return Kind == k_RegisterList; }
1343 bool isRegListWithAPSR() const {
1344 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1345 }
1346 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1347 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1348 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1349 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1350 bool isToken() const override { return Kind == k_Token; }
1351 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1352 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1353 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1354 bool isMem() const override {
1355 return isGPRMem() || isMVEMem();
1356 }
1357 bool isMVEMem() const {
1358 if (Kind != k_Memory)
1359 return false;
1360 if (Memory.BaseRegNum &&
1361 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1362 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1363 return false;
1364 if (Memory.OffsetRegNum &&
1365 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1366 Memory.OffsetRegNum))
1367 return false;
1368 return true;
1369 }
1370 bool isGPRMem() const {
1371 if (Kind != k_Memory)
1372 return false;
1373 if (Memory.BaseRegNum &&
1374 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1375 return false;
1376 if (Memory.OffsetRegNum &&
1377 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1378 return false;
1379 return true;
1380 }
1381 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1382 bool isRegShiftedReg() const {
1383 return Kind == k_ShiftedRegister &&
1384 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1385 RegShiftedReg.SrcReg) &&
1386 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1387 RegShiftedReg.ShiftReg);
1388 }
1389 bool isRegShiftedImm() const {
1390 return Kind == k_ShiftedImmediate &&
1391 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1392 RegShiftedImm.SrcReg);
1393 }
1394 bool isRotImm() const { return Kind == k_RotateImmediate; }
1395
1396 template<unsigned Min, unsigned Max>
1397 bool isPowerTwoInRange() const {
1398 if (!isImm()) return false;
1399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1400 if (!CE) return false;
1401 int64_t Value = CE->getValue();
1402 return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1403 Value >= Min && Value <= Max;
1404 }
1405 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1406
1407 bool isModImmNot() const {
1408 if (!isImm()) return false;
1409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1410 if (!CE) return false;
1411 int64_t Value = CE->getValue();
1412 return ARM_AM::getSOImmVal(~Value) != -1;
1413 }
1414
1415 bool isModImmNeg() const {
1416 if (!isImm()) return false;
1417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1418 if (!CE) return false;
1419 int64_t Value = CE->getValue();
1420 return ARM_AM::getSOImmVal(Value) == -1 &&
1421 ARM_AM::getSOImmVal(-Value) != -1;
1422 }
1423
1424 bool isThumbModImmNeg1_7() const {
1425 if (!isImm()) return false;
1426 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1427 if (!CE) return false;
1428 int32_t Value = -(int32_t)CE->getValue();
1429 return 0 < Value && Value < 8;
1430 }
1431
1432 bool isThumbModImmNeg8_255() const {
1433 if (!isImm()) return false;
1434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1435 if (!CE) return false;
1436 int32_t Value = -(int32_t)CE->getValue();
1437 return 7 < Value && Value < 256;
1438 }
1439
1440 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1441 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1442 bool isPostIdxRegShifted() const {
1443 return Kind == k_PostIndexRegister &&
1444 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1445 }
1446 bool isPostIdxReg() const {
1447 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1448 }
1449 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1450 if (!isGPRMem())
1451 return false;
1452 // No offset of any kind.
1453 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1454 (alignOK || Memory.Alignment == Alignment);
1455 }
1456 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1457 if (!isGPRMem())
1458 return false;
1459
1460 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1461 Memory.BaseRegNum))
1462 return false;
1463
1464 // No offset of any kind.
1465 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1466 (alignOK || Memory.Alignment == Alignment);
1467 }
1468 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1469 if (!isGPRMem())
1470 return false;
1471
1472 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1473 Memory.BaseRegNum))
1474 return false;
1475
1476 // No offset of any kind.
1477 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1478 (alignOK || Memory.Alignment == Alignment);
1479 }
1480 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1481 if (!isGPRMem())
1482 return false;
1483
1484 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1485 Memory.BaseRegNum))
1486 return false;
1487
1488 // No offset of any kind.
1489 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1490 (alignOK || Memory.Alignment == Alignment);
1491 }
1492 bool isMemPCRelImm12() const {
1493 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1494 return false;
1495 // Base register must be PC.
1496 if (Memory.BaseRegNum != ARM::PC)
1497 return false;
1498 // Immediate offset in range [-4095, 4095].
1499 if (!Memory.OffsetImm) return true;
1500 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1501 int64_t Val = CE->getValue();
1502 return (Val > -4096 && Val < 4096) ||
1503 (Val == std::numeric_limits<int32_t>::min());
1504 }
1505 return false;
1506 }
1507
1508 bool isAlignedMemory() const {
1509 return isMemNoOffset(true);
1510 }
1511
1512 bool isAlignedMemoryNone() const {
1513 return isMemNoOffset(false, 0);
1514 }
1515
1516 bool isDupAlignedMemoryNone() const {
1517 return isMemNoOffset(false, 0);
1518 }
1519
1520 bool isAlignedMemory16() const {
1521 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1522 return true;
1523 return isMemNoOffset(false, 0);
1524 }
1525
1526 bool isDupAlignedMemory16() const {
1527 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1528 return true;
1529 return isMemNoOffset(false, 0);
1530 }
1531
1532 bool isAlignedMemory32() const {
1533 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1534 return true;
1535 return isMemNoOffset(false, 0);
1536 }
1537
1538 bool isDupAlignedMemory32() const {
1539 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1540 return true;
1541 return isMemNoOffset(false, 0);
1542 }
1543
1544 bool isAlignedMemory64() const {
1545 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1546 return true;
1547 return isMemNoOffset(false, 0);
1548 }
1549
1550 bool isDupAlignedMemory64() const {
1551 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1552 return true;
1553 return isMemNoOffset(false, 0);
1554 }
1555
1556 bool isAlignedMemory64or128() const {
1557 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1558 return true;
1559 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1560 return true;
1561 return isMemNoOffset(false, 0);
1562 }
1563
1564 bool isDupAlignedMemory64or128() const {
1565 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1566 return true;
1567 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1568 return true;
1569 return isMemNoOffset(false, 0);
1570 }
1571
1572 bool isAlignedMemory64or128or256() const {
1573 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1574 return true;
1575 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1576 return true;
1577 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1578 return true;
1579 return isMemNoOffset(false, 0);
1580 }
1581
1582 bool isAddrMode2() const {
1583 if (!isGPRMem() || Memory.Alignment != 0) return false;
1584 // Check for register offset.
1585 if (Memory.OffsetRegNum) return true;
1586 // Immediate offset in range [-4095, 4095].
1587 if (!Memory.OffsetImm) return true;
1588 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1589 int64_t Val = CE->getValue();
1590 return Val > -4096 && Val < 4096;
1591 }
1592 return false;
1593 }
1594
1595 bool isAM2OffsetImm() const {
1596 if (!isImm()) return false;
1597 // Immediate offset in range [-4095, 4095].
1598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1599 if (!CE) return false;
1600 int64_t Val = CE->getValue();
1601 return (Val == std::numeric_limits<int32_t>::min()) ||
1602 (Val > -4096 && Val < 4096);
1603 }
1604
1605 bool isAddrMode3() const {
1606 // If we have an immediate that's not a constant, treat it as a label
1607 // reference needing a fixup. If it is a constant, it's something else
1608 // and we reject it.
1609 if (isImm() && !isa<MCConstantExpr>(getImm()))
1610 return true;
1611 if (!isGPRMem() || Memory.Alignment != 0) return false;
1612 // No shifts are legal for AM3.
1613 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1614 // Check for register offset.
1615 if (Memory.OffsetRegNum) return true;
1616 // Immediate offset in range [-255, 255].
1617 if (!Memory.OffsetImm) return true;
1618 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1619 int64_t Val = CE->getValue();
1620 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
1621 // we have to check for this too.
1622 return (Val > -256 && Val < 256) ||
1623 Val == std::numeric_limits<int32_t>::min();
1624 }
1625 return false;
1626 }
1627
1628 bool isAM3Offset() const {
1629 if (isPostIdxReg())
1630 return true;
1631 if (!isImm())
1632 return false;
1633 // Immediate offset in range [-255, 255].
1634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1635 if (!CE) return false;
1636 int64_t Val = CE->getValue();
1637 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1638 return (Val > -256 && Val < 256) ||
1639 Val == std::numeric_limits<int32_t>::min();
1640 }
1641
1642 bool isAddrMode5() const {
1643 // If we have an immediate that's not a constant, treat it as a label
1644 // reference needing a fixup. If it is a constant, it's something else
1645 // and we reject it.
1646 if (isImm() && !isa<MCConstantExpr>(getImm()))
1647 return true;
1648 if (!isGPRMem() || Memory.Alignment != 0) return false;
1649 // Check for register offset.
1650 if (Memory.OffsetRegNum) return false;
1651 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1652 if (!Memory.OffsetImm) return true;
1653 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1654 int64_t Val = CE->getValue();
1655 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1656 Val == std::numeric_limits<int32_t>::min();
1657 }
1658 return false;
1659 }
1660
1661 bool isAddrMode5FP16() const {
1662 // If we have an immediate that's not a constant, treat it as a label
1663 // reference needing a fixup. If it is a constant, it's something else
1664 // and we reject it.
1665 if (isImm() && !isa<MCConstantExpr>(getImm()))
1666 return true;
1667 if (!isGPRMem() || Memory.Alignment != 0) return false;
1668 // Check for register offset.
1669 if (Memory.OffsetRegNum) return false;
1670 // Immediate offset in range [-510, 510] and a multiple of 2.
1671 if (!Memory.OffsetImm) return true;
1672 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1673 int64_t Val = CE->getValue();
1674 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1675 Val == std::numeric_limits<int32_t>::min();
1676 }
1677 return false;
1678 }
1679
1680 bool isMemTBB() const {
1681 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1682 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1683 return false;
1684 return true;
1685 }
1686
1687 bool isMemTBH() const {
1688 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1689 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1690 Memory.Alignment != 0 )
1691 return false;
1692 return true;
1693 }
1694
1695 bool isMemRegOffset() const {
1696 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1697 return false;
1698 return true;
1699 }
1700
1701 bool isT2MemRegOffset() const {
1702 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1703 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1704 return false;
1705 // Only lsl #{0, 1, 2, 3} allowed.
1706 if (Memory.ShiftType == ARM_AM::no_shift)
1707 return true;
1708 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1709 return false;
1710 return true;
1711 }
1712
1713 bool isMemThumbRR() const {
1714 // Thumb reg+reg addressing is simple. Just two registers, a base and
1715 // an offset. No shifts, negations or any other complicating factors.
1716 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1717 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1718 return false;
1719 return isARMLowRegister(Memory.BaseRegNum) &&
1720 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1721 }
1722
1723 bool isMemThumbRIs4() const {
1724 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1725 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1726 return false;
1727 // Immediate offset, multiple of 4 in range [0, 124].
1728 if (!Memory.OffsetImm) return true;
1729 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1730 int64_t Val = CE->getValue();
1731 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1732 }
1733 return false;
1734 }
1735
1736 bool isMemThumbRIs2() const {
1737 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1738 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1739 return false;
1740 // Immediate offset, multiple of 4 in range [0, 62].
1741 if (!Memory.OffsetImm) return true;
1742 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1743 int64_t Val = CE->getValue();
1744 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1745 }
1746 return false;
1747 }
1748
1749 bool isMemThumbRIs1() const {
1750 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1751 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1752 return false;
1753 // Immediate offset in range [0, 31].
1754 if (!Memory.OffsetImm) return true;
1755 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1756 int64_t Val = CE->getValue();
1757 return Val >= 0 && Val <= 31;
1758 }
1759 return false;
1760 }
1761
1762 bool isMemThumbSPI() const {
1763 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1764 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1765 return false;
1766 // Immediate offset, multiple of 4 in range [0, 1020].
1767 if (!Memory.OffsetImm) return true;
1768 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1769 int64_t Val = CE->getValue();
1770 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1771 }
1772 return false;
1773 }
1774
1775 bool isMemImm8s4Offset() const {
1776 // If we have an immediate that's not a constant, treat it as a label
1777 // reference needing a fixup. If it is a constant, it's something else
1778 // and we reject it.
1779 if (isImm() && !isa<MCConstantExpr>(getImm()))
1780 return true;
1781 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1782 return false;
1783 // Immediate offset a multiple of 4 in range [-1020, 1020].
1784 if (!Memory.OffsetImm) return true;
1785 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1786 int64_t Val = CE->getValue();
1787 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1788 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1789 Val == std::numeric_limits<int32_t>::min();
1790 }
1791 return false;
1792 }
1793
1794 bool isMemImm7s4Offset() const {
1795 // If we have an immediate that's not a constant, treat it as a label
1796 // reference needing a fixup. If it is a constant, it's something else
1797 // and we reject it.
1798 if (isImm() && !isa<MCConstantExpr>(getImm()))
1799 return true;
1800 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1801 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1802 Memory.BaseRegNum))
1803 return false;
1804 // Immediate offset a multiple of 4 in range [-508, 508].
1805 if (!Memory.OffsetImm) return true;
1806 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1807 int64_t Val = CE->getValue();
1808 // Special case, #-0 is INT32_MIN.
1809 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN(-2147483647-1);
1810 }
1811 return false;
1812 }
1813
1814 bool isMemImm0_1020s4Offset() const {
1815 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1816 return false;
1817 // Immediate offset a multiple of 4 in range [0, 1020].
1818 if (!Memory.OffsetImm) return true;
1819 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1820 int64_t Val = CE->getValue();
1821 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1822 }
1823 return false;
1824 }
1825
1826 bool isMemImm8Offset() const {
1827 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1828 return false;
1829 // Base reg of PC isn't allowed for these encodings.
1830 if (Memory.BaseRegNum == ARM::PC) return false;
1831 // Immediate offset in range [-255, 255].
1832 if (!Memory.OffsetImm) return true;
1833 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1834 int64_t Val = CE->getValue();
1835 return (Val == std::numeric_limits<int32_t>::min()) ||
1836 (Val > -256 && Val < 256);
1837 }
1838 return false;
1839 }
1840
1841 template<unsigned Bits, unsigned RegClassID>
1842 bool isMemImm7ShiftedOffset() const {
1843 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1844 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1845 return false;
1846
1847 // Expect an immediate offset equal to an element of the range
1848 // [-127, 127], shifted left by Bits.
1849
1850 if (!Memory.OffsetImm) return true;
1851 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1852 int64_t Val = CE->getValue();
1853
1854 // INT32_MIN is a special-case value (indicating the encoding with
1855 // zero offset and the subtract bit set)
1856 if (Val == INT32_MIN(-2147483647-1))
1857 return true;
1858
1859 unsigned Divisor = 1U << Bits;
1860
1861 // Check that the low bits are zero
1862 if (Val % Divisor != 0)
1863 return false;
1864
1865 // Check that the remaining offset is within range.
1866 Val /= Divisor;
1867 return (Val >= -127 && Val <= 127);
1868 }
1869 return false;
1870 }
1871
1872 template <int shift> bool isMemRegRQOffset() const {
1873 if (!isMVEMem() || Memory.OffsetImm != nullptr || Memory.Alignment != 0)
1874 return false;
1875
1876 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1877 Memory.BaseRegNum))
1878 return false;
1879 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1880 Memory.OffsetRegNum))
1881 return false;
1882
1883 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1884 return false;
1885
1886 if (shift > 0 &&
1887 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1888 return false;
1889
1890 return true;
1891 }
1892
1893 template <int shift> bool isMemRegQOffset() const {
1894 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1895 return false;
1896
1897 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1898 Memory.BaseRegNum))
1899 return false;
1900
1901 if (!Memory.OffsetImm)
1902 return true;
1903 static_assert(shift < 56,
1904 "Such that we dont shift by a value higher than 62");
1905 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1906 int64_t Val = CE->getValue();
1907
1908 // The value must be a multiple of (1 << shift)
1909 if ((Val & ((1U << shift) - 1)) != 0)
1910 return false;
1911
1912 // And be in the right range, depending on the amount that it is shifted
1913 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1914 // separately.
1915 int64_t Range = (1U << (7 + shift)) - 1;
1916 return (Val == INT32_MIN(-2147483647-1)) || (Val > -Range && Val < Range);
1917 }
1918 return false;
1919 }
1920
1921 bool isMemPosImm8Offset() const {
1922 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1923 return false;
1924 // Immediate offset in range [0, 255].
1925 if (!Memory.OffsetImm) return true;
1926 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1927 int64_t Val = CE->getValue();
1928 return Val >= 0 && Val < 256;
1929 }
1930 return false;
1931 }
1932
1933 bool isMemNegImm8Offset() const {
1934 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1935 return false;
1936 // Base reg of PC isn't allowed for these encodings.
1937 if (Memory.BaseRegNum == ARM::PC) return false;
1938 // Immediate offset in range [-255, -1].
1939 if (!Memory.OffsetImm) return false;
1940 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1941 int64_t Val = CE->getValue();
1942 return (Val == std::numeric_limits<int32_t>::min()) ||
1943 (Val > -256 && Val < 0);
1944 }
1945 return false;
1946 }
1947
1948 bool isMemUImm12Offset() const {
1949 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1950 return false;
1951 // Immediate offset in range [0, 4095].
1952 if (!Memory.OffsetImm) return true;
1953 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1954 int64_t Val = CE->getValue();
1955 return (Val >= 0 && Val < 4096);
1956 }
1957 return false;
1958 }
1959
1960 bool isMemImm12Offset() const {
1961 // If we have an immediate that's not a constant, treat it as a label
1962 // reference needing a fixup. If it is a constant, it's something else
1963 // and we reject it.
1964
1965 if (isImm() && !isa<MCConstantExpr>(getImm()))
1966 return true;
1967
1968 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1969 return false;
1970 // Immediate offset in range [-4095, 4095].
1971 if (!Memory.OffsetImm) return true;
1972 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1973 int64_t Val = CE->getValue();
1974 return (Val > -4096 && Val < 4096) ||
1975 (Val == std::numeric_limits<int32_t>::min());
1976 }
1977 // If we have an immediate that's not a constant, treat it as a
1978 // symbolic expression needing a fixup.
1979 return true;
1980 }
1981
1982 bool isConstPoolAsmImm() const {
1983 // Delay processing of Constant Pool Immediate, this will turn into
1984 // a constant. Match no other operand
1985 return (isConstantPoolImm());
1986 }
1987
1988 bool isPostIdxImm8() const {
1989 if (!isImm()) return false;
1990 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1991 if (!CE) return false;
1992 int64_t Val = CE->getValue();
1993 return (Val > -256 && Val < 256) ||
1994 (Val == std::numeric_limits<int32_t>::min());
1995 }
1996
1997 bool isPostIdxImm8s4() const {
1998 if (!isImm()) return false;
1999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2000 if (!CE) return false;
2001 int64_t Val = CE->getValue();
2002 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
2003 (Val == std::numeric_limits<int32_t>::min());
2004 }
2005
2006 bool isMSRMask() const { return Kind == k_MSRMask; }
2007 bool isBankedReg() const { return Kind == k_BankedReg; }
2008 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
2009
2010 // NEON operands.
2011 bool isSingleSpacedVectorList() const {
2012 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
2013 }
2014
2015 bool isDoubleSpacedVectorList() const {
2016 return Kind == k_VectorList && VectorList.isDoubleSpaced;
2017 }
2018
2019 bool isVecListOneD() const {
2020 if (!isSingleSpacedVectorList()) return false;
2021 return VectorList.Count == 1;
2022 }
2023
2024 bool isVecListTwoMQ() const {
2025 return isSingleSpacedVectorList() && VectorList.Count == 2 &&
2026 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2027 VectorList.RegNum);
2028 }
2029
2030 bool isVecListDPair() const {
2031 if (!isSingleSpacedVectorList()) return false;
2032 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2033 .contains(VectorList.RegNum));
2034 }
2035
2036 bool isVecListThreeD() const {
2037 if (!isSingleSpacedVectorList()) return false;
2038 return VectorList.Count == 3;
2039 }
2040
2041 bool isVecListFourD() const {
2042 if (!isSingleSpacedVectorList()) return false;
2043 return VectorList.Count == 4;
2044 }
2045
2046 bool isVecListDPairSpaced() const {
2047 if (Kind != k_VectorList) return false;
2048 if (isSingleSpacedVectorList()) return false;
2049 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
2050 .contains(VectorList.RegNum));
2051 }
2052
2053 bool isVecListThreeQ() const {
2054 if (!isDoubleSpacedVectorList()) return false;
2055 return VectorList.Count == 3;
2056 }
2057
2058 bool isVecListFourQ() const {
2059 if (!isDoubleSpacedVectorList()) return false;
2060 return VectorList.Count == 4;
2061 }
2062
2063 bool isVecListFourMQ() const {
2064 return isSingleSpacedVectorList() && VectorList.Count == 4 &&
2065 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2066 VectorList.RegNum);
2067 }
2068
2069 bool isSingleSpacedVectorAllLanes() const {
2070 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
2071 }
2072
2073 bool isDoubleSpacedVectorAllLanes() const {
2074 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
2075 }
2076
2077 bool isVecListOneDAllLanes() const {
2078 if (!isSingleSpacedVectorAllLanes()) return false;
2079 return VectorList.Count == 1;
2080 }
2081
2082 bool isVecListDPairAllLanes() const {
2083 if (!isSingleSpacedVectorAllLanes()) return false;
2084 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2085 .contains(VectorList.RegNum));
2086 }
2087
2088 bool isVecListDPairSpacedAllLanes() const {
2089 if (!isDoubleSpacedVectorAllLanes()) return false;
2090 return VectorList.Count == 2;
2091 }
2092
2093 bool isVecListThreeDAllLanes() const {
2094 if (!isSingleSpacedVectorAllLanes()) return false;
2095 return VectorList.Count == 3;
2096 }
2097
2098 bool isVecListThreeQAllLanes() const {
2099 if (!isDoubleSpacedVectorAllLanes()) return false;
2100 return VectorList.Count == 3;
2101 }
2102
2103 bool isVecListFourDAllLanes() const {
2104 if (!isSingleSpacedVectorAllLanes()) return false;
2105 return VectorList.Count == 4;
2106 }
2107
2108 bool isVecListFourQAllLanes() const {
2109 if (!isDoubleSpacedVectorAllLanes()) return false;
2110 return VectorList.Count == 4;
2111 }
2112
2113 bool isSingleSpacedVectorIndexed() const {
2114 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
2115 }
2116
2117 bool isDoubleSpacedVectorIndexed() const {
2118 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
2119 }
2120
2121 bool isVecListOneDByteIndexed() const {
2122 if (!isSingleSpacedVectorIndexed()) return false;
2123 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
2124 }
2125
2126 bool isVecListOneDHWordIndexed() const {
2127 if (!isSingleSpacedVectorIndexed()) return false;
2128 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2129 }
2130
2131 bool isVecListOneDWordIndexed() const {
2132 if (!isSingleSpacedVectorIndexed()) return false;
2133 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2134 }
2135
2136 bool isVecListTwoDByteIndexed() const {
2137 if (!isSingleSpacedVectorIndexed()) return false;
2138 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2139 }
2140
2141 bool isVecListTwoDHWordIndexed() const {
2142 if (!isSingleSpacedVectorIndexed()) return false;
2143 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2144 }
2145
2146 bool isVecListTwoQWordIndexed() const {
2147 if (!isDoubleSpacedVectorIndexed()) return false;
2148 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2149 }
2150
2151 bool isVecListTwoQHWordIndexed() const {
2152 if (!isDoubleSpacedVectorIndexed()) return false;
2153 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2154 }
2155
2156 bool isVecListTwoDWordIndexed() const {
2157 if (!isSingleSpacedVectorIndexed()) return false;
2158 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2159 }
2160
2161 bool isVecListThreeDByteIndexed() const {
2162 if (!isSingleSpacedVectorIndexed()) return false;
2163 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2164 }
2165
2166 bool isVecListThreeDHWordIndexed() const {
2167 if (!isSingleSpacedVectorIndexed()) return false;
2168 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2169 }
2170
2171 bool isVecListThreeQWordIndexed() const {
2172 if (!isDoubleSpacedVectorIndexed()) return false;
2173 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2174 }
2175
2176 bool isVecListThreeQHWordIndexed() const {
2177 if (!isDoubleSpacedVectorIndexed()) return false;
2178 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2179 }
2180
2181 bool isVecListThreeDWordIndexed() const {
2182 if (!isSingleSpacedVectorIndexed()) return false;
2183 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2184 }
2185
2186 bool isVecListFourDByteIndexed() const {
2187 if (!isSingleSpacedVectorIndexed()) return false;
2188 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2189 }
2190
2191 bool isVecListFourDHWordIndexed() const {
2192 if (!isSingleSpacedVectorIndexed()) return false;
2193 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2194 }
2195
2196 bool isVecListFourQWordIndexed() const {
2197 if (!isDoubleSpacedVectorIndexed()) return false;
2198 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2199 }
2200
2201 bool isVecListFourQHWordIndexed() const {
2202 if (!isDoubleSpacedVectorIndexed()) return false;
2203 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2204 }
2205
2206 bool isVecListFourDWordIndexed() const {
2207 if (!isSingleSpacedVectorIndexed()) return false;
2208 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2209 }
2210
2211 bool isVectorIndex() const { return Kind == k_VectorIndex; }
2212
2213 template <unsigned NumLanes>
2214 bool isVectorIndexInRange() const {
2215 if (Kind != k_VectorIndex) return false;
2216 return VectorIndex.Val < NumLanes;
2217 }
2218
2219 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
2220 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2221 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2222 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2223
2224 template<int PermittedValue, int OtherPermittedValue>
2225 bool isMVEPairVectorIndex() const {
2226 if (Kind != k_VectorIndex) return false;
2227 return VectorIndex.Val == PermittedValue ||
2228 VectorIndex.Val == OtherPermittedValue;
2229 }
2230
2231 bool isNEONi8splat() const {
2232 if (!isImm()) return false;
2233 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2234 // Must be a constant.
2235 if (!CE) return false;
2236 int64_t Value = CE->getValue();
2237 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2238 // value.
2239 return Value >= 0 && Value < 256;
2240 }
2241
2242 bool isNEONi16splat() const {
2243 if (isNEONByteReplicate(2))
2244 return false; // Leave that for bytes replication and forbid by default.
2245 if (!isImm())
2246 return false;
2247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2248 // Must be a constant.
2249 if (!CE) return false;
2250 unsigned Value = CE->getValue();
2251 return ARM_AM::isNEONi16splat(Value);
2252 }
2253
2254 bool isNEONi16splatNot() const {
2255 if (!isImm())
2256 return false;
2257 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2258 // Must be a constant.
2259 if (!CE) return false;
2260 unsigned Value = CE->getValue();
2261 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2262 }
2263
2264 bool isNEONi32splat() const {
2265 if (isNEONByteReplicate(4))
2266 return false; // Leave that for bytes replication and forbid by default.
2267 if (!isImm())
2268 return false;
2269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2270 // Must be a constant.
2271 if (!CE) return false;
2272 unsigned Value = CE->getValue();
2273 return ARM_AM::isNEONi32splat(Value);
2274 }
2275
2276 bool isNEONi32splatNot() const {
2277 if (!isImm())
2278 return false;
2279 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2280 // Must be a constant.
2281 if (!CE) return false;
2282 unsigned Value = CE->getValue();
2283 return ARM_AM::isNEONi32splat(~Value);
2284 }
2285
2286 static bool isValidNEONi32vmovImm(int64_t Value) {
2287 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2288 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2289 return ((Value & 0xffffffffffffff00) == 0) ||
2290 ((Value & 0xffffffffffff00ff) == 0) ||
2291 ((Value & 0xffffffffff00ffff) == 0) ||
2292 ((Value & 0xffffffff00ffffff) == 0) ||
2293 ((Value & 0xffffffffffff00ff) == 0xff) ||
2294 ((Value & 0xffffffffff00ffff) == 0xffff);
2295 }
2296
2297 bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2298 assert((Width == 8 || Width == 16 || Width == 32) &&(static_cast <bool> ((Width == 8 || Width == 16 || Width
== 32) && "Invalid element width") ? void (0) : __assert_fail
("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2299, __extension__
__PRETTY_FUNCTION__))
2299 "Invalid element width")(static_cast <bool> ((Width == 8 || Width == 16 || Width
== 32) && "Invalid element width") ? void (0) : __assert_fail
("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2299, __extension__
__PRETTY_FUNCTION__))
;
2300 assert(NumElems * Width <= 64 && "Invalid result width")(static_cast <bool> (NumElems * Width <= 64 &&
"Invalid result width") ? void (0) : __assert_fail ("NumElems * Width <= 64 && \"Invalid result width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2300, __extension__
__PRETTY_FUNCTION__))
;
2301
2302 if (!isImm())
2303 return false;
2304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2305 // Must be a constant.
2306 if (!CE)
2307 return false;
2308 int64_t Value = CE->getValue();
2309 if (!Value)
2310 return false; // Don't bother with zero.
2311 if (Inv)
2312 Value = ~Value;
2313
2314 uint64_t Mask = (1ull << Width) - 1;
2315 uint64_t Elem = Value & Mask;
2316 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2317 return false;
2318 if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2319 return false;
2320
2321 for (unsigned i = 1; i < NumElems; ++i) {
2322 Value >>= Width;
2323 if ((Value & Mask) != Elem)
2324 return false;
2325 }
2326 return true;
2327 }
2328
2329 bool isNEONByteReplicate(unsigned NumBytes) const {
2330 return isNEONReplicate(8, NumBytes, false);
2331 }
2332
2333 static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2334 assert((FromW == 8 || FromW == 16 || FromW == 32) &&(static_cast <bool> ((FromW == 8 || FromW == 16 || FromW
== 32) && "Invalid source width") ? void (0) : __assert_fail
("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2335, __extension__
__PRETTY_FUNCTION__))
2335 "Invalid source width")(static_cast <bool> ((FromW == 8 || FromW == 16 || FromW
== 32) && "Invalid source width") ? void (0) : __assert_fail
("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2335, __extension__
__PRETTY_FUNCTION__))
;
2336 assert((ToW == 16 || ToW == 32 || ToW == 64) &&(static_cast <bool> ((ToW == 16 || ToW == 32 || ToW == 64
) && "Invalid destination width") ? void (0) : __assert_fail
("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2337, __extension__
__PRETTY_FUNCTION__))
2337 "Invalid destination width")(static_cast <bool> ((ToW == 16 || ToW == 32 || ToW == 64
) && "Invalid destination width") ? void (0) : __assert_fail
("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2337, __extension__
__PRETTY_FUNCTION__))
;
2338 assert(FromW < ToW && "ToW is not less than FromW")(static_cast <bool> (FromW < ToW && "ToW is not less than FromW"
) ? void (0) : __assert_fail ("FromW < ToW && \"ToW is not less than FromW\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2338, __extension__
__PRETTY_FUNCTION__))
;
2339 }
2340
2341 template<unsigned FromW, unsigned ToW>
2342 bool isNEONmovReplicate() const {
2343 checkNeonReplicateArgs(FromW, ToW);
2344 if (ToW == 64 && isNEONi64splat())
2345 return false;
2346 return isNEONReplicate(FromW, ToW / FromW, false);
2347 }
2348
2349 template<unsigned FromW, unsigned ToW>
2350 bool isNEONinvReplicate() const {
2351 checkNeonReplicateArgs(FromW, ToW);
2352 return isNEONReplicate(FromW, ToW / FromW, true);
2353 }
2354
2355 bool isNEONi32vmov() const {
2356 if (isNEONByteReplicate(4))
2357 return false; // Let it to be classified as byte-replicate case.
2358 if (!isImm())
2359 return false;
2360 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2361 // Must be a constant.
2362 if (!CE)
2363 return false;
2364 return isValidNEONi32vmovImm(CE->getValue());
2365 }
2366
2367 bool isNEONi32vmovNeg() const {
2368 if (!isImm()) return false;
2369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2370 // Must be a constant.
2371 if (!CE) return false;
2372 return isValidNEONi32vmovImm(~CE->getValue());
2373 }
2374
2375 bool isNEONi64splat() const {
2376 if (!isImm()) return false;
2377 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2378 // Must be a constant.
2379 if (!CE) return false;
2380 uint64_t Value = CE->getValue();
2381 // i64 value with each byte being either 0 or 0xff.
2382 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2383 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2384 return true;
2385 }
2386
2387 template<int64_t Angle, int64_t Remainder>
2388 bool isComplexRotation() const {
2389 if (!isImm()) return false;
2390
2391 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2392 if (!CE) return false;
2393 uint64_t Value = CE->getValue();
2394
2395 return (Value % Angle == Remainder && Value <= 270);
2396 }
2397
2398 bool isMVELongShift() const {
2399 if (!isImm()) return false;
2400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2401 // Must be a constant.
2402 if (!CE) return false;
2403 uint64_t Value = CE->getValue();
2404 return Value >= 1 && Value <= 32;
2405 }
2406
2407 bool isMveSaturateOp() const {
2408 if (!isImm()) return false;
2409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2410 if (!CE) return false;
2411 uint64_t Value = CE->getValue();
2412 return Value == 48 || Value == 64;
2413 }
2414
2415 bool isITCondCodeNoAL() const {
2416 if (!isITCondCode()) return false;
2417 ARMCC::CondCodes CC = getCondCode();
2418 return CC != ARMCC::AL;
2419 }
2420
2421 bool isITCondCodeRestrictedI() const {
2422 if (!isITCondCode())
2423 return false;
2424 ARMCC::CondCodes CC = getCondCode();
2425 return CC == ARMCC::EQ || CC == ARMCC::NE;
2426 }
2427
2428 bool isITCondCodeRestrictedS() const {
2429 if (!isITCondCode())
2430 return false;
2431 ARMCC::CondCodes CC = getCondCode();
2432 return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2433 CC == ARMCC::GE;
2434 }
2435
2436 bool isITCondCodeRestrictedU() const {
2437 if (!isITCondCode())
2438 return false;
2439 ARMCC::CondCodes CC = getCondCode();
2440 return CC == ARMCC::HS || CC == ARMCC::HI;
2441 }
2442
2443 bool isITCondCodeRestrictedFP() const {
2444 if (!isITCondCode())
2445 return false;
2446 ARMCC::CondCodes CC = getCondCode();
2447 return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2448 CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2449 }
2450
2451 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2452 // Add as immediates when possible. Null MCExpr = 0.
2453 if (!Expr)
2454 Inst.addOperand(MCOperand::createImm(0));
2455 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2456 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2457 else
2458 Inst.addOperand(MCOperand::createExpr(Expr));
2459 }
2460
2461 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2462 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2462, __extension__
__PRETTY_FUNCTION__))
;
2463 addExpr(Inst, getImm());
2464 }
2465
2466 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2467 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2467, __extension__
__PRETTY_FUNCTION__))
;
2468 addExpr(Inst, getImm());
2469 }
2470
2471 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2472 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2472, __extension__
__PRETTY_FUNCTION__))
;
2473 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2474 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2475 Inst.addOperand(MCOperand::createReg(RegNum));
2476 }
2477
2478 void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2479 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2479, __extension__
__PRETTY_FUNCTION__))
;
2480 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2481 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2482 Inst.addOperand(MCOperand::createReg(RegNum));
2483 Inst.addOperand(MCOperand::createReg(0));
2484 }
2485
2486 void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2487 assert(N == 4 && "Invalid number of operands!")(static_cast <bool> (N == 4 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 4 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2487, __extension__
__PRETTY_FUNCTION__))
;
2488 addVPTPredNOperands(Inst, N-1);
2489 unsigned RegNum;
2490 if (getVPTPred() == ARMVCC::None) {
2491 RegNum = 0;
2492 } else {
2493 unsigned NextOpIndex = Inst.getNumOperands();
2494 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2495 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2496 assert(TiedOp >= 0 &&(static_cast <bool> (TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"
) ? void (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2497, __extension__
__PRETTY_FUNCTION__))
2497 "Inactive register in vpred_r is not tied to an output!")(static_cast <bool> (TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"
) ? void (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2497, __extension__
__PRETTY_FUNCTION__))
;
2498 RegNum = Inst.getOperand(TiedOp).getReg();
2499 }
2500 Inst.addOperand(MCOperand::createReg(RegNum));
2501 }
2502
2503 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2504 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2504, __extension__
__PRETTY_FUNCTION__))
;
2505 Inst.addOperand(MCOperand::createImm(getCoproc()));
2506 }
2507
2508 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2509 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2509, __extension__
__PRETTY_FUNCTION__))
;
2510 Inst.addOperand(MCOperand::createImm(getCoproc()));
2511 }
2512
2513 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2514 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2514, __extension__
__PRETTY_FUNCTION__))
;
2515 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2516 }
2517
2518 void addITMaskOperands(MCInst &Inst, unsigned N) const {
2519 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2519, __extension__
__PRETTY_FUNCTION__))
;
2520 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2521 }
2522
2523 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2524 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2524, __extension__
__PRETTY_FUNCTION__))
;
2525 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2526 }
2527
2528 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2529 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2529, __extension__
__PRETTY_FUNCTION__))
;
2530 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
2531 }
2532
2533 void addCCOutOperands(MCInst &Inst, unsigned N) const {
2534 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2534, __extension__
__PRETTY_FUNCTION__))
;
2535 Inst.addOperand(MCOperand::createReg(getReg()));
2536 }
2537
2538 void addRegOperands(MCInst &Inst, unsigned N) const {
2539 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2539, __extension__
__PRETTY_FUNCTION__))
;
2540 Inst.addOperand(MCOperand::createReg(getReg()));
2541 }
2542
2543 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2544 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2544, __extension__
__PRETTY_FUNCTION__))
;
2545 assert(isRegShiftedReg() &&(static_cast <bool> (isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"
) ? void (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2546, __extension__
__PRETTY_FUNCTION__))
2546 "addRegShiftedRegOperands() on non-RegShiftedReg!")(static_cast <bool> (isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"
) ? void (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2546, __extension__
__PRETTY_FUNCTION__))
;
2547 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2548 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2549 Inst.addOperand(MCOperand::createImm(
2550 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2551 }
2552
2553 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2554 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2554, __extension__
__PRETTY_FUNCTION__))
;
2555 assert(isRegShiftedImm() &&(static_cast <bool> (isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"
) ? void (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2556, __extension__
__PRETTY_FUNCTION__))
2556 "addRegShiftedImmOperands() on non-RegShiftedImm!")(static_cast <bool> (isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"
) ? void (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2556, __extension__
__PRETTY_FUNCTION__))
;
2557 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2558 // Shift of #32 is encoded as 0 where permitted
2559 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2560 Inst.addOperand(MCOperand::createImm(
2561 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2562 }
2563
2564 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2565 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2565, __extension__
__PRETTY_FUNCTION__))
;
2566 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2567 ShifterImm.Imm));
2568 }
2569
2570 void addRegListOperands(MCInst &Inst, unsigned N) const {
2571 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2571, __extension__
__PRETTY_FUNCTION__))
;
2572 const SmallVectorImpl<unsigned> &RegList = getRegList();
2573 for (unsigned Reg : RegList)
2574 Inst.addOperand(MCOperand::createReg(Reg));
2575 }
2576
2577 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2578 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2578, __extension__
__PRETTY_FUNCTION__))
;
2579 const SmallVectorImpl<unsigned> &RegList = getRegList();
2580 for (unsigned Reg : RegList)
2581 Inst.addOperand(MCOperand::createReg(Reg));
2582 }
2583
2584 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2585 addRegListOperands(Inst, N);
2586 }
2587
2588 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2589 addRegListOperands(Inst, N);
2590 }
2591
2592 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2593 addRegListOperands(Inst, N);
2594 }
2595
2596 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2597 addRegListOperands(Inst, N);
2598 }
2599
2600 void addRotImmOperands(MCInst &Inst, unsigned N) const {
2601 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2601, __extension__
__PRETTY_FUNCTION__))
;
2602 // Encoded as val>>3. The printer handles display as 8, 16, 24.
2603 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2604 }
2605
2606 void addModImmOperands(MCInst &Inst, unsigned N) const {
2607 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2607, __extension__
__PRETTY_FUNCTION__))
;
2608
2609 // Support for fixups (MCFixup)
2610 if (isImm())
2611 return addImmOperands(Inst, N);
2612
2613 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2614 }
2615
2616 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2617 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2617, __extension__
__PRETTY_FUNCTION__))
;
2618 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2619 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2620 Inst.addOperand(MCOperand::createImm(Enc));
2621 }
2622
2623 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2624 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2624, __extension__
__PRETTY_FUNCTION__))
;
2625 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2626 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2627 Inst.addOperand(MCOperand::createImm(Enc));
2628 }
2629
2630 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2631 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2631, __extension__
__PRETTY_FUNCTION__))
;
2632 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2633 uint32_t Val = -CE->getValue();
2634 Inst.addOperand(MCOperand::createImm(Val));
2635 }
2636
2637 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2638 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2638, __extension__
__PRETTY_FUNCTION__))
;
2639 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2640 uint32_t Val = -CE->getValue();
2641 Inst.addOperand(MCOperand::createImm(Val));
2642 }
2643
2644 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2645 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2645, __extension__
__PRETTY_FUNCTION__))
;
2646 // Munge the lsb/width into a bitfield mask.
2647 unsigned lsb = Bitfield.LSB;
2648 unsigned width = Bitfield.Width;
2649 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2650 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2651 (32 - (lsb + width)));
2652 Inst.addOperand(MCOperand::createImm(Mask));
2653 }
2654
2655 void addImmOperands(MCInst &Inst, unsigned N) const {
2656 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2656, __extension__
__PRETTY_FUNCTION__))
;
2657 addExpr(Inst, getImm());
2658 }
2659
2660 void addFBits16Operands(MCInst &Inst, unsigned N) const {
2661 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2661, __extension__
__PRETTY_FUNCTION__))
;
2662 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2663 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2664 }
2665
2666 void addFBits32Operands(MCInst &Inst, unsigned N) const {
2667 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2667, __extension__
__PRETTY_FUNCTION__))
;
2668 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2669 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2670 }
2671
2672 void addFPImmOperands(MCInst &Inst, unsigned N) const {
2673 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2673, __extension__
__PRETTY_FUNCTION__))
;
2674 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2675 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2676 Inst.addOperand(MCOperand::createImm(Val));
2677 }
2678
2679 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2680 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2680, __extension__
__PRETTY_FUNCTION__))
;
2681 // FIXME: We really want to scale the value here, but the LDRD/STRD
2682 // instruction don't encode operands that way yet.
2683 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2684 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2685 }
2686
2687 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2688 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2688, __extension__
__PRETTY_FUNCTION__))
;
2689 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2690 // instruction don't encode operands that way yet.
2691 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2692 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2693 }
2694
2695 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2696 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2696, __extension__
__PRETTY_FUNCTION__))
;
2697 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2698 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2699 }
2700
2701 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2702 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2702, __extension__
__PRETTY_FUNCTION__))
;
2703 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2704 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2705 }
2706
2707 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2708 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2708, __extension__
__PRETTY_FUNCTION__))
;
2709 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2710 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2711 }
2712
2713 void addImm7Operands(MCInst &Inst, unsigned N) const {
2714 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2714, __extension__
__PRETTY_FUNCTION__))
;
2715 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2716 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2717 }
2718
2719 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2720 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2720, __extension__
__PRETTY_FUNCTION__))
;
2721 // The immediate is scaled by four in the encoding and is stored
2722 // in the MCInst as such. Lop off the low two bits here.
2723 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2724 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2725 }
2726
2727 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2728 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2728, __extension__
__PRETTY_FUNCTION__))
;
2729 // The immediate is scaled by four in the encoding and is stored
2730 // in the MCInst as such. Lop off the low two bits here.
2731 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2732 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2733 }
2734
2735 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2736 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2736, __extension__
__PRETTY_FUNCTION__))
;
2737 // The immediate is scaled by four in the encoding and is stored
2738 // in the MCInst as such. Lop off the low two bits here.
2739 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2740 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2741 }
2742
2743 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2744 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2744, __extension__
__PRETTY_FUNCTION__))
;
2745 // The constant encodes as the immediate-1, and we store in the instruction
2746 // the bits as encoded, so subtract off one here.
2747 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2748 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2749 }
2750
2751 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2752 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2752, __extension__
__PRETTY_FUNCTION__))
;
2753 // The constant encodes as the immediate-1, and we store in the instruction
2754 // the bits as encoded, so subtract off one here.
2755 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2756 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2757 }
2758
2759 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2760 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2760, __extension__
__PRETTY_FUNCTION__))
;
2761 // The constant encodes as the immediate, except for 32, which encodes as
2762 // zero.
2763 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2764 unsigned Imm = CE->getValue();
2765 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2766 }
2767
2768 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2769 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2769, __extension__
__PRETTY_FUNCTION__))
;
2770 // An ASR value of 32 encodes as 0, so that's how we want to add it to
2771 // the instruction as well.
2772 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2773 int Val = CE->getValue();
2774 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2775 }
2776
2777 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2778 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2778, __extension__
__PRETTY_FUNCTION__))
;
2779 // The operand is actually a t2_so_imm, but we have its bitwise
2780 // negation in the assembly source, so twiddle it here.
2781 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2782 Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2783 }
2784
2785 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2786 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2786, __extension__
__PRETTY_FUNCTION__))
;
2787 // The operand is actually a t2_so_imm, but we have its
2788 // negation in the assembly source, so twiddle it here.
2789 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2790 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2791 }
2792
2793 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2794 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2794, __extension__
__PRETTY_FUNCTION__))
;
2795 // The operand is actually an imm0_4095, but we have its
2796 // negation in the assembly source, so twiddle it here.
2797 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2798 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2799 }
2800
2801 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2802 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2803 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2804 return;
2805 }
2806 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2807 Inst.addOperand(MCOperand::createExpr(SR));
2808 }
2809
2810 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2811 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2811, __extension__
__PRETTY_FUNCTION__))
;
2812 if (isImm()) {
2813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2814 if (CE) {
2815 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2816 return;
2817 }
2818 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2819 Inst.addOperand(MCOperand::createExpr(SR));
2820 return;
2821 }
2822
2823 assert(isGPRMem() && "Unknown value type!")(static_cast <bool> (isGPRMem() && "Unknown value type!"
) ? void (0) : __assert_fail ("isGPRMem() && \"Unknown value type!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2823, __extension__
__PRETTY_FUNCTION__))
;
2824 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!")(static_cast <bool> (isa<MCConstantExpr>(Memory.OffsetImm
) && "Unknown value type!") ? void (0) : __assert_fail
("isa<MCConstantExpr>(Memory.OffsetImm) && \"Unknown value type!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2824, __extension__
__PRETTY_FUNCTION__))
;
2825 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2826 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2827 else
2828 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2829 }
2830
2831 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2832 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2832, __extension__
__PRETTY_FUNCTION__))
;
2833 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2834 }
2835
2836 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2837 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2837, __extension__
__PRETTY_FUNCTION__))
;
2838 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2839 }
2840
2841 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2842 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2842, __extension__
__PRETTY_FUNCTION__))
;
2843 Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2844 }
2845
2846 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2847 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2847, __extension__
__PRETTY_FUNCTION__))
;
2848 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2849 }
2850
2851 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2852 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2852, __extension__
__PRETTY_FUNCTION__))
;
2853 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2854 }
2855
2856 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2857 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2857, __extension__
__PRETTY_FUNCTION__))
;
2858 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2859 }
2860
2861 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2862 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2862, __extension__
__PRETTY_FUNCTION__))
;
2863 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2864 }
2865
2866 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2867 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2867, __extension__
__PRETTY_FUNCTION__))
;
2868 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2869 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2870 else
2871 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2872 }
2873
2874 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2875 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2875, __extension__
__PRETTY_FUNCTION__))
;
2876 assert(isImm() && "Not an immediate!")(static_cast <bool> (isImm() && "Not an immediate!"
) ? void (0) : __assert_fail ("isImm() && \"Not an immediate!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2876, __extension__
__PRETTY_FUNCTION__))
;
2877
2878 // If we have an immediate that's not a constant, treat it as a label
2879 // reference needing a fixup.
2880 if (!isa<MCConstantExpr>(getImm())) {
2881 Inst.addOperand(MCOperand::createExpr(getImm()));
2882 return;
2883 }
2884
2885 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2886 int Val = CE->getValue();
2887 Inst.addOperand(MCOperand::createImm(Val));
2888 }
2889
2890 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2891 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2891, __extension__
__PRETTY_FUNCTION__))
;
2892 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2893 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2894 }
2895
2896 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2897 addAlignedMemoryOperands(Inst, N);
2898 }
2899
2900 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2901 addAlignedMemoryOperands(Inst, N);
2902 }
2903
2904 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2905 addAlignedMemoryOperands(Inst, N);
2906 }
2907
2908 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2909 addAlignedMemoryOperands(Inst, N);
2910 }
2911
2912 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2913 addAlignedMemoryOperands(Inst, N);
2914 }
2915
2916 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2917 addAlignedMemoryOperands(Inst, N);
2918 }
2919
2920 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2921 addAlignedMemoryOperands(Inst, N);
2922 }
2923
2924 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2925 addAlignedMemoryOperands(Inst, N);
2926 }
2927
2928 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2929 addAlignedMemoryOperands(Inst, N);
2930 }
2931
2932 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2933 addAlignedMemoryOperands(Inst, N);
2934 }
2935
2936 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2937 addAlignedMemoryOperands(Inst, N);
2938 }
2939
2940 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2941 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2941, __extension__
__PRETTY_FUNCTION__))
;
2942 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2943 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2944 if (!Memory.OffsetRegNum) {
2945 if (!Memory.OffsetImm)
2946 Inst.addOperand(MCOperand::createImm(0));
2947 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
2948 int32_t Val = CE->getValue();
2949 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2950 // Special case for #-0
2951 if (Val == std::numeric_limits<int32_t>::min())
2952 Val = 0;
2953 if (Val < 0)
2954 Val = -Val;
2955 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2956 Inst.addOperand(MCOperand::createImm(Val));
2957 } else
2958 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2959 } else {
2960 // For register offset, we encode the shift type and negation flag
2961 // here.
2962 int32_t Val =
2963 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2964 Memory.ShiftImm, Memory.ShiftType);
2965 Inst.addOperand(MCOperand::createImm(Val));
2966 }
2967 }
2968
2969 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2970 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2970, __extension__
__PRETTY_FUNCTION__))
;
2971 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2972 assert(CE && "non-constant AM2OffsetImm operand!")(static_cast <bool> (CE && "non-constant AM2OffsetImm operand!"
) ? void (0) : __assert_fail ("CE && \"non-constant AM2OffsetImm operand!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2972, __extension__
__PRETTY_FUNCTION__))
;
2973 int32_t Val = CE->getValue();
2974 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2975 // Special case for #-0
2976 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2977 if (Val < 0) Val = -Val;
2978 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2979 Inst.addOperand(MCOperand::createReg(0));
2980 Inst.addOperand(MCOperand::createImm(Val));
2981 }
2982
2983 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2984 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2984, __extension__
__PRETTY_FUNCTION__))
;
2985 // If we have an immediate that's not a constant, treat it as a label
2986 // reference needing a fixup. If it is a constant, it's something else
2987 // and we reject it.
2988 if (isImm()) {
2989 Inst.addOperand(MCOperand::createExpr(getImm()));
2990 Inst.addOperand(MCOperand::createReg(0));
2991 Inst.addOperand(MCOperand::createImm(0));
2992 return;
2993 }
2994
2995 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2996 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2997 if (!Memory.OffsetRegNum) {
2998 if (!Memory.OffsetImm)
2999 Inst.addOperand(MCOperand::createImm(0));
3000 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3001 int32_t Val = CE->getValue();
3002 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3003 // Special case for #-0
3004 if (Val == std::numeric_limits<int32_t>::min())
3005 Val = 0;
3006 if (Val < 0)
3007 Val = -Val;
3008 Val = ARM_AM::getAM3Opc(AddSub, Val);
3009 Inst.addOperand(MCOperand::createImm(Val));
3010 } else
3011 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3012 } else {
3013 // For register offset, we encode the shift type and negation flag
3014 // here.
3015 int32_t Val =
3016 ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
3017 Inst.addOperand(MCOperand::createImm(Val));
3018 }
3019 }
3020
3021 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
3022 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3022, __extension__
__PRETTY_FUNCTION__))
;
3023 if (Kind == k_PostIndexRegister) {
3024 int32_t Val =
3025 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
3026 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3027 Inst.addOperand(MCOperand::createImm(Val));
3028 return;
3029 }
3030
3031 // Constant offset.
3032 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
3033 int32_t Val = CE->getValue();
3034 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3035 // Special case for #-0
3036 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3037 if (Val < 0) Val = -Val;
3038 Val = ARM_AM::getAM3Opc(AddSub, Val);
3039 Inst.addOperand(MCOperand::createReg(0));
3040 Inst.addOperand(MCOperand::createImm(Val));
3041 }
3042
3043 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
3044 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3044, __extension__
__PRETTY_FUNCTION__))
;
3045 // If we have an immediate that's not a constant, treat it as a label
3046 // reference needing a fixup. If it is a constant, it's something else
3047 // and we reject it.
3048 if (isImm()) {
3049 Inst.addOperand(MCOperand::createExpr(getImm()));
3050 Inst.addOperand(MCOperand::createImm(0));
3051 return;
3052 }
3053
3054 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3055 if (!Memory.OffsetImm)
3056 Inst.addOperand(MCOperand::createImm(0));
3057 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3058 // The lower two bits are always zero and as such are not encoded.
3059 int32_t Val = CE->getValue() / 4;
3060 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3061 // Special case for #-0
3062 if (Val == std::numeric_limits<int32_t>::min())
3063 Val = 0;
3064 if (Val < 0)
3065 Val = -Val;
3066 Val = ARM_AM::getAM5Opc(AddSub, Val);
3067 Inst.addOperand(MCOperand::createImm(Val));
3068 } else
3069 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3070 }
3071
3072 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
3073 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3073, __extension__
__PRETTY_FUNCTION__))
;
3074 // If we have an immediate that's not a constant, treat it as a label
3075 // reference needing a fixup. If it is a constant, it's something else
3076 // and we reject it.
3077 if (isImm()) {
3078 Inst.addOperand(MCOperand::createExpr(getImm()));
3079 Inst.addOperand(MCOperand::createImm(0));
3080 return;
3081 }
3082
3083 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3084 // The lower bit is always zero and as such is not encoded.
3085 if (!Memory.OffsetImm)
3086 Inst.addOperand(MCOperand::createImm(0));
3087 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3088 int32_t Val = CE->getValue() / 2;
3089 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3090 // Special case for #-0
3091 if (Val == std::numeric_limits<int32_t>::min())
3092 Val = 0;
3093 if (Val < 0)
3094 Val = -Val;
3095 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
3096 Inst.addOperand(MCOperand::createImm(Val));
3097 } else
3098 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3099 }
3100
3101 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
3102 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3102, __extension__
__PRETTY_FUNCTION__))
;
3103 // If we have an immediate that's not a constant, treat it as a label
3104 // reference needing a fixup. If it is a constant, it's something else
3105 // and we reject it.
3106 if (isImm()) {
3107 Inst.addOperand(MCOperand::createExpr(getImm()));
3108 Inst.addOperand(MCOperand::createImm(0));
3109 return;
3110 }
3111
3112 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3113 addExpr(Inst, Memory.OffsetImm);
3114 }
3115
3116 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
3117 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3117, __extension__
__PRETTY_FUNCTION__))
;
3118 // If we have an immediate that's not a constant, treat it as a label
3119 // reference needing a fixup. If it is a constant, it's something else
3120 // and we reject it.
3121 if (isImm()) {
3122 Inst.addOperand(MCOperand::createExpr(getImm()));
3123 Inst.addOperand(MCOperand::createImm(0));
3124 return;
3125 }
3126
3127 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3128 addExpr(Inst, Memory.OffsetImm);
3129 }
3130
3131 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
3132 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3132, __extension__
__PRETTY_FUNCTION__))
;
3133 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3134 if (!Memory.OffsetImm)
3135 Inst.addOperand(MCOperand::createImm(0));
3136 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3137 // The lower two bits are always zero and as such are not encoded.
3138 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3139 else
3140 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3141 }
3142
3143 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
3144 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3144, __extension__
__PRETTY_FUNCTION__))
;
3145 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3146 addExpr(Inst, Memory.OffsetImm);
3147 }
3148
3149 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
3150 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3150, __extension__
__PRETTY_FUNCTION__))
;
3151 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3152 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3153 }
3154
3155 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3156 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3156, __extension__
__PRETTY_FUNCTION__))
;
3157 // If this is an immediate, it's a label reference.
3158 if (isImm()) {
3159 addExpr(Inst, getImm());
3160 Inst.addOperand(MCOperand::createImm(0));
3161 return;
3162 }
3163
3164 // Otherwise, it's a normal memory reg+offset.
3165 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3166 addExpr(Inst, Memory.OffsetImm);
3167 }
3168
3169 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3170 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3170, __extension__
__PRETTY_FUNCTION__))
;
3171 // If this is an immediate, it's a label reference.
3172 if (isImm()) {
3173 addExpr(Inst, getImm());
3174 Inst.addOperand(MCOperand::createImm(0));
3175 return;
3176 }
3177
3178 // Otherwise, it's a normal memory reg+offset.
3179 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3180 addExpr(Inst, Memory.OffsetImm);
3181 }
3182
3183 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3184 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3184, __extension__
__PRETTY_FUNCTION__))
;
3185 // This is container for the immediate that we will create the constant
3186 // pool from
3187 addExpr(Inst, getConstantPoolImm());
3188 }
3189
3190 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3191 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3191, __extension__
__PRETTY_FUNCTION__))
;
3192 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3193 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3194 }
3195
3196 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3197 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3197, __extension__
__PRETTY_FUNCTION__))
;
3198 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3199 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3200 }
3201
3202 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3203 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3203, __extension__
__PRETTY_FUNCTION__))
;
3204 unsigned Val =
3205 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3206 Memory.ShiftImm, Memory.ShiftType);
3207 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3208 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3209 Inst.addOperand(MCOperand::createImm(Val));
3210 }
3211
3212 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3213 assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3213, __extension__
__PRETTY_FUNCTION__))
;
3214 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3215 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3216 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3217 }
3218
3219 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3220 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3220, __extension__
__PRETTY_FUNCTION__))
;
3221 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3222 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3223 }
3224
3225 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3226 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3226, __extension__
__PRETTY_FUNCTION__))
;
3227 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3228 if (!Memory.OffsetImm)
3229 Inst.addOperand(MCOperand::createImm(0));
3230 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3231 // The lower two bits are always zero and as such are not encoded.
3232 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3233 else
3234 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3235 }
3236
3237 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3238 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3238, __extension__
__PRETTY_FUNCTION__))
;
3239 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3240 if (!Memory.OffsetImm)
3241 Inst.addOperand(MCOperand::createImm(0));
3242 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3243 Inst.addOperand(MCOperand::createImm(CE->getValue() / 2));
3244 else
3245 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3246 }
3247
3248 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3249 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3249, __extension__
__PRETTY_FUNCTION__))
;
3250 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3251 addExpr(Inst, Memory.OffsetImm);
3252 }
3253
3254 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3255 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3255, __extension__
__PRETTY_FUNCTION__))
;
3256 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3257 if (!Memory.OffsetImm)
3258 Inst.addOperand(MCOperand::createImm(0));
3259 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3260 // The lower two bits are always zero and as such are not encoded.
3261 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3262 else
3263 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3264 }
3265
3266 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3267 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3267, __extension__
__PRETTY_FUNCTION__))
;
3268 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3269 assert(CE && "non-constant post-idx-imm8 operand!")(static_cast <bool> (CE && "non-constant post-idx-imm8 operand!"
) ? void (0) : __assert_fail ("CE && \"non-constant post-idx-imm8 operand!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3269, __extension__
__PRETTY_FUNCTION__))
;
3270 int Imm = CE->getValue();
3271 bool isAdd = Imm >= 0;
3272 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3273 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3274 Inst.addOperand(MCOperand::createImm(Imm));
3275 }
3276
3277 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3278 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3278, __extension__
__PRETTY_FUNCTION__))
;
3279 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3280 assert(CE && "non-constant post-idx-imm8s4 operand!")(static_cast <bool> (CE && "non-constant post-idx-imm8s4 operand!"
) ? void (0) : __assert_fail ("CE && \"non-constant post-idx-imm8s4 operand!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3280, __extension__
__PRETTY_FUNCTION__))
;
3281 int Imm = CE->getValue();
3282 bool isAdd = Imm >= 0;
3283 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3284 // Immediate is scaled by 4.
3285 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3286 Inst.addOperand(MCOperand::createImm(Imm));
3287 }
3288
3289 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3290 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3290, __extension__
__PRETTY_FUNCTION__))
;
3291 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3292 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3293 }
3294
3295 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3296 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3296, __extension__
__PRETTY_FUNCTION__))
;
3297 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3298 // The sign, shift type, and shift amount are encoded in a single operand
3299 // using the AM2 encoding helpers.
3300 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3301 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3302 PostIdxReg.ShiftTy);
3303 Inst.addOperand(MCOperand::createImm(Imm));
3304 }
3305
3306 void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3307 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3307, __extension__
__PRETTY_FUNCTION__))
;
3308 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3309 Inst.addOperand(MCOperand::createImm(CE->getValue()));
3310 }
3311
3312 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3313 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3313, __extension__
__PRETTY_FUNCTION__))
;
3314 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3315 }
3316
3317 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3318 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3318, __extension__
__PRETTY_FUNCTION__))
;
3319 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3320 }
3321
3322 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3323 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3323, __extension__
__PRETTY_FUNCTION__))
;
3324 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3325 }
3326
3327 void addVecListOperands(MCInst &Inst, unsigned N) const {
3328 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3328, __extension__
__PRETTY_FUNCTION__))
;
3329 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3330 }
3331
3332 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3333 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3333, __extension__
__PRETTY_FUNCTION__))
;
3334
3335 // When we come here, the VectorList field will identify a range
3336 // of q-registers by its base register and length, and it will
3337 // have already been error-checked to be the expected length of
3338 // range and contain only q-regs in the range q0-q7. So we can
3339 // count on the base register being in the range q0-q6 (for 2
3340 // regs) or q0-q4 (for 4)
3341 //
3342 // The MVE instructions taking a register range of this kind will
3343 // need an operand in the MQQPR or MQQQQPR class, representing the
3344 // entire range as a unit. So we must translate into that class,
3345 // by finding the index of the base register in the MQPR reg
3346 // class, and returning the super-register at the corresponding
3347 // index in the target class.
3348
3349 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3350 const MCRegisterClass *RC_out =
3351 (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID]
3352 : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID];
3353
3354 unsigned I, E = RC_out->getNumRegs();
3355 for (I = 0; I < E; I++)
3356 if (RC_in->getRegister(I) == VectorList.RegNum)
3357 break;
3358 assert(I < E && "Invalid vector list start register!")(static_cast <bool> (I < E && "Invalid vector list start register!"
) ? void (0) : __assert_fail ("I < E && \"Invalid vector list start register!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3358, __extension__
__PRETTY_FUNCTION__))
;
3359
3360 Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3361 }
3362
3363 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3364 assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3364, __extension__
__PRETTY_FUNCTION__))
;
3365 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3366 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3367 }
3368
3369 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3370 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3370, __extension__
__PRETTY_FUNCTION__))
;
3371 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3372 }
3373
3374 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3375 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3375, __extension__
__PRETTY_FUNCTION__))
;
3376 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3377 }
3378
3379 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3380 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3380, __extension__
__PRETTY_FUNCTION__))
;
3381 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3382 }
3383
3384 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3385 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3385, __extension__
__PRETTY_FUNCTION__))
;
3386 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3387 }
3388
3389 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3390 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3390, __extension__
__PRETTY_FUNCTION__))
;
3391 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3392 }
3393
3394 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3395 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3395, __extension__
__PRETTY_FUNCTION__))
;
3396 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3397 }
3398
3399 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3400 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3400, __extension__
__PRETTY_FUNCTION__))
;
3401 // The immediate encodes the type of constant as well as the value.
3402 // Mask in that this is an i8 splat.
3403 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3404 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3405 }
3406
3407 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3408 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3408, __extension__
__PRETTY_FUNCTION__))
;
3409 // The immediate encodes the type of constant as well as the value.
3410 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3411 unsigned Value = CE->getValue();
3412 Value = ARM_AM::encodeNEONi16splat(Value);
3413 Inst.addOperand(MCOperand::createImm(Value));
3414 }
3415
3416 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3417 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3417, __extension__
__PRETTY_FUNCTION__))
;
3418 // The immediate encodes the type of constant as well as the value.
3419 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3420 unsigned Value = CE->getValue();
3421 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3422 Inst.addOperand(MCOperand::createImm(Value));
3423 }
3424
3425 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3426 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3426, __extension__
__PRETTY_FUNCTION__))
;
3427 // The immediate encodes the type of constant as well as the value.
3428 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3429 unsigned Value = CE->getValue();
3430 Value = ARM_AM::encodeNEONi32splat(Value);
3431 Inst.addOperand(MCOperand::createImm(Value));
3432 }
3433
3434 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3435 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3435, __extension__
__PRETTY_FUNCTION__))
;
3436 // The immediate encodes the type of constant as well as the value.
3437 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3438 unsigned Value = CE->getValue();
3439 Value = ARM_AM::encodeNEONi32splat(~Value);
3440 Inst.addOperand(MCOperand::createImm(Value));
3441 }
3442
3443 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3444 // The immediate encodes the type of constant as well as the value.
3445 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3446 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8
|| Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void
(0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3449, __extension__
__PRETTY_FUNCTION__))
3447 Inst.getOpcode() == ARM::VMOVv16i8) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8
|| Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void
(0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3449, __extension__
__PRETTY_FUNCTION__))
3448 "All instructions that wants to replicate non-zero byte "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8
|| Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void
(0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3449, __extension__
__PRETTY_FUNCTION__))
3449 "always must be replaced with VMOVv8i8 or VMOVv16i8.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8
|| Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte "
"always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void
(0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3449, __extension__
__PRETTY_FUNCTION__))
;
3450 unsigned Value = CE->getValue();
3451 if (Inv)
3452 Value = ~Value;
3453 unsigned B = Value & 0xff;
3454 B |= 0xe00; // cmode = 0b1110
3455 Inst.addOperand(MCOperand::createImm(B));
3456 }
3457
3458 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3459 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3459, __extension__
__PRETTY_FUNCTION__))
;
3460 addNEONi8ReplicateOperands(Inst, true);
3461 }
3462
3463 static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3464 if (Value >= 256 && Value <= 0xffff)
3465 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3466 else if (Value > 0xffff && Value <= 0xffffff)
3467 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3468 else if (Value > 0xffffff)
3469 Value = (Value >> 24) | 0x600;
3470 return Value;
3471 }
3472
3473 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3474 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3474, __extension__
__PRETTY_FUNCTION__))
;
3475 // The immediate encodes the type of constant as well as the value.
3476 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3477 unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3478 Inst.addOperand(MCOperand::createImm(Value));
3479 }
3480
3481 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3482 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3482, __extension__
__PRETTY_FUNCTION__))
;
3483 addNEONi8ReplicateOperands(Inst, false);
3484 }
3485
3486 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3487 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3487, __extension__
__PRETTY_FUNCTION__))
;
3488 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3489 assert((Inst.getOpcode() == ARM::VMOVv4i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
3490 Inst.getOpcode() == ARM::VMOVv8i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
3491 Inst.getOpcode() == ARM::VMVNv4i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
3492 Inst.getOpcode() == ARM::VMVNv8i16) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
3493 "All instructions that want to replicate non-zero half-word "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
3494 "always must be replaced with V{MOV,MVN}v{4,8}i16.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16
|| Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() ==
ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) &&
"All instructions that want to replicate non-zero half-word "
"always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void (
0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3494, __extension__
__PRETTY_FUNCTION__))
;
3495 uint64_t Value = CE->getValue();
3496 unsigned Elem = Value & 0xffff;
3497 if (Elem >= 256)
3498 Elem = (Elem >> 8) | 0x200;
3499 Inst.addOperand(MCOperand::createImm(Elem));
3500 }
3501
3502 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3503 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3503, __extension__
__PRETTY_FUNCTION__))
;
3504 // The immediate encodes the type of constant as well as the value.
3505 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3506 unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3507 Inst.addOperand(MCOperand::createImm(Value));
3508 }
3509
3510 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3511 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3511, __extension__
__PRETTY_FUNCTION__))
;
3512 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3513 assert((Inst.getOpcode() == ARM::VMOVv2i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3514 Inst.getOpcode() == ARM::VMOVv4i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3515 Inst.getOpcode() == ARM::VMVNv2i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3516 Inst.getOpcode() == ARM::VMVNv4i32) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3517 "All instructions that want to replicate non-zero word "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3518 "always must be replaced with V{MOV,MVN}v{2,4}i32.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32
|| Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() ==
ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) &&
"All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."
) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
;
3519 uint64_t Value = CE->getValue();
3520 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3521 Inst.addOperand(MCOperand::createImm(Elem));
3522 }
3523
3524 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3525 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3525, __extension__
__PRETTY_FUNCTION__))
;
3526 // The immediate encodes the type of constant as well as the value.
3527 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3528 uint64_t Value = CE->getValue();
3529 unsigned Imm = 0;
3530 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3531 Imm |= (Value & 1) << i;
3532 }
3533 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3534 }
3535
3536 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3537 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3537, __extension__
__PRETTY_FUNCTION__))
;
3538 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3539 Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3540 }
3541
3542 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3543 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3543, __extension__
__PRETTY_FUNCTION__))
;
3544 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3545 Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3546 }
3547
3548 void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3549 assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3549, __extension__
__PRETTY_FUNCTION__))
;
3550 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3551 unsigned Imm = CE->getValue();
3552 assert((Imm == 48 || Imm == 64) && "Invalid saturate operand")(static_cast <bool> ((Imm == 48 || Imm == 64) &&
"Invalid saturate operand") ? void (0) : __assert_fail ("(Imm == 48 || Imm == 64) && \"Invalid saturate operand\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3552, __extension__
__PRETTY_FUNCTION__))
;
3553 Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3554 }
3555
3556 void print(raw_ostream &OS) const override;
3557
3558 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3559 auto Op = std::make_unique<ARMOperand>(k_ITCondMask);
3560 Op->ITMask.Mask = Mask;
3561 Op->StartLoc = S;
3562 Op->EndLoc = S;
3563 return Op;
3564 }
3565
3566 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3567 SMLoc S) {
3568 auto Op = std::make_unique<ARMOperand>(k_CondCode);
3569 Op->CC.Val = CC;
3570 Op->StartLoc = S;
3571 Op->EndLoc = S;
3572 return Op;
3573 }
3574
3575 static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3576 SMLoc S) {
3577 auto Op = std::make_unique<ARMOperand>(k_VPTPred);
3578 Op->VCC.Val = CC;
3579 Op->StartLoc = S;
3580 Op->EndLoc = S;
3581 return Op;
3582 }
3583
3584 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3585 auto Op = std::make_unique<ARMOperand>(k_CoprocNum);
3586 Op->Cop.Val = CopVal;
3587 Op->StartLoc = S;
3588 Op->EndLoc = S;
3589 return Op;
3590 }
3591
3592 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3593 auto Op = std::make_unique<ARMOperand>(k_CoprocReg);
3594 Op->Cop.Val = CopVal;
3595 Op->StartLoc = S;
3596 Op->EndLoc = S;
3597 return Op;
3598 }
3599
3600 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3601 SMLoc E) {
3602 auto Op = std::make_unique<ARMOperand>(k_CoprocOption);
3603 Op->Cop.Val = Val;
3604 Op->StartLoc = S;
3605 Op->EndLoc = E;
3606 return Op;
3607 }
3608
3609 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3610 auto Op = std::make_unique<ARMOperand>(k_CCOut);
3611 Op->Reg.RegNum = RegNum;
3612 Op->StartLoc = S;
3613 Op->EndLoc = S;
3614 return Op;
3615 }
3616
3617 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3618 auto Op = std::make_unique<ARMOperand>(k_Token);
3619 Op->Tok.Data = Str.data();
3620 Op->Tok.Length = Str.size();
3621 Op->StartLoc = S;
3622 Op->EndLoc = S;
3623 return Op;
3624 }
3625
3626 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3627 SMLoc E) {
3628 auto Op = std::make_unique<ARMOperand>(k_Register);
3629 Op->Reg.RegNum = RegNum;
3630 Op->StartLoc = S;
3631 Op->EndLoc = E;
3632 return Op;
3633 }
3634
3635 static std::unique_ptr<ARMOperand>
3636 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3637 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3638 SMLoc E) {
3639 auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister);
3640 Op->RegShiftedReg.ShiftTy = ShTy;
3641 Op->RegShiftedReg.SrcReg = SrcReg;
3642 Op->RegShiftedReg.ShiftReg = ShiftReg;
3643 Op->RegShiftedReg.ShiftImm = ShiftImm;
3644 Op->StartLoc = S;
3645 Op->EndLoc = E;
3646 return Op;
3647 }
3648
3649 static std::unique_ptr<ARMOperand>
3650 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3651 unsigned ShiftImm, SMLoc S, SMLoc E) {
3652 auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate);
3653 Op->RegShiftedImm.ShiftTy = ShTy;
3654 Op->RegShiftedImm.SrcReg = SrcReg;
3655 Op->RegShiftedImm.ShiftImm = ShiftImm;
3656 Op->StartLoc = S;
3657 Op->EndLoc = E;
3658 return Op;
3659 }
3660
3661 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3662 SMLoc S, SMLoc E) {
3663 auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate);
3664 Op->ShifterImm.isASR = isASR;
3665 Op->ShifterImm.Imm = Imm;
3666 Op->StartLoc = S;
3667 Op->EndLoc = E;
3668 return Op;
3669 }
3670
3671 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3672 SMLoc E) {
3673 auto Op = std::make_unique<ARMOperand>(k_RotateImmediate);
3674 Op->RotImm.Imm = Imm;
3675 Op->StartLoc = S;
3676 Op->EndLoc = E;
3677 return Op;
3678 }
3679
3680 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3681 SMLoc S, SMLoc E) {
3682 auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate);
3683 Op->ModImm.Bits = Bits;
3684 Op->ModImm.Rot = Rot;
3685 Op->StartLoc = S;
3686 Op->EndLoc = E;
3687 return Op;
3688 }
3689
3690 static std::unique_ptr<ARMOperand>
3691 CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3692 auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate);
3693 Op->Imm.Val = Val;
3694 Op->StartLoc = S;
3695 Op->EndLoc = E;
3696 return Op;
3697 }
3698
3699 static std::unique_ptr<ARMOperand>
3700 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3701 auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor);
3702 Op->Bitfield.LSB = LSB;
3703 Op->Bitfield.Width = Width;
3704 Op->StartLoc = S;
3705 Op->EndLoc = E;
3706 return Op;
3707 }
3708
3709 static std::unique_ptr<ARMOperand>
3710 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3711 SMLoc StartLoc, SMLoc EndLoc) {
3712 assert(Regs.size() > 0 && "RegList contains no registers?")(static_cast <bool> (Regs.size() > 0 && "RegList contains no registers?"
) ? void (0) : __assert_fail ("Regs.size() > 0 && \"RegList contains no registers?\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3712, __extension__
__PRETTY_FUNCTION__))
;
3713 KindTy Kind = k_RegisterList;
3714
3715 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3716 Regs.front().second)) {
3717 if (Regs.back().second == ARM::VPR)
3718 Kind = k_FPDRegisterListWithVPR;
3719 else
3720 Kind = k_DPRRegisterList;
3721 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3722 Regs.front().second)) {
3723 if (Regs.back().second == ARM::VPR)
3724 Kind = k_FPSRegisterListWithVPR;
3725 else
3726 Kind = k_SPRRegisterList;
3727 }
3728
3729 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3730 Kind = k_RegisterListWithAPSR;
3731
3732 assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding")(static_cast <bool> (llvm::is_sorted(Regs) && "Register list must be sorted by encoding"
) ? void (0) : __assert_fail ("llvm::is_sorted(Regs) && \"Register list must be sorted by encoding\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3732, __extension__
__PRETTY_FUNCTION__))
;
3733
3734 auto Op = std::make_unique<ARMOperand>(Kind);
3735 for (const auto &P : Regs)
3736 Op->Registers.push_back(P.second);
3737
3738 Op->StartLoc = StartLoc;
3739 Op->EndLoc = EndLoc;
3740 return Op;
3741 }
3742
3743 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3744 unsigned Count,
3745 bool isDoubleSpaced,
3746 SMLoc S, SMLoc E) {
3747 auto Op = std::make_unique<ARMOperand>(k_VectorList);
3748 Op->VectorList.RegNum = RegNum;
3749 Op->VectorList.Count = Count;
3750 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3751 Op->StartLoc = S;
3752 Op->EndLoc = E;
3753 return Op;
3754 }
3755
3756 static std::unique_ptr<ARMOperand>
3757 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3758 SMLoc S, SMLoc E) {
3759 auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes);
3760 Op->VectorList.RegNum = RegNum;
3761 Op->VectorList.Count = Count;
3762 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3763 Op->StartLoc = S;
3764 Op->EndLoc = E;
3765 return Op;
3766 }
3767
3768 static std::unique_ptr<ARMOperand>
3769 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3770 bool isDoubleSpaced, SMLoc S, SMLoc E) {
3771 auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed);
3772 Op->VectorList.RegNum = RegNum;
3773 Op->VectorList.Count = Count;
3774 Op->VectorList.LaneIndex = Index;
3775 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3776 Op->StartLoc = S;
3777 Op->EndLoc = E;
3778 return Op;
3779 }
3780
3781 static std::unique_ptr<ARMOperand>
3782 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3783 auto Op = std::make_unique<ARMOperand>(k_VectorIndex);
3784 Op->VectorIndex.Val = Idx;
3785 Op->StartLoc = S;
3786 Op->EndLoc = E;
3787 return Op;
3788 }
3789
3790 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3791 SMLoc E) {
3792 auto Op = std::make_unique<ARMOperand>(k_Immediate);
3793 Op->Imm.Val = Val;
3794 Op->StartLoc = S;
3795 Op->EndLoc = E;
3796 return Op;
3797 }
3798
3799 static std::unique_ptr<ARMOperand>
3800 CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
3801 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3802 bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3803 auto Op = std::make_unique<ARMOperand>(k_Memory);
3804 Op->Memory.BaseRegNum = BaseRegNum;
3805 Op->Memory.OffsetImm = OffsetImm;
3806 Op->Memory.OffsetRegNum = OffsetRegNum;
3807 Op->Memory.ShiftType = ShiftType;
3808 Op->Memory.ShiftImm = ShiftImm;
3809 Op->Memory.Alignment = Alignment;
3810 Op->Memory.isNegative = isNegative;
3811 Op->StartLoc = S;
3812 Op->EndLoc = E;
3813 Op->AlignmentLoc = AlignmentLoc;
3814 return Op;
3815 }
3816
3817 static std::unique_ptr<ARMOperand>
3818 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3819 unsigned ShiftImm, SMLoc S, SMLoc E) {
3820 auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister);
3821 Op->PostIdxReg.RegNum = RegNum;
3822 Op->PostIdxReg.isAdd = isAdd;
3823 Op->PostIdxReg.ShiftTy = ShiftTy;
3824 Op->PostIdxReg.ShiftImm = ShiftImm;
3825 Op->StartLoc = S;
3826 Op->EndLoc = E;
3827 return Op;
3828 }
3829
3830 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3831 SMLoc S) {
3832 auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt);
3833 Op->MBOpt.Val = Opt;
3834 Op->StartLoc = S;
3835 Op->EndLoc = S;
3836 return Op;
3837 }
3838
3839 static std::unique_ptr<ARMOperand>
3840 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3841 auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3842 Op->ISBOpt.Val = Opt;
3843 Op->StartLoc = S;
3844 Op->EndLoc = S;
3845 return Op;
3846 }
3847
3848 static std::unique_ptr<ARMOperand>
3849 CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3850 auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3851 Op->TSBOpt.Val = Opt;
3852 Op->StartLoc = S;
3853 Op->EndLoc = S;
3854 return Op;
3855 }
3856
3857 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3858 SMLoc S) {
3859 auto Op = std::make_unique<ARMOperand>(k_ProcIFlags);
3860 Op->IFlags.Val = IFlags;
3861 Op->StartLoc = S;
3862 Op->EndLoc = S;
3863 return Op;
3864 }
3865
3866 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3867 auto Op = std::make_unique<ARMOperand>(k_MSRMask);
3868 Op->MMask.Val = MMask;
3869 Op->StartLoc = S;
3870 Op->EndLoc = S;
3871 return Op;
3872 }
3873
3874 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3875 auto Op = std::make_unique<ARMOperand>(k_BankedReg);
3876 Op->BankedReg.Val = Reg;
3877 Op->StartLoc = S;
3878 Op->EndLoc = S;
3879 return Op;
3880 }
3881};
3882
3883} // end anonymous namespace.
3884
3885void ARMOperand::print(raw_ostream &OS) const {
3886 auto RegName = [](unsigned Reg) {
3887 if (Reg)
3888 return ARMInstPrinter::getRegisterName(Reg);
3889 else
3890 return "noreg";
3891 };
3892
3893 switch (Kind) {
3894 case k_CondCode:
3895 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3896 break;
3897 case k_VPTPred:
3898 OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3899 break;
3900 case k_CCOut:
3901 OS << "<ccout " << RegName(getReg()) << ">";
3902 break;
3903 case k_ITCondMask: {
3904 static const char *const MaskStr[] = {
3905 "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3906 "(tt)", "(ttet)", "(tte)", "(ttee)",
3907 "(t)", "(tett)", "(tet)", "(tete)",
3908 "(te)", "(teet)", "(tee)", "(teee)",
3909 };
3910 assert((ITMask.Mask & 0xf) == ITMask.Mask)(static_cast <bool> ((ITMask.Mask & 0xf) == ITMask.
Mask) ? void (0) : __assert_fail ("(ITMask.Mask & 0xf) == ITMask.Mask"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3910, __extension__
__PRETTY_FUNCTION__))
;
3911 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3912 break;
3913 }
3914 case k_CoprocNum:
3915 OS << "<coprocessor number: " << getCoproc() << ">";
3916 break;
3917 case k_CoprocReg:
3918 OS << "<coprocessor register: " << getCoproc() << ">";
3919 break;
3920 case k_CoprocOption:
3921 OS << "<coprocessor option: " << CoprocOption.Val << ">";
3922 break;
3923 case k_MSRMask:
3924 OS << "<mask: " << getMSRMask() << ">";
3925 break;
3926 case k_BankedReg:
3927 OS << "<banked reg: " << getBankedReg() << ">";
3928 break;
3929 case k_Immediate:
3930 OS << *getImm();
3931 break;
3932 case k_MemBarrierOpt:
3933 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3934 break;
3935 case k_InstSyncBarrierOpt:
3936 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3937 break;
3938 case k_TraceSyncBarrierOpt:
3939 OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3940 break;
3941 case k_Memory:
3942 OS << "<memory";
3943 if (Memory.BaseRegNum)
3944 OS << " base:" << RegName(Memory.BaseRegNum);
3945 if (Memory.OffsetImm)
3946 OS << " offset-imm:" << *Memory.OffsetImm;
3947 if (Memory.OffsetRegNum)
3948 OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3949 << RegName(Memory.OffsetRegNum);
3950 if (Memory.ShiftType != ARM_AM::no_shift) {
3951 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3952 OS << " shift-imm:" << Memory.ShiftImm;
3953 }
3954 if (Memory.Alignment)
3955 OS << " alignment:" << Memory.Alignment;
3956 OS << ">";
3957 break;
3958 case k_PostIndexRegister:
3959 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3960 << RegName(PostIdxReg.RegNum);
3961 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3962 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3963 << PostIdxReg.ShiftImm;
3964 OS << ">";
3965 break;
3966 case k_ProcIFlags: {
3967 OS << "<ARM_PROC::";
3968 unsigned IFlags = getProcIFlags();
3969 for (int i=2; i >= 0; --i)
3970 if (IFlags & (1 << i))
3971 OS << ARM_PROC::IFlagsToString(1 << i);
3972 OS << ">";
3973 break;
3974 }
3975 case k_Register:
3976 OS << "<register " << RegName(getReg()) << ">";
3977 break;
3978 case k_ShifterImmediate:
3979 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3980 << " #" << ShifterImm.Imm << ">";
3981 break;
3982 case k_ShiftedRegister:
3983 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3984 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3985 << RegName(RegShiftedReg.ShiftReg) << ">";
3986 break;
3987 case k_ShiftedImmediate:
3988 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3989 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3990 << RegShiftedImm.ShiftImm << ">";
3991 break;
3992 case k_RotateImmediate:
3993 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3994 break;
3995 case k_ModifiedImmediate:
3996 OS << "<mod_imm #" << ModImm.Bits << ", #"
3997 << ModImm.Rot << ")>";
3998 break;
3999 case k_ConstantPoolImmediate:
4000 OS << "<constant_pool_imm #" << *getConstantPoolImm();
4001 break;
4002 case k_BitfieldDescriptor:
4003 OS << "<bitfield " << "lsb: " << Bitfield.LSB
4004 << ", width: " << Bitfield.Width << ">";
4005 break;
4006 case k_RegisterList:
4007 case k_RegisterListWithAPSR:
4008 case k_DPRRegisterList:
4009 case k_SPRRegisterList:
4010 case k_FPSRegisterListWithVPR:
4011 case k_FPDRegisterListWithVPR: {
4012 OS << "<register_list ";
4013
4014 const SmallVectorImpl<unsigned> &RegList = getRegList();
4015 for (SmallVectorImpl<unsigned>::const_iterator
4016 I = RegList.begin(), E = RegList.end(); I != E; ) {
4017 OS << RegName(*I);
4018 if (++I < E) OS << ", ";
4019 }
4020
4021 OS << ">";
4022 break;
4023 }
4024 case k_VectorList:
4025 OS << "<vector_list " << VectorList.Count << " * "
4026 << RegName(VectorList.RegNum) << ">";
4027 break;
4028 case k_VectorListAllLanes:
4029 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
4030 << RegName(VectorList.RegNum) << ">";
4031 break;
4032 case k_VectorListIndexed:
4033 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
4034 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
4035 break;
4036 case k_Token:
4037 OS << "'" << getToken() << "'";
4038 break;
4039 case k_VectorIndex:
4040 OS << "<vectorindex " << getVectorIndex() << ">";
4041 break;
4042 }
4043}
4044
4045/// @name Auto-generated Match Functions
4046/// {
4047
4048static unsigned MatchRegisterName(StringRef Name);
4049
4050/// }
4051
4052bool ARMAsmParser::ParseRegister(unsigned &RegNo,
4053 SMLoc &StartLoc, SMLoc &EndLoc) {
4054 const AsmToken &Tok = getParser().getTok();
4055 StartLoc = Tok.getLoc();
4056 EndLoc = Tok.getEndLoc();
4057 RegNo = tryParseRegister();
4058
4059 return (RegNo == (unsigned)-1);
4060}
4061
4062OperandMatchResultTy ARMAsmParser::tryParseRegister(unsigned &RegNo,
4063 SMLoc &StartLoc,
4064 SMLoc &EndLoc) {
4065 if (ParseRegister(RegNo, StartLoc, EndLoc))
4066 return MatchOperand_NoMatch;
4067 return MatchOperand_Success;
4068}
4069
4070/// Try to parse a register name. The token must be an Identifier when called,
4071/// and if it is a register name the token is eaten and the register number is
4072/// returned. Otherwise return -1.
4073int ARMAsmParser::tryParseRegister() {
4074 MCAsmParser &Parser = getParser();
4075 const AsmToken &Tok = Parser.getTok();
4076 if (Tok.isNot(AsmToken::Identifier)) return -1;
4077
4078 std::string lowerCase = Tok.getString().lower();
4079 unsigned RegNum = MatchRegisterName(lowerCase);
4080 if (!RegNum) {
4081 RegNum = StringSwitch<unsigned>(lowerCase)
4082 .Case("r13", ARM::SP)
4083 .Case("r14", ARM::LR)
4084 .Case("r15", ARM::PC)
4085 .Case("ip", ARM::R12)
4086 // Additional register name aliases for 'gas' compatibility.
4087 .Case("a1", ARM::R0)
4088 .Case("a2", ARM::R1)
4089 .Case("a3", ARM::R2)
4090 .Case("a4", ARM::R3)
4091 .Case("v1", ARM::R4)
4092 .Case("v2", ARM::R5)
4093 .Case("v3", ARM::R6)
4094 .Case("v4", ARM::R7)
4095 .Case("v5", ARM::R8)
4096 .Case("v6", ARM::R9)
4097 .Case("v7", ARM::R10)
4098 .Case("v8", ARM::R11)
4099 .Case("sb", ARM::R9)
4100 .Case("sl", ARM::R10)
4101 .Case("fp", ARM::R11)
4102 .Default(0);
4103 }
4104 if (!RegNum) {
4105 // Check for aliases registered via .req. Canonicalize to lower case.
4106 // That's more consistent since register names are case insensitive, and
4107 // it's how the original entry was passed in from MC/MCParser/AsmParser.
4108 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
4109 // If no match, return failure.
4110 if (Entry == RegisterReqs.end())
4111 return -1;
4112 Parser.Lex(); // Eat identifier token.
4113 return Entry->getValue();
4114 }
4115
4116 // Some FPUs only have 16 D registers, so D16-D31 are invalid
4117 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
4118 return -1;
4119
4120 Parser.Lex(); // Eat identifier token.
4121
4122 return RegNum;
4123}
4124
4125// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
4126// If a recoverable error occurs, return 1. If an irrecoverable error
4127// occurs, return -1. An irrecoverable error is one where tokens have been
4128// consumed in the process of trying to parse the shifter (i.e., when it is
4129// indeed a shifter operand, but malformed).
4130int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4131 MCAsmParser &Parser = getParser();
4132 SMLoc S = Parser.getTok().getLoc();
4133 const AsmToken &Tok = Parser.getTok();
4134 if (Tok.isNot(AsmToken::Identifier))
4135 return -1;
4136
4137 std::string lowerCase = Tok.getString().lower();
4138 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
4139 .Case("asl", ARM_AM::lsl)
4140 .Case("lsl", ARM_AM::lsl)
4141 .Case("lsr", ARM_AM::lsr)
4142 .Case("asr", ARM_AM::asr)
4143 .Case("ror", ARM_AM::ror)
4144 .Case("rrx", ARM_AM::rrx)
4145 .Default(ARM_AM::no_shift);
4146
4147 if (ShiftTy == ARM_AM::no_shift)
4148 return 1;
4149
4150 Parser.Lex(); // Eat the operator.
4151
4152 // The source register for the shift has already been added to the
4153 // operand list, so we need to pop it off and combine it into the shifted
4154 // register operand instead.
4155 std::unique_ptr<ARMOperand> PrevOp(
4156 (ARMOperand *)Operands.pop_back_val().release());
4157 if (!PrevOp->isReg())
4158 return Error(PrevOp->getStartLoc(), "shift must be of a register");
4159 int SrcReg = PrevOp->getReg();
4160
4161 SMLoc EndLoc;
4162 int64_t Imm = 0;
4163 int ShiftReg = 0;
4164 if (ShiftTy == ARM_AM::rrx) {
4165 // RRX Doesn't have an explicit shift amount. The encoder expects
4166 // the shift register to be the same as the source register. Seems odd,
4167 // but OK.
4168 ShiftReg = SrcReg;
4169 } else {
4170 // Figure out if this is shifted by a constant or a register (for non-RRX).
4171 if (Parser.getTok().is(AsmToken::Hash) ||
4172 Parser.getTok().is(AsmToken::Dollar)) {
4173 Parser.Lex(); // Eat hash.
4174 SMLoc ImmLoc = Parser.getTok().getLoc();
4175 const MCExpr *ShiftExpr = nullptr;
4176 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
4177 Error(ImmLoc, "invalid immediate shift value");
4178 return -1;
4179 }
4180 // The expression must be evaluatable as an immediate.
4181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4182 if (!CE) {
4183 Error(ImmLoc, "invalid immediate shift value");
4184 return -1;
4185 }
4186 // Range check the immediate.
4187 // lsl, ror: 0 <= imm <= 31
4188 // lsr, asr: 0 <= imm <= 32
4189 Imm = CE->getValue();
4190 if (Imm < 0 ||
4191 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4192 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4193 Error(ImmLoc, "immediate shift value out of range");
4194 return -1;
4195 }
4196 // shift by zero is a nop. Always send it through as lsl.
4197 // ('as' compatibility)
4198 if (Imm == 0)
4199 ShiftTy = ARM_AM::lsl;
4200 } else if (Parser.getTok().is(AsmToken::Identifier)) {
4201 SMLoc L = Parser.getTok().getLoc();
4202 EndLoc = Parser.getTok().getEndLoc();
4203 ShiftReg = tryParseRegister();
4204 if (ShiftReg == -1) {
4205 Error(L, "expected immediate or register in shift operand");
4206 return -1;
4207 }
4208 } else {
4209 Error(Parser.getTok().getLoc(),
4210 "expected immediate or register in shift operand");
4211 return -1;
4212 }
4213 }
4214
4215 if (ShiftReg && ShiftTy != ARM_AM::rrx)
4216 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4217 ShiftReg, Imm,
4218 S, EndLoc));
4219 else
4220 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4221 S, EndLoc));
4222
4223 return 0;
4224}
4225
4226/// Try to parse a register name. The token must be an Identifier when called.
4227/// If it's a register, an AsmOperand is created. Another AsmOperand is created
4228/// if there is a "writeback". 'true' if it's not a register.
4229///
4230/// TODO this is likely to change to allow different register types and or to
4231/// parse for a specific register type.
4232bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4233 MCAsmParser &Parser = getParser();
4234 SMLoc RegStartLoc = Parser.getTok().getLoc();
4235 SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4236 int RegNo = tryParseRegister();
4237 if (RegNo == -1)
4238 return true;
4239
4240 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4241
4242 const AsmToken &ExclaimTok = Parser.getTok();
4243 if (ExclaimTok.is(AsmToken::Exclaim)) {
4244 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4245 ExclaimTok.getLoc()));
4246 Parser.Lex(); // Eat exclaim token
4247 return false;
4248 }
4249
4250 // Also check for an index operand. This is only legal for vector registers,
4251 // but that'll get caught OK in operand matching, so we don't need to
4252 // explicitly filter everything else out here.
4253 if (Parser.getTok().is(AsmToken::LBrac)) {
4254 SMLoc SIdx = Parser.getTok().getLoc();
4255 Parser.Lex(); // Eat left bracket token.
4256
4257 const MCExpr *ImmVal;
4258 if (getParser().parseExpression(ImmVal))
4259 return true;
4260 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4261 if (!MCE)
4262 return TokError("immediate value expected for vector index");
4263
4264 if (Parser.getTok().isNot(AsmToken::RBrac))
4265 return Error(Parser.getTok().getLoc(), "']' expected");
4266
4267 SMLoc E = Parser.getTok().getEndLoc();
4268 Parser.Lex(); // Eat right bracket token.
4269
4270 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4271 SIdx, E,
4272 getContext()));
4273 }
4274
4275 return false;
4276}
4277
4278/// MatchCoprocessorOperandName - Try to parse an coprocessor related
4279/// instruction with a symbolic operand name.
4280/// We accept "crN" syntax for GAS compatibility.
4281/// <operand-name> ::= <prefix><number>
4282/// If CoprocOp is 'c', then:
4283/// <prefix> ::= c | cr
4284/// If CoprocOp is 'p', then :
4285/// <prefix> ::= p
4286/// <number> ::= integer in range [0, 15]
4287static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4288 // Use the same layout as the tablegen'erated register name matcher. Ugly,
4289 // but efficient.
4290 if (Name.size() < 2 || Name[0] != CoprocOp)
4291 return -1;
4292 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4293
4294 switch (Name.size()) {
4295 default: return -1;
4296 case 1:
4297 switch (Name[0]) {
4298 default: return -1;
4299 case '0': return 0;
4300 case '1': return 1;
4301 case '2': return 2;
4302 case '3': return 3;
4303 case '4': return 4;
4304 case '5': return 5;
4305 case '6': return 6;
4306 case '7': return 7;
4307 case '8': return 8;
4308 case '9': return 9;
4309 }
4310 case 2:
4311 if (Name[0] != '1')
4312 return -1;
4313 switch (Name[1]) {
4314 default: return -1;
4315 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4316 // However, old cores (v5/v6) did use them in that way.
4317 case '0': return 10;
4318 case '1': return 11;
4319 case '2': return 12;
4320 case '3': return 13;
4321 case '4': return 14;
4322 case '5': return 15;
4323 }
4324 }
4325}
4326
4327/// parseITCondCode - Try to parse a condition code for an IT instruction.
4328OperandMatchResultTy
4329ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4330 MCAsmParser &Parser = getParser();
4331 SMLoc S = Parser.getTok().getLoc();
4332 const AsmToken &Tok = Parser.getTok();
4333 if (!Tok.is(AsmToken::Identifier))
4334 return MatchOperand_NoMatch;
4335 unsigned CC = ARMCondCodeFromString(Tok.getString());
4336 if (CC == ~0U)
4337 return MatchOperand_NoMatch;
4338 Parser.Lex(); // Eat the token.
4339
4340 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4341
4342 return MatchOperand_Success;
4343}
4344
4345/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4346/// token must be an Identifier when called, and if it is a coprocessor
4347/// number, the token is eaten and the operand is added to the operand list.
4348OperandMatchResultTy
4349ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4350 MCAsmParser &Parser = getParser();
4351 SMLoc S = Parser.getTok().getLoc();
4352 const AsmToken &Tok = Parser.getTok();
4353 if (Tok.isNot(AsmToken::Identifier))
4354 return MatchOperand_NoMatch;
4355
4356 int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4357 if (Num == -1)
4358 return MatchOperand_NoMatch;
4359 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4360 return MatchOperand_NoMatch;
4361
4362 Parser.Lex(); // Eat identifier token.
4363 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4364 return MatchOperand_Success;
4365}
4366
4367/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4368/// token must be an Identifier when called, and if it is a coprocessor
4369/// number, the token is eaten and the operand is added to the operand list.
4370OperandMatchResultTy
4371ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4372 MCAsmParser &Parser = getParser();
4373 SMLoc S = Parser.getTok().getLoc();
4374 const AsmToken &Tok = Parser.getTok();
4375 if (Tok.isNot(AsmToken::Identifier))
4376 return MatchOperand_NoMatch;
4377
4378 int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4379 if (Reg == -1)
4380 return MatchOperand_NoMatch;
4381
4382 Parser.Lex(); // Eat identifier token.
4383 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4384 return MatchOperand_Success;
4385}
4386
4387/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4388/// coproc_option : '{' imm0_255 '}'
4389OperandMatchResultTy
4390ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4391 MCAsmParser &Parser = getParser();
4392 SMLoc S = Parser.getTok().getLoc();
4393
4394 // If this isn't a '{', this isn't a coprocessor immediate operand.
4395 if (Parser.getTok().isNot(AsmToken::LCurly))
4396 return MatchOperand_NoMatch;
4397 Parser.Lex(); // Eat the '{'
4398
4399 const MCExpr *Expr;
4400 SMLoc Loc = Parser.getTok().getLoc();
4401 if (getParser().parseExpression(Expr)) {
4402 Error(Loc, "illegal expression");
4403 return MatchOperand_ParseFail;
4404 }
4405 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4406 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4407 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4408 return MatchOperand_ParseFail;
4409 }
4410 int Val = CE->getValue();
4411
4412 // Check for and consume the closing '}'
4413 if (Parser.getTok().isNot(AsmToken::RCurly))
4414 return MatchOperand_ParseFail;
4415 SMLoc E = Parser.getTok().getEndLoc();
4416 Parser.Lex(); // Eat the '}'
4417
4418 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4419 return MatchOperand_Success;
4420}
4421
4422// For register list parsing, we need to map from raw GPR register numbering
4423// to the enumeration values. The enumeration values aren't sorted by
4424// register number due to our using "sp", "lr" and "pc" as canonical names.
4425static unsigned getNextRegister(unsigned Reg) {
4426 // If this is a GPR, we need to do it manually, otherwise we can rely
4427 // on the sort ordering of the enumeration since the other reg-classes
4428 // are sane.
4429 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4430 return Reg + 1;
4431 switch(Reg) {
4432 default: llvm_unreachable("Invalid GPR number!")::llvm::llvm_unreachable_internal("Invalid GPR number!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 4432)
;
4433 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4434 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4435 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
4436 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
4437 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
4438 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4439 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4440 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
4441 }
4442}
4443
4444// Insert an <Encoding, Register> pair in an ordered vector. Return true on
4445// success, or false, if duplicate encoding found.
4446static bool
4447insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4448 unsigned Enc, unsigned Reg) {
4449 Regs.emplace_back(Enc, Reg);
4450 for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4451 if (J->first == Enc) {
4452 Regs.erase(J.base());
4453 return false;
4454 }
4455 if (J->first < Enc)
4456 break;
4457 std::swap(*I, *J);
4458 }
4459 return true;
4460}
4461
4462/// Parse a register list.
4463bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
4464 bool AllowRAAC) {
4465 MCAsmParser &Parser = getParser();
4466 if (Parser.getTok().isNot(AsmToken::LCurly))
4467 return TokError("Token is not a Left Curly Brace");
4468 SMLoc S = Parser.getTok().getLoc();
4469 Parser.Lex(); // Eat '{' token.
4470 SMLoc RegLoc = Parser.getTok().getLoc();
4471
4472 // Check the first register in the list to see what register class
4473 // this is a list of.
4474 int Reg = tryParseRegister();
4475 if (Reg == -1)
4476 return Error(RegLoc, "register expected");
4477 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4478 return Error(RegLoc, "pseudo-register not allowed");
4479 // The reglist instructions have at most 16 registers, so reserve
4480 // space for that many.
4481 int EReg = 0;
4482 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4483
4484 // Allow Q regs and just interpret them as the two D sub-registers.
4485 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4486 Reg = getDRegFromQReg(Reg);
4487 EReg = MRI->getEncodingValue(Reg);
4488 Registers.emplace_back(EReg, Reg);
4489 ++Reg;
4490 }
4491 const MCRegisterClass *RC;
4492 if (Reg == ARM::RA_AUTH_CODE ||
4493 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4494 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4495 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4496 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4497 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4498 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4499 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4500 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4501 else
4502 return Error(RegLoc, "invalid register in register list");
4503
4504 // Store the register.
4505 EReg = MRI->getEncodingValue(Reg);
4506 Registers.emplace_back(EReg, Reg);
4507
4508 // This starts immediately after the first register token in the list,
4509 // so we can see either a comma or a minus (range separator) as a legal
4510 // next token.
4511 while (Parser.getTok().is(AsmToken::Comma) ||
4512 Parser.getTok().is(AsmToken::Minus)) {
4513 if (Parser.getTok().is(AsmToken::Minus)) {
4514 if (Reg == ARM::RA_AUTH_CODE)
4515 return Error(RegLoc, "pseudo-register not allowed");
4516 Parser.Lex(); // Eat the minus.
4517 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4518 int EndReg = tryParseRegister();
4519 if (EndReg == -1)
4520 return Error(AfterMinusLoc, "register expected");
4521 if (EndReg == ARM::RA_AUTH_CODE)
4522 return Error(AfterMinusLoc, "pseudo-register not allowed");
4523 // Allow Q regs and just interpret them as the two D sub-registers.
4524 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4525 EndReg = getDRegFromQReg(EndReg) + 1;
4526 // If the register is the same as the start reg, there's nothing
4527 // more to do.
4528 if (Reg == EndReg)
4529 continue;
4530 // The register must be in the same register class as the first.
4531 if (!RC->contains(Reg))
4532 return Error(AfterMinusLoc, "invalid register in register list");
4533 // Ranges must go from low to high.
4534 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4535 return Error(AfterMinusLoc, "bad range in register list");
4536
4537 // Add all the registers in the range to the register list.
4538 while (Reg != EndReg) {
4539 Reg = getNextRegister(Reg);
4540 EReg = MRI->getEncodingValue(Reg);
4541 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4542 Warning(AfterMinusLoc, StringRef("duplicated register (") +
4543 ARMInstPrinter::getRegisterName(Reg) +
4544 ") in register list");
4545 }
4546 }
4547 continue;
4548 }
4549 Parser.Lex(); // Eat the comma.
4550 RegLoc = Parser.getTok().getLoc();
4551 int OldReg = Reg;
4552 const AsmToken RegTok = Parser.getTok();
4553 Reg = tryParseRegister();
4554 if (Reg == -1)
4555 return Error(RegLoc, "register expected");
4556 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4557 return Error(RegLoc, "pseudo-register not allowed");
4558 // Allow Q regs and just interpret them as the two D sub-registers.
4559 bool isQReg = false;
4560 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4561 Reg = getDRegFromQReg(Reg);
4562 isQReg = true;
4563 }
4564 if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) &&
4565 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4566 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4567 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4568 // subset of GPRRegClassId except it contains APSR as well.
4569 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4570 }
4571 if (Reg == ARM::VPR &&
4572 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4573 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4574 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4575 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4576 EReg = MRI->getEncodingValue(Reg);
4577 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4578 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4579 ") in register list");
4580 }
4581 continue;
4582 }
4583 // The register must be in the same register class as the first.
4584 if ((Reg == ARM::RA_AUTH_CODE &&
4585 RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) ||
4586 (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg)))
4587 return Error(RegLoc, "invalid register in register list");
4588 // In most cases, the list must be monotonically increasing. An
4589 // exception is CLRM, which is order-independent anyway, so
4590 // there's no potential for confusion if you write clrm {r2,r1}
4591 // instead of clrm {r1,r2}.
4592 if (EnforceOrder &&
4593 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4594 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4595 Warning(RegLoc, "register list not in ascending order");
4596 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4597 return Error(RegLoc, "register list not in ascending order");
4598 }
4599 // VFP register lists must also be contiguous.
4600 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4601 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4602 Reg != OldReg + 1)
4603 return Error(RegLoc, "non-contiguous register range");
4604 EReg = MRI->getEncodingValue(Reg);
4605 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4606 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4607 ") in register list");
4608 }
4609 if (isQReg) {
4610 EReg = MRI->getEncodingValue(++Reg);
4611 Registers.emplace_back(EReg, Reg);
4612 }
4613 }
4614
4615 if (Parser.getTok().isNot(AsmToken::RCurly))
4616 return Error(Parser.getTok().getLoc(), "'}' expected");
4617 SMLoc E = Parser.getTok().getEndLoc();
4618 Parser.Lex(); // Eat '}' token.
4619
4620 // Push the register list operand.
4621 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4622
4623 // The ARM system instruction variants for LDM/STM have a '^' token here.
4624 if (Parser.getTok().is(AsmToken::Caret)) {
4625 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4626 Parser.Lex(); // Eat '^' token.
4627 }
4628
4629 return false;
4630}
4631
4632// Helper function to parse the lane index for vector lists.
4633OperandMatchResultTy ARMAsmParser::
4634parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4635 MCAsmParser &Parser = getParser();
4636 Index = 0; // Always return a defined index value.
4637 if (Parser.getTok().is(AsmToken::LBrac)) {
4638 Parser.Lex(); // Eat the '['.
4639 if (Parser.getTok().is(AsmToken::RBrac)) {
4640 // "Dn[]" is the 'all lanes' syntax.
4641 LaneKind = AllLanes;
4642 EndLoc = Parser.getTok().getEndLoc();
4643 Parser.Lex(); // Eat the ']'.
4644 return MatchOperand_Success;
4645 }
4646
4647 // There's an optional '#' token here. Normally there wouldn't be, but
4648 // inline assemble puts one in, and it's friendly to accept that.
4649 if (Parser.getTok().is(AsmToken::Hash))
4650 Parser.Lex(); // Eat '#' or '$'.
4651
4652 const MCExpr *LaneIndex;
4653 SMLoc Loc = Parser.getTok().getLoc();
4654 if (getParser().parseExpression(LaneIndex)) {
4655 Error(Loc, "illegal expression");
4656 return MatchOperand_ParseFail;
4657 }
4658 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4659 if (!CE) {
4660 Error(Loc, "lane index must be empty or an integer");
4661 return MatchOperand_ParseFail;
4662 }
4663 if (Parser.getTok().isNot(AsmToken::RBrac)) {
4664 Error(Parser.getTok().getLoc(), "']' expected");
4665 return MatchOperand_ParseFail;
4666 }
4667 EndLoc = Parser.getTok().getEndLoc();
4668 Parser.Lex(); // Eat the ']'.
4669 int64_t Val = CE->getValue();
4670
4671 // FIXME: Make this range check context sensitive for .8, .16, .32.
4672 if (Val < 0 || Val > 7) {
4673 Error(Parser.getTok().getLoc(), "lane index out of range");
4674 return MatchOperand_ParseFail;
4675 }
4676 Index = Val;
4677 LaneKind = IndexedLane;
4678 return MatchOperand_Success;
4679 }
4680 LaneKind = NoLanes;
4681 return MatchOperand_Success;
4682}
4683
4684// parse a vector register list
4685OperandMatchResultTy
4686ARMAsmParser::parseVectorList(OperandVector &Operands) {
4687 MCAsmParser &Parser = getParser();
4688 VectorLaneTy LaneKind;
4689 unsigned LaneIndex;
4690 SMLoc S = Parser.getTok().getLoc();
4691 // As an extension (to match gas), support a plain D register or Q register
4692 // (without encosing curly braces) as a single or double entry list,
4693 // respectively.
4694 if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4695 SMLoc E = Parser.getTok().getEndLoc();
4696 int Reg = tryParseRegister();
4697 if (Reg == -1)
4698 return MatchOperand_NoMatch;
4699 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4700 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4701 if (Res != MatchOperand_Success)
4702 return Res;
4703 switch (LaneKind) {
4704 case NoLanes:
4705 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4706 break;
4707 case AllLanes:
4708 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4709 S, E));
4710 break;
4711 case IndexedLane:
4712 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4713 LaneIndex,
4714 false, S, E));
4715 break;
4716 }
4717 return MatchOperand_Success;
4718 }
4719 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4720 Reg = getDRegFromQReg(Reg);
4721 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4722 if (Res != MatchOperand_Success)
4723 return Res;
4724 switch (LaneKind) {
4725 case NoLanes:
4726 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4727 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4728 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4729 break;
4730 case AllLanes:
4731 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4732 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4733 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4734 S, E));
4735 break;
4736 case IndexedLane:
4737 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4738 LaneIndex,
4739 false, S, E));
4740 break;
4741 }
4742 return MatchOperand_Success;
4743 }
4744 Error(S, "vector register expected");
4745 return MatchOperand_ParseFail;
4746 }
4747
4748 if (Parser.getTok().isNot(AsmToken::LCurly))
4749 return MatchOperand_NoMatch;
4750
4751 Parser.Lex(); // Eat '{' token.
4752 SMLoc RegLoc = Parser.getTok().getLoc();
4753
4754 int Reg = tryParseRegister();
4755 if (Reg == -1) {
4756 Error(RegLoc, "register expected");
4757 return MatchOperand_ParseFail;
4758 }
4759 unsigned Count = 1;
4760 int Spacing = 0;
4761 unsigned FirstReg = Reg;
4762
4763 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4764 Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4765 return MatchOperand_ParseFail;
4766 }
4767 // The list is of D registers, but we also allow Q regs and just interpret
4768 // them as the two D sub-registers.
4769 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4770 FirstReg = Reg = getDRegFromQReg(Reg);
4771 Spacing = 1; // double-spacing requires explicit D registers, otherwise
4772 // it's ambiguous with four-register single spaced.
4773 ++Reg;
4774 ++Count;
4775 }
4776
4777 SMLoc E;
4778 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4779 return MatchOperand_ParseFail;
4780
4781 while (Parser.getTok().is(AsmToken::Comma) ||
4782 Parser.getTok().is(AsmToken::Minus)) {
4783 if (Parser.getTok().is(AsmToken::Minus)) {
4784 if (!Spacing)
4785 Spacing = 1; // Register range implies a single spaced list.
4786 else if (Spacing == 2) {
4787 Error(Parser.getTok().getLoc(),
4788 "sequential registers in double spaced list");
4789 return MatchOperand_ParseFail;
4790 }
4791 Parser.Lex(); // Eat the minus.
4792 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4793 int EndReg = tryParseRegister();
4794 if (EndReg == -1) {
4795 Error(AfterMinusLoc, "register expected");
4796 return MatchOperand_ParseFail;
4797 }
4798 // Allow Q regs and just interpret them as the two D sub-registers.
4799 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4800 EndReg = getDRegFromQReg(EndReg) + 1;
4801 // If the register is the same as the start reg, there's nothing
4802 // more to do.
4803 if (Reg == EndReg)
4804 continue;
4805 // The register must be in the same register class as the first.
4806 if ((hasMVE() &&
4807 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4808 (!hasMVE() &&
4809 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4810 Error(AfterMinusLoc, "invalid register in register list");
4811 return MatchOperand_ParseFail;
4812 }
4813 // Ranges must go from low to high.
4814 if (Reg > EndReg) {
4815 Error(AfterMinusLoc, "bad range in register list");
4816 return MatchOperand_ParseFail;
4817 }
4818 // Parse the lane specifier if present.
4819 VectorLaneTy NextLaneKind;
4820 unsigned NextLaneIndex;
4821 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4822 MatchOperand_Success)
4823 return MatchOperand_ParseFail;
4824 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4825 Error(AfterMinusLoc, "mismatched lane index in register list");
4826 return MatchOperand_ParseFail;
4827 }
4828
4829 // Add all the registers in the range to the register list.
4830 Count += EndReg - Reg;
4831 Reg = EndReg;
4832 continue;
4833 }
4834 Parser.Lex(); // Eat the comma.
4835 RegLoc = Parser.getTok().getLoc();
4836 int OldReg = Reg;
4837 Reg = tryParseRegister();
4838 if (Reg == -1) {
4839 Error(RegLoc, "register expected");
4840 return MatchOperand_ParseFail;
4841 }
4842
4843 if (hasMVE()) {
4844 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4845 Error(RegLoc, "vector register in range Q0-Q7 expected");
4846 return MatchOperand_ParseFail;
4847 }
4848 Spacing = 1;
4849 }
4850 // vector register lists must be contiguous.
4851 // It's OK to use the enumeration values directly here rather, as the
4852 // VFP register classes have the enum sorted properly.
4853 //
4854 // The list is of D registers, but we also allow Q regs and just interpret
4855 // them as the two D sub-registers.
4856 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4857 if (!Spacing)
4858 Spacing = 1; // Register range implies a single spaced list.
4859 else if (Spacing == 2) {
4860 Error(RegLoc,
4861 "invalid register in double-spaced list (must be 'D' register')");
4862 return MatchOperand_ParseFail;
4863 }
4864 Reg = getDRegFromQReg(Reg);
4865 if (Reg != OldReg + 1) {
4866 Error(RegLoc, "non-contiguous register range");
4867 return MatchOperand_ParseFail;
4868 }
4869 ++Reg;
4870 Count += 2;
4871 // Parse the lane specifier if present.
4872 VectorLaneTy NextLaneKind;
4873 unsigned NextLaneIndex;
4874 SMLoc LaneLoc = Parser.getTok().getLoc();
4875 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4876 MatchOperand_Success)
4877 return MatchOperand_ParseFail;
4878 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4879 Error(LaneLoc, "mismatched lane index in register list");
4880 return MatchOperand_ParseFail;
4881 }
4882 continue;
4883 }
4884 // Normal D register.
4885 // Figure out the register spacing (single or double) of the list if
4886 // we don't know it already.
4887 if (!Spacing)
4888 Spacing = 1 + (Reg == OldReg + 2);
4889
4890 // Just check that it's contiguous and keep going.
4891 if (Reg != OldReg + Spacing) {
4892 Error(RegLoc, "non-contiguous register range");
4893 return MatchOperand_ParseFail;
4894 }
4895 ++Count;
4896 // Parse the lane specifier if present.
4897 VectorLaneTy NextLaneKind;
4898 unsigned NextLaneIndex;
4899 SMLoc EndLoc = Parser.getTok().getLoc();
4900 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4901 return MatchOperand_ParseFail;
4902 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4903 Error(EndLoc, "mismatched lane index in register list");
4904 return MatchOperand_ParseFail;
4905 }
4906 }
4907
4908 if (Parser.getTok().isNot(AsmToken::RCurly)) {
4909 Error(Parser.getTok().getLoc(), "'}' expected");
4910 return MatchOperand_ParseFail;
4911 }
4912 E = Parser.getTok().getEndLoc();
4913 Parser.Lex(); // Eat '}' token.
4914
4915 switch (LaneKind) {
4916 case NoLanes:
4917 case AllLanes: {
4918 // Two-register operands have been converted to the
4919 // composite register classes.
4920 if (Count == 2 && !hasMVE()) {
4921 const MCRegisterClass *RC = (Spacing == 1) ?
4922 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4923 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4924 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4925 }
4926 auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4927 ARMOperand::CreateVectorListAllLanes);
4928 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4929 break;
4930 }
4931 case IndexedLane:
4932 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4933 LaneIndex,
4934 (Spacing == 2),
4935 S, E));
4936 break;
4937 }
4938 return MatchOperand_Success;
4939}
4940
4941/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4942OperandMatchResultTy
4943ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4944 MCAsmParser &Parser = getParser();
4945 SMLoc S = Parser.getTok().getLoc();
4946 const AsmToken &Tok = Parser.getTok();
4947 unsigned Opt;
4948
4949 if (Tok.is(AsmToken::Identifier)) {
4950 StringRef OptStr = Tok.getString();
4951
4952 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4953 .Case("sy", ARM_MB::SY)
4954 .Case("st", ARM_MB::ST)
4955 .Case("ld", ARM_MB::LD)
4956 .Case("sh", ARM_MB::ISH)
4957 .Case("ish", ARM_MB::ISH)
4958 .Case("shst", ARM_MB::ISHST)
4959 .Case("ishst", ARM_MB::ISHST)
4960 .Case("ishld", ARM_MB::ISHLD)
4961 .Case("nsh", ARM_MB::NSH)
4962 .Case("un", ARM_MB::NSH)
4963 .Case("nshst", ARM_MB::NSHST)
4964 .Case("nshld", ARM_MB::NSHLD)
4965 .Case("unst", ARM_MB::NSHST)
4966 .Case("osh", ARM_MB::OSH)
4967 .Case("oshst", ARM_MB::OSHST)
4968 .Case("oshld", ARM_MB::OSHLD)
4969 .Default(~0U);
4970
4971 // ishld, oshld, nshld and ld are only available from ARMv8.
4972 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4973 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4974 Opt = ~0U;
4975
4976 if (Opt == ~0U)
4977 return MatchOperand_NoMatch;
4978
4979 Parser.Lex(); // Eat identifier token.
4980 } else if (Tok.is(AsmToken::Hash) ||
4981 Tok.is(AsmToken::Dollar) ||
4982 Tok.is(AsmToken::Integer)) {
4983 if (Parser.getTok().isNot(AsmToken::Integer))
4984 Parser.Lex(); // Eat '#' or '$'.
4985 SMLoc Loc = Parser.getTok().getLoc();
4986
4987 const MCExpr *MemBarrierID;
4988 if (getParser().parseExpression(MemBarrierID)) {
4989 Error(Loc, "illegal expression");
4990 return MatchOperand_ParseFail;
4991 }
4992
4993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4994 if (!CE) {
4995 Error(Loc, "constant expression expected");
4996 return MatchOperand_ParseFail;
4997 }
4998
4999 int Val = CE->getValue();
5000 if (Val & ~0xf) {
5001 Error(Loc, "immediate value out of range");
5002 return MatchOperand_ParseFail;
5003 }
5004
5005 Opt = ARM_MB::RESERVED_0 + Val;
5006 } else
5007 return MatchOperand_ParseFail;
5008
5009 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
5010 return MatchOperand_Success;
5011}
5012
5013OperandMatchResultTy
5014ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
5015 MCAsmParser &Parser = getParser();
5016 SMLoc S = Parser.getTok().getLoc();
5017 const AsmToken &Tok = Parser.getTok();
5018
5019 if (Tok.isNot(AsmToken::Identifier))
5020 return MatchOperand_NoMatch;
5021
5022 if (!Tok.getString().equals_insensitive("csync"))
5023 return MatchOperand_NoMatch;
5024
5025 Parser.Lex(); // Eat identifier token.
5026
5027 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
5028 return MatchOperand_Success;
5029}
5030
5031/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
5032OperandMatchResultTy
5033ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
5034 MCAsmParser &Parser = getParser();
5035 SMLoc S = Parser.getTok().getLoc();
5036 const AsmToken &Tok = Parser.getTok();
5037 unsigned Opt;
5038
5039 if (Tok.is(AsmToken::Identifier)) {
5040 StringRef OptStr = Tok.getString();
5041
5042 if (OptStr.equals_insensitive("sy"))
5043 Opt = ARM_ISB::SY;
5044 else
5045 return MatchOperand_NoMatch;
5046
5047 Parser.Lex(); // Eat identifier token.
5048 } else if (Tok.is(AsmToken::Hash) ||
5049 Tok.is(AsmToken::Dollar) ||
5050 Tok.is(AsmToken::Integer)) {
5051 if (Parser.getTok().isNot(AsmToken::Integer))
5052 Parser.Lex(); // Eat '#' or '$'.
5053 SMLoc Loc = Parser.getTok().getLoc();
5054
5055 const MCExpr *ISBarrierID;
5056 if (getParser().parseExpression(ISBarrierID)) {
5057 Error(Loc, "illegal expression");
5058 return MatchOperand_ParseFail;
5059 }
5060
5061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
5062 if (!CE) {
5063 Error(Loc, "constant expression expected");
5064 return MatchOperand_ParseFail;
5065 }
5066
5067 int Val = CE->getValue();
5068 if (Val & ~0xf) {
5069 Error(Loc, "immediate value out of range");
5070 return MatchOperand_ParseFail;
5071 }
5072
5073 Opt = ARM_ISB::RESERVED_0 + Val;
5074 } else
5075 return MatchOperand_ParseFail;
5076
5077 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
5078 (ARM_ISB::InstSyncBOpt)Opt, S));
5079 return MatchOperand_Success;
5080}
5081
5082
5083/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
5084OperandMatchResultTy
5085ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
5086 MCAsmParser &Parser = getParser();
5087 SMLoc S = Parser.getTok().getLoc();
5088 const AsmToken &Tok = Parser.getTok();
5089 if (!Tok.is(AsmToken::Identifier))
5090 return MatchOperand_NoMatch;
5091 StringRef IFlagsStr = Tok.getString();
5092
5093 // An iflags string of "none" is interpreted to mean that none of the AIF
5094 // bits are set. Not a terribly useful instruction, but a valid encoding.
5095 unsigned IFlags = 0;
5096 if (IFlagsStr != "none") {
5097 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
5098 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
5099 .Case("a", ARM_PROC::A)
5100 .Case("i", ARM_PROC::I)
5101 .Case("f", ARM_PROC::F)
5102 .Default(~0U);
5103
5104 // If some specific iflag is already set, it means that some letter is
5105 // present more than once, this is not acceptable.
5106 if (Flag == ~0U || (IFlags & Flag))
5107 return MatchOperand_NoMatch;
5108
5109 IFlags |= Flag;
5110 }
5111 }
5112
5113 Parser.Lex(); // Eat identifier token.
5114 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
5115 return MatchOperand_Success;
5116}
5117
5118/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
5119OperandMatchResultTy
5120ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
5121 MCAsmParser &Parser = getParser();
5122 SMLoc S = Parser.getTok().getLoc();
5123 const AsmToken &Tok = Parser.getTok();
5124
5125 if (Tok.is(AsmToken::Integer)) {
5126 int64_t Val = Tok.getIntVal();
5127 if (Val > 255 || Val < 0) {
5128 return MatchOperand_NoMatch;
5129 }
5130 unsigned SYSmvalue = Val & 0xFF;
5131 Parser.Lex();
5132 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5133 return MatchOperand_Success;
5134 }
5135
5136 if (!Tok.is(AsmToken::Identifier))
5137 return MatchOperand_NoMatch;
5138 StringRef Mask = Tok.getString();
5139
5140 if (isMClass()) {
5141 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
5142 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
5143 return MatchOperand_NoMatch;
5144
5145 unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
5146
5147 Parser.Lex(); // Eat identifier token.
5148 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5149 return MatchOperand_Success;
5150 }
5151
5152 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5153 size_t Start = 0, Next = Mask.find('_');
5154 StringRef Flags = "";
5155 std::string SpecReg = Mask.slice(Start, Next).lower();
5156 if (Next != StringRef::npos)
5157 Flags = Mask.slice(Next+1, Mask.size());
5158
5159 // FlagsVal contains the complete mask:
5160 // 3-0: Mask
5161 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5162 unsigned FlagsVal = 0;
5163
5164 if (SpecReg == "apsr") {
5165 FlagsVal = StringSwitch<unsigned>(Flags)
5166 .Case("nzcvq", 0x8) // same as CPSR_f
5167 .Case("g", 0x4) // same as CPSR_s
5168 .Case("nzcvqg", 0xc) // same as CPSR_fs
5169 .Default(~0U);
5170
5171 if (FlagsVal == ~0U) {
5172 if (!Flags.empty())
5173 return MatchOperand_NoMatch;
5174 else
5175 FlagsVal = 8; // No flag
5176 }
5177 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
5178 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
5179 if (Flags == "all" || Flags == "")
5180 Flags = "fc";
5181 for (int i = 0, e = Flags.size(); i != e; ++i) {
5182 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
5183 .Case("c", 1)
5184 .Case("x", 2)
5185 .Case("s", 4)
5186 .Case("f", 8)
5187 .Default(~0U);
5188
5189 // If some specific flag is already set, it means that some letter is
5190 // present more than once, this is not acceptable.
5191 if (Flag == ~0U || (FlagsVal & Flag))
5192 return MatchOperand_NoMatch;
5193 FlagsVal |= Flag;
5194 }
5195 } else // No match for special register.
5196 return MatchOperand_NoMatch;
5197
5198 // Special register without flags is NOT equivalent to "fc" flags.
5199 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
5200 // two lines would enable gas compatibility at the expense of breaking
5201 // round-tripping.
5202 //
5203 // if (!FlagsVal)
5204 // FlagsVal = 0x9;
5205
5206 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5207 if (SpecReg == "spsr")
5208 FlagsVal |= 16;
5209
5210 Parser.Lex(); // Eat identifier token.
5211 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
5212 return MatchOperand_Success;
5213}
5214
5215/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
5216/// use in the MRS/MSR instructions added to support virtualization.
5217OperandMatchResultTy
5218ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5219 MCAsmParser &Parser = getParser();
5220 SMLoc S = Parser.getTok().getLoc();
5221 const AsmToken &Tok = Parser.getTok();
5222 if (!Tok.is(AsmToken::Identifier))
5223 return MatchOperand_NoMatch;
5224 StringRef RegName = Tok.getString();
5225
5226 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5227 if (!TheReg)
5228 return MatchOperand_NoMatch;
5229 unsigned Encoding = TheReg->Encoding;
5230
5231 Parser.Lex(); // Eat identifier token.
5232 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5233 return MatchOperand_Success;
5234}
5235
5236OperandMatchResultTy
5237ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5238 int High) {
5239 MCAsmParser &Parser = getParser();
5240 const AsmToken &Tok = Parser.getTok();
5241 if (Tok.isNot(AsmToken::Identifier)) {
5242 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5243 return MatchOperand_ParseFail;
5244 }
5245 StringRef ShiftName = Tok.getString();
5246 std::string LowerOp = Op.lower();
5247 std::string UpperOp = Op.upper();
5248 if (ShiftName != LowerOp && ShiftName != UpperOp) {
5249 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5250 return MatchOperand_ParseFail;
5251 }
5252 Parser.Lex(); // Eat shift type token.
5253
5254 // There must be a '#' and a shift amount.
5255 if (Parser.getTok().isNot(AsmToken::Hash) &&
5256 Parser.getTok().isNot(AsmToken::Dollar)) {
5257 Error(Parser.getTok().getLoc(), "'#' expected");
5258 return MatchOperand_ParseFail;
5259 }
5260 Parser.Lex(); // Eat hash token.
5261
5262 const MCExpr *ShiftAmount;
5263 SMLoc Loc = Parser.getTok().getLoc();
5264 SMLoc EndLoc;
5265 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5266 Error(Loc, "illegal expression");
5267 return MatchOperand_ParseFail;
5268 }
5269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5270 if (!CE) {
5271 Error(Loc, "constant expression expected");
5272 return MatchOperand_ParseFail;
5273 }
5274 int Val = CE->getValue();
5275 if (Val < Low || Val > High) {
5276 Error(Loc, "immediate value out of range");
5277 return MatchOperand_ParseFail;
5278 }
5279
5280 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5281
5282 return MatchOperand_Success;
5283}
5284
5285OperandMatchResultTy
5286ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5287 MCAsmParser &Parser = getParser();
5288 const AsmToken &Tok = Parser.getTok();
5289 SMLoc S = Tok.getLoc();
5290 if (Tok.isNot(AsmToken::Identifier)) {
5291 Error(S, "'be' or 'le' operand expected");
5292 return MatchOperand_ParseFail;
5293 }
5294 int Val = StringSwitch<int>(Tok.getString().lower())
5295 .Case("be", 1)
5296 .Case("le", 0)
5297 .Default(-1);
5298 Parser.Lex(); // Eat the token.
5299
5300 if (Val == -1) {
5301 Error(S, "'be' or 'le' operand expected");
5302 return MatchOperand_ParseFail;
5303 }
5304 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5305 getContext()),
5306 S, Tok.getEndLoc()));
5307 return MatchOperand_Success;
5308}
5309
5310/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5311/// instructions. Legal values are:
5312/// lsl #n 'n' in [0,31]
5313/// asr #n 'n' in [1,32]
5314/// n == 32 encoded as n == 0.
5315OperandMatchResultTy
5316ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5317 MCAsmParser &Parser = getParser();
5318 const AsmToken &Tok = Parser.getTok();
5319 SMLoc S = Tok.getLoc();
5320 if (Tok.isNot(AsmToken::Identifier)) {
5321 Error(S, "shift operator 'asr' or 'lsl' expected");
5322 return MatchOperand_ParseFail;
5323 }
5324 StringRef ShiftName = Tok.getString();
5325 bool isASR;
5326 if (ShiftName == "lsl" || ShiftName == "LSL")
5327 isASR = false;
5328 else if (ShiftName == "asr" || ShiftName == "ASR")
5329 isASR = true;
5330 else {
5331 Error(S, "shift operator 'asr' or 'lsl' expected");
5332 return MatchOperand_ParseFail;
5333 }
5334 Parser.Lex(); // Eat the operator.
5335
5336 // A '#' and a shift amount.
5337 if (Parser.getTok().isNot(AsmToken::Hash) &&
5338 Parser.getTok().isNot(AsmToken::Dollar)) {
5339 Error(Parser.getTok().getLoc(), "'#' expected");
5340 return MatchOperand_ParseFail;
5341 }
5342 Parser.Lex(); // Eat hash token.
5343 SMLoc ExLoc = Parser.getTok().getLoc();
5344
5345 const MCExpr *ShiftAmount;
5346 SMLoc EndLoc;
5347 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5348 Error(ExLoc, "malformed shift expression");
5349 return MatchOperand_ParseFail;
5350 }
5351 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5352 if (!CE) {
5353 Error(ExLoc, "shift amount must be an immediate");
5354 return MatchOperand_ParseFail;
5355 }
5356
5357 int64_t Val = CE->getValue();
5358 if (isASR) {
5359 // Shift amount must be in [1,32]
5360 if (Val < 1 || Val > 32) {
5361 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5362 return MatchOperand_ParseFail;
5363 }
5364 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5365 if (isThumb() && Val == 32) {
5366 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5367 return MatchOperand_ParseFail;
5368 }
5369 if (Val == 32) Val = 0;
5370 } else {
5371 // Shift amount must be in [1,32]
5372 if (Val < 0 || Val > 31) {
5373 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5374 return MatchOperand_ParseFail;
5375 }
5376 }
5377
5378 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5379
5380 return MatchOperand_Success;
5381}
5382
5383/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5384/// of instructions. Legal values are:
5385/// ror #n 'n' in {0, 8, 16, 24}
5386OperandMatchResultTy
5387ARMAsmParser::parseRotImm(OperandVector &Operands) {
5388 MCAsmParser &Parser = getParser();
5389 const AsmToken &Tok = Parser.getTok();
5390 SMLoc S = Tok.getLoc();
5391 if (Tok.isNot(AsmToken::Identifier))
5392 return MatchOperand_NoMatch;
5393 StringRef ShiftName = Tok.getString();
5394 if (ShiftName != "ror" && ShiftName != "ROR")
5395 return MatchOperand_NoMatch;
5396 Parser.Lex(); // Eat the operator.
5397
5398 // A '#' and a rotate amount.
5399 if (Parser.getTok().isNot(AsmToken::Hash) &&
5400 Parser.getTok().isNot(AsmToken::Dollar)) {
5401 Error(Parser.getTok().getLoc(), "'#' expected");
5402 return MatchOperand_ParseFail;
5403 }
5404 Parser.Lex(); // Eat hash token.
5405 SMLoc ExLoc = Parser.getTok().getLoc();
5406
5407 const MCExpr *ShiftAmount;
5408 SMLoc EndLoc;
5409 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5410 Error(ExLoc, "malformed rotate expression");
5411 return MatchOperand_ParseFail;
5412 }
5413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5414 if (!CE) {
5415 Error(ExLoc, "rotate amount must be an immediate");
5416 return MatchOperand_ParseFail;
5417 }
5418
5419 int64_t Val = CE->getValue();
5420 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5421 // normally, zero is represented in asm by omitting the rotate operand
5422 // entirely.
5423 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5424 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5425 return MatchOperand_ParseFail;
5426 }
5427
5428 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5429
5430 return MatchOperand_Success;
5431}
5432
5433OperandMatchResultTy
5434ARMAsmParser::parseModImm(OperandVector &Operands) {
5435 MCAsmParser &Parser = getParser();
5436 MCAsmLexer &Lexer = getLexer();
5437 int64_t Imm1, Imm2;
5438
5439 SMLoc S = Parser.getTok().getLoc();
5440
5441 // 1) A mod_imm operand can appear in the place of a register name:
5442 // add r0, #mod_imm
5443 // add r0, r0, #mod_imm
5444 // to correctly handle the latter, we bail out as soon as we see an
5445 // identifier.
5446 //
5447 // 2) Similarly, we do not want to parse into complex operands:
5448 // mov r0, #mod_imm
5449 // mov r0, :lower16:(_foo)
5450 if (Parser.getTok().is(AsmToken::Identifier) ||
5451 Parser.getTok().is(AsmToken::Colon))
5452 return MatchOperand_NoMatch;
5453
5454 // Hash (dollar) is optional as per the ARMARM
5455 if (Parser.getTok().is(AsmToken::Hash) ||
5456 Parser.getTok().is(AsmToken::Dollar)) {
5457 // Avoid parsing into complex operands (#:)
5458 if (Lexer.peekTok().is(AsmToken::Colon))
5459 return MatchOperand_NoMatch;
5460
5461 // Eat the hash (dollar)
5462 Parser.Lex();
5463 }
5464
5465 SMLoc Sx1, Ex1;
5466 Sx1 = Parser.getTok().getLoc();
5467 const MCExpr *Imm1Exp;
5468 if (getParser().parseExpression(Imm1Exp, Ex1)) {
5469 Error(Sx1, "malformed expression");
5470 return MatchOperand_ParseFail;
5471 }
5472
5473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5474
5475 if (CE) {
5476 // Immediate must fit within 32-bits
5477 Imm1 = CE->getValue();
5478 int Enc = ARM_AM::getSOImmVal(Imm1);
5479 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5480 // We have a match!
5481 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5482 (Enc & 0xF00) >> 7,
5483 Sx1, Ex1));
5484 return MatchOperand_Success;
5485 }
5486
5487 // We have parsed an immediate which is not for us, fallback to a plain
5488 // immediate. This can happen for instruction aliases. For an example,
5489 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5490 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5491 // instruction with a mod_imm operand. The alias is defined such that the
5492 // parser method is shared, that's why we have to do this here.
5493 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5494 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5495 return MatchOperand_Success;
5496 }
5497 } else {
5498 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5499 // MCFixup). Fallback to a plain immediate.
5500 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5501 return MatchOperand_Success;
5502 }
5503
5504 // From this point onward, we expect the input to be a (#bits, #rot) pair
5505 if (Parser.getTok().isNot(AsmToken::Comma)) {
5506 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5507 return MatchOperand_ParseFail;
5508 }
5509
5510 if (Imm1 & ~0xFF) {
5511 Error(Sx1, "immediate operand must a number in the range [0, 255]");
5512 return MatchOperand_ParseFail;
5513 }
5514
5515 // Eat the comma
5516 Parser.Lex();
5517
5518 // Repeat for #rot
5519 SMLoc Sx2, Ex2;
5520 Sx2 = Parser.getTok().getLoc();
5521
5522 // Eat the optional hash (dollar)
5523 if (Parser.getTok().is(AsmToken::Hash) ||
5524 Parser.getTok().is(AsmToken::Dollar))
5525 Parser.Lex();
5526
5527 const MCExpr *Imm2Exp;
5528 if (getParser().parseExpression(Imm2Exp, Ex2)) {
5529 Error(Sx2, "malformed expression");
5530 return MatchOperand_ParseFail;
5531 }
5532
5533 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5534
5535 if (CE) {
5536 Imm2 = CE->getValue();
5537 if (!(Imm2 & ~0x1E)) {
5538 // We have a match!
5539 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5540 return MatchOperand_Success;
5541 }
5542 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5543 return MatchOperand_ParseFail;
5544 } else {
5545 Error(Sx2, "constant expression expected");
5546 return MatchOperand_ParseFail;
5547 }
5548}
5549
5550OperandMatchResultTy
5551ARMAsmParser::parseBitfield(OperandVector &Operands) {
5552 MCAsmParser &Parser = getParser();
5553 SMLoc S = Parser.getTok().getLoc();
5554 // The bitfield descriptor is really two operands, the LSB and the width.
5555 if (Parser.getTok().isNot(AsmToken::Hash) &&
5556 Parser.getTok().isNot(AsmToken::Dollar)) {
5557 Error(Parser.getTok().getLoc(), "'#' expected");
5558 return MatchOperand_ParseFail;
5559 }
5560 Parser.Lex(); // Eat hash token.
5561
5562 const MCExpr *LSBExpr;
5563 SMLoc E = Parser.getTok().getLoc();
5564 if (getParser().parseExpression(LSBExpr)) {
5565 Error(E, "malformed immediate expression");
5566 return MatchOperand_ParseFail;
5567 }
5568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5569 if (!CE) {
5570 Error(E, "'lsb' operand must be an immediate");
5571 return MatchOperand_ParseFail;
5572 }
5573
5574 int64_t LSB = CE->getValue();
5575 // The LSB must be in the range [0,31]
5576 if (LSB < 0 || LSB > 31) {
5577 Error(E, "'lsb' operand must be in the range [0,31]");
5578 return MatchOperand_ParseFail;
5579 }
5580 E = Parser.getTok().getLoc();
5581
5582 // Expect another immediate operand.
5583 if (Parser.getTok().isNot(AsmToken::Comma)) {
5584 Error(Parser.getTok().getLoc(), "too few operands");
5585 return MatchOperand_ParseFail;
5586 }
5587 Parser.Lex(); // Eat hash token.
5588 if (Parser.getTok().isNot(AsmToken::Hash) &&
5589 Parser.getTok().isNot(AsmToken::Dollar)) {
5590 Error(Parser.getTok().getLoc(), "'#' expected");
5591 return MatchOperand_ParseFail;
5592 }
5593 Parser.Lex(); // Eat hash token.
5594
5595 const MCExpr *WidthExpr;
5596 SMLoc EndLoc;
5597 if (getParser().parseExpression(WidthExpr, EndLoc)) {
5598 Error(E, "malformed immediate expression");
5599 return MatchOperand_ParseFail;
5600 }
5601 CE = dyn_cast<MCConstantExpr>(WidthExpr);
5602 if (!CE) {
5603 Error(E, "'width' operand must be an immediate");
5604 return MatchOperand_ParseFail;
5605 }
5606
5607 int64_t Width = CE->getValue();
5608 // The LSB must be in the range [1,32-lsb]
5609 if (Width < 1 || Width > 32 - LSB) {
5610 Error(E, "'width' operand must be in the range [1,32-lsb]");
5611 return MatchOperand_ParseFail;
5612 }
5613
5614 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
5615
5616 return MatchOperand_Success;
5617}
5618
5619OperandMatchResultTy
5620ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5621 // Check for a post-index addressing register operand. Specifically:
5622 // postidx_reg := '+' register {, shift}
5623 // | '-' register {, shift}
5624 // | register {, shift}
5625
5626 // This method must return MatchOperand_NoMatch without consuming any tokens
5627 // in the case where there is no match, as other alternatives take other
5628 // parse methods.
5629 MCAsmParser &Parser = getParser();
5630 AsmToken Tok = Parser.getTok();
5631 SMLoc S = Tok.getLoc();
5632 bool haveEaten = false;
5633 bool isAdd = true;
5634 if (Tok.is(AsmToken::Plus)) {
5635 Parser.Lex(); // Eat the '+' token.
5636 haveEaten = true;
5637 } else if (Tok.is(AsmToken::Minus)) {
5638 Parser.Lex(); // Eat the '-' token.
5639 isAdd = false;
5640 haveEaten = true;
5641 }
5642
5643 SMLoc E = Parser.getTok().getEndLoc();
5644 int Reg = tryParseRegister();
5645 if (Reg == -1) {
5646 if (!haveEaten)
5647 return MatchOperand_NoMatch;
5648 Error(Parser.getTok().getLoc(), "register expected");
5649 return MatchOperand_ParseFail;
5650 }
5651
5652 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5653 unsigned ShiftImm = 0;
5654 if (Parser.getTok().is(AsmToken::Comma)) {
5655 Parser.Lex(); // Eat the ','.
5656 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5657 return MatchOperand_ParseFail;
5658
5659 // FIXME: Only approximates end...may include intervening whitespace.
5660 E = Parser.getTok().getLoc();
5661 }
5662
5663 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
5664 ShiftImm, S, E));
5665
5666 return MatchOperand_Success;
5667}
5668
5669OperandMatchResultTy
5670ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5671 // Check for a post-index addressing register operand. Specifically:
5672 // am3offset := '+' register
5673 // | '-' register
5674 // | register
5675 // | # imm
5676 // | # + imm
5677 // | # - imm
5678
5679 // This method must return MatchOperand_NoMatch without consuming any tokens
5680 // in the case where there is no match, as other alternatives take other
5681 // parse methods.
5682 MCAsmParser &Parser = getParser();
5683 AsmToken Tok = Parser.getTok();
5684 SMLoc S = Tok.getLoc();
5685
5686 // Do immediates first, as we always parse those if we have a '#'.
5687 if (Parser.getTok().is(AsmToken::Hash) ||
5688 Parser.getTok().is(AsmToken::Dollar)) {
5689 Parser.Lex(); // Eat '#' or '$'.
5690 // Explicitly look for a '-', as we need to encode negative zero
5691 // differently.
5692 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5693 const MCExpr *Offset;
5694 SMLoc E;
5695 if (getParser().parseExpression(Offset, E))
5696 return MatchOperand_ParseFail;
5697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5698 if (!CE) {
5699 Error(S, "constant expression expected");
5700 return MatchOperand_ParseFail;
5701 }
5702 // Negative zero is encoded as the flag value
5703 // std::numeric_limits<int32_t>::min().
5704 int32_t Val = CE->getValue();
5705 if (isNegative && Val == 0)
5706 Val = std::numeric_limits<int32_t>::min();
5707
5708 Operands.push_back(
5709 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
5710
5711 return MatchOperand_Success;
5712 }
5713
5714 bool haveEaten = false;
5715 bool isAdd = true;
5716 if (Tok.is(AsmToken::Plus)) {
5717 Parser.Lex(); // Eat the '+' token.
5718 haveEaten = true;
5719 } else if (Tok.is(AsmToken::Minus)) {
5720 Parser.Lex(); // Eat the '-' token.
5721 isAdd = false;
5722 haveEaten = true;
5723 }
5724
5725 Tok = Parser.getTok();
5726 int Reg = tryParseRegister();
5727 if (Reg == -1) {
5728 if (!haveEaten)
5729 return MatchOperand_NoMatch;
5730 Error(Tok.getLoc(), "register expected");
5731 return MatchOperand_ParseFail;
5732 }
5733
5734 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5735 0, S, Tok.getEndLoc()));
5736
5737 return MatchOperand_Success;
5738}
5739
5740/// Convert parsed operands to MCInst. Needed here because this instruction
5741/// only has two register operands, but multiplication is commutative so
5742/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5743void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5744 const OperandVector &Operands) {
5745 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
5746 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
5747 // If we have a three-operand form, make sure to set Rn to be the operand
5748 // that isn't the same as Rd.
5749 unsigned RegOp = 4;
5750 if (Operands.size() == 6 &&
5751 ((ARMOperand &)*Operands[4]).getReg() ==
5752 ((ARMOperand &)*Operands[3]).getReg())
5753 RegOp = 5;
5754 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5755 Inst.addOperand(Inst.getOperand(0));
5756 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5757}
5758
5759void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5760 const OperandVector &Operands) {
5761 int CondOp = -1, ImmOp = -1;
5762 switch(Inst.getOpcode()) {
5763 case ARM::tB:
5764 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
5765
5766 case ARM::t2B:
5767 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5768
5769 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches")::llvm::llvm_unreachable_internal("Unexpected instruction in cvtThumbBranches"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 5769)
;
5770 }
5771 // first decide whether or not the branch should be conditional
5772 // by looking at it's location relative to an IT block
5773 if(inITBlock()) {
5774 // inside an IT block we cannot have any conditional branches. any
5775 // such instructions needs to be converted to unconditional form
5776 switch(Inst.getOpcode()) {
5777 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5778 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5779 }
5780 } else {
5781 // outside IT blocks we can only have unconditional branches with AL
5782 // condition code or conditional branches with non-AL condition code
5783 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5784 switch(Inst.getOpcode()) {
5785 case ARM::tB:
5786 case ARM::tBcc:
5787 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5788 break;
5789 case ARM::t2B:
5790 case ARM::t2Bcc:
5791 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5792 break;
5793 }
5794 }
5795
5796 // now decide on encoding size based on branch target range
5797 switch(Inst.getOpcode()) {
5798 // classify tB as either t2B or t1B based on range of immediate operand
5799 case ARM::tB: {
5800 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5801 if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5802 Inst.setOpcode(ARM::t2B);
5803 break;
5804 }
5805 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5806 case ARM::tBcc: {
5807 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5808 if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5809 Inst.setOpcode(ARM::t2Bcc);
5810 break;
5811 }
5812 }
5813 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5814 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5815}
5816
5817void ARMAsmParser::cvtMVEVMOVQtoDReg(
5818 MCInst &Inst, const OperandVector &Operands) {
5819
5820 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5821 assert(Operands.size() == 8)(static_cast <bool> (Operands.size() == 8) ? void (0) :
__assert_fail ("Operands.size() == 8", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 5821, __extension__ __PRETTY_FUNCTION__))
;
5822
5823 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
5824 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
5825 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
5826 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
5827 // skip second copy of Qd in Operands[6]
5828 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
5829 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
5830}
5831
5832/// Parse an ARM memory expression, return false if successful else return true
5833/// or an error. The first token must be a '[' when called.
5834bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5835 MCAsmParser &Parser = getParser();
5836 SMLoc S, E;
5837 if (Parser.getTok().isNot(AsmToken::LBrac))
5838 return TokError("Token is not a Left Bracket");
5839 S = Parser.getTok().getLoc();
5840 Parser.Lex(); // Eat left bracket token.
5841
5842 const AsmToken &BaseRegTok = Parser.getTok();
5843 int BaseRegNum = tryParseRegister();
5844 if (BaseRegNum == -1)
5845 return Error(BaseRegTok.getLoc(), "register expected");
5846
5847 // The next token must either be a comma, a colon or a closing bracket.
5848 const AsmToken &Tok = Parser.getTok();
5849 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5850 !Tok.is(AsmToken::RBrac))
5851 return Error(Tok.getLoc(), "malformed memory operand");
5852
5853 if (Tok.is(AsmToken::RBrac)) {
5854 E = Tok.getEndLoc();
5855 Parser.Lex(); // Eat right bracket token.
5856
5857 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5858 ARM_AM::no_shift, 0, 0, false,
5859 S, E));
5860
5861 // If there's a pre-indexing writeback marker, '!', just add it as a token
5862 // operand. It's rather odd, but syntactically valid.
5863 if (Parser.getTok().is(AsmToken::Exclaim)) {
5864 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5865 Parser.Lex(); // Eat the '!'.
5866 }
5867
5868 return false;
5869 }
5870
5871 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&(static_cast <bool> ((Tok.is(AsmToken::Colon) || Tok.is
(AsmToken::Comma)) && "Lost colon or comma in memory operand?!"
) ? void (0) : __assert_fail ("(Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && \"Lost colon or comma in memory operand?!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 5872, __extension__
__PRETTY_FUNCTION__))
5872 "Lost colon or comma in memory operand?!")(static_cast <bool> ((Tok.is(AsmToken::Colon) || Tok.is
(AsmToken::Comma)) && "Lost colon or comma in memory operand?!"
) ? void (0) : __assert_fail ("(Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && \"Lost colon or comma in memory operand?!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 5872, __extension__
__PRETTY_FUNCTION__))
;
5873 if (Tok.is(AsmToken::Comma)) {
5874 Parser.Lex(); // Eat the comma.
5875 }
5876
5877 // If we have a ':', it's an alignment specifier.
5878 if (Parser.getTok().is(AsmToken::Colon)) {
5879 Parser.Lex(); // Eat the ':'.
5880 E = Parser.getTok().getLoc();
5881 SMLoc AlignmentLoc = Tok.getLoc();
5882
5883 const MCExpr *Expr;
5884 if (getParser().parseExpression(Expr))
5885 return true;
5886
5887 // The expression has to be a constant. Memory references with relocations
5888 // don't come through here, as they use the <label> forms of the relevant
5889 // instructions.
5890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5891 if (!CE)
5892 return Error (E, "constant expression expected");
5893
5894 unsigned Align = 0;
5895 switch (CE->getValue()) {
5896 default:
5897 return Error(E,
5898 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5899 case 16: Align = 2; break;
5900 case 32: Align = 4; break;
5901 case 64: Align = 8; break;
5902 case 128: Align = 16; break;
5903 case 256: Align = 32; break;
5904 }
5905
5906 // Now we should have the closing ']'
5907 if (Parser.getTok().isNot(AsmToken::RBrac))
5908 return Error(Parser.getTok().getLoc(), "']' expected");
5909 E = Parser.getTok().getEndLoc();
5910 Parser.Lex(); // Eat right bracket token.
5911
5912 // Don't worry about range checking the value here. That's handled by
5913 // the is*() predicates.
5914 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5915 ARM_AM::no_shift, 0, Align,
5916 false, S, E, AlignmentLoc));
5917
5918 // If there's a pre-indexing writeback marker, '!', just add it as a token
5919 // operand.
5920 if (Parser.getTok().is(AsmToken::Exclaim)) {
5921 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5922 Parser.Lex(); // Eat the '!'.
5923 }
5924
5925 return false;
5926 }
5927
5928 // If we have a '#' or '$', it's an immediate offset, else assume it's a
5929 // register offset. Be friendly and also accept a plain integer or expression
5930 // (without a leading hash) for gas compatibility.
5931 if (Parser.getTok().is(AsmToken::Hash) ||
5932 Parser.getTok().is(AsmToken::Dollar) ||
5933 Parser.getTok().is(AsmToken::LParen) ||
5934 Parser.getTok().is(AsmToken::Integer)) {
5935 if (Parser.getTok().is(AsmToken::Hash) ||
5936 Parser.getTok().is(AsmToken::Dollar))
5937 Parser.Lex(); // Eat '#' or '$'
5938 E = Parser.getTok().getLoc();
5939
5940 bool isNegative = getParser().getTok().is(AsmToken::Minus);
5941 const MCExpr *Offset, *AdjustedOffset;
5942 if (getParser().parseExpression(Offset))
5943 return true;
5944
5945 if (const auto *CE = dyn_cast<MCConstantExpr>(Offset)) {
5946 // If the constant was #-0, represent it as
5947 // std::numeric_limits<int32_t>::min().
5948 int32_t Val = CE->getValue();
5949 if (isNegative && Val == 0)
5950 CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5951 getContext());
5952 // Don't worry about range checking the value here. That's handled by
5953 // the is*() predicates.
5954 AdjustedOffset = CE;
5955 } else
5956 AdjustedOffset = Offset;
5957 Operands.push_back(ARMOperand::CreateMem(
5958 BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E));
5959
5960 // Now we should have the closing ']'
5961 if (Parser.getTok().isNot(AsmToken::RBrac))
5962 return Error(Parser.getTok().getLoc(), "']' expected");
5963 E = Parser.getTok().getEndLoc();
5964 Parser.Lex(); // Eat right bracket token.
5965
5966 // If there's a pre-indexing writeback marker, '!', just add it as a token
5967 // operand.
5968 if (Parser.getTok().is(AsmToken::Exclaim)) {
5969 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5970 Parser.Lex(); // Eat the '!'.
5971 }
5972
5973 return false;
5974 }
5975
5976 // The register offset is optionally preceded by a '+' or '-'
5977 bool isNegative = false;
5978 if (Parser.getTok().is(AsmToken::Minus)) {
5979 isNegative = true;
5980 Parser.Lex(); // Eat the '-'.
5981 } else if (Parser.getTok().is(AsmToken::Plus)) {
5982 // Nothing to do.
5983 Parser.Lex(); // Eat the '+'.
5984 }
5985
5986 E = Parser.getTok().getLoc();
5987 int OffsetRegNum = tryParseRegister();
5988 if (OffsetRegNum == -1)
5989 return Error(E, "register expected");
5990
5991 // If there's a shift operator, handle it.
5992 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5993 unsigned ShiftImm = 0;
5994 if (Parser.getTok().is(AsmToken::Comma)) {
5995 Parser.Lex(); // Eat the ','.
5996 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5997 return true;
5998 }
5999
6000 // Now we should have the closing ']'
6001 if (Parser.getTok().isNot(AsmToken::RBrac))
6002 return Error(Parser.getTok().getLoc(), "']' expected");
6003 E = Parser.getTok().getEndLoc();
6004 Parser.Lex(); // Eat right bracket token.
6005
6006 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
6007 ShiftType, ShiftImm, 0, isNegative,
6008 S, E));
6009
6010 // If there's a pre-indexing writeback marker, '!', just add it as a token
6011 // operand.
6012 if (Parser.getTok().is(AsmToken::Exclaim)) {
6013 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
6014 Parser.Lex(); // Eat the '!'.
6015 }
6016
6017 return false;
6018}
6019
6020/// parseMemRegOffsetShift - one of these two:
6021/// ( lsl | lsr | asr | ror ) , # shift_amount
6022/// rrx
6023/// return true if it parses a shift otherwise it returns false.
6024bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
6025 unsigned &Amount) {
6026 MCAsmParser &Parser = getParser();
6027 SMLoc Loc = Parser.getTok().getLoc();
6028 const AsmToken &Tok = Parser.getTok();
6029 if (Tok.isNot(AsmToken::Identifier))
6030 return Error(Loc, "illegal shift operator");
6031 StringRef ShiftName = Tok.getString();
6032 if (ShiftName == "lsl" || ShiftName == "LSL" ||
6033 ShiftName == "asl" || ShiftName == "ASL")
6034 St = ARM_AM::lsl;
6035 else if (ShiftName == "lsr" || ShiftName == "LSR")
6036 St = ARM_AM::lsr;
6037 else if (ShiftName == "asr" || ShiftName == "ASR")
6038 St = ARM_AM::asr;
6039 else if (ShiftName == "ror" || ShiftName == "ROR")
6040 St = ARM_AM::ror;
6041 else if (ShiftName == "rrx" || ShiftName == "RRX")
6042 St = ARM_AM::rrx;
6043 else if (ShiftName == "uxtw" || ShiftName == "UXTW")
6044 St = ARM_AM::uxtw;
6045 else
6046 return Error(Loc, "illegal shift operator");
6047 Parser.Lex(); // Eat shift type token.
6048
6049 // rrx stands alone.
6050 Amount = 0;
6051 if (St != ARM_AM::rrx) {
6052 Loc = Parser.getTok().getLoc();
6053 // A '#' and a shift amount.
6054 const AsmToken &HashTok = Parser.getTok();
6055 if (HashTok.isNot(AsmToken::Hash) &&
6056 HashTok.isNot(AsmToken::Dollar))
6057 return Error(HashTok.getLoc(), "'#' expected");
6058 Parser.Lex(); // Eat hash token.
6059
6060 const MCExpr *Expr;
6061 if (getParser().parseExpression(Expr))
6062 return true;
6063 // Range check the immediate.
6064 // lsl, ror: 0 <= imm <= 31
6065 // lsr, asr: 0 <= imm <= 32
6066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
6067 if (!CE)
6068 return Error(Loc, "shift amount must be an immediate");
6069 int64_t Imm = CE->getValue();
6070 if (Imm < 0 ||
6071 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
6072 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
6073 return Error(Loc, "immediate shift value out of range");
6074 // If <ShiftTy> #0, turn it into a no_shift.
6075 if (Imm == 0)
6076 St = ARM_AM::lsl;
6077 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
6078 if (Imm == 32)
6079 Imm = 0;
6080 Amount = Imm;
6081 }
6082
6083 return false;
6084}
6085
6086/// parseFPImm - A floating point immediate expression operand.
6087OperandMatchResultTy
6088ARMAsmParser::parseFPImm(OperandVector &Operands) {
6089 MCAsmParser &Parser = getParser();
6090 // Anything that can accept a floating point constant as an operand
6091 // needs to go through here, as the regular parseExpression is
6092 // integer only.
6093 //
6094 // This routine still creates a generic Immediate operand, containing
6095 // a bitcast of the 64-bit floating point value. The various operands
6096 // that accept floats can check whether the value is valid for them
6097 // via the standard is*() predicates.
6098
6099 SMLoc S = Parser.getTok().getLoc();
6100
6101 if (Parser.getTok().isNot(AsmToken::Hash) &&
6102 Parser.getTok().isNot(AsmToken::Dollar))
6103 return MatchOperand_NoMatch;
6104
6105 // Disambiguate the VMOV forms that can accept an FP immediate.
6106 // vmov.f32 <sreg>, #imm
6107 // vmov.f64 <dreg>, #imm
6108 // vmov.f32 <dreg>, #imm @ vector f32x2
6109 // vmov.f32 <qreg>, #imm @ vector f32x4
6110 //
6111 // There are also the NEON VMOV instructions which expect an
6112 // integer constant. Make sure we don't try to parse an FPImm
6113 // for these:
6114 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
6115 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
6116 bool isVmovf = TyOp.isToken() &&
6117 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
6118 TyOp.getToken() == ".f16");
6119 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6120 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
6121 Mnemonic.getToken() == "fconsts");
6122 if (!(isVmovf || isFconst))
6123 return MatchOperand_NoMatch;
6124
6125 Parser.Lex(); // Eat '#' or '$'.
6126
6127 // Handle negation, as that still comes through as a separate token.
6128 bool isNegative = false;
6129 if (Parser.getTok().is(AsmToken::Minus)) {
6130 isNegative = true;
6131 Parser.Lex();
6132 }
6133 const AsmToken &Tok = Parser.getTok();
6134 SMLoc Loc = Tok.getLoc();
6135 if (Tok.is(AsmToken::Real) && isVmovf) {
6136 APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
6137 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
6138 // If we had a '-' in front, toggle the sign bit.
6139 IntVal ^= (uint64_t)isNegative << 31;
6140 Parser.Lex(); // Eat the token.
6141 Operands.push_back(ARMOperand::CreateImm(
6142 MCConstantExpr::create(IntVal, getContext()),
6143 S, Parser.getTok().getLoc()));
6144 return MatchOperand_Success;
6145 }
6146 // Also handle plain integers. Instructions which allow floating point
6147 // immediates also allow a raw encoded 8-bit value.
6148 if (Tok.is(AsmToken::Integer) && isFconst) {
6149 int64_t Val = Tok.getIntVal();
6150 Parser.Lex(); // Eat the token.
6151 if (Val > 255 || Val < 0) {
6152 Error(Loc, "encoded floating point value out of range");
6153 return MatchOperand_ParseFail;
6154 }
6155 float RealVal = ARM_AM::getFPImmFloat(Val);
6156 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
6157
6158 Operands.push_back(ARMOperand::CreateImm(
6159 MCConstantExpr::create(Val, getContext()), S,
6160 Parser.getTok().getLoc()));
6161 return MatchOperand_Success;
6162 }
6163
6164 Error(Loc, "invalid floating point immediate");
6165 return MatchOperand_ParseFail;
6166}
6167
6168/// Parse a arm instruction operand. For now this parses the operand regardless
6169/// of the mnemonic.
6170bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
6171 MCAsmParser &Parser = getParser();
6172 SMLoc S, E;
6173
6174 // Check if the current operand has a custom associated parser, if so, try to
6175 // custom parse the operand, or fallback to the general approach.
6176 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
6177 if (ResTy == MatchOperand_Success)
6178 return false;
6179 // If there wasn't a custom match, try the generic matcher below. Otherwise,
6180 // there was a match, but an error occurred, in which case, just return that
6181 // the operand parsing failed.
6182 if (ResTy == MatchOperand_ParseFail)
6183 return true;
6184
6185 switch (getLexer().getKind()) {
6186 default:
6187 Error(Parser.getTok().getLoc(), "unexpected token in operand");
6188 return true;
6189 case AsmToken::Identifier: {
6190 // If we've seen a branch mnemonic, the next operand must be a label. This
6191 // is true even if the label is a register name. So "br r1" means branch to
6192 // label "r1".
6193 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
6194 if (!ExpectLabel) {
6195 if (!tryParseRegisterWithWriteBack(Operands))
6196 return false;
6197 int Res = tryParseShiftRegister(Operands);
6198 if (Res == 0) // success
6199 return false;
6200 else if (Res == -1) // irrecoverable error
6201 return true;
6202 // If this is VMRS, check for the apsr_nzcv operand.
6203 if (Mnemonic == "vmrs" &&
6204 Parser.getTok().getString().equals_insensitive("apsr_nzcv")) {
6205 S = Parser.getTok().getLoc();
6206 Parser.Lex();
6207 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
6208 return false;
6209 }
6210 }
6211
6212 // Fall though for the Identifier case that is not a register or a
6213 // special name.
6214 LLVM_FALLTHROUGH[[gnu::fallthrough]];
6215 }
6216 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
6217 case AsmToken::Integer: // things like 1f and 2b as a branch targets
6218 case AsmToken::String: // quoted label names.
6219 case AsmToken::Dot: { // . as a branch target
6220 // This was not a register so parse other operands that start with an
6221 // identifier (like labels) as expressions and create them as immediates.
6222 const MCExpr *IdVal;
6223 S = Parser.getTok().getLoc();
6224 if (getParser().parseExpression(IdVal))
6225 return true;
6226 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6227 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
6228 return false;
6229 }
6230 case AsmToken::LBrac:
6231 return parseMemory(Operands);
6232 case AsmToken::LCurly:
6233 return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
6234 case AsmToken::Dollar:
6235 case AsmToken::Hash: {
6236 // #42 -> immediate
6237 // $ 42 -> immediate
6238 // $foo -> symbol name
6239 // $42 -> symbol name
6240 S = Parser.getTok().getLoc();
6241
6242 // Favor the interpretation of $-prefixed operands as symbol names.
6243 // Cases where immediates are explicitly expected are handled by their
6244 // specific ParseMethod implementations.
6245 auto AdjacentToken = getLexer().peekTok(/*ShouldSkipSpace=*/false);
6246 bool ExpectIdentifier = Parser.getTok().is(AsmToken::Dollar) &&
6247 (AdjacentToken.is(AsmToken::Identifier) ||
6248 AdjacentToken.is(AsmToken::Integer));
6249 if (!ExpectIdentifier) {
6250 // Token is not part of identifier. Drop leading $ or # before parsing
6251 // expression.
6252 Parser.Lex();
6253 }
6254
6255 if (Parser.getTok().isNot(AsmToken::Colon)) {
6256 bool IsNegative = Parser.getTok().is(AsmToken::Minus);
6257 const MCExpr *ImmVal;
6258 if (getParser().parseExpression(ImmVal))
6259 return true;
6260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
6261 if (CE) {
6262 int32_t Val = CE->getValue();
6263 if (IsNegative && Val == 0)
6264 ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
6265 getContext());
6266 }
6267 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6268 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
6269
6270 // There can be a trailing '!' on operands that we want as a separate
6271 // '!' Token operand. Handle that here. For example, the compatibility
6272 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
6273 if (Parser.getTok().is(AsmToken::Exclaim)) {
6274 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
6275 Parser.getTok().getLoc()));
6276 Parser.Lex(); // Eat exclaim token
6277 }
6278 return false;
6279 }
6280 // w/ a ':' after the '#', it's just like a plain ':'.
6281 LLVM_FALLTHROUGH[[gnu::fallthrough]];
6282 }
6283 case AsmToken::Colon: {
6284 S = Parser.getTok().getLoc();
6285 // ":lower16:" and ":upper16:" expression prefixes
6286 // FIXME: Check it's an expression prefix,
6287 // e.g. (FOO - :lower16:BAR) isn't legal.
6288 ARMMCExpr::VariantKind RefKind;
6289 if (parsePrefix(RefKind))
6290 return true;
6291
6292 const MCExpr *SubExprVal;
6293 if (getParser().parseExpression(SubExprVal))
6294 return true;
6295
6296 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
6297 getContext());
6298 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6299 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
6300 return false;
6301 }
6302 case AsmToken::Equal: {
6303 S = Parser.getTok().getLoc();
6304 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
6305 return Error(S, "unexpected token in operand");
6306 Parser.Lex(); // Eat '='
6307 const MCExpr *SubExprVal;
6308 if (getParser().parseExpression(SubExprVal))
6309 return true;
6310 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6311
6312 // execute-only: we assume that assembly programmers know what they are
6313 // doing and allow literal pool creation here
6314 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
6315 return false;
6316 }
6317 }
6318}
6319
6320// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
6321// :lower16: and :upper16:.
6322bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
6323 MCAsmParser &Parser = getParser();
6324 RefKind = ARMMCExpr::VK_ARM_None;
6325
6326 // consume an optional '#' (GNU compatibility)
6327 if (getLexer().is(AsmToken::Hash))
6328 Parser.Lex();
6329
6330 // :lower16: and :upper16: modifiers
6331 assert(getLexer().is(AsmToken::Colon) && "expected a :")(static_cast <bool> (getLexer().is(AsmToken::Colon) &&
"expected a :") ? void (0) : __assert_fail ("getLexer().is(AsmToken::Colon) && \"expected a :\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 6331, __extension__
__PRETTY_FUNCTION__))
;
6332 Parser.Lex(); // Eat ':'
6333
6334 if (getLexer().isNot(AsmToken::Identifier)) {
6335 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
6336 return true;
6337 }
6338
6339 enum {
6340 COFF = (1 << MCContext::IsCOFF),
6341 ELF = (1 << MCContext::IsELF),
6342 MACHO = (1 << MCContext::IsMachO),
6343 WASM = (1 << MCContext::IsWasm),
6344 };
6345 static const struct PrefixEntry {
6346 const char *Spelling;
6347 ARMMCExpr::VariantKind VariantKind;
6348 uint8_t SupportedFormats;
6349 } PrefixEntries[] = {
6350 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
6351 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
6352 };
6353
6354 StringRef IDVal = Parser.getTok().getIdentifier();
6355
6356 const auto &Prefix =
6357 llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) {
6358 return PE.Spelling == IDVal;
6359 });
6360 if (Prefix == std::end(PrefixEntries)) {
6361 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
6362 return true;
6363 }
6364
6365 uint8_t CurrentFormat;
6366 switch (getContext().getObjectFileType()) {
6367 case MCContext::IsMachO:
6368 CurrentFormat = MACHO;
6369 break;
6370 case MCContext::IsELF:
6371 CurrentFormat = ELF;
6372 break;
6373 case MCContext::IsCOFF:
6374 CurrentFormat = COFF;
6375 break;
6376 case MCContext::IsWasm:
6377 CurrentFormat = WASM;
6378 break;
6379 case MCContext::IsGOFF:
6380 case MCContext::IsSPIRV:
6381 case MCContext::IsXCOFF:
6382 case MCContext::IsDXContainer:
6383 llvm_unreachable("unexpected object format")::llvm::llvm_unreachable_internal("unexpected object format",
"llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 6383)
;
6384 break;
6385 }
6386
6387 if (~Prefix->SupportedFormats & CurrentFormat) {
6388 Error(Parser.getTok().getLoc(),
6389 "cannot represent relocation in the current file format");
6390 return true;
6391 }
6392
6393 RefKind = Prefix->VariantKind;
6394 Parser.Lex();
6395
6396 if (getLexer().isNot(AsmToken::Colon)) {
6397 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
6398 return true;
6399 }
6400 Parser.Lex(); // Eat the last ':'
6401
6402 return false;
6403}
6404
6405/// Given a mnemonic, split out possible predication code and carry
6406/// setting letters to form a canonical mnemonic and flags.
6407//
6408// FIXME: Would be nice to autogen this.
6409// FIXME: This is a bit of a maze of special cases.
6410StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
6411 StringRef ExtraToken,
6412 unsigned &PredicationCode,
6413 unsigned &VPTPredicationCode,
6414 bool &CarrySetting,
6415 unsigned &ProcessorIMod,
6416 StringRef &ITMask) {
6417 PredicationCode = ARMCC::AL;
6418 VPTPredicationCode = ARMVCC::None;
6419 CarrySetting = false;
6420 ProcessorIMod = 0;
6421
6422 // Ignore some mnemonics we know aren't predicated forms.
6423 //
6424 // FIXME: Would be nice to autogen this.
6425 if ((Mnemonic == "movs" && isThumb()) ||
6426 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
6427 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
6428 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
6429 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
6430 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
6431 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
6432 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
6433 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
6434 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
6435 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
6436 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
6437 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
6438 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
6439 Mnemonic == "bxns" || Mnemonic == "blxns" ||
6440 Mnemonic == "vdot" || Mnemonic == "vmmla" ||
6441 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6442 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6443 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6444 Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6445 Mnemonic == "csel" || Mnemonic == "csinc" ||
6446 Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6447 Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6448 Mnemonic == "csetm" ||
6449 Mnemonic == "aut" || Mnemonic == "pac" || Mnemonic == "pacbti" ||
6450 Mnemonic == "bti")
6451 return Mnemonic;
6452
6453 // First, split out any predication code. Ignore mnemonics we know aren't
6454 // predicated but do have a carry-set and so weren't caught above.
6455 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
6456 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
6457 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
6458 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
6459 !(hasMVE() &&
6460 (Mnemonic == "vmine" ||
6461 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
6462 Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
6463 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
6464 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
6465 Mnemonic == "vmule" || Mnemonic == "vmult" ||
6466 Mnemonic == "vrintne" ||
6467 Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6468 Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
6469 Mnemonic.startswith("vq")))) {
6470 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
6471 if (CC != ~0U) {
6472 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6473 PredicationCode = CC;
6474 }
6475 }
6476
6477 // Next, determine if we have a carry setting bit. We explicitly ignore all
6478 // the instructions we know end in 's'.
6479 if (Mnemonic.endswith("s") &&
6480 !(Mnemonic == "cps" || Mnemonic == "mls" ||
6481 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
6482 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
6483 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
6484 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
6485 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
6486 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
6487 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
6488 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
6489 Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6490 Mnemonic == "vmlas" ||
6491 (Mnemonic == "movs" && isThumb()))) {
6492 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6493 CarrySetting = true;
6494 }
6495
6496 // The "cps" instruction can have a interrupt mode operand which is glued into
6497 // the mnemonic. Check if this is the case, split it and parse the imod op
6498 if (Mnemonic.startswith("cps")) {
6499 // Split out any imod code.
6500 unsigned IMod =
6501 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
6502 .Case("ie", ARM_PROC::IE)
6503 .Case("id", ARM_PROC::ID)
6504 .Default(~0U);
6505 if (IMod != ~0U) {
6506 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6507 ProcessorIMod = IMod;
6508 }
6509 }
6510
6511 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
6512 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
6513 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6514 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6515 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6516 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6517 Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6518 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
6519 if (CC != ~0U) {
6520 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6521 VPTPredicationCode = CC;
6522 }
6523 return Mnemonic;
6524 }
6525
6526 // The "it" instruction has the condition mask on the end of the mnemonic.
6527 if (Mnemonic.startswith("it")) {
6528 ITMask = Mnemonic.slice(2, Mnemonic.size());
6529 Mnemonic = Mnemonic.slice(0, 2);
6530 }
6531
6532 if (Mnemonic.startswith("vpst")) {
6533 ITMask = Mnemonic.slice(4, Mnemonic.size());
6534 Mnemonic = Mnemonic.slice(0, 4);
6535 }
6536 else if (Mnemonic.startswith("vpt")) {
6537 ITMask = Mnemonic.slice(3, Mnemonic.size());
6538 Mnemonic = Mnemonic.slice(0, 3);
6539 }
6540
6541 return Mnemonic;
6542}
6543
6544/// Given a canonical mnemonic, determine if the instruction ever allows
6545/// inclusion of carry set or predication code operands.
6546//
6547// FIXME: It would be nice to autogen this.
6548void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
6549 StringRef ExtraToken,
6550 StringRef FullInst,
6551 bool &CanAcceptCarrySet,
6552 bool &CanAcceptPredicationCode,
6553 bool &CanAcceptVPTPredicationCode) {
6554 CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
6555
6556 CanAcceptCarrySet =
6557 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6558 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
6559 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
6560 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
6561 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
6562 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
6563 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
6564 (!isThumb() &&
6565 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
6566 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
6567
6568 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
6569 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
6570 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
6571 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
6572 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
6573 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
6574 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
6575 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
6576 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
6577 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
6578 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
6579 Mnemonic == "vmovx" || Mnemonic == "vins" ||
6580 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6581 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6582 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6583 Mnemonic == "vfmat" || Mnemonic == "vfmab" ||
6584 Mnemonic == "vdot" || Mnemonic == "vmmla" ||
6585 Mnemonic == "sb" || Mnemonic == "ssbb" ||
6586 Mnemonic == "pssbb" || Mnemonic == "vsmmla" ||
6587 Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
6588 Mnemonic == "vusdot" || Mnemonic == "vsudot" ||
6589 Mnemonic == "bfcsel" || Mnemonic == "wls" ||
6590 Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
6591 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
6592 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
6593 Mnemonic == "cset" || Mnemonic == "csetm" ||
6594 (hasCDE() && MS.isCDEInstr(Mnemonic) &&
6595 !MS.isITPredicableCDEInstr(Mnemonic)) ||
6596 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6597 Mnemonic == "pac" || Mnemonic == "pacbti" || Mnemonic == "aut" ||
6598 Mnemonic == "bti" ||
6599 (hasMVE() &&
6600 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6601 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6602 Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6603 Mnemonic.startswith("letp")))) {
6604 // These mnemonics are never predicable
6605 CanAcceptPredicationCode = false;
6606 } else if (!isThumb()) {
6607 // Some instructions are only predicable in Thumb mode
6608 CanAcceptPredicationCode =
6609 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
6610 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
6611 Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
6612 Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
6613 Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
6614 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
6615 Mnemonic != "tsb" &&
6616 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
6617 } else if (isThumbOne()) {
6618 if (hasV6MOps())
6619 CanAcceptPredicationCode = Mnemonic != "movs";
6620 else
6621 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
6622 } else
6623 CanAcceptPredicationCode = true;
6624}
6625
6626// Some Thumb instructions have two operand forms that are not
6627// available as three operand, convert to two operand form if possible.
6628//
6629// FIXME: We would really like to be able to tablegen'erate this.
6630void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
6631 bool CarrySetting,
6632 OperandVector &Operands) {
6633 if (Operands.size() != 6)
6634 return;
6635
6636 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6637 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6638 if (!Op3.isReg() || !Op4.isReg())
6639 return;
6640
6641 auto Op3Reg = Op3.getReg();
6642 auto Op4Reg = Op4.getReg();
6643
6644 // For most Thumb2 cases we just generate the 3 operand form and reduce
6645 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
6646 // won't accept SP or PC so we do the transformation here taking care
6647 // with immediate range in the 'add sp, sp #imm' case.
6648 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6649 if (isThumbTwo()) {
6650 if (Mnemonic != "add")
6651 return;
6652 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
6653 (Op5.isReg() && Op5.getReg() == ARM::PC);
6654 if (!TryTransform) {
6655 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6656 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6657 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6658 Op5.isImm() && !Op5.isImm0_508s4());
6659 }
6660 if (!TryTransform)
6661 return;
6662 } else if (!isThumbOne())
6663 return;
6664
6665 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
6666 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6667 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
6668 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
6669 return;
6670
6671 // If first 2 operands of a 3 operand instruction are the same
6672 // then transform to 2 operand version of the same instruction
6673 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
6674 bool Transform = Op3Reg == Op4Reg;
6675
6676 // For communtative operations, we might be able to transform if we swap
6677 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6678 // as tADDrsp.
6679 const ARMOperand *LastOp = &Op5;
6680 bool Swap = false;
6681 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6682 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6683 Mnemonic == "and" || Mnemonic == "eor" ||
6684 Mnemonic == "adc" || Mnemonic == "orr")) {
6685 Swap = true;
6686 LastOp = &Op4;
6687 Transform = true;
6688 }
6689
6690 // If both registers are the same then remove one of them from
6691 // the operand list, with certain exceptions.
6692 if (Transform) {
6693 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
6694 // 2 operand forms don't exist.
6695 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
6696 LastOp->isReg())
6697 Transform = false;
6698
6699 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
6700 // 3-bits because the ARMARM says not to.
6701 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
6702 Transform = false;
6703 }
6704
6705 if (Transform) {
6706 if (Swap)
6707 std::swap(Op4, Op5);
6708 Operands.erase(Operands.begin() + 3);
6709 }
6710}
6711
6712bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6713 OperandVector &Operands) {
6714 // FIXME: This is all horribly hacky. We really need a better way to deal
6715 // with optional operands like this in the matcher table.
6716
6717 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
6718 // another does not. Specifically, the MOVW instruction does not. So we
6719 // special case it here and remove the defaulted (non-setting) cc_out
6720 // operand if that's the instruction we're trying to match.
6721 //
6722 // We do this as post-processing of the explicit operands rather than just
6723 // conditionally adding the cc_out in the first place because we need
6724 // to check the type of the parsed immediate operand.
6725 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
6726 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
6727 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
6728 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6729 return true;
6730
6731 // Register-register 'add' for thumb does not have a cc_out operand
6732 // when there are only two register operands.
6733 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
6734 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6735 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6736 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6737 return true;
6738 // Register-register 'add' for thumb does not have a cc_out operand
6739 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
6740 // have to check the immediate range here since Thumb2 has a variant
6741 // that can handle a different range and has a cc_out operand.
6742 if (((isThumb() && Mnemonic == "add") ||
6743 (isThumbTwo() && Mnemonic == "sub")) &&
6744 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6745 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6746 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6747 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6748 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6749 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
6750 return true;
6751 // For Thumb2, add/sub immediate does not have a cc_out operand for the
6752 // imm0_4095 variant. That's the least-preferred variant when
6753 // selecting via the generic "add" mnemonic, so to know that we
6754 // should remove the cc_out operand, we have to explicitly check that
6755 // it's not one of the other variants. Ugh.
6756 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6757 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6758 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6759 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6760 // Nest conditions rather than one big 'if' statement for readability.
6761 //
6762 // If both registers are low, we're in an IT block, and the immediate is
6763 // in range, we should use encoding T1 instead, which has a cc_out.
6764 if (inITBlock() &&
6765 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
6766 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
6767 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
6768 return false;
6769 // Check against T3. If the second register is the PC, this is an
6770 // alternate form of ADR, which uses encoding T4, so check for that too.
6771 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
6772 (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() ||
6773 static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg()))
6774 return false;
6775
6776 // Otherwise, we use encoding T4, which does not have a cc_out
6777 // operand.
6778 return true;
6779 }
6780
6781 // The thumb2 multiply instruction doesn't have a CCOut register, so
6782 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
6783 // use the 16-bit encoding or not.
6784 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
6785 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6786 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6787 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6788 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6789 // If the registers aren't low regs, the destination reg isn't the
6790 // same as one of the source regs, or the cc_out operand is zero
6791 // outside of an IT block, we have to use the 32-bit encoding, so
6792 // remove the cc_out operand.
6793 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6794 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6795 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
6796 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6797 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
6798 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6799 static_cast<ARMOperand &>(*Operands[4]).getReg())))
6800 return true;
6801
6802 // Also check the 'mul' syntax variant that doesn't specify an explicit
6803 // destination register.
6804 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
6805 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6806 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6807 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6808 // If the registers aren't low regs or the cc_out operand is zero
6809 // outside of an IT block, we have to use the 32-bit encoding, so
6810 // remove the cc_out operand.
6811 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6812 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6813 !inITBlock()))
6814 return true;
6815
6816 // Register-register 'add/sub' for thumb does not have a cc_out operand
6817 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
6818 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6819 // right, this will result in better diagnostics (which operand is off)
6820 // anyway.
6821 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
6822 (Operands.size() == 5 || Operands.size() == 6) &&
6823 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6824 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6825 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6826 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
6827 (Operands.size() == 6 &&
6828 static_cast<ARMOperand &>(*Operands[5]).isImm()))) {
6829 // Thumb2 (add|sub){s}{p}.w GPRnopc, sp, #{T2SOImm} has cc_out
6830 return (!(isThumbTwo() &&
6831 (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() ||
6832 static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg())));
6833 }
6834 // Fixme: Should join all the thumb+thumb2 (add|sub) in a single if case
6835 // Thumb2 ADD r0, #4095 -> ADDW r0, r0, #4095 (T4)
6836 // Thumb2 SUB r0, #4095 -> SUBW r0, r0, #4095
6837 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6838 (Operands.size() == 5) &&
6839 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6840 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP &&
6841 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC &&
6842 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6843 static_cast<ARMOperand &>(*Operands[4]).isImm()) {
6844 const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]);
6845 if (IMM.isT2SOImm() || IMM.isT2SOImmNeg())
6846 return false; // add.w / sub.w
6847 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) {
6848 const int64_t Value = CE->getValue();
6849 // Thumb1 imm8 sub / add
6850 if ((Value < ((1 << 7) - 1) << 2) && inITBlock() && (!(Value & 3)) &&
6851 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()))
6852 return false;
6853 return true; // Thumb2 T4 addw / subw
6854 }
6855 }
6856 return false;
6857}
6858
6859bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
6860 OperandVector &Operands) {
6861 // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
6862 unsigned RegIdx = 3;
6863 if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6864 Mnemonic == "vrintr") &&
6865 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
6866 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
6867 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6868 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
6869 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
6870 RegIdx = 4;
6871
6872 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6873 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6874 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6875 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6876 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
6877 return true;
6878 }
6879 return false;
6880}
6881
6882bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
6883 OperandVector &Operands) {
6884 if (!hasMVE() || Operands.size() < 3)
6885 return true;
6886
6887 if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6888 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
6889 return true;
6890
6891 if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
6892 return false;
6893
6894 if (Mnemonic.startswith("vmov") &&
6895 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6896 Mnemonic.startswith("vmovx"))) {
6897 for (auto &Operand : Operands) {
6898 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6899 ((*Operand).isReg() &&
6900 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6901 (*Operand).getReg()) ||
6902 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6903 (*Operand).getReg())))) {
6904 return true;
6905 }
6906 }
6907 return false;
6908 } else {
6909 for (auto &Operand : Operands) {
6910 // We check the larger class QPR instead of just the legal class
6911 // MQPR, to more accurately report errors when using Q registers
6912 // outside of the allowed range.
6913 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6914 (Operand->isReg() &&
6915 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6916 Operand->getReg()))))
6917 return false;
6918 }
6919 return true;
6920 }
6921}
6922
6923static bool isDataTypeToken(StringRef Tok) {
6924 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
6925 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
6926 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6927 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6928 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6929 Tok == ".f" || Tok == ".d";
6930}
6931
6932// FIXME: This bit should probably be handled via an explicit match class
6933// in the .td files that matches the suffix instead of having it be
6934// a literal string token the way it is now.
6935static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6936 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6937}
6938
6939static void applyMnemonicAliases(StringRef &Mnemonic,
6940 const FeatureBitset &Features,
6941 unsigned VariantID);
6942
6943// The GNU assembler has aliases of ldrd and strd with the second register
6944// omitted. We don't have a way to do that in tablegen, so fix it up here.
6945//
6946// We have to be careful to not emit an invalid Rt2 here, because the rest of
6947// the assembly parser could then generate confusing diagnostics refering to
6948// it. If we do find anything that prevents us from doing the transformation we
6949// bail out, and let the assembly parser report an error on the instruction as
6950// it is written.
6951void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6952 OperandVector &Operands) {
6953 if (Mnemonic != "ldrd" && Mnemonic != "strd")
6954 return;
6955 if (Operands.size() < 4)
6956 return;
6957
6958 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6959 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6960
6961 if (!Op2.isReg())
6962 return;
6963 if (!Op3.isGPRMem())
6964 return;
6965
6966 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6967 if (!GPR.contains(Op2.getReg()))
6968 return;
6969
6970 unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6971 if (!isThumb() && (RtEncoding & 1)) {
6972 // In ARM mode, the registers must be from an aligned pair, this
6973 // restriction does not apply in Thumb mode.
6974 return;
6975 }
6976 if (Op2.getReg() == ARM::PC)
6977 return;
6978 unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6979 if (!PairedReg || PairedReg == ARM::PC ||
6980 (PairedReg == ARM::SP && !hasV8Ops()))
6981 return;
6982
6983 Operands.insert(
6984 Operands.begin() + 3,
6985 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6986}
6987
6988// Dual-register instruction have the following syntax:
6989// <mnemonic> <predicate>? <coproc>, <Rdest>, <Rdest+1>, <Rsrc>, ..., #imm
6990// This function tries to remove <Rdest+1> and replace <Rdest> with a pair
6991// operand. If the conversion fails an error is diagnosed, and the function
6992// returns true.
6993bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic,
6994 OperandVector &Operands) {
6995 assert(MS.isCDEDualRegInstr(Mnemonic))(static_cast <bool> (MS.isCDEDualRegInstr(Mnemonic)) ? void
(0) : __assert_fail ("MS.isCDEDualRegInstr(Mnemonic)", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 6995, __extension__ __PRETTY_FUNCTION__))
;
6996 bool isPredicable =
6997 Mnemonic == "cx1da" || Mnemonic == "cx2da" || Mnemonic == "cx3da";
6998 size_t NumPredOps = isPredicable ? 1 : 0;
6999
7000 if (Operands.size() <= 3 + NumPredOps)
7001 return false;
7002
7003 StringRef Op2Diag(
7004 "operand must be an even-numbered register in the range [r0, r10]");
7005
7006 const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps];
7007 if (!Op2.isReg())
7008 return Error(Op2.getStartLoc(), Op2Diag);
7009
7010 unsigned RNext;
7011 unsigned RPair;
7012 switch (Op2.getReg()) {
7013 default:
7014 return Error(Op2.getStartLoc(), Op2Diag);
7015 case ARM::R0:
7016 RNext = ARM::R1;
7017 RPair = ARM::R0_R1;
7018 break;
7019 case ARM::R2:
7020 RNext = ARM::R3;
7021 RPair = ARM::R2_R3;
7022 break;
7023 case ARM::R4:
7024 RNext = ARM::R5;
7025 RPair = ARM::R4_R5;
7026 break;
7027 case ARM::R6:
7028 RNext = ARM::R7;
7029 RPair = ARM::R6_R7;
7030 break;
7031 case ARM::R8:
7032 RNext = ARM::R9;
7033 RPair = ARM::R8_R9;
7034 break;
7035 case ARM::R10:
7036 RNext = ARM::R11;
7037 RPair = ARM::R10_R11;
7038 break;
7039 }
7040
7041 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps];
7042 if (!Op3.isReg() || Op3.getReg() != RNext)
7043 return Error(Op3.getStartLoc(), "operand must be a consecutive register");
7044
7045 Operands.erase(Operands.begin() + 3 + NumPredOps);
7046 Operands[2 + NumPredOps] =
7047 ARMOperand::CreateReg(RPair, Op2.getStartLoc(), Op2.getEndLoc());
7048 return false;
7049}
7050
7051/// Parse an arm instruction mnemonic followed by its operands.
7052bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
7053 SMLoc NameLoc, OperandVector &Operands) {
7054 MCAsmParser &Parser = getParser();
7055
7056 // Apply mnemonic aliases before doing anything else, as the destination
7057 // mnemonic may include suffices and we want to handle them normally.
7058 // The generic tblgen'erated code does this later, at the start of
7059 // MatchInstructionImpl(), but that's too late for aliases that include
7060 // any sort of suffix.
7061 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
7062 unsigned AssemblerDialect = getParser().getAssemblerDialect();
7063 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
7064
7065 // First check for the ARM-specific .req directive.
7066 if (Parser.getTok().is(AsmToken::Identifier) &&
7067 Parser.getTok().getIdentifier().lower() == ".req") {
7068 parseDirectiveReq(Name, NameLoc);
7069 // We always return 'error' for this, as we're done with this
7070 // statement and don't need to match the 'instruction."
7071 return true;
7072 }
7073
7074 // Create the leading tokens for the mnemonic, split by '.' characters.
7075 size_t Start = 0, Next = Name.find('.');
7076 StringRef Mnemonic = Name.slice(Start, Next);
7077 StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
7078
7079 // Split out the predication code and carry setting flag from the mnemonic.
7080 unsigned PredicationCode;
7081 unsigned VPTPredicationCode;
7082 unsigned ProcessorIMod;
7083 bool CarrySetting;
7084 StringRef ITMask;
7085 Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
7086 CarrySetting, ProcessorIMod, ITMask);
7087
7088 // In Thumb1, only the branch (B) instruction can be predicated.
7089 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
7090 return Error(NameLoc, "conditional execution not supported in Thumb1");
7091 }
7092
7093 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
7094
7095 // Handle the mask for IT and VPT instructions. In ARMOperand and
7096 // MCOperand, this is stored in a format independent of the
7097 // condition code: the lowest set bit indicates the end of the
7098 // encoding, and above that, a 1 bit indicates 'else', and an 0
7099 // indicates 'then'. E.g.
7100 // IT -> 1000
7101 // ITx -> x100 (ITT -> 0100, ITE -> 1100)
7102 // ITxy -> xy10 (e.g. ITET -> 1010)
7103 // ITxyz -> xyz1 (e.g. ITEET -> 1101)
7104 // Note: See the ARM::PredBlockMask enum in
7105 // /lib/Target/ARM/Utils/ARMBaseInfo.h
7106 if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
7107 Mnemonic.startswith("vpst")) {
7108 SMLoc Loc = Mnemonic == "it" ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
7109 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
7110 SMLoc::getFromPointer(NameLoc.getPointer() + 4);
7111 if (ITMask.size() > 3) {
7112 if (Mnemonic == "it")
7113 return Error(Loc, "too many conditions on IT instruction");
7114 return Error(Loc, "too many conditions on VPT instruction");
7115 }
7116 unsigned Mask = 8;
7117 for (char Pos : llvm::reverse(ITMask)) {
7118 if (Pos != 't' && Pos != 'e') {
7119 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
7120 }
7121 Mask >>= 1;
7122 if (Pos == 'e')
7123 Mask |= 8;
7124 }
7125 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
7126 }
7127
7128 // FIXME: This is all a pretty gross hack. We should automatically handle
7129 // optional operands like this via tblgen.
7130
7131 // Next, add the CCOut and ConditionCode operands, if needed.
7132 //
7133 // For mnemonics which can ever incorporate a carry setting bit or predication
7134 // code, our matching model involves us always generating CCOut and
7135 // ConditionCode operands to match the mnemonic "as written" and then we let
7136 // the matcher deal with finding the right instruction or generating an
7137 // appropriate error.
7138 bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
7139 getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
7140 CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
7141
7142 // If we had a carry-set on an instruction that can't do that, issue an
7143 // error.
7144 if (!CanAcceptCarrySet && CarrySetting) {
7145 return Error(NameLoc, "instruction '" + Mnemonic +
7146 "' can not set flags, but 's' suffix specified");
7147 }
7148 // If we had a predication code on an instruction that can't do that, issue an
7149 // error.
7150 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
7151 return Error(NameLoc, "instruction '" + Mnemonic +
7152 "' is not predicable, but condition code specified");
7153 }
7154
7155 // If we had a VPT predication code on an instruction that can't do that, issue an
7156 // error.
7157 if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
7158 return Error(NameLoc, "instruction '" + Mnemonic +
7159 "' is not VPT predicable, but VPT code T/E is specified");
7160 }
7161
7162 // Add the carry setting operand, if necessary.
7163 if (CanAcceptCarrySet) {
7164 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
7165 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
7166 Loc));
7167 }
7168
7169 // Add the predication code operand, if necessary.
7170 if (CanAcceptPredicationCode) {
7171 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7172 CarrySetting);
7173 Operands.push_back(ARMOperand::CreateCondCode(
7174 ARMCC::CondCodes(PredicationCode), Loc));
7175 }
7176
7177 // Add the VPT predication code operand, if necessary.
7178 // FIXME: We don't add them for the instructions filtered below as these can
7179 // have custom operands which need special parsing. This parsing requires
7180 // the operand to be in the same place in the OperandVector as their
7181 // definition in tblgen. Since these instructions may also have the
7182 // scalar predication operand we do not add the vector one and leave until
7183 // now to fix it up.
7184 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
7185 !Mnemonic.startswith("vcmp") &&
7186 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
7187 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
7188 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7189 CarrySetting);
7190 Operands.push_back(ARMOperand::CreateVPTPred(
7191 ARMVCC::VPTCodes(VPTPredicationCode), Loc));
7192 }
7193
7194 // Add the processor imod operand, if necessary.
7195 if (ProcessorIMod) {
7196 Operands.push_back(ARMOperand::CreateImm(
7197 MCConstantExpr::create(ProcessorIMod, getContext()),
7198 NameLoc, NameLoc));
7199 } else if (Mnemonic == "cps" && isMClass()) {
7200 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
7201 }
7202
7203 // Add the remaining tokens in the mnemonic.
7204 while (Next != StringRef::npos) {
7205 Start = Next;
7206 Next = Name.find('.', Start + 1);
7207 ExtraToken = Name.slice(Start, Next);
7208
7209 // Some NEON instructions have an optional datatype suffix that is
7210 // completely ignored. Check for that.
7211 if (isDataTypeToken(ExtraToken) &&
7212 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
7213 continue;
7214
7215 // For for ARM mode generate an error if the .n qualifier is used.
7216 if (ExtraToken == ".n" && !isThumb()) {
7217 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7218 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
7219 "arm mode");
7220 }
7221
7222 // The .n qualifier is always discarded as that is what the tables
7223 // and matcher expect. In ARM mode the .w qualifier has no effect,
7224 // so discard it to avoid errors that can be caused by the matcher.
7225 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
7226 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7227 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
7228 }
7229 }
7230
7231 // Read the remaining operands.
7232 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7233 // Read the first operand.
7234 if (parseOperand(Operands, Mnemonic)) {
7235 return true;
7236 }
7237
7238 while (parseOptionalToken(AsmToken::Comma)) {
7239 // Parse and remember the operand.
7240 if (parseOperand(Operands, Mnemonic)) {
7241 return true;
7242 }
7243 }
7244 }
7245
7246 if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
7247 return true;
7248
7249 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
7250
7251 if (hasCDE() && MS.isCDEInstr(Mnemonic)) {
7252 // Dual-register instructions use even-odd register pairs as their
7253 // destination operand, in assembly such pair is spelled as two
7254 // consecutive registers, without any special syntax. ConvertDualRegOperand
7255 // tries to convert such operand into register pair, e.g. r2, r3 -> r2_r3.
7256 // It returns true, if an error message has been emitted. If the function
7257 // returns false, the function either succeeded or an error (e.g. missing
7258 // operand) will be diagnosed elsewhere.
7259 if (MS.isCDEDualRegInstr(Mnemonic)) {
7260 bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands);
7261 if (GotError)
7262 return GotError;
7263 }
7264 }
7265
7266 // Some instructions, mostly Thumb, have forms for the same mnemonic that
7267 // do and don't have a cc_out optional-def operand. With some spot-checks
7268 // of the operand list, we can figure out which variant we're trying to
7269 // parse and adjust accordingly before actually matching. We shouldn't ever
7270 // try to remove a cc_out operand that was explicitly set on the
7271 // mnemonic, of course (CarrySetting == true). Reason number #317 the
7272 // table driven matcher doesn't fit well with the ARM instruction set.
7273 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
7274 Operands.erase(Operands.begin() + 1);
7275
7276 // Some instructions have the same mnemonic, but don't always
7277 // have a predicate. Distinguish them here and delete the
7278 // appropriate predicate if needed. This could be either the scalar
7279 // predication code or the vector predication code.
7280 if (PredicationCode == ARMCC::AL &&
7281 shouldOmitPredicateOperand(Mnemonic, Operands))
7282 Operands.erase(Operands.begin() + 1);
7283
7284
7285 if (hasMVE()) {
7286 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
7287 Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
7288 // Very nasty hack to deal with the vector predicated variant of vmovlt
7289 // the scalar predicated vmov with condition 'lt'. We can not tell them
7290 // apart until we have parsed their operands.
7291 Operands.erase(Operands.begin() + 1);
7292 Operands.erase(Operands.begin());
7293 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7294 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7295 Mnemonic.size() - 1 + CarrySetting);
7296 Operands.insert(Operands.begin(),
7297 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
7298 Operands.insert(Operands.begin(),
7299 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
7300 } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
7301 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7302 // Another nasty hack to deal with the ambiguity between vcvt with scalar
7303 // predication 'ne' and vcvtn with vector predication 'e'. As above we
7304 // can only distinguish between the two after we have parsed their
7305 // operands.
7306 Operands.erase(Operands.begin() + 1);
7307 Operands.erase(Operands.begin());
7308 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7309 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7310 Mnemonic.size() - 1 + CarrySetting);
7311 Operands.insert(Operands.begin(),
7312 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
7313 Operands.insert(Operands.begin(),
7314 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
7315 } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
7316 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7317 // Another hack, this time to distinguish between scalar predicated vmul
7318 // with 'lt' predication code and the vector instruction vmullt with
7319 // vector predication code "none"
7320 Operands.erase(Operands.begin() + 1);
7321 Operands.erase(Operands.begin());
7322 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7323 Operands.insert(Operands.begin(),
7324 ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
7325 }
7326 // For vmov and vcmp, as mentioned earlier, we did not add the vector
7327 // predication code, since these may contain operands that require
7328 // special parsing. So now we have to see if they require vector
7329 // predication and replace the scalar one with the vector predication
7330 // operand if that is the case.
7331 else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
7332 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
7333 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
7334 !Mnemonic.startswith("vcvtm"))) {
7335 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7336 // We could not split the vector predicate off vcvt because it might
7337 // have been the scalar vcvtt instruction. Now we know its a vector
7338 // instruction, we still need to check whether its the vector
7339 // predicated vcvt with 'Then' predication or the vector vcvtt. We can
7340 // distinguish the two based on the suffixes, if it is any of
7341 // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
7342 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
7343 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
7344 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
7345 if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
7346 Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
7347 Operands.erase(Operands.begin());
7348 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7349 VPTPredicationCode = ARMVCC::Then;
7350
7351 Mnemonic = Mnemonic.substr(0, 4);
7352 Operands.insert(Operands.begin(),
7353 ARMOperand::CreateToken(Mnemonic, MLoc));
7354 }
7355 }
7356 Operands.erase(Operands.begin() + 1);
7357 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7358 Mnemonic.size() + CarrySetting);
7359 Operands.insert(Operands.begin() + 1,
7360 ARMOperand::CreateVPTPred(
7361 ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
7362 }
7363 } else if (CanAcceptVPTPredicationCode) {
7364 // For all other instructions, make sure only one of the two
7365 // predication operands is left behind, depending on whether we should
7366 // use the vector predication.
7367 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7368 if (CanAcceptPredicationCode)
7369 Operands.erase(Operands.begin() + 2);
7370 else
7371 Operands.erase(Operands.begin() + 1);
7372 } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
7373 Operands.erase(Operands.begin() + 1);
7374 }
7375 }
7376 }
7377
7378 if (VPTPredicationCode != ARMVCC::None) {
7379 bool usedVPTPredicationCode = false;
7380 for (unsigned I = 1; I < Operands.size(); ++I)
7381 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7382 usedVPTPredicationCode = true;
7383 if (!usedVPTPredicationCode) {
7384 // If we have a VPT predication code and we haven't just turned it
7385 // into an operand, then it was a mistake for splitMnemonic to
7386 // separate it from the rest of the mnemonic in the first place,
7387 // and this may lead to wrong disassembly (e.g. scalar floating
7388 // point VCMPE is actually a different instruction from VCMP, so
7389 // we mustn't treat them the same). In that situation, glue it
7390 // back on.
7391 Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7392 Operands.erase(Operands.begin());
7393 Operands.insert(Operands.begin(),
7394 ARMOperand::CreateToken(Mnemonic, NameLoc));
7395 }
7396 }
7397
7398 // ARM mode 'blx' need special handling, as the register operand version
7399 // is predicable, but the label operand version is not. So, we can't rely
7400 // on the Mnemonic based checking to correctly figure out when to put
7401 // a k_CondCode operand in the list. If we're trying to match the label
7402 // version, remove the k_CondCode operand here.
7403 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
7404 static_cast<ARMOperand &>(*Operands[2]).isImm())
7405 Operands.erase(Operands.begin() + 1);
7406
7407 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
7408 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7409 // a single GPRPair reg operand is used in the .td file to replace the two
7410 // GPRs. However, when parsing from asm, the two GRPs cannot be
7411 // automatically
7412 // expressed as a GPRPair, so we have to manually merge them.
7413 // FIXME: We would really like to be able to tablegen'erate this.
7414 if (!isThumb() && Operands.size() > 4 &&
7415 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
7416 Mnemonic == "stlexd")) {
7417 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
7418 unsigned Idx = isLoad ? 2 : 3;
7419 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7420 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7421
7422 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
7423 // Adjust only if Op1 and Op2 are GPRs.
7424 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7425 MRC.contains(Op2.getReg())) {
7426 unsigned Reg1 = Op1.getReg();
7427 unsigned Reg2 = Op2.getReg();
7428 unsigned Rt = MRI->getEncodingValue(Reg1);
7429 unsigned Rt2 = MRI->getEncodingValue(Reg2);
7430
7431 // Rt2 must be Rt + 1 and Rt must be even.
7432 if (Rt + 1 != Rt2 || (Rt & 1)) {
7433 return Error(Op2.getStartLoc(),
7434 isLoad ? "destination operands must be sequential"
7435 : "source operands must be sequential");
7436 }
7437 unsigned NewReg = MRI->getMatchingSuperReg(
7438 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
7439 Operands[Idx] =
7440 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
7441 Operands.erase(Operands.begin() + Idx + 1);
7442 }
7443 }
7444
7445 // GNU Assembler extension (compatibility).
7446 fixupGNULDRDAlias(Mnemonic, Operands);
7447
7448 // FIXME: As said above, this is all a pretty gross hack. This instruction
7449 // does not fit with other "subs" and tblgen.
7450 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
7451 // so the Mnemonic is the original name "subs" and delete the predicate
7452 // operand so it will match the table entry.
7453 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
7454 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7455 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
7456 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
7457 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7458 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
7459 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
7460 Operands.erase(Operands.begin() + 1);
7461 }
7462 return false;
7463}
7464
7465// Validate context-sensitive operand constraints.
7466
7467// return 'true' if register list contains non-low GPR registers,
7468// 'false' otherwise. If Reg is in the register list or is HiReg, set
7469// 'containsReg' to true.
7470static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7471 unsigned Reg, unsigned HiReg,
7472 bool &containsReg) {
7473 containsReg = false;
7474 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7475 unsigned OpReg = Inst.getOperand(i).getReg();
7476 if (OpReg == Reg)
7477 containsReg = true;
7478 // Anything other than a low register isn't legal here.
7479 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7480 return true;
7481 }
7482 return false;
7483}
7484
7485// Check if the specified regisgter is in the register list of the inst,
7486// starting at the indicated operand number.
7487static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7488 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
7489 unsigned OpReg = Inst.getOperand(i).getReg();
7490 if (OpReg == Reg)
7491 return true;
7492 }
7493 return false;
7494}
7495
7496// Return true if instruction has the interesting property of being
7497// allowed in IT blocks, but not being predicable.
7498static bool instIsBreakpoint(const MCInst &Inst) {
7499 return Inst.getOpcode() == ARM::tBKPT ||
7500 Inst.getOpcode() == ARM::BKPT ||
7501 Inst.getOpcode() == ARM::tHLT ||
7502 Inst.getOpcode() == ARM::HLT;
7503}
7504
7505bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7506 const OperandVector &Operands,
7507 unsigned ListNo, bool IsARPop) {
7508 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7509 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7510
7511 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7512 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7513 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7514
7515 if (!IsARPop && ListContainsSP)
7516 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7517 "SP may not be in the register list");
7518 else if (ListContainsPC && ListContainsLR)
7519 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7520 "PC and LR may not be in the register list simultaneously");
7521 return false;
7522}
7523
7524bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7525 const OperandVector &Operands,
7526 unsigned ListNo) {
7527 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7528 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7529
7530 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7531 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7532
7533 if (ListContainsSP && ListContainsPC)
7534 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7535 "SP and PC may not be in the register list");
7536 else if (ListContainsSP)
7537 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7538 "SP may not be in the register list");
7539 else if (ListContainsPC)
7540 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7541 "PC may not be in the register list");
7542 return false;
7543}
7544
7545bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7546 const OperandVector &Operands,
7547 bool Load, bool ARMMode, bool Writeback) {
7548 unsigned RtIndex = Load || !Writeback ? 0 : 1;
7549 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7550 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7551
7552 if (ARMMode) {
7553 // Rt can't be R14.
7554 if (Rt == 14)
7555 return Error(Operands[3]->getStartLoc(),
7556 "Rt can't be R14");
7557
7558 // Rt must be even-numbered.
7559 if ((Rt & 1) == 1)
7560 return Error(Operands[3]->getStartLoc(),
7561 "Rt must be even-numbered");
7562
7563 // Rt2 must be Rt + 1.
7564 if (Rt2 != Rt + 1) {
7565 if (Load)
7566 return Error(Operands[3]->getStartLoc(),
7567 "destination operands must be sequential");
7568 else
7569 return Error(Operands[3]->getStartLoc(),
7570 "source operands must be sequential");
7571 }
7572
7573 // FIXME: Diagnose m == 15
7574 // FIXME: Diagnose ldrd with m == t || m == t2.
7575 }
7576
7577 if (!ARMMode && Load) {
7578 if (Rt2 == Rt)
7579 return Error(Operands[3]->getStartLoc(),
7580 "destination operands can't be identical");
7581 }
7582
7583 if (Writeback) {
7584 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7585
7586 if (Rn == Rt || Rn == Rt2) {
7587 if (Load)
7588 return Error(Operands[3]->getStartLoc(),
7589 "base register needs to be different from destination "
7590 "registers");
7591 else
7592 return Error(Operands[3]->getStartLoc(),
7593 "source register and base register can't be identical");
7594 }
7595
7596 // FIXME: Diagnose ldrd/strd with writeback and n == 15.
7597 // (Except the immediate form of ldrd?)
7598 }
7599
7600 return false;
7601}
7602
7603static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7604 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7605 if (ARM::isVpred(MCID.OpInfo[i].OperandType))
7606 return i;
7607 }
7608 return -1;
7609}
7610
7611static bool isVectorPredicable(const MCInstrDesc &MCID) {
7612 return findFirstVectorPredOperandIdx(MCID) != -1;
7613}
7614
7615// FIXME: We would really like to be able to tablegen'erate this.
7616bool ARMAsmParser::validateInstruction(MCInst &Inst,
7617 const OperandVector &Operands) {
7618 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7619 SMLoc Loc = Operands[0]->getStartLoc();
7620
7621 // Check the IT block state first.
7622 // NOTE: BKPT and HLT instructions have the interesting property of being
7623 // allowed in IT blocks, but not being predicable. They just always execute.
7624 if (inITBlock() && !instIsBreakpoint(Inst)) {
7625 // The instruction must be predicable.
7626 if (!MCID.isPredicable())
7627 return Error(Loc, "instructions in IT block must be predicable");
7628 ARMCC::CondCodes Cond = ARMCC::CondCodes(
7629 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
7630 if (Cond != currentITCond()) {
7631 // Find the condition code Operand to get its SMLoc information.
7632 SMLoc CondLoc;
7633 for (unsigned I = 1; I < Operands.size(); ++I)
7634 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7635 CondLoc = Operands[I]->getStartLoc();
7636 return Error(CondLoc, "incorrect condition in IT block; got '" +
7637 StringRef(ARMCondCodeToString(Cond)) +
7638 "', but expected '" +
7639 ARMCondCodeToString(currentITCond()) + "'");
7640 }
7641 // Check for non-'al' condition codes outside of the IT block.
7642 } else if (isThumbTwo() && MCID.isPredicable() &&
7643 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7644 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7645 Inst.getOpcode() != ARM::t2Bcc &&
7646 Inst.getOpcode() != ARM::t2BFic) {
7647 return Error(Loc, "predicated instructions must be in IT block");
7648 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7649 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7650 ARMCC::AL) {
7651 return Warning(Loc, "predicated instructions should be in IT block");
7652 } else if (!MCID.isPredicable()) {
7653 // Check the instruction doesn't have a predicate operand anyway
7654 // that it's not allowed to use. Sometimes this happens in order
7655 // to keep instructions the same shape even though one cannot
7656 // legally be predicated, e.g. vmul.f16 vs vmul.f32.
7657 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7658 if (MCID.OpInfo[i].isPredicate()) {
7659 if (Inst.getOperand(i).getImm() != ARMCC::AL)
7660 return Error(Loc, "instruction is not predicable");
7661 break;
7662 }
7663 }
7664 }
7665
7666 // PC-setting instructions in an IT block, but not the last instruction of
7667 // the block, are UNPREDICTABLE.
7668 if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
7669 return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
7670 }
7671
7672 if (inVPTBlock() && !instIsBreakpoint(Inst)) {
7673 unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition);
7674 if (!isVectorPredicable(MCID))
7675 return Error(Loc, "instruction in VPT block must be predicable");
7676 unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
7677 unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
7678 if (Pred != VPTPred) {
7679 SMLoc PredLoc;
7680 for (unsigned I = 1; I < Operands.size(); ++I)
7681 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7682 PredLoc = Operands[I]->getStartLoc();
7683 return Error(PredLoc, "incorrect predication in VPT block; got '" +
7684 StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
7685 "', but expected '" +
7686 ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
7687 }
7688 }
7689 else if (isVectorPredicable(MCID) &&
7690 Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
7691 ARMVCC::None)
7692 return Error(Loc, "VPT predicated instructions must be in VPT block");
7693
7694 const unsigned Opcode = Inst.getOpcode();
7695 switch (Opcode) {
7696 case ARM::t2IT: {
7697 // Encoding is unpredictable if it ever results in a notional 'NV'
7698 // predicate. Since we don't parse 'NV' directly this means an 'AL'
7699 // predicate with an "else" mask bit.
7700 unsigned Cond = Inst.getOperand(0).getImm();
7701 unsigned Mask = Inst.getOperand(1).getImm();
7702
7703 // Conditions only allowing a 't' are those with no set bit except
7704 // the lowest-order one that indicates the end of the sequence. In
7705 // other words, powers of 2.
7706 if (Cond == ARMCC::AL && countPopulation(Mask) != 1)
7707 return Error(Loc, "unpredictable IT predicate sequence");
7708 break;
7709 }
7710 case ARM::LDRD:
7711 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7712 /*Writeback*/false))
7713 return true;
7714 break;
7715 case ARM::LDRD_PRE:
7716 case ARM::LDRD_POST:
7717 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7718 /*Writeback*/true))
7719 return true;
7720 break;
7721 case ARM::t2LDRDi8:
7722 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7723 /*Writeback*/false))
7724 return true;
7725 break;
7726 case ARM::t2LDRD_PRE:
7727 case ARM::t2LDRD_POST:
7728 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7729 /*Writeback*/true))
7730 return true;
7731 break;
7732 case ARM::t2BXJ: {
7733 const unsigned RmReg = Inst.getOperand(0).getReg();
7734 // Rm = SP is no longer unpredictable in v8-A
7735 if (RmReg == ARM::SP && !hasV8Ops())
7736 return Error(Operands[2]->getStartLoc(),
7737 "r13 (SP) is an unpredictable operand to BXJ");
7738 return false;
7739 }
7740 case ARM::STRD:
7741 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7742 /*Writeback*/false))
7743 return true;
7744 break;
7745 case ARM::STRD_PRE:
7746 case ARM::STRD_POST:
7747 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7748 /*Writeback*/true))
7749 return true;
7750 break;
7751 case ARM::t2STRD_PRE:
7752 case ARM::t2STRD_POST:
7753 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
7754 /*Writeback*/true))
7755 return true;
7756 break;
7757 case ARM::STR_PRE_IMM:
7758 case ARM::STR_PRE_REG:
7759 case ARM::t2STR_PRE:
7760 case ARM::STR_POST_IMM:
7761 case ARM::STR_POST_REG:
7762 case ARM::t2STR_POST:
7763 case ARM::STRH_PRE:
7764 case ARM::t2STRH_PRE:
7765 case ARM::STRH_POST:
7766 case ARM::t2STRH_POST:
7767 case ARM::STRB_PRE_IMM:
7768 case ARM::STRB_PRE_REG:
7769 case ARM::t2STRB_PRE:
7770 case ARM::STRB_POST_IMM:
7771 case ARM::STRB_POST_REG:
7772 case ARM::t2STRB_POST: {
7773 // Rt must be different from Rn.
7774 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7775 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7776
7777 if (Rt == Rn)
7778 return Error(Operands[3]->getStartLoc(),
7779 "source register and base register can't be identical");
7780 return false;
7781 }
7782 case ARM::t2LDR_PRE_imm:
7783 case ARM::t2LDR_POST_imm:
7784 case ARM::t2STR_PRE_imm:
7785 case ARM::t2STR_POST_imm: {
7786 // Rt must be different from Rn.
7787 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7788 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7789
7790 if (Rt == Rn)
7791 return Error(Operands[3]->getStartLoc(),
7792 "destination register and base register can't be identical");
7793 if (Inst.getOpcode() == ARM::t2LDR_POST_imm ||
7794 Inst.getOpcode() == ARM::t2STR_POST_imm) {
7795 int Imm = Inst.getOperand(2).getImm();
7796 if (Imm > 255 || Imm < -255)
7797 return Error(Operands[5]->getStartLoc(),
7798 "operand must be in range [-255, 255]");
7799 }
7800 if (Inst.getOpcode() == ARM::t2STR_PRE_imm ||
7801 Inst.getOpcode() == ARM::t2STR_POST_imm) {
7802 if (Inst.getOperand(0).getReg() == ARM::PC) {
7803 return Error(Operands[3]->getStartLoc(),
7804 "operand must be a register in range [r0, r14]");
7805 }
7806 }
7807 return false;
7808 }
7809 case ARM::LDR_PRE_IMM:
7810 case ARM::LDR_PRE_REG:
7811 case ARM::t2LDR_PRE:
7812 case ARM::LDR_POST_IMM:
7813 case ARM::LDR_POST_REG:
7814 case ARM::t2LDR_POST:
7815 case ARM::LDRH_PRE:
7816 case ARM::t2LDRH_PRE:
7817 case ARM::LDRH_POST:
7818 case ARM::t2LDRH_POST:
7819 case ARM::LDRSH_PRE:
7820 case ARM::t2LDRSH_PRE:
7821 case ARM::LDRSH_POST:
7822 case ARM::t2LDRSH_POST:
7823 case ARM::LDRB_PRE_IMM:
7824 case ARM::LDRB_PRE_REG:
7825 case ARM::t2LDRB_PRE:
7826 case ARM::LDRB_POST_IMM:
7827 case ARM::LDRB_POST_REG:
7828 case ARM::t2LDRB_POST:
7829 case ARM::LDRSB_PRE:
7830 case ARM::t2LDRSB_PRE:
7831 case ARM::LDRSB_POST:
7832 case ARM::t2LDRSB_POST: {
7833 // Rt must be different from Rn.
7834 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7835 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7836
7837 if (Rt == Rn)
7838 return Error(Operands[3]->getStartLoc(),
7839 "destination register and base register can't be identical");
7840 return false;
7841 }
7842
7843 case ARM::MVE_VLDRBU8_rq:
7844 case ARM::MVE_VLDRBU16_rq:
7845 case ARM::MVE_VLDRBS16_rq:
7846 case ARM::MVE_VLDRBU32_rq:
7847 case ARM::MVE_VLDRBS32_rq:
7848 case ARM::MVE_VLDRHU16_rq:
7849 case ARM::MVE_VLDRHU16_rq_u:
7850 case ARM::MVE_VLDRHU32_rq:
7851 case ARM::MVE_VLDRHU32_rq_u:
7852 case ARM::MVE_VLDRHS32_rq:
7853 case ARM::MVE_VLDRHS32_rq_u:
7854 case ARM::MVE_VLDRWU32_rq:
7855 case ARM::MVE_VLDRWU32_rq_u:
7856 case ARM::MVE_VLDRDU64_rq:
7857 case ARM::MVE_VLDRDU64_rq_u:
7858 case ARM::MVE_VLDRWU32_qi:
7859 case ARM::MVE_VLDRWU32_qi_pre:
7860 case ARM::MVE_VLDRDU64_qi:
7861 case ARM::MVE_VLDRDU64_qi_pre: {
7862 // Qd must be different from Qm.
7863 unsigned QdIdx = 0, QmIdx = 2;
7864 bool QmIsPointer = false;
7865 switch (Opcode) {
7866 case ARM::MVE_VLDRWU32_qi:
7867 case ARM::MVE_VLDRDU64_qi:
7868 QmIdx = 1;
7869 QmIsPointer = true;
7870 break;
7871 case ARM::MVE_VLDRWU32_qi_pre:
7872 case ARM::MVE_VLDRDU64_qi_pre:
7873 QdIdx = 1;
7874 QmIsPointer = true;
7875 break;
7876 }
7877
7878 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7879 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7880
7881 if (Qd == Qm) {
7882 return Error(Operands[3]->getStartLoc(),
7883 Twine("destination vector register and vector ") +
7884 (QmIsPointer ? "pointer" : "offset") +
7885 " register can't be identical");
7886 }
7887 return false;
7888 }
7889
7890 case ARM::SBFX:
7891 case ARM::t2SBFX:
7892 case ARM::UBFX:
7893 case ARM::t2UBFX: {
7894 // Width must be in range [1, 32-lsb].
7895 unsigned LSB = Inst.getOperand(2).getImm();
7896 unsigned Widthm1 = Inst.getOperand(3).getImm();
7897 if (Widthm1 >= 32 - LSB)
7898 return Error(Operands[5]->getStartLoc(),
7899 "bitfield width must be in range [1,32-lsb]");
7900 return false;
7901 }
7902 // Notionally handles ARM::tLDMIA_UPD too.
7903 case ARM::tLDMIA: {
7904 // If we're parsing Thumb2, the .w variant is available and handles
7905 // most cases that are normally illegal for a Thumb1 LDM instruction.
7906 // We'll make the transformation in processInstruction() if necessary.
7907 //
7908 // Thumb LDM instructions are writeback iff the base register is not
7909 // in the register list.
7910 unsigned Rn = Inst.getOperand(0).getReg();
7911 bool HasWritebackToken =
7912 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7913 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7914 bool ListContainsBase;
7915 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
7916 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
7917 "registers must be in range r0-r7");
7918 // If we should have writeback, then there should be a '!' token.
7919 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
7920 return Error(Operands[2]->getStartLoc(),
7921 "writeback operator '!' expected");
7922 // If we should not have writeback, there must not be a '!'. This is
7923 // true even for the 32-bit wide encodings.
7924 if (ListContainsBase && HasWritebackToken)
7925 return Error(Operands[3]->getStartLoc(),
7926 "writeback operator '!' not allowed when base register "
7927 "in register list");
7928
7929 if (validatetLDMRegList(Inst, Operands, 3))
7930 return true;
7931 break;
7932 }
7933 case ARM::LDMIA_UPD:
7934 case ARM::LDMDB_UPD:
7935 case ARM::LDMIB_UPD:
7936 case ARM::LDMDA_UPD:
7937 // ARM variants loading and updating the same register are only officially
7938 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
7939 if (!hasV7Ops())
7940 break;
7941 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7942 return Error(Operands.back()->getStartLoc(),
7943 "writeback register not allowed in register list");
7944 break;
7945 case ARM::t2LDMIA:
7946 case ARM::t2LDMDB:
7947 if (validatetLDMRegList(Inst, Operands, 3))
7948 return true;
7949 break;
7950 case ARM::t2STMIA:
7951 case ARM::t2STMDB:
7952 if (validatetSTMRegList(Inst, Operands, 3))
7953 return true;
7954 break;
7955 case ARM::t2LDMIA_UPD:
7956 case ARM::t2LDMDB_UPD:
7957 case ARM::t2STMIA_UPD:
7958 case ARM::t2STMDB_UPD:
7959 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7960 return Error(Operands.back()->getStartLoc(),
7961 "writeback register not allowed in register list");
7962
7963 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
7964 if (validatetLDMRegList(Inst, Operands, 3))
7965 return true;
7966 } else {
7967 if (validatetSTMRegList(Inst, Operands, 3))
7968 return true;
7969 }
7970 break;
7971
7972 case ARM::sysLDMIA_UPD:
7973 case ARM::sysLDMDA_UPD:
7974 case ARM::sysLDMDB_UPD:
7975 case ARM::sysLDMIB_UPD:
7976 if (!listContainsReg(Inst, 3, ARM::PC))
7977 return Error(Operands[4]->getStartLoc(),
7978 "writeback register only allowed on system LDM "
7979 "if PC in register-list");
7980 break;
7981 case ARM::sysSTMIA_UPD:
7982 case ARM::sysSTMDA_UPD:
7983 case ARM::sysSTMDB_UPD:
7984 case ARM::sysSTMIB_UPD:
7985 return Error(Operands[2]->getStartLoc(),
7986 "system STM cannot have writeback register");
7987 case ARM::tMUL:
7988 // The second source operand must be the same register as the destination
7989 // operand.
7990 //
7991 // In this case, we must directly check the parsed operands because the
7992 // cvtThumbMultiply() function is written in such a way that it guarantees
7993 // this first statement is always true for the new Inst. Essentially, the
7994 // destination is unconditionally copied into the second source operand
7995 // without checking to see if it matches what we actually parsed.
7996 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
7997 ((ARMOperand &)*Operands[5]).getReg()) &&
7998 (((ARMOperand &)*Operands[3]).getReg() !=
7999 ((ARMOperand &)*Operands[4]).getReg())) {
8000 return Error(Operands[3]->getStartLoc(),
8001 "destination register must match source register");
8002 }
8003 break;
8004
8005 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
8006 // so only issue a diagnostic for thumb1. The instructions will be
8007 // switched to the t2 encodings in processInstruction() if necessary.
8008 case ARM::tPOP: {
8009 bool ListContainsBase;
8010 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
8011 !isThumbTwo())
8012 return Error(Operands[2]->getStartLoc(),
8013 "registers must be in range r0-r7 or pc");
8014 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
8015 return true;
8016 break;
8017 }
8018 case ARM::tPUSH: {
8019 bool ListContainsBase;
8020 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
8021 !isThumbTwo())
8022 return Error(Operands[2]->getStartLoc(),
8023 "registers must be in range r0-r7 or lr");
8024 if (validatetSTMRegList(Inst, Operands, 2))
8025 return true;
8026 break;
8027 }
8028 case ARM::tSTMIA_UPD: {
8029 bool ListContainsBase, InvalidLowList;
8030 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
8031 0, ListContainsBase);
8032 if (InvalidLowList && !isThumbTwo())
8033 return Error(Operands[4]->getStartLoc(),
8034 "registers must be in range r0-r7");
8035
8036 // This would be converted to a 32-bit stm, but that's not valid if the
8037 // writeback register is in the list.
8038 if (InvalidLowList && ListContainsBase)
8039 return Error(Operands[4]->getStartLoc(),
8040 "writeback operator '!' not allowed when base register "
8041 "in register list");
8042
8043 if (validatetSTMRegList(Inst, Operands, 4))
8044 return true;
8045 break;
8046 }
8047 case ARM::tADDrSP:
8048 // If the non-SP source operand and the destination operand are not the
8049 // same, we need thumb2 (for the wide encoding), or we have an error.
8050 if (!isThumbTwo() &&
8051 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8052 return Error(Operands[4]->getStartLoc(),
8053 "source register must be the same as destination");
8054 }
8055 break;
8056
8057 case ARM::t2ADDrr:
8058 case ARM::t2ADDrs:
8059 case ARM::t2SUBrr:
8060 case ARM::t2SUBrs:
8061 if (Inst.getOperand(0).getReg() == ARM::SP &&
8062 Inst.getOperand(1).getReg() != ARM::SP)
8063 return Error(Operands[4]->getStartLoc(),
8064 "source register must be sp if destination is sp");
8065 break;
8066
8067 // Final range checking for Thumb unconditional branch instructions.
8068 case ARM::tB:
8069 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
8070 return Error(Operands[2]->getStartLoc(), "branch target out of range");
8071 break;
8072 case ARM::t2B: {
8073 int op = (Operands[2]->isImm()) ? 2 : 3;
8074 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]);
8075 // Delay the checks of symbolic expressions until they are resolved.
8076 if (!isa<MCBinaryExpr>(Operand.getImm()) &&
8077 !Operand.isSignedOffset<24, 1>())
8078 return Error(Operands[op]->getStartLoc(), "branch target out of range");
8079 break;
8080 }
8081 // Final range checking for Thumb conditional branch instructions.
8082 case ARM::tBcc:
8083 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
8084 return Error(Operands[2]->getStartLoc(), "branch target out of range");
8085 break;
8086 case ARM::t2Bcc: {
8087 int Op = (Operands[2]->isImm()) ? 2 : 3;
8088 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
8089 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
8090 break;
8091 }
8092 case ARM::tCBZ:
8093 case ARM::tCBNZ: {
8094 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
8095 return Error(Operands[2]->getStartLoc(), "branch target out of range");
8096 break;
8097 }
8098 case ARM::MOVi16:
8099 case ARM::MOVTi16:
8100 case ARM::t2MOVi16:
8101 case ARM::t2MOVTi16:
8102 {
8103 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
8104 // especially when we turn it into a movw and the expression <symbol> does
8105 // not have a :lower16: or :upper16 as part of the expression. We don't
8106 // want the behavior of silently truncating, which can be unexpected and
8107 // lead to bugs that are difficult to find since this is an easy mistake
8108 // to make.
8109 int i = (Operands[3]->isImm()) ? 3 : 4;
8110 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
8111 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
8112 if (CE) break;
8113 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
8114 if (!E) break;
8115 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
8116 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
8117 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
8118 return Error(
8119 Op.getStartLoc(),
8120 "immediate expression for mov requires :lower16: or :upper16");
8121 break;
8122 }
8123 case ARM::HINT:
8124 case ARM::t2HINT: {
8125 unsigned Imm8 = Inst.getOperand(0).getImm();
8126 unsigned Pred = Inst.getOperand(1).getImm();
8127 // ESB is not predicable (pred must be AL). Without the RAS extension, this
8128 // behaves as any other unallocated hint.
8129 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
8130 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
8131 "predicable, but condition "
8132 "code specified");
8133 if (Imm8 == 0x14 && Pred != ARMCC::AL)
8134 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
8135 "predicable, but condition "
8136 "code specified");
8137 break;
8138 }
8139 case ARM::t2BFi:
8140 case ARM::t2BFr:
8141 case ARM::t2BFLi:
8142 case ARM::t2BFLr: {
8143 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
8144 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8145 return Error(Operands[2]->getStartLoc(),
8146 "branch location out of range or not a multiple of 2");
8147
8148 if (Opcode == ARM::t2BFi) {
8149 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
8150 return Error(Operands[3]->getStartLoc(),
8151 "branch target out of range or not a multiple of 2");
8152 } else if (Opcode == ARM::t2BFLi) {
8153 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
8154 return Error(Operands[3]->getStartLoc(),
8155 "branch target out of range or not a multiple of 2");
8156 }
8157 break;
8158 }
8159 case ARM::t2BFic: {
8160 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
8161 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8162 return Error(Operands[1]->getStartLoc(),
8163 "branch location out of range or not a multiple of 2");
8164
8165 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
8166 return Error(Operands[2]->getStartLoc(),
8167 "branch target out of range or not a multiple of 2");
8168
8169 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&(static_cast <bool> (Inst.getOperand(0).isImm() == Inst
.getOperand(2).isImm() && "branch location and else branch target should either both be "
"immediates or both labels") ? void (0) : __assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8171, __extension__
__PRETTY_FUNCTION__))
8170 "branch location and else branch target should either both be "(static_cast <bool> (Inst.getOperand(0).isImm() == Inst
.getOperand(2).isImm() && "branch location and else branch target should either both be "
"immediates or both labels") ? void (0) : __assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8171, __extension__
__PRETTY_FUNCTION__))
8171 "immediates or both labels")(static_cast <bool> (Inst.getOperand(0).isImm() == Inst
.getOperand(2).isImm() && "branch location and else branch target should either both be "
"immediates or both labels") ? void (0) : __assert_fail ("Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && \"branch location and else branch target should either both be \" \"immediates or both labels\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8171, __extension__
__PRETTY_FUNCTION__))
;
8172
8173 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
8174 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
8175 if (Diff != 4 && Diff != 2)
8176 return Error(
8177 Operands[3]->getStartLoc(),
8178 "else branch target must be 2 or 4 greater than the branch location");
8179 }
8180 break;
8181 }
8182 case ARM::t2CLRM: {
8183 for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
8184 if (Inst.getOperand(i).isReg() &&
8185 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
8186 Inst.getOperand(i).getReg())) {
8187 return Error(Operands[2]->getStartLoc(),
8188 "invalid register in register list. Valid registers are "
8189 "r0-r12, lr/r14 and APSR.");
8190 }
8191 }
8192 break;
8193 }
8194 case ARM::DSB:
8195 case ARM::t2DSB: {
8196
8197 if (Inst.getNumOperands() < 2)
8198 break;
8199
8200 unsigned Option = Inst.getOperand(0).getImm();
8201 unsigned Pred = Inst.getOperand(1).getImm();
8202
8203 // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
8204 if (Option == 0 && Pred != ARMCC::AL)
8205 return Error(Operands[1]->getStartLoc(),
8206 "instruction 'ssbb' is not predicable, but condition code "
8207 "specified");
8208 if (Option == 4 && Pred != ARMCC::AL)
8209 return Error(Operands[1]->getStartLoc(),
8210 "instruction 'pssbb' is not predicable, but condition code "
8211 "specified");
8212 break;
8213 }
8214 case ARM::VMOVRRS: {
8215 // Source registers must be sequential.
8216 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
8217 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
8218 if (Sm1 != Sm + 1)
8219 return Error(Operands[5]->getStartLoc(),
8220 "source operands must be sequential");
8221 break;
8222 }
8223 case ARM::VMOVSRR: {
8224 // Destination registers must be sequential.
8225 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
8226 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
8227 if (Sm1 != Sm + 1)
8228 return Error(Operands[3]->getStartLoc(),
8229 "destination operands must be sequential");
8230 break;
8231 }
8232 case ARM::VLDMDIA:
8233 case ARM::VSTMDIA: {
8234 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
8235 auto &RegList = Op.getRegList();
8236 if (RegList.size() < 1 || RegList.size() > 16)
8237 return Error(Operands[3]->getStartLoc(),
8238 "list of registers must be at least 1 and at most 16");
8239 break;
8240 }
8241 case ARM::MVE_VQDMULLs32bh:
8242 case ARM::MVE_VQDMULLs32th:
8243 case ARM::MVE_VCMULf32:
8244 case ARM::MVE_VMULLBs32:
8245 case ARM::MVE_VMULLTs32:
8246 case ARM::MVE_VMULLBu32:
8247 case ARM::MVE_VMULLTu32: {
8248 if (Operands[3]->getReg() == Operands[4]->getReg()) {
8249 return Error (Operands[3]->getStartLoc(),
8250 "Qd register and Qn register can't be identical");
8251 }
8252 if (Operands[3]->getReg() == Operands[5]->getReg()) {
8253 return Error (Operands[3]->getStartLoc(),
8254 "Qd register and Qm register can't be identical");
8255 }
8256 break;
8257 }
8258 case ARM::MVE_VMOV_rr_q: {
8259 if (Operands[4]->getReg() != Operands[6]->getReg())
8260 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
8261 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
8262 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
8263 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8264 break;
8265 }
8266 case ARM::MVE_VMOV_q_rr: {
8267 if (Operands[2]->getReg() != Operands[4]->getReg())
8268 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
8269 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
8270 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
8271 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8272 break;
8273 }
8274 case ARM::UMAAL:
8275 case ARM::UMLAL:
8276 case ARM::UMULL:
8277 case ARM::t2UMAAL:
8278 case ARM::t2UMLAL:
8279 case ARM::t2UMULL:
8280 case ARM::SMLAL:
8281 case ARM::SMLALBB:
8282 case ARM::SMLALBT:
8283 case ARM::SMLALD:
8284 case ARM::SMLALDX:
8285 case ARM::SMLALTB:
8286 case ARM::SMLALTT:
8287 case ARM::SMLSLD:
8288 case ARM::SMLSLDX:
8289 case ARM::SMULL:
8290 case ARM::t2SMLAL:
8291 case ARM::t2SMLALBB:
8292 case ARM::t2SMLALBT:
8293 case ARM::t2SMLALD:
8294 case ARM::t2SMLALDX:
8295 case ARM::t2SMLALTB:
8296 case ARM::t2SMLALTT:
8297 case ARM::t2SMLSLD:
8298 case ARM::t2SMLSLDX:
8299 case ARM::t2SMULL: {
8300 unsigned RdHi = Inst.getOperand(0).getReg();
8301 unsigned RdLo = Inst.getOperand(1).getReg();
8302 if(RdHi == RdLo) {
8303 return Error(Loc,
8304 "unpredictable instruction, RdHi and RdLo must be different");
8305 }
8306 break;
8307 }
8308
8309 case ARM::CDE_CX1:
8310 case ARM::CDE_CX1A:
8311 case ARM::CDE_CX1D:
8312 case ARM::CDE_CX1DA:
8313 case ARM::CDE_CX2:
8314 case ARM::CDE_CX2A:
8315 case ARM::CDE_CX2D:
8316 case ARM::CDE_CX2DA:
8317 case ARM::CDE_CX3:
8318 case ARM::CDE_CX3A:
8319 case ARM::CDE_CX3D:
8320 case ARM::CDE_CX3DA:
8321 case ARM::CDE_VCX1_vec:
8322 case ARM::CDE_VCX1_fpsp:
8323 case ARM::CDE_VCX1_fpdp:
8324 case ARM::CDE_VCX1A_vec:
8325 case ARM::CDE_VCX1A_fpsp:
8326 case ARM::CDE_VCX1A_fpdp:
8327 case ARM::CDE_VCX2_vec:
8328 case ARM::CDE_VCX2_fpsp:
8329 case ARM::CDE_VCX2_fpdp:
8330 case ARM::CDE_VCX2A_vec:
8331 case ARM::CDE_VCX2A_fpsp:
8332 case ARM::CDE_VCX2A_fpdp:
8333 case ARM::CDE_VCX3_vec:
8334 case ARM::CDE_VCX3_fpsp:
8335 case ARM::CDE_VCX3_fpdp:
8336 case ARM::CDE_VCX3A_vec:
8337 case ARM::CDE_VCX3A_fpsp:
8338 case ARM::CDE_VCX3A_fpdp: {
8339 assert(Inst.getOperand(1).isImm() &&(static_cast <bool> (Inst.getOperand(1).isImm() &&
"CDE operand 1 must be a coprocessor ID") ? void (0) : __assert_fail
("Inst.getOperand(1).isImm() && \"CDE operand 1 must be a coprocessor ID\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8340, __extension__
__PRETTY_FUNCTION__))
8340 "CDE operand 1 must be a coprocessor ID")(static_cast <bool> (Inst.getOperand(1).isImm() &&
"CDE operand 1 must be a coprocessor ID") ? void (0) : __assert_fail
("Inst.getOperand(1).isImm() && \"CDE operand 1 must be a coprocessor ID\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8340, __extension__
__PRETTY_FUNCTION__))
;
8341 int64_t Coproc = Inst.getOperand(1).getImm();
8342 if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI))
8343 return Error(Operands[1]->getStartLoc(),
8344 "coprocessor must be configured as CDE");
8345 else if (Coproc >= 8)
8346 return Error(Operands[1]->getStartLoc(),
8347 "coprocessor must be in the range [p0, p7]");
8348 break;
8349 }
8350
8351 case ARM::t2CDP:
8352 case ARM::t2CDP2:
8353 case ARM::t2LDC2L_OFFSET:
8354 case ARM::t2LDC2L_OPTION:
8355 case ARM::t2LDC2L_POST:
8356 case ARM::t2LDC2L_PRE:
8357 case ARM::t2LDC2_OFFSET:
8358 case ARM::t2LDC2_OPTION:
8359 case ARM::t2LDC2_POST:
8360 case ARM::t2LDC2_PRE:
8361 case ARM::t2LDCL_OFFSET:
8362 case ARM::t2LDCL_OPTION:
8363 case ARM::t2LDCL_POST:
8364 case ARM::t2LDCL_PRE:
8365 case ARM::t2LDC_OFFSET:
8366 case ARM::t2LDC_OPTION:
8367 case ARM::t2LDC_POST:
8368 case ARM::t2LDC_PRE:
8369 case ARM::t2MCR:
8370 case ARM::t2MCR2:
8371 case ARM::t2MCRR:
8372 case ARM::t2MCRR2:
8373 case ARM::t2MRC:
8374 case ARM::t2MRC2:
8375 case ARM::t2MRRC:
8376 case ARM::t2MRRC2:
8377 case ARM::t2STC2L_OFFSET:
8378 case ARM::t2STC2L_OPTION:
8379 case ARM::t2STC2L_POST:
8380 case ARM::t2STC2L_PRE:
8381 case ARM::t2STC2_OFFSET:
8382 case ARM::t2STC2_OPTION:
8383 case ARM::t2STC2_POST:
8384 case ARM::t2STC2_PRE:
8385 case ARM::t2STCL_OFFSET:
8386 case ARM::t2STCL_OPTION:
8387 case ARM::t2STCL_POST:
8388 case ARM::t2STCL_PRE:
8389 case ARM::t2STC_OFFSET:
8390 case ARM::t2STC_OPTION:
8391 case ARM::t2STC_POST:
8392 case ARM::t2STC_PRE: {
8393 unsigned Opcode = Inst.getOpcode();
8394 // Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags,
8395 // CopInd is the index of the coprocessor operand.
8396 size_t CopInd = 0;
8397 if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2)
8398 CopInd = 2;
8399 else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2)
8400 CopInd = 1;
8401 assert(Inst.getOperand(CopInd).isImm() &&(static_cast <bool> (Inst.getOperand(CopInd).isImm() &&
"Operand must be a coprocessor ID") ? void (0) : __assert_fail
("Inst.getOperand(CopInd).isImm() && \"Operand must be a coprocessor ID\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8402, __extension__
__PRETTY_FUNCTION__))
8402 "Operand must be a coprocessor ID")(static_cast <bool> (Inst.getOperand(CopInd).isImm() &&
"Operand must be a coprocessor ID") ? void (0) : __assert_fail
("Inst.getOperand(CopInd).isImm() && \"Operand must be a coprocessor ID\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 8402, __extension__
__PRETTY_FUNCTION__))
;
8403 int64_t Coproc = Inst.getOperand(CopInd).getImm();
8404 // Operands[2] is the coprocessor operand at syntactic level
8405 if (ARM::isCDECoproc(Coproc, *STI))
8406 return Error(Operands[2]->getStartLoc(),
8407 "coprocessor must be configured as GCP");
8408 break;
8409 }
8410 }
8411
8412 return false;
8413}
8414
8415static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
8416 switch(Opc) {
8417 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 8417)
;
8418 // VST1LN
8419 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
8420 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8421 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8422 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
8423 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8424 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8425 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
8426 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
8427 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
8428
8429 // VST2LN
8430 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
8431 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8432 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8433 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8434 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8435
8436 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
8437 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8438 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8439 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8440 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8441
8442 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
8443 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
8444 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
8445 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
8446 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
8447
8448 // VST3LN
8449 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
8450 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8451 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8452 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
8453 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8454 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
8455 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8456 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8457 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
8458 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8459 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
8460 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
8461 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
8462 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
8463 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
8464
8465 // VST3
8466 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
8467 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8468 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8469 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
8470 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8471 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8472 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
8473 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8474 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8475 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
8476 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8477 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8478 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
8479 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
8480 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
8481 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
8482 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
8483 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
8484
8485 // VST4LN
8486 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8487 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8488 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8489 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
8490 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8491 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8492 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8493 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8494 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
8495 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8496 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
8497 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
8498 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
8499 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
8500 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
8501
8502 // VST4
8503 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8504 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8505 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8506 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8507 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8508 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8509 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8510 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8511 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8512 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8513 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8514 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8515 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
8516 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
8517 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
8518 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
8519 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
8520 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
8521 }
8522}
8523
8524static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
8525 switch(Opc) {
8526 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 8526)
;
8527 // VLD1LN
8528 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8529 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8530 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8531 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8532 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8533 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8534 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
8535 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
8536 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
8537
8538 // VLD2LN
8539 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8540 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8541 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8542 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
8543 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8544 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8545 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8546 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8547 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
8548 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8549 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
8550 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
8551 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
8552 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
8553 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
8554
8555 // VLD3DUP
8556 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8557 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8558 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8559 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
8560 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8561 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8562 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8563 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8564 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8565 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
8566 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8567 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8568 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
8569 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
8570 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
8571 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
8572 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
8573 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
8574
8575 // VLD3LN
8576 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8577 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8578 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8579 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
8580 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8581 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8582 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8583 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8584 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
8585 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8586 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
8587 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
8588 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
8589 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
8590 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
8591
8592 // VLD3
8593 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8594 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8595 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8596 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8597 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8598 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8599 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8600 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8601 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8602 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8603 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8604 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8605 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
8606 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
8607 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
8608 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
8609 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
8610 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
8611
8612 // VLD4LN
8613 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8614 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8615 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8616 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8617 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8618 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8619 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8620 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8621 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8622 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8623 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
8624 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
8625 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
8626 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
8627 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
8628
8629 // VLD4DUP
8630 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8631 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8632 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8633 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
8634 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
8635 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8636 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8637 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8638 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8639 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
8640 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
8641 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8642 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
8643 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
8644 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
8645 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
8646 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
8647 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
8648
8649 // VLD4
8650 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8651 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8652 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8653 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8654 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8655 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8656 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8657 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8658 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8659 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8660 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8661 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8662 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
8663 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
8664 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
8665 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
8666 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
8667 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
8668 }
8669}
8670
8671bool ARMAsmParser::processInstruction(MCInst &Inst,
8672 const OperandVector &Operands,
8673 MCStreamer &Out) {
8674 // Check if we have the wide qualifier, because if it's present we
8675 // must avoid selecting a 16-bit thumb instruction.
8676 bool HasWideQualifier = false;
8677 for (auto &Op : Operands) {
8678 ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
8679 if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
8680 HasWideQualifier = true;
8681 break;
8682 }
8683 }
8684
8685 switch (Inst.getOpcode()) {
8686 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
8687 case ARM::LDRT_POST:
8688 case ARM::LDRBT_POST: {
8689 const unsigned Opcode =
8690 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8691 : ARM::LDRBT_POST_IMM;
8692 MCInst TmpInst;
8693 TmpInst.setOpcode(Opcode);
8694 TmpInst.addOperand(Inst.getOperand(0));
8695 TmpInst.addOperand(Inst.getOperand(1));
8696 TmpInst.addOperand(Inst.getOperand(1));
8697 TmpInst.addOperand(MCOperand::createReg(0));
8698 TmpInst.addOperand(MCOperand::createImm(0));
8699 TmpInst.addOperand(Inst.getOperand(2));
8700 TmpInst.addOperand(Inst.getOperand(3));
8701 Inst = TmpInst;
8702 return true;
8703 }
8704 // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate.
8705 case ARM::LDRSBTii:
8706 case ARM::LDRHTii:
8707 case ARM::LDRSHTii: {
8708 MCInst TmpInst;
8709
8710 if (Inst.getOpcode() == ARM::LDRSBTii)
8711 TmpInst.setOpcode(ARM::LDRSBTi);
8712 else if (Inst.getOpcode() == ARM::LDRHTii)
8713 TmpInst.setOpcode(ARM::LDRHTi);
8714 else if (Inst.getOpcode() == ARM::LDRSHTii)
8715 TmpInst.setOpcode(ARM::LDRSHTi);
8716 TmpInst.addOperand(Inst.getOperand(0));
8717 TmpInst.addOperand(Inst.getOperand(1));
8718 TmpInst.addOperand(Inst.getOperand(1));
8719 TmpInst.addOperand(MCOperand::createImm(256));
8720 TmpInst.addOperand(Inst.getOperand(2));
8721 Inst = TmpInst;
8722 return true;
8723 }
8724 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
8725 case ARM::STRT_POST:
8726 case ARM::STRBT_POST: {
8727 const unsigned Opcode =
8728 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8729 : ARM::STRBT_POST_IMM;
8730 MCInst TmpInst;
8731 TmpInst.setOpcode(Opcode);
8732 TmpInst.addOperand(Inst.getOperand(1));
8733 TmpInst.addOperand(Inst.getOperand(0));
8734 TmpInst.addOperand(Inst.getOperand(1));
8735 TmpInst.addOperand(MCOperand::createReg(0));
8736 TmpInst.addOperand(MCOperand::createImm(0));
8737 TmpInst.addOperand(Inst.getOperand(2));
8738 TmpInst.addOperand(Inst.getOperand(3));
8739 Inst = TmpInst;
8740 return true;
8741 }
8742 // Alias for alternate form of 'ADR Rd, #imm' instruction.
8743 case ARM::ADDri: {
8744 if (Inst.getOperand(1).getReg() != ARM::PC ||
8745 Inst.getOperand(5).getReg() != 0 ||
8746 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
8747 return false;
8748 MCInst TmpInst;
8749 TmpInst.setOpcode(ARM::ADR);
8750 TmpInst.addOperand(Inst.getOperand(0));
8751 if (Inst.getOperand(2).isImm()) {
8752 // Immediate (mod_imm) will be in its encoded form, we must unencode it
8753 // before passing it to the ADR instruction.
8754 unsigned Enc = Inst.getOperand(2).getImm();
8755 TmpInst.addOperand(MCOperand::createImm(
8756 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8757 } else {
8758 // Turn PC-relative expression into absolute expression.
8759 // Reading PC provides the start of the current instruction + 8 and
8760 // the transform to adr is biased by that.
8761 MCSymbol *Dot = getContext().createTempSymbol();
8762 Out.emitLabel(Dot);
8763 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
8764 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
8765 MCSymbolRefExpr::VK_None,
8766 getContext());
8767 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
8768 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
8769 getContext());
8770 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
8771 getContext());
8772 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
8773 }
8774 TmpInst.addOperand(Inst.getOperand(3));
8775 TmpInst.addOperand(Inst.getOperand(4));
8776 Inst = TmpInst;
8777 return true;
8778 }
8779 // Aliases for imm syntax of LDR instructions.
8780 case ARM::t2LDR_PRE_imm:
8781 case ARM::t2LDR_POST_imm: {
8782 MCInst TmpInst;
8783 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE
8784 : ARM::t2LDR_POST);
8785 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8786 TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
8787 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8788 TmpInst.addOperand(Inst.getOperand(2)); // imm
8789 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8790 Inst = TmpInst;
8791 return true;
8792 }
8793 // Aliases for imm syntax of STR instructions.
8794 case ARM::t2STR_PRE_imm:
8795 case ARM::t2STR_POST_imm: {
8796 MCInst TmpInst;
8797 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
8798 : ARM::t2STR_POST);
8799 TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
8800 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8801 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8802 TmpInst.addOperand(Inst.getOperand(2)); // imm
8803 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8804 Inst = TmpInst;
8805 return true;
8806 }
8807 // Aliases for alternate PC+imm syntax of LDR instructions.
8808 case ARM::t2LDRpcrel:
8809 // Select the narrow version if the immediate will fit.
8810 if (Inst.getOperand(1).getImm() > 0 &&
8811 Inst.getOperand(1).getImm() <= 0xff &&
8812 !HasWideQualifier)
8813 Inst.setOpcode(ARM::tLDRpci);
8814 else
8815 Inst.setOpcode(ARM::t2LDRpci);
8816 return true;
8817 case ARM::t2LDRBpcrel:
8818 Inst.setOpcode(ARM::t2LDRBpci);
8819 return true;
8820 case ARM::t2LDRHpcrel:
8821 Inst.setOpcode(ARM::t2LDRHpci);
8822 return true;
8823 case ARM::t2LDRSBpcrel:
8824 Inst.setOpcode(ARM::t2LDRSBpci);
8825 return true;
8826 case ARM::t2LDRSHpcrel:
8827 Inst.setOpcode(ARM::t2LDRSHpci);
8828 return true;
8829 case ARM::LDRConstPool:
8830 case ARM::tLDRConstPool:
8831 case ARM::t2LDRConstPool: {
8832 // Pseudo instruction ldr rt, =immediate is converted to a
8833 // MOV rt, immediate if immediate is known and representable
8834 // otherwise we create a constant pool entry that we load from.
8835 MCInst TmpInst;
8836 if (Inst.getOpcode() == ARM::LDRConstPool)
8837 TmpInst.setOpcode(ARM::LDRi12);
8838 else if (Inst.getOpcode() == ARM::tLDRConstPool)
8839 TmpInst.setOpcode(ARM::tLDRpci);
8840 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8841 TmpInst.setOpcode(ARM::t2LDRpci);
8842 const ARMOperand &PoolOperand =
8843 (HasWideQualifier ?
8844 static_cast<ARMOperand &>(*Operands[4]) :
8845 static_cast<ARMOperand &>(*Operands[3]));
8846 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
8847 // If SubExprVal is a constant we may be able to use a MOV
8848 if (isa<MCConstantExpr>(SubExprVal) &&
8849 Inst.getOperand(0).getReg() != ARM::PC &&
8850 Inst.getOperand(0).getReg() != ARM::SP) {
8851 int64_t Value =
8852 (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
8853 bool UseMov = true;
8854 bool MovHasS = true;
8855 if (Inst.getOpcode() == ARM::LDRConstPool) {
8856 // ARM Constant
8857 if (ARM_AM::getSOImmVal(Value) != -1) {
8858 Value = ARM_AM::getSOImmVal(Value);
8859 TmpInst.setOpcode(ARM::MOVi);
8860 }
8861 else if (ARM_AM::getSOImmVal(~Value) != -1) {
8862 Value = ARM_AM::getSOImmVal(~Value);
8863 TmpInst.setOpcode(ARM::MVNi);
8864 }
8865 else if (hasV6T2Ops() &&
8866 Value >=0 && Value < 65536) {
8867 TmpInst.setOpcode(ARM::MOVi16);
8868 MovHasS = false;
8869 }
8870 else
8871 UseMov = false;
8872 }
8873 else {
8874 // Thumb/Thumb2 Constant
8875 if (hasThumb2() &&
8876 ARM_AM::getT2SOImmVal(Value) != -1)
8877 TmpInst.setOpcode(ARM::t2MOVi);
8878 else if (hasThumb2() &&
8879 ARM_AM::getT2SOImmVal(~Value) != -1) {
8880 TmpInst.setOpcode(ARM::t2MVNi);
8881 Value = ~Value;
8882 }
8883 else if (hasV8MBaseline() &&
8884 Value >=0 && Value < 65536) {
8885 TmpInst.setOpcode(ARM::t2MOVi16);
8886 MovHasS = false;
8887 }
8888 else
8889 UseMov = false;
8890 }
8891 if (UseMov) {
8892 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8893 TmpInst.addOperand(MCOperand::createImm(Value)); // Immediate
8894 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8895 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8896 if (MovHasS)
8897 TmpInst.addOperand(MCOperand::createReg(0)); // S
8898 Inst = TmpInst;
8899 return true;
8900 }
8901 }
8902 // No opportunity to use MOV/MVN create constant pool
8903 const MCExpr *CPLoc =
8904 getTargetStreamer().addConstantPoolEntry(SubExprVal,
8905 PoolOperand.getStartLoc());
8906 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8907 TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
8908 if (TmpInst.getOpcode() == ARM::LDRi12)
8909 TmpInst.addOperand(MCOperand::createImm(0)); // unused offset
8910 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8911 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8912 Inst = TmpInst;
8913 return true;
8914 }
8915 // Handle NEON VST complex aliases.
8916 case ARM::VST1LNdWB_register_Asm_8:
8917 case ARM::VST1LNdWB_register_Asm_16:
8918 case ARM::VST1LNdWB_register_Asm_32: {
8919 MCInst TmpInst;
8920 // Shuffle the operands around so the lane index operand is in the
8921 // right place.
8922 unsigned Spacing;
8923 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8924 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8925 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8926 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8927 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8928 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8929 TmpInst.addOperand(Inst.getOperand(1)); // lane
8930 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8931 TmpInst.addOperand(Inst.getOperand(6));
8932 Inst = TmpInst;
8933 return true;
8934 }
8935
8936 case ARM::VST2LNdWB_register_Asm_8:
8937 case ARM::VST2LNdWB_register_Asm_16:
8938 case ARM::VST2LNdWB_register_Asm_32:
8939 case ARM::VST2LNqWB_register_Asm_16:
8940 case ARM::VST2LNqWB_register_Asm_32: {
8941 MCInst TmpInst;
8942 // Shuffle the operands around so the lane index operand is in the
8943 // right place.
8944 unsigned Spacing;
8945 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8946 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8947 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8948 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8949 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8950 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8951 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8952 Spacing));
8953 TmpInst.addOperand(Inst.getOperand(1)); // lane
8954 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8955 TmpInst.addOperand(Inst.getOperand(6));
8956 Inst = TmpInst;
8957 return true;
8958 }
8959
8960 case ARM::VST3LNdWB_register_Asm_8:
8961 case ARM::VST3LNdWB_register_Asm_16:
8962 case ARM::VST3LNdWB_register_Asm_32:
8963 case ARM::VST3LNqWB_register_Asm_16:
8964 case ARM::VST3LNqWB_register_Asm_32: {
8965 MCInst TmpInst;
8966 // Shuffle the operands around so the lane index operand is in the
8967 // right place.
8968 unsigned Spacing;
8969 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8970 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8971 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8972 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8973 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8975 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8976 Spacing));
8977 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8978 Spacing * 2));
8979 TmpInst.addOperand(Inst.getOperand(1)); // lane
8980 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8981 TmpInst.addOperand(Inst.getOperand(6));
8982 Inst = TmpInst;
8983 return true;
8984 }
8985
8986 case ARM::VST4LNdWB_register_Asm_8:
8987 case ARM::VST4LNdWB_register_Asm_16:
8988 case ARM::VST4LNdWB_register_Asm_32:
8989 case ARM::VST4LNqWB_register_Asm_16:
8990 case ARM::VST4LNqWB_register_Asm_32: {
8991 MCInst TmpInst;
8992 // Shuffle the operands around so the lane index operand is in the
8993 // right place.
8994 unsigned Spacing;
8995 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8996 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8997 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8998 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8999 TmpInst.addOperand(Inst.getOperand(4)); // Rm
9000 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9001 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9002 Spacing));
9003 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9004 Spacing * 2));
9005 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9006 Spacing * 3));
9007 TmpInst.addOperand(Inst.getOperand(1)); // lane
9008 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9009 TmpInst.addOperand(Inst.getOperand(6));
9010 Inst = TmpInst;
9011 return true;
9012 }
9013
9014 case ARM::VST1LNdWB_fixed_Asm_8:
9015 case ARM::VST1LNdWB_fixed_Asm_16:
9016 case ARM::VST1LNdWB_fixed_Asm_32: {
9017 MCInst TmpInst;
9018 // Shuffle the operands around so the lane index operand is in the
9019 // right place.
9020 unsigned Spacing;
9021 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9022 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9023 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9024 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9025 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9026 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9027 TmpInst.addOperand(Inst.getOperand(1)); // lane
9028 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9029 TmpInst.addOperand(Inst.getOperand(5));
9030 Inst = TmpInst;
9031 return true;
9032 }
9033
9034 case ARM::VST2LNdWB_fixed_Asm_8:
9035 case ARM::VST2LNdWB_fixed_Asm_16:
9036 case ARM::VST2LNdWB_fixed_Asm_32:
9037 case ARM::VST2LNqWB_fixed_Asm_16:
9038 case ARM::VST2LNqWB_fixed_Asm_32: {
9039 MCInst TmpInst;
9040 // Shuffle the operands around so the lane index operand is in the
9041 // right place.
9042 unsigned Spacing;
9043 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9044 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9045 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9046 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9047 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9048 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9049 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9050 Spacing));
9051 TmpInst.addOperand(Inst.getOperand(1)); // lane
9052 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9053 TmpInst.addOperand(Inst.getOperand(5));
9054 Inst = TmpInst;
9055 return true;
9056 }
9057
9058 case ARM::VST3LNdWB_fixed_Asm_8:
9059 case ARM::VST3LNdWB_fixed_Asm_16:
9060 case ARM::VST3LNdWB_fixed_Asm_32:
9061 case ARM::VST3LNqWB_fixed_Asm_16:
9062 case ARM::VST3LNqWB_fixed_Asm_32: {
9063 MCInst TmpInst;
9064 // Shuffle the operands around so the lane index operand is in the
9065 // right place.
9066 unsigned Spacing;
9067 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9068 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9069 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9070 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9071 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9072 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9073 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9074 Spacing));
9075 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9076 Spacing * 2));
9077 TmpInst.addOperand(Inst.getOperand(1)); // lane
9078 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9079 TmpInst.addOperand(Inst.getOperand(5));
9080 Inst = TmpInst;
9081 return true;
9082 }
9083
9084 case ARM::VST4LNdWB_fixed_Asm_8:
9085 case ARM::VST4LNdWB_fixed_Asm_16:
9086 case ARM::VST4LNdWB_fixed_Asm_32:
9087 case ARM::VST4LNqWB_fixed_Asm_16:
9088 case ARM::VST4LNqWB_fixed_Asm_32: {
9089 MCInst TmpInst;
9090 // Shuffle the operands around so the lane index operand is in the
9091 // right place.
9092 unsigned Spacing;
9093 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9094 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9095 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9096 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9097 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9098 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9099 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9100 Spacing));
9101 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9102 Spacing * 2));
9103 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9104 Spacing * 3));
9105 TmpInst.addOperand(Inst.getOperand(1)); // lane
9106 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9107 TmpInst.addOperand(Inst.getOperand(5));
9108 Inst = TmpInst;
9109 return true;
9110 }
9111
9112 case ARM::VST1LNdAsm_8:
9113 case ARM::VST1LNdAsm_16:
9114 case ARM::VST1LNdAsm_32: {
9115 MCInst TmpInst;
9116 // Shuffle the operands around so the lane index operand is in the
9117 // right place.
9118 unsigned Spacing;
9119 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9120 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9121 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9122 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9123 TmpInst.addOperand(Inst.getOperand(1)); // lane
9124 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9125 TmpInst.addOperand(Inst.getOperand(5));
9126 Inst = TmpInst;
9127 return true;
9128 }
9129
9130 case ARM::VST2LNdAsm_8:
9131 case ARM::VST2LNdAsm_16:
9132 case ARM::VST2LNdAsm_32:
9133 case ARM::VST2LNqAsm_16:
9134 case ARM::VST2LNqAsm_32: {
9135 MCInst TmpInst;
9136 // Shuffle the operands around so the lane index operand is in the
9137 // right place.
9138 unsigned Spacing;
9139 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9140 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9141 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9142 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9143 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9144 Spacing));
9145 TmpInst.addOperand(Inst.getOperand(1)); // lane
9146 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9147 TmpInst.addOperand(Inst.getOperand(5));
9148 Inst = TmpInst;
9149 return true;
9150 }
9151
9152 case ARM::VST3LNdAsm_8:
9153 case ARM::VST3LNdAsm_16:
9154 case ARM::VST3LNdAsm_32:
9155 case ARM::VST3LNqAsm_16:
9156 case ARM::VST3LNqAsm_32: {
9157 MCInst TmpInst;
9158 // Shuffle the operands around so the lane index operand is in the
9159 // right place.
9160 unsigned Spacing;
9161 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9162 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9163 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9164 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9165 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9166 Spacing));
9167 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9168 Spacing * 2));
9169 TmpInst.addOperand(Inst.getOperand(1)); // lane
9170 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9171 TmpInst.addOperand(Inst.getOperand(5));
9172 Inst = TmpInst;
9173 return true;
9174 }
9175
9176 case ARM::VST4LNdAsm_8:
9177 case ARM::VST4LNdAsm_16:
9178 case ARM::VST4LNdAsm_32:
9179 case ARM::VST4LNqAsm_16:
9180 case ARM::VST4LNqAsm_32: {
9181 MCInst TmpInst;
9182 // Shuffle the operands around so the lane index operand is in the
9183 // right place.
9184 unsigned Spacing;
9185 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9186 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9187 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9188 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9189 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9190 Spacing));
9191 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9192 Spacing * 2));
9193 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9194 Spacing * 3));
9195 TmpInst.addOperand(Inst.getOperand(1)); // lane
9196 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9197 TmpInst.addOperand(Inst.getOperand(5));
9198 Inst = TmpInst;
9199 return true;
9200 }
9201
9202 // Handle NEON VLD complex aliases.
9203 case ARM::VLD1LNdWB_register_Asm_8:
9204 case ARM::VLD1LNdWB_register_Asm_16:
9205 case ARM::VLD1LNdWB_register_Asm_32: {
9206 MCInst TmpInst;
9207 // Shuffle the operands around so the lane index operand is in the
9208 // right place.
9209 unsigned Spacing;
9210 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9211 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9212 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9213 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9214 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9215 TmpInst.addOperand(Inst.getOperand(4)); // Rm
9216 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9217 TmpInst.addOperand(Inst.getOperand(1)); // lane
9218 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9219 TmpInst.addOperand(Inst.getOperand(6));
9220 Inst = TmpInst;
9221 return true;
9222 }
9223
9224 case ARM::VLD2LNdWB_register_Asm_8:
9225 case ARM::VLD2LNdWB_register_Asm_16:
9226 case ARM::VLD2LNdWB_register_Asm_32:
9227 case ARM::VLD2LNqWB_register_Asm_16:
9228 case ARM::VLD2LNqWB_register_Asm_32: {
9229 MCInst TmpInst;
9230 // Shuffle the operands around so the lane index operand is in the
9231 // right place.
9232 unsigned Spacing;
9233 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9234 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9235 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9236 Spacing));
9237 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9238 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9239 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9240 TmpInst.addOperand(Inst.getOperand(4)); // Rm
9241 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9242 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9243 Spacing));
9244 TmpInst.addOperand(Inst.getOperand(1)); // lane
9245 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9246 TmpInst.addOperand(Inst.getOperand(6));
9247 Inst = TmpInst;
9248 return true;
9249 }
9250
9251 case ARM::VLD3LNdWB_register_Asm_8:
9252 case ARM::VLD3LNdWB_register_Asm_16:
9253 case ARM::VLD3LNdWB_register_Asm_32:
9254 case ARM::VLD3LNqWB_register_Asm_16:
9255 case ARM::VLD3LNqWB_register_Asm_32: {
9256 MCInst TmpInst;
9257 // Shuffle the operands around so the lane index operand is in the
9258 // right place.
9259 unsigned Spacing;
9260 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9261 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9262 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9263 Spacing));
9264 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9265 Spacing * 2));
9266 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9267 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9268 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9269 TmpInst.addOperand(Inst.getOperand(4)); // Rm
9270 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9271 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9272 Spacing));
9273 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9274 Spacing * 2));
9275 TmpInst.addOperand(Inst.getOperand(1)); // lane
9276 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9277 TmpInst.addOperand(Inst.getOperand(6));
9278 Inst = TmpInst;
9279 return true;
9280 }
9281
9282 case ARM::VLD4LNdWB_register_Asm_8:
9283 case ARM::VLD4LNdWB_register_Asm_16:
9284 case ARM::VLD4LNdWB_register_Asm_32:
9285 case ARM::VLD4LNqWB_register_Asm_16:
9286 case ARM::VLD4LNqWB_register_Asm_32: {
9287 MCInst TmpInst;
9288 // Shuffle the operands around so the lane index operand is in the
9289 // right place.
9290 unsigned Spacing;
9291 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9292 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9293 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9294 Spacing));
9295 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9296 Spacing * 2));
9297 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9298 Spacing * 3));
9299 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9300 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9301 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9302 TmpInst.addOperand(Inst.getOperand(4)); // Rm
9303 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9304 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9305 Spacing));
9306 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9307 Spacing * 2));
9308 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9309 Spacing * 3));
9310 TmpInst.addOperand(Inst.getOperand(1)); // lane
9311 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9312 TmpInst.addOperand(Inst.getOperand(6));
9313 Inst = TmpInst;
9314 return true;
9315 }
9316
9317 case ARM::VLD1LNdWB_fixed_Asm_8:
9318 case ARM::VLD1LNdWB_fixed_Asm_16:
9319 case ARM::VLD1LNdWB_fixed_Asm_32: {
9320 MCInst TmpInst;
9321 // Shuffle the operands around so the lane index operand is in the
9322 // right place.
9323 unsigned Spacing;
9324 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9325 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9326 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9327 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9328 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9329 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9330 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9331 TmpInst.addOperand(Inst.getOperand(1)); // lane
9332 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9333 TmpInst.addOperand(Inst.getOperand(5));
9334 Inst = TmpInst;
9335 return true;
9336 }
9337
9338 case ARM::VLD2LNdWB_fixed_Asm_8:
9339 case ARM::VLD2LNdWB_fixed_Asm_16:
9340 case ARM::VLD2LNdWB_fixed_Asm_32:
9341 case ARM::VLD2LNqWB_fixed_Asm_16:
9342 case ARM::VLD2LNqWB_fixed_Asm_32: {
9343 MCInst TmpInst;
9344 // Shuffle the operands around so the lane index operand is in the
9345 // right place.
9346 unsigned Spacing;
9347 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9348 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9349 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9350 Spacing));
9351 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9352 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9353 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9354 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9355 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9356 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9357 Spacing));
9358 TmpInst.addOperand(Inst.getOperand(1)); // lane
9359 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9360 TmpInst.addOperand(Inst.getOperand(5));
9361 Inst = TmpInst;
9362 return true;
9363 }
9364
9365 case ARM::VLD3LNdWB_fixed_Asm_8:
9366 case ARM::VLD3LNdWB_fixed_Asm_16:
9367 case ARM::VLD3LNdWB_fixed_Asm_32:
9368 case ARM::VLD3LNqWB_fixed_Asm_16:
9369 case ARM::VLD3LNqWB_fixed_Asm_32: {
9370 MCInst TmpInst;
9371 // Shuffle the operands around so the lane index operand is in the
9372 // right place.
9373 unsigned Spacing;
9374 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9375 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9376 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9377 Spacing));
9378 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9379 Spacing * 2));
9380 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9381 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9382 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9383 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9384 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9385 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9386 Spacing));
9387 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9388 Spacing * 2));
9389 TmpInst.addOperand(Inst.getOperand(1)); // lane
9390 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9391 TmpInst.addOperand(Inst.getOperand(5));
9392 Inst = TmpInst;
9393 return true;
9394 }
9395
9396 case ARM::VLD4LNdWB_fixed_Asm_8:
9397 case ARM::VLD4LNdWB_fixed_Asm_16:
9398 case ARM::VLD4LNdWB_fixed_Asm_32:
9399 case ARM::VLD4LNqWB_fixed_Asm_16:
9400 case ARM::VLD4LNqWB_fixed_Asm_32: {
9401 MCInst TmpInst;
9402 // Shuffle the operands around so the lane index operand is in the
9403 // right place.
9404 unsigned Spacing;
9405 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9406 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9407 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9408 Spacing));
9409 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9410 Spacing * 2));
9411 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9412 Spacing * 3));
9413 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9414 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9415 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9416 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9417 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9418 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9419 Spacing));
9420 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9421 Spacing * 2));
9422 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9423 Spacing * 3));
9424 TmpInst.addOperand(Inst.getOperand(1)); // lane
9425 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9426 TmpInst.addOperand(Inst.getOperand(5));
9427 Inst = TmpInst;
9428 return true;
9429 }
9430
9431 case ARM::VLD1LNdAsm_8:
9432 case ARM::VLD1LNdAsm_16:
9433 case ARM::VLD1LNdAsm_32: {
9434 MCInst TmpInst;
9435 // Shuffle the operands around so the lane index operand is in the
9436 // right place.
9437 unsigned Spacing;
9438 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9439 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9440 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9441 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9442 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9443 TmpInst.addOperand(Inst.getOperand(1)); // lane
9444 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9445 TmpInst.addOperand(Inst.getOperand(5));
9446 Inst = TmpInst;
9447 return true;
9448 }
9449
9450 case ARM::VLD2LNdAsm_8:
9451 case ARM::VLD2LNdAsm_16:
9452 case ARM::VLD2LNdAsm_32:
9453 case ARM::VLD2LNqAsm_16:
9454 case ARM::VLD2LNqAsm_32: {
9455 MCInst TmpInst;
9456 // Shuffle the operands around so the lane index operand is in the
9457 // right place.
9458 unsigned Spacing;
9459 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9460 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9461 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9462 Spacing));
9463 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9464 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9465 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9466 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9467 Spacing));
9468 TmpInst.addOperand(Inst.getOperand(1)); // lane
9469 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9470 TmpInst.addOperand(Inst.getOperand(5));
9471 Inst = TmpInst;
9472 return true;
9473 }
9474
9475 case ARM::VLD3LNdAsm_8:
9476 case ARM::VLD3LNdAsm_16:
9477 case ARM::VLD3LNdAsm_32:
9478 case ARM::VLD3LNqAsm_16:
9479 case ARM::VLD3LNqAsm_32: {
9480 MCInst TmpInst;
9481 // Shuffle the operands around so the lane index operand is in the
9482 // right place.
9483 unsigned Spacing;
9484 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9485 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9486 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9487 Spacing));
9488 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9489 Spacing * 2));
9490 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9491 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9492 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9493 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9494 Spacing));
9495 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9496 Spacing * 2));
9497 TmpInst.addOperand(Inst.getOperand(1)); // lane
9498 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9499 TmpInst.addOperand(Inst.getOperand(5));
9500 Inst = TmpInst;
9501 return true;
9502 }
9503
9504 case ARM::VLD4LNdAsm_8:
9505 case ARM::VLD4LNdAsm_16:
9506 case ARM::VLD4LNdAsm_32:
9507 case ARM::VLD4LNqAsm_16:
9508 case ARM::VLD4LNqAsm_32: {
9509 MCInst TmpInst;
9510 // Shuffle the operands around so the lane index operand is in the
9511 // right place.
9512 unsigned Spacing;
9513 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9514 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9515 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9516 Spacing));
9517 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9518 Spacing * 2));
9519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9520 Spacing * 3));
9521 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9522 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9523 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9524 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9525 Spacing));
9526 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9527 Spacing * 2));
9528 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9529 Spacing * 3));
9530 TmpInst.addOperand(Inst.getOperand(1)); // lane
9531 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9532 TmpInst.addOperand(Inst.getOperand(5));
9533 Inst = TmpInst;
9534 return true;
9535 }
9536
9537 // VLD3DUP single 3-element structure to all lanes instructions.
9538 case ARM::VLD3DUPdAsm_8:
9539 case ARM::VLD3DUPdAsm_16:
9540 case ARM::VLD3DUPdAsm_32:
9541 case ARM::VLD3DUPqAsm_8:
9542 case ARM::VLD3DUPqAsm_16:
9543 case ARM::VLD3DUPqAsm_32: {
9544 MCInst TmpInst;
9545 unsigned Spacing;
9546 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9547 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9548 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9549 Spacing));
9550 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9551 Spacing * 2));
9552 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9553 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9554 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9555 TmpInst.addOperand(Inst.getOperand(4));
9556 Inst = TmpInst;
9557 return true;
9558 }
9559
9560 case ARM::VLD3DUPdWB_fixed_Asm_8:
9561 case ARM::VLD3DUPdWB_fixed_Asm_16:
9562 case ARM::VLD3DUPdWB_fixed_Asm_32:
9563 case ARM::VLD3DUPqWB_fixed_Asm_8:
9564 case ARM::VLD3DUPqWB_fixed_Asm_16:
9565 case ARM::VLD3DUPqWB_fixed_Asm_32: {
9566 MCInst TmpInst;
9567 unsigned Spacing;
9568 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9569 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9570 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9571 Spacing));
9572 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9573 Spacing * 2));
9574 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9575 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9576 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9577 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9578 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9579 TmpInst.addOperand(Inst.getOperand(4));
9580 Inst = TmpInst;
9581 return true;
9582 }
9583
9584 case ARM::VLD3DUPdWB_register_Asm_8:
9585 case ARM::VLD3DUPdWB_register_Asm_16:
9586 case ARM::VLD3DUPdWB_register_Asm_32:
9587 case ARM::VLD3DUPqWB_register_Asm_8:
9588 case ARM::VLD3DUPqWB_register_Asm_16:
9589 case ARM::VLD3DUPqWB_register_Asm_32: {
9590 MCInst TmpInst;
9591 unsigned Spacing;
9592 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9593 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9594 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9595 Spacing));
9596 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9597 Spacing * 2));
9598 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9599 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9600 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9601 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9602 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9603 TmpInst.addOperand(Inst.getOperand(5));
9604 Inst = TmpInst;
9605 return true;
9606 }
9607
9608 // VLD3 multiple 3-element structure instructions.
9609 case ARM::VLD3dAsm_8:
9610 case ARM::VLD3dAsm_16:
9611 case ARM::VLD3dAsm_32:
9612 case ARM::VLD3qAsm_8:
9613 case ARM::VLD3qAsm_16:
9614 case ARM::VLD3qAsm_32: {
9615 MCInst TmpInst;
9616 unsigned Spacing;
9617 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9618 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9619 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9620 Spacing));
9621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9622 Spacing * 2));
9623 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9624 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9625 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9626 TmpInst.addOperand(Inst.getOperand(4));
9627 Inst = TmpInst;
9628 return true;
9629 }
9630
9631 case ARM::VLD3dWB_fixed_Asm_8:
9632 case ARM::VLD3dWB_fixed_Asm_16:
9633 case ARM::VLD3dWB_fixed_Asm_32:
9634 case ARM::VLD3qWB_fixed_Asm_8:
9635 case ARM::VLD3qWB_fixed_Asm_16:
9636 case ARM::VLD3qWB_fixed_Asm_32: {
9637 MCInst TmpInst;
9638 unsigned Spacing;
9639 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9640 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9641 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9642 Spacing));
9643 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9644 Spacing * 2));
9645 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9646 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9647 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9648 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9649 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9650 TmpInst.addOperand(Inst.getOperand(4));
9651 Inst = TmpInst;
9652 return true;
9653 }
9654
9655 case ARM::VLD3dWB_register_Asm_8:
9656 case ARM::VLD3dWB_register_Asm_16:
9657 case ARM::VLD3dWB_register_Asm_32:
9658 case ARM::VLD3qWB_register_Asm_8:
9659 case ARM::VLD3qWB_register_Asm_16:
9660 case ARM::VLD3qWB_register_Asm_32: {
9661 MCInst TmpInst;
9662 unsigned Spacing;
9663 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9664 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9665 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9666 Spacing));
9667 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9668 Spacing * 2));
9669 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9670 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9671 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9672 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9673 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9674 TmpInst.addOperand(Inst.getOperand(5));
9675 Inst = TmpInst;
9676 return true;
9677 }
9678
9679 // VLD4DUP single 3-element structure to all lanes instructions.
9680 case ARM::VLD4DUPdAsm_8:
9681 case ARM::VLD4DUPdAsm_16:
9682 case ARM::VLD4DUPdAsm_32:
9683 case ARM::VLD4DUPqAsm_8:
9684 case ARM::VLD4DUPqAsm_16:
9685 case ARM::VLD4DUPqAsm_32: {
9686 MCInst TmpInst;
9687 unsigned Spacing;
9688 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9689 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9690 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9691 Spacing));
9692 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9693 Spacing * 2));
9694 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9695 Spacing * 3));
9696 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9697 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9698 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9699 TmpInst.addOperand(Inst.getOperand(4));
9700 Inst = TmpInst;
9701 return true;
9702 }
9703
9704 case ARM::VLD4DUPdWB_fixed_Asm_8:
9705 case ARM::VLD4DUPdWB_fixed_Asm_16:
9706 case ARM::VLD4DUPdWB_fixed_Asm_32:
9707 case ARM::VLD4DUPqWB_fixed_Asm_8:
9708 case ARM::VLD4DUPqWB_fixed_Asm_16:
9709 case ARM::VLD4DUPqWB_fixed_Asm_32: {
9710 MCInst TmpInst;
9711 unsigned Spacing;
9712 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9713 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9714 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9715 Spacing));
9716 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9717 Spacing * 2));
9718 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9719 Spacing * 3));
9720 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9721 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9722 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9723 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9724 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9725 TmpInst.addOperand(Inst.getOperand(4));
9726 Inst = TmpInst;
9727 return true;
9728 }
9729
9730 case ARM::VLD4DUPdWB_register_Asm_8:
9731 case ARM::VLD4DUPdWB_register_Asm_16:
9732 case ARM::VLD4DUPdWB_register_Asm_32:
9733 case ARM::VLD4DUPqWB_register_Asm_8:
9734 case ARM::VLD4DUPqWB_register_Asm_16:
9735 case ARM::VLD4DUPqWB_register_Asm_32: {
9736 MCInst TmpInst;
9737 unsigned Spacing;
9738 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9739 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9740 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9741 Spacing));
9742 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9743 Spacing * 2));
9744 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9745 Spacing * 3));
9746 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9747 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9748 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9749 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9750 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9751 TmpInst.addOperand(Inst.getOperand(5));
9752 Inst = TmpInst;
9753 return true;
9754 }
9755
9756 // VLD4 multiple 4-element structure instructions.
9757 case ARM::VLD4dAsm_8:
9758 case ARM::VLD4dAsm_16:
9759 case ARM::VLD4dAsm_32:
9760 case ARM::VLD4qAsm_8:
9761 case ARM::VLD4qAsm_16:
9762 case ARM::VLD4qAsm_32: {
9763 MCInst TmpInst;
9764 unsigned Spacing;
9765 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9766 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9767 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9768 Spacing));
9769 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9770 Spacing * 2));
9771 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9772 Spacing * 3));
9773 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9774 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9775 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9776 TmpInst.addOperand(Inst.getOperand(4));
9777 Inst = TmpInst;
9778 return true;
9779 }
9780
9781 case ARM::VLD4dWB_fixed_Asm_8:
9782 case ARM::VLD4dWB_fixed_Asm_16:
9783 case ARM::VLD4dWB_fixed_Asm_32:
9784 case ARM::VLD4qWB_fixed_Asm_8:
9785 case ARM::VLD4qWB_fixed_Asm_16:
9786 case ARM::VLD4qWB_fixed_Asm_32: {
9787 MCInst TmpInst;
9788 unsigned Spacing;
9789 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9790 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9791 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9792 Spacing));
9793 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9794 Spacing * 2));
9795 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9796 Spacing * 3));
9797 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9798 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9799 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9800 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9801 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9802 TmpInst.addOperand(Inst.getOperand(4));
9803 Inst = TmpInst;
9804 return true;
9805 }
9806
9807 case ARM::VLD4dWB_register_Asm_8:
9808 case ARM::VLD4dWB_register_Asm_16:
9809 case ARM::VLD4dWB_register_Asm_32:
9810 case ARM::VLD4qWB_register_Asm_8:
9811 case ARM::VLD4qWB_register_Asm_16:
9812 case ARM::VLD4qWB_register_Asm_32: {
9813 MCInst TmpInst;
9814 unsigned Spacing;
9815 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9816 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9817 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9818 Spacing));
9819 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9820 Spacing * 2));
9821 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9822 Spacing * 3));
9823 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9824 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9825 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9826 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9827 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9828 TmpInst.addOperand(Inst.getOperand(5));
9829 Inst = TmpInst;
9830 return true;
9831 }
9832
9833 // VST3 multiple 3-element structure instructions.
9834 case ARM::VST3dAsm_8:
9835 case ARM::VST3dAsm_16:
9836 case ARM::VST3dAsm_32:
9837 case ARM::VST3qAsm_8:
9838 case ARM::VST3qAsm_16:
9839 case ARM::VST3qAsm_32: {
9840 MCInst TmpInst;
9841 unsigned Spacing;
9842 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9843 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9844 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9845 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9846 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9847 Spacing));
9848 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9849 Spacing * 2));
9850 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9851 TmpInst.addOperand(Inst.getOperand(4));
9852 Inst = TmpInst;
9853 return true;
9854 }
9855
9856 case ARM::VST3dWB_fixed_Asm_8:
9857 case ARM::VST3dWB_fixed_Asm_16:
9858 case ARM::VST3dWB_fixed_Asm_32:
9859 case ARM::VST3qWB_fixed_Asm_8:
9860 case ARM::VST3qWB_fixed_Asm_16:
9861 case ARM::VST3qWB_fixed_Asm_32: {
9862 MCInst TmpInst;
9863 unsigned Spacing;
9864 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9865 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9866 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9867 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9868 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9869 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9870 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9871 Spacing));
9872 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9873 Spacing * 2));
9874 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9875 TmpInst.addOperand(Inst.getOperand(4));
9876 Inst = TmpInst;
9877 return true;
9878 }
9879
9880 case ARM::VST3dWB_register_Asm_8:
9881 case ARM::VST3dWB_register_Asm_16:
9882 case ARM::VST3dWB_register_Asm_32:
9883 case ARM::VST3qWB_register_Asm_8:
9884 case ARM::VST3qWB_register_Asm_16:
9885 case ARM::VST3qWB_register_Asm_32: {
9886 MCInst TmpInst;
9887 unsigned Spacing;
9888 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9889 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9890 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9891 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9892 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9893 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9894 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9895 Spacing));
9896 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9897 Spacing * 2));
9898 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9899 TmpInst.addOperand(Inst.getOperand(5));
9900 Inst = TmpInst;
9901 return true;
9902 }
9903
9904 // VST4 multiple 3-element structure instructions.
9905 case ARM::VST4dAsm_8:
9906 case ARM::VST4dAsm_16:
9907 case ARM::VST4dAsm_32:
9908 case ARM::VST4qAsm_8:
9909 case ARM::VST4qAsm_16:
9910 case ARM::VST4qAsm_32: {
9911 MCInst TmpInst;
9912 unsigned Spacing;
9913 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9914 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9915 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9917 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9918 Spacing));
9919 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9920 Spacing * 2));
9921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9922 Spacing * 3));
9923 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9924 TmpInst.addOperand(Inst.getOperand(4));
9925 Inst = TmpInst;
9926 return true;
9927 }
9928
9929 case ARM::VST4dWB_fixed_Asm_8:
9930 case ARM::VST4dWB_fixed_Asm_16:
9931 case ARM::VST4dWB_fixed_Asm_32:
9932 case ARM::VST4qWB_fixed_Asm_8:
9933 case ARM::VST4qWB_fixed_Asm_16:
9934 case ARM::VST4qWB_fixed_Asm_32: {
9935 MCInst TmpInst;
9936 unsigned Spacing;
9937 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9938 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9939 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9940 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9941 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9942 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9943 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9944 Spacing));
9945 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9946 Spacing * 2));
9947 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9948 Spacing * 3));
9949 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9950 TmpInst.addOperand(Inst.getOperand(4));
9951 Inst = TmpInst;
9952 return true;
9953 }
9954
9955 case ARM::VST4dWB_register_Asm_8:
9956 case ARM::VST4dWB_register_Asm_16:
9957 case ARM::VST4dWB_register_Asm_32:
9958 case ARM::VST4qWB_register_Asm_8:
9959 case ARM::VST4qWB_register_Asm_16:
9960 case ARM::VST4qWB_register_Asm_32: {
9961 MCInst TmpInst;
9962 unsigned Spacing;
9963 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9964 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9965 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9966 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9967 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9968 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9969 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9970 Spacing));
9971 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9972 Spacing * 2));
9973 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9974 Spacing * 3));
9975 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9976 TmpInst.addOperand(Inst.getOperand(5));
9977 Inst = TmpInst;
9978 return true;
9979 }
9980
9981 // Handle encoding choice for the shift-immediate instructions.
9982 case ARM::t2LSLri:
9983 case ARM::t2LSRri:
9984 case ARM::t2ASRri:
9985 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9986 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9987 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9988 !HasWideQualifier) {
9989 unsigned NewOpc;
9990 switch (Inst.getOpcode()) {
9991 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 9991)
;
9992 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9993 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
9994 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
9995 }
9996 // The Thumb1 operands aren't in the same order. Awesome, eh?
9997 MCInst TmpInst;
9998 TmpInst.setOpcode(NewOpc);
9999 TmpInst.addOperand(Inst.getOperand(0));
10000 TmpInst.addOperand(Inst.getOperand(5));
10001 TmpInst.addOperand(Inst.getOperand(1));
10002 TmpInst.addOperand(Inst.getOperand(2));
10003 TmpInst.addOperand(Inst.getOperand(3));
10004 TmpInst.addOperand(Inst.getOperand(4));
10005 Inst = TmpInst;
10006 return true;
10007 }
10008 return false;
10009
10010 // Handle the Thumb2 mode MOV complex aliases.
10011 case ARM::t2MOVsr:
10012 case ARM::t2MOVSsr: {
10013 // Which instruction to expand to depends on the CCOut operand and
10014 // whether we're in an IT block if the register operands are low
10015 // registers.
10016 bool isNarrow = false;
10017 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10018 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10019 isARMLowRegister(Inst.getOperand(2).getReg()) &&
10020 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10021 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
10022 !HasWideQualifier)
10023 isNarrow = true;
10024 MCInst TmpInst;
10025 unsigned newOpc;
10026 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
10027 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10027)
;
10028 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
10029 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
10030 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
10031 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
10032 }
10033 TmpInst.setOpcode(newOpc);
10034 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10035 if (isNarrow)
10036 TmpInst.addOperand(MCOperand::createReg(
10037 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10038 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10039 TmpInst.addOperand(Inst.getOperand(2)); // Rm
10040 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
10041 TmpInst.addOperand(Inst.getOperand(5));
10042 if (!isNarrow)
10043 TmpInst.addOperand(MCOperand::createReg(
10044 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10045 Inst = TmpInst;
10046 return true;
10047 }
10048 case ARM::t2MOVsi:
10049 case ARM::t2MOVSsi: {
10050 // Which instruction to expand to depends on the CCOut operand and
10051 // whether we're in an IT block if the register operands are low
10052 // registers.
10053 bool isNarrow = false;
10054 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10055 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10056 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
10057 !HasWideQualifier)
10058 isNarrow = true;
10059 MCInst TmpInst;
10060 unsigned newOpc;
10061 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10062 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
10063 bool isMov = false;
10064 // MOV rd, rm, LSL #0 is actually a MOV instruction
10065 if (Shift == ARM_AM::lsl && Amount == 0) {
10066 isMov = true;
10067 // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
10068 // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
10069 // unpredictable in an IT block so the 32-bit encoding T3 has to be used
10070 // instead.
10071 if (inITBlock()) {
10072 isNarrow = false;
10073 }
10074 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
10075 } else {
10076 switch(Shift) {
10077 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10077)
;
10078 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
10079 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
10080 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
10081 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
10082 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
10083 }
10084 }
10085 if (Amount == 32) Amount = 0;
10086 TmpInst.setOpcode(newOpc);
10087 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10088 if (isNarrow && !isMov)
10089 TmpInst.addOperand(MCOperand::createReg(
10090 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10091 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10092 if (newOpc != ARM::t2RRX && !isMov)
10093 TmpInst.addOperand(MCOperand::createImm(Amount));
10094 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10095 TmpInst.addOperand(Inst.getOperand(4));
10096 if (!isNarrow)
10097 TmpInst.addOperand(MCOperand::createReg(
10098 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10099 Inst = TmpInst;
10100 return true;
10101 }
10102 // Handle the ARM mode MOV complex aliases.
10103 case ARM::ASRr:
10104 case ARM::LSRr:
10105 case ARM::LSLr:
10106 case ARM::RORr: {
10107 ARM_AM::ShiftOpc ShiftTy;
10108 switch(Inst.getOpcode()) {
10109 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10109)
;
10110 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
10111 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
10112 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
10113 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
10114 }
10115 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10116 MCInst TmpInst;
10117 TmpInst.setOpcode(ARM::MOVsr);
10118 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10119 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10120 TmpInst.addOperand(Inst.getOperand(2)); // Rm
10121 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10122 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10123 TmpInst.addOperand(Inst.getOperand(4));
10124 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
10125 Inst = TmpInst;
10126 return true;
10127 }
10128 case ARM::ASRi:
10129 case ARM::LSRi:
10130 case ARM::LSLi:
10131 case ARM::RORi: {
10132 ARM_AM::ShiftOpc ShiftTy;
10133 switch(Inst.getOpcode()) {
10134 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10134)
;
10135 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
10136 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
10137 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
10138 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
10139 }
10140 // A shift by zero is a plain MOVr, not a MOVsi.
10141 unsigned Amt = Inst.getOperand(2).getImm();
10142 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
10143 // A shift by 32 should be encoded as 0 when permitted
10144 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10145 Amt = 0;
10146 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
10147 MCInst TmpInst;
10148 TmpInst.setOpcode(Opc);
10149 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10150 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10151 if (Opc == ARM::MOVsi)
10152 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10153 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10154 TmpInst.addOperand(Inst.getOperand(4));
10155 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
10156 Inst = TmpInst;
10157 return true;
10158 }
10159 case ARM::RRXi: {
10160 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
10161 MCInst TmpInst;
10162 TmpInst.setOpcode(ARM::MOVsi);
10163 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10164 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10165 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10166 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10167 TmpInst.addOperand(Inst.getOperand(3));
10168 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
10169 Inst = TmpInst;
10170 return true;
10171 }
10172 case ARM::t2LDMIA_UPD: {
10173 // If this is a load of a single register, then we should use
10174 // a post-indexed LDR instruction instead, per the ARM ARM.
10175 if (Inst.getNumOperands() != 5)
10176 return false;
10177 MCInst TmpInst;
10178 TmpInst.setOpcode(ARM::t2LDR_POST);
10179 TmpInst.addOperand(Inst.getOperand(4)); // Rt
10180 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10181 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10182 TmpInst.addOperand(MCOperand::createImm(4));
10183 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10184 TmpInst.addOperand(Inst.getOperand(3));
10185 Inst = TmpInst;
10186 return true;
10187 }
10188 case ARM::t2STMDB_UPD: {
10189 // If this is a store of a single register, then we should use
10190 // a pre-indexed STR instruction instead, per the ARM ARM.
10191 if (Inst.getNumOperands() != 5)
10192 return false;
10193 MCInst TmpInst;
10194 TmpInst.setOpcode(ARM::t2STR_PRE);
10195 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10196 TmpInst.addOperand(Inst.getOperand(4)); // Rt
10197 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10198 TmpInst.addOperand(MCOperand::createImm(-4));
10199 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10200 TmpInst.addOperand(Inst.getOperand(3));
10201 Inst = TmpInst;
10202 return true;
10203 }
10204 case ARM::LDMIA_UPD:
10205 // If this is a load of a single register via a 'pop', then we should use
10206 // a post-indexed LDR instruction instead, per the ARM ARM.
10207 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10208 Inst.getNumOperands() == 5) {
10209 MCInst TmpInst;
10210 TmpInst.setOpcode(ARM::LDR_POST_IMM);
10211 TmpInst.addOperand(Inst.getOperand(4)); // Rt
10212 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10213 TmpInst.addOperand(Inst.getOperand(1)); // Rn
10214 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
10215 TmpInst.addOperand(MCOperand::createImm(4));
10216 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10217 TmpInst.addOperand(Inst.getOperand(3));
10218 Inst = TmpInst;
10219 return true;
10220 }
10221 break;
10222 case ARM::STMDB_UPD:
10223 // If this is a store of a single register via a 'push', then we should use
10224 // a pre-indexed STR instruction instead, per the ARM ARM.
10225 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10226 Inst.getNumOperands() == 5) {
10227 MCInst TmpInst;
10228 TmpInst.setOpcode(ARM::STR_PRE_IMM);
10229 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10230 TmpInst.addOperand(Inst.getOperand(4)); // Rt
10231 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
10232 TmpInst.addOperand(MCOperand::createImm(-4));
10233 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10234 TmpInst.addOperand(Inst.getOperand(3));
10235 Inst = TmpInst;
10236 }
10237 break;
10238 case ARM::t2ADDri12:
10239 case ARM::t2SUBri12:
10240 case ARM::t2ADDspImm12:
10241 case ARM::t2SUBspImm12: {
10242 // If the immediate fits for encoding T3 and the generic
10243 // mnemonic was used, encoding T3 is preferred.
10244 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10245 if ((Token != "add" && Token != "sub") ||
10246 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
10247 break;
10248 switch (Inst.getOpcode()) {
10249 case ARM::t2ADDri12:
10250 Inst.setOpcode(ARM::t2ADDri);
10251 break;
10252 case ARM::t2SUBri12:
10253 Inst.setOpcode(ARM::t2SUBri);
10254 break;
10255 case ARM::t2ADDspImm12:
10256 Inst.setOpcode(ARM::t2ADDspImm);
10257 break;
10258 case ARM::t2SUBspImm12:
10259 Inst.setOpcode(ARM::t2SUBspImm);
10260 break;
10261 }
10262
10263 Inst.addOperand(MCOperand::createReg(0)); // cc_out
10264 return true;
10265 }
10266 case ARM::tADDi8:
10267 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10268 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10269 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10270 // to encoding T1 if <Rd> is omitted."
10271 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10272 Inst.setOpcode(ARM::tADDi3);
10273 return true;
10274 }
10275 break;
10276 case ARM::tSUBi8:
10277 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10278 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10279 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10280 // to encoding T1 if <Rd> is omitted."
10281 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10282 Inst.setOpcode(ARM::tSUBi3);
10283 return true;
10284 }
10285 break;
10286 case ARM::t2ADDri:
10287 case ARM::t2SUBri: {
10288 // If the destination and first source operand are the same, and
10289 // the flags are compatible with the current IT status, use encoding T2
10290 // instead of T3. For compatibility with the system 'as'. Make sure the
10291 // wide encoding wasn't explicit.
10292 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
10293 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
10294 (Inst.getOperand(2).isImm() &&
10295 (unsigned)Inst.getOperand(2).getImm() > 255) ||
10296 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
10297 HasWideQualifier)
10298 break;
10299 MCInst TmpInst;
10300 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
10301 ARM::tADDi8 : ARM::tSUBi8);
10302 TmpInst.addOperand(Inst.getOperand(0));
10303 TmpInst.addOperand(Inst.getOperand(5));
10304 TmpInst.addOperand(Inst.getOperand(0));
10305 TmpInst.addOperand(Inst.getOperand(2));
10306 TmpInst.addOperand(Inst.getOperand(3));
10307 TmpInst.addOperand(Inst.getOperand(4));
10308 Inst = TmpInst;
10309 return true;
10310 }
10311 case ARM::t2ADDspImm:
10312 case ARM::t2SUBspImm: {
10313 // Prefer T1 encoding if possible
10314 if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
10315 break;
10316 unsigned V = Inst.getOperand(2).getImm();
10317 if (V & 3 || V > ((1 << 7) - 1) << 2)
10318 break;
10319 MCInst TmpInst;
10320 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi
10321 : ARM::tSUBspi);
10322 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg
10323 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg
10324 TmpInst.addOperand(MCOperand::createImm(V / 4)); // immediate
10325 TmpInst.addOperand(Inst.getOperand(3)); // pred
10326 TmpInst.addOperand(Inst.getOperand(4));
10327 Inst = TmpInst;
10328 return true;
10329 }
10330 case ARM::t2ADDrr: {
10331 // If the destination and first source operand are the same, and
10332 // there's no setting of the flags, use encoding T2 instead of T3.
10333 // Note that this is only for ADD, not SUB. This mirrors the system
10334 // 'as' behaviour. Also take advantage of ADD being commutative.
10335 // Make sure the wide encoding wasn't explicit.
10336 bool Swap = false;
10337 auto DestReg = Inst.getOperand(0).getReg();
10338 bool Transform = DestReg == Inst.getOperand(1).getReg();
10339 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
10340 Transform = true;
10341 Swap = true;
10342 }
10343 if (!Transform ||
10344 Inst.getOperand(5).getReg() != 0 ||
10345 HasWideQualifier)
10346 break;
10347 MCInst TmpInst;
10348 TmpInst.setOpcode(ARM::tADDhirr);
10349 TmpInst.addOperand(Inst.getOperand(0));
10350 TmpInst.addOperand(Inst.getOperand(0));
10351 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
10352 TmpInst.addOperand(Inst.getOperand(3));
10353 TmpInst.addOperand(Inst.getOperand(4));
10354 Inst = TmpInst;
10355 return true;
10356 }
10357 case ARM::tADDrSP:
10358 // If the non-SP source operand and the destination operand are not the
10359 // same, we need to use the 32-bit encoding if it's available.
10360 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
10361 Inst.setOpcode(ARM::t2ADDrr);
10362 Inst.addOperand(MCOperand::createReg(0)); // cc_out
10363 return true;
10364 }
10365 break;
10366 case ARM::tB:
10367 // A Thumb conditional branch outside of an IT block is a tBcc.
10368 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
10369 Inst.setOpcode(ARM::tBcc);
10370 return true;
10371 }
10372 break;
10373 case ARM::t2B:
10374 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
10375 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
10376 Inst.setOpcode(ARM::t2Bcc);
10377 return true;
10378 }
10379 break;
10380 case ARM::t2Bcc:
10381 // If the conditional is AL or we're in an IT block, we really want t2B.
10382 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
10383 Inst.setOpcode(ARM::t2B);
10384 return true;
10385 }
10386 break;
10387 case ARM::tBcc:
10388 // If the conditional is AL, we really want tB.
10389 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
10390 Inst.setOpcode(ARM::tB);
10391 return true;
10392 }
10393 break;
10394 case ARM::tLDMIA: {
10395 // If the register list contains any high registers, or if the writeback
10396 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
10397 // instead if we're in Thumb2. Otherwise, this should have generated
10398 // an error in validateInstruction().
10399 unsigned Rn = Inst.getOperand(0).getReg();
10400 bool hasWritebackToken =
10401 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
10402 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
10403 bool listContainsBase;
10404 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
10405 (!listContainsBase && !hasWritebackToken) ||
10406 (listContainsBase && hasWritebackToken)) {
10407 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10408 assert(isThumbTwo())(static_cast <bool> (isThumbTwo()) ? void (0) : __assert_fail
("isThumbTwo()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10408, __extension__ __PRETTY_FUNCTION__))
;
10409 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
10410 // If we're switching to the updating version, we need to insert
10411 // the writeback tied operand.
10412 if (hasWritebackToken)
10413 Inst.insert(Inst.begin(),
10414 MCOperand::createReg(Inst.getOperand(0).getReg()));
10415 return true;
10416 }
10417 break;
10418 }
10419 case ARM::tSTMIA_UPD: {
10420 // If the register list contains any high registers, we need to use
10421 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10422 // should have generated an error in validateInstruction().
10423 unsigned Rn = Inst.getOperand(0).getReg();
10424 bool listContainsBase;
10425 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
10426 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10427 assert(isThumbTwo())(static_cast <bool> (isThumbTwo()) ? void (0) : __assert_fail
("isThumbTwo()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10427, __extension__ __PRETTY_FUNCTION__))
;
10428 Inst.setOpcode(ARM::t2STMIA_UPD);
10429 return true;
10430 }
10431 break;
10432 }
10433 case ARM::tPOP: {
10434 bool listContainsBase;
10435 // If the register list contains any high registers, we need to use
10436 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10437 // should have generated an error in validateInstruction().
10438 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
10439 return false;
10440 assert(isThumbTwo())(static_cast <bool> (isThumbTwo()) ? void (0) : __assert_fail
("isThumbTwo()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10440, __extension__ __PRETTY_FUNCTION__))
;
10441 Inst.setOpcode(ARM::t2LDMIA_UPD);
10442 // Add the base register and writeback operands.
10443 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10444 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10445 return true;
10446 }
10447 case ARM::tPUSH: {
10448 bool listContainsBase;
10449 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
10450 return false;
10451 assert(isThumbTwo())(static_cast <bool> (isThumbTwo()) ? void (0) : __assert_fail
("isThumbTwo()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10451, __extension__ __PRETTY_FUNCTION__))
;
10452 Inst.setOpcode(ARM::t2STMDB_UPD);
10453 // Add the base register and writeback operands.
10454 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10455 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10456 return true;
10457 }
10458 case ARM::t2MOVi:
10459 // If we can use the 16-bit encoding and the user didn't explicitly
10460 // request the 32-bit variant, transform it here.
10461 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10462 (Inst.getOperand(1).isImm() &&
10463 (unsigned)Inst.getOperand(1).getImm() <= 255) &&
10464 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10465 !HasWideQualifier) {
10466 // The operands aren't in the same order for tMOVi8...
10467 MCInst TmpInst;
10468 TmpInst.setOpcode(ARM::tMOVi8);
10469 TmpInst.addOperand(Inst.getOperand(0));
10470 TmpInst.addOperand(Inst.getOperand(4));
10471 TmpInst.addOperand(Inst.getOperand(1));
10472 TmpInst.addOperand(Inst.getOperand(2));
10473 TmpInst.addOperand(Inst.getOperand(3));
10474 Inst = TmpInst;
10475 return true;
10476 }
10477 break;
10478
10479 case ARM::t2MOVr:
10480 // If we can use the 16-bit encoding and the user didn't explicitly
10481 // request the 32-bit variant, transform it here.
10482 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10483 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10484 Inst.getOperand(2).getImm() == ARMCC::AL &&
10485 Inst.getOperand(4).getReg() == ARM::CPSR &&
10486 !HasWideQualifier) {
10487 // The operands aren't the same for tMOV[S]r... (no cc_out)
10488 MCInst TmpInst;
10489 unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
10490 TmpInst.setOpcode(Op);
10491 TmpInst.addOperand(Inst.getOperand(0));
10492 TmpInst.addOperand(Inst.getOperand(1));
10493 if (Op == ARM::tMOVr) {
10494 TmpInst.addOperand(Inst.getOperand(2));
10495 TmpInst.addOperand(Inst.getOperand(3));
10496 }
10497 Inst = TmpInst;
10498 return true;
10499 }
10500 break;
10501
10502 case ARM::t2SXTH:
10503 case ARM::t2SXTB:
10504 case ARM::t2UXTH:
10505 case ARM::t2UXTB:
10506 // If we can use the 16-bit encoding and the user didn't explicitly
10507 // request the 32-bit variant, transform it here.
10508 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10509 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10510 Inst.getOperand(2).getImm() == 0 &&
10511 !HasWideQualifier) {
10512 unsigned NewOpc;
10513 switch (Inst.getOpcode()) {
10514 default: llvm_unreachable("Illegal opcode!")::llvm::llvm_unreachable_internal("Illegal opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10514)
;
10515 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
10516 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
10517 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
10518 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
10519 }
10520 // The operands aren't the same for thumb1 (no rotate operand).
10521 MCInst TmpInst;
10522 TmpInst.setOpcode(NewOpc);
10523 TmpInst.addOperand(Inst.getOperand(0));
10524 TmpInst.addOperand(Inst.getOperand(1));
10525 TmpInst.addOperand(Inst.getOperand(3));
10526 TmpInst.addOperand(Inst.getOperand(4));
10527 Inst = TmpInst;
10528 return true;
10529 }
10530 break;
10531
10532 case ARM::MOVsi: {
10533 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10534 // rrx shifts and asr/lsr of #32 is encoded as 0
10535 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10536 return false;
10537 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10538 // Shifting by zero is accepted as a vanilla 'MOVr'
10539 MCInst TmpInst;
10540 TmpInst.setOpcode(ARM::MOVr);
10541 TmpInst.addOperand(Inst.getOperand(0));
10542 TmpInst.addOperand(Inst.getOperand(1));
10543 TmpInst.addOperand(Inst.getOperand(3));
10544 TmpInst.addOperand(Inst.getOperand(4));
10545 TmpInst.addOperand(Inst.getOperand(5));
10546 Inst = TmpInst;
10547 return true;
10548 }
10549 return false;
10550 }
10551 case ARM::ANDrsi:
10552 case ARM::ORRrsi:
10553 case ARM::EORrsi:
10554 case ARM::BICrsi:
10555 case ARM::SUBrsi:
10556 case ARM::ADDrsi: {
10557 unsigned newOpc;
10558 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10559 if (SOpc == ARM_AM::rrx) return false;
10560 switch (Inst.getOpcode()) {
10561 default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10561)
;
10562 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
10563 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
10564 case ARM::EORrsi: newOpc = ARM::EORrr; break;
10565 case ARM::BICrsi: newOpc = ARM::BICrr; break;
10566 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
10567 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
10568 }
10569 // If the shift is by zero, use the non-shifted instruction definition.
10570 // The exception is for right shifts, where 0 == 32
10571 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10572 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
10573 MCInst TmpInst;
10574 TmpInst.setOpcode(newOpc);
10575 TmpInst.addOperand(Inst.getOperand(0));
10576 TmpInst.addOperand(Inst.getOperand(1));
10577 TmpInst.addOperand(Inst.getOperand(2));
10578 TmpInst.addOperand(Inst.getOperand(4));
10579 TmpInst.addOperand(Inst.getOperand(5));
10580 TmpInst.addOperand(Inst.getOperand(6));
10581 Inst = TmpInst;
10582 return true;
10583 }
10584 return false;
10585 }
10586 case ARM::ITasm:
10587 case ARM::t2IT: {
10588 // Set up the IT block state according to the IT instruction we just
10589 // matched.
10590 assert(!inITBlock() && "nested IT blocks?!")(static_cast <bool> (!inITBlock() && "nested IT blocks?!"
) ? void (0) : __assert_fail ("!inITBlock() && \"nested IT blocks?!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10590, __extension__
__PRETTY_FUNCTION__))
;
10591 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
10592 Inst.getOperand(1).getImm());
10593 break;
10594 }
10595 case ARM::t2LSLrr:
10596 case ARM::t2LSRrr:
10597 case ARM::t2ASRrr:
10598 case ARM::t2SBCrr:
10599 case ARM::t2RORrr:
10600 case ARM::t2BICrr:
10601 // Assemblers should use the narrow encodings of these instructions when permissible.
10602 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10603 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10604 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10605 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10606 !HasWideQualifier) {
10607 unsigned NewOpc;
10608 switch (Inst.getOpcode()) {
10609 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10609)
;
10610 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
10611 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
10612 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
10613 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
10614 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
10615 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
10616 }
10617 MCInst TmpInst;
10618 TmpInst.setOpcode(NewOpc);
10619 TmpInst.addOperand(Inst.getOperand(0));
10620 TmpInst.addOperand(Inst.getOperand(5));
10621 TmpInst.addOperand(Inst.getOperand(1));
10622 TmpInst.addOperand(Inst.getOperand(2));
10623 TmpInst.addOperand(Inst.getOperand(3));
10624 TmpInst.addOperand(Inst.getOperand(4));
10625 Inst = TmpInst;
10626 return true;
10627 }
10628 return false;
10629
10630 case ARM::t2ANDrr:
10631 case ARM::t2EORrr:
10632 case ARM::t2ADCrr:
10633 case ARM::t2ORRrr:
10634 // Assemblers should use the narrow encodings of these instructions when permissible.
10635 // These instructions are special in that they are commutable, so shorter encodings
10636 // are available more often.
10637 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10638 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10639 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
10640 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
10641 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10642 !HasWideQualifier) {
10643 unsigned NewOpc;
10644 switch (Inst.getOpcode()) {
10645 default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 10645)
;
10646 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
10647 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
10648 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
10649 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
10650 }
10651 MCInst TmpInst;
10652 TmpInst.setOpcode(NewOpc);
10653 TmpInst.addOperand(Inst.getOperand(0));
10654 TmpInst.addOperand(Inst.getOperand(5));
10655 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
10656 TmpInst.addOperand(Inst.getOperand(1));
10657 TmpInst.addOperand(Inst.getOperand(2));
10658 } else {
10659 TmpInst.addOperand(Inst.getOperand(2));
10660 TmpInst.addOperand(Inst.getOperand(1));
10661 }
10662 TmpInst.addOperand(Inst.getOperand(3));
10663 TmpInst.addOperand(Inst.getOperand(4));
10664 Inst = TmpInst;
10665 return true;
10666 }
10667 return false;
10668 case ARM::MVE_VPST:
10669 case ARM::MVE_VPTv16i8:
10670 case ARM::MVE_VPTv8i16:
10671 case ARM::MVE_VPTv4i32:
10672 case ARM::MVE_VPTv16u8:
10673 case ARM::MVE_VPTv8u16:
10674 case ARM::MVE_VPTv4u32:
10675 case ARM::MVE_VPTv16s8:
10676 case ARM::MVE_VPTv8s16:
10677 case ARM::MVE_VPTv4s32:
10678 case ARM::MVE_VPTv4f32:
10679 case ARM::MVE_VPTv8f16:
10680 case ARM::MVE_VPTv16i8r:
10681 case ARM::MVE_VPTv8i16r:
10682 case ARM::MVE_VPTv4i32r:
10683 case ARM::MVE_VPTv16u8r:
10684 case ARM::MVE_VPTv8u16r:
10685 case ARM::MVE_VPTv4u32r:
10686 case ARM::MVE_VPTv16s8r:
10687 case ARM::MVE_VPTv8s16r:
10688 case ARM::MVE_VPTv4s32r:
10689 case ARM::MVE_VPTv4f32r:
10690 case ARM::MVE_VPTv8f16r: {
10691 assert(!inVPTBlock() && "Nested VPT blocks are not allowed")(static_cast <bool> (!inVPTBlock() && "Nested VPT blocks are not allowed"
) ? void (0) : __assert_fail ("!inVPTBlock() && \"Nested VPT blocks are not allowed\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10691, __extension__
__PRETTY_FUNCTION__))
;
10692 MCOperand &MO = Inst.getOperand(0);
10693 VPTState.Mask = MO.getImm();
10694 VPTState.CurPosition = 0;
10695 break;
10696 }
10697 }
10698 return false;
10699}
10700
10701unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10702 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
10703 // suffix depending on whether they're in an IT block or not.
10704 unsigned Opc = Inst.getOpcode();
10705 const MCInstrDesc &MCID = MII.get(Opc);
10706 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
10707 assert(MCID.hasOptionalDef() &&(static_cast <bool> (MCID.hasOptionalDef() && "optionally flag setting instruction missing optional def operand"
) ? void (0) : __assert_fail ("MCID.hasOptionalDef() && \"optionally flag setting instruction missing optional def operand\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10708, __extension__
__PRETTY_FUNCTION__))
10708 "optionally flag setting instruction missing optional def operand")(static_cast <bool> (MCID.hasOptionalDef() && "optionally flag setting instruction missing optional def operand"
) ? void (0) : __assert_fail ("MCID.hasOptionalDef() && \"optionally flag setting instruction missing optional def operand\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10708, __extension__
__PRETTY_FUNCTION__))
;
10709 assert(MCID.NumOperands == Inst.getNumOperands() &&(static_cast <bool> (MCID.NumOperands == Inst.getNumOperands
() && "operand count mismatch!") ? void (0) : __assert_fail
("MCID.NumOperands == Inst.getNumOperands() && \"operand count mismatch!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10710, __extension__
__PRETTY_FUNCTION__))
10710 "operand count mismatch!")(static_cast <bool> (MCID.NumOperands == Inst.getNumOperands
() && "operand count mismatch!") ? void (0) : __assert_fail
("MCID.NumOperands == Inst.getNumOperands() && \"operand count mismatch!\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 10710, __extension__
__PRETTY_FUNCTION__))
;
10711 // Find the optional-def operand (cc_out).
10712 unsigned OpNo;
10713 for (OpNo = 0;
10714 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10715 ++OpNo)
10716 ;
10717 // If we're parsing Thumb1, reject it completely.
10718 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10719 return Match_RequiresFlagSetting;
10720 // If we're parsing Thumb2, which form is legal depends on whether we're
10721 // in an IT block.
10722 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10723 !inITBlock())
10724 return Match_RequiresITBlock;
10725 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10726 inITBlock())
10727 return Match_RequiresNotITBlock;
10728 // LSL with zero immediate is not allowed in an IT block
10729 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
10730 return Match_RequiresNotITBlock;
10731 } else if (isThumbOne()) {
10732 // Some high-register supporting Thumb1 encodings only allow both registers
10733 // to be from r0-r7 when in Thumb2.
10734 if (Opc == ARM::tADDhirr && !hasV6MOps() &&
10735 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10736 isARMLowRegister(Inst.getOperand(2).getReg()))
10737 return Match_RequiresThumb2;
10738 // Others only require ARMv6 or later.
10739 else if (Opc == ARM::tMOVr && !hasV6Ops() &&
10740 isARMLowRegister(Inst.getOperand(0).getReg()) &&
10741 isARMLowRegister(Inst.getOperand(1).getReg()))
10742 return Match_RequiresV6;
10743 }
10744
10745 // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
10746 // than the loop below can handle, so it uses the GPRnopc register class and
10747 // we do SP handling here.
10748 if (Opc == ARM::t2MOVr && !hasV8Ops())
10749 {
10750 // SP as both source and destination is not allowed
10751 if (Inst.getOperand(0).getReg() == ARM::SP &&
10752 Inst.getOperand(1).getReg() == ARM::SP)
10753 return Match_RequiresV8;
10754 // When flags-setting SP as either source or destination is not allowed
10755 if (Inst.getOperand(4).getReg() == ARM::CPSR &&
10756 (Inst.getOperand(0).getReg() == ARM::SP ||
10757 Inst.getOperand(1).getReg() == ARM::SP))
10758 return Match_RequiresV8;
10759 }
10760
10761 switch (Inst.getOpcode()) {
10762 case ARM::VMRS:
10763 case ARM::VMSR:
10764 case ARM::VMRS_FPCXTS:
10765 case ARM::VMRS_FPCXTNS:
10766 case ARM::VMSR_FPCXTS:
10767 case ARM::VMSR_FPCXTNS:
10768 case ARM::VMRS_FPSCR_NZCVQC:
10769 case ARM::VMSR_FPSCR_NZCVQC:
10770 case ARM::FMSTAT:
10771 case ARM::VMRS_VPR:
10772 case ARM::VMRS_P0:
10773 case ARM::VMSR_VPR:
10774 case ARM::VMSR_P0:
10775 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
10776 // ARMv8-A.
10777 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10778 (isThumb() && !hasV8Ops()))
10779 return Match_InvalidOperand;
10780 break;
10781 case ARM::t2TBB:
10782 case ARM::t2TBH:
10783 // Rn = sp is only allowed with ARMv8-A
10784 if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
10785 return Match_RequiresV8;
10786 break;
10787 default:
10788 break;
10789 }
10790
10791 for (unsigned I = 0; I < MCID.NumOperands; ++I)
10792 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
10793 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10794 const auto &Op = Inst.getOperand(I);
10795 if (!Op.isReg()) {
10796 // This can happen in awkward cases with tied operands, e.g. a
10797 // writeback load/store with a complex addressing mode in
10798 // which there's an output operand corresponding to the
10799 // updated written-back base register: the Tablegen-generated
10800 // AsmMatcher will have written a placeholder operand to that
10801 // slot in the form of an immediate 0, because it can't
10802 // generate the register part of the complex addressing-mode
10803 // operand ahead of time.
10804 continue;
10805 }
10806
10807 unsigned Reg = Op.getReg();
10808 if ((Reg == ARM::SP) && !hasV8Ops())
10809 return Match_RequiresV8;
10810 else if (Reg == ARM::PC)
10811 return Match_InvalidOperand;
10812 }
10813
10814 return Match_Success;
10815}
10816
10817namespace llvm {
10818
10819template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10820 return true; // In an assembly source, no need to second-guess
10821}
10822
10823} // end namespace llvm
10824
10825// Returns true if Inst is unpredictable if it is in and IT block, but is not
10826// the last instruction in the block.
10827bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10828 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10829
10830 // All branch & call instructions terminate IT blocks with the exception of
10831 // SVC.
10832 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10833 MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
10834 return true;
10835
10836 // Any arithmetic instruction which writes to the PC also terminates the IT
10837 // block.
10838 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
10839 return true;
10840
10841 return false;
10842}
10843
10844unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10845 SmallVectorImpl<NearMissInfo> &NearMisses,
10846 bool MatchingInlineAsm,
10847 bool &EmitInITBlock,
10848 MCStreamer &Out) {
10849 // If we can't use an implicit IT block here, just match as normal.
10850 if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
10851 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10852
10853 // Try to match the instruction in an extension of the current IT block (if
10854 // there is one).
10855 if (inImplicitITBlock()) {
10856 extendImplicitITBlock(ITState.Cond);
10857 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10858 Match_Success) {
10859 // The match succeded, but we still have to check that the instruction is
10860 // valid in this implicit IT block.
10861 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10862 if (MCID.isPredicable()) {
10863 ARMCC::CondCodes InstCond =
10864 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10865 .getImm();
10866 ARMCC::CondCodes ITCond = currentITCond();
10867 if (InstCond == ITCond) {
10868 EmitInITBlock = true;
10869 return Match_Success;
10870 } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
10871 invertCurrentITCondition();
10872 EmitInITBlock = true;
10873 return Match_Success;
10874 }
10875 }
10876 }
10877 rewindImplicitITPosition();
10878 }
10879
10880 // Finish the current IT block, and try to match outside any IT block.
10881 flushPendingInstructions(Out);
10882 unsigned PlainMatchResult =
10883 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10884 if (PlainMatchResult == Match_Success) {
10885 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10886 if (MCID.isPredicable()) {
10887 ARMCC::CondCodes InstCond =
10888 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10889 .getImm();
10890 // Some forms of the branch instruction have their own condition code
10891 // fields, so can be conditionally executed without an IT block.
10892 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10893 EmitInITBlock = false;
10894 return Match_Success;
10895 }
10896 if (InstCond == ARMCC::AL) {
10897 EmitInITBlock = false;
10898 return Match_Success;
10899 }
10900 } else {
10901 EmitInITBlock = false;
10902 return Match_Success;
10903 }
10904 }
10905
10906 // Try to match in a new IT block. The matcher doesn't check the actual
10907 // condition, so we create an IT block with a dummy condition, and fix it up
10908 // once we know the actual condition.
10909 startImplicitITBlock();
10910 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10911 Match_Success) {
10912 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10913 if (MCID.isPredicable()) {
10914 ITState.Cond =
10915 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10916 .getImm();
10917 EmitInITBlock = true;
10918 return Match_Success;
10919 }
10920 }
10921 discardImplicitITBlock();
10922
10923 // If none of these succeed, return the error we got when trying to match
10924 // outside any IT blocks.
10925 EmitInITBlock = false;
10926 return PlainMatchResult;
10927}
10928
10929static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
10930 unsigned VariantID = 0);
10931
10932static const char *getSubtargetFeatureName(uint64_t Val);
10933bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
10934 OperandVector &Operands,
10935 MCStreamer &Out, uint64_t &ErrorInfo,
10936 bool MatchingInlineAsm) {
10937 MCInst Inst;
10938 unsigned MatchResult;
10939 bool PendConditionalInstruction = false;
10940
10941 SmallVector<NearMissInfo, 4> NearMisses;
10942 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
10943 PendConditionalInstruction, Out);
10944
10945 switch (MatchResult) {
10946 case Match_Success:
10947 LLVM_DEBUG(dbgs() << "Parsed as: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10948 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10949 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Parsed as: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
;
10950
10951 // Context sensitive operand constraints aren't handled by the matcher,
10952 // so check them here.
10953 if (validateInstruction(Inst, Operands)) {
10954 // Still progress the IT block, otherwise one wrong condition causes
10955 // nasty cascading errors.
10956 forwardITPosition();
10957 forwardVPTPosition();
10958 return true;
10959 }
10960
10961 {
10962 // Some instructions need post-processing to, for example, tweak which
10963 // encoding is selected. Loop on it while changes happen so the
10964 // individual transformations can chain off each other. E.g.,
10965 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
10966 while (processInstruction(Inst, Operands, Out))
10967 LLVM_DEBUG(dbgs() << "Changed to: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10968 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
10969 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Changed to: "; Inst.dump_pretty
(dbgs(), MII.getName(Inst.getOpcode())); dbgs() << "\n"
; } } while (false)
;
10970 }
10971
10972 // Only move forward at the very end so that everything in validate
10973 // and process gets a consistent answer about whether we're in an IT
10974 // block.
10975 forwardITPosition();
10976 forwardVPTPosition();
10977
10978 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
10979 // doesn't actually encode.
10980 if (Inst.getOpcode() == ARM::ITasm)
10981 return false;
10982
10983 Inst.setLoc(IDLoc);
10984 if (PendConditionalInstruction) {
10985 PendingConditionalInsts.push_back(Inst);
10986 if (isITBlockFull() || isITBlockTerminator(Inst))
10987 flushPendingInstructions(Out);
10988 } else {
10989 Out.emitInstruction(Inst, getSTI());
10990 }
10991 return false;
10992 case Match_NearMisses:
10993 ReportNearMisses(NearMisses, IDLoc, Operands);
10994 return true;
10995 case Match_MnemonicFail: {
10996 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
10997 std::string Suggestion = ARMMnemonicSpellCheck(
10998 ((ARMOperand &)*Operands[0]).getToken(), FBS);
10999 return Error(IDLoc, "invalid instruction" + Suggestion,
11000 ((ARMOperand &)*Operands[0]).getLocRange());
11001 }
11002 }
11003
11004 llvm_unreachable("Implement any new match types added!")::llvm::llvm_unreachable_internal("Implement any new match types added!"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 11004)
;
11005}
11006
11007/// parseDirective parses the arm specific directives
11008bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
11009 const MCContext::Environment Format = getContext().getObjectFileType();
11010 bool IsMachO = Format == MCContext::IsMachO;
1
Assuming 'Format' is not equal to IsMachO
11011 bool IsCOFF = Format == MCContext::IsCOFF;
2
Assuming 'Format' is not equal to IsCOFF
11012
11013 std::string IDVal = DirectiveID.getIdentifier().lower();
11014 if (IDVal == ".word")
11015 parseLiteralValues(4, DirectiveID.getLoc());
11016 else if (IDVal == ".short" || IDVal == ".hword")
3
Taking false branch
11017 parseLiteralValues(2, DirectiveID.getLoc());
11018 else if (IDVal == ".thumb")
4
Taking false branch
11019 parseDirectiveThumb(DirectiveID.getLoc());
11020 else if (IDVal == ".arm")
5
Taking false branch
11021 parseDirectiveARM(DirectiveID.getLoc());
11022 else if (IDVal == ".thumb_func")
6
Taking false branch
11023 parseDirectiveThumbFunc(DirectiveID.getLoc());
11024 else if (IDVal == ".code")
7
Taking false branch
11025 parseDirectiveCode(DirectiveID.getLoc());
11026 else if (IDVal == ".syntax")
8
Taking false branch
11027 parseDirectiveSyntax(DirectiveID.getLoc());
11028 else if (IDVal == ".unreq")
9
Taking false branch
11029 parseDirectiveUnreq(DirectiveID.getLoc());
11030 else if (IDVal == ".fnend")
10
Taking false branch
11031 parseDirectiveFnEnd(DirectiveID.getLoc());
11032 else if (IDVal == ".cantunwind")
11
Taking false branch
11033 parseDirectiveCantUnwind(DirectiveID.getLoc());
11034 else if (IDVal == ".personality")
12
Taking false branch
11035 parseDirectivePersonality(DirectiveID.getLoc());
11036 else if (IDVal == ".handlerdata")
13
Taking false branch
11037 parseDirectiveHandlerData(DirectiveID.getLoc());
11038 else if (IDVal == ".setfp")
14
Taking false branch
11039 parseDirectiveSetFP(DirectiveID.getLoc());
11040 else if (IDVal == ".pad")
15
Taking false branch
11041 parseDirectivePad(DirectiveID.getLoc());
11042 else if (IDVal == ".save")
16
Taking false branch
11043 parseDirectiveRegSave(DirectiveID.getLoc(), false);
11044 else if (IDVal == ".vsave")
11045 parseDirectiveRegSave(DirectiveID.getLoc(), true);
11046 else if (IDVal == ".ltorg" || IDVal == ".pool")
17
Taking false branch
11047 parseDirectiveLtorg(DirectiveID.getLoc());
11048 else if (IDVal == ".even")
18
Taking false branch
11049 parseDirectiveEven(DirectiveID.getLoc());
11050 else if (IDVal == ".personalityindex")
19
Taking false branch
11051 parseDirectivePersonalityIndex(DirectiveID.getLoc());
11052 else if (IDVal == ".unwind_raw")
20
Taking false branch
11053 parseDirectiveUnwindRaw(DirectiveID.getLoc());
11054 else if (IDVal == ".movsp")
21
Taking false branch
11055 parseDirectiveMovSP(DirectiveID.getLoc());
11056 else if (IDVal == ".arch_extension")
22
Taking false branch
11057 parseDirectiveArchExtension(DirectiveID.getLoc());
11058 else if (IDVal == ".align")
23
Taking false branch
11059 return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
11060 else if (IDVal == ".thumb_set")
24
Taking false branch
11061 parseDirectiveThumbSet(DirectiveID.getLoc());
11062 else if (IDVal == ".inst")
25
Taking false branch
11063 parseDirectiveInst(DirectiveID.getLoc());
11064 else if (IDVal == ".inst.n")
26
Taking false branch
11065 parseDirectiveInst(DirectiveID.getLoc(), 'n');
11066 else if (IDVal == ".inst.w")
11067 parseDirectiveInst(DirectiveID.getLoc(), 'w');
11068 else if (!IsMachO
26.1
'IsMachO' is false
&& !IsCOFF
26.2
'IsCOFF' is false
) {
27
Taking true branch
11069 if (IDVal == ".arch")
28
Taking false branch
11070 parseDirectiveArch(DirectiveID.getLoc());
11071 else if (IDVal == ".cpu")
29
Taking false branch
11072 parseDirectiveCPU(DirectiveID.getLoc());
11073 else if (IDVal == ".eabi_attribute")
30
Taking true branch
11074 parseDirectiveEabiAttr(DirectiveID.getLoc());
31
Calling 'ARMAsmParser::parseDirectiveEabiAttr'
11075 else if (IDVal == ".fpu")
11076 parseDirectiveFPU(DirectiveID.getLoc());
11077 else if (IDVal == ".fnstart")
11078 parseDirectiveFnStart(DirectiveID.getLoc());
11079 else if (IDVal == ".object_arch")
11080 parseDirectiveObjectArch(DirectiveID.getLoc());
11081 else if (IDVal == ".tlsdescseq")
11082 parseDirectiveTLSDescSeq(DirectiveID.getLoc());
11083 else
11084 return true;
11085 } else
11086 return true;
11087 return false;
11088}
11089
11090/// parseLiteralValues
11091/// ::= .hword expression [, expression]*
11092/// ::= .short expression [, expression]*
11093/// ::= .word expression [, expression]*
11094bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
11095 auto parseOne = [&]() -> bool {
11096 const MCExpr *Value;
11097 if (getParser().parseExpression(Value))
11098 return true;
11099 getParser().getStreamer().emitValue(Value, Size, L);
11100 return false;
11101 };
11102 return (parseMany(parseOne));
11103}
11104
11105/// parseDirectiveThumb
11106/// ::= .thumb
11107bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
11108 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
11109 check(!hasThumb(), L, "target does not support Thumb mode"))
11110 return true;
11111
11112 if (!isThumb())
11113 SwitchMode();
11114
11115 getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11116 return false;
11117}
11118
11119/// parseDirectiveARM
11120/// ::= .arm
11121bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
11122 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
11123 check(!hasARM(), L, "target does not support ARM mode"))
11124 return true;
11125
11126 if (isThumb())
11127 SwitchMode();
11128 getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
11129 return false;
11130}
11131
11132void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) {
11133 // We need to flush the current implicit IT block on a label, because it is
11134 // not legal to branch into an IT block.
11135 flushPendingInstructions(getStreamer());
11136}
11137
11138void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
11139 if (NextSymbolIsThumb) {
11140 getParser().getStreamer().emitThumbFunc(Symbol);
11141 NextSymbolIsThumb = false;
11142 }
11143}
11144
11145/// parseDirectiveThumbFunc
11146/// ::= .thumbfunc symbol_name
11147bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
11148 MCAsmParser &Parser = getParser();
11149 const auto Format = getContext().getObjectFileType();
11150 bool IsMachO = Format == MCContext::IsMachO;
11151
11152 // Darwin asm has (optionally) function name after .thumb_func direction
11153 // ELF doesn't
11154
11155 if (IsMachO) {
11156 if (Parser.getTok().is(AsmToken::Identifier) ||
11157 Parser.getTok().is(AsmToken::String)) {
11158 MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
11159 Parser.getTok().getIdentifier());
11160 getParser().getStreamer().emitThumbFunc(Func);
11161 Parser.Lex();
11162 if (parseToken(AsmToken::EndOfStatement,
11163 "unexpected token in '.thumb_func' directive"))
11164 return true;
11165 return false;
11166 }
11167 }
11168
11169 if (parseToken(AsmToken::EndOfStatement,
11170 "unexpected token in '.thumb_func' directive"))
11171 return true;
11172
11173 // .thumb_func implies .thumb
11174 if (!isThumb())
11175 SwitchMode();
11176
11177 getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11178
11179 NextSymbolIsThumb = true;
11180 return false;
11181}
11182
11183/// parseDirectiveSyntax
11184/// ::= .syntax unified | divided
11185bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
11186 MCAsmParser &Parser = getParser();
11187 const AsmToken &Tok = Parser.getTok();
11188 if (Tok.isNot(AsmToken::Identifier)) {
11189 Error(L, "unexpected token in .syntax directive");
11190 return false;
11191 }
11192
11193 StringRef Mode = Tok.getString();
11194 Parser.Lex();
11195 if (check(Mode == "divided" || Mode == "DIVIDED", L,
11196 "'.syntax divided' arm assembly not supported") ||
11197 check(Mode != "unified" && Mode != "UNIFIED", L,
11198 "unrecognized syntax mode in .syntax directive") ||
11199 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11200 return true;
11201
11202 // TODO tell the MC streamer the mode
11203 // getParser().getStreamer().Emit???();
11204 return false;
11205}
11206
11207/// parseDirectiveCode
11208/// ::= .code 16 | 32
11209bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
11210 MCAsmParser &Parser = getParser();
11211 const AsmToken &Tok = Parser.getTok();
11212 if (Tok.isNot(AsmToken::Integer))
11213 return Error(L, "unexpected token in .code directive");
11214 int64_t Val = Parser.getTok().getIntVal();
11215 if (Val != 16 && Val != 32) {
11216 Error(L, "invalid operand to .code directive");
11217 return false;
11218 }
11219 Parser.Lex();
11220
11221 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11222 return true;
11223
11224 if (Val == 16) {
11225 if (!hasThumb())
11226 return Error(L, "target does not support Thumb mode");
11227
11228 if (!isThumb())
11229 SwitchMode();
11230 getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11231 } else {
11232 if (!hasARM())
11233 return Error(L, "target does not support ARM mode");
11234
11235 if (isThumb())
11236 SwitchMode();
11237 getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
11238 }
11239
11240 return false;
11241}
11242
11243/// parseDirectiveReq
11244/// ::= name .req registername
11245bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
11246 MCAsmParser &Parser = getParser();
11247 Parser.Lex(); // Eat the '.req' token.
11248 unsigned Reg;
11249 SMLoc SRegLoc, ERegLoc;
11250 if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
11251 "register name expected") ||
11252 parseToken(AsmToken::EndOfStatement,
11253 "unexpected input in .req directive."))
11254 return true;
11255
11256 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
11257 return Error(SRegLoc,
11258 "redefinition of '" + Name + "' does not match original.");
11259
11260 return false;
11261}
11262
11263/// parseDirectiveUneq
11264/// ::= .unreq registername
11265bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
11266 MCAsmParser &Parser = getParser();
11267 if (Parser.getTok().isNot(AsmToken::Identifier))
11268 return Error(L, "unexpected input in .unreq directive.");
11269 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
11270 Parser.Lex(); // Eat the identifier.
11271 if (parseToken(AsmToken::EndOfStatement,
11272 "unexpected input in '.unreq' directive"))
11273 return true;
11274 return false;
11275}
11276
11277// After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
11278// before, if supported by the new target, or emit mapping symbols for the mode
11279// switch.
11280void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
11281 if (WasThumb != isThumb()) {
11282 if (WasThumb && hasThumb()) {
11283 // Stay in Thumb mode
11284 SwitchMode();
11285 } else if (!WasThumb && hasARM()) {
11286 // Stay in ARM mode
11287 SwitchMode();
11288 } else {
11289 // Mode switch forced, because the new arch doesn't support the old mode.
11290 getParser().getStreamer().emitAssemblerFlag(isThumb() ? MCAF_Code16
11291 : MCAF_Code32);
11292 // Warn about the implcit mode switch. GAS does not switch modes here,
11293 // but instead stays in the old mode, reporting an error on any following
11294 // instructions as the mode does not exist on the target.
11295 Warning(Loc, Twine("new target does not support ") +
11296 (WasThumb ? "thumb" : "arm") + " mode, switching to " +
11297 (!WasThumb ? "thumb" : "arm") + " mode");
11298 }
11299 }
11300}
11301
11302/// parseDirectiveArch
11303/// ::= .arch token
11304bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
11305 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
11306 ARM::ArchKind ID = ARM::parseArch(Arch);
11307
11308 if (ID == ARM::ArchKind::INVALID)
11309 return Error(L, "Unknown arch name");
11310
11311 bool WasThumb = isThumb();
11312 Triple T;
11313 MCSubtargetInfo &STI = copySTI();
11314 STI.setDefaultFeatures("", /*TuneCPU*/ "",
11315 ("+" + ARM::getArchName(ID)).str());
11316 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11317 FixModeAfterArchChange(WasThumb, L);
11318
11319 getTargetStreamer().emitArch(ID);
11320 return false;
11321}
11322
11323/// parseDirectiveEabiAttr
11324/// ::= .eabi_attribute int, int [, "str"]
11325/// ::= .eabi_attribute Tag_name, int [, "str"]
11326bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
11327 MCAsmParser &Parser = getParser();
11328 int64_t Tag;
11329 SMLoc TagLoc;
11330 TagLoc = Parser.getTok().getLoc();
11331 if (Parser.getTok().is(AsmToken::Identifier)) {
32
Taking false branch
11332 StringRef Name = Parser.getTok().getIdentifier();
11333 Optional<unsigned> Ret = ELFAttrs::attrTypeFromString(
11334 Name, ARMBuildAttrs::getARMAttributeTags());
11335 if (!Ret.hasValue()) {
11336 Error(TagLoc, "attribute name not recognised: " + Name);
11337 return false;
11338 }
11339 Tag = Ret.getValue();
11340 Parser.Lex();
11341 } else {
11342 const MCExpr *AttrExpr;
11343
11344 TagLoc = Parser.getTok().getLoc();
11345 if (Parser.parseExpression(AttrExpr))
33
Assuming the condition is false
34
Taking false branch
11346 return true;
11347
11348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
35
Assuming 'AttrExpr' is not a 'MCConstantExpr'
36
'CE' initialized to a null pointer value
11349 if (check(!CE, TagLoc, "expected numeric constant"))
37
Assuming the condition is false
38
Taking false branch
11350 return true;
11351
11352 Tag = CE->getValue();
39
Called C++ object pointer is null
11353 }
11354
11355 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11356 return true;
11357
11358 StringRef StringValue = "";
11359 bool IsStringValue = false;
11360
11361 int64_t IntegerValue = 0;
11362 bool IsIntegerValue = false;
11363
11364 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
11365 IsStringValue = true;
11366 else if (Tag == ARMBuildAttrs::compatibility) {
11367 IsStringValue = true;
11368 IsIntegerValue = true;
11369 } else if (Tag < 32 || Tag % 2 == 0)
11370 IsIntegerValue = true;
11371 else if (Tag % 2 == 1)
11372 IsStringValue = true;
11373 else
11374 llvm_unreachable("invalid tag type")::llvm::llvm_unreachable_internal("invalid tag type", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 11374)
;
11375
11376 if (IsIntegerValue) {
11377 const MCExpr *ValueExpr;
11378 SMLoc ValueExprLoc = Parser.getTok().getLoc();
11379 if (Parser.parseExpression(ValueExpr))
11380 return true;
11381
11382 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
11383 if (!CE)
11384 return Error(ValueExprLoc, "expected numeric constant");
11385 IntegerValue = CE->getValue();
11386 }
11387
11388 if (Tag == ARMBuildAttrs::compatibility) {
11389 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11390 return true;
11391 }
11392
11393 if (IsStringValue) {
11394 if (Parser.getTok().isNot(AsmToken::String))
11395 return Error(Parser.getTok().getLoc(), "bad string constant");
11396
11397 StringValue = Parser.getTok().getStringContents();
11398 Parser.Lex();
11399 }
11400
11401 if (Parser.parseToken(AsmToken::EndOfStatement,
11402 "unexpected token in '.eabi_attribute' directive"))
11403 return true;
11404
11405 if (IsIntegerValue && IsStringValue) {
11406 assert(Tag == ARMBuildAttrs::compatibility)(static_cast <bool> (Tag == ARMBuildAttrs::compatibility
) ? void (0) : __assert_fail ("Tag == ARMBuildAttrs::compatibility"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 11406, __extension__
__PRETTY_FUNCTION__))
;
11407 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
11408 } else if (IsIntegerValue)
11409 getTargetStreamer().emitAttribute(Tag, IntegerValue);
11410 else if (IsStringValue)
11411 getTargetStreamer().emitTextAttribute(Tag, StringValue);
11412 return false;
11413}
11414
11415/// parseDirectiveCPU
11416/// ::= .cpu str
11417bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
11418 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
11419 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
11420
11421 // FIXME: This is using table-gen data, but should be moved to
11422 // ARMTargetParser once that is table-gen'd.
11423 if (!getSTI().isCPUStringValid(CPU))
11424 return Error(L, "Unknown CPU name");
11425
11426 bool WasThumb = isThumb();
11427 MCSubtargetInfo &STI = copySTI();
11428 STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
11429 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11430 FixModeAfterArchChange(WasThumb, L);
11431
11432 return false;
11433}
11434
11435/// parseDirectiveFPU
11436/// ::= .fpu str
11437bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
11438 SMLoc FPUNameLoc = getTok().getLoc();
11439 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
11440
11441 unsigned ID = ARM::parseFPU(FPU);
11442 std::vector<StringRef> Features;
11443 if (!ARM::getFPUFeatures(ID, Features))
11444 return Error(FPUNameLoc, "Unknown FPU name");
11445
11446 MCSubtargetInfo &STI = copySTI();
11447 for (auto Feature : Features)
11448 STI.ApplyFeatureFlag(Feature);
11449 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11450
11451 getTargetStreamer().emitFPU(ID);
11452 return false;
11453}
11454
11455/// parseDirectiveFnStart
11456/// ::= .fnstart
11457bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
11458 if (parseToken(AsmToken::EndOfStatement,
11459 "unexpected token in '.fnstart' directive"))
11460 return true;
11461
11462 if (UC.hasFnStart()) {
11463 Error(L, ".fnstart starts before the end of previous one");
11464 UC.emitFnStartLocNotes();
11465 return true;
11466 }
11467
11468 // Reset the unwind directives parser state
11469 UC.reset();
11470
11471 getTargetStreamer().emitFnStart();
11472
11473 UC.recordFnStart(L);
11474 return false;
11475}
11476
11477/// parseDirectiveFnEnd
11478/// ::= .fnend
11479bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
11480 if (parseToken(AsmToken::EndOfStatement,
11481 "unexpected token in '.fnend' directive"))
11482 return true;
11483 // Check the ordering of unwind directives
11484 if (!UC.hasFnStart())
11485 return Error(L, ".fnstart must precede .fnend directive");
11486
11487 // Reset the unwind directives parser state
11488 getTargetStreamer().emitFnEnd();
11489
11490 UC.reset();
11491 return false;
11492}
11493
11494/// parseDirectiveCantUnwind
11495/// ::= .cantunwind
11496bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
11497 if (parseToken(AsmToken::EndOfStatement,
11498 "unexpected token in '.cantunwind' directive"))
11499 return true;
11500
11501 UC.recordCantUnwind(L);
11502 // Check the ordering of unwind directives
11503 if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
11504 return true;
11505
11506 if (UC.hasHandlerData()) {
11507 Error(L, ".cantunwind can't be used with .handlerdata directive");
11508 UC.emitHandlerDataLocNotes();
11509 return true;
11510 }
11511 if (UC.hasPersonality()) {
11512 Error(L, ".cantunwind can't be used with .personality directive");
11513 UC.emitPersonalityLocNotes();
11514 return true;
11515 }
11516
11517 getTargetStreamer().emitCantUnwind();
11518 return false;
11519}
11520
11521/// parseDirectivePersonality
11522/// ::= .personality name
11523bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
11524 MCAsmParser &Parser = getParser();
11525 bool HasExistingPersonality = UC.hasPersonality();
11526
11527 // Parse the name of the personality routine
11528 if (Parser.getTok().isNot(AsmToken::Identifier))
11529 return Error(L, "unexpected input in .personality directive.");
11530 StringRef Name(Parser.getTok().getIdentifier());
11531 Parser.Lex();
11532
11533 if (parseToken(AsmToken::EndOfStatement,
11534 "unexpected token in '.personality' directive"))
11535 return true;
11536
11537 UC.recordPersonality(L);
11538
11539 // Check the ordering of unwind directives
11540 if (!UC.hasFnStart())
11541 return Error(L, ".fnstart must precede .personality directive");
11542 if (UC.cantUnwind()) {
11543 Error(L, ".personality can't be used with .cantunwind directive");
11544 UC.emitCantUnwindLocNotes();
11545 return true;
11546 }
11547 if (UC.hasHandlerData()) {
11548 Error(L, ".personality must precede .handlerdata directive");
11549 UC.emitHandlerDataLocNotes();
11550 return true;
11551 }
11552 if (HasExistingPersonality) {
11553 Error(L, "multiple personality directives");
11554 UC.emitPersonalityLocNotes();
11555 return true;
11556 }
11557
11558 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
11559 getTargetStreamer().emitPersonality(PR);
11560 return false;
11561}
11562
11563/// parseDirectiveHandlerData
11564/// ::= .handlerdata
11565bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
11566 if (parseToken(AsmToken::EndOfStatement,
11567 "unexpected token in '.handlerdata' directive"))
11568 return true;
11569
11570 UC.recordHandlerData(L);
11571 // Check the ordering of unwind directives
11572 if (!UC.hasFnStart())
11573 return Error(L, ".fnstart must precede .personality directive");
11574 if (UC.cantUnwind()) {
11575 Error(L, ".handlerdata can't be used with .cantunwind directive");
11576 UC.emitCantUnwindLocNotes();
11577 return true;
11578 }
11579
11580 getTargetStreamer().emitHandlerData();
11581 return false;
11582}
11583
11584/// parseDirectiveSetFP
11585/// ::= .setfp fpreg, spreg [, offset]
11586bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
11587 MCAsmParser &Parser = getParser();
11588 // Check the ordering of unwind directives
11589 if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
11590 check(UC.hasHandlerData(), L,
11591 ".setfp must precede .handlerdata directive"))
11592 return true;
11593
11594 // Parse fpreg
11595 SMLoc FPRegLoc = Parser.getTok().getLoc();
11596 int FPReg = tryParseRegister();
11597
11598 if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
11599 Parser.parseToken(AsmToken::Comma, "comma expected"))
11600 return true;
11601
11602 // Parse spreg
11603 SMLoc SPRegLoc = Parser.getTok().getLoc();
11604 int SPReg = tryParseRegister();
11605 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11606 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11607 "register should be either $sp or the latest fp register"))
11608 return true;
11609
11610 // Update the frame pointer register
11611 UC.saveFPReg(FPReg);
11612
11613 // Parse offset
11614 int64_t Offset = 0;
11615 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11616 if (Parser.getTok().isNot(AsmToken::Hash) &&
11617 Parser.getTok().isNot(AsmToken::Dollar))
11618 return Error(Parser.getTok().getLoc(), "'#' expected");
11619 Parser.Lex(); // skip hash token.
11620
11621 const MCExpr *OffsetExpr;
11622 SMLoc ExLoc = Parser.getTok().getLoc();
11623 SMLoc EndLoc;
11624 if (getParser().parseExpression(OffsetExpr, EndLoc))
11625 return Error(ExLoc, "malformed setfp offset");
11626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11627 if (check(!CE, ExLoc, "setfp offset must be an immediate"))
11628 return true;
11629 Offset = CE->getValue();
11630 }
11631
11632 if (Parser.parseToken(AsmToken::EndOfStatement))
11633 return true;
11634
11635 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
11636 static_cast<unsigned>(SPReg), Offset);
11637 return false;
11638}
11639
11640/// parseDirective
11641/// ::= .pad offset
11642bool ARMAsmParser::parseDirectivePad(SMLoc L) {
11643 MCAsmParser &Parser = getParser();
11644 // Check the ordering of unwind directives
11645 if (!UC.hasFnStart())
11646 return Error(L, ".fnstart must precede .pad directive");
11647 if (UC.hasHandlerData())
11648 return Error(L, ".pad must precede .handlerdata directive");
11649
11650 // Parse the offset
11651 if (Parser.getTok().isNot(AsmToken::Hash) &&
11652 Parser.getTok().isNot(AsmToken::Dollar))
11653 return Error(Parser.getTok().getLoc(), "'#' expected");
11654 Parser.Lex(); // skip hash token.
11655
11656 const MCExpr *OffsetExpr;
11657 SMLoc ExLoc = Parser.getTok().getLoc();
11658 SMLoc EndLoc;
11659 if (getParser().parseExpression(OffsetExpr, EndLoc))
11660 return Error(ExLoc, "malformed pad offset");
11661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11662 if (!CE)
11663 return Error(ExLoc, "pad offset must be an immediate");
11664
11665 if (parseToken(AsmToken::EndOfStatement,
11666 "unexpected token in '.pad' directive"))
11667 return true;
11668
11669 getTargetStreamer().emitPad(CE->getValue());
11670 return false;
11671}
11672
11673/// parseDirectiveRegSave
11674/// ::= .save { registers }
11675/// ::= .vsave { registers }
11676bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11677 // Check the ordering of unwind directives
11678 if (!UC.hasFnStart())
11679 return Error(L, ".fnstart must precede .save or .vsave directives");
11680 if (UC.hasHandlerData())
11681 return Error(L, ".save or .vsave must precede .handlerdata directive");
11682
11683 // RAII object to make sure parsed operands are deleted.
11684 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
11685
11686 // Parse the register list
11687 if (parseRegisterList(Operands, true, true) ||
11688 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11689 return true;
11690 ARMOperand &Op = (ARMOperand &)*Operands[0];
11691 if (!IsVector && !Op.isRegList())
11692 return Error(L, ".save expects GPR registers");
11693 if (IsVector && !Op.isDPRRegList())
11694 return Error(L, ".vsave expects DPR registers");
11695
11696 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
11697 return false;
11698}
11699
11700/// parseDirectiveInst
11701/// ::= .inst opcode [, ...]
11702/// ::= .inst.n opcode [, ...]
11703/// ::= .inst.w opcode [, ...]
11704bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
11705 int Width = 4;
11706
11707 if (isThumb()) {
11708 switch (Suffix) {
11709 case 'n':
11710 Width = 2;
11711 break;
11712 case 'w':
11713 break;
11714 default:
11715 Width = 0;
11716 break;
11717 }
11718 } else {
11719 if (Suffix)
11720 return Error(Loc, "width suffixes are invalid in ARM mode");
11721 }
11722
11723 auto parseOne = [&]() -> bool {
11724 const MCExpr *Expr;
11725 if (getParser().parseExpression(Expr))
11726 return true;
11727 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
11728 if (!Value) {
11729 return Error(Loc, "expected constant expression");
11730 }
11731
11732 char CurSuffix = Suffix;
11733 switch (Width) {
11734 case 2:
11735 if (Value->getValue() > 0xffff)
11736 return Error(Loc, "inst.n operand is too big, use inst.w instead");
11737 break;
11738 case 4:
11739 if (Value->getValue() > 0xffffffff)
11740 return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
11741 " operand is too big");
11742 break;
11743 case 0:
11744 // Thumb mode, no width indicated. Guess from the opcode, if possible.
11745 if (Value->getValue() < 0xe800)
11746 CurSuffix = 'n';
11747 else if (Value->getValue() >= 0xe8000000)
11748 CurSuffix = 'w';
11749 else
11750 return Error(Loc, "cannot determine Thumb instruction size, "
11751 "use inst.n/inst.w instead");
11752 break;
11753 default:
11754 llvm_unreachable("only supported widths are 2 and 4")::llvm::llvm_unreachable_internal("only supported widths are 2 and 4"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 11754)
;
11755 }
11756
11757 getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
11758 return false;
11759 };
11760
11761 if (parseOptionalToken(AsmToken::EndOfStatement))
11762 return Error(Loc, "expected expression following directive");
11763 if (parseMany(parseOne))
11764 return true;
11765 return false;
11766}
11767
11768/// parseDirectiveLtorg
11769/// ::= .ltorg | .pool
11770bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
11771 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11772 return true;
11773 getTargetStreamer().emitCurrentConstantPool();
11774 return false;
11775}
11776
11777bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
11778 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11779
11780 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11781 return true;
11782
11783 if (!Section) {
11784 getStreamer().initSections(false, getSTI());
11785 Section = getStreamer().getCurrentSectionOnly();
11786 }
11787
11788 assert(Section && "must have section to emit alignment")(static_cast <bool> (Section && "must have section to emit alignment"
) ? void (0) : __assert_fail ("Section && \"must have section to emit alignment\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 11788, __extension__
__PRETTY_FUNCTION__))
;
11789 if (Section->useCodeAlign())
11790 getStreamer().emitCodeAlignment(2, &getSTI());
11791 else
11792 getStreamer().emitValueToAlignment(2);
11793
11794 return false;
11795}
11796
11797/// parseDirectivePersonalityIndex
11798/// ::= .personalityindex index
11799bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
11800 MCAsmParser &Parser = getParser();
11801 bool HasExistingPersonality = UC.hasPersonality();
11802
11803 const MCExpr *IndexExpression;
11804 SMLoc IndexLoc = Parser.getTok().getLoc();
11805 if (Parser.parseExpression(IndexExpression) ||
11806 parseToken(AsmToken::EndOfStatement,
11807 "unexpected token in '.personalityindex' directive")) {
11808 return true;
11809 }
11810
11811 UC.recordPersonalityIndex(L);
11812
11813 if (!UC.hasFnStart()) {
11814 return Error(L, ".fnstart must precede .personalityindex directive");
11815 }
11816 if (UC.cantUnwind()) {
11817 Error(L, ".personalityindex cannot be used with .cantunwind");
11818 UC.emitCantUnwindLocNotes();
11819 return true;
11820 }
11821 if (UC.hasHandlerData()) {
11822 Error(L, ".personalityindex must precede .handlerdata directive");
11823 UC.emitHandlerDataLocNotes();
11824 return true;
11825 }
11826 if (HasExistingPersonality) {
11827 Error(L, "multiple personality directives");
11828 UC.emitPersonalityLocNotes();
11829 return true;
11830 }
11831
11832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
11833 if (!CE)
11834 return Error(IndexLoc, "index must be a constant number");
11835 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
11836 return Error(IndexLoc,
11837 "personality routine index should be in range [0-3]");
11838
11839 getTargetStreamer().emitPersonalityIndex(CE->getValue());
11840 return false;
11841}
11842
11843/// parseDirectiveUnwindRaw
11844/// ::= .unwind_raw offset, opcode [, opcode...]
11845bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
11846 MCAsmParser &Parser = getParser();
11847 int64_t StackOffset;
11848 const MCExpr *OffsetExpr;
11849 SMLoc OffsetLoc = getLexer().getLoc();
11850
11851 if (!UC.hasFnStart())
11852 return Error(L, ".fnstart must precede .unwind_raw directives");
11853 if (getParser().parseExpression(OffsetExpr))
11854 return Error(OffsetLoc, "expected expression");
11855
11856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11857 if (!CE)
11858 return Error(OffsetLoc, "offset must be a constant");
11859
11860 StackOffset = CE->getValue();
11861
11862 if (Parser.parseToken(AsmToken::Comma, "expected comma"))
11863 return true;
11864
11865 SmallVector<uint8_t, 16> Opcodes;
11866
11867 auto parseOne = [&]() -> bool {
11868 const MCExpr *OE = nullptr;
11869 SMLoc OpcodeLoc = getLexer().getLoc();
11870 if (check(getLexer().is(AsmToken::EndOfStatement) ||
11871 Parser.parseExpression(OE),
11872 OpcodeLoc, "expected opcode expression"))
11873 return true;
11874 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
11875 if (!OC)
11876 return Error(OpcodeLoc, "opcode value must be a constant");
11877 const int64_t Opcode = OC->getValue();
11878 if (Opcode & ~0xff)
11879 return Error(OpcodeLoc, "invalid opcode");
11880 Opcodes.push_back(uint8_t(Opcode));
11881 return false;
11882 };
11883
11884 // Must have at least 1 element
11885 SMLoc OpcodeLoc = getLexer().getLoc();
11886 if (parseOptionalToken(AsmToken::EndOfStatement))
11887 return Error(OpcodeLoc, "expected opcode expression");
11888 if (parseMany(parseOne))
11889 return true;
11890
11891 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
11892 return false;
11893}
11894
11895/// parseDirectiveTLSDescSeq
11896/// ::= .tlsdescseq tls-variable
11897bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
11898 MCAsmParser &Parser = getParser();
11899
11900 if (getLexer().isNot(AsmToken::Identifier))
11901 return TokError("expected variable after '.tlsdescseq' directive");
11902
11903 const MCSymbolRefExpr *SRE =
11904 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
11905 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
11906 Lex();
11907
11908 if (parseToken(AsmToken::EndOfStatement,
11909 "unexpected token in '.tlsdescseq' directive"))
11910 return true;
11911
11912 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
11913 return false;
11914}
11915
11916/// parseDirectiveMovSP
11917/// ::= .movsp reg [, #offset]
11918bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
11919 MCAsmParser &Parser = getParser();
11920 if (!UC.hasFnStart())
11921 return Error(L, ".fnstart must precede .movsp directives");
11922 if (UC.getFPReg() != ARM::SP)
11923 return Error(L, "unexpected .movsp directive");
11924
11925 SMLoc SPRegLoc = Parser.getTok().getLoc();
11926 int SPReg = tryParseRegister();
11927 if (SPReg == -1)
11928 return Error(SPRegLoc, "register expected");
11929 if (SPReg == ARM::SP || SPReg == ARM::PC)
11930 return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
11931
11932 int64_t Offset = 0;
11933 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11934 if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
11935 return true;
11936
11937 const MCExpr *OffsetExpr;
11938 SMLoc OffsetLoc = Parser.getTok().getLoc();
11939
11940 if (Parser.parseExpression(OffsetExpr))
11941 return Error(OffsetLoc, "malformed offset expression");
11942
11943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11944 if (!CE)
11945 return Error(OffsetLoc, "offset must be an immediate constant");
11946
11947 Offset = CE->getValue();
11948 }
11949
11950 if (parseToken(AsmToken::EndOfStatement,
11951 "unexpected token in '.movsp' directive"))
11952 return true;
11953
11954 getTargetStreamer().emitMovSP(SPReg, Offset);
11955 UC.saveFPReg(SPReg);
11956
11957 return false;
11958}
11959
11960/// parseDirectiveObjectArch
11961/// ::= .object_arch name
11962bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
11963 MCAsmParser &Parser = getParser();
11964 if (getLexer().isNot(AsmToken::Identifier))
11965 return Error(getLexer().getLoc(), "unexpected token");
11966
11967 StringRef Arch = Parser.getTok().getString();
11968 SMLoc ArchLoc = Parser.getTok().getLoc();
11969 Lex();
11970
11971 ARM::ArchKind ID = ARM::parseArch(Arch);
11972
11973 if (ID == ARM::ArchKind::INVALID)
11974 return Error(ArchLoc, "unknown architecture '" + Arch + "'");
11975 if (parseToken(AsmToken::EndOfStatement))
11976 return true;
11977
11978 getTargetStreamer().emitObjectArch(ID);
11979 return false;
11980}
11981
11982/// parseDirectiveAlign
11983/// ::= .align
11984bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
11985 // NOTE: if this is not the end of the statement, fall back to the target
11986 // agnostic handling for this directive which will correctly handle this.
11987 if (parseOptionalToken(AsmToken::EndOfStatement)) {
11988 // '.align' is target specifically handled to mean 2**2 byte alignment.
11989 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11990 assert(Section && "must have section to emit alignment")(static_cast <bool> (Section && "must have section to emit alignment"
) ? void (0) : __assert_fail ("Section && \"must have section to emit alignment\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 11990, __extension__
__PRETTY_FUNCTION__))
;
11991 if (Section->useCodeAlign())
11992 getStreamer().emitCodeAlignment(4, &getSTI(), 0);
11993 else
11994 getStreamer().emitValueToAlignment(4, 0, 1, 0);
11995 return false;
11996 }
11997 return true;
11998}
11999
12000/// parseDirectiveThumbSet
12001/// ::= .thumb_set name, value
12002bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
12003 MCAsmParser &Parser = getParser();
12004
12005 StringRef Name;
12006 if (check(Parser.parseIdentifier(Name),
12007 "expected identifier after '.thumb_set'") ||
12008 parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
12009 return true;
12010
12011 MCSymbol *Sym;
12012 const MCExpr *Value;
12013 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
12014 Parser, Sym, Value))
12015 return true;
12016
12017 getTargetStreamer().emitThumbSet(Sym, Value);
12018 return false;
12019}
12020
12021/// Force static initialization.
12022extern "C" LLVM_EXTERNAL_VISIBILITY__attribute__((visibility("default"))) void LLVMInitializeARMAsmParser() {
12023 RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
12024 RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
12025 RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
12026 RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
12027}
12028
12029#define GET_REGISTER_MATCHER
12030#define GET_SUBTARGET_FEATURE_NAME
12031#define GET_MATCHER_IMPLEMENTATION
12032#define GET_MNEMONIC_SPELL_CHECKER
12033#include "ARMGenAsmMatcher.inc"
12034
12035// Some diagnostics need to vary with subtarget features, so they are handled
12036// here. For example, the DPR class has either 16 or 32 registers, depending
12037// on the FPU available.
12038const char *
12039ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
12040 switch (MatchError) {
12041 // rGPR contains sp starting with ARMv8.
12042 case Match_rGPR:
12043 return hasV8Ops() ? "operand must be a register in range [r0, r14]"
12044 : "operand must be a register in range [r0, r12] or r14";
12045 // DPR contains 16 registers for some FPUs, and 32 for others.
12046 case Match_DPR:
12047 return hasD32() ? "operand must be a register in range [d0, d31]"
12048 : "operand must be a register in range [d0, d15]";
12049 case Match_DPR_RegList:
12050 return hasD32() ? "operand must be a list of registers in range [d0, d31]"
12051 : "operand must be a list of registers in range [d0, d15]";
12052
12053 // For all other diags, use the static string from tablegen.
12054 default:
12055 return getMatchKindDiag(MatchError);
12056 }
12057}
12058
12059// Process the list of near-misses, throwing away ones we don't want to report
12060// to the user, and converting the rest to a source location and string that
12061// should be reported.
12062void
12063ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
12064 SmallVectorImpl<NearMissMessage> &NearMissesOut,
12065 SMLoc IDLoc, OperandVector &Operands) {
12066 // TODO: If operand didn't match, sub in a dummy one and run target
12067 // predicate, so that we can avoid reporting near-misses that are invalid?
12068 // TODO: Many operand types dont have SuperClasses set, so we report
12069 // redundant ones.
12070 // TODO: Some operands are superclasses of registers (e.g.
12071 // MCK_RegShiftedImm), we don't have any way to represent that currently.
12072 // TODO: This is not all ARM-specific, can some of it be factored out?
12073
12074 // Record some information about near-misses that we have already seen, so
12075 // that we can avoid reporting redundant ones. For example, if there are
12076 // variants of an instruction that take 8- and 16-bit immediates, we want
12077 // to only report the widest one.
12078 std::multimap<unsigned, unsigned> OperandMissesSeen;
12079 SmallSet<FeatureBitset, 4> FeatureMissesSeen;
12080 bool ReportedTooFewOperands = false;
12081
12082 // Process the near-misses in reverse order, so that we see more general ones
12083 // first, and so can avoid emitting more specific ones.
12084 for (NearMissInfo &I : reverse(NearMissesIn)) {
12085 switch (I.getKind()) {
12086 case NearMissInfo::NearMissOperand: {
12087 SMLoc OperandLoc =
12088 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
12089 const char *OperandDiag =
12090 getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
12091
12092 // If we have already emitted a message for a superclass, don't also report
12093 // the sub-class. We consider all operand classes that we don't have a
12094 // specialised diagnostic for to be equal for the propose of this check,
12095 // so that we don't report the generic error multiple times on the same
12096 // operand.
12097 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
12098 auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
12099 if (std::any_of(PrevReports.first, PrevReports.second,
12100 [DupCheckMatchClass](
12101 const std::pair<unsigned, unsigned> Pair) {
12102 if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
12103 return Pair.second == DupCheckMatchClass;
12104 else
12105 return isSubclass((MatchClassKind)DupCheckMatchClass,
12106 (MatchClassKind)Pair.second);
12107 }))
12108 break;
12109 OperandMissesSeen.insert(
12110 std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
12111
12112 NearMissMessage Message;
12113 Message.Loc = OperandLoc;
12114 if (OperandDiag) {
12115 Message.Message = OperandDiag;
12116 } else if (I.getOperandClass() == InvalidMatchClass) {
12117 Message.Message = "too many operands for instruction";
12118 } else {
12119 Message.Message = "invalid operand for instruction";
12120 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
12121 dbgs() << "Missing diagnostic string for operand class "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
12122 << getMatchClassName((MatchClassKind)I.getOperandClass())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
12123 << I.getOperandClass() << ", error " << I.getOperandError()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
12124 << ", opcode " << MII.getName(I.getOpcode()) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("asm-parser")) { dbgs() << "Missing diagnostic string for operand class "
<< getMatchClassName((MatchClassKind)I.getOperandClass
()) << I.getOperandClass() << ", error " <<
I.getOperandError() << ", opcode " << MII.getName
(I.getOpcode()) << "\n"; } } while (false)
;
12125 }
12126 NearMissesOut.emplace_back(Message);
12127 break;
12128 }
12129 case NearMissInfo::NearMissFeature: {
12130 const FeatureBitset &MissingFeatures = I.getFeatures();
12131 // Don't report the same set of features twice.
12132 if (FeatureMissesSeen.count(MissingFeatures))
12133 break;
12134 FeatureMissesSeen.insert(MissingFeatures);
12135
12136 // Special case: don't report a feature set which includes arm-mode for
12137 // targets that don't have ARM mode.
12138 if (MissingFeatures.test(Feature_IsARMBit) && !hasARM())
12139 break;
12140 // Don't report any near-misses that both require switching instruction
12141 // set, and adding other subtarget features.
12142 if (isThumb() && MissingFeatures.test(Feature_IsARMBit) &&
12143 MissingFeatures.count() > 1)
12144 break;
12145 if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) &&
12146 MissingFeatures.count() > 1)
12147 break;
12148 if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) &&
12149 (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit,
12150 Feature_IsThumbBit})).any())
12151 break;
12152 if (isMClass() && MissingFeatures.test(Feature_HasNEONBit))
12153 break;
12154
12155 NearMissMessage Message;
12156 Message.Loc = IDLoc;
12157 raw_svector_ostream OS(Message.Message);
12158
12159 OS << "instruction requires:";
12160 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
12161 if (MissingFeatures.test(i))
12162 OS << ' ' << getSubtargetFeatureName(i);
12163
12164 NearMissesOut.emplace_back(Message);
12165
12166 break;
12167 }
12168 case NearMissInfo::NearMissPredicate: {
12169 NearMissMessage Message;
12170 Message.Loc = IDLoc;
12171 switch (I.getPredicateError()) {
12172 case Match_RequiresNotITBlock:
12173 Message.Message = "flag setting instruction only valid outside IT block";
12174 break;
12175 case Match_RequiresITBlock:
12176 Message.Message = "instruction only valid inside IT block";
12177 break;
12178 case Match_RequiresV6:
12179 Message.Message = "instruction variant requires ARMv6 or later";
12180 break;
12181 case Match_RequiresThumb2:
12182 Message.Message = "instruction variant requires Thumb2";
12183 break;
12184 case Match_RequiresV8:
12185 Message.Message = "instruction variant requires ARMv8 or later";
12186 break;
12187 case Match_RequiresFlagSetting:
12188 Message.Message = "no flag-preserving variant of this instruction available";
12189 break;
12190 case Match_InvalidOperand:
12191 Message.Message = "invalid operand for instruction";
12192 break;
12193 default:
12194 llvm_unreachable("Unhandled target predicate error")::llvm::llvm_unreachable_internal("Unhandled target predicate error"
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 12194)
;
12195 break;
12196 }
12197 NearMissesOut.emplace_back(Message);
12198 break;
12199 }
12200 case NearMissInfo::NearMissTooFewOperands: {
12201 if (!ReportedTooFewOperands) {
12202 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
12203 NearMissesOut.emplace_back(NearMissMessage{
12204 EndLoc, StringRef("too few operands for instruction")});
12205 ReportedTooFewOperands = true;
12206 }
12207 break;
12208 }
12209 case NearMissInfo::NoNearMiss:
12210 // This should never leave the matcher.
12211 llvm_unreachable("not a near-miss")::llvm::llvm_unreachable_internal("not a near-miss", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp"
, 12211)
;
12212 break;
12213 }
12214 }
12215}
12216
12217void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
12218 SMLoc IDLoc, OperandVector &Operands) {
12219 SmallVector<NearMissMessage, 4> Messages;
12220 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
12221
12222 if (Messages.size() == 0) {
12223 // No near-misses were found, so the best we can do is "invalid
12224 // instruction".
12225 Error(IDLoc, "invalid instruction");
12226 } else if (Messages.size() == 1) {
12227 // One near miss was found, report it as the sole error.
12228 Error(Messages[0].Loc, Messages[0].Message);
12229 } else {
12230 // More than one near miss, so report a generic "invalid instruction"
12231 // error, followed by notes for each of the near-misses.
12232 Error(IDLoc, "invalid instruction, any one of the following would fix this:");
12233 for (auto &M : Messages) {
12234 Note(M.Loc, M.Message);
12235 }
12236 }
12237}
12238
12239bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) {
12240 // FIXME: This structure should be moved inside ARMTargetParser
12241 // when we start to table-generate them, and we can use the ARM
12242 // flags below, that were generated by table-gen.
12243 static const struct {
12244 const uint64_t Kind;
12245 const FeatureBitset ArchCheck;
12246 const FeatureBitset Features;
12247 } Extensions[] = {
12248 {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}},
12249 {ARM::AEK_AES,
12250 {Feature_HasV8Bit},
12251 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12252 {ARM::AEK_SHA2,
12253 {Feature_HasV8Bit},
12254 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12255 {ARM::AEK_CRYPTO,
12256 {Feature_HasV8Bit},
12257 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12258 {ARM::AEK_FP,
12259 {Feature_HasV8Bit},
12260 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},
12261 {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
12262 {Feature_HasV7Bit, Feature_IsNotMClassBit},
12263 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}},
12264 {ARM::AEK_MP,
12265 {Feature_HasV7Bit, Feature_IsNotMClassBit},
12266 {ARM::FeatureMP}},
12267 {ARM::AEK_SIMD,
12268 {Feature_HasV8Bit},
12269 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},
12270 {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}},
12271 // FIXME: Only available in A-class, isel not predicated
12272 {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}},
12273 {ARM::AEK_FP16,
12274 {Feature_HasV8_2aBit},
12275 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}},
12276 {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}},
12277 {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}},
12278 {ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI}},
12279 // FIXME: Unsupported extensions.
12280 {ARM::AEK_OS, {}, {}},
12281 {ARM::AEK_IWMMXT, {}, {}},
12282 {ARM::AEK_IWMMXT2, {}, {}},
12283 {ARM::AEK_MAVERICK, {}, {}},
12284 {ARM::AEK_XSCALE, {}, {}},
12285 };
12286 bool EnableFeature = true;
12287 if (Name.startswith_insensitive("no")) {
12288 EnableFeature = false;
12289 Name = Name.substr(2);
12290 }
12291 uint64_t FeatureKind = ARM::parseArchExt(Name);
12292 if (FeatureKind == ARM::AEK_INVALID)
12293 return Error(ExtLoc, "unknown architectural extension: " + Name);
12294
12295 for (const auto &Extension : Extensions) {
12296 if (Extension.Kind != FeatureKind)
12297 continue;
12298
12299 if (Extension.Features.none())
12300 return Error(ExtLoc, "unsupported architectural extension: " + Name);
12301
12302 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
12303 return Error(ExtLoc, "architectural extension '" + Name +
12304 "' is not "
12305 "allowed for the current base architecture");
12306
12307 MCSubtargetInfo &STI = copySTI();
12308 if (EnableFeature) {
12309 STI.SetFeatureBitsTransitively(Extension.Features);
12310 } else {
12311 STI.ClearFeatureBitsTransitively(Extension.Features);
12312 }
12313 FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
12314 setAvailableFeatures(Features);
12315 return true;
12316 }
12317 return false;
12318}
12319
12320/// parseDirectiveArchExtension
12321/// ::= .arch_extension [no]feature
12322bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
12323
12324 MCAsmParser &Parser = getParser();
12325
12326 if (getLexer().isNot(AsmToken::Identifier))
12327 return Error(getLexer().getLoc(), "expected architecture extension name");
12328
12329 StringRef Name = Parser.getTok().getString();
12330 SMLoc ExtLoc = Parser.getTok().getLoc();
12331 Lex();
12332
12333 if (parseToken(AsmToken::EndOfStatement,
12334 "unexpected token in '.arch_extension' directive"))
12335 return true;
12336
12337 if (Name == "nocrypto") {
12338 enableArchExtFeature("nosha2", ExtLoc);
12339 enableArchExtFeature("noaes", ExtLoc);
12340 }
12341
12342 if (enableArchExtFeature(Name, ExtLoc))
12343 return false;
12344
12345 return Error(ExtLoc, "unknown architectural extension: " + Name);
12346}
12347
12348// Define this matcher function after the auto-generated include so we
12349// have the match class enum definitions.
12350unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
12351 unsigned Kind) {
12352 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
12353 // If the kind is a token for a literal immediate, check if our asm
12354 // operand matches. This is for InstAliases which have a fixed-value
12355 // immediate in the syntax.
12356 switch (Kind) {
12357 default: break;
12358 case MCK__HASH_0:
12359 if (Op.isImm())
12360 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12361 if (CE->getValue() == 0)
12362 return Match_Success;
12363 break;
12364 case MCK__HASH_8:
12365 if (Op.isImm())
12366 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12367 if (CE->getValue() == 8)
12368 return Match_Success;
12369 break;
12370 case MCK__HASH_16:
12371 if (Op.isImm())
12372 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12373 if (CE->getValue() == 16)
12374 return Match_Success;
12375 break;
12376 case MCK_ModImm:
12377 if (Op.isImm()) {
12378 const MCExpr *SOExpr = Op.getImm();
12379 int64_t Value;
12380 if (!SOExpr->evaluateAsAbsolute(Value))
12381 return Match_Success;
12382 assert((Value >= std::numeric_limits<int32_t>::min() &&(static_cast <bool> ((Value >= std::numeric_limits<
int32_t>::min() && Value <= std::numeric_limits
<uint32_t>::max()) && "expression value must be representable in 32 bits"
) ? void (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 12384, __extension__
__PRETTY_FUNCTION__))
12383 Value <= std::numeric_limits<uint32_t>::max()) &&(static_cast <bool> ((Value >= std::numeric_limits<
int32_t>::min() && Value <= std::numeric_limits
<uint32_t>::max()) && "expression value must be representable in 32 bits"
) ? void (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 12384, __extension__
__PRETTY_FUNCTION__))
12384 "expression value must be representable in 32 bits")(static_cast <bool> ((Value >= std::numeric_limits<
int32_t>::min() && Value <= std::numeric_limits
<uint32_t>::max()) && "expression value must be representable in 32 bits"
) ? void (0) : __assert_fail ("(Value >= std::numeric_limits<int32_t>::min() && Value <= std::numeric_limits<uint32_t>::max()) && \"expression value must be representable in 32 bits\""
, "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 12384, __extension__
__PRETTY_FUNCTION__))
;
12385 }
12386 break;
12387 case MCK_rGPR:
12388 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
12389 return Match_Success;
12390 return Match_rGPR;
12391 case MCK_GPRPair:
12392 if (Op.isReg() &&
12393 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
12394 return Match_Success;
12395 break;
12396 }
12397 return Match_InvalidOperand;
12398}
12399
12400bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
12401 StringRef ExtraToken) {
12402 if (!hasMVE())
12403 return false;
12404
12405 return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
12406 Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
12407 Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
12408 Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
12409 Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
12410 Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
12411 Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
12412 Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
12413 Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
12414 Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
12415 Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
12416 Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
12417 Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
12418 Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
12419 Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
12420 Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
12421 Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
12422 Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
12423 Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
12424 Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
12425 Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
12426 Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
12427 Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
12428 Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
12429 Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
12430 Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
12431 Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
12432 Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
12433 Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
12434 Mnemonic.startswith("vqabs") ||
12435 (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
12436 Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
12437 Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
12438 Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
12439 Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
12440 Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
12441 Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
12442 Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
12443 Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
12444 Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
12445 Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
12446 Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
12447 Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
12448 Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
12449 Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
12450 Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
12451 Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
12452 Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
12453 Mnemonic.startswith("vldrb") ||
12454 (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
12455 (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
12456 Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
12457 Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
12458 Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
12459 Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
12460 Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
12461 Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
12462 Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
12463 Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
12464 Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
12465 Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
12466 Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
12467 Mnemonic.startswith("vcvt") ||
12468 MS.isVPTPredicableCDEInstr(Mnemonic) ||
12469 (Mnemonic.startswith("vmov") &&
12470 !(ExtraToken == ".f16" || ExtraToken == ".32" ||
12471 ExtraToken == ".16" || ExtraToken == ".8"));
12472}