| File: | build/source/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp |
| Warning: | line 11957, column 14 Called C++ object pointer is null |
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| 1 | //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | |
| 9 | #include "ARMBaseInstrInfo.h" |
| 10 | #include "ARMFeatures.h" |
| 11 | #include "MCTargetDesc/ARMAddressingModes.h" |
| 12 | #include "MCTargetDesc/ARMBaseInfo.h" |
| 13 | #include "MCTargetDesc/ARMInstPrinter.h" |
| 14 | #include "MCTargetDesc/ARMMCExpr.h" |
| 15 | #include "MCTargetDesc/ARMMCTargetDesc.h" |
| 16 | #include "TargetInfo/ARMTargetInfo.h" |
| 17 | #include "Utils/ARMBaseInfo.h" |
| 18 | #include "llvm/ADT/APFloat.h" |
| 19 | #include "llvm/ADT/APInt.h" |
| 20 | #include "llvm/ADT/STLExtras.h" |
| 21 | #include "llvm/ADT/SmallSet.h" |
| 22 | #include "llvm/ADT/SmallVector.h" |
| 23 | #include "llvm/ADT/StringMap.h" |
| 24 | #include "llvm/ADT/StringRef.h" |
| 25 | #include "llvm/ADT/StringSet.h" |
| 26 | #include "llvm/ADT/StringSwitch.h" |
| 27 | #include "llvm/ADT/Twine.h" |
| 28 | #include "llvm/MC/MCContext.h" |
| 29 | #include "llvm/MC/MCExpr.h" |
| 30 | #include "llvm/MC/MCInst.h" |
| 31 | #include "llvm/MC/MCInstrDesc.h" |
| 32 | #include "llvm/MC/MCInstrInfo.h" |
| 33 | #include "llvm/MC/MCParser/MCAsmLexer.h" |
| 34 | #include "llvm/MC/MCParser/MCAsmParser.h" |
| 35 | #include "llvm/MC/MCParser/MCAsmParserExtension.h" |
| 36 | #include "llvm/MC/MCParser/MCAsmParserUtils.h" |
| 37 | #include "llvm/MC/MCParser/MCParsedAsmOperand.h" |
| 38 | #include "llvm/MC/MCParser/MCTargetAsmParser.h" |
| 39 | #include "llvm/MC/MCRegisterInfo.h" |
| 40 | #include "llvm/MC/MCSection.h" |
| 41 | #include "llvm/MC/MCStreamer.h" |
| 42 | #include "llvm/MC/MCSubtargetInfo.h" |
| 43 | #include "llvm/MC/MCSymbol.h" |
| 44 | #include "llvm/MC/SubtargetFeature.h" |
| 45 | #include "llvm/MC/TargetRegistry.h" |
| 46 | #include "llvm/Support/ARMBuildAttributes.h" |
| 47 | #include "llvm/Support/ARMEHABI.h" |
| 48 | #include "llvm/Support/Casting.h" |
| 49 | #include "llvm/Support/CommandLine.h" |
| 50 | #include "llvm/Support/Compiler.h" |
| 51 | #include "llvm/Support/ErrorHandling.h" |
| 52 | #include "llvm/Support/MathExtras.h" |
| 53 | #include "llvm/Support/SMLoc.h" |
| 54 | #include "llvm/Support/raw_ostream.h" |
| 55 | #include "llvm/TargetParser/TargetParser.h" |
| 56 | #include "llvm/TargetParser/Triple.h" |
| 57 | #include <algorithm> |
| 58 | #include <cassert> |
| 59 | #include <cstddef> |
| 60 | #include <cstdint> |
| 61 | #include <iterator> |
| 62 | #include <limits> |
| 63 | #include <memory> |
| 64 | #include <string> |
| 65 | #include <utility> |
| 66 | #include <vector> |
| 67 | |
| 68 | #define DEBUG_TYPE"asm-parser" "asm-parser" |
| 69 | |
| 70 | using namespace llvm; |
| 71 | |
| 72 | namespace llvm { |
| 73 | struct ARMInstrTable { |
| 74 | MCInstrDesc Insts[4445]; |
| 75 | MCOperandInfo OperandInfo[3026]; |
| 76 | MCPhysReg ImplicitOps[130]; |
| 77 | }; |
| 78 | extern const ARMInstrTable ARMDescs; |
| 79 | } // end namespace llvm |
| 80 | |
| 81 | namespace { |
| 82 | |
| 83 | enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly }; |
| 84 | |
| 85 | static cl::opt<ImplicitItModeTy> ImplicitItMode( |
| 86 | "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), |
| 87 | cl::desc("Allow conditional instructions outdside of an IT block"), |
| 88 | cl::values(clEnumValN(ImplicitItModeTy::Always, "always",llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always ), "Accept in both ISAs, emit implicit ITs in Thumb" } |
| 89 | "Accept in both ISAs, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "always", int(ImplicitItModeTy::Always ), "Accept in both ISAs, emit implicit ITs in Thumb" }, |
| 90 | clEnumValN(ImplicitItModeTy::Never, "never",llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never ), "Warn in ARM, reject in Thumb" } |
| 91 | "Warn in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "never", int(ImplicitItModeTy::Never ), "Warn in ARM, reject in Thumb" }, |
| 92 | clEnumValN(ImplicitItModeTy::ARMOnly, "arm",llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly ), "Accept in ARM, reject in Thumb" } |
| 93 | "Accept in ARM, reject in Thumb")llvm::cl::OptionEnumValue { "arm", int(ImplicitItModeTy::ARMOnly ), "Accept in ARM, reject in Thumb" }, |
| 94 | clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly ), "Warn in ARM, emit implicit ITs in Thumb" } |
| 95 | "Warn in ARM, emit implicit ITs in Thumb")llvm::cl::OptionEnumValue { "thumb", int(ImplicitItModeTy::ThumbOnly ), "Warn in ARM, emit implicit ITs in Thumb" })); |
| 96 | |
| 97 | static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes", |
| 98 | cl::init(false)); |
| 99 | |
| 100 | enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; |
| 101 | |
| 102 | static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { |
| 103 | // Position==0 means we're not in an IT block at all. Position==1 |
| 104 | // means we want the first state bit, which is always 0 (Then). |
| 105 | // Position==2 means we want the second state bit, stored at bit 3 |
| 106 | // of Mask, and so on downwards. So (5 - Position) will shift the |
| 107 | // right bit down to bit 0, including the always-0 bit at bit 4 for |
| 108 | // the mandatory initial Then. |
| 109 | return (Mask >> (5 - Position) & 1); |
| 110 | } |
| 111 | |
| 112 | class UnwindContext { |
| 113 | using Locs = SmallVector<SMLoc, 4>; |
| 114 | |
| 115 | MCAsmParser &Parser; |
| 116 | Locs FnStartLocs; |
| 117 | Locs CantUnwindLocs; |
| 118 | Locs PersonalityLocs; |
| 119 | Locs PersonalityIndexLocs; |
| 120 | Locs HandlerDataLocs; |
| 121 | int FPReg; |
| 122 | |
| 123 | public: |
| 124 | UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} |
| 125 | |
| 126 | bool hasFnStart() const { return !FnStartLocs.empty(); } |
| 127 | bool cantUnwind() const { return !CantUnwindLocs.empty(); } |
| 128 | bool hasHandlerData() const { return !HandlerDataLocs.empty(); } |
| 129 | |
| 130 | bool hasPersonality() const { |
| 131 | return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); |
| 132 | } |
| 133 | |
| 134 | void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } |
| 135 | void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } |
| 136 | void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } |
| 137 | void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } |
| 138 | void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } |
| 139 | |
| 140 | void saveFPReg(int Reg) { FPReg = Reg; } |
| 141 | int getFPReg() const { return FPReg; } |
| 142 | |
| 143 | void emitFnStartLocNotes() const { |
| 144 | for (const SMLoc &Loc : FnStartLocs) |
| 145 | Parser.Note(Loc, ".fnstart was specified here"); |
| 146 | } |
| 147 | |
| 148 | void emitCantUnwindLocNotes() const { |
| 149 | for (const SMLoc &Loc : CantUnwindLocs) |
| 150 | Parser.Note(Loc, ".cantunwind was specified here"); |
| 151 | } |
| 152 | |
| 153 | void emitHandlerDataLocNotes() const { |
| 154 | for (const SMLoc &Loc : HandlerDataLocs) |
| 155 | Parser.Note(Loc, ".handlerdata was specified here"); |
| 156 | } |
| 157 | |
| 158 | void emitPersonalityLocNotes() const { |
| 159 | for (Locs::const_iterator PI = PersonalityLocs.begin(), |
| 160 | PE = PersonalityLocs.end(), |
| 161 | PII = PersonalityIndexLocs.begin(), |
| 162 | PIE = PersonalityIndexLocs.end(); |
| 163 | PI != PE || PII != PIE;) { |
| 164 | if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) |
| 165 | Parser.Note(*PI++, ".personality was specified here"); |
| 166 | else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) |
| 167 | Parser.Note(*PII++, ".personalityindex was specified here"); |
| 168 | else |
| 169 | llvm_unreachable(".personality and .personalityindex cannot be "::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be " "at the same location", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 170) |
| 170 | "at the same location")::llvm::llvm_unreachable_internal(".personality and .personalityindex cannot be " "at the same location", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 170); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | void reset() { |
| 175 | FnStartLocs = Locs(); |
| 176 | CantUnwindLocs = Locs(); |
| 177 | PersonalityLocs = Locs(); |
| 178 | HandlerDataLocs = Locs(); |
| 179 | PersonalityIndexLocs = Locs(); |
| 180 | FPReg = ARM::SP; |
| 181 | } |
| 182 | }; |
| 183 | |
| 184 | // Various sets of ARM instruction mnemonics which are used by the asm parser |
| 185 | class ARMMnemonicSets { |
| 186 | StringSet<> CDE; |
| 187 | StringSet<> CDEWithVPTSuffix; |
| 188 | public: |
| 189 | ARMMnemonicSets(const MCSubtargetInfo &STI); |
| 190 | |
| 191 | /// Returns true iff a given mnemonic is a CDE instruction |
| 192 | bool isCDEInstr(StringRef Mnemonic) { |
| 193 | // Quick check before searching the set |
| 194 | if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx")) |
| 195 | return false; |
| 196 | return CDE.count(Mnemonic); |
| 197 | } |
| 198 | |
| 199 | /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction |
| 200 | /// (possibly with a predication suffix "e" or "t") |
| 201 | bool isVPTPredicableCDEInstr(StringRef Mnemonic) { |
| 202 | if (!Mnemonic.startswith("vcx")) |
| 203 | return false; |
| 204 | return CDEWithVPTSuffix.count(Mnemonic); |
| 205 | } |
| 206 | |
| 207 | /// Returns true iff a given mnemonic is an IT-predicable CDE instruction |
| 208 | /// (possibly with a condition suffix) |
| 209 | bool isITPredicableCDEInstr(StringRef Mnemonic) { |
| 210 | if (!Mnemonic.startswith("cx")) |
| 211 | return false; |
| 212 | return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") || |
| 213 | Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") || |
| 214 | Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da"); |
| 215 | } |
| 216 | |
| 217 | /// Return true iff a given mnemonic is an integer CDE instruction with |
| 218 | /// dual-register destination |
| 219 | bool isCDEDualRegInstr(StringRef Mnemonic) { |
| 220 | if (!Mnemonic.startswith("cx")) |
| 221 | return false; |
| 222 | return Mnemonic == "cx1d" || Mnemonic == "cx1da" || |
| 223 | Mnemonic == "cx2d" || Mnemonic == "cx2da" || |
| 224 | Mnemonic == "cx3d" || Mnemonic == "cx3da"; |
| 225 | } |
| 226 | }; |
| 227 | |
| 228 | ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) { |
| 229 | for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da", |
| 230 | "cx2", "cx2a", "cx2d", "cx2da", |
| 231 | "cx3", "cx3a", "cx3d", "cx3da", }) |
| 232 | CDE.insert(Mnemonic); |
| 233 | for (StringRef Mnemonic : |
| 234 | {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) { |
| 235 | CDE.insert(Mnemonic); |
| 236 | CDEWithVPTSuffix.insert(Mnemonic); |
| 237 | CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t"); |
| 238 | CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e"); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | class ARMAsmParser : public MCTargetAsmParser { |
| 243 | const MCRegisterInfo *MRI; |
| 244 | UnwindContext UC; |
| 245 | ARMMnemonicSets MS; |
| 246 | |
| 247 | ARMTargetStreamer &getTargetStreamer() { |
| 248 | assert(getParser().getStreamer().getTargetStreamer() &&(static_cast <bool> (getParser().getStreamer().getTargetStreamer () && "do not have a target streamer") ? void (0) : __assert_fail ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 249, __extension__ __PRETTY_FUNCTION__)) |
| 249 | "do not have a target streamer")(static_cast <bool> (getParser().getStreamer().getTargetStreamer () && "do not have a target streamer") ? void (0) : __assert_fail ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 249, __extension__ __PRETTY_FUNCTION__)); |
| 250 | MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); |
| 251 | return static_cast<ARMTargetStreamer &>(TS); |
| 252 | } |
| 253 | |
| 254 | // Map of register aliases registers via the .req directive. |
| 255 | StringMap<unsigned> RegisterReqs; |
| 256 | |
| 257 | bool NextSymbolIsThumb; |
| 258 | |
| 259 | bool useImplicitITThumb() const { |
| 260 | return ImplicitItMode == ImplicitItModeTy::Always || |
| 261 | ImplicitItMode == ImplicitItModeTy::ThumbOnly; |
| 262 | } |
| 263 | |
| 264 | bool useImplicitITARM() const { |
| 265 | return ImplicitItMode == ImplicitItModeTy::Always || |
| 266 | ImplicitItMode == ImplicitItModeTy::ARMOnly; |
| 267 | } |
| 268 | |
| 269 | struct { |
| 270 | ARMCC::CondCodes Cond; // Condition for IT block. |
| 271 | unsigned Mask:4; // Condition mask for instructions. |
| 272 | // Starting at first 1 (from lsb). |
| 273 | // '1' condition as indicated in IT. |
| 274 | // '0' inverse of condition (else). |
| 275 | // Count of instructions in IT block is |
| 276 | // 4 - trailingzeroes(mask) |
| 277 | // Note that this does not have the same encoding |
| 278 | // as in the IT instruction, which also depends |
| 279 | // on the low bit of the condition code. |
| 280 | |
| 281 | unsigned CurPosition; // Current position in parsing of IT |
| 282 | // block. In range [0,4], with 0 being the IT |
| 283 | // instruction itself. Initialized according to |
| 284 | // count of instructions in block. ~0U if no |
| 285 | // active IT block. |
| 286 | |
| 287 | bool IsExplicit; // true - The IT instruction was present in the |
| 288 | // input, we should not modify it. |
| 289 | // false - The IT instruction was added |
| 290 | // implicitly, we can extend it if that |
| 291 | // would be legal. |
| 292 | } ITState; |
| 293 | |
| 294 | SmallVector<MCInst, 4> PendingConditionalInsts; |
| 295 | |
| 296 | void flushPendingInstructions(MCStreamer &Out) override { |
| 297 | if (!inImplicitITBlock()) { |
| 298 | assert(PendingConditionalInsts.size() == 0)(static_cast <bool> (PendingConditionalInsts.size() == 0 ) ? void (0) : __assert_fail ("PendingConditionalInsts.size() == 0" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 298, __extension__ __PRETTY_FUNCTION__)); |
| 299 | return; |
| 300 | } |
| 301 | |
| 302 | // Emit the IT instruction |
| 303 | MCInst ITInst; |
| 304 | ITInst.setOpcode(ARM::t2IT); |
| 305 | ITInst.addOperand(MCOperand::createImm(ITState.Cond)); |
| 306 | ITInst.addOperand(MCOperand::createImm(ITState.Mask)); |
| 307 | Out.emitInstruction(ITInst, getSTI()); |
| 308 | |
| 309 | // Emit the conditional instructions |
| 310 | assert(PendingConditionalInsts.size() <= 4)(static_cast <bool> (PendingConditionalInsts.size() <= 4) ? void (0) : __assert_fail ("PendingConditionalInsts.size() <= 4" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 310, __extension__ __PRETTY_FUNCTION__)); |
| 311 | for (const MCInst &Inst : PendingConditionalInsts) { |
| 312 | Out.emitInstruction(Inst, getSTI()); |
| 313 | } |
| 314 | PendingConditionalInsts.clear(); |
| 315 | |
| 316 | // Clear the IT state |
| 317 | ITState.Mask = 0; |
| 318 | ITState.CurPosition = ~0U; |
| 319 | } |
| 320 | |
| 321 | bool inITBlock() { return ITState.CurPosition != ~0U; } |
| 322 | bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; } |
| 323 | bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; } |
| 324 | |
| 325 | bool lastInITBlock() { |
| 326 | return ITState.CurPosition == 4 - (unsigned)llvm::countr_zero(ITState.Mask); |
| 327 | } |
| 328 | |
| 329 | void forwardITPosition() { |
| 330 | if (!inITBlock()) return; |
| 331 | // Move to the next instruction in the IT block, if there is one. If not, |
| 332 | // mark the block as done, except for implicit IT blocks, which we leave |
| 333 | // open until we find an instruction that can't be added to it. |
| 334 | unsigned TZ = llvm::countr_zero(ITState.Mask); |
| 335 | if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit) |
| 336 | ITState.CurPosition = ~0U; // Done with the IT block after this. |
| 337 | } |
| 338 | |
| 339 | // Rewind the state of the current IT block, removing the last slot from it. |
| 340 | void rewindImplicitITPosition() { |
| 341 | assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail ("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 341, __extension__ __PRETTY_FUNCTION__)); |
| 342 | assert(ITState.CurPosition > 1)(static_cast <bool> (ITState.CurPosition > 1) ? void (0) : __assert_fail ("ITState.CurPosition > 1", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 342, __extension__ __PRETTY_FUNCTION__)); |
| 343 | ITState.CurPosition--; |
| 344 | unsigned TZ = llvm::countr_zero(ITState.Mask); |
| 345 | unsigned NewMask = 0; |
| 346 | NewMask |= ITState.Mask & (0xC << TZ); |
| 347 | NewMask |= 0x2 << TZ; |
| 348 | ITState.Mask = NewMask; |
| 349 | } |
| 350 | |
| 351 | // Rewind the state of the current IT block, removing the last slot from it. |
| 352 | // If we were at the first slot, this closes the IT block. |
| 353 | void discardImplicitITBlock() { |
| 354 | assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail ("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 354, __extension__ __PRETTY_FUNCTION__)); |
| 355 | assert(ITState.CurPosition == 1)(static_cast <bool> (ITState.CurPosition == 1) ? void ( 0) : __assert_fail ("ITState.CurPosition == 1", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 355, __extension__ __PRETTY_FUNCTION__)); |
| 356 | ITState.CurPosition = ~0U; |
| 357 | } |
| 358 | |
| 359 | // Return the low-subreg of a given Q register. |
| 360 | unsigned getDRegFromQReg(unsigned QReg) const { |
| 361 | return MRI->getSubReg(QReg, ARM::dsub_0); |
| 362 | } |
| 363 | |
| 364 | // Get the condition code corresponding to the current IT block slot. |
| 365 | ARMCC::CondCodes currentITCond() { |
| 366 | unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition); |
| 367 | return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond; |
| 368 | } |
| 369 | |
| 370 | // Invert the condition of the current IT block slot without changing any |
| 371 | // other slots in the same block. |
| 372 | void invertCurrentITCondition() { |
| 373 | if (ITState.CurPosition == 1) { |
| 374 | ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond); |
| 375 | } else { |
| 376 | ITState.Mask ^= 1 << (5 - ITState.CurPosition); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | // Returns true if the current IT block is full (all 4 slots used). |
| 381 | bool isITBlockFull() { |
| 382 | return inITBlock() && (ITState.Mask & 1); |
| 383 | } |
| 384 | |
| 385 | // Extend the current implicit IT block to have one more slot with the given |
| 386 | // condition code. |
| 387 | void extendImplicitITBlock(ARMCC::CondCodes Cond) { |
| 388 | assert(inImplicitITBlock())(static_cast <bool> (inImplicitITBlock()) ? void (0) : __assert_fail ("inImplicitITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 388, __extension__ __PRETTY_FUNCTION__)); |
| 389 | assert(!isITBlockFull())(static_cast <bool> (!isITBlockFull()) ? void (0) : __assert_fail ("!isITBlockFull()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 389, __extension__ __PRETTY_FUNCTION__)); |
| 390 | assert(Cond == ITState.Cond ||(static_cast <bool> (Cond == ITState.Cond || Cond == ARMCC ::getOppositeCondition(ITState.Cond)) ? void (0) : __assert_fail ("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 391, __extension__ __PRETTY_FUNCTION__)) |
| 391 | Cond == ARMCC::getOppositeCondition(ITState.Cond))(static_cast <bool> (Cond == ITState.Cond || Cond == ARMCC ::getOppositeCondition(ITState.Cond)) ? void (0) : __assert_fail ("Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 391, __extension__ __PRETTY_FUNCTION__)); |
| 392 | unsigned TZ = llvm::countr_zero(ITState.Mask); |
| 393 | unsigned NewMask = 0; |
| 394 | // Keep any existing condition bits. |
| 395 | NewMask |= ITState.Mask & (0xE << TZ); |
| 396 | // Insert the new condition bit. |
| 397 | NewMask |= (Cond != ITState.Cond) << TZ; |
| 398 | // Move the trailing 1 down one bit. |
| 399 | NewMask |= 1 << (TZ - 1); |
| 400 | ITState.Mask = NewMask; |
| 401 | } |
| 402 | |
| 403 | // Create a new implicit IT block with a dummy condition code. |
| 404 | void startImplicitITBlock() { |
| 405 | assert(!inITBlock())(static_cast <bool> (!inITBlock()) ? void (0) : __assert_fail ("!inITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 405, __extension__ __PRETTY_FUNCTION__)); |
| 406 | ITState.Cond = ARMCC::AL; |
| 407 | ITState.Mask = 8; |
| 408 | ITState.CurPosition = 1; |
| 409 | ITState.IsExplicit = false; |
| 410 | } |
| 411 | |
| 412 | // Create a new explicit IT block with the given condition and mask. |
| 413 | // The mask should be in the format used in ARMOperand and |
| 414 | // MCOperand, with a 1 implying 'e', regardless of the low bit of |
| 415 | // the condition. |
| 416 | void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) { |
| 417 | assert(!inITBlock())(static_cast <bool> (!inITBlock()) ? void (0) : __assert_fail ("!inITBlock()", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 417, __extension__ __PRETTY_FUNCTION__)); |
| 418 | ITState.Cond = Cond; |
| 419 | ITState.Mask = Mask; |
| 420 | ITState.CurPosition = 0; |
| 421 | ITState.IsExplicit = true; |
| 422 | } |
| 423 | |
| 424 | struct { |
| 425 | unsigned Mask : 4; |
| 426 | unsigned CurPosition; |
| 427 | } VPTState; |
| 428 | bool inVPTBlock() { return VPTState.CurPosition != ~0U; } |
| 429 | void forwardVPTPosition() { |
| 430 | if (!inVPTBlock()) return; |
| 431 | unsigned TZ = llvm::countr_zero(VPTState.Mask); |
| 432 | if (++VPTState.CurPosition == 5 - TZ) |
| 433 | VPTState.CurPosition = ~0U; |
| 434 | } |
| 435 | |
| 436 | void Note(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) { |
| 437 | return getParser().Note(L, Msg, Range); |
| 438 | } |
| 439 | |
| 440 | bool Warning(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) { |
| 441 | return getParser().Warning(L, Msg, Range); |
| 442 | } |
| 443 | |
| 444 | bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) { |
| 445 | return getParser().Error(L, Msg, Range); |
| 446 | } |
| 447 | |
| 448 | bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, |
| 449 | unsigned ListNo, bool IsARPop = false); |
| 450 | bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, |
| 451 | unsigned ListNo); |
| 452 | |
| 453 | int tryParseRegister(); |
| 454 | bool tryParseRegisterWithWriteBack(OperandVector &); |
| 455 | int tryParseShiftRegister(OperandVector &); |
| 456 | bool parseRegisterList(OperandVector &, bool EnforceOrder = true, |
| 457 | bool AllowRAAC = false); |
| 458 | bool parseMemory(OperandVector &); |
| 459 | bool parseOperand(OperandVector &, StringRef Mnemonic); |
| 460 | bool parseImmExpr(int64_t &Out); |
| 461 | bool parsePrefix(ARMMCExpr::VariantKind &RefKind); |
| 462 | bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, |
| 463 | unsigned &ShiftAmount); |
| 464 | bool parseLiteralValues(unsigned Size, SMLoc L); |
| 465 | bool parseDirectiveThumb(SMLoc L); |
| 466 | bool parseDirectiveARM(SMLoc L); |
| 467 | bool parseDirectiveThumbFunc(SMLoc L); |
| 468 | bool parseDirectiveCode(SMLoc L); |
| 469 | bool parseDirectiveSyntax(SMLoc L); |
| 470 | bool parseDirectiveReq(StringRef Name, SMLoc L); |
| 471 | bool parseDirectiveUnreq(SMLoc L); |
| 472 | bool parseDirectiveArch(SMLoc L); |
| 473 | bool parseDirectiveEabiAttr(SMLoc L); |
| 474 | bool parseDirectiveCPU(SMLoc L); |
| 475 | bool parseDirectiveFPU(SMLoc L); |
| 476 | bool parseDirectiveFnStart(SMLoc L); |
| 477 | bool parseDirectiveFnEnd(SMLoc L); |
| 478 | bool parseDirectiveCantUnwind(SMLoc L); |
| 479 | bool parseDirectivePersonality(SMLoc L); |
| 480 | bool parseDirectiveHandlerData(SMLoc L); |
| 481 | bool parseDirectiveSetFP(SMLoc L); |
| 482 | bool parseDirectivePad(SMLoc L); |
| 483 | bool parseDirectiveRegSave(SMLoc L, bool IsVector); |
| 484 | bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); |
| 485 | bool parseDirectiveLtorg(SMLoc L); |
| 486 | bool parseDirectiveEven(SMLoc L); |
| 487 | bool parseDirectivePersonalityIndex(SMLoc L); |
| 488 | bool parseDirectiveUnwindRaw(SMLoc L); |
| 489 | bool parseDirectiveTLSDescSeq(SMLoc L); |
| 490 | bool parseDirectiveMovSP(SMLoc L); |
| 491 | bool parseDirectiveObjectArch(SMLoc L); |
| 492 | bool parseDirectiveArchExtension(SMLoc L); |
| 493 | bool parseDirectiveAlign(SMLoc L); |
| 494 | bool parseDirectiveThumbSet(SMLoc L); |
| 495 | |
| 496 | bool parseDirectiveSEHAllocStack(SMLoc L, bool Wide); |
| 497 | bool parseDirectiveSEHSaveRegs(SMLoc L, bool Wide); |
| 498 | bool parseDirectiveSEHSaveSP(SMLoc L); |
| 499 | bool parseDirectiveSEHSaveFRegs(SMLoc L); |
| 500 | bool parseDirectiveSEHSaveLR(SMLoc L); |
| 501 | bool parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment); |
| 502 | bool parseDirectiveSEHNop(SMLoc L, bool Wide); |
| 503 | bool parseDirectiveSEHEpilogStart(SMLoc L, bool Condition); |
| 504 | bool parseDirectiveSEHEpilogEnd(SMLoc L); |
| 505 | bool parseDirectiveSEHCustom(SMLoc L); |
| 506 | |
| 507 | bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken); |
| 508 | StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken, |
| 509 | unsigned &PredicationCode, |
| 510 | unsigned &VPTPredicationCode, bool &CarrySetting, |
| 511 | unsigned &ProcessorIMod, StringRef &ITMask); |
| 512 | void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken, |
| 513 | StringRef FullInst, bool &CanAcceptCarrySet, |
| 514 | bool &CanAcceptPredicationCode, |
| 515 | bool &CanAcceptVPTPredicationCode); |
| 516 | bool enableArchExtFeature(StringRef Name, SMLoc &ExtLoc); |
| 517 | |
| 518 | void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, |
| 519 | OperandVector &Operands); |
| 520 | bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands); |
| 521 | |
| 522 | bool isThumb() const { |
| 523 | // FIXME: Can tablegen auto-generate this? |
| 524 | return getSTI().hasFeature(ARM::ModeThumb); |
| 525 | } |
| 526 | |
| 527 | bool isThumbOne() const { |
| 528 | return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2); |
| 529 | } |
| 530 | |
| 531 | bool isThumbTwo() const { |
| 532 | return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2); |
| 533 | } |
| 534 | |
| 535 | bool hasThumb() const { |
| 536 | return getSTI().hasFeature(ARM::HasV4TOps); |
| 537 | } |
| 538 | |
| 539 | bool hasThumb2() const { |
| 540 | return getSTI().hasFeature(ARM::FeatureThumb2); |
| 541 | } |
| 542 | |
| 543 | bool hasV6Ops() const { |
| 544 | return getSTI().hasFeature(ARM::HasV6Ops); |
| 545 | } |
| 546 | |
| 547 | bool hasV6T2Ops() const { |
| 548 | return getSTI().hasFeature(ARM::HasV6T2Ops); |
| 549 | } |
| 550 | |
| 551 | bool hasV6MOps() const { |
| 552 | return getSTI().hasFeature(ARM::HasV6MOps); |
| 553 | } |
| 554 | |
| 555 | bool hasV7Ops() const { |
| 556 | return getSTI().hasFeature(ARM::HasV7Ops); |
| 557 | } |
| 558 | |
| 559 | bool hasV8Ops() const { |
| 560 | return getSTI().hasFeature(ARM::HasV8Ops); |
| 561 | } |
| 562 | |
| 563 | bool hasV8MBaseline() const { |
| 564 | return getSTI().hasFeature(ARM::HasV8MBaselineOps); |
| 565 | } |
| 566 | |
| 567 | bool hasV8MMainline() const { |
| 568 | return getSTI().hasFeature(ARM::HasV8MMainlineOps); |
| 569 | } |
| 570 | bool hasV8_1MMainline() const { |
| 571 | return getSTI().hasFeature(ARM::HasV8_1MMainlineOps); |
| 572 | } |
| 573 | bool hasMVE() const { |
| 574 | return getSTI().hasFeature(ARM::HasMVEIntegerOps); |
| 575 | } |
| 576 | bool hasMVEFloat() const { |
| 577 | return getSTI().hasFeature(ARM::HasMVEFloatOps); |
| 578 | } |
| 579 | bool hasCDE() const { |
| 580 | return getSTI().hasFeature(ARM::HasCDEOps); |
| 581 | } |
| 582 | bool has8MSecExt() const { |
| 583 | return getSTI().hasFeature(ARM::Feature8MSecExt); |
| 584 | } |
| 585 | |
| 586 | bool hasARM() const { |
| 587 | return !getSTI().hasFeature(ARM::FeatureNoARM); |
| 588 | } |
| 589 | |
| 590 | bool hasDSP() const { |
| 591 | return getSTI().hasFeature(ARM::FeatureDSP); |
| 592 | } |
| 593 | |
| 594 | bool hasD32() const { |
| 595 | return getSTI().hasFeature(ARM::FeatureD32); |
| 596 | } |
| 597 | |
| 598 | bool hasV8_1aOps() const { |
| 599 | return getSTI().hasFeature(ARM::HasV8_1aOps); |
| 600 | } |
| 601 | |
| 602 | bool hasRAS() const { |
| 603 | return getSTI().hasFeature(ARM::FeatureRAS); |
| 604 | } |
| 605 | |
| 606 | void SwitchMode() { |
| 607 | MCSubtargetInfo &STI = copySTI(); |
| 608 | auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); |
| 609 | setAvailableFeatures(FB); |
| 610 | } |
| 611 | |
| 612 | void FixModeAfterArchChange(bool WasThumb, SMLoc Loc); |
| 613 | |
| 614 | bool isMClass() const { |
| 615 | return getSTI().hasFeature(ARM::FeatureMClass); |
| 616 | } |
| 617 | |
| 618 | /// @name Auto-generated Match Functions |
| 619 | /// { |
| 620 | |
| 621 | #define GET_ASSEMBLER_HEADER |
| 622 | #include "ARMGenAsmMatcher.inc" |
| 623 | |
| 624 | /// } |
| 625 | |
| 626 | OperandMatchResultTy parseITCondCode(OperandVector &); |
| 627 | OperandMatchResultTy parseCoprocNumOperand(OperandVector &); |
| 628 | OperandMatchResultTy parseCoprocRegOperand(OperandVector &); |
| 629 | OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); |
| 630 | OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); |
| 631 | OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &); |
| 632 | OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); |
| 633 | OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); |
| 634 | OperandMatchResultTy parseMSRMaskOperand(OperandVector &); |
| 635 | OperandMatchResultTy parseBankedRegOperand(OperandVector &); |
| 636 | OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, |
| 637 | int High); |
| 638 | OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { |
| 639 | return parsePKHImm(O, "lsl", 0, 31); |
| 640 | } |
| 641 | OperandMatchResultTy parsePKHASRImm(OperandVector &O) { |
| 642 | return parsePKHImm(O, "asr", 1, 32); |
| 643 | } |
| 644 | OperandMatchResultTy parseSetEndImm(OperandVector &); |
| 645 | OperandMatchResultTy parseShifterImm(OperandVector &); |
| 646 | OperandMatchResultTy parseRotImm(OperandVector &); |
| 647 | OperandMatchResultTy parseModImm(OperandVector &); |
| 648 | OperandMatchResultTy parseBitfield(OperandVector &); |
| 649 | OperandMatchResultTy parsePostIdxReg(OperandVector &); |
| 650 | OperandMatchResultTy parseAM3Offset(OperandVector &); |
| 651 | OperandMatchResultTy parseFPImm(OperandVector &); |
| 652 | OperandMatchResultTy parseVectorList(OperandVector &); |
| 653 | OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, |
| 654 | SMLoc &EndLoc); |
| 655 | |
| 656 | // Asm Match Converter Methods |
| 657 | void cvtThumbMultiply(MCInst &Inst, const OperandVector &); |
| 658 | void cvtThumbBranches(MCInst &Inst, const OperandVector &); |
| 659 | void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &); |
| 660 | |
| 661 | bool validateInstruction(MCInst &Inst, const OperandVector &Ops); |
| 662 | bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); |
| 663 | bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); |
| 664 | bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); |
| 665 | bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands); |
| 666 | bool isITBlockTerminator(MCInst &Inst) const; |
| 667 | void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands); |
| 668 | bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, |
| 669 | bool Load, bool ARMMode, bool Writeback); |
| 670 | |
| 671 | public: |
| 672 | enum ARMMatchResultTy { |
| 673 | Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, |
| 674 | Match_RequiresNotITBlock, |
| 675 | Match_RequiresV6, |
| 676 | Match_RequiresThumb2, |
| 677 | Match_RequiresV8, |
| 678 | Match_RequiresFlagSetting, |
| 679 | #define GET_OPERAND_DIAGNOSTIC_TYPES |
| 680 | #include "ARMGenAsmMatcher.inc" |
| 681 | |
| 682 | }; |
| 683 | |
| 684 | ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, |
| 685 | const MCInstrInfo &MII, const MCTargetOptions &Options) |
| 686 | : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) { |
| 687 | MCAsmParserExtension::Initialize(Parser); |
| 688 | |
| 689 | // Cache the MCRegisterInfo. |
| 690 | MRI = getContext().getRegisterInfo(); |
| 691 | |
| 692 | // Initialize the set of available features. |
| 693 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); |
| 694 | |
| 695 | // Add build attributes based on the selected target. |
| 696 | if (AddBuildAttributes) |
| 697 | getTargetStreamer().emitTargetAttributes(STI); |
| 698 | |
| 699 | // Not in an ITBlock to start with. |
| 700 | ITState.CurPosition = ~0U; |
| 701 | |
| 702 | VPTState.CurPosition = ~0U; |
| 703 | |
| 704 | NextSymbolIsThumb = false; |
| 705 | } |
| 706 | |
| 707 | // Implementation of the MCTargetAsmParser interface: |
| 708 | bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc, |
| 709 | SMLoc &EndLoc) override; |
| 710 | OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc, |
| 711 | SMLoc &EndLoc) override; |
| 712 | bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, |
| 713 | SMLoc NameLoc, OperandVector &Operands) override; |
| 714 | bool ParseDirective(AsmToken DirectiveID) override; |
| 715 | |
| 716 | unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, |
| 717 | unsigned Kind) override; |
| 718 | unsigned checkTargetMatchPredicate(MCInst &Inst) override; |
| 719 | |
| 720 | bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
| 721 | OperandVector &Operands, MCStreamer &Out, |
| 722 | uint64_t &ErrorInfo, |
| 723 | bool MatchingInlineAsm) override; |
| 724 | unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst, |
| 725 | SmallVectorImpl<NearMissInfo> &NearMisses, |
| 726 | bool MatchingInlineAsm, bool &EmitInITBlock, |
| 727 | MCStreamer &Out); |
| 728 | |
| 729 | struct NearMissMessage { |
| 730 | SMLoc Loc; |
| 731 | SmallString<128> Message; |
| 732 | }; |
| 733 | |
| 734 | const char *getCustomOperandDiag(ARMMatchResultTy MatchError); |
| 735 | |
| 736 | void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, |
| 737 | SmallVectorImpl<NearMissMessage> &NearMissesOut, |
| 738 | SMLoc IDLoc, OperandVector &Operands); |
| 739 | void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc, |
| 740 | OperandVector &Operands); |
| 741 | |
| 742 | void doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) override; |
| 743 | |
| 744 | void onLabelParsed(MCSymbol *Symbol) override; |
| 745 | }; |
| 746 | |
| 747 | /// ARMOperand - Instances of this class represent a parsed ARM machine |
| 748 | /// operand. |
| 749 | class ARMOperand : public MCParsedAsmOperand { |
| 750 | enum KindTy { |
| 751 | k_CondCode, |
| 752 | k_VPTPred, |
| 753 | k_CCOut, |
| 754 | k_ITCondMask, |
| 755 | k_CoprocNum, |
| 756 | k_CoprocReg, |
| 757 | k_CoprocOption, |
| 758 | k_Immediate, |
| 759 | k_MemBarrierOpt, |
| 760 | k_InstSyncBarrierOpt, |
| 761 | k_TraceSyncBarrierOpt, |
| 762 | k_Memory, |
| 763 | k_PostIndexRegister, |
| 764 | k_MSRMask, |
| 765 | k_BankedReg, |
| 766 | k_ProcIFlags, |
| 767 | k_VectorIndex, |
| 768 | k_Register, |
| 769 | k_RegisterList, |
| 770 | k_RegisterListWithAPSR, |
| 771 | k_DPRRegisterList, |
| 772 | k_SPRRegisterList, |
| 773 | k_FPSRegisterListWithVPR, |
| 774 | k_FPDRegisterListWithVPR, |
| 775 | k_VectorList, |
| 776 | k_VectorListAllLanes, |
| 777 | k_VectorListIndexed, |
| 778 | k_ShiftedRegister, |
| 779 | k_ShiftedImmediate, |
| 780 | k_ShifterImmediate, |
| 781 | k_RotateImmediate, |
| 782 | k_ModifiedImmediate, |
| 783 | k_ConstantPoolImmediate, |
| 784 | k_BitfieldDescriptor, |
| 785 | k_Token, |
| 786 | } Kind; |
| 787 | |
| 788 | SMLoc StartLoc, EndLoc, AlignmentLoc; |
| 789 | SmallVector<unsigned, 8> Registers; |
| 790 | |
| 791 | struct CCOp { |
| 792 | ARMCC::CondCodes Val; |
| 793 | }; |
| 794 | |
| 795 | struct VCCOp { |
| 796 | ARMVCC::VPTCodes Val; |
| 797 | }; |
| 798 | |
| 799 | struct CopOp { |
| 800 | unsigned Val; |
| 801 | }; |
| 802 | |
| 803 | struct CoprocOptionOp { |
| 804 | unsigned Val; |
| 805 | }; |
| 806 | |
| 807 | struct ITMaskOp { |
| 808 | unsigned Mask:4; |
| 809 | }; |
| 810 | |
| 811 | struct MBOptOp { |
| 812 | ARM_MB::MemBOpt Val; |
| 813 | }; |
| 814 | |
| 815 | struct ISBOptOp { |
| 816 | ARM_ISB::InstSyncBOpt Val; |
| 817 | }; |
| 818 | |
| 819 | struct TSBOptOp { |
| 820 | ARM_TSB::TraceSyncBOpt Val; |
| 821 | }; |
| 822 | |
| 823 | struct IFlagsOp { |
| 824 | ARM_PROC::IFlags Val; |
| 825 | }; |
| 826 | |
| 827 | struct MMaskOp { |
| 828 | unsigned Val; |
| 829 | }; |
| 830 | |
| 831 | struct BankedRegOp { |
| 832 | unsigned Val; |
| 833 | }; |
| 834 | |
| 835 | struct TokOp { |
| 836 | const char *Data; |
| 837 | unsigned Length; |
| 838 | }; |
| 839 | |
| 840 | struct RegOp { |
| 841 | unsigned RegNum; |
| 842 | }; |
| 843 | |
| 844 | // A vector register list is a sequential list of 1 to 4 registers. |
| 845 | struct VectorListOp { |
| 846 | unsigned RegNum; |
| 847 | unsigned Count; |
| 848 | unsigned LaneIndex; |
| 849 | bool isDoubleSpaced; |
| 850 | }; |
| 851 | |
| 852 | struct VectorIndexOp { |
| 853 | unsigned Val; |
| 854 | }; |
| 855 | |
| 856 | struct ImmOp { |
| 857 | const MCExpr *Val; |
| 858 | }; |
| 859 | |
| 860 | /// Combined record for all forms of ARM address expressions. |
| 861 | struct MemoryOp { |
| 862 | unsigned BaseRegNum; |
| 863 | // Offset is in OffsetReg or OffsetImm. If both are zero, no offset |
| 864 | // was specified. |
| 865 | const MCExpr *OffsetImm; // Offset immediate value |
| 866 | unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL |
| 867 | ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg |
| 868 | unsigned ShiftImm; // shift for OffsetReg. |
| 869 | unsigned Alignment; // 0 = no alignment specified |
| 870 | // n = alignment in bytes (2, 4, 8, 16, or 32) |
| 871 | unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) |
| 872 | }; |
| 873 | |
| 874 | struct PostIdxRegOp { |
| 875 | unsigned RegNum; |
| 876 | bool isAdd; |
| 877 | ARM_AM::ShiftOpc ShiftTy; |
| 878 | unsigned ShiftImm; |
| 879 | }; |
| 880 | |
| 881 | struct ShifterImmOp { |
| 882 | bool isASR; |
| 883 | unsigned Imm; |
| 884 | }; |
| 885 | |
| 886 | struct RegShiftedRegOp { |
| 887 | ARM_AM::ShiftOpc ShiftTy; |
| 888 | unsigned SrcReg; |
| 889 | unsigned ShiftReg; |
| 890 | unsigned ShiftImm; |
| 891 | }; |
| 892 | |
| 893 | struct RegShiftedImmOp { |
| 894 | ARM_AM::ShiftOpc ShiftTy; |
| 895 | unsigned SrcReg; |
| 896 | unsigned ShiftImm; |
| 897 | }; |
| 898 | |
| 899 | struct RotImmOp { |
| 900 | unsigned Imm; |
| 901 | }; |
| 902 | |
| 903 | struct ModImmOp { |
| 904 | unsigned Bits; |
| 905 | unsigned Rot; |
| 906 | }; |
| 907 | |
| 908 | struct BitfieldOp { |
| 909 | unsigned LSB; |
| 910 | unsigned Width; |
| 911 | }; |
| 912 | |
| 913 | union { |
| 914 | struct CCOp CC; |
| 915 | struct VCCOp VCC; |
| 916 | struct CopOp Cop; |
| 917 | struct CoprocOptionOp CoprocOption; |
| 918 | struct MBOptOp MBOpt; |
| 919 | struct ISBOptOp ISBOpt; |
| 920 | struct TSBOptOp TSBOpt; |
| 921 | struct ITMaskOp ITMask; |
| 922 | struct IFlagsOp IFlags; |
| 923 | struct MMaskOp MMask; |
| 924 | struct BankedRegOp BankedReg; |
| 925 | struct TokOp Tok; |
| 926 | struct RegOp Reg; |
| 927 | struct VectorListOp VectorList; |
| 928 | struct VectorIndexOp VectorIndex; |
| 929 | struct ImmOp Imm; |
| 930 | struct MemoryOp Memory; |
| 931 | struct PostIdxRegOp PostIdxReg; |
| 932 | struct ShifterImmOp ShifterImm; |
| 933 | struct RegShiftedRegOp RegShiftedReg; |
| 934 | struct RegShiftedImmOp RegShiftedImm; |
| 935 | struct RotImmOp RotImm; |
| 936 | struct ModImmOp ModImm; |
| 937 | struct BitfieldOp Bitfield; |
| 938 | }; |
| 939 | |
| 940 | public: |
| 941 | ARMOperand(KindTy K) : Kind(K) {} |
| 942 | |
| 943 | /// getStartLoc - Get the location of the first token of this operand. |
| 944 | SMLoc getStartLoc() const override { return StartLoc; } |
| 945 | |
| 946 | /// getEndLoc - Get the location of the last token of this operand. |
| 947 | SMLoc getEndLoc() const override { return EndLoc; } |
| 948 | |
| 949 | /// getLocRange - Get the range between the first and last token of this |
| 950 | /// operand. |
| 951 | SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } |
| 952 | |
| 953 | /// getAlignmentLoc - Get the location of the Alignment token of this operand. |
| 954 | SMLoc getAlignmentLoc() const { |
| 955 | assert(Kind == k_Memory && "Invalid access!")(static_cast <bool> (Kind == k_Memory && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_Memory && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 955, __extension__ __PRETTY_FUNCTION__)); |
| 956 | return AlignmentLoc; |
| 957 | } |
| 958 | |
| 959 | ARMCC::CondCodes getCondCode() const { |
| 960 | assert(Kind == k_CondCode && "Invalid access!")(static_cast <bool> (Kind == k_CondCode && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_CondCode && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 960, __extension__ __PRETTY_FUNCTION__)); |
| 961 | return CC.Val; |
| 962 | } |
| 963 | |
| 964 | ARMVCC::VPTCodes getVPTPred() const { |
| 965 | assert(isVPTPred() && "Invalid access!")(static_cast <bool> (isVPTPred() && "Invalid access!" ) ? void (0) : __assert_fail ("isVPTPred() && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 965, __extension__ __PRETTY_FUNCTION__)); |
| 966 | return VCC.Val; |
| 967 | } |
| 968 | |
| 969 | unsigned getCoproc() const { |
| 970 | assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!")(static_cast <bool> ((Kind == k_CoprocNum || Kind == k_CoprocReg ) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_CoprocNum || Kind == k_CoprocReg) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 970, __extension__ __PRETTY_FUNCTION__)); |
| 971 | return Cop.Val; |
| 972 | } |
| 973 | |
| 974 | StringRef getToken() const { |
| 975 | assert(Kind == k_Token && "Invalid access!")(static_cast <bool> (Kind == k_Token && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_Token && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 975, __extension__ __PRETTY_FUNCTION__)); |
| 976 | return StringRef(Tok.Data, Tok.Length); |
| 977 | } |
| 978 | |
| 979 | unsigned getReg() const override { |
| 980 | assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!")(static_cast <bool> ((Kind == k_Register || Kind == k_CCOut ) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_Register || Kind == k_CCOut) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 980, __extension__ __PRETTY_FUNCTION__)); |
| 981 | return Reg.RegNum; |
| 982 | } |
| 983 | |
| 984 | const SmallVectorImpl<unsigned> &getRegList() const { |
| 985 | assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||(static_cast <bool> ((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 989, __extension__ __PRETTY_FUNCTION__)) |
| 986 | Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||(static_cast <bool> ((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 989, __extension__ __PRETTY_FUNCTION__)) |
| 987 | Kind == k_FPSRegisterListWithVPR ||(static_cast <bool> ((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 989, __extension__ __PRETTY_FUNCTION__)) |
| 988 | Kind == k_FPDRegisterListWithVPR) &&(static_cast <bool> ((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 989, __extension__ __PRETTY_FUNCTION__)) |
| 989 | "Invalid access!")(static_cast <bool> ((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!") ? void (0) : __assert_fail ("(Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 989, __extension__ __PRETTY_FUNCTION__)); |
| 990 | return Registers; |
| 991 | } |
| 992 | |
| 993 | const MCExpr *getImm() const { |
| 994 | assert(isImm() && "Invalid access!")(static_cast <bool> (isImm() && "Invalid access!" ) ? void (0) : __assert_fail ("isImm() && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 994, __extension__ __PRETTY_FUNCTION__)); |
| 995 | return Imm.Val; |
| 996 | } |
| 997 | |
| 998 | const MCExpr *getConstantPoolImm() const { |
| 999 | assert(isConstantPoolImm() && "Invalid access!")(static_cast <bool> (isConstantPoolImm() && "Invalid access!" ) ? void (0) : __assert_fail ("isConstantPoolImm() && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 999, __extension__ __PRETTY_FUNCTION__)); |
| 1000 | return Imm.Val; |
| 1001 | } |
| 1002 | |
| 1003 | unsigned getVectorIndex() const { |
| 1004 | assert(Kind == k_VectorIndex && "Invalid access!")(static_cast <bool> (Kind == k_VectorIndex && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_VectorIndex && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1004, __extension__ __PRETTY_FUNCTION__)); |
| 1005 | return VectorIndex.Val; |
| 1006 | } |
| 1007 | |
| 1008 | ARM_MB::MemBOpt getMemBarrierOpt() const { |
| 1009 | assert(Kind == k_MemBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_MemBarrierOpt && "Invalid access!") ? void (0) : __assert_fail ("Kind == k_MemBarrierOpt && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1009, __extension__ __PRETTY_FUNCTION__)); |
| 1010 | return MBOpt.Val; |
| 1011 | } |
| 1012 | |
| 1013 | ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { |
| 1014 | assert(Kind == k_InstSyncBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_InstSyncBarrierOpt && "Invalid access!") ? void (0) : __assert_fail ("Kind == k_InstSyncBarrierOpt && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1014, __extension__ __PRETTY_FUNCTION__)); |
| 1015 | return ISBOpt.Val; |
| 1016 | } |
| 1017 | |
| 1018 | ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const { |
| 1019 | assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!")(static_cast <bool> (Kind == k_TraceSyncBarrierOpt && "Invalid access!") ? void (0) : __assert_fail ("Kind == k_TraceSyncBarrierOpt && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1019, __extension__ __PRETTY_FUNCTION__)); |
| 1020 | return TSBOpt.Val; |
| 1021 | } |
| 1022 | |
| 1023 | ARM_PROC::IFlags getProcIFlags() const { |
| 1024 | assert(Kind == k_ProcIFlags && "Invalid access!")(static_cast <bool> (Kind == k_ProcIFlags && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_ProcIFlags && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1024, __extension__ __PRETTY_FUNCTION__)); |
| 1025 | return IFlags.Val; |
| 1026 | } |
| 1027 | |
| 1028 | unsigned getMSRMask() const { |
| 1029 | assert(Kind == k_MSRMask && "Invalid access!")(static_cast <bool> (Kind == k_MSRMask && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_MSRMask && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1029, __extension__ __PRETTY_FUNCTION__)); |
| 1030 | return MMask.Val; |
| 1031 | } |
| 1032 | |
| 1033 | unsigned getBankedReg() const { |
| 1034 | assert(Kind == k_BankedReg && "Invalid access!")(static_cast <bool> (Kind == k_BankedReg && "Invalid access!" ) ? void (0) : __assert_fail ("Kind == k_BankedReg && \"Invalid access!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 1034, __extension__ __PRETTY_FUNCTION__)); |
| 1035 | return BankedReg.Val; |
| 1036 | } |
| 1037 | |
| 1038 | bool isCoprocNum() const { return Kind == k_CoprocNum; } |
| 1039 | bool isCoprocReg() const { return Kind == k_CoprocReg; } |
| 1040 | bool isCoprocOption() const { return Kind == k_CoprocOption; } |
| 1041 | bool isCondCode() const { return Kind == k_CondCode; } |
| 1042 | bool isVPTPred() const { return Kind == k_VPTPred; } |
| 1043 | bool isCCOut() const { return Kind == k_CCOut; } |
| 1044 | bool isITMask() const { return Kind == k_ITCondMask; } |
| 1045 | bool isITCondCode() const { return Kind == k_CondCode; } |
| 1046 | bool isImm() const override { |
| 1047 | return Kind == k_Immediate; |
| 1048 | } |
| 1049 | |
| 1050 | bool isARMBranchTarget() const { |
| 1051 | if (!isImm()) return false; |
| 1052 | |
| 1053 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) |
| 1054 | return CE->getValue() % 4 == 0; |
| 1055 | return true; |
| 1056 | } |
| 1057 | |
| 1058 | |
| 1059 | bool isThumbBranchTarget() const { |
| 1060 | if (!isImm()) return false; |
| 1061 | |
| 1062 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) |
| 1063 | return CE->getValue() % 2 == 0; |
| 1064 | return true; |
| 1065 | } |
| 1066 | |
| 1067 | // checks whether this operand is an unsigned offset which fits is a field |
| 1068 | // of specified width and scaled by a specific number of bits |
| 1069 | template<unsigned width, unsigned scale> |
| 1070 | bool isUnsignedOffset() const { |
| 1071 | if (!isImm()) return false; |
| 1072 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; |
| 1073 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { |
| 1074 | int64_t Val = CE->getValue(); |
| 1075 | int64_t Align = 1LL << scale; |
| 1076 | int64_t Max = Align * ((1LL << width) - 1); |
| 1077 | return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); |
| 1078 | } |
| 1079 | return false; |
| 1080 | } |
| 1081 | |
| 1082 | // checks whether this operand is an signed offset which fits is a field |
| 1083 | // of specified width and scaled by a specific number of bits |
| 1084 | template<unsigned width, unsigned scale> |
| 1085 | bool isSignedOffset() const { |
| 1086 | if (!isImm()) return false; |
| 1087 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; |
| 1088 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { |
| 1089 | int64_t Val = CE->getValue(); |
| 1090 | int64_t Align = 1LL << scale; |
| 1091 | int64_t Max = Align * ((1LL << (width-1)) - 1); |
| 1092 | int64_t Min = -Align * (1LL << (width-1)); |
| 1093 | return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); |
| 1094 | } |
| 1095 | return false; |
| 1096 | } |
| 1097 | |
| 1098 | // checks whether this operand is an offset suitable for the LE / |
| 1099 | // LETP instructions in Arm v8.1M |
| 1100 | bool isLEOffset() const { |
| 1101 | if (!isImm()) return false; |
| 1102 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; |
| 1103 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { |
| 1104 | int64_t Val = CE->getValue(); |
| 1105 | return Val < 0 && Val >= -4094 && (Val & 1) == 0; |
| 1106 | } |
| 1107 | return false; |
| 1108 | } |
| 1109 | |
| 1110 | // checks whether this operand is a memory operand computed as an offset |
| 1111 | // applied to PC. the offset may have 8 bits of magnitude and is represented |
| 1112 | // with two bits of shift. textually it may be either [pc, #imm], #imm or |
| 1113 | // relocable expression... |
| 1114 | bool isThumbMemPC() const { |
| 1115 | int64_t Val = 0; |
| 1116 | if (isImm()) { |
| 1117 | if (isa<MCSymbolRefExpr>(Imm.Val)) return true; |
| 1118 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); |
| 1119 | if (!CE) return false; |
| 1120 | Val = CE->getValue(); |
| 1121 | } |
| 1122 | else if (isGPRMem()) { |
| 1123 | if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; |
| 1124 | if(Memory.BaseRegNum != ARM::PC) return false; |
| 1125 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 1126 | Val = CE->getValue(); |
| 1127 | else |
| 1128 | return false; |
| 1129 | } |
| 1130 | else return false; |
| 1131 | return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); |
| 1132 | } |
| 1133 | |
| 1134 | bool isFPImm() const { |
| 1135 | if (!isImm()) return false; |
| 1136 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1137 | if (!CE) return false; |
| 1138 | int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); |
| 1139 | return Val != -1; |
| 1140 | } |
| 1141 | |
| 1142 | template<int64_t N, int64_t M> |
| 1143 | bool isImmediate() const { |
| 1144 | if (!isImm()) return false; |
| 1145 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1146 | if (!CE) return false; |
| 1147 | int64_t Value = CE->getValue(); |
| 1148 | return Value >= N && Value <= M; |
| 1149 | } |
| 1150 | |
| 1151 | template<int64_t N, int64_t M> |
| 1152 | bool isImmediateS4() const { |
| 1153 | if (!isImm()) return false; |
| 1154 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1155 | if (!CE) return false; |
| 1156 | int64_t Value = CE->getValue(); |
| 1157 | return ((Value & 3) == 0) && Value >= N && Value <= M; |
| 1158 | } |
| 1159 | template<int64_t N, int64_t M> |
| 1160 | bool isImmediateS2() const { |
| 1161 | if (!isImm()) return false; |
| 1162 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1163 | if (!CE) return false; |
| 1164 | int64_t Value = CE->getValue(); |
| 1165 | return ((Value & 1) == 0) && Value >= N && Value <= M; |
| 1166 | } |
| 1167 | bool isFBits16() const { |
| 1168 | return isImmediate<0, 17>(); |
| 1169 | } |
| 1170 | bool isFBits32() const { |
| 1171 | return isImmediate<1, 33>(); |
| 1172 | } |
| 1173 | bool isImm8s4() const { |
| 1174 | return isImmediateS4<-1020, 1020>(); |
| 1175 | } |
| 1176 | bool isImm7s4() const { |
| 1177 | return isImmediateS4<-508, 508>(); |
| 1178 | } |
| 1179 | bool isImm7Shift0() const { |
| 1180 | return isImmediate<-127, 127>(); |
| 1181 | } |
| 1182 | bool isImm7Shift1() const { |
| 1183 | return isImmediateS2<-255, 255>(); |
| 1184 | } |
| 1185 | bool isImm7Shift2() const { |
| 1186 | return isImmediateS4<-511, 511>(); |
| 1187 | } |
| 1188 | bool isImm7() const { |
| 1189 | return isImmediate<-127, 127>(); |
| 1190 | } |
| 1191 | bool isImm0_1020s4() const { |
| 1192 | return isImmediateS4<0, 1020>(); |
| 1193 | } |
| 1194 | bool isImm0_508s4() const { |
| 1195 | return isImmediateS4<0, 508>(); |
| 1196 | } |
| 1197 | bool isImm0_508s4Neg() const { |
| 1198 | if (!isImm()) return false; |
| 1199 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1200 | if (!CE) return false; |
| 1201 | int64_t Value = -CE->getValue(); |
| 1202 | // explicitly exclude zero. we want that to use the normal 0_508 version. |
| 1203 | return ((Value & 3) == 0) && Value > 0 && Value <= 508; |
| 1204 | } |
| 1205 | |
| 1206 | bool isImm0_4095Neg() const { |
| 1207 | if (!isImm()) return false; |
| 1208 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1209 | if (!CE) return false; |
| 1210 | // isImm0_4095Neg is used with 32-bit immediates only. |
| 1211 | // 32-bit immediates are zero extended to 64-bit when parsed, |
| 1212 | // thus simple -CE->getValue() results in a big negative number, |
| 1213 | // not a small positive number as intended |
| 1214 | if ((CE->getValue() >> 32) > 0) return false; |
| 1215 | uint32_t Value = -static_cast<uint32_t>(CE->getValue()); |
| 1216 | return Value > 0 && Value < 4096; |
| 1217 | } |
| 1218 | |
| 1219 | bool isImm0_7() const { |
| 1220 | return isImmediate<0, 7>(); |
| 1221 | } |
| 1222 | |
| 1223 | bool isImm1_16() const { |
| 1224 | return isImmediate<1, 16>(); |
| 1225 | } |
| 1226 | |
| 1227 | bool isImm1_32() const { |
| 1228 | return isImmediate<1, 32>(); |
| 1229 | } |
| 1230 | |
| 1231 | bool isImm8_255() const { |
| 1232 | return isImmediate<8, 255>(); |
| 1233 | } |
| 1234 | |
| 1235 | bool isImm256_65535Expr() const { |
| 1236 | if (!isImm()) return false; |
| 1237 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1238 | // If it's not a constant expression, it'll generate a fixup and be |
| 1239 | // handled later. |
| 1240 | if (!CE) return true; |
| 1241 | int64_t Value = CE->getValue(); |
| 1242 | return Value >= 256 && Value < 65536; |
| 1243 | } |
| 1244 | |
| 1245 | bool isImm0_65535Expr() const { |
| 1246 | if (!isImm()) return false; |
| 1247 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1248 | // If it's not a constant expression, it'll generate a fixup and be |
| 1249 | // handled later. |
| 1250 | if (!CE) return true; |
| 1251 | int64_t Value = CE->getValue(); |
| 1252 | return Value >= 0 && Value < 65536; |
| 1253 | } |
| 1254 | |
| 1255 | bool isImm24bit() const { |
| 1256 | return isImmediate<0, 0xffffff + 1>(); |
| 1257 | } |
| 1258 | |
| 1259 | bool isImmThumbSR() const { |
| 1260 | return isImmediate<1, 33>(); |
| 1261 | } |
| 1262 | |
| 1263 | template<int shift> |
| 1264 | bool isExpImmValue(uint64_t Value) const { |
| 1265 | uint64_t mask = (1 << shift) - 1; |
| 1266 | if ((Value & mask) != 0 || (Value >> shift) > 0xff) |
| 1267 | return false; |
| 1268 | return true; |
| 1269 | } |
| 1270 | |
| 1271 | template<int shift> |
| 1272 | bool isExpImm() const { |
| 1273 | if (!isImm()) return false; |
| 1274 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1275 | if (!CE) return false; |
| 1276 | |
| 1277 | return isExpImmValue<shift>(CE->getValue()); |
| 1278 | } |
| 1279 | |
| 1280 | template<int shift, int size> |
| 1281 | bool isInvertedExpImm() const { |
| 1282 | if (!isImm()) return false; |
| 1283 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1284 | if (!CE) return false; |
| 1285 | |
| 1286 | uint64_t OriginalValue = CE->getValue(); |
| 1287 | uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1); |
| 1288 | return isExpImmValue<shift>(InvertedValue); |
| 1289 | } |
| 1290 | |
| 1291 | bool isPKHLSLImm() const { |
| 1292 | return isImmediate<0, 32>(); |
| 1293 | } |
| 1294 | |
| 1295 | bool isPKHASRImm() const { |
| 1296 | return isImmediate<0, 33>(); |
| 1297 | } |
| 1298 | |
| 1299 | bool isAdrLabel() const { |
| 1300 | // If we have an immediate that's not a constant, treat it as a label |
| 1301 | // reference needing a fixup. |
| 1302 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1303 | return true; |
| 1304 | |
| 1305 | // If it is a constant, it must fit into a modified immediate encoding. |
| 1306 | if (!isImm()) return false; |
| 1307 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1308 | if (!CE) return false; |
| 1309 | int64_t Value = CE->getValue(); |
| 1310 | return (ARM_AM::getSOImmVal(Value) != -1 || |
| 1311 | ARM_AM::getSOImmVal(-Value) != -1); |
| 1312 | } |
| 1313 | |
| 1314 | bool isT2SOImm() const { |
| 1315 | // If we have an immediate that's not a constant, treat it as an expression |
| 1316 | // needing a fixup. |
| 1317 | if (isImm() && !isa<MCConstantExpr>(getImm())) { |
| 1318 | // We want to avoid matching :upper16: and :lower16: as we want these |
| 1319 | // expressions to match in isImm0_65535Expr() |
| 1320 | const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm()); |
| 1321 | return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && |
| 1322 | ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)); |
| 1323 | } |
| 1324 | if (!isImm()) return false; |
| 1325 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1326 | if (!CE) return false; |
| 1327 | int64_t Value = CE->getValue(); |
| 1328 | return ARM_AM::getT2SOImmVal(Value) != -1; |
| 1329 | } |
| 1330 | |
| 1331 | bool isT2SOImmNot() const { |
| 1332 | if (!isImm()) return false; |
| 1333 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1334 | if (!CE) return false; |
| 1335 | int64_t Value = CE->getValue(); |
| 1336 | return ARM_AM::getT2SOImmVal(Value) == -1 && |
| 1337 | ARM_AM::getT2SOImmVal(~Value) != -1; |
| 1338 | } |
| 1339 | |
| 1340 | bool isT2SOImmNeg() const { |
| 1341 | if (!isImm()) return false; |
| 1342 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1343 | if (!CE) return false; |
| 1344 | int64_t Value = CE->getValue(); |
| 1345 | // Only use this when not representable as a plain so_imm. |
| 1346 | return ARM_AM::getT2SOImmVal(Value) == -1 && |
| 1347 | ARM_AM::getT2SOImmVal(-Value) != -1; |
| 1348 | } |
| 1349 | |
| 1350 | bool isSetEndImm() const { |
| 1351 | if (!isImm()) return false; |
| 1352 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1353 | if (!CE) return false; |
| 1354 | int64_t Value = CE->getValue(); |
| 1355 | return Value == 1 || Value == 0; |
| 1356 | } |
| 1357 | |
| 1358 | bool isReg() const override { return Kind == k_Register; } |
| 1359 | bool isRegList() const { return Kind == k_RegisterList; } |
| 1360 | bool isRegListWithAPSR() const { |
| 1361 | return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList; |
| 1362 | } |
| 1363 | bool isDPRRegList() const { return Kind == k_DPRRegisterList; } |
| 1364 | bool isSPRRegList() const { return Kind == k_SPRRegisterList; } |
| 1365 | bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; } |
| 1366 | bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; } |
| 1367 | bool isToken() const override { return Kind == k_Token; } |
| 1368 | bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } |
| 1369 | bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } |
| 1370 | bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; } |
| 1371 | bool isMem() const override { |
| 1372 | return isGPRMem() || isMVEMem(); |
| 1373 | } |
| 1374 | bool isMVEMem() const { |
| 1375 | if (Kind != k_Memory) |
| 1376 | return false; |
| 1377 | if (Memory.BaseRegNum && |
| 1378 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && |
| 1379 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) |
| 1380 | return false; |
| 1381 | if (Memory.OffsetRegNum && |
| 1382 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( |
| 1383 | Memory.OffsetRegNum)) |
| 1384 | return false; |
| 1385 | return true; |
| 1386 | } |
| 1387 | bool isGPRMem() const { |
| 1388 | if (Kind != k_Memory) |
| 1389 | return false; |
| 1390 | if (Memory.BaseRegNum && |
| 1391 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) |
| 1392 | return false; |
| 1393 | if (Memory.OffsetRegNum && |
| 1394 | !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) |
| 1395 | return false; |
| 1396 | return true; |
| 1397 | } |
| 1398 | bool isShifterImm() const { return Kind == k_ShifterImmediate; } |
| 1399 | bool isRegShiftedReg() const { |
| 1400 | return Kind == k_ShiftedRegister && |
| 1401 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( |
| 1402 | RegShiftedReg.SrcReg) && |
| 1403 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( |
| 1404 | RegShiftedReg.ShiftReg); |
| 1405 | } |
| 1406 | bool isRegShiftedImm() const { |
| 1407 | return Kind == k_ShiftedImmediate && |
| 1408 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains( |
| 1409 | RegShiftedImm.SrcReg); |
| 1410 | } |
| 1411 | bool isRotImm() const { return Kind == k_RotateImmediate; } |
| 1412 | |
| 1413 | template<unsigned Min, unsigned Max> |
| 1414 | bool isPowerTwoInRange() const { |
| 1415 | if (!isImm()) return false; |
| 1416 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1417 | if (!CE) return false; |
| 1418 | int64_t Value = CE->getValue(); |
| 1419 | return Value > 0 && llvm::popcount((uint64_t)Value) == 1 && Value >= Min && |
| 1420 | Value <= Max; |
| 1421 | } |
| 1422 | bool isModImm() const { return Kind == k_ModifiedImmediate; } |
| 1423 | |
| 1424 | bool isModImmNot() const { |
| 1425 | if (!isImm()) return false; |
| 1426 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1427 | if (!CE) return false; |
| 1428 | int64_t Value = CE->getValue(); |
| 1429 | return ARM_AM::getSOImmVal(~Value) != -1; |
| 1430 | } |
| 1431 | |
| 1432 | bool isModImmNeg() const { |
| 1433 | if (!isImm()) return false; |
| 1434 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1435 | if (!CE) return false; |
| 1436 | int64_t Value = CE->getValue(); |
| 1437 | return ARM_AM::getSOImmVal(Value) == -1 && |
| 1438 | ARM_AM::getSOImmVal(-Value) != -1; |
| 1439 | } |
| 1440 | |
| 1441 | bool isThumbModImmNeg1_7() const { |
| 1442 | if (!isImm()) return false; |
| 1443 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1444 | if (!CE) return false; |
| 1445 | int32_t Value = -(int32_t)CE->getValue(); |
| 1446 | return 0 < Value && Value < 8; |
| 1447 | } |
| 1448 | |
| 1449 | bool isThumbModImmNeg8_255() const { |
| 1450 | if (!isImm()) return false; |
| 1451 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1452 | if (!CE) return false; |
| 1453 | int32_t Value = -(int32_t)CE->getValue(); |
| 1454 | return 7 < Value && Value < 256; |
| 1455 | } |
| 1456 | |
| 1457 | bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; } |
| 1458 | bool isBitfield() const { return Kind == k_BitfieldDescriptor; } |
| 1459 | bool isPostIdxRegShifted() const { |
| 1460 | return Kind == k_PostIndexRegister && |
| 1461 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); |
| 1462 | } |
| 1463 | bool isPostIdxReg() const { |
| 1464 | return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; |
| 1465 | } |
| 1466 | bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { |
| 1467 | if (!isGPRMem()) |
| 1468 | return false; |
| 1469 | // No offset of any kind. |
| 1470 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && |
| 1471 | (alignOK || Memory.Alignment == Alignment); |
| 1472 | } |
| 1473 | bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const { |
| 1474 | if (!isGPRMem()) |
| 1475 | return false; |
| 1476 | |
| 1477 | if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( |
| 1478 | Memory.BaseRegNum)) |
| 1479 | return false; |
| 1480 | |
| 1481 | // No offset of any kind. |
| 1482 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && |
| 1483 | (alignOK || Memory.Alignment == Alignment); |
| 1484 | } |
| 1485 | bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const { |
| 1486 | if (!isGPRMem()) |
| 1487 | return false; |
| 1488 | |
| 1489 | if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( |
| 1490 | Memory.BaseRegNum)) |
| 1491 | return false; |
| 1492 | |
| 1493 | // No offset of any kind. |
| 1494 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && |
| 1495 | (alignOK || Memory.Alignment == Alignment); |
| 1496 | } |
| 1497 | bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const { |
| 1498 | if (!isGPRMem()) |
| 1499 | return false; |
| 1500 | |
| 1501 | if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( |
| 1502 | Memory.BaseRegNum)) |
| 1503 | return false; |
| 1504 | |
| 1505 | // No offset of any kind. |
| 1506 | return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && |
| 1507 | (alignOK || Memory.Alignment == Alignment); |
| 1508 | } |
| 1509 | bool isMemPCRelImm12() const { |
| 1510 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1511 | return false; |
| 1512 | // Base register must be PC. |
| 1513 | if (Memory.BaseRegNum != ARM::PC) |
| 1514 | return false; |
| 1515 | // Immediate offset in range [-4095, 4095]. |
| 1516 | if (!Memory.OffsetImm) return true; |
| 1517 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1518 | int64_t Val = CE->getValue(); |
| 1519 | return (Val > -4096 && Val < 4096) || |
| 1520 | (Val == std::numeric_limits<int32_t>::min()); |
| 1521 | } |
| 1522 | return false; |
| 1523 | } |
| 1524 | |
| 1525 | bool isAlignedMemory() const { |
| 1526 | return isMemNoOffset(true); |
| 1527 | } |
| 1528 | |
| 1529 | bool isAlignedMemoryNone() const { |
| 1530 | return isMemNoOffset(false, 0); |
| 1531 | } |
| 1532 | |
| 1533 | bool isDupAlignedMemoryNone() const { |
| 1534 | return isMemNoOffset(false, 0); |
| 1535 | } |
| 1536 | |
| 1537 | bool isAlignedMemory16() const { |
| 1538 | if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. |
| 1539 | return true; |
| 1540 | return isMemNoOffset(false, 0); |
| 1541 | } |
| 1542 | |
| 1543 | bool isDupAlignedMemory16() const { |
| 1544 | if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. |
| 1545 | return true; |
| 1546 | return isMemNoOffset(false, 0); |
| 1547 | } |
| 1548 | |
| 1549 | bool isAlignedMemory32() const { |
| 1550 | if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. |
| 1551 | return true; |
| 1552 | return isMemNoOffset(false, 0); |
| 1553 | } |
| 1554 | |
| 1555 | bool isDupAlignedMemory32() const { |
| 1556 | if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. |
| 1557 | return true; |
| 1558 | return isMemNoOffset(false, 0); |
| 1559 | } |
| 1560 | |
| 1561 | bool isAlignedMemory64() const { |
| 1562 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. |
| 1563 | return true; |
| 1564 | return isMemNoOffset(false, 0); |
| 1565 | } |
| 1566 | |
| 1567 | bool isDupAlignedMemory64() const { |
| 1568 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. |
| 1569 | return true; |
| 1570 | return isMemNoOffset(false, 0); |
| 1571 | } |
| 1572 | |
| 1573 | bool isAlignedMemory64or128() const { |
| 1574 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. |
| 1575 | return true; |
| 1576 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. |
| 1577 | return true; |
| 1578 | return isMemNoOffset(false, 0); |
| 1579 | } |
| 1580 | |
| 1581 | bool isDupAlignedMemory64or128() const { |
| 1582 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. |
| 1583 | return true; |
| 1584 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. |
| 1585 | return true; |
| 1586 | return isMemNoOffset(false, 0); |
| 1587 | } |
| 1588 | |
| 1589 | bool isAlignedMemory64or128or256() const { |
| 1590 | if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. |
| 1591 | return true; |
| 1592 | if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. |
| 1593 | return true; |
| 1594 | if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. |
| 1595 | return true; |
| 1596 | return isMemNoOffset(false, 0); |
| 1597 | } |
| 1598 | |
| 1599 | bool isAddrMode2() const { |
| 1600 | if (!isGPRMem() || Memory.Alignment != 0) return false; |
| 1601 | // Check for register offset. |
| 1602 | if (Memory.OffsetRegNum) return true; |
| 1603 | // Immediate offset in range [-4095, 4095]. |
| 1604 | if (!Memory.OffsetImm) return true; |
| 1605 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1606 | int64_t Val = CE->getValue(); |
| 1607 | return Val > -4096 && Val < 4096; |
| 1608 | } |
| 1609 | return false; |
| 1610 | } |
| 1611 | |
| 1612 | bool isAM2OffsetImm() const { |
| 1613 | if (!isImm()) return false; |
| 1614 | // Immediate offset in range [-4095, 4095]. |
| 1615 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1616 | if (!CE) return false; |
| 1617 | int64_t Val = CE->getValue(); |
| 1618 | return (Val == std::numeric_limits<int32_t>::min()) || |
| 1619 | (Val > -4096 && Val < 4096); |
| 1620 | } |
| 1621 | |
| 1622 | bool isAddrMode3() const { |
| 1623 | // If we have an immediate that's not a constant, treat it as a label |
| 1624 | // reference needing a fixup. If it is a constant, it's something else |
| 1625 | // and we reject it. |
| 1626 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1627 | return true; |
| 1628 | if (!isGPRMem() || Memory.Alignment != 0) return false; |
| 1629 | // No shifts are legal for AM3. |
| 1630 | if (Memory.ShiftType != ARM_AM::no_shift) return false; |
| 1631 | // Check for register offset. |
| 1632 | if (Memory.OffsetRegNum) return true; |
| 1633 | // Immediate offset in range [-255, 255]. |
| 1634 | if (!Memory.OffsetImm) return true; |
| 1635 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1636 | int64_t Val = CE->getValue(); |
| 1637 | // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and |
| 1638 | // we have to check for this too. |
| 1639 | return (Val > -256 && Val < 256) || |
| 1640 | Val == std::numeric_limits<int32_t>::min(); |
| 1641 | } |
| 1642 | return false; |
| 1643 | } |
| 1644 | |
| 1645 | bool isAM3Offset() const { |
| 1646 | if (isPostIdxReg()) |
| 1647 | return true; |
| 1648 | if (!isImm()) |
| 1649 | return false; |
| 1650 | // Immediate offset in range [-255, 255]. |
| 1651 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 1652 | if (!CE) return false; |
| 1653 | int64_t Val = CE->getValue(); |
| 1654 | // Special case, #-0 is std::numeric_limits<int32_t>::min(). |
| 1655 | return (Val > -256 && Val < 256) || |
| 1656 | Val == std::numeric_limits<int32_t>::min(); |
| 1657 | } |
| 1658 | |
| 1659 | bool isAddrMode5() const { |
| 1660 | // If we have an immediate that's not a constant, treat it as a label |
| 1661 | // reference needing a fixup. If it is a constant, it's something else |
| 1662 | // and we reject it. |
| 1663 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1664 | return true; |
| 1665 | if (!isGPRMem() || Memory.Alignment != 0) return false; |
| 1666 | // Check for register offset. |
| 1667 | if (Memory.OffsetRegNum) return false; |
| 1668 | // Immediate offset in range [-1020, 1020] and a multiple of 4. |
| 1669 | if (!Memory.OffsetImm) return true; |
| 1670 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1671 | int64_t Val = CE->getValue(); |
| 1672 | return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || |
| 1673 | Val == std::numeric_limits<int32_t>::min(); |
| 1674 | } |
| 1675 | return false; |
| 1676 | } |
| 1677 | |
| 1678 | bool isAddrMode5FP16() const { |
| 1679 | // If we have an immediate that's not a constant, treat it as a label |
| 1680 | // reference needing a fixup. If it is a constant, it's something else |
| 1681 | // and we reject it. |
| 1682 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1683 | return true; |
| 1684 | if (!isGPRMem() || Memory.Alignment != 0) return false; |
| 1685 | // Check for register offset. |
| 1686 | if (Memory.OffsetRegNum) return false; |
| 1687 | // Immediate offset in range [-510, 510] and a multiple of 2. |
| 1688 | if (!Memory.OffsetImm) return true; |
| 1689 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1690 | int64_t Val = CE->getValue(); |
| 1691 | return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || |
| 1692 | Val == std::numeric_limits<int32_t>::min(); |
| 1693 | } |
| 1694 | return false; |
| 1695 | } |
| 1696 | |
| 1697 | bool isMemTBB() const { |
| 1698 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || |
| 1699 | Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) |
| 1700 | return false; |
| 1701 | return true; |
| 1702 | } |
| 1703 | |
| 1704 | bool isMemTBH() const { |
| 1705 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || |
| 1706 | Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || |
| 1707 | Memory.Alignment != 0 ) |
| 1708 | return false; |
| 1709 | return true; |
| 1710 | } |
| 1711 | |
| 1712 | bool isMemRegOffset() const { |
| 1713 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) |
| 1714 | return false; |
| 1715 | return true; |
| 1716 | } |
| 1717 | |
| 1718 | bool isT2MemRegOffset() const { |
| 1719 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || |
| 1720 | Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) |
| 1721 | return false; |
| 1722 | // Only lsl #{0, 1, 2, 3} allowed. |
| 1723 | if (Memory.ShiftType == ARM_AM::no_shift) |
| 1724 | return true; |
| 1725 | if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) |
| 1726 | return false; |
| 1727 | return true; |
| 1728 | } |
| 1729 | |
| 1730 | bool isMemThumbRR() const { |
| 1731 | // Thumb reg+reg addressing is simple. Just two registers, a base and |
| 1732 | // an offset. No shifts, negations or any other complicating factors. |
| 1733 | if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || |
| 1734 | Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) |
| 1735 | return false; |
| 1736 | return isARMLowRegister(Memory.BaseRegNum) && |
| 1737 | (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); |
| 1738 | } |
| 1739 | |
| 1740 | bool isMemThumbRIs4() const { |
| 1741 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || |
| 1742 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) |
| 1743 | return false; |
| 1744 | // Immediate offset, multiple of 4 in range [0, 124]. |
| 1745 | if (!Memory.OffsetImm) return true; |
| 1746 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1747 | int64_t Val = CE->getValue(); |
| 1748 | return Val >= 0 && Val <= 124 && (Val % 4) == 0; |
| 1749 | } |
| 1750 | return false; |
| 1751 | } |
| 1752 | |
| 1753 | bool isMemThumbRIs2() const { |
| 1754 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || |
| 1755 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) |
| 1756 | return false; |
| 1757 | // Immediate offset, multiple of 4 in range [0, 62]. |
| 1758 | if (!Memory.OffsetImm) return true; |
| 1759 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1760 | int64_t Val = CE->getValue(); |
| 1761 | return Val >= 0 && Val <= 62 && (Val % 2) == 0; |
| 1762 | } |
| 1763 | return false; |
| 1764 | } |
| 1765 | |
| 1766 | bool isMemThumbRIs1() const { |
| 1767 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || |
| 1768 | !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) |
| 1769 | return false; |
| 1770 | // Immediate offset in range [0, 31]. |
| 1771 | if (!Memory.OffsetImm) return true; |
| 1772 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1773 | int64_t Val = CE->getValue(); |
| 1774 | return Val >= 0 && Val <= 31; |
| 1775 | } |
| 1776 | return false; |
| 1777 | } |
| 1778 | |
| 1779 | bool isMemThumbSPI() const { |
| 1780 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || |
| 1781 | Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) |
| 1782 | return false; |
| 1783 | // Immediate offset, multiple of 4 in range [0, 1020]. |
| 1784 | if (!Memory.OffsetImm) return true; |
| 1785 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1786 | int64_t Val = CE->getValue(); |
| 1787 | return Val >= 0 && Val <= 1020 && (Val % 4) == 0; |
| 1788 | } |
| 1789 | return false; |
| 1790 | } |
| 1791 | |
| 1792 | bool isMemImm8s4Offset() const { |
| 1793 | // If we have an immediate that's not a constant, treat it as a label |
| 1794 | // reference needing a fixup. If it is a constant, it's something else |
| 1795 | // and we reject it. |
| 1796 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1797 | return true; |
| 1798 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1799 | return false; |
| 1800 | // Immediate offset a multiple of 4 in range [-1020, 1020]. |
| 1801 | if (!Memory.OffsetImm) return true; |
| 1802 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1803 | int64_t Val = CE->getValue(); |
| 1804 | // Special case, #-0 is std::numeric_limits<int32_t>::min(). |
| 1805 | return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || |
| 1806 | Val == std::numeric_limits<int32_t>::min(); |
| 1807 | } |
| 1808 | return false; |
| 1809 | } |
| 1810 | |
| 1811 | bool isMemImm7s4Offset() const { |
| 1812 | // If we have an immediate that's not a constant, treat it as a label |
| 1813 | // reference needing a fixup. If it is a constant, it's something else |
| 1814 | // and we reject it. |
| 1815 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1816 | return true; |
| 1817 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || |
| 1818 | !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( |
| 1819 | Memory.BaseRegNum)) |
| 1820 | return false; |
| 1821 | // Immediate offset a multiple of 4 in range [-508, 508]. |
| 1822 | if (!Memory.OffsetImm) return true; |
| 1823 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1824 | int64_t Val = CE->getValue(); |
| 1825 | // Special case, #-0 is INT32_MIN. |
| 1826 | return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN(-2147483647-1); |
| 1827 | } |
| 1828 | return false; |
| 1829 | } |
| 1830 | |
| 1831 | bool isMemImm0_1020s4Offset() const { |
| 1832 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1833 | return false; |
| 1834 | // Immediate offset a multiple of 4 in range [0, 1020]. |
| 1835 | if (!Memory.OffsetImm) return true; |
| 1836 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1837 | int64_t Val = CE->getValue(); |
| 1838 | return Val >= 0 && Val <= 1020 && (Val & 3) == 0; |
| 1839 | } |
| 1840 | return false; |
| 1841 | } |
| 1842 | |
| 1843 | bool isMemImm8Offset() const { |
| 1844 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1845 | return false; |
| 1846 | // Base reg of PC isn't allowed for these encodings. |
| 1847 | if (Memory.BaseRegNum == ARM::PC) return false; |
| 1848 | // Immediate offset in range [-255, 255]. |
| 1849 | if (!Memory.OffsetImm) return true; |
| 1850 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1851 | int64_t Val = CE->getValue(); |
| 1852 | return (Val == std::numeric_limits<int32_t>::min()) || |
| 1853 | (Val > -256 && Val < 256); |
| 1854 | } |
| 1855 | return false; |
| 1856 | } |
| 1857 | |
| 1858 | template<unsigned Bits, unsigned RegClassID> |
| 1859 | bool isMemImm7ShiftedOffset() const { |
| 1860 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || |
| 1861 | !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) |
| 1862 | return false; |
| 1863 | |
| 1864 | // Expect an immediate offset equal to an element of the range |
| 1865 | // [-127, 127], shifted left by Bits. |
| 1866 | |
| 1867 | if (!Memory.OffsetImm) return true; |
| 1868 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1869 | int64_t Val = CE->getValue(); |
| 1870 | |
| 1871 | // INT32_MIN is a special-case value (indicating the encoding with |
| 1872 | // zero offset and the subtract bit set) |
| 1873 | if (Val == INT32_MIN(-2147483647-1)) |
| 1874 | return true; |
| 1875 | |
| 1876 | unsigned Divisor = 1U << Bits; |
| 1877 | |
| 1878 | // Check that the low bits are zero |
| 1879 | if (Val % Divisor != 0) |
| 1880 | return false; |
| 1881 | |
| 1882 | // Check that the remaining offset is within range. |
| 1883 | Val /= Divisor; |
| 1884 | return (Val >= -127 && Val <= 127); |
| 1885 | } |
| 1886 | return false; |
| 1887 | } |
| 1888 | |
| 1889 | template <int shift> bool isMemRegRQOffset() const { |
| 1890 | if (!isMVEMem() || Memory.OffsetImm != nullptr || Memory.Alignment != 0) |
| 1891 | return false; |
| 1892 | |
| 1893 | if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( |
| 1894 | Memory.BaseRegNum)) |
| 1895 | return false; |
| 1896 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( |
| 1897 | Memory.OffsetRegNum)) |
| 1898 | return false; |
| 1899 | |
| 1900 | if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) |
| 1901 | return false; |
| 1902 | |
| 1903 | if (shift > 0 && |
| 1904 | (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) |
| 1905 | return false; |
| 1906 | |
| 1907 | return true; |
| 1908 | } |
| 1909 | |
| 1910 | template <int shift> bool isMemRegQOffset() const { |
| 1911 | if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1912 | return false; |
| 1913 | |
| 1914 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( |
| 1915 | Memory.BaseRegNum)) |
| 1916 | return false; |
| 1917 | |
| 1918 | if (!Memory.OffsetImm) |
| 1919 | return true; |
| 1920 | static_assert(shift < 56, |
| 1921 | "Such that we dont shift by a value higher than 62"); |
| 1922 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1923 | int64_t Val = CE->getValue(); |
| 1924 | |
| 1925 | // The value must be a multiple of (1 << shift) |
| 1926 | if ((Val & ((1U << shift) - 1)) != 0) |
| 1927 | return false; |
| 1928 | |
| 1929 | // And be in the right range, depending on the amount that it is shifted |
| 1930 | // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set |
| 1931 | // separately. |
| 1932 | int64_t Range = (1U << (7 + shift)) - 1; |
| 1933 | return (Val == INT32_MIN(-2147483647-1)) || (Val > -Range && Val < Range); |
| 1934 | } |
| 1935 | return false; |
| 1936 | } |
| 1937 | |
| 1938 | bool isMemPosImm8Offset() const { |
| 1939 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1940 | return false; |
| 1941 | // Immediate offset in range [0, 255]. |
| 1942 | if (!Memory.OffsetImm) return true; |
| 1943 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1944 | int64_t Val = CE->getValue(); |
| 1945 | return Val >= 0 && Val < 256; |
| 1946 | } |
| 1947 | return false; |
| 1948 | } |
| 1949 | |
| 1950 | bool isMemNegImm8Offset() const { |
| 1951 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1952 | return false; |
| 1953 | // Base reg of PC isn't allowed for these encodings. |
| 1954 | if (Memory.BaseRegNum == ARM::PC) return false; |
| 1955 | // Immediate offset in range [-255, -1]. |
| 1956 | if (!Memory.OffsetImm) return false; |
| 1957 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1958 | int64_t Val = CE->getValue(); |
| 1959 | return (Val == std::numeric_limits<int32_t>::min()) || |
| 1960 | (Val > -256 && Val < 0); |
| 1961 | } |
| 1962 | return false; |
| 1963 | } |
| 1964 | |
| 1965 | bool isMemUImm12Offset() const { |
| 1966 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1967 | return false; |
| 1968 | // Immediate offset in range [0, 4095]. |
| 1969 | if (!Memory.OffsetImm) return true; |
| 1970 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1971 | int64_t Val = CE->getValue(); |
| 1972 | return (Val >= 0 && Val < 4096); |
| 1973 | } |
| 1974 | return false; |
| 1975 | } |
| 1976 | |
| 1977 | bool isMemImm12Offset() const { |
| 1978 | // If we have an immediate that's not a constant, treat it as a label |
| 1979 | // reference needing a fixup. If it is a constant, it's something else |
| 1980 | // and we reject it. |
| 1981 | |
| 1982 | if (isImm() && !isa<MCConstantExpr>(getImm())) |
| 1983 | return true; |
| 1984 | |
| 1985 | if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) |
| 1986 | return false; |
| 1987 | // Immediate offset in range [-4095, 4095]. |
| 1988 | if (!Memory.OffsetImm) return true; |
| 1989 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 1990 | int64_t Val = CE->getValue(); |
| 1991 | return (Val > -4096 && Val < 4096) || |
| 1992 | (Val == std::numeric_limits<int32_t>::min()); |
| 1993 | } |
| 1994 | // If we have an immediate that's not a constant, treat it as a |
| 1995 | // symbolic expression needing a fixup. |
| 1996 | return true; |
| 1997 | } |
| 1998 | |
| 1999 | bool isConstPoolAsmImm() const { |
| 2000 | // Delay processing of Constant Pool Immediate, this will turn into |
| 2001 | // a constant. Match no other operand |
| 2002 | return (isConstantPoolImm()); |
| 2003 | } |
| 2004 | |
| 2005 | bool isPostIdxImm8() const { |
| 2006 | if (!isImm()) return false; |
| 2007 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2008 | if (!CE) return false; |
| 2009 | int64_t Val = CE->getValue(); |
| 2010 | return (Val > -256 && Val < 256) || |
| 2011 | (Val == std::numeric_limits<int32_t>::min()); |
| 2012 | } |
| 2013 | |
| 2014 | bool isPostIdxImm8s4() const { |
| 2015 | if (!isImm()) return false; |
| 2016 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2017 | if (!CE) return false; |
| 2018 | int64_t Val = CE->getValue(); |
| 2019 | return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || |
| 2020 | (Val == std::numeric_limits<int32_t>::min()); |
| 2021 | } |
| 2022 | |
| 2023 | bool isMSRMask() const { return Kind == k_MSRMask; } |
| 2024 | bool isBankedReg() const { return Kind == k_BankedReg; } |
| 2025 | bool isProcIFlags() const { return Kind == k_ProcIFlags; } |
| 2026 | |
| 2027 | // NEON operands. |
| 2028 | bool isSingleSpacedVectorList() const { |
| 2029 | return Kind == k_VectorList && !VectorList.isDoubleSpaced; |
| 2030 | } |
| 2031 | |
| 2032 | bool isDoubleSpacedVectorList() const { |
| 2033 | return Kind == k_VectorList && VectorList.isDoubleSpaced; |
| 2034 | } |
| 2035 | |
| 2036 | bool isVecListOneD() const { |
| 2037 | if (!isSingleSpacedVectorList()) return false; |
| 2038 | return VectorList.Count == 1; |
| 2039 | } |
| 2040 | |
| 2041 | bool isVecListTwoMQ() const { |
| 2042 | return isSingleSpacedVectorList() && VectorList.Count == 2 && |
| 2043 | ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( |
| 2044 | VectorList.RegNum); |
| 2045 | } |
| 2046 | |
| 2047 | bool isVecListDPair() const { |
| 2048 | if (!isSingleSpacedVectorList()) return false; |
| 2049 | return (ARMMCRegisterClasses[ARM::DPairRegClassID] |
| 2050 | .contains(VectorList.RegNum)); |
| 2051 | } |
| 2052 | |
| 2053 | bool isVecListThreeD() const { |
| 2054 | if (!isSingleSpacedVectorList()) return false; |
| 2055 | return VectorList.Count == 3; |
| 2056 | } |
| 2057 | |
| 2058 | bool isVecListFourD() const { |
| 2059 | if (!isSingleSpacedVectorList()) return false; |
| 2060 | return VectorList.Count == 4; |
| 2061 | } |
| 2062 | |
| 2063 | bool isVecListDPairSpaced() const { |
| 2064 | if (Kind != k_VectorList) return false; |
| 2065 | if (isSingleSpacedVectorList()) return false; |
| 2066 | return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] |
| 2067 | .contains(VectorList.RegNum)); |
| 2068 | } |
| 2069 | |
| 2070 | bool isVecListThreeQ() const { |
| 2071 | if (!isDoubleSpacedVectorList()) return false; |
| 2072 | return VectorList.Count == 3; |
| 2073 | } |
| 2074 | |
| 2075 | bool isVecListFourQ() const { |
| 2076 | if (!isDoubleSpacedVectorList()) return false; |
| 2077 | return VectorList.Count == 4; |
| 2078 | } |
| 2079 | |
| 2080 | bool isVecListFourMQ() const { |
| 2081 | return isSingleSpacedVectorList() && VectorList.Count == 4 && |
| 2082 | ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( |
| 2083 | VectorList.RegNum); |
| 2084 | } |
| 2085 | |
| 2086 | bool isSingleSpacedVectorAllLanes() const { |
| 2087 | return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; |
| 2088 | } |
| 2089 | |
| 2090 | bool isDoubleSpacedVectorAllLanes() const { |
| 2091 | return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; |
| 2092 | } |
| 2093 | |
| 2094 | bool isVecListOneDAllLanes() const { |
| 2095 | if (!isSingleSpacedVectorAllLanes()) return false; |
| 2096 | return VectorList.Count == 1; |
| 2097 | } |
| 2098 | |
| 2099 | bool isVecListDPairAllLanes() const { |
| 2100 | if (!isSingleSpacedVectorAllLanes()) return false; |
| 2101 | return (ARMMCRegisterClasses[ARM::DPairRegClassID] |
| 2102 | .contains(VectorList.RegNum)); |
| 2103 | } |
| 2104 | |
| 2105 | bool isVecListDPairSpacedAllLanes() const { |
| 2106 | if (!isDoubleSpacedVectorAllLanes()) return false; |
| 2107 | return VectorList.Count == 2; |
| 2108 | } |
| 2109 | |
| 2110 | bool isVecListThreeDAllLanes() const { |
| 2111 | if (!isSingleSpacedVectorAllLanes()) return false; |
| 2112 | return VectorList.Count == 3; |
| 2113 | } |
| 2114 | |
| 2115 | bool isVecListThreeQAllLanes() const { |
| 2116 | if (!isDoubleSpacedVectorAllLanes()) return false; |
| 2117 | return VectorList.Count == 3; |
| 2118 | } |
| 2119 | |
| 2120 | bool isVecListFourDAllLanes() const { |
| 2121 | if (!isSingleSpacedVectorAllLanes()) return false; |
| 2122 | return VectorList.Count == 4; |
| 2123 | } |
| 2124 | |
| 2125 | bool isVecListFourQAllLanes() const { |
| 2126 | if (!isDoubleSpacedVectorAllLanes()) return false; |
| 2127 | return VectorList.Count == 4; |
| 2128 | } |
| 2129 | |
| 2130 | bool isSingleSpacedVectorIndexed() const { |
| 2131 | return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; |
| 2132 | } |
| 2133 | |
| 2134 | bool isDoubleSpacedVectorIndexed() const { |
| 2135 | return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; |
| 2136 | } |
| 2137 | |
| 2138 | bool isVecListOneDByteIndexed() const { |
| 2139 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2140 | return VectorList.Count == 1 && VectorList.LaneIndex <= 7; |
| 2141 | } |
| 2142 | |
| 2143 | bool isVecListOneDHWordIndexed() const { |
| 2144 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2145 | return VectorList.Count == 1 && VectorList.LaneIndex <= 3; |
| 2146 | } |
| 2147 | |
| 2148 | bool isVecListOneDWordIndexed() const { |
| 2149 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2150 | return VectorList.Count == 1 && VectorList.LaneIndex <= 1; |
| 2151 | } |
| 2152 | |
| 2153 | bool isVecListTwoDByteIndexed() const { |
| 2154 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2155 | return VectorList.Count == 2 && VectorList.LaneIndex <= 7; |
| 2156 | } |
| 2157 | |
| 2158 | bool isVecListTwoDHWordIndexed() const { |
| 2159 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2160 | return VectorList.Count == 2 && VectorList.LaneIndex <= 3; |
| 2161 | } |
| 2162 | |
| 2163 | bool isVecListTwoQWordIndexed() const { |
| 2164 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2165 | return VectorList.Count == 2 && VectorList.LaneIndex <= 1; |
| 2166 | } |
| 2167 | |
| 2168 | bool isVecListTwoQHWordIndexed() const { |
| 2169 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2170 | return VectorList.Count == 2 && VectorList.LaneIndex <= 3; |
| 2171 | } |
| 2172 | |
| 2173 | bool isVecListTwoDWordIndexed() const { |
| 2174 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2175 | return VectorList.Count == 2 && VectorList.LaneIndex <= 1; |
| 2176 | } |
| 2177 | |
| 2178 | bool isVecListThreeDByteIndexed() const { |
| 2179 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2180 | return VectorList.Count == 3 && VectorList.LaneIndex <= 7; |
| 2181 | } |
| 2182 | |
| 2183 | bool isVecListThreeDHWordIndexed() const { |
| 2184 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2185 | return VectorList.Count == 3 && VectorList.LaneIndex <= 3; |
| 2186 | } |
| 2187 | |
| 2188 | bool isVecListThreeQWordIndexed() const { |
| 2189 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2190 | return VectorList.Count == 3 && VectorList.LaneIndex <= 1; |
| 2191 | } |
| 2192 | |
| 2193 | bool isVecListThreeQHWordIndexed() const { |
| 2194 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2195 | return VectorList.Count == 3 && VectorList.LaneIndex <= 3; |
| 2196 | } |
| 2197 | |
| 2198 | bool isVecListThreeDWordIndexed() const { |
| 2199 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2200 | return VectorList.Count == 3 && VectorList.LaneIndex <= 1; |
| 2201 | } |
| 2202 | |
| 2203 | bool isVecListFourDByteIndexed() const { |
| 2204 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2205 | return VectorList.Count == 4 && VectorList.LaneIndex <= 7; |
| 2206 | } |
| 2207 | |
| 2208 | bool isVecListFourDHWordIndexed() const { |
| 2209 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2210 | return VectorList.Count == 4 && VectorList.LaneIndex <= 3; |
| 2211 | } |
| 2212 | |
| 2213 | bool isVecListFourQWordIndexed() const { |
| 2214 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2215 | return VectorList.Count == 4 && VectorList.LaneIndex <= 1; |
| 2216 | } |
| 2217 | |
| 2218 | bool isVecListFourQHWordIndexed() const { |
| 2219 | if (!isDoubleSpacedVectorIndexed()) return false; |
| 2220 | return VectorList.Count == 4 && VectorList.LaneIndex <= 3; |
| 2221 | } |
| 2222 | |
| 2223 | bool isVecListFourDWordIndexed() const { |
| 2224 | if (!isSingleSpacedVectorIndexed()) return false; |
| 2225 | return VectorList.Count == 4 && VectorList.LaneIndex <= 1; |
| 2226 | } |
| 2227 | |
| 2228 | bool isVectorIndex() const { return Kind == k_VectorIndex; } |
| 2229 | |
| 2230 | template <unsigned NumLanes> |
| 2231 | bool isVectorIndexInRange() const { |
| 2232 | if (Kind != k_VectorIndex) return false; |
| 2233 | return VectorIndex.Val < NumLanes; |
| 2234 | } |
| 2235 | |
| 2236 | bool isVectorIndex8() const { return isVectorIndexInRange<8>(); } |
| 2237 | bool isVectorIndex16() const { return isVectorIndexInRange<4>(); } |
| 2238 | bool isVectorIndex32() const { return isVectorIndexInRange<2>(); } |
| 2239 | bool isVectorIndex64() const { return isVectorIndexInRange<1>(); } |
| 2240 | |
| 2241 | template<int PermittedValue, int OtherPermittedValue> |
| 2242 | bool isMVEPairVectorIndex() const { |
| 2243 | if (Kind != k_VectorIndex) return false; |
| 2244 | return VectorIndex.Val == PermittedValue || |
| 2245 | VectorIndex.Val == OtherPermittedValue; |
| 2246 | } |
| 2247 | |
| 2248 | bool isNEONi8splat() const { |
| 2249 | if (!isImm()) return false; |
| 2250 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2251 | // Must be a constant. |
| 2252 | if (!CE) return false; |
| 2253 | int64_t Value = CE->getValue(); |
| 2254 | // i8 value splatted across 8 bytes. The immediate is just the 8 byte |
| 2255 | // value. |
| 2256 | return Value >= 0 && Value < 256; |
| 2257 | } |
| 2258 | |
| 2259 | bool isNEONi16splat() const { |
| 2260 | if (isNEONByteReplicate(2)) |
| 2261 | return false; // Leave that for bytes replication and forbid by default. |
| 2262 | if (!isImm()) |
| 2263 | return false; |
| 2264 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2265 | // Must be a constant. |
| 2266 | if (!CE) return false; |
| 2267 | unsigned Value = CE->getValue(); |
| 2268 | return ARM_AM::isNEONi16splat(Value); |
| 2269 | } |
| 2270 | |
| 2271 | bool isNEONi16splatNot() const { |
| 2272 | if (!isImm()) |
| 2273 | return false; |
| 2274 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2275 | // Must be a constant. |
| 2276 | if (!CE) return false; |
| 2277 | unsigned Value = CE->getValue(); |
| 2278 | return ARM_AM::isNEONi16splat(~Value & 0xffff); |
| 2279 | } |
| 2280 | |
| 2281 | bool isNEONi32splat() const { |
| 2282 | if (isNEONByteReplicate(4)) |
| 2283 | return false; // Leave that for bytes replication and forbid by default. |
| 2284 | if (!isImm()) |
| 2285 | return false; |
| 2286 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2287 | // Must be a constant. |
| 2288 | if (!CE) return false; |
| 2289 | unsigned Value = CE->getValue(); |
| 2290 | return ARM_AM::isNEONi32splat(Value); |
| 2291 | } |
| 2292 | |
| 2293 | bool isNEONi32splatNot() const { |
| 2294 | if (!isImm()) |
| 2295 | return false; |
| 2296 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2297 | // Must be a constant. |
| 2298 | if (!CE) return false; |
| 2299 | unsigned Value = CE->getValue(); |
| 2300 | return ARM_AM::isNEONi32splat(~Value); |
| 2301 | } |
| 2302 | |
| 2303 | static bool isValidNEONi32vmovImm(int64_t Value) { |
| 2304 | // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, |
| 2305 | // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. |
| 2306 | return ((Value & 0xffffffffffffff00) == 0) || |
| 2307 | ((Value & 0xffffffffffff00ff) == 0) || |
| 2308 | ((Value & 0xffffffffff00ffff) == 0) || |
| 2309 | ((Value & 0xffffffff00ffffff) == 0) || |
| 2310 | ((Value & 0xffffffffffff00ff) == 0xff) || |
| 2311 | ((Value & 0xffffffffff00ffff) == 0xffff); |
| 2312 | } |
| 2313 | |
| 2314 | bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const { |
| 2315 | assert((Width == 8 || Width == 16 || Width == 32) &&(static_cast <bool> ((Width == 8 || Width == 16 || Width == 32) && "Invalid element width") ? void (0) : __assert_fail ("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2316, __extension__ __PRETTY_FUNCTION__)) |
| 2316 | "Invalid element width")(static_cast <bool> ((Width == 8 || Width == 16 || Width == 32) && "Invalid element width") ? void (0) : __assert_fail ("(Width == 8 || Width == 16 || Width == 32) && \"Invalid element width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2316, __extension__ __PRETTY_FUNCTION__)); |
| 2317 | assert(NumElems * Width <= 64 && "Invalid result width")(static_cast <bool> (NumElems * Width <= 64 && "Invalid result width") ? void (0) : __assert_fail ("NumElems * Width <= 64 && \"Invalid result width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2317, __extension__ __PRETTY_FUNCTION__)); |
| 2318 | |
| 2319 | if (!isImm()) |
| 2320 | return false; |
| 2321 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2322 | // Must be a constant. |
| 2323 | if (!CE) |
| 2324 | return false; |
| 2325 | int64_t Value = CE->getValue(); |
| 2326 | if (!Value) |
| 2327 | return false; // Don't bother with zero. |
| 2328 | if (Inv) |
| 2329 | Value = ~Value; |
| 2330 | |
| 2331 | uint64_t Mask = (1ull << Width) - 1; |
| 2332 | uint64_t Elem = Value & Mask; |
| 2333 | if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0) |
| 2334 | return false; |
| 2335 | if (Width == 32 && !isValidNEONi32vmovImm(Elem)) |
| 2336 | return false; |
| 2337 | |
| 2338 | for (unsigned i = 1; i < NumElems; ++i) { |
| 2339 | Value >>= Width; |
| 2340 | if ((Value & Mask) != Elem) |
| 2341 | return false; |
| 2342 | } |
| 2343 | return true; |
| 2344 | } |
| 2345 | |
| 2346 | bool isNEONByteReplicate(unsigned NumBytes) const { |
| 2347 | return isNEONReplicate(8, NumBytes, false); |
| 2348 | } |
| 2349 | |
| 2350 | static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) { |
| 2351 | assert((FromW == 8 || FromW == 16 || FromW == 32) &&(static_cast <bool> ((FromW == 8 || FromW == 16 || FromW == 32) && "Invalid source width") ? void (0) : __assert_fail ("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2352, __extension__ __PRETTY_FUNCTION__)) |
| 2352 | "Invalid source width")(static_cast <bool> ((FromW == 8 || FromW == 16 || FromW == 32) && "Invalid source width") ? void (0) : __assert_fail ("(FromW == 8 || FromW == 16 || FromW == 32) && \"Invalid source width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2352, __extension__ __PRETTY_FUNCTION__)); |
| 2353 | assert((ToW == 16 || ToW == 32 || ToW == 64) &&(static_cast <bool> ((ToW == 16 || ToW == 32 || ToW == 64 ) && "Invalid destination width") ? void (0) : __assert_fail ("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2354, __extension__ __PRETTY_FUNCTION__)) |
| 2354 | "Invalid destination width")(static_cast <bool> ((ToW == 16 || ToW == 32 || ToW == 64 ) && "Invalid destination width") ? void (0) : __assert_fail ("(ToW == 16 || ToW == 32 || ToW == 64) && \"Invalid destination width\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2354, __extension__ __PRETTY_FUNCTION__)); |
| 2355 | assert(FromW < ToW && "ToW is not less than FromW")(static_cast <bool> (FromW < ToW && "ToW is not less than FromW" ) ? void (0) : __assert_fail ("FromW < ToW && \"ToW is not less than FromW\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2355, __extension__ __PRETTY_FUNCTION__)); |
| 2356 | } |
| 2357 | |
| 2358 | template<unsigned FromW, unsigned ToW> |
| 2359 | bool isNEONmovReplicate() const { |
| 2360 | checkNeonReplicateArgs(FromW, ToW); |
| 2361 | if (ToW == 64 && isNEONi64splat()) |
| 2362 | return false; |
| 2363 | return isNEONReplicate(FromW, ToW / FromW, false); |
| 2364 | } |
| 2365 | |
| 2366 | template<unsigned FromW, unsigned ToW> |
| 2367 | bool isNEONinvReplicate() const { |
| 2368 | checkNeonReplicateArgs(FromW, ToW); |
| 2369 | return isNEONReplicate(FromW, ToW / FromW, true); |
| 2370 | } |
| 2371 | |
| 2372 | bool isNEONi32vmov() const { |
| 2373 | if (isNEONByteReplicate(4)) |
| 2374 | return false; // Let it to be classified as byte-replicate case. |
| 2375 | if (!isImm()) |
| 2376 | return false; |
| 2377 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2378 | // Must be a constant. |
| 2379 | if (!CE) |
| 2380 | return false; |
| 2381 | return isValidNEONi32vmovImm(CE->getValue()); |
| 2382 | } |
| 2383 | |
| 2384 | bool isNEONi32vmovNeg() const { |
| 2385 | if (!isImm()) return false; |
| 2386 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2387 | // Must be a constant. |
| 2388 | if (!CE) return false; |
| 2389 | return isValidNEONi32vmovImm(~CE->getValue()); |
| 2390 | } |
| 2391 | |
| 2392 | bool isNEONi64splat() const { |
| 2393 | if (!isImm()) return false; |
| 2394 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2395 | // Must be a constant. |
| 2396 | if (!CE) return false; |
| 2397 | uint64_t Value = CE->getValue(); |
| 2398 | // i64 value with each byte being either 0 or 0xff. |
| 2399 | for (unsigned i = 0; i < 8; ++i, Value >>= 8) |
| 2400 | if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; |
| 2401 | return true; |
| 2402 | } |
| 2403 | |
| 2404 | template<int64_t Angle, int64_t Remainder> |
| 2405 | bool isComplexRotation() const { |
| 2406 | if (!isImm()) return false; |
| 2407 | |
| 2408 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2409 | if (!CE) return false; |
| 2410 | uint64_t Value = CE->getValue(); |
| 2411 | |
| 2412 | return (Value % Angle == Remainder && Value <= 270); |
| 2413 | } |
| 2414 | |
| 2415 | bool isMVELongShift() const { |
| 2416 | if (!isImm()) return false; |
| 2417 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2418 | // Must be a constant. |
| 2419 | if (!CE) return false; |
| 2420 | uint64_t Value = CE->getValue(); |
| 2421 | return Value >= 1 && Value <= 32; |
| 2422 | } |
| 2423 | |
| 2424 | bool isMveSaturateOp() const { |
| 2425 | if (!isImm()) return false; |
| 2426 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2427 | if (!CE) return false; |
| 2428 | uint64_t Value = CE->getValue(); |
| 2429 | return Value == 48 || Value == 64; |
| 2430 | } |
| 2431 | |
| 2432 | bool isITCondCodeNoAL() const { |
| 2433 | if (!isITCondCode()) return false; |
| 2434 | ARMCC::CondCodes CC = getCondCode(); |
| 2435 | return CC != ARMCC::AL; |
| 2436 | } |
| 2437 | |
| 2438 | bool isITCondCodeRestrictedI() const { |
| 2439 | if (!isITCondCode()) |
| 2440 | return false; |
| 2441 | ARMCC::CondCodes CC = getCondCode(); |
| 2442 | return CC == ARMCC::EQ || CC == ARMCC::NE; |
| 2443 | } |
| 2444 | |
| 2445 | bool isITCondCodeRestrictedS() const { |
| 2446 | if (!isITCondCode()) |
| 2447 | return false; |
| 2448 | ARMCC::CondCodes CC = getCondCode(); |
| 2449 | return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE || |
| 2450 | CC == ARMCC::GE; |
| 2451 | } |
| 2452 | |
| 2453 | bool isITCondCodeRestrictedU() const { |
| 2454 | if (!isITCondCode()) |
| 2455 | return false; |
| 2456 | ARMCC::CondCodes CC = getCondCode(); |
| 2457 | return CC == ARMCC::HS || CC == ARMCC::HI; |
| 2458 | } |
| 2459 | |
| 2460 | bool isITCondCodeRestrictedFP() const { |
| 2461 | if (!isITCondCode()) |
| 2462 | return false; |
| 2463 | ARMCC::CondCodes CC = getCondCode(); |
| 2464 | return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT || |
| 2465 | CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE; |
| 2466 | } |
| 2467 | |
| 2468 | void addExpr(MCInst &Inst, const MCExpr *Expr) const { |
| 2469 | // Add as immediates when possible. Null MCExpr = 0. |
| 2470 | if (!Expr) |
| 2471 | Inst.addOperand(MCOperand::createImm(0)); |
| 2472 | else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) |
| 2473 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2474 | else |
| 2475 | Inst.addOperand(MCOperand::createExpr(Expr)); |
| 2476 | } |
| 2477 | |
| 2478 | void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const { |
| 2479 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2479, __extension__ __PRETTY_FUNCTION__)); |
| 2480 | addExpr(Inst, getImm()); |
| 2481 | } |
| 2482 | |
| 2483 | void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const { |
| 2484 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2484, __extension__ __PRETTY_FUNCTION__)); |
| 2485 | addExpr(Inst, getImm()); |
| 2486 | } |
| 2487 | |
| 2488 | void addCondCodeOperands(MCInst &Inst, unsigned N) const { |
| 2489 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2489, __extension__ __PRETTY_FUNCTION__)); |
| 2490 | Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); |
| 2491 | unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; |
| 2492 | Inst.addOperand(MCOperand::createReg(RegNum)); |
| 2493 | } |
| 2494 | |
| 2495 | void addVPTPredNOperands(MCInst &Inst, unsigned N) const { |
| 2496 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2496, __extension__ __PRETTY_FUNCTION__)); |
| 2497 | Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); |
| 2498 | unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; |
| 2499 | Inst.addOperand(MCOperand::createReg(RegNum)); |
| 2500 | Inst.addOperand(MCOperand::createReg(0)); |
| 2501 | } |
| 2502 | |
| 2503 | void addVPTPredROperands(MCInst &Inst, unsigned N) const { |
| 2504 | assert(N == 4 && "Invalid number of operands!")(static_cast <bool> (N == 4 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 4 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2504, __extension__ __PRETTY_FUNCTION__)); |
| 2505 | addVPTPredNOperands(Inst, N-1); |
| 2506 | unsigned RegNum; |
| 2507 | if (getVPTPred() == ARMVCC::None) { |
| 2508 | RegNum = 0; |
| 2509 | } else { |
| 2510 | unsigned NextOpIndex = Inst.getNumOperands(); |
| 2511 | const MCInstrDesc &MCID = |
| 2512 | ARMDescs.Insts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()]; |
| 2513 | int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); |
| 2514 | assert(TiedOp >= 0 &&(static_cast <bool> (TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!" ) ? void (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2515, __extension__ __PRETTY_FUNCTION__)) |
| 2515 | "Inactive register in vpred_r is not tied to an output!")(static_cast <bool> (TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!" ) ? void (0) : __assert_fail ("TiedOp >= 0 && \"Inactive register in vpred_r is not tied to an output!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2515, __extension__ __PRETTY_FUNCTION__)); |
| 2516 | RegNum = Inst.getOperand(TiedOp).getReg(); |
| 2517 | } |
| 2518 | Inst.addOperand(MCOperand::createReg(RegNum)); |
| 2519 | } |
| 2520 | |
| 2521 | void addCoprocNumOperands(MCInst &Inst, unsigned N) const { |
| 2522 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2522, __extension__ __PRETTY_FUNCTION__)); |
| 2523 | Inst.addOperand(MCOperand::createImm(getCoproc())); |
| 2524 | } |
| 2525 | |
| 2526 | void addCoprocRegOperands(MCInst &Inst, unsigned N) const { |
| 2527 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2527, __extension__ __PRETTY_FUNCTION__)); |
| 2528 | Inst.addOperand(MCOperand::createImm(getCoproc())); |
| 2529 | } |
| 2530 | |
| 2531 | void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { |
| 2532 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2532, __extension__ __PRETTY_FUNCTION__)); |
| 2533 | Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); |
| 2534 | } |
| 2535 | |
| 2536 | void addITMaskOperands(MCInst &Inst, unsigned N) const { |
| 2537 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2537, __extension__ __PRETTY_FUNCTION__)); |
| 2538 | Inst.addOperand(MCOperand::createImm(ITMask.Mask)); |
| 2539 | } |
| 2540 | |
| 2541 | void addITCondCodeOperands(MCInst &Inst, unsigned N) const { |
| 2542 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2542, __extension__ __PRETTY_FUNCTION__)); |
| 2543 | Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); |
| 2544 | } |
| 2545 | |
| 2546 | void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const { |
| 2547 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2547, __extension__ __PRETTY_FUNCTION__)); |
| 2548 | Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); |
| 2549 | } |
| 2550 | |
| 2551 | void addCCOutOperands(MCInst &Inst, unsigned N) const { |
| 2552 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2552, __extension__ __PRETTY_FUNCTION__)); |
| 2553 | Inst.addOperand(MCOperand::createReg(getReg())); |
| 2554 | } |
| 2555 | |
| 2556 | void addRegOperands(MCInst &Inst, unsigned N) const { |
| 2557 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2557, __extension__ __PRETTY_FUNCTION__)); |
| 2558 | Inst.addOperand(MCOperand::createReg(getReg())); |
| 2559 | } |
| 2560 | |
| 2561 | void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { |
| 2562 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2562, __extension__ __PRETTY_FUNCTION__)); |
| 2563 | assert(isRegShiftedReg() &&(static_cast <bool> (isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!" ) ? void (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2564, __extension__ __PRETTY_FUNCTION__)) |
| 2564 | "addRegShiftedRegOperands() on non-RegShiftedReg!")(static_cast <bool> (isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!" ) ? void (0) : __assert_fail ("isRegShiftedReg() && \"addRegShiftedRegOperands() on non-RegShiftedReg!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2564, __extension__ __PRETTY_FUNCTION__)); |
| 2565 | Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); |
| 2566 | Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); |
| 2567 | Inst.addOperand(MCOperand::createImm( |
| 2568 | ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); |
| 2569 | } |
| 2570 | |
| 2571 | void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { |
| 2572 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2572, __extension__ __PRETTY_FUNCTION__)); |
| 2573 | assert(isRegShiftedImm() &&(static_cast <bool> (isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!" ) ? void (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2574, __extension__ __PRETTY_FUNCTION__)) |
| 2574 | "addRegShiftedImmOperands() on non-RegShiftedImm!")(static_cast <bool> (isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!" ) ? void (0) : __assert_fail ("isRegShiftedImm() && \"addRegShiftedImmOperands() on non-RegShiftedImm!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2574, __extension__ __PRETTY_FUNCTION__)); |
| 2575 | Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); |
| 2576 | // Shift of #32 is encoded as 0 where permitted |
| 2577 | unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); |
| 2578 | Inst.addOperand(MCOperand::createImm( |
| 2579 | ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); |
| 2580 | } |
| 2581 | |
| 2582 | void addShifterImmOperands(MCInst &Inst, unsigned N) const { |
| 2583 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2583, __extension__ __PRETTY_FUNCTION__)); |
| 2584 | Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | |
| 2585 | ShifterImm.Imm)); |
| 2586 | } |
| 2587 | |
| 2588 | void addRegListOperands(MCInst &Inst, unsigned N) const { |
| 2589 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2589, __extension__ __PRETTY_FUNCTION__)); |
| 2590 | const SmallVectorImpl<unsigned> &RegList = getRegList(); |
| 2591 | for (unsigned Reg : RegList) |
| 2592 | Inst.addOperand(MCOperand::createReg(Reg)); |
| 2593 | } |
| 2594 | |
| 2595 | void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const { |
| 2596 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2596, __extension__ __PRETTY_FUNCTION__)); |
| 2597 | const SmallVectorImpl<unsigned> &RegList = getRegList(); |
| 2598 | for (unsigned Reg : RegList) |
| 2599 | Inst.addOperand(MCOperand::createReg(Reg)); |
| 2600 | } |
| 2601 | |
| 2602 | void addDPRRegListOperands(MCInst &Inst, unsigned N) const { |
| 2603 | addRegListOperands(Inst, N); |
| 2604 | } |
| 2605 | |
| 2606 | void addSPRRegListOperands(MCInst &Inst, unsigned N) const { |
| 2607 | addRegListOperands(Inst, N); |
| 2608 | } |
| 2609 | |
| 2610 | void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const { |
| 2611 | addRegListOperands(Inst, N); |
| 2612 | } |
| 2613 | |
| 2614 | void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const { |
| 2615 | addRegListOperands(Inst, N); |
| 2616 | } |
| 2617 | |
| 2618 | void addRotImmOperands(MCInst &Inst, unsigned N) const { |
| 2619 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2619, __extension__ __PRETTY_FUNCTION__)); |
| 2620 | // Encoded as val>>3. The printer handles display as 8, 16, 24. |
| 2621 | Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); |
| 2622 | } |
| 2623 | |
| 2624 | void addModImmOperands(MCInst &Inst, unsigned N) const { |
| 2625 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2625, __extension__ __PRETTY_FUNCTION__)); |
| 2626 | |
| 2627 | // Support for fixups (MCFixup) |
| 2628 | if (isImm()) |
| 2629 | return addImmOperands(Inst, N); |
| 2630 | |
| 2631 | Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); |
| 2632 | } |
| 2633 | |
| 2634 | void addModImmNotOperands(MCInst &Inst, unsigned N) const { |
| 2635 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2635, __extension__ __PRETTY_FUNCTION__)); |
| 2636 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2637 | uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); |
| 2638 | Inst.addOperand(MCOperand::createImm(Enc)); |
| 2639 | } |
| 2640 | |
| 2641 | void addModImmNegOperands(MCInst &Inst, unsigned N) const { |
| 2642 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2642, __extension__ __PRETTY_FUNCTION__)); |
| 2643 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2644 | uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); |
| 2645 | Inst.addOperand(MCOperand::createImm(Enc)); |
| 2646 | } |
| 2647 | |
| 2648 | void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const { |
| 2649 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2649, __extension__ __PRETTY_FUNCTION__)); |
| 2650 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2651 | uint32_t Val = -CE->getValue(); |
| 2652 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2653 | } |
| 2654 | |
| 2655 | void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const { |
| 2656 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2656, __extension__ __PRETTY_FUNCTION__)); |
| 2657 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2658 | uint32_t Val = -CE->getValue(); |
| 2659 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2660 | } |
| 2661 | |
| 2662 | void addBitfieldOperands(MCInst &Inst, unsigned N) const { |
| 2663 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2663, __extension__ __PRETTY_FUNCTION__)); |
| 2664 | // Munge the lsb/width into a bitfield mask. |
| 2665 | unsigned lsb = Bitfield.LSB; |
| 2666 | unsigned width = Bitfield.Width; |
| 2667 | // Make a 32-bit mask w/ the referenced bits clear and all other bits set. |
| 2668 | uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> |
| 2669 | (32 - (lsb + width))); |
| 2670 | Inst.addOperand(MCOperand::createImm(Mask)); |
| 2671 | } |
| 2672 | |
| 2673 | void addImmOperands(MCInst &Inst, unsigned N) const { |
| 2674 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2674, __extension__ __PRETTY_FUNCTION__)); |
| 2675 | addExpr(Inst, getImm()); |
| 2676 | } |
| 2677 | |
| 2678 | void addFBits16Operands(MCInst &Inst, unsigned N) const { |
| 2679 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2679, __extension__ __PRETTY_FUNCTION__)); |
| 2680 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2681 | Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); |
| 2682 | } |
| 2683 | |
| 2684 | void addFBits32Operands(MCInst &Inst, unsigned N) const { |
| 2685 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2685, __extension__ __PRETTY_FUNCTION__)); |
| 2686 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2687 | Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); |
| 2688 | } |
| 2689 | |
| 2690 | void addFPImmOperands(MCInst &Inst, unsigned N) const { |
| 2691 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2691, __extension__ __PRETTY_FUNCTION__)); |
| 2692 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2693 | int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); |
| 2694 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2695 | } |
| 2696 | |
| 2697 | void addImm8s4Operands(MCInst &Inst, unsigned N) const { |
| 2698 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2698, __extension__ __PRETTY_FUNCTION__)); |
| 2699 | // FIXME: We really want to scale the value here, but the LDRD/STRD |
| 2700 | // instruction don't encode operands that way yet. |
| 2701 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2702 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2703 | } |
| 2704 | |
| 2705 | void addImm7s4Operands(MCInst &Inst, unsigned N) const { |
| 2706 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2706, __extension__ __PRETTY_FUNCTION__)); |
| 2707 | // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR |
| 2708 | // instruction don't encode operands that way yet. |
| 2709 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2710 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2711 | } |
| 2712 | |
| 2713 | void addImm7Shift0Operands(MCInst &Inst, unsigned N) const { |
| 2714 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2714, __extension__ __PRETTY_FUNCTION__)); |
| 2715 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2716 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2717 | } |
| 2718 | |
| 2719 | void addImm7Shift1Operands(MCInst &Inst, unsigned N) const { |
| 2720 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2720, __extension__ __PRETTY_FUNCTION__)); |
| 2721 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2722 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2723 | } |
| 2724 | |
| 2725 | void addImm7Shift2Operands(MCInst &Inst, unsigned N) const { |
| 2726 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2726, __extension__ __PRETTY_FUNCTION__)); |
| 2727 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2728 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2729 | } |
| 2730 | |
| 2731 | void addImm7Operands(MCInst &Inst, unsigned N) const { |
| 2732 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2732, __extension__ __PRETTY_FUNCTION__)); |
| 2733 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2734 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2735 | } |
| 2736 | |
| 2737 | void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { |
| 2738 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2738, __extension__ __PRETTY_FUNCTION__)); |
| 2739 | // The immediate is scaled by four in the encoding and is stored |
| 2740 | // in the MCInst as such. Lop off the low two bits here. |
| 2741 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2742 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); |
| 2743 | } |
| 2744 | |
| 2745 | void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { |
| 2746 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2746, __extension__ __PRETTY_FUNCTION__)); |
| 2747 | // The immediate is scaled by four in the encoding and is stored |
| 2748 | // in the MCInst as such. Lop off the low two bits here. |
| 2749 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2750 | Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); |
| 2751 | } |
| 2752 | |
| 2753 | void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { |
| 2754 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2754, __extension__ __PRETTY_FUNCTION__)); |
| 2755 | // The immediate is scaled by four in the encoding and is stored |
| 2756 | // in the MCInst as such. Lop off the low two bits here. |
| 2757 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2758 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); |
| 2759 | } |
| 2760 | |
| 2761 | void addImm1_16Operands(MCInst &Inst, unsigned N) const { |
| 2762 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2762, __extension__ __PRETTY_FUNCTION__)); |
| 2763 | // The constant encodes as the immediate-1, and we store in the instruction |
| 2764 | // the bits as encoded, so subtract off one here. |
| 2765 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2766 | Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); |
| 2767 | } |
| 2768 | |
| 2769 | void addImm1_32Operands(MCInst &Inst, unsigned N) const { |
| 2770 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2770, __extension__ __PRETTY_FUNCTION__)); |
| 2771 | // The constant encodes as the immediate-1, and we store in the instruction |
| 2772 | // the bits as encoded, so subtract off one here. |
| 2773 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2774 | Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); |
| 2775 | } |
| 2776 | |
| 2777 | void addImmThumbSROperands(MCInst &Inst, unsigned N) const { |
| 2778 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2778, __extension__ __PRETTY_FUNCTION__)); |
| 2779 | // The constant encodes as the immediate, except for 32, which encodes as |
| 2780 | // zero. |
| 2781 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2782 | unsigned Imm = CE->getValue(); |
| 2783 | Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); |
| 2784 | } |
| 2785 | |
| 2786 | void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { |
| 2787 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2787, __extension__ __PRETTY_FUNCTION__)); |
| 2788 | // An ASR value of 32 encodes as 0, so that's how we want to add it to |
| 2789 | // the instruction as well. |
| 2790 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2791 | int Val = CE->getValue(); |
| 2792 | Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); |
| 2793 | } |
| 2794 | |
| 2795 | void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { |
| 2796 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2796, __extension__ __PRETTY_FUNCTION__)); |
| 2797 | // The operand is actually a t2_so_imm, but we have its bitwise |
| 2798 | // negation in the assembly source, so twiddle it here. |
| 2799 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2800 | Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue())); |
| 2801 | } |
| 2802 | |
| 2803 | void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { |
| 2804 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2804, __extension__ __PRETTY_FUNCTION__)); |
| 2805 | // The operand is actually a t2_so_imm, but we have its |
| 2806 | // negation in the assembly source, so twiddle it here. |
| 2807 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2808 | Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); |
| 2809 | } |
| 2810 | |
| 2811 | void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { |
| 2812 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2812, __extension__ __PRETTY_FUNCTION__)); |
| 2813 | // The operand is actually an imm0_4095, but we have its |
| 2814 | // negation in the assembly source, so twiddle it here. |
| 2815 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2816 | Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); |
| 2817 | } |
| 2818 | |
| 2819 | void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { |
| 2820 | if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { |
| 2821 | Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); |
| 2822 | return; |
| 2823 | } |
| 2824 | const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val); |
| 2825 | Inst.addOperand(MCOperand::createExpr(SR)); |
| 2826 | } |
| 2827 | |
| 2828 | void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { |
| 2829 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2829, __extension__ __PRETTY_FUNCTION__)); |
| 2830 | if (isImm()) { |
| 2831 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2832 | if (CE) { |
| 2833 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2834 | return; |
| 2835 | } |
| 2836 | const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val); |
| 2837 | Inst.addOperand(MCOperand::createExpr(SR)); |
| 2838 | return; |
| 2839 | } |
| 2840 | |
| 2841 | assert(isGPRMem() && "Unknown value type!")(static_cast <bool> (isGPRMem() && "Unknown value type!" ) ? void (0) : __assert_fail ("isGPRMem() && \"Unknown value type!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2841, __extension__ __PRETTY_FUNCTION__)); |
| 2842 | assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!")(static_cast <bool> (isa<MCConstantExpr>(Memory.OffsetImm ) && "Unknown value type!") ? void (0) : __assert_fail ("isa<MCConstantExpr>(Memory.OffsetImm) && \"Unknown value type!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2842, __extension__ __PRETTY_FUNCTION__)); |
| 2843 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 2844 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2845 | else |
| 2846 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 2847 | } |
| 2848 | |
| 2849 | void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { |
| 2850 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2850, __extension__ __PRETTY_FUNCTION__)); |
| 2851 | Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); |
| 2852 | } |
| 2853 | |
| 2854 | void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { |
| 2855 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2855, __extension__ __PRETTY_FUNCTION__)); |
| 2856 | Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); |
| 2857 | } |
| 2858 | |
| 2859 | void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { |
| 2860 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2860, __extension__ __PRETTY_FUNCTION__)); |
| 2861 | Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt()))); |
| 2862 | } |
| 2863 | |
| 2864 | void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { |
| 2865 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2865, __extension__ __PRETTY_FUNCTION__)); |
| 2866 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2867 | } |
| 2868 | |
| 2869 | void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const { |
| 2870 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2870, __extension__ __PRETTY_FUNCTION__)); |
| 2871 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2872 | } |
| 2873 | |
| 2874 | void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const { |
| 2875 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2875, __extension__ __PRETTY_FUNCTION__)); |
| 2876 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2877 | } |
| 2878 | |
| 2879 | void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const { |
| 2880 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2880, __extension__ __PRETTY_FUNCTION__)); |
| 2881 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2882 | } |
| 2883 | |
| 2884 | void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { |
| 2885 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2885, __extension__ __PRETTY_FUNCTION__)); |
| 2886 | if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 2887 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 2888 | else |
| 2889 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 2890 | } |
| 2891 | |
| 2892 | void addAdrLabelOperands(MCInst &Inst, unsigned N) const { |
| 2893 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2893, __extension__ __PRETTY_FUNCTION__)); |
| 2894 | assert(isImm() && "Not an immediate!")(static_cast <bool> (isImm() && "Not an immediate!" ) ? void (0) : __assert_fail ("isImm() && \"Not an immediate!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2894, __extension__ __PRETTY_FUNCTION__)); |
| 2895 | |
| 2896 | // If we have an immediate that's not a constant, treat it as a label |
| 2897 | // reference needing a fixup. |
| 2898 | if (!isa<MCConstantExpr>(getImm())) { |
| 2899 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 2900 | return; |
| 2901 | } |
| 2902 | |
| 2903 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 2904 | int Val = CE->getValue(); |
| 2905 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2906 | } |
| 2907 | |
| 2908 | void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { |
| 2909 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2909, __extension__ __PRETTY_FUNCTION__)); |
| 2910 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2911 | Inst.addOperand(MCOperand::createImm(Memory.Alignment)); |
| 2912 | } |
| 2913 | |
| 2914 | void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { |
| 2915 | addAlignedMemoryOperands(Inst, N); |
| 2916 | } |
| 2917 | |
| 2918 | void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { |
| 2919 | addAlignedMemoryOperands(Inst, N); |
| 2920 | } |
| 2921 | |
| 2922 | void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { |
| 2923 | addAlignedMemoryOperands(Inst, N); |
| 2924 | } |
| 2925 | |
| 2926 | void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { |
| 2927 | addAlignedMemoryOperands(Inst, N); |
| 2928 | } |
| 2929 | |
| 2930 | void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { |
| 2931 | addAlignedMemoryOperands(Inst, N); |
| 2932 | } |
| 2933 | |
| 2934 | void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { |
| 2935 | addAlignedMemoryOperands(Inst, N); |
| 2936 | } |
| 2937 | |
| 2938 | void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { |
| 2939 | addAlignedMemoryOperands(Inst, N); |
| 2940 | } |
| 2941 | |
| 2942 | void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { |
| 2943 | addAlignedMemoryOperands(Inst, N); |
| 2944 | } |
| 2945 | |
| 2946 | void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { |
| 2947 | addAlignedMemoryOperands(Inst, N); |
| 2948 | } |
| 2949 | |
| 2950 | void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { |
| 2951 | addAlignedMemoryOperands(Inst, N); |
| 2952 | } |
| 2953 | |
| 2954 | void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { |
| 2955 | addAlignedMemoryOperands(Inst, N); |
| 2956 | } |
| 2957 | |
| 2958 | void addAddrMode2Operands(MCInst &Inst, unsigned N) const { |
| 2959 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2959, __extension__ __PRETTY_FUNCTION__)); |
| 2960 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 2961 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 2962 | if (!Memory.OffsetRegNum) { |
| 2963 | if (!Memory.OffsetImm) |
| 2964 | Inst.addOperand(MCOperand::createImm(0)); |
| 2965 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 2966 | int32_t Val = CE->getValue(); |
| 2967 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 2968 | // Special case for #-0 |
| 2969 | if (Val == std::numeric_limits<int32_t>::min()) |
| 2970 | Val = 0; |
| 2971 | if (Val < 0) |
| 2972 | Val = -Val; |
| 2973 | Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); |
| 2974 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2975 | } else |
| 2976 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 2977 | } else { |
| 2978 | // For register offset, we encode the shift type and negation flag |
| 2979 | // here. |
| 2980 | int32_t Val = |
| 2981 | ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, |
| 2982 | Memory.ShiftImm, Memory.ShiftType); |
| 2983 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2984 | } |
| 2985 | } |
| 2986 | |
| 2987 | void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { |
| 2988 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2988, __extension__ __PRETTY_FUNCTION__)); |
| 2989 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 2990 | assert(CE && "non-constant AM2OffsetImm operand!")(static_cast <bool> (CE && "non-constant AM2OffsetImm operand!" ) ? void (0) : __assert_fail ("CE && \"non-constant AM2OffsetImm operand!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 2990, __extension__ __PRETTY_FUNCTION__)); |
| 2991 | int32_t Val = CE->getValue(); |
| 2992 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 2993 | // Special case for #-0 |
| 2994 | if (Val == std::numeric_limits<int32_t>::min()) Val = 0; |
| 2995 | if (Val < 0) Val = -Val; |
| 2996 | Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); |
| 2997 | Inst.addOperand(MCOperand::createReg(0)); |
| 2998 | Inst.addOperand(MCOperand::createImm(Val)); |
| 2999 | } |
| 3000 | |
| 3001 | void addAddrMode3Operands(MCInst &Inst, unsigned N) const { |
| 3002 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3002, __extension__ __PRETTY_FUNCTION__)); |
| 3003 | // If we have an immediate that's not a constant, treat it as a label |
| 3004 | // reference needing a fixup. If it is a constant, it's something else |
| 3005 | // and we reject it. |
| 3006 | if (isImm()) { |
| 3007 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 3008 | Inst.addOperand(MCOperand::createReg(0)); |
| 3009 | Inst.addOperand(MCOperand::createImm(0)); |
| 3010 | return; |
| 3011 | } |
| 3012 | |
| 3013 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3014 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3015 | if (!Memory.OffsetRegNum) { |
| 3016 | if (!Memory.OffsetImm) |
| 3017 | Inst.addOperand(MCOperand::createImm(0)); |
| 3018 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 3019 | int32_t Val = CE->getValue(); |
| 3020 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 3021 | // Special case for #-0 |
| 3022 | if (Val == std::numeric_limits<int32_t>::min()) |
| 3023 | Val = 0; |
| 3024 | if (Val < 0) |
| 3025 | Val = -Val; |
| 3026 | Val = ARM_AM::getAM3Opc(AddSub, Val); |
| 3027 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3028 | } else |
| 3029 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3030 | } else { |
| 3031 | // For register offset, we encode the shift type and negation flag |
| 3032 | // here. |
| 3033 | int32_t Val = |
| 3034 | ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); |
| 3035 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3036 | } |
| 3037 | } |
| 3038 | |
| 3039 | void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3040 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3040, __extension__ __PRETTY_FUNCTION__)); |
| 3041 | if (Kind == k_PostIndexRegister) { |
| 3042 | int32_t Val = |
| 3043 | ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); |
| 3044 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); |
| 3045 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3046 | return; |
| 3047 | } |
| 3048 | |
| 3049 | // Constant offset. |
| 3050 | const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); |
| 3051 | int32_t Val = CE->getValue(); |
| 3052 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 3053 | // Special case for #-0 |
| 3054 | if (Val == std::numeric_limits<int32_t>::min()) Val = 0; |
| 3055 | if (Val < 0) Val = -Val; |
| 3056 | Val = ARM_AM::getAM3Opc(AddSub, Val); |
| 3057 | Inst.addOperand(MCOperand::createReg(0)); |
| 3058 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3059 | } |
| 3060 | |
| 3061 | void addAddrMode5Operands(MCInst &Inst, unsigned N) const { |
| 3062 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3062, __extension__ __PRETTY_FUNCTION__)); |
| 3063 | // If we have an immediate that's not a constant, treat it as a label |
| 3064 | // reference needing a fixup. If it is a constant, it's something else |
| 3065 | // and we reject it. |
| 3066 | if (isImm()) { |
| 3067 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 3068 | Inst.addOperand(MCOperand::createImm(0)); |
| 3069 | return; |
| 3070 | } |
| 3071 | |
| 3072 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3073 | if (!Memory.OffsetImm) |
| 3074 | Inst.addOperand(MCOperand::createImm(0)); |
| 3075 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 3076 | // The lower two bits are always zero and as such are not encoded. |
| 3077 | int32_t Val = CE->getValue() / 4; |
| 3078 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 3079 | // Special case for #-0 |
| 3080 | if (Val == std::numeric_limits<int32_t>::min()) |
| 3081 | Val = 0; |
| 3082 | if (Val < 0) |
| 3083 | Val = -Val; |
| 3084 | Val = ARM_AM::getAM5Opc(AddSub, Val); |
| 3085 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3086 | } else |
| 3087 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3088 | } |
| 3089 | |
| 3090 | void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const { |
| 3091 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3091, __extension__ __PRETTY_FUNCTION__)); |
| 3092 | // If we have an immediate that's not a constant, treat it as a label |
| 3093 | // reference needing a fixup. If it is a constant, it's something else |
| 3094 | // and we reject it. |
| 3095 | if (isImm()) { |
| 3096 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 3097 | Inst.addOperand(MCOperand::createImm(0)); |
| 3098 | return; |
| 3099 | } |
| 3100 | |
| 3101 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3102 | // The lower bit is always zero and as such is not encoded. |
| 3103 | if (!Memory.OffsetImm) |
| 3104 | Inst.addOperand(MCOperand::createImm(0)); |
| 3105 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) { |
| 3106 | int32_t Val = CE->getValue() / 2; |
| 3107 | ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; |
| 3108 | // Special case for #-0 |
| 3109 | if (Val == std::numeric_limits<int32_t>::min()) |
| 3110 | Val = 0; |
| 3111 | if (Val < 0) |
| 3112 | Val = -Val; |
| 3113 | Val = ARM_AM::getAM5FP16Opc(AddSub, Val); |
| 3114 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3115 | } else |
| 3116 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3117 | } |
| 3118 | |
| 3119 | void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3120 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3120, __extension__ __PRETTY_FUNCTION__)); |
| 3121 | // If we have an immediate that's not a constant, treat it as a label |
| 3122 | // reference needing a fixup. If it is a constant, it's something else |
| 3123 | // and we reject it. |
| 3124 | if (isImm()) { |
| 3125 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 3126 | Inst.addOperand(MCOperand::createImm(0)); |
| 3127 | return; |
| 3128 | } |
| 3129 | |
| 3130 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3131 | addExpr(Inst, Memory.OffsetImm); |
| 3132 | } |
| 3133 | |
| 3134 | void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3135 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3135, __extension__ __PRETTY_FUNCTION__)); |
| 3136 | // If we have an immediate that's not a constant, treat it as a label |
| 3137 | // reference needing a fixup. If it is a constant, it's something else |
| 3138 | // and we reject it. |
| 3139 | if (isImm()) { |
| 3140 | Inst.addOperand(MCOperand::createExpr(getImm())); |
| 3141 | Inst.addOperand(MCOperand::createImm(0)); |
| 3142 | return; |
| 3143 | } |
| 3144 | |
| 3145 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3146 | addExpr(Inst, Memory.OffsetImm); |
| 3147 | } |
| 3148 | |
| 3149 | void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3150 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3150, __extension__ __PRETTY_FUNCTION__)); |
| 3151 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3152 | if (!Memory.OffsetImm) |
| 3153 | Inst.addOperand(MCOperand::createImm(0)); |
| 3154 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 3155 | // The lower two bits are always zero and as such are not encoded. |
| 3156 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); |
| 3157 | else |
| 3158 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3159 | } |
| 3160 | |
| 3161 | void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const { |
| 3162 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3162, __extension__ __PRETTY_FUNCTION__)); |
| 3163 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3164 | addExpr(Inst, Memory.OffsetImm); |
| 3165 | } |
| 3166 | |
| 3167 | void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const { |
| 3168 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3168, __extension__ __PRETTY_FUNCTION__)); |
| 3169 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3170 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3171 | } |
| 3172 | |
| 3173 | void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3174 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3174, __extension__ __PRETTY_FUNCTION__)); |
| 3175 | // If this is an immediate, it's a label reference. |
| 3176 | if (isImm()) { |
| 3177 | addExpr(Inst, getImm()); |
| 3178 | Inst.addOperand(MCOperand::createImm(0)); |
| 3179 | return; |
| 3180 | } |
| 3181 | |
| 3182 | // Otherwise, it's a normal memory reg+offset. |
| 3183 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3184 | addExpr(Inst, Memory.OffsetImm); |
| 3185 | } |
| 3186 | |
| 3187 | void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { |
| 3188 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3188, __extension__ __PRETTY_FUNCTION__)); |
| 3189 | // If this is an immediate, it's a label reference. |
| 3190 | if (isImm()) { |
| 3191 | addExpr(Inst, getImm()); |
| 3192 | Inst.addOperand(MCOperand::createImm(0)); |
| 3193 | return; |
| 3194 | } |
| 3195 | |
| 3196 | // Otherwise, it's a normal memory reg+offset. |
| 3197 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3198 | addExpr(Inst, Memory.OffsetImm); |
| 3199 | } |
| 3200 | |
| 3201 | void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const { |
| 3202 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3202, __extension__ __PRETTY_FUNCTION__)); |
| 3203 | // This is container for the immediate that we will create the constant |
| 3204 | // pool from |
| 3205 | addExpr(Inst, getConstantPoolImm()); |
| 3206 | } |
| 3207 | |
| 3208 | void addMemTBBOperands(MCInst &Inst, unsigned N) const { |
| 3209 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3209, __extension__ __PRETTY_FUNCTION__)); |
| 3210 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3211 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3212 | } |
| 3213 | |
| 3214 | void addMemTBHOperands(MCInst &Inst, unsigned N) const { |
| 3215 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3215, __extension__ __PRETTY_FUNCTION__)); |
| 3216 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3217 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3218 | } |
| 3219 | |
| 3220 | void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { |
| 3221 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3221, __extension__ __PRETTY_FUNCTION__)); |
| 3222 | unsigned Val = |
| 3223 | ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, |
| 3224 | Memory.ShiftImm, Memory.ShiftType); |
| 3225 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3226 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3227 | Inst.addOperand(MCOperand::createImm(Val)); |
| 3228 | } |
| 3229 | |
| 3230 | void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { |
| 3231 | assert(N == 3 && "Invalid number of operands!")(static_cast <bool> (N == 3 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3231, __extension__ __PRETTY_FUNCTION__)); |
| 3232 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3233 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3234 | Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); |
| 3235 | } |
| 3236 | |
| 3237 | void addMemThumbRROperands(MCInst &Inst, unsigned N) const { |
| 3238 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3238, __extension__ __PRETTY_FUNCTION__)); |
| 3239 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3240 | Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); |
| 3241 | } |
| 3242 | |
| 3243 | void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { |
| 3244 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3244, __extension__ __PRETTY_FUNCTION__)); |
| 3245 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3246 | if (!Memory.OffsetImm) |
| 3247 | Inst.addOperand(MCOperand::createImm(0)); |
| 3248 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 3249 | // The lower two bits are always zero and as such are not encoded. |
| 3250 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); |
| 3251 | else |
| 3252 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3253 | } |
| 3254 | |
| 3255 | void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { |
| 3256 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3256, __extension__ __PRETTY_FUNCTION__)); |
| 3257 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3258 | if (!Memory.OffsetImm) |
| 3259 | Inst.addOperand(MCOperand::createImm(0)); |
| 3260 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 3261 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 2)); |
| 3262 | else |
| 3263 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3264 | } |
| 3265 | |
| 3266 | void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { |
| 3267 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3267, __extension__ __PRETTY_FUNCTION__)); |
| 3268 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3269 | addExpr(Inst, Memory.OffsetImm); |
| 3270 | } |
| 3271 | |
| 3272 | void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { |
| 3273 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3273, __extension__ __PRETTY_FUNCTION__)); |
| 3274 | Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); |
| 3275 | if (!Memory.OffsetImm) |
| 3276 | Inst.addOperand(MCOperand::createImm(0)); |
| 3277 | else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) |
| 3278 | // The lower two bits are always zero and as such are not encoded. |
| 3279 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); |
| 3280 | else |
| 3281 | Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm)); |
| 3282 | } |
| 3283 | |
| 3284 | void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { |
| 3285 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3285, __extension__ __PRETTY_FUNCTION__)); |
| 3286 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 3287 | assert(CE && "non-constant post-idx-imm8 operand!")(static_cast <bool> (CE && "non-constant post-idx-imm8 operand!" ) ? void (0) : __assert_fail ("CE && \"non-constant post-idx-imm8 operand!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3287, __extension__ __PRETTY_FUNCTION__)); |
| 3288 | int Imm = CE->getValue(); |
| 3289 | bool isAdd = Imm >= 0; |
| 3290 | if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; |
| 3291 | Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; |
| 3292 | Inst.addOperand(MCOperand::createImm(Imm)); |
| 3293 | } |
| 3294 | |
| 3295 | void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { |
| 3296 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3296, __extension__ __PRETTY_FUNCTION__)); |
| 3297 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); |
| 3298 | assert(CE && "non-constant post-idx-imm8s4 operand!")(static_cast <bool> (CE && "non-constant post-idx-imm8s4 operand!" ) ? void (0) : __assert_fail ("CE && \"non-constant post-idx-imm8s4 operand!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3298, __extension__ __PRETTY_FUNCTION__)); |
| 3299 | int Imm = CE->getValue(); |
| 3300 | bool isAdd = Imm >= 0; |
| 3301 | if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; |
| 3302 | // Immediate is scaled by 4. |
| 3303 | Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; |
| 3304 | Inst.addOperand(MCOperand::createImm(Imm)); |
| 3305 | } |
| 3306 | |
| 3307 | void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { |
| 3308 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3308, __extension__ __PRETTY_FUNCTION__)); |
| 3309 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); |
| 3310 | Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); |
| 3311 | } |
| 3312 | |
| 3313 | void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { |
| 3314 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3314, __extension__ __PRETTY_FUNCTION__)); |
| 3315 | Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); |
| 3316 | // The sign, shift type, and shift amount are encoded in a single operand |
| 3317 | // using the AM2 encoding helpers. |
| 3318 | ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; |
| 3319 | unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, |
| 3320 | PostIdxReg.ShiftTy); |
| 3321 | Inst.addOperand(MCOperand::createImm(Imm)); |
| 3322 | } |
| 3323 | |
| 3324 | void addPowerTwoOperands(MCInst &Inst, unsigned N) const { |
| 3325 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3325, __extension__ __PRETTY_FUNCTION__)); |
| 3326 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3327 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
| 3328 | } |
| 3329 | |
| 3330 | void addMSRMaskOperands(MCInst &Inst, unsigned N) const { |
| 3331 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3331, __extension__ __PRETTY_FUNCTION__)); |
| 3332 | Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); |
| 3333 | } |
| 3334 | |
| 3335 | void addBankedRegOperands(MCInst &Inst, unsigned N) const { |
| 3336 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3336, __extension__ __PRETTY_FUNCTION__)); |
| 3337 | Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); |
| 3338 | } |
| 3339 | |
| 3340 | void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { |
| 3341 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3341, __extension__ __PRETTY_FUNCTION__)); |
| 3342 | Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); |
| 3343 | } |
| 3344 | |
| 3345 | void addVecListOperands(MCInst &Inst, unsigned N) const { |
| 3346 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3346, __extension__ __PRETTY_FUNCTION__)); |
| 3347 | Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); |
| 3348 | } |
| 3349 | |
| 3350 | void addMVEVecListOperands(MCInst &Inst, unsigned N) const { |
| 3351 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3351, __extension__ __PRETTY_FUNCTION__)); |
| 3352 | |
| 3353 | // When we come here, the VectorList field will identify a range |
| 3354 | // of q-registers by its base register and length, and it will |
| 3355 | // have already been error-checked to be the expected length of |
| 3356 | // range and contain only q-regs in the range q0-q7. So we can |
| 3357 | // count on the base register being in the range q0-q6 (for 2 |
| 3358 | // regs) or q0-q4 (for 4) |
| 3359 | // |
| 3360 | // The MVE instructions taking a register range of this kind will |
| 3361 | // need an operand in the MQQPR or MQQQQPR class, representing the |
| 3362 | // entire range as a unit. So we must translate into that class, |
| 3363 | // by finding the index of the base register in the MQPR reg |
| 3364 | // class, and returning the super-register at the corresponding |
| 3365 | // index in the target class. |
| 3366 | |
| 3367 | const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; |
| 3368 | const MCRegisterClass *RC_out = |
| 3369 | (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID] |
| 3370 | : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID]; |
| 3371 | |
| 3372 | unsigned I, E = RC_out->getNumRegs(); |
| 3373 | for (I = 0; I < E; I++) |
| 3374 | if (RC_in->getRegister(I) == VectorList.RegNum) |
| 3375 | break; |
| 3376 | assert(I < E && "Invalid vector list start register!")(static_cast <bool> (I < E && "Invalid vector list start register!" ) ? void (0) : __assert_fail ("I < E && \"Invalid vector list start register!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3376, __extension__ __PRETTY_FUNCTION__)); |
| 3377 | |
| 3378 | Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I))); |
| 3379 | } |
| 3380 | |
| 3381 | void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { |
| 3382 | assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3382, __extension__ __PRETTY_FUNCTION__)); |
| 3383 | Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); |
| 3384 | Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); |
| 3385 | } |
| 3386 | |
| 3387 | void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { |
| 3388 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3388, __extension__ __PRETTY_FUNCTION__)); |
| 3389 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3390 | } |
| 3391 | |
| 3392 | void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { |
| 3393 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3393, __extension__ __PRETTY_FUNCTION__)); |
| 3394 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3395 | } |
| 3396 | |
| 3397 | void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { |
| 3398 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3398, __extension__ __PRETTY_FUNCTION__)); |
| 3399 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3400 | } |
| 3401 | |
| 3402 | void addVectorIndex64Operands(MCInst &Inst, unsigned N) const { |
| 3403 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3403, __extension__ __PRETTY_FUNCTION__)); |
| 3404 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3405 | } |
| 3406 | |
| 3407 | void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const { |
| 3408 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3408, __extension__ __PRETTY_FUNCTION__)); |
| 3409 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3410 | } |
| 3411 | |
| 3412 | void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const { |
| 3413 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3413, __extension__ __PRETTY_FUNCTION__)); |
| 3414 | Inst.addOperand(MCOperand::createImm(getVectorIndex())); |
| 3415 | } |
| 3416 | |
| 3417 | void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { |
| 3418 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3418, __extension__ __PRETTY_FUNCTION__)); |
| 3419 | // The immediate encodes the type of constant as well as the value. |
| 3420 | // Mask in that this is an i8 splat. |
| 3421 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3422 | Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); |
| 3423 | } |
| 3424 | |
| 3425 | void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { |
| 3426 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3426, __extension__ __PRETTY_FUNCTION__)); |
| 3427 | // The immediate encodes the type of constant as well as the value. |
| 3428 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3429 | unsigned Value = CE->getValue(); |
| 3430 | Value = ARM_AM::encodeNEONi16splat(Value); |
| 3431 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3432 | } |
| 3433 | |
| 3434 | void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { |
| 3435 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3435, __extension__ __PRETTY_FUNCTION__)); |
| 3436 | // The immediate encodes the type of constant as well as the value. |
| 3437 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3438 | unsigned Value = CE->getValue(); |
| 3439 | Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); |
| 3440 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3441 | } |
| 3442 | |
| 3443 | void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { |
| 3444 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3444, __extension__ __PRETTY_FUNCTION__)); |
| 3445 | // The immediate encodes the type of constant as well as the value. |
| 3446 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3447 | unsigned Value = CE->getValue(); |
| 3448 | Value = ARM_AM::encodeNEONi32splat(Value); |
| 3449 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3450 | } |
| 3451 | |
| 3452 | void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { |
| 3453 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3453, __extension__ __PRETTY_FUNCTION__)); |
| 3454 | // The immediate encodes the type of constant as well as the value. |
| 3455 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3456 | unsigned Value = CE->getValue(); |
| 3457 | Value = ARM_AM::encodeNEONi32splat(~Value); |
| 3458 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3459 | } |
| 3460 | |
| 3461 | void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const { |
| 3462 | // The immediate encodes the type of constant as well as the value. |
| 3463 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3464 | assert((Inst.getOpcode() == ARM::VMOVv8i8 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3467, __extension__ __PRETTY_FUNCTION__)) |
| 3465 | Inst.getOpcode() == ARM::VMOVv16i8) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3467, __extension__ __PRETTY_FUNCTION__)) |
| 3466 | "All instructions that wants to replicate non-zero byte "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3467, __extension__ __PRETTY_FUNCTION__)) |
| 3467 | "always must be replaced with VMOVv8i8 or VMOVv16i8.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8.") ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && \"All instructions that wants to replicate non-zero byte \" \"always must be replaced with VMOVv8i8 or VMOVv16i8.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3467, __extension__ __PRETTY_FUNCTION__)); |
| 3468 | unsigned Value = CE->getValue(); |
| 3469 | if (Inv) |
| 3470 | Value = ~Value; |
| 3471 | unsigned B = Value & 0xff; |
| 3472 | B |= 0xe00; // cmode = 0b1110 |
| 3473 | Inst.addOperand(MCOperand::createImm(B)); |
| 3474 | } |
| 3475 | |
| 3476 | void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const { |
| 3477 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3477, __extension__ __PRETTY_FUNCTION__)); |
| 3478 | addNEONi8ReplicateOperands(Inst, true); |
| 3479 | } |
| 3480 | |
| 3481 | static unsigned encodeNeonVMOVImmediate(unsigned Value) { |
| 3482 | if (Value >= 256 && Value <= 0xffff) |
| 3483 | Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); |
| 3484 | else if (Value > 0xffff && Value <= 0xffffff) |
| 3485 | Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); |
| 3486 | else if (Value > 0xffffff) |
| 3487 | Value = (Value >> 24) | 0x600; |
| 3488 | return Value; |
| 3489 | } |
| 3490 | |
| 3491 | void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { |
| 3492 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3492, __extension__ __PRETTY_FUNCTION__)); |
| 3493 | // The immediate encodes the type of constant as well as the value. |
| 3494 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3495 | unsigned Value = encodeNeonVMOVImmediate(CE->getValue()); |
| 3496 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3497 | } |
| 3498 | |
| 3499 | void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const { |
| 3500 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3500, __extension__ __PRETTY_FUNCTION__)); |
| 3501 | addNEONi8ReplicateOperands(Inst, false); |
| 3502 | } |
| 3503 | |
| 3504 | void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const { |
| 3505 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3505, __extension__ __PRETTY_FUNCTION__)); |
| 3506 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3507 | assert((Inst.getOpcode() == ARM::VMOVv4i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)) |
| 3508 | Inst.getOpcode() == ARM::VMOVv8i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)) |
| 3509 | Inst.getOpcode() == ARM::VMVNv4i16 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)) |
| 3510 | Inst.getOpcode() == ARM::VMVNv8i16) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)) |
| 3511 | "All instructions that want to replicate non-zero half-word "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)) |
| 3512 | "always must be replaced with V{MOV,MVN}v{4,8}i16.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16.") ? void ( 0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && \"All instructions that want to replicate non-zero half-word \" \"always must be replaced with V{MOV,MVN}v{4,8}i16.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3512, __extension__ __PRETTY_FUNCTION__)); |
| 3513 | uint64_t Value = CE->getValue(); |
| 3514 | unsigned Elem = Value & 0xffff; |
| 3515 | if (Elem >= 256) |
| 3516 | Elem = (Elem >> 8) | 0x200; |
| 3517 | Inst.addOperand(MCOperand::createImm(Elem)); |
| 3518 | } |
| 3519 | |
| 3520 | void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { |
| 3521 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3521, __extension__ __PRETTY_FUNCTION__)); |
| 3522 | // The immediate encodes the type of constant as well as the value. |
| 3523 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3524 | unsigned Value = encodeNeonVMOVImmediate(~CE->getValue()); |
| 3525 | Inst.addOperand(MCOperand::createImm(Value)); |
| 3526 | } |
| 3527 | |
| 3528 | void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const { |
| 3529 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3529, __extension__ __PRETTY_FUNCTION__)); |
| 3530 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3531 | assert((Inst.getOpcode() == ARM::VMOVv2i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)) |
| 3532 | Inst.getOpcode() == ARM::VMOVv4i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)) |
| 3533 | Inst.getOpcode() == ARM::VMVNv2i32 ||(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)) |
| 3534 | Inst.getOpcode() == ARM::VMVNv4i32) &&(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)) |
| 3535 | "All instructions that want to replicate non-zero word "(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)) |
| 3536 | "always must be replaced with V{MOV,MVN}v{2,4}i32.")(static_cast <bool> ((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32." ) ? void (0) : __assert_fail ("(Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && \"All instructions that want to replicate non-zero word \" \"always must be replaced with V{MOV,MVN}v{2,4}i32.\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3536, __extension__ __PRETTY_FUNCTION__)); |
| 3537 | uint64_t Value = CE->getValue(); |
| 3538 | unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff); |
| 3539 | Inst.addOperand(MCOperand::createImm(Elem)); |
| 3540 | } |
| 3541 | |
| 3542 | void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { |
| 3543 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3543, __extension__ __PRETTY_FUNCTION__)); |
| 3544 | // The immediate encodes the type of constant as well as the value. |
| 3545 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3546 | uint64_t Value = CE->getValue(); |
| 3547 | unsigned Imm = 0; |
| 3548 | for (unsigned i = 0; i < 8; ++i, Value >>= 8) { |
| 3549 | Imm |= (Value & 1) << i; |
| 3550 | } |
| 3551 | Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); |
| 3552 | } |
| 3553 | |
| 3554 | void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const { |
| 3555 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3555, __extension__ __PRETTY_FUNCTION__)); |
| 3556 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3557 | Inst.addOperand(MCOperand::createImm(CE->getValue() / 90)); |
| 3558 | } |
| 3559 | |
| 3560 | void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const { |
| 3561 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3561, __extension__ __PRETTY_FUNCTION__)); |
| 3562 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3563 | Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180)); |
| 3564 | } |
| 3565 | |
| 3566 | void addMveSaturateOperands(MCInst &Inst, unsigned N) const { |
| 3567 | assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!" ) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3567, __extension__ __PRETTY_FUNCTION__)); |
| 3568 | const MCConstantExpr *CE = cast<MCConstantExpr>(getImm()); |
| 3569 | unsigned Imm = CE->getValue(); |
| 3570 | assert((Imm == 48 || Imm == 64) && "Invalid saturate operand")(static_cast <bool> ((Imm == 48 || Imm == 64) && "Invalid saturate operand") ? void (0) : __assert_fail ("(Imm == 48 || Imm == 64) && \"Invalid saturate operand\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3570, __extension__ __PRETTY_FUNCTION__)); |
| 3571 | Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0)); |
| 3572 | } |
| 3573 | |
| 3574 | void print(raw_ostream &OS) const override; |
| 3575 | |
| 3576 | static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { |
| 3577 | auto Op = std::make_unique<ARMOperand>(k_ITCondMask); |
| 3578 | Op->ITMask.Mask = Mask; |
| 3579 | Op->StartLoc = S; |
| 3580 | Op->EndLoc = S; |
| 3581 | return Op; |
| 3582 | } |
| 3583 | |
| 3584 | static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, |
| 3585 | SMLoc S) { |
| 3586 | auto Op = std::make_unique<ARMOperand>(k_CondCode); |
| 3587 | Op->CC.Val = CC; |
| 3588 | Op->StartLoc = S; |
| 3589 | Op->EndLoc = S; |
| 3590 | return Op; |
| 3591 | } |
| 3592 | |
| 3593 | static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC, |
| 3594 | SMLoc S) { |
| 3595 | auto Op = std::make_unique<ARMOperand>(k_VPTPred); |
| 3596 | Op->VCC.Val = CC; |
| 3597 | Op->StartLoc = S; |
| 3598 | Op->EndLoc = S; |
| 3599 | return Op; |
| 3600 | } |
| 3601 | |
| 3602 | static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { |
| 3603 | auto Op = std::make_unique<ARMOperand>(k_CoprocNum); |
| 3604 | Op->Cop.Val = CopVal; |
| 3605 | Op->StartLoc = S; |
| 3606 | Op->EndLoc = S; |
| 3607 | return Op; |
| 3608 | } |
| 3609 | |
| 3610 | static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { |
| 3611 | auto Op = std::make_unique<ARMOperand>(k_CoprocReg); |
| 3612 | Op->Cop.Val = CopVal; |
| 3613 | Op->StartLoc = S; |
| 3614 | Op->EndLoc = S; |
| 3615 | return Op; |
| 3616 | } |
| 3617 | |
| 3618 | static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, |
| 3619 | SMLoc E) { |
| 3620 | auto Op = std::make_unique<ARMOperand>(k_CoprocOption); |
| 3621 | Op->Cop.Val = Val; |
| 3622 | Op->StartLoc = S; |
| 3623 | Op->EndLoc = E; |
| 3624 | return Op; |
| 3625 | } |
| 3626 | |
| 3627 | static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { |
| 3628 | auto Op = std::make_unique<ARMOperand>(k_CCOut); |
| 3629 | Op->Reg.RegNum = RegNum; |
| 3630 | Op->StartLoc = S; |
| 3631 | Op->EndLoc = S; |
| 3632 | return Op; |
| 3633 | } |
| 3634 | |
| 3635 | static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { |
| 3636 | auto Op = std::make_unique<ARMOperand>(k_Token); |
| 3637 | Op->Tok.Data = Str.data(); |
| 3638 | Op->Tok.Length = Str.size(); |
| 3639 | Op->StartLoc = S; |
| 3640 | Op->EndLoc = S; |
| 3641 | return Op; |
| 3642 | } |
| 3643 | |
| 3644 | static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, |
| 3645 | SMLoc E) { |
| 3646 | auto Op = std::make_unique<ARMOperand>(k_Register); |
| 3647 | Op->Reg.RegNum = RegNum; |
| 3648 | Op->StartLoc = S; |
| 3649 | Op->EndLoc = E; |
| 3650 | return Op; |
| 3651 | } |
| 3652 | |
| 3653 | static std::unique_ptr<ARMOperand> |
| 3654 | CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, |
| 3655 | unsigned ShiftReg, unsigned ShiftImm, SMLoc S, |
| 3656 | SMLoc E) { |
| 3657 | auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister); |
| 3658 | Op->RegShiftedReg.ShiftTy = ShTy; |
| 3659 | Op->RegShiftedReg.SrcReg = SrcReg; |
| 3660 | Op->RegShiftedReg.ShiftReg = ShiftReg; |
| 3661 | Op->RegShiftedReg.ShiftImm = ShiftImm; |
| 3662 | Op->StartLoc = S; |
| 3663 | Op->EndLoc = E; |
| 3664 | return Op; |
| 3665 | } |
| 3666 | |
| 3667 | static std::unique_ptr<ARMOperand> |
| 3668 | CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, |
| 3669 | unsigned ShiftImm, SMLoc S, SMLoc E) { |
| 3670 | auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate); |
| 3671 | Op->RegShiftedImm.ShiftTy = ShTy; |
| 3672 | Op->RegShiftedImm.SrcReg = SrcReg; |
| 3673 | Op->RegShiftedImm.ShiftImm = ShiftImm; |
| 3674 | Op->StartLoc = S; |
| 3675 | Op->EndLoc = E; |
| 3676 | return Op; |
| 3677 | } |
| 3678 | |
| 3679 | static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, |
| 3680 | SMLoc S, SMLoc E) { |
| 3681 | auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate); |
| 3682 | Op->ShifterImm.isASR = isASR; |
| 3683 | Op->ShifterImm.Imm = Imm; |
| 3684 | Op->StartLoc = S; |
| 3685 | Op->EndLoc = E; |
| 3686 | return Op; |
| 3687 | } |
| 3688 | |
| 3689 | static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, |
| 3690 | SMLoc E) { |
| 3691 | auto Op = std::make_unique<ARMOperand>(k_RotateImmediate); |
| 3692 | Op->RotImm.Imm = Imm; |
| 3693 | Op->StartLoc = S; |
| 3694 | Op->EndLoc = E; |
| 3695 | return Op; |
| 3696 | } |
| 3697 | |
| 3698 | static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, |
| 3699 | SMLoc S, SMLoc E) { |
| 3700 | auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate); |
| 3701 | Op->ModImm.Bits = Bits; |
| 3702 | Op->ModImm.Rot = Rot; |
| 3703 | Op->StartLoc = S; |
| 3704 | Op->EndLoc = E; |
| 3705 | return Op; |
| 3706 | } |
| 3707 | |
| 3708 | static std::unique_ptr<ARMOperand> |
| 3709 | CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) { |
| 3710 | auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate); |
| 3711 | Op->Imm.Val = Val; |
| 3712 | Op->StartLoc = S; |
| 3713 | Op->EndLoc = E; |
| 3714 | return Op; |
| 3715 | } |
| 3716 | |
| 3717 | static std::unique_ptr<ARMOperand> |
| 3718 | CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { |
| 3719 | auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor); |
| 3720 | Op->Bitfield.LSB = LSB; |
| 3721 | Op->Bitfield.Width = Width; |
| 3722 | Op->StartLoc = S; |
| 3723 | Op->EndLoc = E; |
| 3724 | return Op; |
| 3725 | } |
| 3726 | |
| 3727 | static std::unique_ptr<ARMOperand> |
| 3728 | CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, |
| 3729 | SMLoc StartLoc, SMLoc EndLoc) { |
| 3730 | assert(Regs.size() > 0 && "RegList contains no registers?")(static_cast <bool> (Regs.size() > 0 && "RegList contains no registers?" ) ? void (0) : __assert_fail ("Regs.size() > 0 && \"RegList contains no registers?\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3730, __extension__ __PRETTY_FUNCTION__)); |
| 3731 | KindTy Kind = k_RegisterList; |
| 3732 | |
| 3733 | if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( |
| 3734 | Regs.front().second)) { |
| 3735 | if (Regs.back().second == ARM::VPR) |
| 3736 | Kind = k_FPDRegisterListWithVPR; |
| 3737 | else |
| 3738 | Kind = k_DPRRegisterList; |
| 3739 | } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( |
| 3740 | Regs.front().second)) { |
| 3741 | if (Regs.back().second == ARM::VPR) |
| 3742 | Kind = k_FPSRegisterListWithVPR; |
| 3743 | else |
| 3744 | Kind = k_SPRRegisterList; |
| 3745 | } |
| 3746 | |
| 3747 | if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) |
| 3748 | Kind = k_RegisterListWithAPSR; |
| 3749 | |
| 3750 | assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding")(static_cast <bool> (llvm::is_sorted(Regs) && "Register list must be sorted by encoding" ) ? void (0) : __assert_fail ("llvm::is_sorted(Regs) && \"Register list must be sorted by encoding\"" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3750, __extension__ __PRETTY_FUNCTION__)); |
| 3751 | |
| 3752 | auto Op = std::make_unique<ARMOperand>(Kind); |
| 3753 | for (const auto &P : Regs) |
| 3754 | Op->Registers.push_back(P.second); |
| 3755 | |
| 3756 | Op->StartLoc = StartLoc; |
| 3757 | Op->EndLoc = EndLoc; |
| 3758 | return Op; |
| 3759 | } |
| 3760 | |
| 3761 | static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, |
| 3762 | unsigned Count, |
| 3763 | bool isDoubleSpaced, |
| 3764 | SMLoc S, SMLoc E) { |
| 3765 | auto Op = std::make_unique<ARMOperand>(k_VectorList); |
| 3766 | Op->VectorList.RegNum = RegNum; |
| 3767 | Op->VectorList.Count = Count; |
| 3768 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; |
| 3769 | Op->StartLoc = S; |
| 3770 | Op->EndLoc = E; |
| 3771 | return Op; |
| 3772 | } |
| 3773 | |
| 3774 | static std::unique_ptr<ARMOperand> |
| 3775 | CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, |
| 3776 | SMLoc S, SMLoc E) { |
| 3777 | auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes); |
| 3778 | Op->VectorList.RegNum = RegNum; |
| 3779 | Op->VectorList.Count = Count; |
| 3780 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; |
| 3781 | Op->StartLoc = S; |
| 3782 | Op->EndLoc = E; |
| 3783 | return Op; |
| 3784 | } |
| 3785 | |
| 3786 | static std::unique_ptr<ARMOperand> |
| 3787 | CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, |
| 3788 | bool isDoubleSpaced, SMLoc S, SMLoc E) { |
| 3789 | auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed); |
| 3790 | Op->VectorList.RegNum = RegNum; |
| 3791 | Op->VectorList.Count = Count; |
| 3792 | Op->VectorList.LaneIndex = Index; |
| 3793 | Op->VectorList.isDoubleSpaced = isDoubleSpaced; |
| 3794 | Op->StartLoc = S; |
| 3795 | Op->EndLoc = E; |
| 3796 | return Op; |
| 3797 | } |
| 3798 | |
| 3799 | static std::unique_ptr<ARMOperand> |
| 3800 | CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { |
| 3801 | auto Op = std::make_unique<ARMOperand>(k_VectorIndex); |
| 3802 | Op->VectorIndex.Val = Idx; |
| 3803 | Op->StartLoc = S; |
| 3804 | Op->EndLoc = E; |
| 3805 | return Op; |
| 3806 | } |
| 3807 | |
| 3808 | static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, |
| 3809 | SMLoc E) { |
| 3810 | auto Op = std::make_unique<ARMOperand>(k_Immediate); |
| 3811 | Op->Imm.Val = Val; |
| 3812 | Op->StartLoc = S; |
| 3813 | Op->EndLoc = E; |
| 3814 | return Op; |
| 3815 | } |
| 3816 | |
| 3817 | static std::unique_ptr<ARMOperand> |
| 3818 | CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum, |
| 3819 | ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, |
| 3820 | bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) { |
| 3821 | auto Op = std::make_unique<ARMOperand>(k_Memory); |
| 3822 | Op->Memory.BaseRegNum = BaseRegNum; |
| 3823 | Op->Memory.OffsetImm = OffsetImm; |
| 3824 | Op->Memory.OffsetRegNum = OffsetRegNum; |
| 3825 | Op->Memory.ShiftType = ShiftType; |
| 3826 | Op->Memory.ShiftImm = ShiftImm; |
| 3827 | Op->Memory.Alignment = Alignment; |
| 3828 | Op->Memory.isNegative = isNegative; |
| 3829 | Op->StartLoc = S; |
| 3830 | Op->EndLoc = E; |
| 3831 | Op->AlignmentLoc = AlignmentLoc; |
| 3832 | return Op; |
| 3833 | } |
| 3834 | |
| 3835 | static std::unique_ptr<ARMOperand> |
| 3836 | CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, |
| 3837 | unsigned ShiftImm, SMLoc S, SMLoc E) { |
| 3838 | auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister); |
| 3839 | Op->PostIdxReg.RegNum = RegNum; |
| 3840 | Op->PostIdxReg.isAdd = isAdd; |
| 3841 | Op->PostIdxReg.ShiftTy = ShiftTy; |
| 3842 | Op->PostIdxReg.ShiftImm = ShiftImm; |
| 3843 | Op->StartLoc = S; |
| 3844 | Op->EndLoc = E; |
| 3845 | return Op; |
| 3846 | } |
| 3847 | |
| 3848 | static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, |
| 3849 | SMLoc S) { |
| 3850 | auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt); |
| 3851 | Op->MBOpt.Val = Opt; |
| 3852 | Op->StartLoc = S; |
| 3853 | Op->EndLoc = S; |
| 3854 | return Op; |
| 3855 | } |
| 3856 | |
| 3857 | static std::unique_ptr<ARMOperand> |
| 3858 | CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { |
| 3859 | auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt); |
| 3860 | Op->ISBOpt.Val = Opt; |
| 3861 | Op->StartLoc = S; |
| 3862 | Op->EndLoc = S; |
| 3863 | return Op; |
| 3864 | } |
| 3865 | |
| 3866 | static std::unique_ptr<ARMOperand> |
| 3867 | CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) { |
| 3868 | auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt); |
| 3869 | Op->TSBOpt.Val = Opt; |
| 3870 | Op->StartLoc = S; |
| 3871 | Op->EndLoc = S; |
| 3872 | return Op; |
| 3873 | } |
| 3874 | |
| 3875 | static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, |
| 3876 | SMLoc S) { |
| 3877 | auto Op = std::make_unique<ARMOperand>(k_ProcIFlags); |
| 3878 | Op->IFlags.Val = IFlags; |
| 3879 | Op->StartLoc = S; |
| 3880 | Op->EndLoc = S; |
| 3881 | return Op; |
| 3882 | } |
| 3883 | |
| 3884 | static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { |
| 3885 | auto Op = std::make_unique<ARMOperand>(k_MSRMask); |
| 3886 | Op->MMask.Val = MMask; |
| 3887 | Op->StartLoc = S; |
| 3888 | Op->EndLoc = S; |
| 3889 | return Op; |
| 3890 | } |
| 3891 | |
| 3892 | static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { |
| 3893 | auto Op = std::make_unique<ARMOperand>(k_BankedReg); |
| 3894 | Op->BankedReg.Val = Reg; |
| 3895 | Op->StartLoc = S; |
| 3896 | Op->EndLoc = S; |
| 3897 | return Op; |
| 3898 | } |
| 3899 | }; |
| 3900 | |
| 3901 | } // end anonymous namespace. |
| 3902 | |
| 3903 | void ARMOperand::print(raw_ostream &OS) const { |
| 3904 | auto RegName = [](MCRegister Reg) { |
| 3905 | if (Reg) |
| 3906 | return ARMInstPrinter::getRegisterName(Reg); |
| 3907 | else |
| 3908 | return "noreg"; |
| 3909 | }; |
| 3910 | |
| 3911 | switch (Kind) { |
| 3912 | case k_CondCode: |
| 3913 | OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; |
| 3914 | break; |
| 3915 | case k_VPTPred: |
| 3916 | OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">"; |
| 3917 | break; |
| 3918 | case k_CCOut: |
| 3919 | OS << "<ccout " << RegName(getReg()) << ">"; |
| 3920 | break; |
| 3921 | case k_ITCondMask: { |
| 3922 | static const char *const MaskStr[] = { |
| 3923 | "(invalid)", "(tttt)", "(ttt)", "(ttte)", |
| 3924 | "(tt)", "(ttet)", "(tte)", "(ttee)", |
| 3925 | "(t)", "(tett)", "(tet)", "(tete)", |
| 3926 | "(te)", "(teet)", "(tee)", "(teee)", |
| 3927 | }; |
| 3928 | assert((ITMask.Mask & 0xf) == ITMask.Mask)(static_cast <bool> ((ITMask.Mask & 0xf) == ITMask. Mask) ? void (0) : __assert_fail ("(ITMask.Mask & 0xf) == ITMask.Mask" , "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp", 3928, __extension__ __PRETTY_FUNCTION__)); |
| 3929 | OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; |
| 3930 | break; |
| 3931 | } |
| 3932 | case k_CoprocNum: |
| 3933 | OS << "<coprocessor number: " << getCoproc() << ">"; |
| 3934 | break; |
| 3935 | case k_CoprocReg: |
| 3936 | OS << "<coprocessor register: " << getCoproc() << ">"; |
| 3937 | break; |
| 3938 | case k_CoprocOption: |
| 3939 | OS << "<coprocessor option: " << CoprocOption.Val << ">"; |
| 3940 | break; |
| 3941 | case k_MSRMask: |
| 3942 | OS << "<mask: " << getMSRMask() << ">"; |
| 3943 | break; |
| 3944 | case k_BankedReg: |
| 3945 | OS << "<banked reg: " << getBankedReg() << ">"; |
| 3946 | break; |
| 3947 | case k_Immediate: |
| 3948 | OS << *getImm(); |
| 3949 | break; |
| 3950 | case k_MemBarrierOpt: |
| 3951 | OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; |
| 3952 | break; |
| 3953 | case k_InstSyncBarrierOpt: |
| 3954 | OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; |
| 3955 | break; |
| 3956 | case k_TraceSyncBarrierOpt: |
| 3957 | OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">"; |
| 3958 | break; |
| 3959 | case k_Memory: |
| 3960 | OS << "<memory"; |
| 3961 | if (Memory.BaseRegNum) |
| 3962 | OS << " base:" << RegName(Memory.BaseRegNum); |
| 3963 | if (Memory.OffsetImm) |
| 3964 | OS << " offset-imm:" << *Memory.OffsetImm; |
| 3965 | if (Memory.OffsetRegNum) |
| 3966 | OS << " offset-reg:" << (Memory.isNegative ? "-" : "") |
| 3967 | << RegName(Memory.OffsetRegNum); |
| 3968 | if (Memory.ShiftType != ARM_AM::no_shift) { |
| 3969 | OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType); |
| 3970 | OS << " shift-imm:" << Memory.ShiftImm; |
| 3971 | } |
| 3972 | if (Memory.Alignment) |
| 3973 | OS << " alignment:" << Memory.Alignment; |
| 3974 | OS << ">"; |
| 3975 | break; |
| 3976 | case k_PostIndexRegister: |
| 3977 | OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") |
| 3978 | << RegName(PostIdxReg.RegNum); |
| 3979 | if (PostIdxReg.ShiftTy != ARM_AM::no_shift) |
| 3980 | OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " |
| 3981 | << PostIdxReg.ShiftImm; |
| 3982 | OS << ">"; |
| 3983 | break; |
| 3984 | case k_ProcIFlags: { |
| 3985 | OS << "<ARM_PROC::"; |
| 3986 | unsigned IFlags = getProcIFlags(); |
| 3987 | for (int i=2; i >= 0; --i) |
| 3988 | if (IFlags & (1 << i)) |
| 3989 | OS << ARM_PROC::IFlagsToString(1 << i); |
| 3990 | OS << ">"; |
| 3991 | break; |
| 3992 | } |
| 3993 | case k_Register: |
| 3994 | OS << "<register " << RegName(getReg()) << ">"; |
| 3995 | break; |
| 3996 | case k_ShifterImmediate: |
| 3997 | OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") |
| 3998 | << " #" << ShifterImm.Imm << ">"; |
| 3999 | break; |
| 4000 | case k_ShiftedRegister: |
| 4001 | OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " " |
| 4002 | << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " " |
| 4003 | << RegName(RegShiftedReg.ShiftReg) << ">"; |
| 4004 | break; |
| 4005 | case k_ShiftedImmediate: |
| 4006 | OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " " |
| 4007 | << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #" |
| 4008 | << RegShiftedImm.ShiftImm << ">"; |
| 4009 | break; |
| 4010 | case k_RotateImmediate: |
| 4011 | OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; |
| 4012 | break; |
| 4013 | case k_ModifiedImmediate: |
| 4014 | OS << "<mod_imm #" << ModImm.Bits << ", #" |
| 4015 | << ModImm.Rot << ")>"; |
| 4016 | break; |
| 4017 | case k_ConstantPoolImmediate: |
| 4018 | OS << "<constant_pool_imm #" << *getConstantPoolImm(); |
| 4019 | break; |
| 4020 | case k_BitfieldDescriptor: |
| 4021 | OS << "<bitfield " << "lsb: " << Bitfield.LSB |
| 4022 | << ", width: " << Bitfield.Width << ">"; |
| 4023 | break; |
| 4024 | case k_RegisterList: |
| 4025 | case k_RegisterListWithAPSR: |
| 4026 | case k_DPRRegisterList: |
| 4027 | case k_SPRRegisterList: |
| 4028 | case k_FPSRegisterListWithVPR: |
| 4029 | case k_FPDRegisterListWithVPR: { |
| 4030 | OS << "<register_list "; |
| 4031 | |
| 4032 | const SmallVectorImpl<unsigned> &RegList = getRegList(); |
| 4033 | for (SmallVectorImpl<unsigned>::const_iterator |
| 4034 | I = RegList.begin(), E = RegList.end(); I != E; ) { |
| 4035 | OS << RegName(*I); |
| 4036 | if (++I < E) OS << ", "; |
| 4037 | } |
| 4038 | |
| 4039 | OS << ">"; |
| 4040 | break; |
| 4041 | } |
| 4042 | case k_VectorList: |
| 4043 | OS << "<vector_list " << VectorList.Count << " * " |
| 4044 | << RegName(VectorList.RegNum) << ">"; |
| 4045 | break; |
| 4046 | case k_VectorListAllLanes: |
| 4047 | OS << "<vector_list(all lanes) " << VectorList.Count << " * " |
| 4048 | << RegName(VectorList.RegNum) << ">"; |
| 4049 | break; |
| 4050 | case k_VectorListIndexed: |
| 4051 | OS << "<vector_list(lane " << VectorList.LaneIndex << ") " |
| 4052 | << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">"; |
| 4053 | break; |
| 4054 | case k_Token: |
| 4055 | OS << "'" << getToken() << "'"; |
| 4056 | break; |
| 4057 | case k_VectorIndex: |
| 4058 | OS << "<vectorindex " << getVectorIndex() << ">"; |
| 4059 | break; |
| 4060 | } |
| 4061 | } |
| 4062 | |
| 4063 | /// @name Auto-generated Match Functions |
| 4064 | /// { |
| 4065 | |
| 4066 | static unsigned MatchRegisterName(StringRef Name); |
| 4067 | |
| 4068 | /// } |
| 4069 | |
| 4070 | bool ARMAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc, |
| 4071 | SMLoc &EndLoc) { |
| 4072 | const AsmToken &Tok = getParser().getTok(); |
| 4073 | StartLoc = Tok.getLoc(); |
| 4074 | EndLoc = Tok.getEndLoc(); |
| 4075 | RegNo = tryParseRegister(); |
| 4076 | |
| 4077 | return (RegNo == (unsigned)-1); |
| 4078 | } |
| 4079 | |
| 4080 | OperandMatchResultTy ARMAsmParser::tryParseRegister(MCRegister &RegNo, |
| 4081 | SMLoc &StartLoc, |
| 4082 | SMLoc &EndLoc) { |
| 4083 | if (parseRegister(RegNo, StartLoc, EndLoc)) |
| 4084 | return MatchOperand_NoMatch; |
| 4085 | return MatchOperand_Success; |
| 4086 | } |
| 4087 | |
| 4088 | /// Try to parse a register name. The token must be an Identifier when called, |
| 4089 | /// and if it is a register name the token is eaten and the register number is |
| 4090 | /// returned. Otherwise return -1. |
| 4091 | int ARMAsmParser::tryParseRegister() { |
| 4092 | MCAsmParser &Parser = getParser(); |
| 4093 | const AsmToken &Tok = Parser.getTok(); |
| 4094 | if (Tok.isNot(AsmToken::Identifier)) return -1; |
| 4095 | |
| 4096 | std::string lowerCase = Tok.getString().lower(); |
| 4097 | unsigned RegNum = MatchRegisterName(lowerCase); |
| 4098 | if (!RegNum) { |
| 4099 | RegNum = StringSwitch<unsigned>(lowerCase) |
| 4100 | .Case("r13", ARM::SP) |
| 4101 | .Case("r14", ARM::LR) |
| 4102 | .Case("r15", ARM::PC) |
| 4103 | .Case("ip", ARM::R12) |
| 4104 | // Additional register name aliases for 'gas' compatibility. |
| 4105 | .Case("a1", ARM::R0) |
| 4106 | .Case("a2", ARM::R1) |
| 4107 | .Case("a3", ARM::R2) |
| 4108 | .Case("a4", ARM::R3) |
| 4109 | .Case("v1", ARM::R4) |
| 4110 | .Case("v2", ARM::R5) |
| 4111 | .Case("v3", ARM::R6) |
| 4112 | .Case("v4", ARM::R7) |
| 4113 | .Case("v5", ARM::R8) |
| 4114 | .Case("v6", ARM::R9) |
| 4115 | .Case("v7", ARM::R10) |
| 4116 | .Case("v8", ARM::R11) |
| 4117 | .Case("sb", ARM::R9) |
| 4118 | .Case("sl", ARM::R10) |
| 4119 | .Case("fp", ARM::R11) |
| 4120 | .Default(0); |
| 4121 | } |
| 4122 | if (!RegNum) { |
| 4123 | // Check for aliases registered via .req. Canonicalize to lower case. |
| 4124 | // That's more consistent since register names are case insensitive, and |
| 4125 | // it's how the original entry was passed in from MC/MCParser/AsmParser. |
| 4126 | StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); |
| 4127 | // If no match, return failure. |
| 4128 | if (Entry == RegisterReqs.end()) |
| 4129 | return -1; |
| 4130 | Parser.Lex(); // Eat identifier token. |
| 4131 | return Entry->getValue(); |
| 4132 | } |
| 4133 | |
| 4134 | // Some FPUs only have 16 D registers, so D16-D31 are invalid |
| 4135 | if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) |
| 4136 | return -1; |
| 4137 | |
| 4138 | Parser.Lex(); // Eat identifier token. |
| 4139 | |
| 4140 | return RegNum; |
| 4141 | } |
| 4142 | |
| 4143 | // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. |
| 4144 | // If a recoverable error occurs, return 1. If an irrecoverable error |
| 4145 | // occurs, return -1. An irrecoverable error is one where tokens have been |
| 4146 | // consumed in the process of trying to parse the shifter (i.e., when it is |
| 4147 | // indeed a shifter operand, but malformed). |
| 4148 | int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { |
| 4149 | MCAsmParser &Parser = getParser(); |
| 4150 | SMLoc S = Parser.getTok().getLoc(); |
| 4151 | const AsmToken &Tok = Parser.getTok(); |
| 4152 | if (Tok.isNot(AsmToken::Identifier)) |
| 4153 | return -1; |
| 4154 | |
| 4155 | std::string lowerCase = Tok.getString().lower(); |
| 4156 | ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) |
| 4157 | .Case("asl", ARM_AM::lsl) |
| 4158 | .Case("lsl", ARM_AM::lsl) |
| 4159 | .Case("lsr", ARM_AM::lsr) |
| 4160 | .Case("asr", ARM_AM::asr) |
| 4161 | .Case("ror", ARM_AM::ror) |
| 4162 | .Case("rrx", ARM_AM::rrx) |
| 4163 | .Default(ARM_AM::no_shift); |
| 4164 | |
| 4165 | if (ShiftTy == ARM_AM::no_shift) |
| 4166 | return 1; |
| 4167 | |
| 4168 | Parser.Lex(); // Eat the operator. |
| 4169 | |
| 4170 | // The source register for the shift has already been added to the |
| 4171 | // operand list, so we need to pop it off and combine it into the shifted |
| 4172 | // register operand instead. |
| 4173 | std::unique_ptr<ARMOperand> PrevOp( |
| 4174 | (ARMOperand *)Operands.pop_back_val().release()); |
| 4175 | if (!PrevOp->isReg()) |
| 4176 | return Error(PrevOp->getStartLoc(), "shift must be of a register"); |
| 4177 | int SrcReg = PrevOp->getReg(); |
| 4178 | |
| 4179 | SMLoc EndLoc; |
| 4180 | int64_t Imm = 0; |
| 4181 | int ShiftReg = 0; |
| 4182 | if (ShiftTy == ARM_AM::rrx) { |
| 4183 | // RRX Doesn't have an explicit shift amount. The encoder expects |
| 4184 | // the shift register to be the same as the source register. Seems odd, |
| 4185 | // but OK. |
| 4186 | ShiftReg = SrcReg; |
| 4187 | } else { |
| 4188 | // Figure out if this is shifted by a constant or a register (for non-RRX). |
| 4189 | if (Parser.getTok().is(AsmToken::Hash) || |
| 4190 | Parser.getTok().is(AsmToken::Dollar)) { |
| 4191 | Parser.Lex(); // Eat hash. |
| 4192 | SMLoc ImmLoc = Parser.getTok().getLoc(); |
| 4193 | const MCExpr *ShiftExpr = nullptr; |
| 4194 | if (getParser().parseExpression(ShiftExpr, EndLoc)) { |
| 4195 | Error(ImmLoc, "invalid immediate shift value"); |
| 4196 | return -1; |
| 4197 | } |
| 4198 | // The expression must be evaluatable as an immediate. |
| 4199 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); |
| 4200 | if (!CE) { |
| 4201 | Error(ImmLoc, "invalid immediate shift value"); |
| 4202 | return -1; |
| 4203 | } |
| 4204 | // Range check the immediate. |
| 4205 | // lsl, ror: 0 <= imm <= 31 |
| 4206 | // lsr, asr: 0 <= imm <= 32 |
| 4207 | Imm = CE->getValue(); |
| 4208 | if (Imm < 0 || |
| 4209 | ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || |
| 4210 | ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { |
| 4211 | Error(ImmLoc, "immediate shift value out of range"); |
| 4212 | return -1; |
| 4213 | } |
| 4214 | // shift by zero is a nop. Always send it through as lsl. |
| 4215 | // ('as' compatibility) |
| 4216 | if (Imm == 0) |
| 4217 | ShiftTy = ARM_AM::lsl; |
| 4218 | } else if (Parser.getTok().is(AsmToken::Identifier)) { |
| 4219 | SMLoc L = Parser.getTok().getLoc(); |
| 4220 | EndLoc = Parser.getTok().getEndLoc(); |
| 4221 | ShiftReg = tryParseRegister(); |
| 4222 | if (ShiftReg == -1) { |
| 4223 | Error(L, "expected immediate or register in shift operand"); |
| 4224 | return -1; |
| 4225 | } |
| 4226 | } else { |
| 4227 | Error(Parser.getTok().getLoc(), |
| 4228 | "expected immediate or register in shift operand"); |
| 4229 | return -1; |
| 4230 | } |
| 4231 | } |
| 4232 | |
| 4233 | if (ShiftReg && ShiftTy != ARM_AM::rrx) |
| 4234 | Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, |
| 4235 | ShiftReg, Imm, |
| 4236 | S, EndLoc)); |
| 4237 | else |
| 4238 | Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, |
| 4239 | S, EndLoc)); |
| 4240 | |
| 4241 | return 0; |
| 4242 | } |
| 4243 | |
| 4244 | /// Try to parse a register name. The token must be an Identifier when called. |
| 4245 | /// If it's a register, an AsmOperand is created. Another AsmOperand is created |
| 4246 | /// if there is a "writeback". 'true' if it's not a register. |
| 4247 | /// |
| 4248 | /// TODO this is likely to change to allow different register types and or to |
| 4249 | /// parse for a specific register type. |
| 4250 | bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { |
| 4251 | MCAsmParser &Parser = getParser(); |
| 4252 | SMLoc RegStartLoc = Parser.getTok().getLoc(); |
| 4253 | SMLoc RegEndLoc = Parser.getTok().getEndLoc(); |
| 4254 | int RegNo = tryParseRegister(); |
| 4255 | if (RegNo == -1) |
| 4256 | return true; |
| 4257 | |
| 4258 | Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); |
| 4259 | |
| 4260 | const AsmToken &ExclaimTok = Parser.getTok(); |
| 4261 | if (ExclaimTok.is(AsmToken::Exclaim)) { |
| 4262 | Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), |
| 4263 | ExclaimTok.getLoc())); |
| 4264 | Parser.Lex(); // Eat exclaim token |
| 4265 | return false; |
| 4266 | } |
| 4267 | |
| 4268 | // Also check for an index operand. This is only legal for vector registers, |
| 4269 | // but that'll get caught OK in operand matching, so we don't need to |
| 4270 | // explicitly filter everything else out here. |
| 4271 | if (Parser.getTok().is(AsmToken::LBrac)) { |
| 4272 | SMLoc SIdx = Parser.getTok().getLoc(); |
| 4273 | Parser.Lex(); // Eat left bracket token. |
| 4274 | |
| 4275 | const MCExpr *ImmVal; |
| 4276 | if (getParser().parseExpression(ImmVal)) |
| 4277 | return true; |
| 4278 | const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); |
| 4279 | if (!MCE) |
| 4280 | return TokError("immediate value expected for vector index"); |
| 4281 | |
| 4282 | if (Parser.getTok().isNot(AsmToken::RBrac)) |
| 4283 | return Error(Parser.getTok().getLoc(), "']' expected"); |
| 4284 | |
| 4285 | SMLoc E = Parser.getTok().getEndLoc(); |
| 4286 | Parser.Lex(); // Eat right bracket token. |
| 4287 | |
| 4288 | Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), |
| 4289 | SIdx, E, |
| 4290 | getContext())); |
| 4291 | } |
| 4292 | |
| 4293 | return false; |
| 4294 | } |
| 4295 | |
| 4296 | /// MatchCoprocessorOperandName - Try to parse an coprocessor related |
| 4297 | /// instruction with a symbolic operand name. |
| 4298 | /// We accept "crN" syntax for GAS compatibility. |
| 4299 | /// <operand-name> ::= <prefix><number> |
| 4300 | /// If CoprocOp is 'c', then: |
| 4301 | /// <prefix> ::= c | cr |
| 4302 | /// If CoprocOp is 'p', then : |
| 4303 | /// <prefix> ::= p |
| 4304 | /// <number> ::= integer in range [0, 15] |
| 4305 | static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { |
| 4306 | // Use the same layout as the tablegen'erated register name matcher. Ugly, |
| 4307 | // but efficient. |
| 4308 | if (Name.size() < 2 || Name[0] != CoprocOp) |
| 4309 | return -1; |
| 4310 | Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); |
| 4311 | |
| 4312 | switch (Name.size()) { |
| 4313 | default: return -1; |
| 4314 | case 1: |
| 4315 | switch (Name[0]) { |
| 4316 | default: return -1; |
| 4317 | case '0': return 0; |
| 4318 | case '1': return 1; |
| 4319 | case '2': return 2; |
| 4320 | case '3': return 3; |
| 4321 | case '4': return 4; |
| 4322 | case '5': return 5; |
| 4323 | case '6': return 6; |
| 4324 | case '7': return 7; |
| 4325 | case '8': return 8; |
| 4326 | case '9': return 9; |
| 4327 | } |
| 4328 | case 2: |
| 4329 | if (Name[0] != '1') |
| 4330 | return -1; |
| 4331 | switch (Name[1]) { |
| 4332 | default: return -1; |
| 4333 | // CP10 and CP11 are VFP/NEON and so vector instructions should be used. |
| 4334 | // However, old cores (v5/v6) did use them in that way. |
| 4335 | case '0': return 10; |
| 4336 | case '1': return 11; |
| 4337 | case '2': return 12; |
| 4338 | case '3': return 13; |
| 4339 | case '4': return 14; |
| 4340 | case '5': return 15; |
| 4341 | } |
| 4342 | } |
| 4343 | } |
| 4344 | |
| 4345 | /// parseITCondCode - Try to parse a condition code for an IT instruction. |
| 4346 | OperandMatchResultTy |
| 4347 | ARMAsmParser::parseITCondCode(OperandVector &Operands) { |
| 4348 | MCAsmParser &Parser = getParser(); |
| 4349 | SMLoc S = Parser.getTok().getLoc(); |
| 4350 | const AsmToken &Tok = Parser.getTok(); |
| 4351 | if (!Tok.is(AsmToken::Identifier)) |
| 4352 | return MatchOperand_NoMatch; |
| 4353 | unsigned CC = ARMCondCodeFromString(Tok.getString()); |
| 4354 | if (CC == ~0U) |
| 4355 | return MatchOperand_NoMatch; |
| 4356 | Parser.Lex(); // Eat the token. |
| 4357 | |
| 4358 | Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); |
| 4359 | |
| 4360 | return MatchOperand_Success; |
| 4361 | } |
| 4362 | |
| 4363 | /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The |
| 4364 | /// token must be an Identifier when called, and if it is a coprocessor |
| 4365 | /// number, the token is eaten and the operand is added to the operand list. |
| 4366 | OperandMatchResultTy |
| 4367 | ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { |
| 4368 | MCAsmParser &Parser = getParser(); |
| 4369 | SMLoc S = Parser.getTok().getLoc(); |
| 4370 | const AsmToken &Tok = Parser.getTok(); |
| 4371 | if (Tok.isNot(AsmToken::Identifier)) |
| 4372 | return MatchOperand_NoMatch; |
| 4373 | |
| 4374 | int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p'); |
| 4375 | if (Num == -1) |
| 4376 | return MatchOperand_NoMatch; |
| 4377 | if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits())) |
| 4378 | return MatchOperand_NoMatch; |
| 4379 | |
| 4380 | Parser.Lex(); // Eat identifier token. |
| 4381 | Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); |
| 4382 | return MatchOperand_Success; |
| 4383 | } |
| 4384 | |
| 4385 | /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The |
| 4386 | /// token must be an Identifier when called, and if it is a coprocessor |
| 4387 | /// number, the token is eaten and the operand is added to the operand list. |
| 4388 | OperandMatchResultTy |
| 4389 | ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { |
| 4390 | MCAsmParser &Parser = getParser(); |
| 4391 | SMLoc S = Parser.getTok().getLoc(); |
| 4392 | const AsmToken &Tok = Parser.getTok(); |
| 4393 | if (Tok.isNot(AsmToken::Identifier)) |
| 4394 | return MatchOperand_NoMatch; |
| 4395 | |
| 4396 | int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c'); |
| 4397 | if (Reg == -1) |
| 4398 | return MatchOperand_NoMatch; |
| 4399 | |
| 4400 | Parser.Lex(); // Eat identifier token. |
| 4401 | Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); |
| 4402 | return MatchOperand_Success; |
| 4403 | } |
| 4404 | |
| 4405 | /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. |
| 4406 | /// coproc_option : '{' imm0_255 '}' |
| 4407 | OperandMatchResultTy |
| 4408 | ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { |
| 4409 | MCAsmParser &Parser = getParser(); |
| 4410 | SMLoc S = Parser.getTok().getLoc(); |
| 4411 | |
| 4412 | // If this isn't a '{', this isn't a coprocessor immediate operand. |
| 4413 | if (Parser.getTok().isNot(AsmToken::LCurly)) |
| 4414 | return MatchOperand_NoMatch; |
| 4415 | Parser.Lex(); // Eat the '{' |
| 4416 | |
| 4417 | const MCExpr *Expr; |
| 4418 | SMLoc Loc = Parser.getTok().getLoc(); |
| 4419 | if (getParser().parseExpression(Expr)) { |
| 4420 | Error(Loc, "illegal expression"); |
| 4421 | return MatchOperand_ParseFail; |
| 4422 | } |
| 4423 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); |
| 4424 | if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { |
| 4425 | Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); |
| 4426 | return MatchOperand_ParseFail; |
| 4427 | } |
| 4428 | int Val = CE->getValue(); |
| 4429 | |
| 4430 | // Check for and consume the closing '}' |
| 4431 | if (Parser.getTok().isNot(AsmToken::RCurly)) |
| 4432 | return MatchOperand_ParseFail; |
| 4433 | SMLoc E = Parser.getTok().getEndLoc(); |
| 4434 | Parser.Lex(); // Eat the '}' |
| 4435 | |
| 4436 | Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); |
| 4437 | return MatchOperand_Success; |
| 4438 | } |
| 4439 | |
| 4440 | // For register list parsing, we need to map from raw GPR register numbering |
| 4441 | // to the enumeration values. The enumeration values aren't sorted by |
| 4442 | // register number due to our using "sp", "lr" and "pc" as canonical names. |
| 4443 | static unsigned getNextRegister(unsigned Reg) { |
| 4444 | // If this is a GPR, we need to do it manually, otherwise we can rely |
| 4445 | // on the sort ordering of the enumeration since the other reg-classes |
| 4446 | // are sane. |
| 4447 | if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) |
| 4448 | return Reg + 1; |
| 4449 | switch(Reg) { |
| 4450 | default: llvm_unreachable("Invalid GPR number!")::llvm::llvm_unreachable_internal("Invalid GPR number!", "llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp" , 4450); |
| 4451 | case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; |
| 4452 | case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; |
| 4453 | case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; |
| 4454 | case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; |
| 4455 | case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; |
| 4456 | case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; |
| 4457 | case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; |
| 4458 | case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; |
| 4459 | } |
| 4460 | } |
| 4461 | |
| 4462 | // Insert an <Encoding, Register> pair in an ordered vector. Return true on |
| 4463 | // success, or false, if duplicate encoding found. |
| 4464 | static bool |
| 4465 | insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, |
| 4466 | unsigned Enc, unsigned Reg) { |
| 4467 | Regs.emplace_back(Enc, Reg); |
| 4468 | for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) { |
| 4469 | if (J->first == Enc) { |
| 4470 | Regs.erase(J.base()); |
| 4471 | return false; |
| 4472 | } |
| 4473 | if (J->first < Enc) |
| 4474 | break; |
| 4475 | std::swap(*I, *J); |
| 4476 | } |
| 4477 | return true; |
| 4478 | } |
| 4479 | |
| 4480 | /// Parse a register list. |
| 4481 | bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder, |
| 4482 | bool AllowRAAC) { |
| 4483 | MCAsmParser &Parser = getParser(); |
| 4484 | if (Parser.getTok().isNot(AsmToken::LCurly)) |
| 4485 | return TokError("Token is not a Left Curly Brace"); |
| 4486 | SMLoc S = Parser.getTok().getLoc(); |
| 4487 | Parser.Lex(); // Eat '{' token. |
| 4488 | SMLoc RegLoc = Parser.getTok().getLoc(); |
| 4489 | |
| 4490 | // Check the first register in the list to see what register class |
| 4491 | // this is a list of. |
| 4492 | int Reg = tryParseRegister(); |
| 4493 | if (Reg == -1) |
| 4494 | return Error(RegLoc, "register expected"); |
| 4495 | if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) |
| 4496 | return Error(RegLoc, "pseudo-register not allowed"); |
| 4497 | // The reglist instructions have at most 16 registers, so reserve |
| 4498 | // space for that many. |
| 4499 | int EReg = 0; |
| 4500 | SmallVector<std::pair<unsigned, unsigned>, 16> Registers; |
| 4501 | |
| 4502 | // Allow Q regs and just interpret them as the two D sub-registers. |
| 4503 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { |
| 4504 | Reg = getDRegFromQReg(Reg); |
| 4505 | EReg = MRI->getEncodingValue(Reg); |
| 4506 | Registers.emplace_back(EReg, Reg); |
| 4507 | ++Reg; |
| 4508 | } |
| 4509 | const MCRegisterClass *RC; |
| 4510 | if (Reg == ARM::RA_AUTH_CODE || |
| 4511 | ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) |
| 4512 | RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; |
| 4513 | else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) |
| 4514 | RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; |
| 4515 | else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) |
| 4516 | RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; |
| 4517 | else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) |
| 4518 | RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; |
| 4519 | else |
| 4520 | return Error(RegLoc, "invalid register in register list"); |
| 4521 | |
| 4522 | // Store the register. |
| 4523 | EReg = MRI->getEncodingValue(Reg); |
| 4524 | Registers.emplace_back(EReg, Reg); |
| 4525 | |
| 4526 | // This starts immediately after the first register token in the list, |
| 4527 | // so we can see either a comma or a minus (range separator) as a legal |
| 4528 | // next token. |
| 4529 | while (Parser.getTok().is(AsmToken::Comma) || |
| 4530 | Parser.getTok().is(AsmToken::Minus)) { |
| 4531 | if (Parser.getTok().is(AsmToken::Minus)) { |
| 4532 | if (Reg == ARM::RA_AUTH_CODE) |
| 4533 | return Error(RegLoc, "pseudo-register not allowed"); |
| 4534 | Parser.Lex(); // Eat the minus. |
| 4535 | SMLoc AfterMinusLoc = Parser.getTok().getLoc(); |
| 4536 | int EndReg = tryParseRegister(); |
| 4537 | if (EndReg == -1) |
| 4538 | return Error(AfterMinusLoc, "register expected"); |
| 4539 | if (EndReg == ARM::RA_AUTH_CODE) |
| 4540 | return Error(AfterMinusLoc, "pseudo-register not allowed"); |
| 4541 | // Allow Q regs and just interpret them as the two D sub-registers. |
| 4542 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) |
| 4543 | EndReg = getDRegFromQReg(EndReg) + 1; |
| 4544 | // If the register is the same as the start reg, there's nothing |
| 4545 | // more to do. |
| 4546 | if (Reg == EndReg) |
| 4547 | continue; |
| 4548 | // The register must be in the same register class as the first. |
| 4549 | if (!RC->contains(Reg)) |
| 4550 | return Error(AfterMinusLoc, "invalid register in register list"); |
| 4551 | // Ranges must go from low to high. |
| 4552 | if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) |
| 4553 | return Error(AfterMinusLoc, "bad range in register list"); |
| 4554 | |
| 4555 | // Add all the registers in the range to the register list. |
| 4556 | while (Reg != EndReg) { |
| 4557 | Reg = getNextRegister(Reg); |
| 4558 | EReg = MRI->getEncodingValue(Reg); |
| 4559 | if (!insertNoDuplicates(Registers, EReg, Reg)) { |
| 4560 | Warning(AfterMinusLoc, StringRef("duplicated register (") + |
| 4561 | ARMInstPrinter::getRegisterName(Reg) + |
| 4562 | ") in register list"); |
| 4563 | } |
| 4564 | } |
| 4565 | continue; |
| 4566 | } |
| 4567 | Parser.Lex(); // Eat the comma. |
| 4568 | RegLoc = Parser.getTok().getLoc(); |
| 4569 | int OldReg = Reg; |
| 4570 | const AsmToken RegTok = Parser.getTok(); |
| 4571 | Reg = tryParseRegister(); |
| 4572 | if (Reg == -1) |
| 4573 | return Error(RegLoc, "register expected"); |
| 4574 | if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) |
| 4575 | return Error(RegLoc, "pseudo-register not allowed"); |
| 4576 | // Allow Q regs and just interpret them as the two D sub-registers. |
| 4577 | bool isQReg = false; |
| 4578 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { |
| 4579 | Reg = getDRegFromQReg(Reg); |
| 4580 | isQReg = true; |
| 4581 | } |
| 4582 | if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) && |
| 4583 | RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && |
| 4584 | ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { |
| 4585 | // switch the register classes, as GPRwithAPSRnospRegClassID is a partial |
| 4586 | // subset of GPRRegClassId except it contains APSR as well. |
| 4587 | RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; |
| 4588 | } |
| 4589 | if (Reg == ARM::VPR && |
| 4590 | (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || |
| 4591 | RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || |
| 4592 | RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { |
| 4593 | RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; |
| 4594 | EReg = MRI->getEncodingValue(Reg); |
| 4595 | if (!insertNoDuplicates(Registers, EReg, Reg)) { |
| 4596 | Warning(RegLoc, "duplicated register (" + RegTok.getString() + |
| 4597 | ") in register list"); |
| 4598 | } |
| 4599 | continue; |
| 4600 | } |
| 4601 | // The register must be in the same register class as the first. |
| 4602 | if ((Reg == ARM::RA_AUTH_CODE && |
| 4603 | RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) || |
| 4604 | (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg))) |
| 4605 | return Error(RegLoc, "invalid register in register list"); |
| 4606 | // In most cases, the list must be monotonically increasing. An |
| 4607 | // exception is CLRM, which is order-independent anyway, so |
| 4608 | // there's no potential for confusion if you write clrm {r2,r1} |
| 4609 | // instead of clrm {r1,r2}. |
| 4610 | if (EnforceOrder && |
| 4611 | MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { |
| 4612 | if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) |
| 4613 | Warning(RegLoc, "register list not in ascending order"); |
| 4614 | else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) |
| 4615 | return Error(RegLoc, "register list not in ascending order"); |
| 4616 | } |
| 4617 | // VFP register lists must also be contiguous. |
| 4618 | if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && |
| 4619 | RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && |
| 4620 | Reg != OldReg + 1) |
| 4621 | return Error(RegLoc, "non-contiguous register range"); |
| 4622 | EReg = MRI->getEncodingValue(Reg); |
| 4623 | if (!insertNoDuplicates(Registers, EReg, Reg)) { |
| 4624 | Warning(RegLoc, "duplicated register (" + RegTok.getString() + |
| 4625 | ") in register list"); |
| 4626 | } |
| 4627 | if (isQReg) { |
| 4628 | EReg = MRI->getEncodingValue(++Reg); |
| 4629 | Registers.emplace_back(EReg, Reg); |
| 4630 | } |
| 4631 | } |
| 4632 | |
| 4633 | if (Parser.getTok().isNot(AsmToken::RCurly)) |
| 4634 | return Error(Parser.getTok().getLoc(), "'}' expected"); |
| 4635 | SMLoc E = Parser.getTok().getEndLoc(); |
| 4636 | Parser.Lex(); // Eat '}' token. |
| 4637 | |
| 4638 | // Push the register list operand. |
| 4639 | Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); |
| 4640 | |
| 4641 | // The ARM system instruction variants for LDM/STM have a '^' token here. |
| 4642 | if (Parser.getTok().is(AsmToken::Caret)) { |
| 4643 | Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); |
| 4644 | Parser.Lex(); // Eat '^' token. |
| 4645 | } |
| 4646 | |
| 4647 | return false; |
| 4648 | } |
| 4649 | |
| 4650 | // Helper function to parse the lane index for vector lists. |
| 4651 | OperandMatchResultTy ARMAsmParser:: |
| 4652 | parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { |
| 4653 | MCAsmParser &Parser = getParser(); |
| 4654 | Index = 0; // Always return a defined index value. |
| 4655 | if (Parser.getTok().is(AsmToken::LBrac)) { |
| 4656 | Parser.Lex(); // Eat the '['. |
| 4657 | if (Parser.getTok().is(AsmToken::RBrac)) { |
| 4658 | // "Dn[]" is the 'all lanes' syntax. |
| 4659 | LaneKind = AllLanes; |
| 4660 | EndLoc = Parser.getTok().getEndLoc(); |
| 4661 | Parser.Lex(); // Eat the ']'. |
| 4662 | return MatchOperand_Success; |
| 4663 | } |
| 4664 | |
| 4665 | // There's an optional '#' token here. Normally there wouldn't be, but |
| 4666 | // inline assemble puts one in, and it's friendly to accept that. |
| 4667 | if (Parser.getTok().is(AsmToken::Hash)) |
| 4668 | Parser.Lex(); // Eat '#' or '$'. |
| 4669 | |
| 4670 | const MCExpr *LaneIndex; |
| 4671 | SMLoc Loc = Parser.getTok().getLoc(); |
| 4672 | if (getParser().parseExpression(LaneIndex)) { |
| 4673 | Error(Loc, "illegal expression"); |
| 4674 | return MatchOperand_ParseFail; |
| 4675 | } |
| 4676 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); |
| 4677 | if (!CE) { |
| 4678 | Error(Loc, "lane index must be empty or an integer"); |
| 4679 | return MatchOperand_ParseFail; |
| 4680 | } |
| 4681 | if (Parser.getTok().isNot(AsmToken::RBrac)) { |
| 4682 | Error(Parser.getTok().getLoc(), "']' expected"); |
| 4683 | return MatchOperand_ParseFail; |
| 4684 | } |
| 4685 | EndLoc = Parser.getTok().getEndLoc(); |
| 4686 | Parser.Lex(); // Eat the ']'. |
| 4687 | int64_t Val = CE->getValue(); |
| 4688 | |
| 4689 | // FIXME: Make this range check context sensitive for .8, .16, .32. |
| 4690 | if (Val < 0 || Val > 7) { |
| 4691 | Error(Parser.getTok().getLoc(), "lane index out of range"); |
| 4692 | return MatchOperand_ParseFail; |
| 4693 | } |
| 4694 | Index = Val; |
| 4695 | LaneKind = IndexedLane; |
| 4696 | return MatchOperand_Success; |
| 4697 | } |
| 4698 | LaneKind = NoLanes; |
| 4699 | return MatchOperand_Success; |
| 4700 | } |
| 4701 | |
| 4702 | // parse a vector register list |
| 4703 | OperandMatchResultTy |
| 4704 | ARMAsmParser::parseVectorList(OperandVector &Operands) { |
| 4705 | MCAsmParser &Parser = getParser(); |
| 4706 | VectorLaneTy LaneKind; |
| 4707 | unsigned LaneIndex; |
| 4708 | SMLoc S = Parser.getTok().getLoc(); |
| 4709 | // As an extension (to match gas), support a plain D register or Q register |
| 4710 | // (without encosing curly braces) as a single or double entry list, |
| 4711 | // respectively. |
| 4712 | if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) { |
| 4713 | SMLoc E = Parser.getTok().getEndLoc(); |
| 4714 | int Reg = tryParseRegister(); |
| 4715 | if (Reg == -1) |
| 4716 | return MatchOperand_NoMatch; |
| 4717 | if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { |
| 4718 | OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); |
| 4719 | if (Res != MatchOperand_Success) |
| 4720 | return Res; |
| 4721 | switch (LaneKind) { |
| 4722 | case NoLanes: |
| 4723 | Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); |
| 4724 | break; |
| 4725 | case AllLanes: |
| 4726 | Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, |
| 4727 | S, E)); |
| 4728 | break; |
| 4729 | case IndexedLane: |
| 4730 | Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, |
| 4731 | LaneIndex, |
| 4732 | false, S, E)); |
| 4733 | break; |
| 4734 | } |
| 4735 | return MatchOperand_Success; |
| 4736 | } |
| 4737 | if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { |
| 4738 | Reg = getDRegFromQReg(Reg); |
| 4739 | OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); |
| 4740 | if (Res != MatchOperand_Success) |
| 4741 | return Res; |
| 4742 | switch (LaneKind) { |
| 4743 | case NoLanes: |
| 4744 | Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, |
| 4745 | &ARMMCRegisterClasses[ARM::DPairRegClassID]); |
| 4746 | Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); |
| 4747 | break; |
| 4748 | case AllLanes: |
| 4749 | Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, |
| 4750 | &ARMMCRegisterClasses[ARM::DPairRegClassID]); |
| 4751 | Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, |
| 4752 | S, E)); |
| 4753 | break; |
| 4754 | case IndexedLane: |
| 4755 | Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, |
| 4756 | LaneIndex, |
| 4757 | false, S, E)); |
| 4758 | break; |
| 4759 | } |
| 4760 | return MatchOperand_Success; |
| 4761 | } |
| 4762 | Error(S, "vector register expected"); |
| 4763 | return MatchOperand_ParseFail; |
| 4764 | } |
| 4765 | |
| 4766 | if (Parser.getTok().isNot(AsmToken::LCurly)) |
| 4767 | return MatchOperand_NoMatch; |
| 4768 | |
| 4769 | Parser.Lex(); // Eat '{' token. |
| 4770 | SMLoc RegLoc = Parser.getTok().getLoc(); |
| 4771 | |
| 4772 | int Reg = tryParseRegister(); |
| 4773 | if (Reg == -1) { |
| 4774 | Error(RegLoc, "register expected"); |
| 4775 | return MatchOperand_ParseFail; |
| 4776 | } |
| 4777 | unsigned Count = 1; |
| 4778 | int Spacing = 0; |
| 4779 | unsigned FirstReg = Reg; |
| 4780 | |
| 4781 | if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { |
| 4782 | Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected"); |
| 4783 | return MatchOperand_ParseFail; |
| 4784 | } |
| 4785 | // The list is of D registers, but we also allow Q regs and just interpret |
| 4786 | // them as the two D sub-registers. |
| 4787 | else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { |
| 4788 | FirstReg = Reg = getDRegFromQReg(Reg); |
| 4789 | Spacing = 1; // double-spacing requires explicit D registers, otherwise |
| 4790 | // it's ambiguous with four-register single spaced. |
| 4791 | ++Reg; |
| 4792 | ++Count; |
| 4793 | } |
| 4794 | |
| 4795 | SMLoc E; |
| 4796 | if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) |
| 4797 | return MatchOperand_ParseFail; |
| 4798 | |
| 4799 | while (Parser.getTok().is(AsmToken::Comma) || |
| 4800 | Parser.getTok().is(AsmToken::Minus)) { |
| 4801 | if (Parser.getTok().is(AsmToken::Minus)) { |
| 4802 | if (!Spacing) |
| 4803 | Spacing = 1; // Register range implies a single spaced list. |
| 4804 | else if (Spacing == 2) { |
| 4805 | Error(Parser.getTok().getLoc(), |
| 4806 | "sequential registers in double spaced list"); |
| 4807 | return MatchOperand_ParseFail; |
| 4808 | } |
| 4809 | Parser.Lex(); // Eat the minus. |
| 4810 | SMLoc AfterMinusLoc = Parser.getTok().getLoc(); |
| 4811 | int EndReg = tryParseRegister(); |
| 4812 | if (EndReg == -1) { |
| 4813 | Error(AfterMinusLoc, "register expected"); |
| 4814 | return MatchOperand_ParseFail; |
| 4815 | } |
| 4816 | // Allow Q regs and just interpret them as the two D sub-registers. |
| 4817 | if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) |
| 4818 | EndReg = getDRegFromQReg(EndReg) + 1; |
| 4819 | // If the register is the same as the start reg, there's nothing |
| 4820 | // more to do. |
| 4821 | if (Reg == EndReg) |
| 4822 | continue; |
| 4823 | // The register must be in the same register class as the first. |
| 4824 | if ((hasMVE() && |
| 4825 | !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || |
| 4826 | (!hasMVE() && |
| 4827 | !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { |
| 4828 | Error(AfterMinusLoc, "invalid register in register list"); |
| 4829 | return MatchOperand_ParseFail; |
| 4830 | } |
| 4831 | // Ranges must go from low to high. |
| 4832 | if (Reg > EndReg) { |
| 4833 | Error(AfterMinusLoc, "bad range in register list"); |
| 4834 | return MatchOperand_ParseFail; |
| 4835 | } |
| 4836 | // Parse the lane specifier if present. |
| 4837 | VectorLaneTy NextLaneKind; |
| 4838 | unsigned NextLaneIndex; |
| 4839 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != |
| 4840 | MatchOperand_Success) |
| 4841 | return MatchOperand_ParseFail; |
| 4842 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { |
| 4843 | Error(AfterMinusLoc, "mismatched lane index in register list"); |
| 4844 | return MatchOperand_ParseFail; |
| 4845 | } |
| 4846 | |
| 4847 | // Add all the registers in the range to the register list. |
| 4848 | Count += EndReg - Reg; |
| 4849 | Reg = EndReg; |
| 4850 | continue; |
| 4851 | } |
| 4852 | Parser.Lex(); // Eat the comma. |
| 4853 | RegLoc = Parser.getTok().getLoc(); |
| 4854 | int OldReg = Reg; |
| 4855 | Reg = tryParseRegister(); |
| 4856 | if (Reg == -1) { |
| 4857 | Error(RegLoc, "register expected"); |
| 4858 | return MatchOperand_ParseFail; |
| 4859 | } |
| 4860 | |
| 4861 | if (hasMVE()) { |
| 4862 | if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { |
| 4863 | Error(RegLoc, "vector register in range Q0-Q7 expected"); |
| 4864 | return MatchOperand_ParseFail; |
| 4865 | } |
| 4866 | Spacing = 1; |
| 4867 | } |
| 4868 | // vector register lists must be contiguous. |
| 4869 | // It's OK to use the enumeration values directly here rather, as the |
| 4870 | // VFP register classes have the enum sorted properly. |
| 4871 | // |
| 4872 | // The list is of D registers, but we also allow Q regs and just interpret |
| 4873 | // them as the two D sub-registers. |
| 4874 | else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { |
| 4875 | if (!Spacing) |
| 4876 | Spacing = 1; // Register range implies a single spaced list. |
| 4877 | else if (Spacing == 2) { |
| 4878 | Error(RegLoc, |
| 4879 | "invalid register in double-spaced list (must be 'D' register')"); |
| 4880 | return MatchOperand_ParseFail; |
| 4881 | } |
| 4882 | Reg = getDRegFromQReg(Reg); |
| 4883 | if (Reg != OldReg + 1) { |
| 4884 | Error(RegLoc, "non-contiguous register range"); |
| 4885 | return MatchOperand_ParseFail; |
| 4886 | } |
| 4887 | ++Reg; |
| 4888 | Count += 2; |
| 4889 | // Parse the lane specifier if present. |
| 4890 | VectorLaneTy NextLaneKind; |
| 4891 | unsigned NextLaneIndex; |
| 4892 | SMLoc LaneLoc = Parser.getTok().getLoc(); |
| 4893 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != |
| 4894 | MatchOperand_Success) |
| 4895 | return MatchOperand_ParseFail; |
| 4896 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { |
| 4897 | Error(LaneLoc, "mismatched lane index in register list"); |
| 4898 | return MatchOperand_ParseFail; |
| 4899 | } |
| 4900 | continue; |
| 4901 | } |
| 4902 | // Normal D register. |
| 4903 | // Figure out the register spacing (single or double) of the list if |
| 4904 | // we don't know it already. |
| 4905 | if (!Spacing) |
| 4906 | Spacing = 1 + (Reg == OldReg + 2); |
| 4907 | |
| 4908 | // Just check that it's contiguous and keep going. |
| 4909 | if (Reg != OldReg + Spacing) { |
| 4910 | Error(RegLoc, "non-contiguous register range"); |
| 4911 | return MatchOperand_ParseFail; |
| 4912 | } |
| 4913 | ++Count; |
| 4914 | // Parse the lane specifier if present. |
| 4915 | VectorLaneTy NextLaneKind; |
| 4916 | unsigned NextLaneIndex; |
| 4917 | SMLoc EndLoc = Parser.getTok().getLoc(); |
| 4918 | if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) |
| 4919 | return MatchOperand_ParseFail; |
| 4920 | if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { |
| 4921 | Error(EndLoc, "mismatched lane index in register list"); |
| 4922 | return MatchOperand_ParseFail; |
| 4923 | } |
| 4924 | } |
| 4925 | |
| 4926 | if (Parser.getTok().isNot(AsmToken::RCurly)) { |
| 4927 | Error(Parser.getTok().getLoc(), "'}' expected"); |
| 4928 | return MatchOperand_ParseFail; |
| 4929 | } |
| 4930 | E = Parser.getTok().getEndLoc(); |
| 4931 | Parser.Lex(); // Eat '}' token. |
| 4932 | |
| 4933 | switch (LaneKind) { |
| 4934 | case NoLanes: |
| 4935 | case AllLanes: { |
| 4936 | // Two-register operands have been converted to the |
| 4937 | // composite register classes. |
| 4938 | if (Count == 2 && !hasMVE()) { |
| 4939 | const MCRegisterClass *RC = (Spacing == 1) ? |
| 4940 | &ARMMCRegisterClasses[ARM::DPairRegClassID] : |
| 4941 | &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; |
| 4942 | FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); |
| 4943 | } |
| 4944 | auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : |
| 4945 | ARMOperand::CreateVectorListAllLanes); |
| 4946 | Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); |
| 4947 | break; |
| 4948 | } |
| 4949 | case IndexedLane: |
| 4950 | Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, |
| 4951 | LaneIndex, |
| 4952 | (Spacing == 2), |
| 4953 | S, E)); |
| 4954 | break; |
| 4955 | } |
| 4956 | return MatchOperand_Success; |
| 4957 | } |
| 4958 | |
| 4959 | /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. |
| 4960 | OperandMatchResultTy |
| 4961 | ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { |
| 4962 | MCAsmParser &Parser = getParser(); |
| 4963 | SMLoc S = Parser.getTok().getLoc(); |
| 4964 | const AsmToken &Tok = Parser.getTok(); |
| 4965 | unsigned Opt; |
| 4966 | |
| 4967 | if (Tok.is(AsmToken::Identifier)) { |
| 4968 | StringRef OptStr = Tok.getString(); |
| 4969 | |
| 4970 | Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) |
| 4971 | .Case("sy", ARM_MB::SY) |
| 4972 | .Case("st", ARM_MB::ST) |
| 4973 | .Case("ld", ARM_MB::LD) |
| 4974 | .Case("sh", ARM_MB::ISH) |
| 4975 | .Case("ish", ARM_MB::ISH) |
| 4976 | .Case("shst", ARM_MB::ISHST) |
| 4977 | .Case("ishst", ARM_MB::ISHST) |
| 4978 | .Case("ishld", ARM_MB::ISHLD) |
| 4979 | .Case("nsh", ARM_MB::NSH) |
| 4980 | .Case("un", ARM_MB::NSH) |
| 4981 | .Case("nshst", ARM_MB::NSHST) |
| 4982 | .Case("nshld", ARM_MB::NSHLD) |
| 4983 | .Case("unst", ARM_MB::NSHST) |
| 4984 | .Case("osh", ARM_MB::OSH) |
| 4985 | .Case("oshst", ARM_MB::OSHST) |
| 4986 | .Case("oshld", ARM_MB::OSHLD) |
| 4987 | .Default(~0U); |
| 4988 | |
| 4989 | // ishld, oshld, nshld and ld are only available from ARMv8. |
| 4990 | if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || |
| 4991 | Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) |
| 4992 | Opt = ~0U; |
| 4993 | |
| 4994 | if (Opt == ~0U) |
| 4995 | return MatchOperand_NoMatch; |
| 4996 | |
| 4997 | Parser.Lex(); // Eat identifier token. |
| 4998 | } else if (Tok.is(AsmToken::Hash) || |
| 4999 | Tok.is(AsmToken::Dollar) || |
| 5000 | Tok.is(AsmToken::Integer)) { |
| 5001 | if (Parser.getTok().isNot(AsmToken::Integer)) |
| 5002 | Parser.Lex(); // Eat '#' or '$'. |
| 5003 | SMLoc Loc = Parser.getTok().getLoc(); |
| 5004 | |
| 5005 | const MCExpr *MemBarrierID; |
| 5006 | if (getParser().parseExpression(MemBarrierID)) { |
| 5007 | Error(Loc, "illegal expression"); |
| 5008 | return MatchOperand_ParseFail; |
| 5009 | } |
| 5010 | |
| 5011 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); |
| 5012 | if (!CE) { |
| 5013 | Error(Loc, "constant expression expected"); |
| 5014 | return MatchOperand_ParseFail; |
| 5015 | } |
| 5016 | |
| 5017 | int Val = CE->getValue(); |
| 5018 | if (Val & ~0xf) { |
| 5019 | Error(Loc, "immediate value out of range"); |
| 5020 | return MatchOperand_ParseFail; |
| 5021 | } |
| 5022 | |
| 5023 | Opt = ARM_MB::RESERVED_0 + Val; |
| 5024 | } else |
| 5025 | return MatchOperand_ParseFail; |
| 5026 | |
| 5027 | Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); |
| 5028 | return MatchOperand_Success; |
| 5029 | } |
| 5030 | |
| 5031 | OperandMatchResultTy |
| 5032 | ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { |
| 5033 | MCAsmParser &Parser = getParser(); |
| 5034 | SMLoc S = Parser.getTok().getLoc(); |
| 5035 | const AsmToken &Tok = Parser.getTok(); |
| 5036 | |
| 5037 | if (Tok.isNot(AsmToken::Identifier)) |
| 5038 | return MatchOperand_NoMatch; |
| 5039 | |
| 5040 | if (!Tok.getString().equals_insensitive("csync")) |
| 5041 | return MatchOperand_NoMatch; |
| 5042 | |
| 5043 | Parser.Lex(); // Eat identifier token. |
| 5044 | |
| 5045 | Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); |
| 5046 | return MatchOperand_Success; |
| 5047 | } |
| 5048 | |
| 5049 | /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. |
| 5050 | OperandMatchResultTy |
| 5051 | ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { |
| 5052 | MCAsmParser &Parser = getParser(); |
| 5053 | SMLoc S = Parser.getTok().getLoc(); |
| 5054 | const AsmToken &Tok = Parser.getTok(); |
| 5055 | unsigned Opt; |
| 5056 | |
| 5057 | if (Tok.is(AsmToken::Identifier)) { |
| 5058 | StringRef OptStr = Tok.getString(); |
| 5059 | |
| 5060 | if (OptStr.equals_insensitive("sy")) |
| 5061 | Opt = ARM_ISB::SY; |
| 5062 | else |
| 5063 | return MatchOperand_NoMatch; |
| 5064 | |
| 5065 | Parser.Lex(); // Eat identifier token. |
| 5066 | } else if (Tok.is(AsmToken::Hash) || |
| 5067 | Tok.is(AsmToken::Dollar) || |
| 5068 | Tok.is(AsmToken::Integer)) { |
| 5069 | if (Parser.getTok().isNot(AsmToken::Integer)) |
| 5070 | Parser.Lex(); // Eat '#' or '$'. |
| 5071 | SMLoc Loc = Parser.getTok().getLoc(); |
| 5072 | |
| 5073 | const MCExpr *ISBarrierID; |
| 5074 | if (getParser().parseExpression(ISBarrierID)) { |
| 5075 | Error(Loc, "illegal expression"); |
| 5076 | return MatchOperand_ParseFail; |
| 5077 | } |
| 5078 | |
| 5079 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); |
| 5080 | if (!CE) { |
| 5081 | Error(Loc, "constant expression expected"); |
| 5082 | return MatchOperand_ParseFail; |
| 5083 | } |
| 5084 | |
| 5085 | int Val = CE->getValue(); |
| 5086 | if (Val & ~0xf) { |
| 5087 | Error(Loc, "immediate value out of range"); |
| 5088 | return MatchOperand_ParseFail; |
| 5089 | } |
| 5090 | |
| 5091 | Opt = ARM_ISB::RESERVED_0 + Val; |
| 5092 | } else |
| 5093 | return MatchOperand_ParseFail; |
| 5094 | |
| 5095 | Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( |
| 5096 | (ARM_ISB::InstSyncBOpt)Opt, S)); |
| 5097 | return MatchOperand_Success; |
| 5098 | } |
| 5099 | |
| 5100 | |
| 5101 | /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. |
| 5102 | OperandMatchResultTy |
| 5103 | ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { |
| 5104 | MCAsmParser &Parser = getParser(); |
| 5105 | SMLoc S = Parser.getTok().getLoc(); |
| 5106 | const AsmToken &Tok = Parser.getTok(); |
| 5107 | if (!Tok.is(AsmToken::Identifier)) |
| 5108 | return MatchOperand_NoMatch; |
| 5109 | StringRef IFlagsStr = Tok.getString(); |
| 5110 | |
| 5111 | // An iflags string of "none" is interpreted to mean that none of the AIF |
| 5112 | // bits are set. Not a terribly useful instruction, but a valid encoding. |
| 5113 | unsigned IFlags = 0; |
| 5114 | if (IFlagsStr != "none") { |
| 5115 | for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { |
| 5116 | unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower()) |
| 5117 | .Case("a", ARM_PROC::A) |
| 5118 | .Case("i", ARM_PROC::I) |
| 5119 | .Case("f", ARM_PROC::F) |
| 5120 | .Default(~0U); |
| 5121 | |
| 5122 | // If some specific iflag is already set, it means that some letter is |
| 5123 | // present more than once, this is not acceptable. |
| 5124 | if (Flag == ~0U || (IFlags & Flag)) |
| 5125 | return MatchOperand_NoMatch; |
| 5126 | |
| 5127 | IFlags |= Flag; |
| 5128 | } |
| 5129 | } |
| 5130 | |
| 5131 | Parser.Lex(); // Eat identifier token. |
| 5132 | Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); |
| 5133 | return MatchOperand_Success; |
| 5134 | } |
| 5135 | |
| 5136 | /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. |
| 5137 | OperandMatchResultTy |
| 5138 | ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { |
| 5139 | MCAsmParser &Parser = getParser(); |
| 5140 | SMLoc S = Parser.getTok().getLoc(); |
| 5141 | const AsmToken &Tok = Parser.getTok(); |
| 5142 | |
| 5143 | if (Tok.is(AsmToken::Integer)) { |
| 5144 | int64_t Val = Tok.getIntVal(); |
| 5145 | if (Val > 255 || Val < 0) { |
| 5146 | return MatchOperand_NoMatch; |
| 5147 | } |
| 5148 | unsigned SYSmvalue = Val & 0xFF; |
| 5149 | Parser.Lex(); |
| 5150 | Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); |
| 5151 | return MatchOperand_Success; |
| 5152 | } |
| 5153 | |
| 5154 | if (!Tok.is(AsmToken::Identifier)) |
| 5155 | return MatchOperand_NoMatch; |
| 5156 | StringRef Mask = Tok.getString(); |
| 5157 | |
| 5158 | if (isMClass()) { |
| 5159 | auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower()); |
| 5160 | if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits())) |
| 5161 | return MatchOperand_NoMatch; |
| 5162 | |
| 5163 | unsigned SYSmvalue = TheReg->Encoding & 0xFFF; |
| 5164 | |
| 5165 | Parser.Lex(); // Eat identifier token. |
| 5166 | Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); |
| 5167 | return MatchOperand_Success; |
| 5168 | } |
| 5169 | |
| 5170 | // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" |
| 5171 | size_t Start = 0, Next = Mask.find('_'); |
| 5172 | StringRef Flags = ""; |
| 5173 | std::string SpecReg = Mask.slice(Start, Next).lower(); |
| 5174 | if (Next != StringRef::npos) |
| 5175 | Flags = Mask.slice(Next+1, Mask.size()); |
| 5176 | |
| 5177 | // FlagsVal contains the complete mask: |
| 5178 | // 3-0: Mask |
| 5179 | // 4: Special Reg (cpsr, apsr => 0; spsr => 1) |
| 5180 | unsigned FlagsVal = 0; |
| 5181 | |
| 5182 | if (SpecReg == "apsr") { |
| 5183 | FlagsVal = StringSwitch<unsigned>(Flags) |
| 5184 | .Case("nzcvq", 0x8) // same as CPSR_f |
| 5185 | .Case("g", 0x4) // same as CPSR_s |
| 5186 | .Case("nzcvqg", 0xc) // same as CPSR_fs |
| 5187 | .Default(~0U); |
| 5188 | |
| 5189 | if (FlagsVal == ~0U) { |
| 5190 | if (!Flags.empty()) |
| 5191 | return MatchOperand_NoMatch; |
| 5192 | else |
| 5193 | FlagsVal = 8; // No flag |
| 5194 | } |
| 5195 | } else if (SpecReg == "cpsr" || SpecReg == "spsr") { |
| 5196 | // cpsr_all is an alias for cpsr_fc, as is plain cpsr. |
| 5197 | if (Flags == "all" || Flags == "") |
| 5198 | Flags = "fc"; |
| 5199 | for (int i = 0, e = Flags.size(); i != e; ++i) { |
| 5200 | unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) |
| 5201 | .Case("c", 1) |
| 5202 | .Case("x", 2) |
| 5203 | .Case("s", 4) |
| 5204 | .Case("f", 8) |
| 5205 | .Default(~0U); |
| 5206 | |
| 5207 | // If some specific flag is already set, it means that some letter is |
| 5208 | // present more than once, this is not acceptable. |
| 5209 | if (Flag == ~0U || (FlagsVal & Flag)) |
| 5210 | return MatchOperand_NoMatch; |
| 5211 | FlagsVal |= Flag; |
| 5212 | } |
| 5213 | } else // No match for special register. |
| 5214 | return MatchOperand_NoMatch; |
| 5215 | |
| 5216 | // Special register without flags is NOT equivalent to "fc" flags. |
| 5217 | // NOTE: This is a divergence from gas' behavior. Uncommenting the following |
| 5218 | // two lines would enable gas compatibility at the expense of breaking |
| 5219 | // round-tripping. |
| 5220 | // |
| 5221 | // if (!FlagsVal) |
| 5222 | // FlagsVal = 0x9; |
| 5223 | |
| 5224 | // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) |
| 5225 | if (SpecReg == "spsr") |
| 5226 | FlagsVal |= 16; |
| 5227 | |
| 5228 | Parser.Lex(); // Eat identifier token. |
| 5229 | Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); |
| 5230 | return MatchOperand_Success; |
| 5231 | } |
| 5232 | |
| 5233 | /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for |
| 5234 | /// use in the MRS/MSR instructions added to support virtualization. |
| 5235 | OperandMatchResultTy |
| 5236 | ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { |
| 5237 | MCAsmParser &Parser = getParser(); |
| 5238 | SMLoc S = Parser.getTok().getLoc(); |
| 5239 | const AsmToken &Tok = Parser.getTok(); |
| 5240 | if (!Tok.is(AsmToken::Identifier)) |
| 5241 | return MatchOperand_NoMatch; |
| 5242 | StringRef RegName = Tok.getString(); |
| 5243 | |
| 5244 | auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower()); |
| 5245 | if (!TheReg) |
| 5246 | return MatchOperand_NoMatch; |
| 5247 | unsigned Encoding = TheReg->Encoding; |
| 5248 | |
| 5249 | Parser.Lex(); // Eat identifier token. |
| 5250 | Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); |
| 5251 | return MatchOperand_Success; |
| 5252 | } |
| 5253 | |
| 5254 | OperandMatchResultTy |
| 5255 | ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, |
| 5256 | int High) { |
| 5257 | MCAsmParser &Parser = getParser(); |
| 5258 | const AsmToken &Tok = Parser.getTok(); |
| 5259 | if (Tok.isNot(AsmToken::Identifier)) { |
| 5260 | Error(Parser.getTok().getLoc(), Op + " operand expected."); |
| 5261 | return MatchOperand_ParseFail; |
| 5262 | } |
| 5263 | StringRef ShiftName = Tok.getString(); |
| 5264 | std::string LowerOp = Op.lower(); |
| 5265 | std::string UpperOp = Op.upper(); |
| 5266 | if (ShiftName != LowerOp && ShiftName != UpperOp) { |
| 5267 | Error(Parser.getTok().getLoc(), Op + " operand expected."); |
| 5268 | return MatchOperand_ParseFail; |
| 5269 | } |
| 5270 | Parser.Lex(); // Eat shift type token. |
| 5271 | |
| 5272 | // There must be a '#' and a shift amount. |
| 5273 | if (Parser.getTok().isNot(AsmToken::Hash) && |
| 5274 | Parser.getTok().isNot(AsmToken::Dollar)) { |
| 5275 | Error(Parser.getTok().getLoc(), "'#' expected"); |
| 5276 | return MatchOperand_ParseFail; |
| 5277 | } |
| 5278 | Parser.Lex(); // Eat hash token. |
| 5279 | |
| 5280 | const MCExpr *ShiftAmount; |
| 5281 | SMLoc Loc = Parser.getTok().getLoc(); |
| 5282 | SMLoc EndLoc; |
| 5283 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { |
| 5284 | Error(Loc, "illegal expression"); |
| 5285 | return MatchOperand_ParseFail; |
| 5286 | } |
| 5287 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); |
| 5288 | if (!CE) { |
| 5289 | Error(Loc, "constant expression expected"); |
| 5290 | return MatchOperand_ParseFail; |
| 5291 | } |
| 5292 | int Val = CE->getValue(); |
| 5293 | if (Val < Low || Val > High) { |
| 5294 | Error(Loc, "immediate value out of range"); |
| 5295 | return MatchOperand_ParseFail; |
| 5296 | } |
| 5297 | |
| 5298 | Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); |
| 5299 | |
| 5300 | return MatchOperand_Success; |
| 5301 | } |
| 5302 | |
| 5303 | OperandMatchResultTy |
| 5304 | ARMAsmParser::parseSetEndImm(OperandVector &Operands) { |
| 5305 | MCAsmParser &Parser = getParser(); |
| 5306 | const AsmToken &Tok = Parser.getTok(); |
| 5307 | SMLoc S = Tok.getLoc(); |
| 5308 | if (Tok.isNot(AsmToken::Identifier)) { |
| 5309 | Error(S, "'be' or 'le' operand expected"); |
| 5310 | return MatchOperand_ParseFail; |
| 5311 | } |
| 5312 | int Val = StringSwitch<int>(Tok.getString().lower()) |
| 5313 | .Case("be", 1) |
| 5314 | .Case("le", 0) |
| 5315 | .Default(-1); |
| 5316 | Parser.Lex(); // Eat the token. |
| 5317 | |
| 5318 | if (Val == -1) { |
| 5319 | Error(S, "'be' or 'le' operand expected"); |
| 5320 | return MatchOperand_ParseFail; |
| 5321 | } |
| 5322 | Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, |
| 5323 | getContext()), |
| 5324 | S, Tok.getEndLoc())); |
| 5325 | return MatchOperand_Success; |
| 5326 | } |
| 5327 | |
| 5328 | /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT |
| 5329 | /// instructions. Legal values are: |
| 5330 | /// lsl #n 'n' in [0,31] |
| 5331 | /// asr #n 'n' in [1,32] |
| 5332 | /// n == 32 encoded as n == 0. |
| 5333 | OperandMatchResultTy |
| 5334 | ARMAsmParser::parseShifterImm(OperandVector &Operands) { |
| 5335 | MCAsmParser &Parser = getParser(); |
| 5336 | const AsmToken &Tok = Parser.getTok(); |
| 5337 | SMLoc S = Tok.getLoc(); |
| 5338 | if (Tok.isNot(AsmToken::Identifier)) { |
| 5339 | Error(S, "shift operator 'asr' or 'lsl' expected"); |
| 5340 | return MatchOperand_ParseFail; |
| 5341 | } |
| 5342 | StringRef ShiftName = Tok.getString(); |
| 5343 | bool isASR; |
| 5344 | if (ShiftName == "lsl" || ShiftName == "LSL") |
| 5345 | isASR = false; |
| 5346 | else if (ShiftName == "asr" || ShiftName == "ASR") |
| 5347 | isASR = true; |
| 5348 | else { |
| 5349 | Error(S, "shift operator 'asr' or 'lsl' expected"); |
| 5350 | return MatchOperand_ParseFail; |
| 5351 | } |
| 5352 | Parser.Lex(); // Eat the operator. |
| 5353 | |
| 5354 | // A '#' and a shift amount. |
| 5355 | if (Parser.getTok().isNot(AsmToken::Hash) && |
| 5356 | Parser.getTok().isNot(AsmToken::Dollar)) { |
| 5357 | Error(Parser.getTok().getLoc(), "'#' expected"); |
| 5358 | return MatchOperand_ParseFail; |
| 5359 | } |
| 5360 | Parser.Lex(); // Eat hash token. |
| 5361 | SMLoc ExLoc = Parser.getTok().getLoc(); |
| 5362 | |
| 5363 | const MCExpr *ShiftAmount; |
| 5364 | SMLoc EndLoc; |
| 5365 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { |
| 5366 | Error(ExLoc, "malformed shift expression"); |
| 5367 | return MatchOperand_ParseFail; |
| 5368 | } |
| 5369 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); |
| 5370 | if (!CE) { |
| 5371 | Error(ExLoc, "shift amount must be an immediate"); |
| 5372 | return MatchOperand_ParseFail; |
| 5373 | } |
| 5374 | |
| 5375 | int64_t Val = CE->getValue(); |
| 5376 | if (isASR) { |
| 5377 | // Shift amount must be in [1,32] |
| 5378 | if (Val < 1 || Val > 32) { |
| 5379 | Error(ExLoc, "'asr' shift amount must be in range [1,32]"); |
| 5380 | return MatchOperand_ParseFail; |
| 5381 | } |
| 5382 | // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. |
| 5383 | if (isThumb() && Val == 32) { |
| 5384 | Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); |
| 5385 | return MatchOperand_ParseFail; |
| 5386 | } |
| 5387 | if (Val == 32) Val = 0; |
| 5388 | } else { |
| 5389 | // Shift amount must be in [1,32] |
| 5390 | if (Val < 0 || Val > 31) { |
| 5391 | Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); |
| 5392 | return MatchOperand_ParseFail; |
| 5393 | } |
| 5394 | } |
| 5395 | |
| 5396 | Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); |
| 5397 | |
| 5398 | return MatchOperand_Success; |
| 5399 | } |
| 5400 | |
| 5401 | /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family |
| 5402 | /// of instructions. Legal values are: |
| 5403 | /// ror #n 'n' in {0, 8, 16, 24} |
| 5404 | OperandMatchResultTy |
| 5405 | ARMAsmParser::parseRotImm(OperandVector &Operands) { |
| 5406 | MCAsmParser &Parser = getParser(); |
| 5407 | const AsmToken &Tok = Parser.getTok(); |
| 5408 | SMLoc S = Tok.getLoc(); |
| 5409 | if (Tok.isNot(AsmToken::Identifier)) |
| 5410 | return MatchOperand_NoMatch; |
| 5411 | StringRef ShiftName = Tok.getString(); |
| 5412 | if (ShiftName != "ror" && ShiftName != "ROR") |
| 5413 | return MatchOperand_NoMatch; |
| 5414 | Parser.Lex(); // Eat the operator. |
| 5415 | |
| 5416 | // A '#' and a rotate amount. |
| 5417 | if (Parser.getTok().isNot(AsmToken::Hash) && |
| 5418 | Parser.getTok().isNot(AsmToken::Dollar)) { |
| 5419 | Error(Parser.getTok().getLoc(), "'#' expected"); |
| 5420 | return MatchOperand_ParseFail; |
| 5421 | } |
| 5422 | Parser.Lex(); // Eat hash token. |
| 5423 | SMLoc ExLoc = Parser.getTok().getLoc(); |
| 5424 | |
| 5425 | const MCExpr *ShiftAmount; |
| 5426 | SMLoc EndLoc; |
| 5427 | if (getParser().parseExpression(ShiftAmount, EndLoc)) { |
| 5428 | Error(ExLoc, "malformed rotate expression"); |
| 5429 | return MatchOperand_ParseFail; |
| 5430 | } |
| 5431 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); |
| 5432 | if (!CE) { |
| 5433 | Error(ExLoc, "rotate amount must be an immediate"); |
| 5434 | return MatchOperand_ParseFail; |
| 5435 | } |
| 5436 | |
| 5437 | int64_t Val = CE->getValue(); |
| 5438 | // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) |
| 5439 | // normally, zero is represented in asm by omitting the rotate operand |
| 5440 | // entirely. |
| 5441 | if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { |
| 5442 | Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); |
| 5443 | return MatchOperand_ParseFail; |
| 5444 | } |
| 5445 | |
| 5446 | Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); |
| 5447 | |
| 5448 | return MatchOperand_Success; |
| 5449 | } |
| 5450 | |
| 5451 | OperandMatchResultTy |
| 5452 | ARMAsmParser::parseModImm(OperandVector &Operands) { |
| 5453 | MCAsmParser &Parser = getParser(); |
| 5454 | MCAsmLexer &Lexer = getLexer(); |
| 5455 | int64_t Imm1, Imm2; |
| 5456 | |
| 5457 | SMLoc S = Parser.getTok().getLoc(); |
| 5458 | |
| 5459 | // 1) A mod_imm operand can appear in the place of a register name: |
| 5460 | // add r0, #mod_imm |
| 5461 | // add r0, r0, #mod_imm |
| 5462 | // to correctly handle the latter, we bail out as soon as we see an |
| 5463 | // identifier. |
| 5464 | // |
| 5465 | // 2) Similarly, we do not want to parse into complex operands: |
| 5466 | // mov r0, #mod_imm |
| 5467 | // mov r0, :lower16:(_foo) |
| 5468 | if (Parser.getTok().is(AsmToken::Identifier) || |
| 5469 | Parser.getTok().is(AsmToken::Colon)) |
| 5470 | return MatchOperand_NoMatch; |
| 5471 | |
| 5472 | // Hash (dollar) is optional as per the ARMARM |
| 5473 | if (Parser.getTok().is(AsmToken::Hash) || |
| 5474 | Parser.getTok().is(AsmToken::Dollar)) { |
| 5475 | // Avoid parsing into complex operands (#:) |
| 5476 | if (Lexer.peekTok().is(AsmToken::Colon)) |
| 5477 | return MatchOperand_NoMatch; |
| 5478 | |
| 5479 | // Eat the hash (dollar) |
| 5480 | Parser.Lex(); |
| 5481 | } |
| 5482 | |
| 5483 | SMLoc Sx1, Ex1; |
| 5484 | Sx1 = Parser.getTok().getLoc(); |
| 5485 | const MCExpr *Imm1Exp; |
| 5486 | if (getParser().parseExpression(Imm1Exp, Ex1)) { |
| 5487 | Error(Sx1, "malformed expression"); |
| 5488 | return MatchOperand_ParseFail; |
| 5489 | } |
| 5490 | |
| 5491 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp); |
| 5492 | |
| 5493 | if (CE) { |
| 5494 | // Immediate must fit within 32-bits |
| 5495 | Imm1 = CE->getValue(); |
| 5496 | int Enc = ARM_AM::getSOImmVal(Imm1); |
| 5497 | if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { |
| 5498 | // We have a match! |
| 5499 | Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), |
| 5500 | (Enc & 0xF00) >> 7, |
| 5501 | Sx1, Ex1)); |
| 5502 | return MatchOperand_Success; |
| 5503 | } |
| 5504 | |
| 5505 | // We have parsed an immediate which is not for us, fallback to a plain |
| 5506 | // immediate. This can happen for instruction aliases. For an example, |
| 5507 | // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform |
| 5508 | // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite |
| 5509 | // instruction with a mod_imm operand. The alias is defined such that the |
| 5510 | // parser method is shared, that's why we have to do this here. |
| 5511 | if (Parser.getTok().is(AsmToken::EndOfStatement)) { |
| 5512 | Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); |
| 5513 | return MatchOperand_Success; |
| 5514 | } |
| 5515 | } else { |
| 5516 | // Operands like #(l1 - l2) can only be evaluated at a later stage (via an |
| 5517 | // MCFixup). Fallback to a plain immediate. |
| 5518 | Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); |
| 5519 | return MatchOperand_Success; |
| 5520 | } |
| 5521 | |
| 5522 | // From this point onward, we expect the input to be a (#bits, #rot) pair |
| 5523 | if (Parser.getTok().isNot(AsmToken::Comma)) { |
| 5524 | Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); |
| 5525 | return MatchOperand_ParseFail; |
| 5526 | } |
| 5527 | |
| 5528 | if (Imm1 & ~0xFF) { |
| 5529 | Error(Sx1, "immediate operand must a number in the range [0, 255]"); |
| 5530 | return MatchOperand_ParseFail; |
| 5531 | } |
| 5532 | |
| 5533 | // Eat the comma |
| 5534 | Parser.Lex(); |
| 5535 | |
| 5536 | // Repeat for #rot |
| 5537 | SMLoc Sx2, Ex2; |
| 5538 | Sx2 = Parser.getTok().getLoc(); |
| 5539 | |
| 5540 | // Eat the optional hash (dollar) |
| 5541 | if (Parser.getTok().is(AsmToken::Hash) || |
| 5542 | Parser.getTok().is(AsmToken::Dollar)) |
| 5543 | Parser.Lex(); |
| 5544 | |
| 5545 | const MCExpr *Imm2Exp; |
| 5546 | if (getParser().parseExpression(Imm2Exp, Ex2)) { |
| 5547 | Error(Sx2, "malformed expression"); |
| 5548 | return MatchOperand_ParseFail; |
| 5549 | } |
| 5550 | |
| 5551 | CE = dyn_cast<MCConstantExpr>(Imm2Exp); |
| 5552 | |
| 5553 | if (CE) { |
| 5554 | Imm2 = CE->getValue(); |
| 5555 | if (!(Imm2 & ~0x1E)) { |
| 5556 | // We have a match! |
| 5557 | Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); |
| 5558 | return MatchOperand_Success; |
| 5559 | } |
| 5560 | Error(Sx2, "immediate operand must an even number in the range [0, 30]"); |
| 5561 | return MatchOperand_ParseFail; |
| 5562 | } else { |
| 5563 | Error(Sx2, "constant expression expected"); |
| 5564 | return MatchOperand_ParseFail; |
| 5565 | } |
| 5566 | } |
| 5567 | |
| 5568 | OperandMatchResultTy |
| 5569 | ARMAsmParser::parseBitfield(OperandVector &Operands) { |
| 5570 | MCAsmParser &Parser = getParser(); |
| 5571 | SMLoc S = Parser.getTok().getLoc(); |
| 5572 | // The bitfield descriptor is really two operands, the LSB and the width. |
| 5573 | if (Parser.getTok().isNot(AsmToken::Hash) && |
| 5574 | Parser.getTok().isNot(AsmToken::Dollar)) { |
| 5575 | Error(Parser.getTok().getLoc(), "'#' expected"); |
| 5576 | return MatchOperand_ParseFail; |
| 5577 | } |
| 5578 | Parser.Lex(); // Eat hash token. |
| 5579 | |
| 5580 | const MCExpr *LSBExpr; |
| 5581 | SMLoc E = Parser.getTok().getLoc(); |
| 5582 | if (getParser().parseExpression(LSBExpr)) { |
| 5583 | Error(E, "malformed immediate expression"); |
| 5584 | return MatchOperand_ParseFail; |
| 5585 | } |
| 5586 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); |
| 5587 | if (!CE) { |
| 5588 | Error(E, "'lsb' operand must be an immediate"); |
| 5589 | return MatchOperand_ParseFail; |
| 5590 | } |
| 5591 | |
| 5592 | int64_t LSB = CE->getValue(); |
| 5593 | // The LSB must be in the range [0,31] |
| 5594 | if (LSB < 0 || LSB > 31) { |
| 5595 | Error(E, "'lsb' operand must be in the range [0,31]"); |
| 5596 | return MatchOperand_ParseFail; |
| 5597 | } |
| 5598 | E = Parser.getTok().getLoc(); |
| 5599 | |
| 5600 | // Expect another immediate operand. |
| 5601 | if (Parser.getTok().isNot(AsmToken::Comma)) { |
| 5602 | Error(Parser.getTok().getLoc(), "too few operands"); |
| 5603 | return MatchOperand_ParseFail; |
| 5604 | } |
| 5605 | Parser.Lex(); // Eat hash token. |
| 5606 | if (Parser.getTok().isNot(AsmToken::Hash) && |
| 5607 | Parser.getTok().isNot(AsmToken::Dollar)) { |
| 5608 | Error(Parser.getTok().getLoc(), "'#' expected"); |
| 5609 | return MatchOperand_ParseFail; |
| 5610 | } |
| 5611 | Parser.Lex(); // Eat hash token. |
| 5612 | |
| 5613 | const MCExpr *WidthExpr; |
| 5614 | SMLoc EndLoc; |
| 5615 | if (getParser().parseExpression(WidthExpr, EndLoc)) { |
| 5616 | Error(E, "malformed immediate expression"); |
| 5617 | return MatchOperand_ParseFail; |
| 5618 | } |
| 5619 | CE = dyn_cast<MCConstantExpr>(WidthExpr); |
| 5620 | if (!CE) { |
| 5621 | Error(E, "'width' operand must be an immediate"); |
| 5622 | return MatchOperand_ParseFail; |
| 5623 | } |
| 5624 | |
| 5625 | int64_t Width = CE->getValue(); |
| 5626 | // The LSB must be in the range [1,32-lsb] |
| 5627 | if (Width < 1 || Width > 32 - LSB) { |
| 5628 | Error(E, "'width' operand must be in the range [1,32-lsb]"); |
| 5629 | return MatchOperand_ParseFail; |
| 5630 | } |
| 5631 | |
| 5632 | Operands.push_back(ARMOperand::CreateBitfi |