Bug Summary

File:lib/Target/ARM/ARMCallingConv.cpp
Warning:line 132, column 16
3rd function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMCallingConv.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn374877/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn374877=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-15-233810-7101-1 -x c++ /build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM/ARMCallingConv.cpp
1//=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the custom routines for the ARM Calling Convention that
10// aren't done by tablegen, and includes the table generated implementations.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMCallingConv.h"
16#include "ARMSubtarget.h"
17#include "ARMRegisterInfo.h"
18using namespace llvm;
19
20// APCS f64 is in register pairs, possibly split to stack
21static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
22 CCValAssign::LocInfo &LocInfo,
23 CCState &State, bool CanFail) {
24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
25
26 // Try to get the first register.
27 if (unsigned Reg = State.AllocateReg(RegList))
28 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
29 else {
30 // For the 2nd half of a v2f64, do not fail.
31 if (CanFail)
32 return false;
33
34 // Put the whole thing on the stack.
35 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
36 State.AllocateStack(8, 4),
37 LocVT, LocInfo));
38 return true;
39 }
40
41 // Try to get the second register.
42 if (unsigned Reg = State.AllocateReg(RegList))
43 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
44 else
45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
46 State.AllocateStack(4, 4),
47 LocVT, LocInfo));
48 return true;
49}
50
51static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
54 CCState &State) {
55 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
56 return false;
57 if (LocVT == MVT::v2f64 &&
58 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
59 return false;
60 return true; // we handled it
61}
62
63// AAPCS f64 is in aligned register pairs
64static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
65 CCValAssign::LocInfo &LocInfo,
66 CCState &State, bool CanFail) {
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
68 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
71
72 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
73 if (Reg == 0) {
74
75 // If we had R3 unallocated only, now we still must to waste it.
76 Reg = State.AllocateReg(GPRArgRegs);
77 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64")(((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"
) ? static_cast<void> (0) : __assert_fail ("(!Reg || Reg == ARM::R3) && \"Wrong GPRs usage for f64\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM/ARMCallingConv.cpp"
, 77, __PRETTY_FUNCTION__))
;
78
79 // For the 2nd half of a v2f64, do not just fail.
80 if (CanFail)
81 return false;
82
83 // Put the whole thing on the stack.
84 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
85 State.AllocateStack(8, 8),
86 LocVT, LocInfo));
87 return true;
88 }
89
90 unsigned i;
91 for (i = 0; i < 2; ++i)
92 if (HiRegList[i] == Reg)
93 break;
94
95 unsigned T = State.AllocateReg(LoRegList[i]);
96 (void)T;
97 assert(T == LoRegList[i] && "Could not allocate register")((T == LoRegList[i] && "Could not allocate register")
? static_cast<void> (0) : __assert_fail ("T == LoRegList[i] && \"Could not allocate register\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM/ARMCallingConv.cpp"
, 97, __PRETTY_FUNCTION__))
;
98
99 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
101 LocVT, LocInfo));
102 return true;
103}
104
105static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
106 CCValAssign::LocInfo &LocInfo,
107 ISD::ArgFlagsTy &ArgFlags,
108 CCState &State) {
109 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
110 return false;
111 if (LocVT == MVT::v2f64 &&
112 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
113 return false;
114 return true; // we handled it
115}
116
117static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
118 CCValAssign::LocInfo &LocInfo, CCState &State) {
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
120 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
121
122 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
123 if (Reg == 0)
3
Assuming 'Reg' is not equal to 0
4
Taking false branch
124 return false; // we didn't handle it
125
126 unsigned i;
127 for (i = 0; i < 2; ++i)
5
Loop condition is true. Entering loop body
8
Loop condition is true. Entering loop body
11
The value 2 is assigned to 'i'
12
Loop condition is false. Execution continues on line 131
128 if (HiRegList[i] == Reg)
6
Assuming the condition is false
7
Taking false branch
9
Assuming the condition is false
10
Taking false branch
129 break;
130
131 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
132 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
13
3rd function call argument is an uninitialized value
133 LocVT, LocInfo));
134 return true;
135}
136
137static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
138 CCValAssign::LocInfo &LocInfo,
139 ISD::ArgFlagsTy &ArgFlags,
140 CCState &State) {
141 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
2
Calling 'f64RetAssign'
142 return false;
143 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
144 return false;
145 return true; // we handled it
146}
147
148static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
149 CCValAssign::LocInfo &LocInfo,
150 ISD::ArgFlagsTy &ArgFlags,
151 CCState &State) {
152 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
1
Calling 'RetCC_ARM_APCS_Custom_f64'
153 State);
154}
155
156static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
157
158static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
159 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
160 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
161 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
162static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
163 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
164static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
165
166
167// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
168// has InConsecutiveRegs set, and that the last member also has
169// InConsecutiveRegsLast set. We must process all members of the HA before
170// we can allocate it, as we need to know the total number of registers that
171// will be needed in order to (attempt to) allocate a contiguous block.
172static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT,
173 MVT &LocVT,
174 CCValAssign::LocInfo &LocInfo,
175 ISD::ArgFlagsTy &ArgFlags,
176 CCState &State) {
177 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
178
179 // AAPCS HFAs must have 1-4 elements, all of the same type
180 if (PendingMembers.size() > 0)
181 assert(PendingMembers[0].getLocVT() == LocVT)((PendingMembers[0].getLocVT() == LocVT) ? static_cast<void
> (0) : __assert_fail ("PendingMembers[0].getLocVT() == LocVT"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM/ARMCallingConv.cpp"
, 181, __PRETTY_FUNCTION__))
;
182
183 // Add the argument to the list to be allocated once we know the size of the
184 // aggregate. Store the type's required alignmnent as extra info for later: in
185 // the [N x i64] case all trace has been removed by the time we actually get
186 // to do allocation.
187 PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
188 ArgFlags.getOrigAlign()));
189
190 if (!ArgFlags.isInConsecutiveRegsLast())
191 return true;
192
193 // Try to allocate a contiguous block of registers, each of the correct
194 // size to hold one member.
195 auto &DL = State.getMachineFunction().getDataLayout();
196 unsigned StackAlign = DL.getStackAlignment().value();
197 unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign);
198
199 ArrayRef<MCPhysReg> RegList;
200 switch (LocVT.SimpleTy) {
201 case MVT::i32: {
202 RegList = RRegList;
203 unsigned RegIdx = State.getFirstUnallocated(RegList);
204
205 // First consume all registers that would give an unaligned object. Whether
206 // we go on stack or in regs, no-one will be using them in future.
207 unsigned RegAlign = alignTo(Align, 4) / 4;
208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
209 State.AllocateReg(RegList[RegIdx++]);
210
211 break;
212 }
213 case MVT::f16:
214 case MVT::f32:
215 RegList = SRegList;
216 break;
217 case MVT::v4f16:
218 case MVT::f64:
219 RegList = DRegList;
220 break;
221 case MVT::v8f16:
222 case MVT::v2f64:
223 RegList = QRegList;
224 break;
225 default:
226 llvm_unreachable("Unexpected member type for block aggregate")::llvm::llvm_unreachable_internal("Unexpected member type for block aggregate"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/Target/ARM/ARMCallingConv.cpp"
, 226)
;
227 break;
228 }
229
230 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
231 if (RegResult) {
232 for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
233 It != PendingMembers.end(); ++It) {
234 It->convertToReg(RegResult);
235 State.addLoc(*It);
236 ++RegResult;
237 }
238 PendingMembers.clear();
239 return true;
240 }
241
242 // Register allocation failed, we'll be needing the stack
243 unsigned Size = LocVT.getSizeInBits() / 8;
244 if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) {
245 // If nothing else has used the stack until this point, a non-HFA aggregate
246 // can be split between regs and stack.
247 unsigned RegIdx = State.getFirstUnallocated(RegList);
248 for (auto &It : PendingMembers) {
249 if (RegIdx >= RegList.size())
250 It.convertToMem(State.AllocateStack(Size, Size));
251 else
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
253
254 State.addLoc(It);
255 }
256 PendingMembers.clear();
257 return true;
258 } else if (LocVT != MVT::i32)
259 RegList = SRegList;
260
261 // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core)
262 for (auto Reg : RegList)
263 State.AllocateReg(Reg);
264
265 // After the first item has been allocated, the rest are packed as tightly as
266 // possible. (E.g. an incoming i64 would have starting Align of 8, but we'll
267 // be allocating a bunch of i32 slots).
268 unsigned RestAlign = std::min(Align, Size);
269
270 for (auto &It : PendingMembers) {
271 It.convertToMem(State.AllocateStack(Size, Align));
272 State.addLoc(It);
273 Align = RestAlign;
274 }
275
276 // All pending members have now been allocated
277 PendingMembers.clear();
278
279 // This will be allocated by the last member of the aggregate
280 return true;
281}
282
283// Include the table generated calling convention implementations.
284#include "ARMGenCallingConv.inc"