Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 5004, column 7
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/build-llvm/lib/Target/ARM -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-07-24-235614-16331-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/IntrinsicsARM.h"
83#include "llvm/IR/Module.h"
84#include "llvm/IR/PatternMatch.h"
85#include "llvm/IR/Type.h"
86#include "llvm/IR/User.h"
87#include "llvm/IR/Value.h"
88#include "llvm/MC/MCInstrDesc.h"
89#include "llvm/MC/MCInstrItineraries.h"
90#include "llvm/MC/MCRegisterInfo.h"
91#include "llvm/MC/MCSchedule.h"
92#include "llvm/Support/AtomicOrdering.h"
93#include "llvm/Support/BranchProbability.h"
94#include "llvm/Support/Casting.h"
95#include "llvm/Support/CodeGen.h"
96#include "llvm/Support/CommandLine.h"
97#include "llvm/Support/Compiler.h"
98#include "llvm/Support/Debug.h"
99#include "llvm/Support/ErrorHandling.h"
100#include "llvm/Support/KnownBits.h"
101#include "llvm/Support/MachineValueType.h"
102#include "llvm/Support/MathExtras.h"
103#include "llvm/Support/raw_ostream.h"
104#include "llvm/Target/TargetMachine.h"
105#include "llvm/Target/TargetOptions.h"
106#include <algorithm>
107#include <cassert>
108#include <cstdint>
109#include <cstdlib>
110#include <iterator>
111#include <limits>
112#include <string>
113#include <tuple>
114#include <utility>
115#include <vector>
116
117using namespace llvm;
118using namespace llvm::PatternMatch;
119
120#define DEBUG_TYPE"arm-isel" "arm-isel"
121
122STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
123STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
124STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
125STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
126 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
127
128static cl::opt<bool>
129ARMInterworking("arm-interworking", cl::Hidden,
130 cl::desc("Enable / disable ARM interworking (for debugging only)"),
131 cl::init(true));
132
133static cl::opt<bool> EnableConstpoolPromotion(
134 "arm-promote-constant", cl::Hidden,
135 cl::desc("Enable / disable promotion of unnamed_addr constants into "
136 "constant pools"),
137 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
138static cl::opt<unsigned> ConstpoolPromotionMaxSize(
139 "arm-promote-constant-max-size", cl::Hidden,
140 cl::desc("Maximum size of constant to promote into a constant pool"),
141 cl::init(64));
142static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
143 "arm-promote-constant-max-total", cl::Hidden,
144 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
145 cl::init(128));
146
147cl::opt<unsigned>
148MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
149 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
150 cl::init(2));
151
152// The APCS parameter registers.
153static const MCPhysReg GPRArgRegs[] = {
154 ARM::R0, ARM::R1, ARM::R2, ARM::R3
155};
156
157void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Neon does not support vector divide/remainder operations.
197 setOperationAction(ISD::SDIV, VT, Expand);
198 setOperationAction(ISD::UDIV, VT, Expand);
199 setOperationAction(ISD::FDIV, VT, Expand);
200 setOperationAction(ISD::SREM, VT, Expand);
201 setOperationAction(ISD::UREM, VT, Expand);
202 setOperationAction(ISD::FREM, VT, Expand);
203 setOperationAction(ISD::SDIVREM, VT, Expand);
204 setOperationAction(ISD::UDIVREM, VT, Expand);
205
206 if (!VT.isFloatingPoint() &&
207 VT != MVT::v2i64 && VT != MVT::v1i64)
208 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
209 setOperationAction(Opcode, VT, Legal);
210 if (!VT.isFloatingPoint())
211 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
212 setOperationAction(Opcode, VT, Legal);
213}
214
215void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
216 addRegisterClass(VT, &ARM::DPRRegClass);
217 addTypeForNEON(VT, MVT::f64);
218}
219
220void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
221 addRegisterClass(VT, &ARM::DPairRegClass);
222 addTypeForNEON(VT, MVT::v2f64);
223}
224
225void ARMTargetLowering::setAllExpand(MVT VT) {
226 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
227 setOperationAction(Opc, VT, Expand);
228
229 // We support these really simple operations even on types where all
230 // the actual arithmetic has to be broken down into simpler
231 // operations or turned into library calls.
232 setOperationAction(ISD::BITCAST, VT, Legal);
233 setOperationAction(ISD::LOAD, VT, Legal);
234 setOperationAction(ISD::STORE, VT, Legal);
235 setOperationAction(ISD::UNDEF, VT, Legal);
236}
237
238void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
239 LegalizeAction Action) {
240 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
241 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
243}
244
245void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
246 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
247
248 for (auto VT : IntTypes) {
249 addRegisterClass(VT, &ARM::MQPRRegClass);
250 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
251 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
252 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
254 setOperationAction(ISD::SHL, VT, Custom);
255 setOperationAction(ISD::SRA, VT, Custom);
256 setOperationAction(ISD::SRL, VT, Custom);
257 setOperationAction(ISD::SMIN, VT, Legal);
258 setOperationAction(ISD::SMAX, VT, Legal);
259 setOperationAction(ISD::UMIN, VT, Legal);
260 setOperationAction(ISD::UMAX, VT, Legal);
261 setOperationAction(ISD::ABS, VT, Legal);
262 setOperationAction(ISD::SETCC, VT, Custom);
263 setOperationAction(ISD::MLOAD, VT, Custom);
264 setOperationAction(ISD::MSTORE, VT, Legal);
265 setOperationAction(ISD::CTLZ, VT, Legal);
266 setOperationAction(ISD::CTTZ, VT, Custom);
267 setOperationAction(ISD::BITREVERSE, VT, Legal);
268 setOperationAction(ISD::BSWAP, VT, Legal);
269 setOperationAction(ISD::SADDSAT, VT, Legal);
270 setOperationAction(ISD::UADDSAT, VT, Legal);
271 setOperationAction(ISD::SSUBSAT, VT, Legal);
272 setOperationAction(ISD::USUBSAT, VT, Legal);
273 setOperationAction(ISD::ABDS, VT, Legal);
274 setOperationAction(ISD::ABDU, VT, Legal);
275
276 // No native support for these.
277 setOperationAction(ISD::UDIV, VT, Expand);
278 setOperationAction(ISD::SDIV, VT, Expand);
279 setOperationAction(ISD::UREM, VT, Expand);
280 setOperationAction(ISD::SREM, VT, Expand);
281 setOperationAction(ISD::UDIVREM, VT, Expand);
282 setOperationAction(ISD::SDIVREM, VT, Expand);
283 setOperationAction(ISD::CTPOP, VT, Expand);
284 setOperationAction(ISD::SELECT, VT, Expand);
285 setOperationAction(ISD::SELECT_CC, VT, Expand);
286
287 // Vector reductions
288 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
289 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
290 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
291 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
292 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
293 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
294 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
295 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
296 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
297
298 if (!HasMVEFP) {
299 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
300 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
301 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
302 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
303 }
304
305 // Pre and Post inc are supported on loads and stores
306 for (unsigned im = (unsigned)ISD::PRE_INC;
307 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
308 setIndexedLoadAction(im, VT, Legal);
309 setIndexedStoreAction(im, VT, Legal);
310 setIndexedMaskedLoadAction(im, VT, Legal);
311 setIndexedMaskedStoreAction(im, VT, Legal);
312 }
313 }
314
315 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
316 for (auto VT : FloatTypes) {
317 addRegisterClass(VT, &ARM::MQPRRegClass);
318 if (!HasMVEFP)
319 setAllExpand(VT);
320
321 // These are legal or custom whether we have MVE.fp or not
322 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
323 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
324 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
326 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
327 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
329 setOperationAction(ISD::SETCC, VT, Custom);
330 setOperationAction(ISD::MLOAD, VT, Custom);
331 setOperationAction(ISD::MSTORE, VT, Legal);
332 setOperationAction(ISD::SELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334
335 // Pre and Post inc are supported on loads and stores
336 for (unsigned im = (unsigned)ISD::PRE_INC;
337 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
338 setIndexedLoadAction(im, VT, Legal);
339 setIndexedStoreAction(im, VT, Legal);
340 setIndexedMaskedLoadAction(im, VT, Legal);
341 setIndexedMaskedStoreAction(im, VT, Legal);
342 }
343
344 if (HasMVEFP) {
345 setOperationAction(ISD::FMINNUM, VT, Legal);
346 setOperationAction(ISD::FMAXNUM, VT, Legal);
347 setOperationAction(ISD::FROUND, VT, Legal);
348 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
349 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
350 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
351 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
352
353 // No native support for these.
354 setOperationAction(ISD::FDIV, VT, Expand);
355 setOperationAction(ISD::FREM, VT, Expand);
356 setOperationAction(ISD::FSQRT, VT, Expand);
357 setOperationAction(ISD::FSIN, VT, Expand);
358 setOperationAction(ISD::FCOS, VT, Expand);
359 setOperationAction(ISD::FPOW, VT, Expand);
360 setOperationAction(ISD::FLOG, VT, Expand);
361 setOperationAction(ISD::FLOG2, VT, Expand);
362 setOperationAction(ISD::FLOG10, VT, Expand);
363 setOperationAction(ISD::FEXP, VT, Expand);
364 setOperationAction(ISD::FEXP2, VT, Expand);
365 setOperationAction(ISD::FNEARBYINT, VT, Expand);
366 }
367 }
368
369 // Custom Expand smaller than legal vector reductions to prevent false zero
370 // items being added.
371 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
372 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
373 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
374 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
375 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
376 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
377 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
378 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
379
380 // We 'support' these types up to bitcast/load/store level, regardless of
381 // MVE integer-only / float support. Only doing FP data processing on the FP
382 // vector types is inhibited at integer-only level.
383 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
384 for (auto VT : LongTypes) {
385 addRegisterClass(VT, &ARM::MQPRRegClass);
386 setAllExpand(VT);
387 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
389 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
390 }
391 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
392
393 // We can do bitwise operations on v2i64 vectors
394 setOperationAction(ISD::AND, MVT::v2i64, Legal);
395 setOperationAction(ISD::OR, MVT::v2i64, Legal);
396 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
397
398 // It is legal to extload from v4i8 to v4i16 or v4i32.
399 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
400 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
401 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
402
403 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
409
410 // Some truncating stores are legal too.
411 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
412 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
413 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
414
415 // Pre and Post inc on these are legal, given the correct extends
416 for (unsigned im = (unsigned)ISD::PRE_INC;
417 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
418 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
419 setIndexedLoadAction(im, VT, Legal);
420 setIndexedStoreAction(im, VT, Legal);
421 setIndexedMaskedLoadAction(im, VT, Legal);
422 setIndexedMaskedStoreAction(im, VT, Legal);
423 }
424 }
425
426 // Predicate types
427 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
428 for (auto VT : pTypes) {
429 addRegisterClass(VT, &ARM::VCCRRegClass);
430 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
431 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
433 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
434 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
435 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
436 setOperationAction(ISD::SETCC, VT, Custom);
437 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
438 setOperationAction(ISD::LOAD, VT, Custom);
439 setOperationAction(ISD::STORE, VT, Custom);
440 setOperationAction(ISD::TRUNCATE, VT, Custom);
441 setOperationAction(ISD::VSELECT, VT, Expand);
442 setOperationAction(ISD::SELECT, VT, Expand);
443 }
444 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
445 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
446 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
447 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
448 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
449 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
450 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
451 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
452}
453
454ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
455 const ARMSubtarget &STI)
456 : TargetLowering(TM), Subtarget(&STI) {
457 RegInfo = Subtarget->getRegisterInfo();
458 Itins = Subtarget->getInstrItineraryData();
459
460 setBooleanContents(ZeroOrOneBooleanContent);
461 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
462
463 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
464 !Subtarget->isTargetWatchOS()) {
465 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
466 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
467 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
468 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
469 : CallingConv::ARM_AAPCS);
470 }
471
472 if (Subtarget->isTargetMachO()) {
473 // Uses VFP for Thumb libfuncs if available.
474 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
475 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
476 static const struct {
477 const RTLIB::Libcall Op;
478 const char * const Name;
479 const ISD::CondCode Cond;
480 } LibraryCalls[] = {
481 // Single-precision floating-point arithmetic.
482 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
483 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
484 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
485 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
486
487 // Double-precision floating-point arithmetic.
488 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
489 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
490 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
491 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
492
493 // Single-precision comparisons.
494 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
495 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
496 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
497 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
498 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
499 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
500 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
501
502 // Double-precision comparisons.
503 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
504 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
505 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
506 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
507 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
508 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
509 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
510
511 // Floating-point to integer conversions.
512 // i64 conversions are done via library routines even when generating VFP
513 // instructions, so use the same ones.
514 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
515 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
516 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
517 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
518
519 // Conversions between floating types.
520 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
521 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
522
523 // Integer to floating-point conversions.
524 // i64 conversions are done via library routines even when generating VFP
525 // instructions, so use the same ones.
526 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
527 // e.g., __floatunsidf vs. __floatunssidfvfp.
528 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
529 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
530 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
531 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
532 };
533
534 for (const auto &LC : LibraryCalls) {
535 setLibcallName(LC.Op, LC.Name);
536 if (LC.Cond != ISD::SETCC_INVALID)
537 setCmpLibcallCC(LC.Op, LC.Cond);
538 }
539 }
540 }
541
542 // These libcalls are not available in 32-bit.
543 setLibcallName(RTLIB::SHL_I128, nullptr);
544 setLibcallName(RTLIB::SRL_I128, nullptr);
545 setLibcallName(RTLIB::SRA_I128, nullptr);
546 setLibcallName(RTLIB::MUL_I128, nullptr);
547
548 // RTLIB
549 if (Subtarget->isAAPCS_ABI() &&
550 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
551 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
552 static const struct {
553 const RTLIB::Libcall Op;
554 const char * const Name;
555 const CallingConv::ID CC;
556 const ISD::CondCode Cond;
557 } LibraryCalls[] = {
558 // Double-precision floating-point arithmetic helper functions
559 // RTABI chapter 4.1.2, Table 2
560 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
561 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
562 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
563 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564
565 // Double-precision floating-point comparison helper functions
566 // RTABI chapter 4.1.2, Table 3
567 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
568 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
569 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
570 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
571 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
572 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
573 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
574
575 // Single-precision floating-point arithmetic helper functions
576 // RTABI chapter 4.1.2, Table 4
577 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
578 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
579 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
580 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581
582 // Single-precision floating-point comparison helper functions
583 // RTABI chapter 4.1.2, Table 5
584 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
585 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
586 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
587 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
588 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
589 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
590 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
591
592 // Floating-point to integer conversions.
593 // RTABI chapter 4.1.2, Table 6
594 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
595 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
600 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
601 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602
603 // Conversions between floating types.
604 // RTABI chapter 4.1.2, Table 7
605 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
606 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
607 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608
609 // Integer to floating-point conversions.
610 // RTABI chapter 4.1.2, Table 8
611 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
612 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
617 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
618 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
619
620 // Long long helper functions
621 // RTABI chapter 4.2, Table 9
622 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
623 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
624 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626
627 // Integer division functions
628 // RTABI chapter 4.3.1
629 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
634 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
635 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 };
638
639 for (const auto &LC : LibraryCalls) {
640 setLibcallName(LC.Op, LC.Name);
641 setLibcallCallingConv(LC.Op, LC.CC);
642 if (LC.Cond != ISD::SETCC_INVALID)
643 setCmpLibcallCC(LC.Op, LC.Cond);
644 }
645
646 // EABI dependent RTLIB
647 if (TM.Options.EABIVersion == EABI::EABI4 ||
648 TM.Options.EABIVersion == EABI::EABI5) {
649 static const struct {
650 const RTLIB::Libcall Op;
651 const char *const Name;
652 const CallingConv::ID CC;
653 const ISD::CondCode Cond;
654 } MemOpsLibraryCalls[] = {
655 // Memory operations
656 // RTABI chapter 4.3.4
657 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
658 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
659 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
660 };
661
662 for (const auto &LC : MemOpsLibraryCalls) {
663 setLibcallName(LC.Op, LC.Name);
664 setLibcallCallingConv(LC.Op, LC.CC);
665 if (LC.Cond != ISD::SETCC_INVALID)
666 setCmpLibcallCC(LC.Op, LC.Cond);
667 }
668 }
669 }
670
671 if (Subtarget->isTargetWindows()) {
672 static const struct {
673 const RTLIB::Libcall Op;
674 const char * const Name;
675 const CallingConv::ID CC;
676 } LibraryCalls[] = {
677 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
678 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
679 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
680 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
681 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
682 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
683 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
684 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
685 };
686
687 for (const auto &LC : LibraryCalls) {
688 setLibcallName(LC.Op, LC.Name);
689 setLibcallCallingConv(LC.Op, LC.CC);
690 }
691 }
692
693 // Use divmod compiler-rt calls for iOS 5.0 and later.
694 if (Subtarget->isTargetMachO() &&
695 !(Subtarget->isTargetIOS() &&
696 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
697 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
698 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
699 }
700
701 // The half <-> float conversion functions are always soft-float on
702 // non-watchos platforms, but are needed for some targets which use a
703 // hard-float calling convention by default.
704 if (!Subtarget->isTargetWatchABI()) {
705 if (Subtarget->isAAPCS_ABI()) {
706 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
707 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
708 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
709 } else {
710 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
711 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
712 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
713 }
714 }
715
716 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
717 // a __gnu_ prefix (which is the default).
718 if (Subtarget->isTargetAEABI()) {
719 static const struct {
720 const RTLIB::Libcall Op;
721 const char * const Name;
722 const CallingConv::ID CC;
723 } LibraryCalls[] = {
724 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
725 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
726 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
727 };
728
729 for (const auto &LC : LibraryCalls) {
730 setLibcallName(LC.Op, LC.Name);
731 setLibcallCallingConv(LC.Op, LC.CC);
732 }
733 }
734
735 if (Subtarget->isThumb1Only())
736 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
737 else
738 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
739
740 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
741 Subtarget->hasFPRegs()) {
742 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
743 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
744 if (!Subtarget->hasVFP2Base())
745 setAllExpand(MVT::f32);
746 if (!Subtarget->hasFP64())
747 setAllExpand(MVT::f64);
748 }
749
750 if (Subtarget->hasFullFP16()) {
751 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
752 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
753 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
754
755 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
756 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
757 }
758
759 if (Subtarget->hasBF16()) {
760 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
761 setAllExpand(MVT::bf16);
762 if (!Subtarget->hasFullFP16())
763 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
764 }
765
766 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
767 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
768 setTruncStoreAction(VT, InnerVT, Expand);
769 addAllExtLoads(VT, InnerVT, Expand);
770 }
771
772 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
773 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
774
775 setOperationAction(ISD::BSWAP, VT, Expand);
776 }
777
778 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
779 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
780
781 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
782 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
783
784 if (Subtarget->hasMVEIntegerOps())
785 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
786
787 // Combine low-overhead loop intrinsics so that we can lower i1 types.
788 if (Subtarget->hasLOB()) {
789 setTargetDAGCombine(ISD::BRCOND);
790 setTargetDAGCombine(ISD::BR_CC);
791 }
792
793 if (Subtarget->hasNEON()) {
794 addDRTypeForNEON(MVT::v2f32);
795 addDRTypeForNEON(MVT::v8i8);
796 addDRTypeForNEON(MVT::v4i16);
797 addDRTypeForNEON(MVT::v2i32);
798 addDRTypeForNEON(MVT::v1i64);
799
800 addQRTypeForNEON(MVT::v4f32);
801 addQRTypeForNEON(MVT::v2f64);
802 addQRTypeForNEON(MVT::v16i8);
803 addQRTypeForNEON(MVT::v8i16);
804 addQRTypeForNEON(MVT::v4i32);
805 addQRTypeForNEON(MVT::v2i64);
806
807 if (Subtarget->hasFullFP16()) {
808 addQRTypeForNEON(MVT::v8f16);
809 addDRTypeForNEON(MVT::v4f16);
810 }
811
812 if (Subtarget->hasBF16()) {
813 addQRTypeForNEON(MVT::v8bf16);
814 addDRTypeForNEON(MVT::v4bf16);
815 }
816 }
817
818 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
819 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
820 // none of Neon, MVE or VFP supports any arithmetic operations on it.
821 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
822 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
823 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
824 // FIXME: Code duplication: FDIV and FREM are expanded always, see
825 // ARMTargetLowering::addTypeForNEON method for details.
826 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
827 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
828 // FIXME: Create unittest.
829 // In another words, find a way when "copysign" appears in DAG with vector
830 // operands.
831 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
832 // FIXME: Code duplication: SETCC has custom operation action, see
833 // ARMTargetLowering::addTypeForNEON method for details.
834 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
835 // FIXME: Create unittest for FNEG and for FABS.
836 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
837 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
838 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
839 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
840 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
841 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
842 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
843 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
844 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
845 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
846 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
847 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
848 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
849 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
850 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
851 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
852 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
853 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
854 }
855
856 if (Subtarget->hasNEON()) {
857 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
858 // supported for v4f32.
859 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
860 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
861 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
862 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
863 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
864 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
865 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
866 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
867 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
868 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
869 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
870 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
871 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
872 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
873
874 // Mark v2f32 intrinsics.
875 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
876 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
877 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
878 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
879 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
880 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
881 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
882 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
883 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
884 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
885 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
886 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
887 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
888 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
889
890 // Neon does not support some operations on v1i64 and v2i64 types.
891 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
892 // Custom handling for some quad-vector types to detect VMULL.
893 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
894 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
895 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
896 // Custom handling for some vector types to avoid expensive expansions
897 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
898 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
899 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
900 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
901 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
902 // a destination type that is wider than the source, and nor does
903 // it have a FP_TO_[SU]INT instruction with a narrower destination than
904 // source.
905 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
906 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
907 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
908 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
909 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
910 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
911 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
912 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
913
914 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
915 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
916
917 // NEON does not have single instruction CTPOP for vectors with element
918 // types wider than 8-bits. However, custom lowering can leverage the
919 // v8i8/v16i8 vcnt instruction.
920 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
921 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
922 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
923 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
924 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
925 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
926
927 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
928 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
929
930 // NEON does not have single instruction CTTZ for vectors.
931 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
932 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
933 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
934 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
935
936 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
937 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
938 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
939 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
940
941 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
942 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
943 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
944 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
945
946 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
947 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
948 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
949 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
950
951 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
952 setOperationAction(ISD::MULHS, VT, Expand);
953 setOperationAction(ISD::MULHU, VT, Expand);
954 }
955
956 // NEON only has FMA instructions as of VFP4.
957 if (!Subtarget->hasVFP4Base()) {
958 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
959 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
960 }
961
962 setTargetDAGCombine(ISD::SHL);
963 setTargetDAGCombine(ISD::SRL);
964 setTargetDAGCombine(ISD::SRA);
965 setTargetDAGCombine(ISD::FP_TO_SINT);
966 setTargetDAGCombine(ISD::FP_TO_UINT);
967 setTargetDAGCombine(ISD::FDIV);
968 setTargetDAGCombine(ISD::LOAD);
969
970 // It is legal to extload from v4i8 to v4i16 or v4i32.
971 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
972 MVT::v2i32}) {
973 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
974 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
977 }
978 }
979 }
980
981 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
982 setTargetDAGCombine(ISD::BUILD_VECTOR);
983 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
984 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
985 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
986 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
987 setTargetDAGCombine(ISD::STORE);
988 setTargetDAGCombine(ISD::SIGN_EXTEND);
989 setTargetDAGCombine(ISD::ZERO_EXTEND);
990 setTargetDAGCombine(ISD::ANY_EXTEND);
991 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
992 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
993 setTargetDAGCombine(ISD::INTRINSIC_VOID);
994 setTargetDAGCombine(ISD::VECREDUCE_ADD);
995 setTargetDAGCombine(ISD::ADD);
996 setTargetDAGCombine(ISD::BITCAST);
997 }
998 if (Subtarget->hasMVEIntegerOps()) {
999 setTargetDAGCombine(ISD::SMIN);
1000 setTargetDAGCombine(ISD::UMIN);
1001 setTargetDAGCombine(ISD::SMAX);
1002 setTargetDAGCombine(ISD::UMAX);
1003 setTargetDAGCombine(ISD::FP_EXTEND);
1004 setTargetDAGCombine(ISD::SELECT);
1005 setTargetDAGCombine(ISD::SELECT_CC);
1006 }
1007
1008 if (!Subtarget->hasFP64()) {
1009 // When targeting a floating-point unit with only single-precision
1010 // operations, f64 is legal for the few double-precision instructions which
1011 // are present However, no double-precision operations other than moves,
1012 // loads and stores are provided by the hardware.
1013 setOperationAction(ISD::FADD, MVT::f64, Expand);
1014 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1015 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1016 setOperationAction(ISD::FMA, MVT::f64, Expand);
1017 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1018 setOperationAction(ISD::FREM, MVT::f64, Expand);
1019 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1020 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1021 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1022 setOperationAction(ISD::FABS, MVT::f64, Expand);
1023 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1024 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1025 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1026 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1027 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1028 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1029 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1030 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1031 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1032 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1033 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1034 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1035 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1036 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1037 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1038 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1040 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1041 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1042 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1043 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1044 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1045 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1046 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1047 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1048 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1049 }
1050
1051 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1052 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1053 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1054 if (Subtarget->hasFullFP16()) {
1055 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1056 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1057 }
1058 }
1059
1060 if (!Subtarget->hasFP16()) {
1061 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1062 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1063 }
1064
1065 computeRegisterProperties(Subtarget->getRegisterInfo());
1066
1067 // ARM does not have floating-point extending loads.
1068 for (MVT VT : MVT::fp_valuetypes()) {
1069 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1070 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1071 }
1072
1073 // ... or truncating stores
1074 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1075 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1076 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1077
1078 // ARM does not have i1 sign extending load.
1079 for (MVT VT : MVT::integer_valuetypes())
1080 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1081
1082 // ARM supports all 4 flavors of integer indexed load / store.
1083 if (!Subtarget->isThumb1Only()) {
1084 for (unsigned im = (unsigned)ISD::PRE_INC;
1085 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1086 setIndexedLoadAction(im, MVT::i1, Legal);
1087 setIndexedLoadAction(im, MVT::i8, Legal);
1088 setIndexedLoadAction(im, MVT::i16, Legal);
1089 setIndexedLoadAction(im, MVT::i32, Legal);
1090 setIndexedStoreAction(im, MVT::i1, Legal);
1091 setIndexedStoreAction(im, MVT::i8, Legal);
1092 setIndexedStoreAction(im, MVT::i16, Legal);
1093 setIndexedStoreAction(im, MVT::i32, Legal);
1094 }
1095 } else {
1096 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1097 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1098 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1099 }
1100
1101 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1102 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1103 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1104 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1105
1106 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1107 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1108 if (Subtarget->hasDSP()) {
1109 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1110 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1111 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1112 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1113 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1114 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1115 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1116 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1117 }
1118 if (Subtarget->hasBaseDSP()) {
1119 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1120 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1121 }
1122
1123 // i64 operation support.
1124 setOperationAction(ISD::MUL, MVT::i64, Expand);
1125 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1126 if (Subtarget->isThumb1Only()) {
1127 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1128 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1129 }
1130 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1131 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1132 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1133
1134 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1135 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1136 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1137 setOperationAction(ISD::SRL, MVT::i64, Custom);
1138 setOperationAction(ISD::SRA, MVT::i64, Custom);
1139 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1140 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1141 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1142 setOperationAction(ISD::STORE, MVT::i64, Custom);
1143
1144 // MVE lowers 64 bit shifts to lsll and lsrl
1145 // assuming that ISD::SRL and SRA of i64 are already marked custom
1146 if (Subtarget->hasMVEIntegerOps())
1147 setOperationAction(ISD::SHL, MVT::i64, Custom);
1148
1149 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1150 if (Subtarget->isThumb1Only()) {
1151 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1152 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1153 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1154 }
1155
1156 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1157 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1158
1159 // ARM does not have ROTL.
1160 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1161 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1162 setOperationAction(ISD::ROTL, VT, Expand);
1163 setOperationAction(ISD::ROTR, VT, Expand);
1164 }
1165 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1166 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1167 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1168 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1169 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1170 }
1171
1172 // @llvm.readcyclecounter requires the Performance Monitors extension.
1173 // Default to the 0 expansion on unsupported platforms.
1174 // FIXME: Technically there are older ARM CPUs that have
1175 // implementation-specific ways of obtaining this information.
1176 if (Subtarget->hasPerfMon())
1177 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1178
1179 // Only ARMv6 has BSWAP.
1180 if (!Subtarget->hasV6Ops())
1181 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1182
1183 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1184 : Subtarget->hasDivideInARMMode();
1185 if (!hasDivide) {
1186 // These are expanded into libcalls if the cpu doesn't have HW divider.
1187 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1188 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1189 }
1190
1191 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1192 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1193 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1194
1195 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1196 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1197 }
1198
1199 setOperationAction(ISD::SREM, MVT::i32, Expand);
1200 setOperationAction(ISD::UREM, MVT::i32, Expand);
1201
1202 // Register based DivRem for AEABI (RTABI 4.2)
1203 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1204 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1205 Subtarget->isTargetWindows()) {
1206 setOperationAction(ISD::SREM, MVT::i64, Custom);
1207 setOperationAction(ISD::UREM, MVT::i64, Custom);
1208 HasStandaloneRem = false;
1209
1210 if (Subtarget->isTargetWindows()) {
1211 const struct {
1212 const RTLIB::Libcall Op;
1213 const char * const Name;
1214 const CallingConv::ID CC;
1215 } LibraryCalls[] = {
1216 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1217 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1218 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1219 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1220
1221 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1222 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1223 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1224 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1225 };
1226
1227 for (const auto &LC : LibraryCalls) {
1228 setLibcallName(LC.Op, LC.Name);
1229 setLibcallCallingConv(LC.Op, LC.CC);
1230 }
1231 } else {
1232 const struct {
1233 const RTLIB::Libcall Op;
1234 const char * const Name;
1235 const CallingConv::ID CC;
1236 } LibraryCalls[] = {
1237 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1238 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1239 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1240 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1241
1242 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1243 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1244 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1245 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1246 };
1247
1248 for (const auto &LC : LibraryCalls) {
1249 setLibcallName(LC.Op, LC.Name);
1250 setLibcallCallingConv(LC.Op, LC.CC);
1251 }
1252 }
1253
1254 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1255 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1256 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1257 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1258 } else {
1259 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1260 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1261 }
1262
1263 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1264 // MSVCRT doesn't have powi; fall back to pow
1265 setLibcallName(RTLIB::POWI_F32, nullptr);
1266 setLibcallName(RTLIB::POWI_F64, nullptr);
1267 }
1268
1269 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1270 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1271 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1272 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1273
1274 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1275 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1276
1277 // Use the default implementation.
1278 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1279 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1280 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1281 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1282 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1283 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1284
1285 if (Subtarget->isTargetWindows())
1286 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1287 else
1288 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1289
1290 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1291 // the default expansion.
1292 InsertFencesForAtomic = false;
1293 if (Subtarget->hasAnyDataBarrier() &&
1294 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1295 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1296 // to ldrex/strex loops already.
1297 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1298 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1299 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1300
1301 // On v8, we have particularly efficient implementations of atomic fences
1302 // if they can be combined with nearby atomic loads and stores.
1303 if (!Subtarget->hasAcquireRelease() ||
1304 getTargetMachine().getOptLevel() == 0) {
1305 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1306 InsertFencesForAtomic = true;
1307 }
1308 } else {
1309 // If there's anything we can use as a barrier, go through custom lowering
1310 // for ATOMIC_FENCE.
1311 // If target has DMB in thumb, Fences can be inserted.
1312 if (Subtarget->hasDataBarrier())
1313 InsertFencesForAtomic = true;
1314
1315 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1316 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1317
1318 // Set them all for expansion, which will force libcalls.
1319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1320 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1327 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1328 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1329 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1330 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1331 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1332 // Unordered/Monotonic case.
1333 if (!InsertFencesForAtomic) {
1334 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1335 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1336 }
1337 }
1338
1339 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1340
1341 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1342 if (!Subtarget->hasV6Ops()) {
1343 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1344 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1345 }
1346 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1347
1348 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1349 !Subtarget->isThumb1Only()) {
1350 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1351 // iff target supports vfp2.
1352 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1353 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1354 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1355 }
1356
1357 // We want to custom lower some of our intrinsics.
1358 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1359 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1360 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1361 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1362 if (Subtarget->useSjLjEH())
1363 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1364
1365 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1366 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1367 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1368 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1369 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1370 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1371 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1372 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1373 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1374 if (Subtarget->hasFullFP16()) {
1375 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1376 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1377 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1378 }
1379
1380 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1381
1382 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1383 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1384 if (Subtarget->hasFullFP16())
1385 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1386 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1387 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1388 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1389
1390 // We don't support sin/cos/fmod/copysign/pow
1391 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1392 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1393 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1394 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1395 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1396 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1397 setOperationAction(ISD::FREM, MVT::f64, Expand);
1398 setOperationAction(ISD::FREM, MVT::f32, Expand);
1399 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1400 !Subtarget->isThumb1Only()) {
1401 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1402 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1403 }
1404 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1405 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1406
1407 if (!Subtarget->hasVFP4Base()) {
1408 setOperationAction(ISD::FMA, MVT::f64, Expand);
1409 setOperationAction(ISD::FMA, MVT::f32, Expand);
1410 }
1411
1412 // Various VFP goodness
1413 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1414 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1415 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1416 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1417 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1418 }
1419
1420 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1421 if (!Subtarget->hasFP16()) {
1422 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1423 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1424 }
1425
1426 // Strict floating-point comparisons need custom lowering.
1427 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1428 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1429 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1430 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1431 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1432 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1433 }
1434
1435 // Use __sincos_stret if available.
1436 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1437 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1438 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1439 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1440 }
1441
1442 // FP-ARMv8 implements a lot of rounding-like FP operations.
1443 if (Subtarget->hasFPARMv8Base()) {
1444 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1445 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1446 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1447 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1448 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1449 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1450 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1451 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1452 if (Subtarget->hasNEON()) {
1453 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1454 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1455 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1456 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1457 }
1458
1459 if (Subtarget->hasFP64()) {
1460 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1461 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1462 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1463 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1464 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1465 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1466 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1467 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1468 }
1469 }
1470
1471 // FP16 often need to be promoted to call lib functions
1472 if (Subtarget->hasFullFP16()) {
1473 setOperationAction(ISD::FREM, MVT::f16, Promote);
1474 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1475 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1476 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1477 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1478 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1479 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1480 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1481 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1482 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1483 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1484 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1485
1486 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1487 }
1488
1489 if (Subtarget->hasNEON()) {
1490 // vmin and vmax aren't available in a scalar form, so we can use
1491 // a NEON instruction with an undef lane instead. This has a performance
1492 // penalty on some cores, so we don't do this unless we have been
1493 // asked to by the core tuning model.
1494 if (Subtarget->useNEONForSinglePrecisionFP()) {
1495 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1496 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1497 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1498 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1499 }
1500 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1501 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1502 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1503 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1504
1505 if (Subtarget->hasFullFP16()) {
1506 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1507 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1508 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1509 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1510
1511 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1512 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1513 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1514 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1515 }
1516 }
1517
1518 // We have target-specific dag combine patterns for the following nodes:
1519 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1520 setTargetDAGCombine(ISD::ADD);
1521 setTargetDAGCombine(ISD::SUB);
1522 setTargetDAGCombine(ISD::MUL);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::OR);
1525 setTargetDAGCombine(ISD::XOR);
1526
1527 if (Subtarget->hasMVEIntegerOps())
1528 setTargetDAGCombine(ISD::VSELECT);
1529
1530 if (Subtarget->hasV6Ops())
1531 setTargetDAGCombine(ISD::SRL);
1532 if (Subtarget->isThumb1Only())
1533 setTargetDAGCombine(ISD::SHL);
1534
1535 setStackPointerRegisterToSaveRestore(ARM::SP);
1536
1537 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1538 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1539 setSchedulingPreference(Sched::RegPressure);
1540 else
1541 setSchedulingPreference(Sched::Hybrid);
1542
1543 //// temporary - rewrite interface to use type
1544 MaxStoresPerMemset = 8;
1545 MaxStoresPerMemsetOptSize = 4;
1546 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1547 MaxStoresPerMemcpyOptSize = 2;
1548 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1549 MaxStoresPerMemmoveOptSize = 2;
1550
1551 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1552 // are at least 4 bytes aligned.
1553 setMinStackArgumentAlignment(Align(4));
1554
1555 // Prefer likely predicted branches to selects on out-of-order cores.
1556 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1557
1558 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1559
1560 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1561
1562 if (Subtarget->isThumb() || Subtarget->isThumb2())
1563 setTargetDAGCombine(ISD::ABS);
1564}
1565
1566bool ARMTargetLowering::useSoftFloat() const {
1567 return Subtarget->useSoftFloat();
1568}
1569
1570// FIXME: It might make sense to define the representative register class as the
1571// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1572// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1573// SPR's representative would be DPR_VFP2. This should work well if register
1574// pressure tracking were modified such that a register use would increment the
1575// pressure of the register class's representative and all of it's super
1576// classes' representatives transitively. We have not implemented this because
1577// of the difficulty prior to coalescing of modeling operand register classes
1578// due to the common occurrence of cross class copies and subregister insertions
1579// and extractions.
1580std::pair<const TargetRegisterClass *, uint8_t>
1581ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1582 MVT VT) const {
1583 const TargetRegisterClass *RRC = nullptr;
1584 uint8_t Cost = 1;
1585 switch (VT.SimpleTy) {
1586 default:
1587 return TargetLowering::findRepresentativeClass(TRI, VT);
1588 // Use DPR as representative register class for all floating point
1589 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1590 // the cost is 1 for both f32 and f64.
1591 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1592 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1593 RRC = &ARM::DPRRegClass;
1594 // When NEON is used for SP, only half of the register file is available
1595 // because operations that define both SP and DP results will be constrained
1596 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1597 // coalescing by double-counting the SP regs. See the FIXME above.
1598 if (Subtarget->useNEONForSinglePrecisionFP())
1599 Cost = 2;
1600 break;
1601 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1602 case MVT::v4f32: case MVT::v2f64:
1603 RRC = &ARM::DPRRegClass;
1604 Cost = 2;
1605 break;
1606 case MVT::v4i64:
1607 RRC = &ARM::DPRRegClass;
1608 Cost = 4;
1609 break;
1610 case MVT::v8i64:
1611 RRC = &ARM::DPRRegClass;
1612 Cost = 8;
1613 break;
1614 }
1615 return std::make_pair(RRC, Cost);
1616}
1617
1618const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1619#define MAKE_CASE(V) \
1620 case V: \
1621 return #V;
1622 switch ((ARMISD::NodeType)Opcode) {
1623 case ARMISD::FIRST_NUMBER:
1624 break;
1625 MAKE_CASE(ARMISD::Wrapper)
1626 MAKE_CASE(ARMISD::WrapperPIC)
1627 MAKE_CASE(ARMISD::WrapperJT)
1628 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1629 MAKE_CASE(ARMISD::CALL)
1630 MAKE_CASE(ARMISD::CALL_PRED)
1631 MAKE_CASE(ARMISD::CALL_NOLINK)
1632 MAKE_CASE(ARMISD::tSECALL)
1633 MAKE_CASE(ARMISD::BRCOND)
1634 MAKE_CASE(ARMISD::BR_JT)
1635 MAKE_CASE(ARMISD::BR2_JT)
1636 MAKE_CASE(ARMISD::RET_FLAG)
1637 MAKE_CASE(ARMISD::SERET_FLAG)
1638 MAKE_CASE(ARMISD::INTRET_FLAG)
1639 MAKE_CASE(ARMISD::PIC_ADD)
1640 MAKE_CASE(ARMISD::CMP)
1641 MAKE_CASE(ARMISD::CMN)
1642 MAKE_CASE(ARMISD::CMPZ)
1643 MAKE_CASE(ARMISD::CMPFP)
1644 MAKE_CASE(ARMISD::CMPFPE)
1645 MAKE_CASE(ARMISD::CMPFPw0)
1646 MAKE_CASE(ARMISD::CMPFPEw0)
1647 MAKE_CASE(ARMISD::BCC_i64)
1648 MAKE_CASE(ARMISD::FMSTAT)
1649 MAKE_CASE(ARMISD::CMOV)
1650 MAKE_CASE(ARMISD::SUBS)
1651 MAKE_CASE(ARMISD::SSAT)
1652 MAKE_CASE(ARMISD::USAT)
1653 MAKE_CASE(ARMISD::ASRL)
1654 MAKE_CASE(ARMISD::LSRL)
1655 MAKE_CASE(ARMISD::LSLL)
1656 MAKE_CASE(ARMISD::SRL_FLAG)
1657 MAKE_CASE(ARMISD::SRA_FLAG)
1658 MAKE_CASE(ARMISD::RRX)
1659 MAKE_CASE(ARMISD::ADDC)
1660 MAKE_CASE(ARMISD::ADDE)
1661 MAKE_CASE(ARMISD::SUBC)
1662 MAKE_CASE(ARMISD::SUBE)
1663 MAKE_CASE(ARMISD::LSLS)
1664 MAKE_CASE(ARMISD::VMOVRRD)
1665 MAKE_CASE(ARMISD::VMOVDRR)
1666 MAKE_CASE(ARMISD::VMOVhr)
1667 MAKE_CASE(ARMISD::VMOVrh)
1668 MAKE_CASE(ARMISD::VMOVSR)
1669 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1670 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1671 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1672 MAKE_CASE(ARMISD::TC_RETURN)
1673 MAKE_CASE(ARMISD::THREAD_POINTER)
1674 MAKE_CASE(ARMISD::DYN_ALLOC)
1675 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1676 MAKE_CASE(ARMISD::PRELOAD)
1677 MAKE_CASE(ARMISD::LDRD)
1678 MAKE_CASE(ARMISD::STRD)
1679 MAKE_CASE(ARMISD::WIN__CHKSTK)
1680 MAKE_CASE(ARMISD::WIN__DBZCHK)
1681 MAKE_CASE(ARMISD::PREDICATE_CAST)
1682 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1683 MAKE_CASE(ARMISD::MVESEXT)
1684 MAKE_CASE(ARMISD::MVEZEXT)
1685 MAKE_CASE(ARMISD::MVETRUNC)
1686 MAKE_CASE(ARMISD::VCMP)
1687 MAKE_CASE(ARMISD::VCMPZ)
1688 MAKE_CASE(ARMISD::VTST)
1689 MAKE_CASE(ARMISD::VSHLs)
1690 MAKE_CASE(ARMISD::VSHLu)
1691 MAKE_CASE(ARMISD::VSHLIMM)
1692 MAKE_CASE(ARMISD::VSHRsIMM)
1693 MAKE_CASE(ARMISD::VSHRuIMM)
1694 MAKE_CASE(ARMISD::VRSHRsIMM)
1695 MAKE_CASE(ARMISD::VRSHRuIMM)
1696 MAKE_CASE(ARMISD::VRSHRNIMM)
1697 MAKE_CASE(ARMISD::VQSHLsIMM)
1698 MAKE_CASE(ARMISD::VQSHLuIMM)
1699 MAKE_CASE(ARMISD::VQSHLsuIMM)
1700 MAKE_CASE(ARMISD::VQSHRNsIMM)
1701 MAKE_CASE(ARMISD::VQSHRNuIMM)
1702 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1703 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1704 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1705 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1706 MAKE_CASE(ARMISD::VSLIIMM)
1707 MAKE_CASE(ARMISD::VSRIIMM)
1708 MAKE_CASE(ARMISD::VGETLANEu)
1709 MAKE_CASE(ARMISD::VGETLANEs)
1710 MAKE_CASE(ARMISD::VMOVIMM)
1711 MAKE_CASE(ARMISD::VMVNIMM)
1712 MAKE_CASE(ARMISD::VMOVFPIMM)
1713 MAKE_CASE(ARMISD::VDUP)
1714 MAKE_CASE(ARMISD::VDUPLANE)
1715 MAKE_CASE(ARMISD::VEXT)
1716 MAKE_CASE(ARMISD::VREV64)
1717 MAKE_CASE(ARMISD::VREV32)
1718 MAKE_CASE(ARMISD::VREV16)
1719 MAKE_CASE(ARMISD::VZIP)
1720 MAKE_CASE(ARMISD::VUZP)
1721 MAKE_CASE(ARMISD::VTRN)
1722 MAKE_CASE(ARMISD::VTBL1)
1723 MAKE_CASE(ARMISD::VTBL2)
1724 MAKE_CASE(ARMISD::VMOVN)
1725 MAKE_CASE(ARMISD::VQMOVNs)
1726 MAKE_CASE(ARMISD::VQMOVNu)
1727 MAKE_CASE(ARMISD::VCVTN)
1728 MAKE_CASE(ARMISD::VCVTL)
1729 MAKE_CASE(ARMISD::VIDUP)
1730 MAKE_CASE(ARMISD::VMULLs)
1731 MAKE_CASE(ARMISD::VMULLu)
1732 MAKE_CASE(ARMISD::VQDMULH)
1733 MAKE_CASE(ARMISD::VADDVs)
1734 MAKE_CASE(ARMISD::VADDVu)
1735 MAKE_CASE(ARMISD::VADDVps)
1736 MAKE_CASE(ARMISD::VADDVpu)
1737 MAKE_CASE(ARMISD::VADDLVs)
1738 MAKE_CASE(ARMISD::VADDLVu)
1739 MAKE_CASE(ARMISD::VADDLVAs)
1740 MAKE_CASE(ARMISD::VADDLVAu)
1741 MAKE_CASE(ARMISD::VADDLVps)
1742 MAKE_CASE(ARMISD::VADDLVpu)
1743 MAKE_CASE(ARMISD::VADDLVAps)
1744 MAKE_CASE(ARMISD::VADDLVApu)
1745 MAKE_CASE(ARMISD::VMLAVs)
1746 MAKE_CASE(ARMISD::VMLAVu)
1747 MAKE_CASE(ARMISD::VMLAVps)
1748 MAKE_CASE(ARMISD::VMLAVpu)
1749 MAKE_CASE(ARMISD::VMLALVs)
1750 MAKE_CASE(ARMISD::VMLALVu)
1751 MAKE_CASE(ARMISD::VMLALVps)
1752 MAKE_CASE(ARMISD::VMLALVpu)
1753 MAKE_CASE(ARMISD::VMLALVAs)
1754 MAKE_CASE(ARMISD::VMLALVAu)
1755 MAKE_CASE(ARMISD::VMLALVAps)
1756 MAKE_CASE(ARMISD::VMLALVApu)
1757 MAKE_CASE(ARMISD::VMINVu)
1758 MAKE_CASE(ARMISD::VMINVs)
1759 MAKE_CASE(ARMISD::VMAXVu)
1760 MAKE_CASE(ARMISD::VMAXVs)
1761 MAKE_CASE(ARMISD::UMAAL)
1762 MAKE_CASE(ARMISD::UMLAL)
1763 MAKE_CASE(ARMISD::SMLAL)
1764 MAKE_CASE(ARMISD::SMLALBB)
1765 MAKE_CASE(ARMISD::SMLALBT)
1766 MAKE_CASE(ARMISD::SMLALTB)
1767 MAKE_CASE(ARMISD::SMLALTT)
1768 MAKE_CASE(ARMISD::SMULWB)
1769 MAKE_CASE(ARMISD::SMULWT)
1770 MAKE_CASE(ARMISD::SMLALD)
1771 MAKE_CASE(ARMISD::SMLALDX)
1772 MAKE_CASE(ARMISD::SMLSLD)
1773 MAKE_CASE(ARMISD::SMLSLDX)
1774 MAKE_CASE(ARMISD::SMMLAR)
1775 MAKE_CASE(ARMISD::SMMLSR)
1776 MAKE_CASE(ARMISD::QADD16b)
1777 MAKE_CASE(ARMISD::QSUB16b)
1778 MAKE_CASE(ARMISD::QADD8b)
1779 MAKE_CASE(ARMISD::QSUB8b)
1780 MAKE_CASE(ARMISD::UQADD16b)
1781 MAKE_CASE(ARMISD::UQSUB16b)
1782 MAKE_CASE(ARMISD::UQADD8b)
1783 MAKE_CASE(ARMISD::UQSUB8b)
1784 MAKE_CASE(ARMISD::BUILD_VECTOR)
1785 MAKE_CASE(ARMISD::BFI)
1786 MAKE_CASE(ARMISD::VORRIMM)
1787 MAKE_CASE(ARMISD::VBICIMM)
1788 MAKE_CASE(ARMISD::VBSP)
1789 MAKE_CASE(ARMISD::MEMCPY)
1790 MAKE_CASE(ARMISD::VLD1DUP)
1791 MAKE_CASE(ARMISD::VLD2DUP)
1792 MAKE_CASE(ARMISD::VLD3DUP)
1793 MAKE_CASE(ARMISD::VLD4DUP)
1794 MAKE_CASE(ARMISD::VLD1_UPD)
1795 MAKE_CASE(ARMISD::VLD2_UPD)
1796 MAKE_CASE(ARMISD::VLD3_UPD)
1797 MAKE_CASE(ARMISD::VLD4_UPD)
1798 MAKE_CASE(ARMISD::VLD1x2_UPD)
1799 MAKE_CASE(ARMISD::VLD1x3_UPD)
1800 MAKE_CASE(ARMISD::VLD1x4_UPD)
1801 MAKE_CASE(ARMISD::VLD2LN_UPD)
1802 MAKE_CASE(ARMISD::VLD3LN_UPD)
1803 MAKE_CASE(ARMISD::VLD4LN_UPD)
1804 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1805 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1806 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1807 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1808 MAKE_CASE(ARMISD::VST1_UPD)
1809 MAKE_CASE(ARMISD::VST2_UPD)
1810 MAKE_CASE(ARMISD::VST3_UPD)
1811 MAKE_CASE(ARMISD::VST4_UPD)
1812 MAKE_CASE(ARMISD::VST1x2_UPD)
1813 MAKE_CASE(ARMISD::VST1x3_UPD)
1814 MAKE_CASE(ARMISD::VST1x4_UPD)
1815 MAKE_CASE(ARMISD::VST2LN_UPD)
1816 MAKE_CASE(ARMISD::VST3LN_UPD)
1817 MAKE_CASE(ARMISD::VST4LN_UPD)
1818 MAKE_CASE(ARMISD::WLS)
1819 MAKE_CASE(ARMISD::WLSSETUP)
1820 MAKE_CASE(ARMISD::LE)
1821 MAKE_CASE(ARMISD::LOOP_DEC)
1822 MAKE_CASE(ARMISD::CSINV)
1823 MAKE_CASE(ARMISD::CSNEG)
1824 MAKE_CASE(ARMISD::CSINC)
1825 MAKE_CASE(ARMISD::MEMCPYLOOP)
1826 MAKE_CASE(ARMISD::MEMSETLOOP)
1827#undef MAKE_CASE
1828 }
1829 return nullptr;
1830}
1831
1832EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1833 EVT VT) const {
1834 if (!VT.isVector())
1835 return getPointerTy(DL);
1836
1837 // MVE has a predicate register.
1838 if ((Subtarget->hasMVEIntegerOps() &&
1839 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8)) ||
1840 (Subtarget->hasMVEFloatOps() && (VT == MVT::v4f32 || VT == MVT::v8f16)))
1841 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1842 return VT.changeVectorElementTypeToInteger();
1843}
1844
1845/// getRegClassFor - Return the register class that should be used for the
1846/// specified value type.
1847const TargetRegisterClass *
1848ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1849 (void)isDivergent;
1850 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1851 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1852 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1853 // MVE Q registers.
1854 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1855 if (VT == MVT::v4i64)
1856 return &ARM::QQPRRegClass;
1857 if (VT == MVT::v8i64)
1858 return &ARM::QQQQPRRegClass;
1859 }
1860 return TargetLowering::getRegClassFor(VT);
1861}
1862
1863// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1864// source/dest is aligned and the copy size is large enough. We therefore want
1865// to align such objects passed to memory intrinsics.
1866bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1867 unsigned &PrefAlign) const {
1868 if (!isa<MemIntrinsic>(CI))
1869 return false;
1870 MinSize = 8;
1871 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1872 // cycle faster than 4-byte aligned LDM.
1873 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1874 return true;
1875}
1876
1877// Create a fast isel object.
1878FastISel *
1879ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1880 const TargetLibraryInfo *libInfo) const {
1881 return ARM::createFastISel(funcInfo, libInfo);
1882}
1883
1884Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1885 unsigned NumVals = N->getNumValues();
1886 if (!NumVals)
1887 return Sched::RegPressure;
1888
1889 for (unsigned i = 0; i != NumVals; ++i) {
1890 EVT VT = N->getValueType(i);
1891 if (VT == MVT::Glue || VT == MVT::Other)
1892 continue;
1893 if (VT.isFloatingPoint() || VT.isVector())
1894 return Sched::ILP;
1895 }
1896
1897 if (!N->isMachineOpcode())
1898 return Sched::RegPressure;
1899
1900 // Load are scheduled for latency even if there instruction itinerary
1901 // is not available.
1902 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1903 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1904
1905 if (MCID.getNumDefs() == 0)
1906 return Sched::RegPressure;
1907 if (!Itins->isEmpty() &&
1908 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1909 return Sched::ILP;
1910
1911 return Sched::RegPressure;
1912}
1913
1914//===----------------------------------------------------------------------===//
1915// Lowering Code
1916//===----------------------------------------------------------------------===//
1917
1918static bool isSRL16(const SDValue &Op) {
1919 if (Op.getOpcode() != ISD::SRL)
1920 return false;
1921 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1922 return Const->getZExtValue() == 16;
1923 return false;
1924}
1925
1926static bool isSRA16(const SDValue &Op) {
1927 if (Op.getOpcode() != ISD::SRA)
1928 return false;
1929 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1930 return Const->getZExtValue() == 16;
1931 return false;
1932}
1933
1934static bool isSHL16(const SDValue &Op) {
1935 if (Op.getOpcode() != ISD::SHL)
1936 return false;
1937 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1938 return Const->getZExtValue() == 16;
1939 return false;
1940}
1941
1942// Check for a signed 16-bit value. We special case SRA because it makes it
1943// more simple when also looking for SRAs that aren't sign extending a
1944// smaller value. Without the check, we'd need to take extra care with
1945// checking order for some operations.
1946static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1947 if (isSRA16(Op))
1948 return isSHL16(Op.getOperand(0));
1949 return DAG.ComputeNumSignBits(Op) == 17;
1950}
1951
1952/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1953static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1954 switch (CC) {
1955 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1955)
;
1956 case ISD::SETNE: return ARMCC::NE;
1957 case ISD::SETEQ: return ARMCC::EQ;
1958 case ISD::SETGT: return ARMCC::GT;
1959 case ISD::SETGE: return ARMCC::GE;
1960 case ISD::SETLT: return ARMCC::LT;
1961 case ISD::SETLE: return ARMCC::LE;
1962 case ISD::SETUGT: return ARMCC::HI;
1963 case ISD::SETUGE: return ARMCC::HS;
1964 case ISD::SETULT: return ARMCC::LO;
1965 case ISD::SETULE: return ARMCC::LS;
1966 }
1967}
1968
1969/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1970static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1971 ARMCC::CondCodes &CondCode2) {
1972 CondCode2 = ARMCC::AL;
1973 switch (CC) {
1974 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1974)
;
1975 case ISD::SETEQ:
1976 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1977 case ISD::SETGT:
1978 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1979 case ISD::SETGE:
1980 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1981 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1982 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1983 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1984 case ISD::SETO: CondCode = ARMCC::VC; break;
1985 case ISD::SETUO: CondCode = ARMCC::VS; break;
1986 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1987 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1988 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1989 case ISD::SETLT:
1990 case ISD::SETULT: CondCode = ARMCC::LT; break;
1991 case ISD::SETLE:
1992 case ISD::SETULE: CondCode = ARMCC::LE; break;
1993 case ISD::SETNE:
1994 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1995 }
1996}
1997
1998//===----------------------------------------------------------------------===//
1999// Calling Convention Implementation
2000//===----------------------------------------------------------------------===//
2001
2002/// getEffectiveCallingConv - Get the effective calling convention, taking into
2003/// account presence of floating point hardware and calling convention
2004/// limitations, such as support for variadic functions.
2005CallingConv::ID
2006ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2007 bool isVarArg) const {
2008 switch (CC) {
2009 default:
2010 report_fatal_error("Unsupported calling convention");
2011 case CallingConv::ARM_AAPCS:
2012 case CallingConv::ARM_APCS:
2013 case CallingConv::GHC:
2014 case CallingConv::CFGuard_Check:
2015 return CC;
2016 case CallingConv::PreserveMost:
2017 return CallingConv::PreserveMost;
2018 case CallingConv::ARM_AAPCS_VFP:
2019 case CallingConv::Swift:
2020 case CallingConv::SwiftTail:
2021 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2022 case CallingConv::C:
2023 case CallingConv::Tail:
2024 if (!Subtarget->isAAPCS_ABI())
2025 return CallingConv::ARM_APCS;
2026 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2027 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2028 !isVarArg)
2029 return CallingConv::ARM_AAPCS_VFP;
2030 else
2031 return CallingConv::ARM_AAPCS;
2032 case CallingConv::Fast:
2033 case CallingConv::CXX_FAST_TLS:
2034 if (!Subtarget->isAAPCS_ABI()) {
2035 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2036 return CallingConv::Fast;
2037 return CallingConv::ARM_APCS;
2038 } else if (Subtarget->hasVFP2Base() &&
2039 !Subtarget->isThumb1Only() && !isVarArg)
2040 return CallingConv::ARM_AAPCS_VFP;
2041 else
2042 return CallingConv::ARM_AAPCS;
2043 }
2044}
2045
2046CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2047 bool isVarArg) const {
2048 return CCAssignFnForNode(CC, false, isVarArg);
2049}
2050
2051CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2052 bool isVarArg) const {
2053 return CCAssignFnForNode(CC, true, isVarArg);
2054}
2055
2056/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2057/// CallingConvention.
2058CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2059 bool Return,
2060 bool isVarArg) const {
2061 switch (getEffectiveCallingConv(CC, isVarArg)) {
2062 default:
2063 report_fatal_error("Unsupported calling convention");
2064 case CallingConv::ARM_APCS:
2065 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2066 case CallingConv::ARM_AAPCS:
2067 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2068 case CallingConv::ARM_AAPCS_VFP:
2069 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2070 case CallingConv::Fast:
2071 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2072 case CallingConv::GHC:
2073 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2074 case CallingConv::PreserveMost:
2075 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2076 case CallingConv::CFGuard_Check:
2077 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2078 }
2079}
2080
2081SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2082 MVT LocVT, MVT ValVT, SDValue Val) const {
2083 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2084 Val);
2085 if (Subtarget->hasFullFP16()) {
2086 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2087 } else {
2088 Val = DAG.getNode(ISD::TRUNCATE, dl,
2089 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2090 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2091 }
2092 return Val;
2093}
2094
2095SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2096 MVT LocVT, MVT ValVT,
2097 SDValue Val) const {
2098 if (Subtarget->hasFullFP16()) {
2099 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2100 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2101 } else {
2102 Val = DAG.getNode(ISD::BITCAST, dl,
2103 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2104 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2105 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2106 }
2107 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2108}
2109
2110/// LowerCallResult - Lower the result values of a call into the
2111/// appropriate copies out of appropriate physical registers.
2112SDValue ARMTargetLowering::LowerCallResult(
2113 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2114 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2115 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2116 SDValue ThisVal) const {
2117 // Assign locations to each value returned by this call.
2118 SmallVector<CCValAssign, 16> RVLocs;
2119 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2120 *DAG.getContext());
2121 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2122
2123 // Copy all of the result registers out of their specified physreg.
2124 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2125 CCValAssign VA = RVLocs[i];
2126
2127 // Pass 'this' value directly from the argument to return value, to avoid
2128 // reg unit interference
2129 if (i == 0 && isThisReturn) {
2130 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2131, __extension__ __PRETTY_FUNCTION__))
2131 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2131, __extension__ __PRETTY_FUNCTION__))
;
2132 InVals.push_back(ThisVal);
2133 continue;
2134 }
2135
2136 SDValue Val;
2137 if (VA.needsCustom() &&
2138 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2139 // Handle f64 or half of a v2f64.
2140 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2141 InFlag);
2142 Chain = Lo.getValue(1);
2143 InFlag = Lo.getValue(2);
2144 VA = RVLocs[++i]; // skip ahead to next loc
2145 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2146 InFlag);
2147 Chain = Hi.getValue(1);
2148 InFlag = Hi.getValue(2);
2149 if (!Subtarget->isLittle())
2150 std::swap (Lo, Hi);
2151 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2152
2153 if (VA.getLocVT() == MVT::v2f64) {
2154 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2155 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2156 DAG.getConstant(0, dl, MVT::i32));
2157
2158 VA = RVLocs[++i]; // skip ahead to next loc
2159 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2160 Chain = Lo.getValue(1);
2161 InFlag = Lo.getValue(2);
2162 VA = RVLocs[++i]; // skip ahead to next loc
2163 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2164 Chain = Hi.getValue(1);
2165 InFlag = Hi.getValue(2);
2166 if (!Subtarget->isLittle())
2167 std::swap (Lo, Hi);
2168 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2169 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2170 DAG.getConstant(1, dl, MVT::i32));
2171 }
2172 } else {
2173 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2174 InFlag);
2175 Chain = Val.getValue(1);
2176 InFlag = Val.getValue(2);
2177 }
2178
2179 switch (VA.getLocInfo()) {
2180 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2180)
;
2181 case CCValAssign::Full: break;
2182 case CCValAssign::BCvt:
2183 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2184 break;
2185 }
2186
2187 // f16 arguments have their size extended to 4 bytes and passed as if they
2188 // had been copied to the LSBs of a 32-bit register.
2189 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2190 if (VA.needsCustom() &&
2191 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2192 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2193
2194 InVals.push_back(Val);
2195 }
2196
2197 return Chain;
2198}
2199
2200std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2201 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2202 bool IsTailCall, int SPDiff) const {
2203 SDValue DstAddr;
2204 MachinePointerInfo DstInfo;
2205 int32_t Offset = VA.getLocMemOffset();
2206 MachineFunction &MF = DAG.getMachineFunction();
2207
2208 if (IsTailCall) {
2209 Offset += SPDiff;
2210 auto PtrVT = getPointerTy(DAG.getDataLayout());
2211 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2212 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2213 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2214 DstInfo =
2215 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2216 } else {
2217 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2218 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2219 StackPtr, PtrOff);
2220 DstInfo =
2221 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2222 }
2223
2224 return std::make_pair(DstAddr, DstInfo);
2225}
2226
2227void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2228 SDValue Chain, SDValue &Arg,
2229 RegsToPassVector &RegsToPass,
2230 CCValAssign &VA, CCValAssign &NextVA,
2231 SDValue &StackPtr,
2232 SmallVectorImpl<SDValue> &MemOpChains,
2233 bool IsTailCall,
2234 int SPDiff) const {
2235 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2236 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2237 unsigned id = Subtarget->isLittle() ? 0 : 1;
2238 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2239
2240 if (NextVA.isRegLoc())
2241 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2242 else {
2243 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2243, __extension__ __PRETTY_FUNCTION__))
;
2244 if (!StackPtr.getNode())
2245 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2246 getPointerTy(DAG.getDataLayout()));
2247
2248 SDValue DstAddr;
2249 MachinePointerInfo DstInfo;
2250 std::tie(DstAddr, DstInfo) =
2251 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2252 MemOpChains.push_back(
2253 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2254 }
2255}
2256
2257static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2258 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2259 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2260}
2261
2262/// LowerCall - Lowering a call into a callseq_start <-
2263/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2264/// nodes.
2265SDValue
2266ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2267 SmallVectorImpl<SDValue> &InVals) const {
2268 SelectionDAG &DAG = CLI.DAG;
2269 SDLoc &dl = CLI.DL;
2270 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2271 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2272 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2273 SDValue Chain = CLI.Chain;
2274 SDValue Callee = CLI.Callee;
2275 bool &isTailCall = CLI.IsTailCall;
2276 CallingConv::ID CallConv = CLI.CallConv;
2277 bool doesNotRet = CLI.DoesNotReturn;
2278 bool isVarArg = CLI.IsVarArg;
2279
2280 MachineFunction &MF = DAG.getMachineFunction();
2281 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2282 MachineFunction::CallSiteInfo CSInfo;
2283 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2284 bool isThisReturn = false;
2285 bool isCmseNSCall = false;
2286 bool isSibCall = false;
2287 bool PreferIndirect = false;
2288
2289 // Determine whether this is a non-secure function call.
2290 if (CLI.CB && CLI.CB->getAttributes().hasFnAttribute("cmse_nonsecure_call"))
2291 isCmseNSCall = true;
2292
2293 // Disable tail calls if they're not supported.
2294 if (!Subtarget->supportsTailCall())
2295 isTailCall = false;
2296
2297 // For both the non-secure calls and the returns from a CMSE entry function,
2298 // the function needs to do some extra work afte r the call, or before the
2299 // return, respectively, thus it cannot end with atail call
2300 if (isCmseNSCall || AFI->isCmseNSEntryFunction())
2301 isTailCall = false;
2302
2303 if (isa<GlobalAddressSDNode>(Callee)) {
2304 // If we're optimizing for minimum size and the function is called three or
2305 // more times in this block, we can improve codesize by calling indirectly
2306 // as BLXr has a 16-bit encoding.
2307 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2308 if (CLI.CB) {
2309 auto *BB = CLI.CB->getParent();
2310 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2311 count_if(GV->users(), [&BB](const User *U) {
2312 return isa<Instruction>(U) &&
2313 cast<Instruction>(U)->getParent() == BB;
2314 }) > 2;
2315 }
2316 }
2317 if (isTailCall) {
2318 // Check if it's really possible to do a tail call.
2319 isTailCall = IsEligibleForTailCallOptimization(
2320 Callee, CallConv, isVarArg, isStructRet,
2321 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2322 PreferIndirect);
2323
2324 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2325 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2326 isSibCall = true;
2327
2328 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2329 // detected sibcalls.
2330 if (isTailCall)
2331 ++NumTailCalls;
2332 }
2333
2334 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2335 report_fatal_error("failed to perform tail call elimination on a call "
2336 "site marked musttail");
2337 // Analyze operands of the call, assigning locations to each operand.
2338 SmallVector<CCValAssign, 16> ArgLocs;
2339 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2340 *DAG.getContext());
2341 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2342
2343 // Get a count of how many bytes are to be pushed on the stack.
2344 unsigned NumBytes = CCInfo.getNextStackOffset();
2345
2346 // SPDiff is the byte offset of the call's argument area from the callee's.
2347 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2348 // by this amount for a tail call. In a sibling call it must be 0 because the
2349 // caller will deallocate the entire stack and the callee still expects its
2350 // arguments to begin at SP+0. Completely unused for non-tail calls.
2351 int SPDiff = 0;
2352
2353 if (isTailCall && !isSibCall) {
2354 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2355 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2356
2357 // Since callee will pop argument stack as a tail call, we must keep the
2358 // popped size 16-byte aligned.
2359 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2360 NumBytes = alignTo(NumBytes, StackAlign);
2361
2362 // SPDiff will be negative if this tail call requires more space than we
2363 // would automatically have in our incoming argument space. Positive if we
2364 // can actually shrink the stack.
2365 SPDiff = NumReusableBytes - NumBytes;
2366
2367 // If this call requires more stack than we have available from
2368 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2369 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2370 AFI->setArgRegsSaveSize(-SPDiff);
2371 }
2372
2373 if (isSibCall) {
2374 // For sibling tail calls, memory operands are available in our caller's stack.
2375 NumBytes = 0;
2376 } else {
2377 // Adjust the stack pointer for the new arguments...
2378 // These operations are automatically eliminated by the prolog/epilog pass
2379 Chain = DAG.getCALLSEQ_START(Chain, isTailCall ? 0 : NumBytes, 0, dl);
2380 }
2381
2382 SDValue StackPtr =
2383 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2384
2385 RegsToPassVector RegsToPass;
2386 SmallVector<SDValue, 8> MemOpChains;
2387
2388 // During a tail call, stores to the argument area must happen after all of
2389 // the function's incoming arguments have been loaded because they may alias.
2390 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2391 // there's no point in doing so repeatedly so this tracks whether that's
2392 // happened yet.
2393 bool AfterFormalArgLoads = false;
2394
2395 // Walk the register/memloc assignments, inserting copies/loads. In the case
2396 // of tail call optimization, arguments are handled later.
2397 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2398 i != e;
2399 ++i, ++realArgIdx) {
2400 CCValAssign &VA = ArgLocs[i];
2401 SDValue Arg = OutVals[realArgIdx];
2402 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2403 bool isByVal = Flags.isByVal();
2404
2405 // Promote the value if needed.
2406 switch (VA.getLocInfo()) {
2407 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2407)
;
2408 case CCValAssign::Full: break;
2409 case CCValAssign::SExt:
2410 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2411 break;
2412 case CCValAssign::ZExt:
2413 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2414 break;
2415 case CCValAssign::AExt:
2416 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2417 break;
2418 case CCValAssign::BCvt:
2419 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2420 break;
2421 }
2422
2423 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2424 Chain = DAG.getStackArgumentTokenFactor(Chain);
2425 AfterFormalArgLoads = true;
2426 }
2427
2428 // f16 arguments have their size extended to 4 bytes and passed as if they
2429 // had been copied to the LSBs of a 32-bit register.
2430 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2431 if (VA.needsCustom() &&
2432 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2433 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2434 } else {
2435 // f16 arguments could have been extended prior to argument lowering.
2436 // Mask them arguments if this is a CMSE nonsecure call.
2437 auto ArgVT = Outs[realArgIdx].ArgVT;
2438 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2439 auto LocBits = VA.getLocVT().getSizeInBits();
2440 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2441 SDValue Mask =
2442 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2443 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2444 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2445 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2446 }
2447 }
2448
2449 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2450 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2451 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2452 DAG.getConstant(0, dl, MVT::i32));
2453 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2454 DAG.getConstant(1, dl, MVT::i32));
2455
2456 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2457 StackPtr, MemOpChains, isTailCall, SPDiff);
2458
2459 VA = ArgLocs[++i]; // skip ahead to next loc
2460 if (VA.isRegLoc()) {
2461 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2462 StackPtr, MemOpChains, isTailCall, SPDiff);
2463 } else {
2464 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2464, __extension__ __PRETTY_FUNCTION__))
;
2465 SDValue DstAddr;
2466 MachinePointerInfo DstInfo;
2467 std::tie(DstAddr, DstInfo) =
2468 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2469 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2470 }
2471 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2472 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2473 StackPtr, MemOpChains, isTailCall, SPDiff);
2474 } else if (VA.isRegLoc()) {
2475 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2476 Outs[0].VT == MVT::i32) {
2477 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2478, __extension__ __PRETTY_FUNCTION__))
2478 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2478, __extension__ __PRETTY_FUNCTION__))
;
2479 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2480, __extension__ __PRETTY_FUNCTION__))
2480 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2480, __extension__ __PRETTY_FUNCTION__))
;
2481 isThisReturn = true;
2482 }
2483 const TargetOptions &Options = DAG.getTarget().Options;
2484 if (Options.EmitCallSiteInfo)
2485 CSInfo.emplace_back(VA.getLocReg(), i);
2486 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2487 } else if (isByVal) {
2488 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2488, __extension__ __PRETTY_FUNCTION__))
;
2489 unsigned offset = 0;
2490
2491 // True if this byval aggregate will be split between registers
2492 // and memory.
2493 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2494 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2495
2496 if (CurByValIdx < ByValArgsCount) {
2497
2498 unsigned RegBegin, RegEnd;
2499 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2500
2501 EVT PtrVT =
2502 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2503 unsigned int i, j;
2504 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2505 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2506 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2507 SDValue Load =
2508 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2509 DAG.InferPtrAlign(AddArg));
2510 MemOpChains.push_back(Load.getValue(1));
2511 RegsToPass.push_back(std::make_pair(j, Load));
2512 }
2513
2514 // If parameter size outsides register area, "offset" value
2515 // helps us to calculate stack slot for remained part properly.
2516 offset = RegEnd - RegBegin;
2517
2518 CCInfo.nextInRegsParam();
2519 }
2520
2521 if (Flags.getByValSize() > 4*offset) {
2522 auto PtrVT = getPointerTy(DAG.getDataLayout());
2523 SDValue Dst;
2524 MachinePointerInfo DstInfo;
2525 std::tie(Dst, DstInfo) =
2526 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2527 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2528 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2529 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2530 MVT::i32);
2531 SDValue AlignNode =
2532 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2533
2534 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2535 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2536 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2537 Ops));
2538 }
2539 } else {
2540 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2540, __extension__ __PRETTY_FUNCTION__))
;
2541 SDValue DstAddr;
2542 MachinePointerInfo DstInfo;
2543 std::tie(DstAddr, DstInfo) =
2544 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2545
2546 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2547 MemOpChains.push_back(Store);
2548 }
2549 }
2550
2551 if (!MemOpChains.empty())
2552 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2553
2554 // Build a sequence of copy-to-reg nodes chained together with token chain
2555 // and flag operands which copy the outgoing args into the appropriate regs.
2556 SDValue InFlag;
2557 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2558 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2559 RegsToPass[i].second, InFlag);
2560 InFlag = Chain.getValue(1);
2561 }
2562
2563 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2564 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2565 // node so that legalize doesn't hack it.
2566 bool isDirect = false;
2567
2568 const TargetMachine &TM = getTargetMachine();
2569 const Module *Mod = MF.getFunction().getParent();
2570 const GlobalValue *GV = nullptr;
2571 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2572 GV = G->getGlobal();
2573 bool isStub =
2574 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2575
2576 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2577 bool isLocalARMFunc = false;
2578 auto PtrVt = getPointerTy(DAG.getDataLayout());
2579
2580 if (Subtarget->genLongCalls()) {
2581 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2582, __extension__ __PRETTY_FUNCTION__))
2582 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2582, __extension__ __PRETTY_FUNCTION__))
;
2583 // Handle a global address or an external symbol. If it's not one of
2584 // those, the target's already in a register, so we don't need to do
2585 // anything extra.
2586 if (isa<GlobalAddressSDNode>(Callee)) {
2587 // Create a constant pool entry for the callee address
2588 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2589 ARMConstantPoolValue *CPV =
2590 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2591
2592 // Get the address of the callee into a register
2593 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2594 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2595 Callee = DAG.getLoad(
2596 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2597 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2598 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2599 const char *Sym = S->getSymbol();
2600
2601 // Create a constant pool entry for the callee address
2602 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2603 ARMConstantPoolValue *CPV =
2604 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2605 ARMPCLabelIndex, 0);
2606 // Get the address of the callee into a register
2607 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2608 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2609 Callee = DAG.getLoad(
2610 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2611 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2612 }
2613 } else if (isa<GlobalAddressSDNode>(Callee)) {
2614 if (!PreferIndirect) {
2615 isDirect = true;
2616 bool isDef = GV->isStrongDefinitionForLinker();
2617
2618 // ARM call to a local ARM function is predicable.
2619 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2620 // tBX takes a register source operand.
2621 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2622 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2622, __extension__ __PRETTY_FUNCTION__))
;
2623 Callee = DAG.getNode(
2624 ARMISD::WrapperPIC, dl, PtrVt,
2625 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2626 Callee = DAG.getLoad(
2627 PtrVt, dl, DAG.getEntryNode(), Callee,
2628 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2629 MachineMemOperand::MODereferenceable |
2630 MachineMemOperand::MOInvariant);
2631 } else if (Subtarget->isTargetCOFF()) {
2632 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2633, __extension__ __PRETTY_FUNCTION__))
2633 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2633, __extension__ __PRETTY_FUNCTION__))
;
2634 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2635 if (GV->hasDLLImportStorageClass())
2636 TargetFlags = ARMII::MO_DLLIMPORT;
2637 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2638 TargetFlags = ARMII::MO_COFFSTUB;
2639 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2640 TargetFlags);
2641 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2642 Callee =
2643 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2644 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2645 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2646 } else {
2647 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2648 }
2649 }
2650 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2651 isDirect = true;
2652 // tBX takes a register source operand.
2653 const char *Sym = S->getSymbol();
2654 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2655 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2656 ARMConstantPoolValue *CPV =
2657 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2658 ARMPCLabelIndex, 4);
2659 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2660 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2661 Callee = DAG.getLoad(
2662 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2663 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2664 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2665 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2666 } else {
2667 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2668 }
2669 }
2670
2671 if (isCmseNSCall) {
2672 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2673, __extension__ __PRETTY_FUNCTION__))
2673 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2673, __extension__ __PRETTY_FUNCTION__))
;
2674 if (NumBytes > 0) {
2675 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2676 "call to non-secure function would "
2677 "require passing arguments on stack",
2678 dl.getDebugLoc());
2679 DAG.getContext()->diagnose(Diag);
2680 }
2681 if (isStructRet) {
2682 DiagnosticInfoUnsupported Diag(
2683 DAG.getMachineFunction().getFunction(),
2684 "call to non-secure function would return value through pointer",
2685 dl.getDebugLoc());
2686 DAG.getContext()->diagnose(Diag);
2687 }
2688 }
2689
2690 // FIXME: handle tail calls differently.
2691 unsigned CallOpc;
2692 if (Subtarget->isThumb()) {
2693 if (isCmseNSCall)
2694 CallOpc = ARMISD::tSECALL;
2695 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2696 CallOpc = ARMISD::CALL_NOLINK;
2697 else
2698 CallOpc = ARMISD::CALL;
2699 } else {
2700 if (!isDirect && !Subtarget->hasV5TOps())
2701 CallOpc = ARMISD::CALL_NOLINK;
2702 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2703 // Emit regular call when code size is the priority
2704 !Subtarget->hasMinSize())
2705 // "mov lr, pc; b _foo" to avoid confusing the RSP
2706 CallOpc = ARMISD::CALL_NOLINK;
2707 else
2708 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2709 }
2710
2711 // We don't usually want to end the call-sequence here because we would tidy
2712 // the frame up *after* the call, however in the ABI-changing tail-call case
2713 // we've carefully laid out the parameters so that when sp is reset they'll be
2714 // in the correct location.
2715 if (isTailCall && !isSibCall) {
2716 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
2717 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2718 InFlag = Chain.getValue(1);
2719 }
2720
2721 std::vector<SDValue> Ops;
2722 Ops.push_back(Chain);
2723 Ops.push_back(Callee);
2724
2725 if (isTailCall) {
2726 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2727 }
2728
2729 // Add argument registers to the end of the list so that they are known live
2730 // into the call.
2731 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2732 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2733 RegsToPass[i].second.getValueType()));
2734
2735 // Add a register mask operand representing the call-preserved registers.
2736 if (!isTailCall) {
2737 const uint32_t *Mask;
2738 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2739 if (isThisReturn) {
2740 // For 'this' returns, use the R0-preserving mask if applicable
2741 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2742 if (!Mask) {
2743 // Set isThisReturn to false if the calling convention is not one that
2744 // allows 'returned' to be modeled in this way, so LowerCallResult does
2745 // not try to pass 'this' straight through
2746 isThisReturn = false;
2747 Mask = ARI->getCallPreservedMask(MF, CallConv);
2748 }
2749 } else
2750 Mask = ARI->getCallPreservedMask(MF, CallConv);
2751
2752 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2752, __extension__ __PRETTY_FUNCTION__))
;
2753 Ops.push_back(DAG.getRegisterMask(Mask));
2754 }
2755
2756 if (InFlag.getNode())
2757 Ops.push_back(InFlag);
2758
2759 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2760 if (isTailCall) {
2761 MF.getFrameInfo().setHasTailCall();
2762 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2763 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2764 return Ret;
2765 }
2766
2767 // Returns a chain and a flag for retval copy to use.
2768 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2769 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2770 InFlag = Chain.getValue(1);
2771 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2772
2773 // If we're guaranteeing tail-calls will be honoured, the callee must
2774 // pop its own argument stack on return. But this call is *not* a tail call so
2775 // we need to undo that after it returns to restore the status-quo.
2776 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2777 uint64_t CalleePopBytes =
2778 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2779
2780 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2781 DAG.getIntPtrConstant(CalleePopBytes, dl, true),
2782 InFlag, dl);
2783 if (!Ins.empty())
2784 InFlag = Chain.getValue(1);
2785
2786 // Handle result values, copying them out of physregs into vregs that we
2787 // return.
2788 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2789 InVals, isThisReturn,
2790 isThisReturn ? OutVals[0] : SDValue());
2791}
2792
2793/// HandleByVal - Every parameter *after* a byval parameter is passed
2794/// on the stack. Remember the next parameter register to allocate,
2795/// and then confiscate the rest of the parameter registers to insure
2796/// this.
2797void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2798 Align Alignment) const {
2799 // Byval (as with any stack) slots are always at least 4 byte aligned.
2800 Alignment = std::max(Alignment, Align(4));
2801
2802 unsigned Reg = State->AllocateReg(GPRArgRegs);
2803 if (!Reg)
2804 return;
2805
2806 unsigned AlignInRegs = Alignment.value() / 4;
2807 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2808 for (unsigned i = 0; i < Waste; ++i)
2809 Reg = State->AllocateReg(GPRArgRegs);
2810
2811 if (!Reg)
2812 return;
2813
2814 unsigned Excess = 4 * (ARM::R4 - Reg);
2815
2816 // Special case when NSAA != SP and parameter size greater than size of
2817 // all remained GPR regs. In that case we can't split parameter, we must
2818 // send it to stack. We also must set NCRN to R4, so waste all
2819 // remained registers.
2820 const unsigned NSAAOffset = State->getNextStackOffset();
2821 if (NSAAOffset != 0 && Size > Excess) {
2822 while (State->AllocateReg(GPRArgRegs))
2823 ;
2824 return;
2825 }
2826
2827 // First register for byval parameter is the first register that wasn't
2828 // allocated before this method call, so it would be "reg".
2829 // If parameter is small enough to be saved in range [reg, r4), then
2830 // the end (first after last) register would be reg + param-size-in-regs,
2831 // else parameter would be splitted between registers and stack,
2832 // end register would be r4 in this case.
2833 unsigned ByValRegBegin = Reg;
2834 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2835 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2836 // Note, first register is allocated in the beginning of function already,
2837 // allocate remained amount of registers we need.
2838 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2839 State->AllocateReg(GPRArgRegs);
2840 // A byval parameter that is split between registers and memory needs its
2841 // size truncated here.
2842 // In the case where the entire structure fits in registers, we set the
2843 // size in memory to zero.
2844 Size = std::max<int>(Size - Excess, 0);
2845}
2846
2847/// MatchingStackOffset - Return true if the given stack call argument is
2848/// already available in the same position (relatively) of the caller's
2849/// incoming argument stack.
2850static
2851bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2852 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2853 const TargetInstrInfo *TII) {
2854 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2855 int FI = std::numeric_limits<int>::max();
2856 if (Arg.getOpcode() == ISD::CopyFromReg) {
2857 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2858 if (!Register::isVirtualRegister(VR))
2859 return false;
2860 MachineInstr *Def = MRI->getVRegDef(VR);
2861 if (!Def)
2862 return false;
2863 if (!Flags.isByVal()) {
2864 if (!TII->isLoadFromStackSlot(*Def, FI))
2865 return false;
2866 } else {
2867 return false;
2868 }
2869 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2870 if (Flags.isByVal())
2871 // ByVal argument is passed in as a pointer but it's now being
2872 // dereferenced. e.g.
2873 // define @foo(%struct.X* %A) {
2874 // tail call @bar(%struct.X* byval %A)
2875 // }
2876 return false;
2877 SDValue Ptr = Ld->getBasePtr();
2878 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2879 if (!FINode)
2880 return false;
2881 FI = FINode->getIndex();
2882 } else
2883 return false;
2884
2885 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2885, __extension__ __PRETTY_FUNCTION__))
;
2886 if (!MFI.isFixedObjectIndex(FI))
2887 return false;
2888 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2889}
2890
2891/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2892/// for tail call optimization. Targets which want to do tail call
2893/// optimization should implement this function.
2894bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2895 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2896 bool isCalleeStructRet, bool isCallerStructRet,
2897 const SmallVectorImpl<ISD::OutputArg> &Outs,
2898 const SmallVectorImpl<SDValue> &OutVals,
2899 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2900 const bool isIndirect) const {
2901 MachineFunction &MF = DAG.getMachineFunction();
2902 const Function &CallerF = MF.getFunction();
2903 CallingConv::ID CallerCC = CallerF.getCallingConv();
2904
2905 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2905, __extension__ __PRETTY_FUNCTION__))
;
2906
2907 // Indirect tail calls cannot be optimized for Thumb1 if the args
2908 // to the call take up r0-r3. The reason is that there are no legal registers
2909 // left to hold the pointer to the function to be called.
2910 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2911 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2912 return false;
2913
2914 // Look for obvious safe cases to perform tail call optimization that do not
2915 // require ABI changes. This is what gcc calls sibcall.
2916
2917 // Exception-handling functions need a special set of instructions to indicate
2918 // a return to the hardware. Tail-calling another function would probably
2919 // break this.
2920 if (CallerF.hasFnAttribute("interrupt"))
2921 return false;
2922
2923 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2924 return CalleeCC == CallerCC;
2925
2926 // Also avoid sibcall optimization if either caller or callee uses struct
2927 // return semantics.
2928 if (isCalleeStructRet || isCallerStructRet)
2929 return false;
2930
2931 // Externally-defined functions with weak linkage should not be
2932 // tail-called on ARM when the OS does not support dynamic
2933 // pre-emption of symbols, as the AAELF spec requires normal calls
2934 // to undefined weak functions to be replaced with a NOP or jump to the
2935 // next instruction. The behaviour of branch instructions in this
2936 // situation (as used for tail calls) is implementation-defined, so we
2937 // cannot rely on the linker replacing the tail call with a return.
2938 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2939 const GlobalValue *GV = G->getGlobal();
2940 const Triple &TT = getTargetMachine().getTargetTriple();
2941 if (GV->hasExternalWeakLinkage() &&
2942 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2943 return false;
2944 }
2945
2946 // Check that the call results are passed in the same way.
2947 LLVMContext &C = *DAG.getContext();
2948 if (!CCState::resultsCompatible(
2949 getEffectiveCallingConv(CalleeCC, isVarArg),
2950 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2951 CCAssignFnForReturn(CalleeCC, isVarArg),
2952 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2953 return false;
2954 // The callee has to preserve all registers the caller needs to preserve.
2955 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2956 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2957 if (CalleeCC != CallerCC) {
2958 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2959 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2960 return false;
2961 }
2962
2963 // If Caller's vararg or byval argument has been split between registers and
2964 // stack, do not perform tail call, since part of the argument is in caller's
2965 // local frame.
2966 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2967 if (AFI_Caller->getArgRegsSaveSize())
2968 return false;
2969
2970 // If the callee takes no arguments then go on to check the results of the
2971 // call.
2972 if (!Outs.empty()) {
2973 // Check if stack adjustment is needed. For now, do not do this if any
2974 // argument is passed on the stack.
2975 SmallVector<CCValAssign, 16> ArgLocs;
2976 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2977 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2978 if (CCInfo.getNextStackOffset()) {
2979 // Check if the arguments are already laid out in the right way as
2980 // the caller's fixed stack objects.
2981 MachineFrameInfo &MFI = MF.getFrameInfo();
2982 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2983 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2984 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2985 i != e;
2986 ++i, ++realArgIdx) {
2987 CCValAssign &VA = ArgLocs[i];
2988 EVT RegVT = VA.getLocVT();
2989 SDValue Arg = OutVals[realArgIdx];
2990 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2991 if (VA.getLocInfo() == CCValAssign::Indirect)
2992 return false;
2993 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2994 // f64 and vector types are split into multiple registers or
2995 // register/stack-slot combinations. The types will not match
2996 // the registers; give up on memory f64 refs until we figure
2997 // out what to do about this.
2998 if (!VA.isRegLoc())
2999 return false;
3000 if (!ArgLocs[++i].isRegLoc())
3001 return false;
3002 if (RegVT == MVT::v2f64) {
3003 if (!ArgLocs[++i].isRegLoc())
3004 return false;
3005 if (!ArgLocs[++i].isRegLoc())
3006 return false;
3007 }
3008 } else if (!VA.isRegLoc()) {
3009 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3010 MFI, MRI, TII))
3011 return false;
3012 }
3013 }
3014 }
3015
3016 const MachineRegisterInfo &MRI = MF.getRegInfo();
3017 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3018 return false;
3019 }
3020
3021 return true;
3022}
3023
3024bool
3025ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3026 MachineFunction &MF, bool isVarArg,
3027 const SmallVectorImpl<ISD::OutputArg> &Outs,
3028 LLVMContext &Context) const {
3029 SmallVector<CCValAssign, 16> RVLocs;
3030 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3031 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3032}
3033
3034static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3035 const SDLoc &DL, SelectionDAG &DAG) {
3036 const MachineFunction &MF = DAG.getMachineFunction();
3037 const Function &F = MF.getFunction();
3038
3039 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3040
3041 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3042 // version of the "preferred return address". These offsets affect the return
3043 // instruction if this is a return from PL1 without hypervisor extensions.
3044 // IRQ/FIQ: +4 "subs pc, lr, #4"
3045 // SWI: 0 "subs pc, lr, #0"
3046 // ABORT: +4 "subs pc, lr, #4"
3047 // UNDEF: +4/+2 "subs pc, lr, #0"
3048 // UNDEF varies depending on where the exception came from ARM or Thumb
3049 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3050
3051 int64_t LROffset;
3052 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3053 IntKind == "ABORT")
3054 LROffset = 4;
3055 else if (IntKind == "SWI" || IntKind == "UNDEF")
3056 LROffset = 0;
3057 else
3058 report_fatal_error("Unsupported interrupt attribute. If present, value "
3059 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3060
3061 RetOps.insert(RetOps.begin() + 1,
3062 DAG.getConstant(LROffset, DL, MVT::i32, false));
3063
3064 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3065}
3066
3067SDValue
3068ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3069 bool isVarArg,
3070 const SmallVectorImpl<ISD::OutputArg> &Outs,
3071 const SmallVectorImpl<SDValue> &OutVals,
3072 const SDLoc &dl, SelectionDAG &DAG) const {
3073 // CCValAssign - represent the assignment of the return value to a location.
3074 SmallVector<CCValAssign, 16> RVLocs;
3075
3076 // CCState - Info about the registers and stack slots.
3077 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3078 *DAG.getContext());
3079
3080 // Analyze outgoing return values.
3081 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3082
3083 SDValue Flag;
3084 SmallVector<SDValue, 4> RetOps;
3085 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3086 bool isLittleEndian = Subtarget->isLittle();
3087
3088 MachineFunction &MF = DAG.getMachineFunction();
3089 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3090 AFI->setReturnRegsCount(RVLocs.size());
3091
3092 // Report error if cmse entry function returns structure through first ptr arg.
3093 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3094 // Note: using an empty SDLoc(), as the first line of the function is a
3095 // better place to report than the last line.
3096 DiagnosticInfoUnsupported Diag(
3097 DAG.getMachineFunction().getFunction(),
3098 "secure entry function would return value through pointer",
3099 SDLoc().getDebugLoc());
3100 DAG.getContext()->diagnose(Diag);
3101 }
3102
3103 // Copy the result values into the output registers.
3104 for (unsigned i = 0, realRVLocIdx = 0;
3105 i != RVLocs.size();
3106 ++i, ++realRVLocIdx) {
3107 CCValAssign &VA = RVLocs[i];
3108 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3108, __extension__ __PRETTY_FUNCTION__))
;
3109
3110 SDValue Arg = OutVals[realRVLocIdx];
3111 bool ReturnF16 = false;
3112
3113 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3114 // Half-precision return values can be returned like this:
3115 //
3116 // t11 f16 = fadd ...
3117 // t12: i16 = bitcast t11
3118 // t13: i32 = zero_extend t12
3119 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3120 //
3121 // to avoid code generation for bitcasts, we simply set Arg to the node
3122 // that produces the f16 value, t11 in this case.
3123 //
3124 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3125 SDValue ZE = Arg.getOperand(0);
3126 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3127 SDValue BC = ZE.getOperand(0);
3128 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3129 Arg = BC.getOperand(0);
3130 ReturnF16 = true;
3131 }
3132 }
3133 }
3134 }
3135
3136 switch (VA.getLocInfo()) {
3137 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3137)
;
3138 case CCValAssign::Full: break;
3139 case CCValAssign::BCvt:
3140 if (!ReturnF16)
3141 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3142 break;
3143 }
3144
3145 // Mask f16 arguments if this is a CMSE nonsecure entry.
3146 auto RetVT = Outs[realRVLocIdx].ArgVT;
3147 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3148 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3149 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3150 } else {
3151 auto LocBits = VA.getLocVT().getSizeInBits();
3152 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3153 SDValue Mask =
3154 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3155 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3156 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3157 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3158 }
3159 }
3160
3161 if (VA.needsCustom() &&
3162 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3163 if (VA.getLocVT() == MVT::v2f64) {
3164 // Extract the first half and return it in two registers.
3165 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3166 DAG.getConstant(0, dl, MVT::i32));
3167 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3168 DAG.getVTList(MVT::i32, MVT::i32), Half);
3169
3170 Chain =
3171 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3172 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3173 Flag = Chain.getValue(1);
3174 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3175 VA = RVLocs[++i]; // skip ahead to next loc
3176 Chain =
3177 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3178 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3179 Flag = Chain.getValue(1);
3180 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3181 VA = RVLocs[++i]; // skip ahead to next loc
3182
3183 // Extract the 2nd half and fall through to handle it as an f64 value.
3184 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3185 DAG.getConstant(1, dl, MVT::i32));
3186 }
3187 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3188 // available.
3189 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3190 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3191 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3192 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3193 Flag = Chain.getValue(1);
3194 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3195 VA = RVLocs[++i]; // skip ahead to next loc
3196 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3197 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3198 } else
3199 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3200
3201 // Guarantee that all emitted copies are
3202 // stuck together, avoiding something bad.
3203 Flag = Chain.getValue(1);
3204 RetOps.push_back(DAG.getRegister(
3205 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3206 }
3207 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3208 const MCPhysReg *I =
3209 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3210 if (I) {
3211 for (; *I; ++I) {
3212 if (ARM::GPRRegClass.contains(*I))
3213 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3214 else if (ARM::DPRRegClass.contains(*I))
3215 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3216 else
3217 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3217)
;
3218 }
3219 }
3220
3221 // Update chain and glue.
3222 RetOps[0] = Chain;
3223 if (Flag.getNode())
3224 RetOps.push_back(Flag);
3225
3226 // CPUs which aren't M-class use a special sequence to return from
3227 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3228 // though we use "subs pc, lr, #N").
3229 //
3230 // M-class CPUs actually use a normal return sequence with a special
3231 // (hardware-provided) value in LR, so the normal code path works.
3232 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3233 !Subtarget->isMClass()) {
3234 if (Subtarget->isThumb1Only())
3235 report_fatal_error("interrupt attribute is not supported in Thumb1");
3236 return LowerInterruptReturn(RetOps, dl, DAG);
3237 }
3238
3239 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3240 ARMISD::RET_FLAG;
3241 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3242}
3243
3244bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3245 if (N->getNumValues() != 1)
3246 return false;
3247 if (!N->hasNUsesOfValue(1, 0))
3248 return false;
3249
3250 SDValue TCChain = Chain;
3251 SDNode *Copy = *N->use_begin();
3252 if (Copy->getOpcode() == ISD::CopyToReg) {
3253 // If the copy has a glue operand, we conservatively assume it isn't safe to
3254 // perform a tail call.
3255 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3256 return false;
3257 TCChain = Copy->getOperand(0);
3258 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3259 SDNode *VMov = Copy;
3260 // f64 returned in a pair of GPRs.
3261 SmallPtrSet<SDNode*, 2> Copies;
3262 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3263 UI != UE; ++UI) {
3264 if (UI->getOpcode() != ISD::CopyToReg)
3265 return false;
3266 Copies.insert(*UI);
3267 }
3268 if (Copies.size() > 2)
3269 return false;
3270
3271 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3272 UI != UE; ++UI) {
3273 SDValue UseChain = UI->getOperand(0);
3274 if (Copies.count(UseChain.getNode()))
3275 // Second CopyToReg
3276 Copy = *UI;
3277 else {
3278 // We are at the top of this chain.
3279 // If the copy has a glue operand, we conservatively assume it
3280 // isn't safe to perform a tail call.
3281 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3282 return false;
3283 // First CopyToReg
3284 TCChain = UseChain;
3285 }
3286 }
3287 } else if (Copy->getOpcode() == ISD::BITCAST) {
3288 // f32 returned in a single GPR.
3289 if (!Copy->hasOneUse())
3290 return false;
3291 Copy = *Copy->use_begin();
3292 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3293 return false;
3294 // If the copy has a glue operand, we conservatively assume it isn't safe to
3295 // perform a tail call.
3296 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3297 return false;
3298 TCChain = Copy->getOperand(0);
3299 } else {
3300 return false;
3301 }
3302
3303 bool HasRet = false;
3304 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3305 UI != UE; ++UI) {
3306 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3307 UI->getOpcode() != ARMISD::INTRET_FLAG)
3308 return false;
3309 HasRet = true;
3310 }
3311
3312 if (!HasRet)
3313 return false;
3314
3315 Chain = TCChain;
3316 return true;
3317}
3318
3319bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3320 if (!Subtarget->supportsTailCall())
3321 return false;
3322
3323 if (!CI->isTailCall())
3324 return false;
3325
3326 return true;
3327}
3328
3329// Trying to write a 64 bit value so need to split into two 32 bit values first,
3330// and pass the lower and high parts through.
3331static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3332 SDLoc DL(Op);
3333 SDValue WriteValue = Op->getOperand(2);
3334
3335 // This function is only supposed to be called for i64 type argument.
3336 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3337, __extension__ __PRETTY_FUNCTION__))
3337 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3337, __extension__ __PRETTY_FUNCTION__))
;
3338
3339 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3340 DAG.getConstant(0, DL, MVT::i32));
3341 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3342 DAG.getConstant(1, DL, MVT::i32));
3343 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3344 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3345}
3346
3347// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3348// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3349// one of the above mentioned nodes. It has to be wrapped because otherwise
3350// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3351// be used to form addressing mode. These wrapped nodes will be selected
3352// into MOVi.
3353SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3354 SelectionDAG &DAG) const {
3355 EVT PtrVT = Op.getValueType();
3356 // FIXME there is no actual debug info here
3357 SDLoc dl(Op);
3358 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3359 SDValue Res;
3360
3361 // When generating execute-only code Constant Pools must be promoted to the
3362 // global data section. It's a bit ugly that we can't share them across basic
3363 // blocks, but this way we guarantee that execute-only behaves correct with
3364 // position-independent addressing modes.
3365 if (Subtarget->genExecuteOnly()) {
3366 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3367 auto T = const_cast<Type*>(CP->getType());
3368 auto C = const_cast<Constant*>(CP->getConstVal());
3369 auto M = const_cast<Module*>(DAG.getMachineFunction().
3370 getFunction().getParent());
3371 auto GV = new GlobalVariable(
3372 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3373 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3374 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3375 Twine(AFI->createPICLabelUId())
3376 );
3377 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3378 dl, PtrVT);
3379 return LowerGlobalAddress(GA, DAG);
3380 }
3381
3382 if (CP->isMachineConstantPoolEntry())
3383 Res =
3384 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3385 else
3386 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3387 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3388}
3389
3390unsigned ARMTargetLowering::getJumpTableEncoding() const {
3391 return MachineJumpTableInfo::EK_Inline;
3392}
3393
3394SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3395 SelectionDAG &DAG) const {
3396 MachineFunction &MF = DAG.getMachineFunction();
3397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3398 unsigned ARMPCLabelIndex = 0;
3399 SDLoc DL(Op);
3400 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3401 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3402 SDValue CPAddr;
3403 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3404 if (!IsPositionIndependent) {
3405 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3406 } else {
3407 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3408 ARMPCLabelIndex = AFI->createPICLabelUId();
3409 ARMConstantPoolValue *CPV =
3410 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3411 ARMCP::CPBlockAddress, PCAdj);
3412 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3413 }
3414 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3415 SDValue Result = DAG.getLoad(
3416 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3417 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3418 if (!IsPositionIndependent)
3419 return Result;
3420 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3421 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3422}
3423
3424/// Convert a TLS address reference into the correct sequence of loads
3425/// and calls to compute the variable's address for Darwin, and return an
3426/// SDValue containing the final node.
3427
3428/// Darwin only has one TLS scheme which must be capable of dealing with the
3429/// fully general situation, in the worst case. This means:
3430/// + "extern __thread" declaration.
3431/// + Defined in a possibly unknown dynamic library.
3432///
3433/// The general system is that each __thread variable has a [3 x i32] descriptor
3434/// which contains information used by the runtime to calculate the address. The
3435/// only part of this the compiler needs to know about is the first word, which
3436/// contains a function pointer that must be called with the address of the
3437/// entire descriptor in "r0".
3438///
3439/// Since this descriptor may be in a different unit, in general access must
3440/// proceed along the usual ARM rules. A common sequence to produce is:
3441///
3442/// movw rT1, :lower16:_var$non_lazy_ptr
3443/// movt rT1, :upper16:_var$non_lazy_ptr
3444/// ldr r0, [rT1]
3445/// ldr rT2, [r0]
3446/// blx rT2
3447/// [...address now in r0...]
3448SDValue
3449ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3450 SelectionDAG &DAG) const {
3451 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3452, __extension__ __PRETTY_FUNCTION__))
3452 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3452, __extension__ __PRETTY_FUNCTION__))
;
3453 SDLoc DL(Op);
3454
3455 // First step is to get the address of the actua global symbol. This is where
3456 // the TLS descriptor lives.
3457 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3458
3459 // The first entry in the descriptor is a function pointer that we must call
3460 // to obtain the address of the variable.
3461 SDValue Chain = DAG.getEntryNode();
3462 SDValue FuncTLVGet = DAG.getLoad(
3463 MVT::i32, DL, Chain, DescAddr,
3464 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3465 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3466 MachineMemOperand::MOInvariant);
3467 Chain = FuncTLVGet.getValue(1);
3468
3469 MachineFunction &F = DAG.getMachineFunction();
3470 MachineFrameInfo &MFI = F.getFrameInfo();
3471 MFI.setAdjustsStack(true);
3472
3473 // TLS calls preserve all registers except those that absolutely must be
3474 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3475 // silly).
3476 auto TRI =
3477 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3478 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3479 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3480
3481 // Finally, we can make the call. This is just a degenerate version of a
3482 // normal AArch64 call node: r0 takes the address of the descriptor, and
3483 // returns the address of the variable in this thread.
3484 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3485 Chain =
3486 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3487 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3488 DAG.getRegisterMask(Mask), Chain.getValue(1));
3489 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3490}
3491
3492SDValue
3493ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3494 SelectionDAG &DAG) const {
3495 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3495, __extension__ __PRETTY_FUNCTION__))
;
3496
3497 SDValue Chain = DAG.getEntryNode();
3498 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3499 SDLoc DL(Op);
3500
3501 // Load the current TEB (thread environment block)
3502 SDValue Ops[] = {Chain,
3503 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3504 DAG.getTargetConstant(15, DL, MVT::i32),
3505 DAG.getTargetConstant(0, DL, MVT::i32),
3506 DAG.getTargetConstant(13, DL, MVT::i32),
3507 DAG.getTargetConstant(0, DL, MVT::i32),
3508 DAG.getTargetConstant(2, DL, MVT::i32)};
3509 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3510 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3511
3512 SDValue TEB = CurrentTEB.getValue(0);
3513 Chain = CurrentTEB.getValue(1);
3514
3515 // Load the ThreadLocalStoragePointer from the TEB
3516 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3517 SDValue TLSArray =
3518 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3519 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3520
3521 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3522 // offset into the TLSArray.
3523
3524 // Load the TLS index from the C runtime
3525 SDValue TLSIndex =
3526 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3527 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3528 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3529
3530 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3531 DAG.getConstant(2, DL, MVT::i32));
3532 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3533 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3534 MachinePointerInfo());
3535
3536 // Get the offset of the start of the .tls section (section base)
3537 const auto *GA = cast<GlobalAddressSDNode>(Op);
3538 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3539 SDValue Offset = DAG.getLoad(
3540 PtrVT, DL, Chain,
3541 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3542 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3543 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3544
3545 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3546}
3547
3548// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3549SDValue
3550ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3551 SelectionDAG &DAG) const {
3552 SDLoc dl(GA);
3553 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3554 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3555 MachineFunction &MF = DAG.getMachineFunction();
3556 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3557 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3558 ARMConstantPoolValue *CPV =
3559 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3560 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3561 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3562 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3563 Argument = DAG.getLoad(
3564 PtrVT, dl, DAG.getEntryNode(), Argument,
3565 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3566 SDValue Chain = Argument.getValue(1);
3567
3568 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3569 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3570
3571 // call __tls_get_addr.
3572 ArgListTy Args;
3573 ArgListEntry Entry;
3574 Entry.Node = Argument;
3575 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3576 Args.push_back(Entry);
3577
3578 // FIXME: is there useful debug info available here?
3579 TargetLowering::CallLoweringInfo CLI(DAG);
3580 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3581 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3582 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3583
3584 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3585 return CallResult.first;
3586}
3587
3588// Lower ISD::GlobalTLSAddress using the "initial exec" or
3589// "local exec" model.
3590SDValue
3591ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3592 SelectionDAG &DAG,
3593 TLSModel::Model model) const {
3594 const GlobalValue *GV = GA->getGlobal();
3595 SDLoc dl(GA);
3596 SDValue Offset;
3597 SDValue Chain = DAG.getEntryNode();
3598 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3599 // Get the Thread Pointer
3600 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3601
3602 if (model == TLSModel::InitialExec) {
3603 MachineFunction &MF = DAG.getMachineFunction();
3604 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3605 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3606 // Initial exec model.
3607 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3608 ARMConstantPoolValue *CPV =
3609 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3610 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3611 true);
3612 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3613 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3614 Offset = DAG.getLoad(
3615 PtrVT, dl, Chain, Offset,
3616 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3617 Chain = Offset.getValue(1);
3618
3619 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3620 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3621
3622 Offset = DAG.getLoad(
3623 PtrVT, dl, Chain, Offset,
3624 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3625 } else {
3626 // local exec model
3627 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3627, __extension__ __PRETTY_FUNCTION__))
;
3628 ARMConstantPoolValue *CPV =
3629 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3630 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3631 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3632 Offset = DAG.getLoad(
3633 PtrVT, dl, Chain, Offset,
3634 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3635 }
3636
3637 // The address of the thread local variable is the add of the thread
3638 // pointer with the offset of the variable.
3639 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3640}
3641
3642SDValue
3643ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3644 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3645 if (DAG.getTarget().useEmulatedTLS())
3646 return LowerToTLSEmulatedModel(GA, DAG);
3647
3648 if (Subtarget->isTargetDarwin())
3649 return LowerGlobalTLSAddressDarwin(Op, DAG);
3650
3651 if (Subtarget->isTargetWindows())
3652 return LowerGlobalTLSAddressWindows(Op, DAG);
3653
3654 // TODO: implement the "local dynamic" model
3655 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3655, __extension__ __PRETTY_FUNCTION__))
;
3656 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3657
3658 switch (model) {
3659 case TLSModel::GeneralDynamic:
3660 case TLSModel::LocalDynamic:
3661 return LowerToTLSGeneralDynamicModel(GA, DAG);
3662 case TLSModel::InitialExec:
3663 case TLSModel::LocalExec:
3664 return LowerToTLSExecModels(GA, DAG, model);
3665 }
3666 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3666)
;
3667}
3668
3669/// Return true if all users of V are within function F, looking through
3670/// ConstantExprs.
3671static bool allUsersAreInFunction(const Value *V, const Function *F) {
3672 SmallVector<const User*,4> Worklist(V->users());
3673 while (!Worklist.empty()) {
3674 auto *U = Worklist.pop_back_val();
3675 if (isa<ConstantExpr>(U)) {
3676 append_range(Worklist, U->users());
3677 continue;
3678 }
3679
3680 auto *I = dyn_cast<Instruction>(U);
3681 if (!I || I->getParent()->getParent() != F)
3682 return false;
3683 }
3684 return true;
3685}
3686
3687static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3688 const GlobalValue *GV, SelectionDAG &DAG,
3689 EVT PtrVT, const SDLoc &dl) {
3690 // If we're creating a pool entry for a constant global with unnamed address,
3691 // and the global is small enough, we can emit it inline into the constant pool
3692 // to save ourselves an indirection.
3693 //
3694 // This is a win if the constant is only used in one function (so it doesn't
3695 // need to be duplicated) or duplicating the constant wouldn't increase code
3696 // size (implying the constant is no larger than 4 bytes).
3697 const Function &F = DAG.getMachineFunction().getFunction();
3698
3699 // We rely on this decision to inline being idemopotent and unrelated to the
3700 // use-site. We know that if we inline a variable at one use site, we'll
3701 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3702 // doesn't know about this optimization, so bail out if it's enabled else
3703 // we could decide to inline here (and thus never emit the GV) but require
3704 // the GV from fast-isel generated code.
3705 if (!EnableConstpoolPromotion ||
3706 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3707 return SDValue();
3708
3709 auto *GVar = dyn_cast<GlobalVariable>(GV);
3710 if (!GVar || !GVar->hasInitializer() ||
3711 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3712 !GVar->hasLocalLinkage())
3713 return SDValue();
3714
3715 // If we inline a value that contains relocations, we move the relocations
3716 // from .data to .text. This is not allowed in position-independent code.
3717 auto *Init = GVar->getInitializer();
3718 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3719 Init->needsDynamicRelocation())
3720 return SDValue();
3721
3722 // The constant islands pass can only really deal with alignment requests
3723 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3724 // any type wanting greater alignment requirements than 4 bytes. We also
3725 // can only promote constants that are multiples of 4 bytes in size or
3726 // are paddable to a multiple of 4. Currently we only try and pad constants
3727 // that are strings for simplicity.
3728 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3729 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3730 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3731 unsigned RequiredPadding = 4 - (Size % 4);
3732 bool PaddingPossible =
3733 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3734 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3735 Size == 0)
3736 return SDValue();
3737
3738 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3739 MachineFunction &MF = DAG.getMachineFunction();
3740 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3741
3742 // We can't bloat the constant pool too much, else the ConstantIslands pass
3743 // may fail to converge. If we haven't promoted this global yet (it may have
3744 // multiple uses), and promoting it would increase the constant pool size (Sz
3745 // > 4), ensure we have space to do so up to MaxTotal.
3746 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3747 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3748 ConstpoolPromotionMaxTotal)
3749 return SDValue();
3750
3751 // This is only valid if all users are in a single function; we can't clone
3752 // the constant in general. The LLVM IR unnamed_addr allows merging
3753 // constants, but not cloning them.
3754 //
3755 // We could potentially allow cloning if we could prove all uses of the
3756 // constant in the current function don't care about the address, like
3757 // printf format strings. But that isn't implemented for now.
3758 if (!allUsersAreInFunction(GVar, &F))
3759 return SDValue();
3760
3761 // We're going to inline this global. Pad it out if needed.
3762 if (RequiredPadding != 4) {
3763 StringRef S = CDAInit->getAsString();
3764
3765 SmallVector<uint8_t,16> V(S.size());
3766 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3767 while (RequiredPadding--)
3768 V.push_back(0);
3769 Init = ConstantDataArray::get(*DAG.getContext(), V);
3770 }
3771
3772 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3773 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3774 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3775 AFI->markGlobalAsPromotedToConstantPool(GVar);
3776 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3777 PaddedSize - 4);
3778 }
3779 ++NumConstpoolPromoted;
3780 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3781}
3782
3783bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3784 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3785 if (!(GV = GA->getBaseObject()))
3786 return false;
3787 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3788 return V->isConstant();
3789 return isa<Function>(GV);
3790}
3791
3792SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3793 SelectionDAG &DAG) const {
3794 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3795 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3795)
;
3796 case Triple::COFF:
3797 return LowerGlobalAddressWindows(Op, DAG);
3798 case Triple::ELF:
3799 return LowerGlobalAddressELF(Op, DAG);
3800 case Triple::MachO:
3801 return LowerGlobalAddressDarwin(Op, DAG);
3802 }
3803}
3804
3805SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3806 SelectionDAG &DAG) const {
3807 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3808 SDLoc dl(Op);
3809 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3810 const TargetMachine &TM = getTargetMachine();
3811 bool IsRO = isReadOnly(GV);
3812
3813 // promoteToConstantPool only if not generating XO text section
3814 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3815 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3816 return V;
3817
3818 if (isPositionIndependent()) {
3819 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3820 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3821 UseGOT_PREL ? ARMII::MO_GOT : 0);
3822 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3823 if (UseGOT_PREL)
3824 Result =
3825 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3826 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3827 return Result;
3828 } else if (Subtarget->isROPI() && IsRO) {
3829 // PC-relative.
3830 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3831 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3832 return Result;
3833 } else if (Subtarget->isRWPI() && !IsRO) {
3834 // SB-relative.
3835 SDValue RelAddr;
3836 if (Subtarget->useMovt()) {
3837 ++NumMovwMovt;
3838 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3839 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3840 } else { // use literal pool for address constant
3841 ARMConstantPoolValue *CPV =
3842 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3843 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3844 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3845 RelAddr = DAG.getLoad(
3846 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3847 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3848 }
3849 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3850 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3851 return Result;
3852 }
3853
3854 // If we have T2 ops, we can materialize the address directly via movt/movw
3855 // pair. This is always cheaper.
3856 if (Subtarget->useMovt()) {
3857 ++NumMovwMovt;
3858 // FIXME: Once remat is capable of dealing with instructions with register
3859 // operands, expand this into two nodes.
3860 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3861 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3862 } else {
3863 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3864 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3865 return DAG.getLoad(
3866 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3867 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3868 }
3869}
3870
3871SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3872 SelectionDAG &DAG) const {
3873 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3874, __extension__ __PRETTY_FUNCTION__))
3874 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3874, __extension__ __PRETTY_FUNCTION__))
;
3875 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3876 SDLoc dl(Op);
3877 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3878
3879 if (Subtarget->useMovt())
3880 ++NumMovwMovt;
3881
3882 // FIXME: Once remat is capable of dealing with instructions with register
3883 // operands, expand this into multiple nodes
3884 unsigned Wrapper =
3885 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3886
3887 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3888 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3889
3890 if (Subtarget->isGVIndirectSymbol(GV))
3891 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3892 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3893 return Result;
3894}
3895
3896SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3897 SelectionDAG &DAG) const {
3898 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3898, __extension__ __PRETTY_FUNCTION__))
;
3899 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3900, __extension__ __PRETTY_FUNCTION__))
3900 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3900, __extension__ __PRETTY_FUNCTION__))
;
3901 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3902, __extension__ __PRETTY_FUNCTION__))
3902 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3902, __extension__ __PRETTY_FUNCTION__))
;
3903
3904 const TargetMachine &TM = getTargetMachine();
3905 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3906 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3907 if (GV->hasDLLImportStorageClass())
3908 TargetFlags = ARMII::MO_DLLIMPORT;
3909 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3910 TargetFlags = ARMII::MO_COFFSTUB;
3911 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3912 SDValue Result;
3913 SDLoc DL(Op);
3914
3915 ++NumMovwMovt;
3916
3917 // FIXME: Once remat is capable of dealing with instructions with register
3918 // operands, expand this into two nodes.
3919 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3920 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3921 TargetFlags));
3922 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3923 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3924 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3925 return Result;
3926}
3927
3928SDValue
3929ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3930 SDLoc dl(Op);
3931 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3932 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3933 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3934 Op.getOperand(1), Val);
3935}
3936
3937SDValue
3938ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3939 SDLoc dl(Op);
3940 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3941 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3942}
3943
3944SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3945 SelectionDAG &DAG) const {
3946 SDLoc dl(Op);
3947 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3948 Op.getOperand(0));
3949}
3950
3951SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3952 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3953 unsigned IntNo =
3954 cast<ConstantSDNode>(
3955 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3956 ->getZExtValue();
3957 switch (IntNo) {
3958 default:
3959 return SDValue(); // Don't custom lower most intrinsics.
3960 case Intrinsic::arm_gnu_eabi_mcount: {
3961 MachineFunction &MF = DAG.getMachineFunction();
3962 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3963 SDLoc dl(Op);
3964 SDValue Chain = Op.getOperand(0);
3965 // call "\01__gnu_mcount_nc"
3966 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3967 const uint32_t *Mask =
3968 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3969 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3969, __extension__ __PRETTY_FUNCTION__))
;
3970 // Mark LR an implicit live-in.
3971 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3972 SDValue ReturnAddress =
3973 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3974 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3975 SDValue Callee =
3976 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3977 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3978 if (Subtarget->isThumb())
3979 return SDValue(
3980 DAG.getMachineNode(
3981 ARM::tBL_PUSHLR, dl, ResultTys,
3982 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3983 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3984 0);
3985 return SDValue(
3986 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3987 {ReturnAddress, Callee, RegisterMask, Chain}),
3988 0);
3989 }
3990 }
3991}
3992
3993SDValue
3994ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3995 const ARMSubtarget *Subtarget) const {
3996 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3997 SDLoc dl(Op);
3998 switch (IntNo) {
3999 default: return SDValue(); // Don't custom lower most intrinsics.
4000 case Intrinsic::thread_pointer: {
4001 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4002 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4003 }
4004 case Intrinsic::arm_cls: {
4005 const SDValue &Operand = Op.getOperand(1);
4006 const EVT VTy = Op.getValueType();
4007 SDValue SRA =
4008 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4009 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4010 SDValue SHL =
4011 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4012 SDValue OR =
4013 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4014 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4015 return Result;
4016 }
4017 case Intrinsic::arm_cls64: {
4018 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4019 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4020 const SDValue &Operand = Op.getOperand(1);
4021 const EVT VTy = Op.getValueType();
4022
4023 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4024 DAG.getConstant(1, dl, VTy));
4025 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4026 DAG.getConstant(0, dl, VTy));
4027 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4028 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4029 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4030 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4031 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4032 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4033 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4034 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4035 SDValue CheckLo =
4036 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4037 SDValue HiIsZero =
4038 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4039 SDValue AdjustedLo =
4040 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4041 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4042 SDValue Result =
4043 DAG.getSelect(dl, VTy, CheckLo,
4044 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4045 return Result;
4046 }
4047 case Intrinsic::eh_sjlj_lsda: {
4048 MachineFunction &MF = DAG.getMachineFunction();
4049 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4050 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4051 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4052 SDValue CPAddr;
4053 bool IsPositionIndependent = isPositionIndependent();
4054 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4055 ARMConstantPoolValue *CPV =
4056 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4057 ARMCP::CPLSDA, PCAdj);
4058 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4059 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4060 SDValue Result = DAG.getLoad(
4061 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4062 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4063
4064 if (IsPositionIndependent) {
4065 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4066 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4067 }
4068 return Result;
4069 }
4070 case Intrinsic::arm_neon_vabs:
4071 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4072 Op.getOperand(1));
4073 case Intrinsic::arm_neon_vmulls:
4074 case Intrinsic::arm_neon_vmullu: {
4075 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4076 ? ARMISD::VMULLs : ARMISD::VMULLu;
4077 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4078 Op.getOperand(1), Op.getOperand(2));
4079 }
4080 case Intrinsic::arm_neon_vminnm:
4081 case Intrinsic::arm_neon_vmaxnm: {
4082 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4083 ? ISD::FMINNUM : ISD::FMAXNUM;
4084 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4085 Op.getOperand(1), Op.getOperand(2));
4086 }
4087 case Intrinsic::arm_neon_vminu:
4088 case Intrinsic::arm_neon_vmaxu: {
4089 if (Op.getValueType().isFloatingPoint())
4090 return SDValue();
4091 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4092 ? ISD::UMIN : ISD::UMAX;
4093 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4094 Op.getOperand(1), Op.getOperand(2));
4095 }
4096 case Intrinsic::arm_neon_vmins:
4097 case Intrinsic::arm_neon_vmaxs: {
4098 // v{min,max}s is overloaded between signed integers and floats.
4099 if (!Op.getValueType().isFloatingPoint()) {
4100 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4101 ? ISD::SMIN : ISD::SMAX;
4102 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4103 Op.getOperand(1), Op.getOperand(2));
4104 }
4105 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4106 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4107 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4108 Op.getOperand(1), Op.getOperand(2));
4109 }
4110 case Intrinsic::arm_neon_vtbl1:
4111 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4112 Op.getOperand(1), Op.getOperand(2));
4113 case Intrinsic::arm_neon_vtbl2:
4114 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4115 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4116 case Intrinsic::arm_mve_pred_i2v:
4117 case Intrinsic::arm_mve_pred_v2i:
4118 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4119 Op.getOperand(1));
4120 case Intrinsic::arm_mve_vreinterpretq:
4121 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4122 Op.getOperand(1));
4123 case Intrinsic::arm_mve_lsll:
4124 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4125 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4126 case Intrinsic::arm_mve_asrl:
4127 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4128 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4129 }
4130}
4131
4132static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4133 const ARMSubtarget *Subtarget) {
4134 SDLoc dl(Op);
4135 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4136 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4137 if (SSID == SyncScope::SingleThread)
4138 return Op;
4139
4140 if (!Subtarget->hasDataBarrier()) {
4141 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4142 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4143 // here.
4144 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4145, __extension__ __PRETTY_FUNCTION__))
4145 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4145, __extension__ __PRETTY_FUNCTION__))
;
4146 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4147 DAG.getConstant(0, dl, MVT::i32));
4148 }
4149
4150 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4151 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4152 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4153 if (Subtarget->isMClass()) {
4154 // Only a full system barrier exists in the M-class architectures.
4155 Domain = ARM_MB::SY;
4156 } else if (Subtarget->preferISHSTBarriers() &&
4157 Ord == AtomicOrdering::Release) {
4158 // Swift happens to implement ISHST barriers in a way that's compatible with
4159 // Release semantics but weaker than ISH so we'd be fools not to use
4160 // it. Beware: other processors probably don't!
4161 Domain = ARM_MB::ISHST;
4162 }
4163
4164 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4165 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4166 DAG.getConstant(Domain, dl, MVT::i32));
4167}
4168
4169static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4170 const ARMSubtarget *Subtarget) {
4171 // ARM pre v5TE and Thumb1 does not have preload instructions.
4172 if (!(Subtarget->isThumb2() ||
4173 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4174 // Just preserve the chain.
4175 return Op.getOperand(0);
4176
4177 SDLoc dl(Op);
4178 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4179 if (!isRead &&
4180 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4181 // ARMv7 with MP extension has PLDW.
4182 return Op.getOperand(0);
4183
4184 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4185 if (Subtarget->isThumb()) {
4186 // Invert the bits.
4187 isRead = ~isRead & 1;
4188 isData = ~isData & 1;
4189 }
4190
4191 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4192 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4193 DAG.getConstant(isData, dl, MVT::i32));
4194}
4195
4196static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4197 MachineFunction &MF = DAG.getMachineFunction();
4198 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4199
4200 // vastart just stores the address of the VarArgsFrameIndex slot into the
4201 // memory location argument.
4202 SDLoc dl(Op);
4203 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4204 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4205 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4206 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4207 MachinePointerInfo(SV));
4208}
4209
4210SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4211 CCValAssign &NextVA,
4212 SDValue &Root,
4213 SelectionDAG &DAG,
4214 const SDLoc &dl) const {
4215 MachineFunction &MF = DAG.getMachineFunction();
4216 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4217
4218 const TargetRegisterClass *RC;
4219 if (AFI->isThumb1OnlyFunction())
4220 RC = &ARM::tGPRRegClass;
4221 else
4222 RC = &ARM::GPRRegClass;
4223
4224 // Transform the arguments stored in physical registers into virtual ones.
4225 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4226 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4227
4228 SDValue ArgValue2;
4229 if (NextVA.isMemLoc()) {
4230 MachineFrameInfo &MFI = MF.getFrameInfo();
4231 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4232
4233 // Create load node to retrieve arguments from the stack.
4234 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4235 ArgValue2 = DAG.getLoad(
4236 MVT::i32, dl, Root, FIN,
4237 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4238 } else {
4239 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4240 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4241 }
4242 if (!Subtarget->isLittle())
4243 std::swap (ArgValue, ArgValue2);
4244 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4245}
4246
4247// The remaining GPRs hold either the beginning of variable-argument
4248// data, or the beginning of an aggregate passed by value (usually
4249// byval). Either way, we allocate stack slots adjacent to the data
4250// provided by our caller, and store the unallocated registers there.
4251// If this is a variadic function, the va_list pointer will begin with
4252// these values; otherwise, this reassembles a (byval) structure that
4253// was split between registers and memory.
4254// Return: The frame index registers were stored into.
4255int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4256 const SDLoc &dl, SDValue &Chain,
4257 const Value *OrigArg,
4258 unsigned InRegsParamRecordIdx,
4259 int ArgOffset, unsigned ArgSize) const {
4260 // Currently, two use-cases possible:
4261 // Case #1. Non-var-args function, and we meet first byval parameter.
4262 // Setup first unallocated register as first byval register;
4263 // eat all remained registers
4264 // (these two actions are performed by HandleByVal method).
4265 // Then, here, we initialize stack frame with
4266 // "store-reg" instructions.
4267 // Case #2. Var-args function, that doesn't contain byval parameters.
4268 // The same: eat all remained unallocated registers,
4269 // initialize stack frame.
4270
4271 MachineFunction &MF = DAG.getMachineFunction();
4272 MachineFrameInfo &MFI = MF.getFrameInfo();
4273 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4274 unsigned RBegin, REnd;
4275 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4276 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4277 } else {
4278 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4279 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4280 REnd = ARM::R4;
4281 }
4282
4283 if (REnd != RBegin)
4284 ArgOffset = -4 * (ARM::R4 - RBegin);
4285
4286 auto PtrVT = getPointerTy(DAG.getDataLayout());
4287 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4288 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4289
4290 SmallVector<SDValue, 4> MemOps;
4291 const TargetRegisterClass *RC =
4292 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4293
4294 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4295 unsigned VReg = MF.addLiveIn(Reg, RC);
4296 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4297 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4298 MachinePointerInfo(OrigArg, 4 * i));
4299 MemOps.push_back(Store);
4300 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4301 }
4302
4303 if (!MemOps.empty())
4304 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4305 return FrameIndex;
4306}
4307
4308// Setup stack frame, the va_list pointer will start from.
4309void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4310 const SDLoc &dl, SDValue &Chain,
4311 unsigned ArgOffset,
4312 unsigned TotalArgRegsSaveSize,
4313 bool ForceMutable) const {
4314 MachineFunction &MF = DAG.getMachineFunction();
4315 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4316
4317 // Try to store any remaining integer argument regs
4318 // to their spots on the stack so that they may be loaded by dereferencing
4319 // the result of va_next.
4320 // If there is no regs to be stored, just point address after last
4321 // argument passed via stack.
4322 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4323 CCInfo.getInRegsParamsCount(),
4324 CCInfo.getNextStackOffset(),
4325 std::max(4U, TotalArgRegsSaveSize));
4326 AFI->setVarArgsFrameIndex(FrameIndex);
4327}
4328
4329bool ARMTargetLowering::splitValueIntoRegisterParts(
4330 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4331 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4332 bool IsABIRegCopy = CC.hasValue();
4333 EVT ValueVT = Val.getValueType();
4334 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4335 PartVT == MVT::f32) {
4336 unsigned ValueBits = ValueVT.getSizeInBits();
4337 unsigned PartBits = PartVT.getSizeInBits();
4338 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4339 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4340 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4341 Parts[0] = Val;
4342 return true;
4343 }
4344 return false;
4345}
4346
4347SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4348 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4349 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4350 bool IsABIRegCopy = CC.hasValue();
4351 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4352 PartVT == MVT::f32) {
4353 unsigned ValueBits = ValueVT.getSizeInBits();
4354 unsigned PartBits = PartVT.getSizeInBits();
4355 SDValue Val = Parts[0];
4356
4357 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4358 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4359 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4360 return Val;
4361 }
4362 return SDValue();
4363}
4364
4365SDValue ARMTargetLowering::LowerFormalArguments(
4366 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4367 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4368 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4369 MachineFunction &MF = DAG.getMachineFunction();
4370 MachineFrameInfo &MFI = MF.getFrameInfo();
4371
4372 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4373
4374 // Assign locations to all of the incoming arguments.
4375 SmallVector<CCValAssign, 16> ArgLocs;
4376 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4377 *DAG.getContext());
4378 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4379
4380 SmallVector<SDValue, 16> ArgValues;
4381 SDValue ArgValue;
4382 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4383 unsigned CurArgIdx = 0;
4384
4385 // Initially ArgRegsSaveSize is zero.
4386 // Then we increase this value each time we meet byval parameter.
4387 // We also increase this value in case of varargs function.
4388 AFI->setArgRegsSaveSize(0);
4389
4390 // Calculate the amount of stack space that we need to allocate to store
4391 // byval and variadic arguments that are passed in registers.
4392 // We need to know this before we allocate the first byval or variadic
4393 // argument, as they will be allocated a stack slot below the CFA (Canonical
4394 // Frame Address, the stack pointer at entry to the function).
4395 unsigned ArgRegBegin = ARM::R4;
4396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4397 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4398 break;
4399
4400 CCValAssign &VA = ArgLocs[i];
4401 unsigned Index = VA.getValNo();
4402 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4403 if (!Flags.isByVal())
4404 continue;
4405
4406 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4406, __extension__ __PRETTY_FUNCTION__))
;
4407 unsigned RBegin, REnd;
4408 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4409 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4410
4411 CCInfo.nextInRegsParam();
4412 }
4413 CCInfo.rewindByValRegsInfo();
4414
4415 int lastInsIndex = -1;
4416 if (isVarArg && MFI.hasVAStart()) {
4417 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4418 if (RegIdx != array_lengthof(GPRArgRegs))
4419 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4420 }
4421
4422 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4423 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4424 auto PtrVT = getPointerTy(DAG.getDataLayout());
4425
4426 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4427 CCValAssign &VA = ArgLocs[i];
4428 if (Ins[VA.getValNo()].isOrigArg()) {
4429 std::advance(CurOrigArg,
4430 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4431 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4432 }
4433 // Arguments stored in registers.
4434 if (VA.isRegLoc()) {
4435 EVT RegVT = VA.getLocVT();
4436
4437 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4438 // f64 and vector types are split up into multiple registers or
4439 // combinations of registers and stack slots.
4440 SDValue ArgValue1 =
4441 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4442 VA = ArgLocs[++i]; // skip ahead to next loc
4443 SDValue ArgValue2;
4444 if (VA.isMemLoc()) {
4445 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4446 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4447 ArgValue2 = DAG.getLoad(
4448 MVT::f64, dl, Chain, FIN,
4449 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4450 } else {
4451 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4452 }
4453 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4454 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4455 ArgValue1, DAG.getIntPtrConstant(0, dl));
4456 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4457 ArgValue2, DAG.getIntPtrConstant(1, dl));
4458 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4459 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4460 } else {
4461 const TargetRegisterClass *RC;
4462
4463 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4464 RC = &ARM::HPRRegClass;
4465 else if (RegVT == MVT::f32)
4466 RC = &ARM::SPRRegClass;
4467 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4468 RegVT == MVT::v4bf16)
4469 RC = &ARM::DPRRegClass;
4470 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4471 RegVT == MVT::v8bf16)
4472 RC = &ARM::QPRRegClass;
4473 else if (RegVT == MVT::i32)
4474 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4475 : &ARM::GPRRegClass;
4476 else
4477 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4477)
;
4478
4479 // Transform the arguments in physical registers into virtual ones.
4480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4482
4483 // If this value is passed in r0 and has the returned attribute (e.g.
4484 // C++ 'structors), record this fact for later use.
4485 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4486 AFI->setPreservesR0();
4487 }
4488 }
4489
4490 // If this is an 8 or 16-bit value, it is really passed promoted
4491 // to 32 bits. Insert an assert[sz]ext to capture this, then
4492 // truncate to the right size.
4493 switch (VA.getLocInfo()) {
4494 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4494)
;
4495 case CCValAssign::Full: break;
4496 case CCValAssign::BCvt:
4497 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4498 break;
4499 case CCValAssign::SExt:
4500 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4501 DAG.getValueType(VA.getValVT()));
4502 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4503 break;
4504 case CCValAssign::ZExt:
4505 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4506 DAG.getValueType(VA.getValVT()));
4507 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4508 break;
4509 }
4510
4511 // f16 arguments have their size extended to 4 bytes and passed as if they
4512 // had been copied to the LSBs of a 32-bit register.
4513 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4514 if (VA.needsCustom() &&
4515 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4516 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4517
4518 InVals.push_back(ArgValue);
4519 } else { // VA.isRegLoc()
4520 // sanity check
4521 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4521, __extension__ __PRETTY_FUNCTION__))
;
4522 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4522, __extension__ __PRETTY_FUNCTION__))
;
4523
4524 int index = VA.getValNo();
4525
4526 // Some Ins[] entries become multiple ArgLoc[] entries.
4527 // Process them only once.
4528 if (index != lastInsIndex)
4529 {
4530 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4531 // FIXME: For now, all byval parameter objects are marked mutable.
4532 // This can be changed with more analysis.
4533 // In case of tail call optimization mark all arguments mutable.
4534 // Since they could be overwritten by lowering of arguments in case of
4535 // a tail call.
4536 if (Flags.isByVal()) {
4537 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4538, __extension__ __PRETTY_FUNCTION__))
4538 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4538, __extension__ __PRETTY_FUNCTION__))
;
4539 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4540
4541 int FrameIndex = StoreByValRegs(
4542 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4543 VA.getLocMemOffset(), Flags.getByValSize());
4544 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4545 CCInfo.nextInRegsParam();
4546 } else {
4547 unsigned FIOffset = VA.getLocMemOffset();
4548 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4549 FIOffset, true);
4550
4551 // Create load nodes to retrieve arguments from the stack.
4552 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4553 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4554 MachinePointerInfo::getFixedStack(
4555 DAG.getMachineFunction(), FI)));
4556 }
4557 lastInsIndex = index;
4558 }
4559 }
4560 }
4561
4562 // varargs
4563 if (isVarArg && MFI.hasVAStart()) {
4564 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4565 TotalArgRegsSaveSize);
4566 if (AFI->isCmseNSEntryFunction()) {
4567 DiagnosticInfoUnsupported Diag(
4568 DAG.getMachineFunction().getFunction(),
4569 "secure entry function must not be variadic", dl.getDebugLoc());
4570 DAG.getContext()->diagnose(Diag);
4571 }
4572 }
4573
4574 unsigned StackArgSize = CCInfo.getNextStackOffset();
4575 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4576 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4577 // The only way to guarantee a tail call is if the callee restores its
4578 // argument area, but it must also keep the stack aligned when doing so.
4579 const DataLayout &DL = DAG.getDataLayout();
4580 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4581
4582 AFI->setArgumentStackToRestore(StackArgSize);
4583 }
4584 AFI->setArgumentStackSize(StackArgSize);
4585
4586 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4587 DiagnosticInfoUnsupported Diag(
4588 DAG.getMachineFunction().getFunction(),
4589 "secure entry function requires arguments on stack", dl.getDebugLoc());
4590 DAG.getContext()->diagnose(Diag);
4591 }
4592
4593 return Chain;
4594}
4595
4596/// isFloatingPointZero - Return true if this is +0.0.
4597static bool isFloatingPointZero(SDValue Op) {
4598 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4599 return CFP->getValueAPF().isPosZero();
4600 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4601 // Maybe this has already been legalized into the constant pool?
4602 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4603 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4604 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4605 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4606 return CFP->getValueAPF().isPosZero();
4607 }
4608 } else if (Op->getOpcode() == ISD::BITCAST &&
4609 Op->getValueType(0) == MVT::f64) {
4610 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4611 // created by LowerConstantFP().
4612 SDValue BitcastOp = Op->getOperand(0);
4613 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4614 isNullConstant(BitcastOp->getOperand(0)))
4615 return true;
4616 }
4617 return false;
4618}
4619
4620/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4621/// the given operands.
4622SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4623 SDValue &ARMcc, SelectionDAG &DAG,
4624 const SDLoc &dl) const {
4625 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4626 unsigned C = RHSC->getZExtValue();
4627 if (!isLegalICmpImmediate((int32_t)C)) {
4628 // Constant does not fit, try adjusting it by one.
4629 switch (CC) {
4630 default: break;
4631 case ISD::SETLT:
4632 case ISD::SETGE:
4633 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4634 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4635 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4636 }
4637 break;
4638 case ISD::SETULT:
4639 case ISD::SETUGE:
4640 if (C != 0 && isLegalICmpImmediate(C-1)) {
4641 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4642 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4643 }
4644 break;
4645 case ISD::SETLE:
4646 case ISD::SETGT:
4647 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4648 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4649 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4650 }
4651 break;
4652 case ISD::SETULE:
4653 case ISD::SETUGT:
4654 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4655 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4656 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4657 }
4658 break;
4659 }
4660 }
4661 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4662 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4663 // In ARM and Thumb-2, the compare instructions can shift their second
4664 // operand.
4665 CC = ISD::getSetCCSwappedOperands(CC);
4666 std::swap(LHS, RHS);
4667 }
4668
4669 // Thumb1 has very limited immediate modes, so turning an "and" into a
4670 // shift can save multiple instructions.
4671 //
4672 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4673 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4674 // own. If it's the operand to an unsigned comparison with an immediate,
4675 // we can eliminate one of the shifts: we transform
4676 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4677 //
4678 // We avoid transforming cases which aren't profitable due to encoding
4679 // details:
4680 //
4681 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4682 // would not; in that case, we're essentially trading one immediate load for
4683 // another.
4684 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4685 // 3. C2 is zero; we have other code for this special case.
4686 //
4687 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4688 // instruction, since the AND is always one instruction anyway, but we could
4689 // use narrow instructions in some cases.
4690 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4691 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4692 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4693 !isSignedIntSetCC(CC)) {
4694 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4695 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4696 uint64_t RHSV = RHSC->getZExtValue();
4697 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4698 unsigned ShiftBits = countLeadingZeros(Mask);
4699 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4700 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4701 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4702 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4703 }
4704 }
4705 }
4706
4707 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4708 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4709 // way a cmp would.
4710 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4711 // some tweaks to the heuristics for the previous and->shift transform.
4712 // FIXME: Optimize cases where the LHS isn't a shift.
4713 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4714 isa<ConstantSDNode>(RHS) &&
4715 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4716 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4717 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4718 unsigned ShiftAmt =
4719 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4720 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4721 DAG.getVTList(MVT::i32, MVT::i32),
4722 LHS.getOperand(0),
4723 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4724 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4725 Shift.getValue(1), SDValue());
4726 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4727 return Chain.getValue(1);
4728 }
4729
4730 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4731
4732 // If the RHS is a constant zero then the V (overflow) flag will never be
4733 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4734 // simpler for other passes (like the peephole optimiser) to deal with.
4735 if (isNullConstant(RHS)) {
4736 switch (CondCode) {
4737 default: break;
4738 case ARMCC::GE:
4739 CondCode = ARMCC::PL;
4740 break;
4741 case ARMCC::LT:
4742 CondCode = ARMCC::MI;
4743 break;
4744 }
4745 }
4746
4747 ARMISD::NodeType CompareType;
4748 switch (CondCode) {
4749 default:
4750 CompareType = ARMISD::CMP;
4751 break;
4752 case ARMCC::EQ:
4753 case ARMCC::NE:
4754 // Uses only Z Flag
4755 CompareType = ARMISD::CMPZ;
4756 break;
4757 }
4758 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4759 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4760}
4761
4762/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4763SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4764 SelectionDAG &DAG, const SDLoc &dl,
4765 bool Signaling) const {
4766 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4766, __extension__ __PRETTY_FUNCTION__))
;
4767 SDValue Cmp;
4768 if (!isFloatingPointZero(RHS))
4769 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4770 dl, MVT::Glue, LHS, RHS);
4771 else
4772 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4773 dl, MVT::Glue, LHS);
4774 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4775}
4776
4777/// duplicateCmp - Glue values can have only one use, so this function
4778/// duplicates a comparison node.
4779SDValue
4780ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4781 unsigned Opc = Cmp.getOpcode();
4782 SDLoc DL(Cmp);
4783 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4784 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4785
4786 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4786, __extension__ __PRETTY_FUNCTION__))
;
4787 Cmp = Cmp.getOperand(0);
4788 Opc = Cmp.getOpcode();
4789 if (Opc == ARMISD::CMPFP)
4790 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4791 else {
4792 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4792, __extension__ __PRETTY_FUNCTION__))
;
4793 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4794 }
4795 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4796}
4797
4798// This function returns three things: the arithmetic computation itself
4799// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4800// comparison and the condition code define the case in which the arithmetic
4801// computation *does not* overflow.
4802std::pair<SDValue, SDValue>
4803ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4804 SDValue &ARMcc) const {
4805 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4805, __extension__ __PRETTY_FUNCTION__))
;
4806
4807 SDValue Value, OverflowCmp;
4808 SDValue LHS = Op.getOperand(0);
4809 SDValue RHS = Op.getOperand(1);
4810 SDLoc dl(Op);
4811
4812 // FIXME: We are currently always generating CMPs because we don't support
4813 // generating CMN through the backend. This is not as good as the natural
4814 // CMP case because it causes a register dependency and cannot be folded
4815 // later.
4816
4817 switch (Op.getOpcode()) {
4818 default:
4819 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4819)
;
4820 case ISD::SADDO:
4821 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4822 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4823 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4824 break;
4825 case ISD::UADDO:
4826 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4827 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4828 // We do not use it in the USUBO case as Value may not be used.
4829 Value = DAG.getNode(ARMISD::ADDC, dl,
4830 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4831 .getValue(0);
4832 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4833 break;
4834 case ISD::SSUBO:
4835 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4836 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4837 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4838 break;
4839 case ISD::USUBO:
4840 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4841 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4842 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4843 break;
4844 case ISD::UMULO:
4845 // We generate a UMUL_LOHI and then check if the high word is 0.
4846 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4847 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4848 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4849 LHS, RHS);
4850 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4851 DAG.getConstant(0, dl, MVT::i32));
4852 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4853 break;
4854 case ISD::SMULO:
4855 // We generate a SMUL_LOHI and then check if all the bits of the high word
4856 // are the same as the sign bit of the low word.
4857 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4858 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4859 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4860 LHS, RHS);
4861 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4862 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4863 Value.getValue(0),
4864 DAG.getConstant(31, dl, MVT::i32)));
4865 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4866 break;
4867 } // switch (...)
4868
4869 return std::make_pair(Value, OverflowCmp);
4870}
4871
4872SDValue
4873ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4874 // Let legalize expand this if it isn't a legal type yet.
4875 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4876 return SDValue();
4877
4878 SDValue Value, OverflowCmp;
4879 SDValue ARMcc;
4880 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4881 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4882 SDLoc dl(Op);
4883 // We use 0 and 1 as false and true values.
4884 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4885 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4886 EVT VT = Op.getValueType();
4887
4888 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4889 ARMcc, CCR, OverflowCmp);
4890
4891 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4892 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4893}
4894
4895static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4896 SelectionDAG &DAG) {
4897 SDLoc DL(BoolCarry);
4898 EVT CarryVT = BoolCarry.getValueType();
4899
4900 // This converts the boolean value carry into the carry flag by doing
4901 // ARMISD::SUBC Carry, 1
4902 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4903 DAG.getVTList(CarryVT, MVT::i32),
4904 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4905 return Carry.getValue(1);
4906}
4907
4908static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4909 SelectionDAG &DAG) {
4910 SDLoc DL(Flags);
4911
4912 // Now convert the carry flag into a boolean carry. We do this
4913 // using ARMISD:ADDE 0, 0, Carry
4914 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4915 DAG.getConstant(0, DL, MVT::i32),
4916 DAG.getConstant(0, DL, MVT::i32), Flags);
4917}
4918
4919SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4920 SelectionDAG &DAG) const {
4921 // Let legalize expand this if it isn't a legal type yet.
4922 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4923 return SDValue();
4924
4925 SDValue LHS = Op.getOperand(0);
4926 SDValue RHS = Op.getOperand(1);
4927 SDLoc dl(Op);
4928
4929 EVT VT = Op.getValueType();
4930 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4931 SDValue Value;
4932 SDValue Overflow;
4933 switch (Op.getOpcode()) {
4934 default:
4935 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4935)
;
4936 case ISD::UADDO:
4937 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4938 // Convert the carry flag into a boolean value.
4939 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4940 break;
4941 case ISD::USUBO: {
4942 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4943 // Convert the carry flag into a boolean value.
4944 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4945 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4946 // value. So compute 1 - C.
4947 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4948 DAG.getConstant(1, dl, MVT::i32), Overflow);
4949 break;
4950 }
4951 }
4952
4953 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4954}
4955
4956static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4957 const ARMSubtarget *Subtarget) {
4958 EVT VT = Op.getValueType();
4959 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
3
Assuming the condition is false
4
Assuming the condition is false
5
Taking false branch
4960 return SDValue();
4961 if (!VT.isSimple())
6
Calling 'EVT::isSimple'
9
Returning from 'EVT::isSimple'
10
Taking false branch
4962 return SDValue();
4963
4964 unsigned NewOpcode;
11
'NewOpcode' declared without an initial value
4965 switch (VT.getSimpleVT().SimpleTy) {
12
Control jumps to 'case i16:' at line 4984
4966 default:
4967 return SDValue();
4968 case MVT::i8:
4969 switch (Op->getOpcode()) {
4970 case ISD::UADDSAT:
4971 NewOpcode = ARMISD::UQADD8b;
4972 break;
4973 case ISD::SADDSAT:
4974 NewOpcode = ARMISD::QADD8b;
4975 break;
4976 case ISD::USUBSAT:
4977 NewOpcode = ARMISD::UQSUB8b;
4978 break;
4979 case ISD::SSUBSAT:
4980 NewOpcode = ARMISD::QSUB8b;
4981 break;
4982 }
4983 break;
4984 case MVT::i16:
4985 switch (Op->getOpcode()) {
13
'Default' branch taken. Execution continues on line 4999
4986 case ISD::UADDSAT:
4987 NewOpcode = ARMISD::UQADD16b;
4988 break;
4989 case ISD::SADDSAT:
4990 NewOpcode = ARMISD::QADD16b;
4991 break;
4992 case ISD::USUBSAT:
4993 NewOpcode = ARMISD::UQSUB16b;
4994 break;
4995 case ISD::SSUBSAT:
4996 NewOpcode = ARMISD::QSUB16b;
4997 break;
4998 }
4999 break;
14
Execution continues on line 5002
5000 }
5001
5002 SDLoc dl(Op);
5003 SDValue Add =
5004 DAG.getNode(NewOpcode, dl, MVT::i32,
15
1st function call argument is an uninitialized value
5005 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5006 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5007 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5008}
5009
5010SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5011 SDValue Cond = Op.getOperand(0);
5012 SDValue SelectTrue = Op.getOperand(1);
5013 SDValue SelectFalse = Op.getOperand(2);
5014 SDLoc dl(Op);
5015 unsigned Opc = Cond.getOpcode();
5016
5017 if (Cond.getResNo() == 1 &&
5018 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5019 Opc == ISD::USUBO)) {
5020 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5021 return SDValue();
5022
5023 SDValue Value, OverflowCmp;
5024 SDValue ARMcc;
5025 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5026 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5027 EVT VT = Op.getValueType();
5028
5029 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5030 OverflowCmp, DAG);
5031 }
5032
5033 // Convert:
5034 //
5035 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5036 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5037 //
5038 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5039 const ConstantSDNode *CMOVTrue =
5040 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5041 const ConstantSDNode *CMOVFalse =
5042 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5043
5044 if (CMOVTrue && CMOVFalse) {
5045 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5046 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5047
5048 SDValue True;
5049 SDValue False;
5050 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5051 True = SelectTrue;
5052 False = SelectFalse;
5053 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5054 True = SelectFalse;
5055 False = SelectTrue;
5056 }
5057
5058 if (True.getNode() && False.getNode()) {
5059 EVT VT = Op.getValueType();
5060 SDValue ARMcc = Cond.getOperand(2);
5061 SDValue CCR = Cond.getOperand(3);
5062 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5063 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5063, __extension__ __PRETTY_FUNCTION__))
;
5064 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5065 }
5066 }
5067 }
5068
5069 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5070 // undefined bits before doing a full-word comparison with zero.
5071 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5072 DAG.getConstant(1, dl, Cond.getValueType()));
5073
5074 return DAG.getSelectCC(dl, Cond,
5075 DAG.getConstant(0, dl, Cond.getValueType()),
5076 SelectTrue, SelectFalse, ISD::SETNE);
5077}
5078
5079static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5080 bool &swpCmpOps, bool &swpVselOps) {
5081 // Start by selecting the GE condition code for opcodes that return true for
5082 // 'equality'
5083 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5084 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5085 CondCode = ARMCC::GE;
5086
5087 // and GT for opcodes that return false for 'equality'.
5088 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5089 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5090 CondCode = ARMCC::GT;
5091
5092 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5093 // to swap the compare operands.
5094 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5095 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5096 swpCmpOps = true;
5097
5098 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5099 // If we have an unordered opcode, we need to swap the operands to the VSEL
5100 // instruction (effectively negating the condition).
5101 //
5102 // This also has the effect of swapping which one of 'less' or 'greater'
5103 // returns true, so we also swap the compare operands. It also switches
5104 // whether we return true for 'equality', so we compensate by picking the
5105 // opposite condition code to our original choice.
5106 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5107 CC == ISD::SETUGT) {
5108 swpCmpOps = !swpCmpOps;
5109 swpVselOps = !swpVselOps;
5110 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5111 }
5112
5113 // 'ordered' is 'anything but unordered', so use the VS condition code and
5114 // swap the VSEL operands.
5115 if (CC == ISD::SETO) {
5116 CondCode = ARMCC::VS;
5117 swpVselOps = true;
5118 }
5119
5120 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5121 // code and swap the VSEL operands. Also do this if we don't care about the
5122 // unordered case.
5123 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5124 CondCode = ARMCC::EQ;
5125 swpVselOps = true;
5126 }
5127}
5128
5129SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5130 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5131 SDValue Cmp, SelectionDAG &DAG) const {
5132 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5133 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5134 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5135 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5136 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5137
5138 SDValue TrueLow = TrueVal.getValue(0);
5139 SDValue TrueHigh = TrueVal.getValue(1);
5140 SDValue FalseLow = FalseVal.getValue(0);
5141 SDValue FalseHigh = FalseVal.getValue(1);
5142
5143 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5144 ARMcc, CCR, Cmp);
5145 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5146 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5147
5148 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5149 } else {
5150 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5151 Cmp);
5152 }
5153}
5154
5155static bool isGTorGE(ISD::CondCode CC) {
5156 return CC == ISD::SETGT || CC == ISD::SETGE;
5157}
5158
5159static bool isLTorLE(ISD::CondCode CC) {
5160 return CC == ISD::SETLT || CC == ISD::SETLE;
5161}
5162
5163// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5164// All of these conditions (and their <= and >= counterparts) will do:
5165// x < k ? k : x
5166// x > k ? x : k
5167// k < x ? x : k
5168// k > x ? k : x
5169static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5170 const SDValue TrueVal, const SDValue FalseVal,
5171 const ISD::CondCode CC, const SDValue K) {
5172 return (isGTorGE(CC) &&
5173 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5174 (isLTorLE(CC) &&
5175 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5176}
5177
5178// Check if two chained conditionals could be converted into SSAT or USAT.
5179//
5180// SSAT can replace a set of two conditional selectors that bound a number to an
5181// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5182//
5183// x < -k ? -k : (x > k ? k : x)
5184// x < -k ? -k : (x < k ? x : k)
5185// x > -k ? (x > k ? k : x) : -k
5186// x < k ? (x < -k ? -k : x) : k
5187// etc.
5188//
5189// LLVM canonicalizes these to either a min(max()) or a max(min())
5190// pattern. This function tries to match one of these and will return a SSAT
5191// node if successful.
5192//
5193// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5194// is a power of 2.
5195static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5196 EVT VT = Op.getValueType();
5197 SDValue V1 = Op.getOperand(0);
5198 SDValue K1 = Op.getOperand(1);
5199 SDValue TrueVal1 = Op.getOperand(2);
5200 SDValue FalseVal1 = Op.getOperand(3);
5201 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5202
5203 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5204 if (Op2.getOpcode() != ISD::SELECT_CC)
5205 return SDValue();
5206
5207 SDValue V2 = Op2.getOperand(0);
5208 SDValue K2 = Op2.getOperand(1);
5209 SDValue TrueVal2 = Op2.getOperand(2);
5210 SDValue FalseVal2 = Op2.getOperand(3);
5211 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5212
5213 SDValue V1Tmp = V1;
5214 SDValue V2Tmp = V2;
5215
5216 // Check that the registers and the constants match a max(min()) or min(max())
5217 // pattern
5218 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5219 K2 != FalseVal2 ||
5220 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5221 return SDValue();
5222
5223 // Check that the constant in the lower-bound check is
5224 // the opposite of the constant in the upper-bound check
5225 // in 1's complement.
5226 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5227 return SDValue();
5228
5229 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5230 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5231 int64_t PosVal = std::max(Val1, Val2);
5232 int64_t NegVal = std::min(Val1, Val2);
5233
5234 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5235 !isPowerOf2_64(PosVal + 1))
5236 return SDValue();
5237
5238 // Handle the difference between USAT (unsigned) and SSAT (signed)
5239 // saturation
5240 // At this point, PosVal is guaranteed to be positive
5241 uint64_t K = PosVal;
5242 SDLoc dl(Op);
5243 if (Val1 == ~Val2)
5244 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5245 DAG.getConstant(countTrailingOnes(K), dl, VT));
5246 if (NegVal == 0)
5247 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5248 DAG.getConstant(countTrailingOnes(K), dl, VT));
5249
5250 return SDValue();
5251}
5252
5253// Check if a condition of the type x < k ? k : x can be converted into a
5254// bit operation instead of conditional moves.
5255// Currently this is allowed given:
5256// - The conditions and values match up
5257// - k is 0 or -1 (all ones)
5258// This function will not check the last condition, thats up to the caller
5259// It returns true if the transformation can be made, and in such case
5260// returns x in V, and k in SatK.
5261static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5262 SDValue &SatK)
5263{
5264 SDValue LHS = Op.getOperand(0);
5265 SDValue RHS = Op.getOperand(1);
5266 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5267 SDValue TrueVal = Op.getOperand(2);
5268 SDValue FalseVal = Op.getOperand(3);
5269
5270 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5271 ? &RHS
5272 : nullptr;
5273
5274 // No constant operation in comparison, early out
5275 if (!K)
5276 return false;
5277
5278 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5279 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5280 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5281
5282 // If the constant on left and right side, or variable on left and right,
5283 // does not match, early out
5284 if (*K != KTmp || V != VTmp)
5285 return false;
5286
5287 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5288 SatK = *K;
5289 return true;
5290 }
5291
5292 return false;
5293}
5294
5295bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5296 if (VT == MVT::f32)
5297 return !Subtarget->hasVFP2Base();
5298 if (VT == MVT::f64)
5299 return !Subtarget->hasFP64();
5300 if (VT == MVT::f16)
5301 return !Subtarget->hasFullFP16();
5302 return false;
5303}
5304
5305SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5306 EVT VT = Op.getValueType();
5307 SDLoc dl(Op);
5308
5309 // Try to convert two saturating conditional selects into a single SSAT
5310 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5311 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5312 return SatValue;
5313
5314 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5315 // into more efficient bit operations, which is possible when k is 0 or -1
5316 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5317 // single instructions. On Thumb the shift and the bit operation will be two
5318 // instructions.
5319 // Only allow this transformation on full-width (32-bit) operations
5320 SDValue LowerSatConstant;
5321 SDValue SatValue;
5322 if (VT == MVT::i32 &&
5323 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5324 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5325 DAG.getConstant(31, dl, VT));
5326 if (isNullConstant(LowerSatConstant)) {
5327 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5328 DAG.getAllOnesConstant(dl, VT));
5329 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5330 } else if (isAllOnesConstant(LowerSatConstant))
5331 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5332 }
5333
5334 SDValue LHS = Op.getOperand(0);
5335 SDValue RHS = Op.getOperand(1);
5336 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5337 SDValue TrueVal = Op.getOperand(2);
5338 SDValue FalseVal = Op.getOperand(3);
5339 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5340 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5341
5342 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5343 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5344 unsigned TVal = CTVal->getZExtValue();
5345 unsigned FVal = CFVal->getZExtValue();
5346 unsigned Opcode = 0;
5347
5348 if (TVal == ~FVal) {
5349 Opcode = ARMISD::CSINV;
5350 } else if (TVal == ~FVal + 1) {
5351 Opcode = ARMISD::CSNEG;
5352 } else if (TVal + 1 == FVal) {
5353 Opcode = ARMISD::CSINC;
5354 } else if (TVal == FVal + 1) {
5355 Opcode = ARMISD::CSINC;
5356 std::swap(TrueVal, FalseVal);
5357 std::swap(TVal, FVal);
5358 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5359 }
5360
5361 if (Opcode) {
5362 // If one of the constants is cheaper than another, materialise the
5363 // cheaper one and let the csel generate the other.
5364 if (Opcode != ARMISD::CSINC &&
5365 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5366 std::swap(TrueVal, FalseVal);
5367 std::swap(TVal, FVal);
5368 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5369 }
5370
5371 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5372 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5373 // -(-a) == a, but (a+1)+1 != a).
5374 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5375 std::swap(TrueVal, FalseVal);
5376 std::swap(TVal, FVal);
5377 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5378 }
5379
5380 // Drops F's value because we can get it by inverting/negating TVal.
5381 FalseVal = TrueVal;
5382
5383 SDValue ARMcc;
5384 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5385 EVT VT = TrueVal.getValueType();
5386 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5387 }
5388 }
5389
5390 if (isUnsupportedFloatingType(LHS.getValueType())) {
5391 DAG.getTargetLoweringInfo().softenSetCCOperands(
5392 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5393
5394 // If softenSetCCOperands only returned one value, we should compare it to
5395 // zero.
5396 if (!RHS.getNode()) {
5397 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5398 CC = ISD::SETNE;
5399 }
5400 }
5401
5402 if (LHS.getValueType() == MVT::i32) {
5403 // Try to generate VSEL on ARMv8.
5404 // The VSEL instruction can't use all the usual ARM condition
5405 // codes: it only has two bits to select the condition code, so it's
5406 // constrained to use only GE, GT, VS and EQ.
5407 //
5408 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5409 // swap the operands of the previous compare instruction (effectively
5410 // inverting the compare condition, swapping 'less' and 'greater') and
5411 // sometimes need to swap the operands to the VSEL (which inverts the
5412 // condition in the sense of firing whenever the previous condition didn't)
5413 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5414 TrueVal.getValueType() == MVT::f32 ||
5415 TrueVal.getValueType() == MVT::f64)) {
5416 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5417 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5418 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5419 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5420 std::swap(TrueVal, FalseVal);
5421 }
5422 }
5423
5424 SDValue ARMcc;
5425 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5426 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5427 // Choose GE over PL, which vsel does now support
5428 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5429 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5430 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5431 }
5432
5433 ARMCC::CondCodes CondCode, CondCode2;
5434 FPCCToARMCC(CC, CondCode, CondCode2);
5435
5436 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5437 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5438 // must use VSEL (limited condition codes), due to not having conditional f16
5439 // moves.
5440 if (Subtarget->hasFPARMv8Base() &&
5441 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5442 (TrueVal.getValueType() == MVT::f16 ||
5443 TrueVal.getValueType() == MVT::f32 ||
5444 TrueVal.getValueType() == MVT::f64)) {
5445 bool swpCmpOps = false;
5446 bool swpVselOps = false;
5447 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5448
5449 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5450 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5451 if (swpCmpOps)
5452 std::swap(LHS, RHS);
5453 if (swpVselOps)
5454 std::swap(TrueVal, FalseVal);
5455 }
5456 }
5457
5458 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5459 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5460 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5461 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5462 if (CondCode2 != ARMCC::AL) {
5463 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5464 // FIXME: Needs another CMP because flag can have but one use.
5465 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5466 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5467 }
5468 return Result;
5469}
5470
5471/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5472/// to morph to an integer compare sequence.
5473static bool canChangeToInt(SDValue Op, bool &SeenZero,
5474 const ARMSubtarget *Subtarget) {
5475 SDNode *N = Op.getNode();
5476 if (!N->hasOneUse())
5477 // Otherwise it requires moving the value from fp to integer registers.
5478 return false;
5479 if (!N->getNumValues())
5480 return false;
5481 EVT VT = Op.getValueType();
5482 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5483 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5484 // vmrs are very slow, e.g. cortex-a8.
5485 return false;
5486
5487 if (isFloatingPointZero(Op)) {
5488 SeenZero = true;
5489 return true;
5490 }
5491 return ISD::isNormalLoad(N);
5492}
5493
5494static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5495 if (isFloatingPointZero(Op))
5496 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5497
5498 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5499 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5500 Ld->getPointerInfo(), Ld->getAlignment(),
5501 Ld->getMemOperand()->getFlags());
5502
5503 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5503)
;
5504}
5505
5506static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5507 SDValue &RetVal1, SDValue &RetVal2) {
5508 SDLoc dl(Op);
5509
5510 if (isFloatingPointZero(Op)) {
5511 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5512 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5513 return;
5514 }
5515
5516 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5517 SDValue Ptr = Ld->getBasePtr();
5518 RetVal1 =
5519 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5520 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5521
5522 EVT PtrType = Ptr.getValueType();
5523 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5524 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5525 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5526 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5527 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5528 Ld->getMemOperand()->getFlags());
5529 return;
5530 }
5531
5532 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5532)
;
5533}
5534
5535/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5536/// f32 and even f64 comparisons to integer ones.
5537SDValue
5538ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5539 SDValue Chain = Op.getOperand(0);
5540 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5541 SDValue LHS = Op.getOperand(2);
5542 SDValue RHS = Op.getOperand(3);
5543 SDValue Dest = Op.getOperand(4);
5544 SDLoc dl(Op);
5545
5546 bool LHSSeenZero = false;
5547 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5548 bool RHSSeenZero = false;
5549 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5550 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5551 // If unsafe fp math optimization is enabled and there are no other uses of
5552 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5553 // to an integer comparison.
5554 if (CC == ISD::SETOEQ)
5555 CC = ISD::SETEQ;
5556 else if (CC == ISD::SETUNE)
5557 CC = ISD::SETNE;
5558
5559 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5560 SDValue ARMcc;
5561 if (LHS.getValueType() == MVT::f32) {
5562 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5563 bitcastf32Toi32(LHS, DAG), Mask);
5564 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5565 bitcastf32Toi32(RHS, DAG), Mask);
5566 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5567 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5568 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5569 Chain, Dest, ARMcc, CCR, Cmp);
5570 }
5571
5572 SDValue LHS1, LHS2;
5573 SDValue RHS1, RHS2;
5574 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5575 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5576 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5577 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5578 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5579 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5580 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5581 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5582 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5583 }
5584
5585 return SDValue();
5586}
5587
5588SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5589 SDValue Chain = Op.getOperand(0);
5590 SDValue Cond = Op.getOperand(1);
5591 SDValue Dest = Op.getOperand(2);
5592 SDLoc dl(Op);
5593
5594 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5595 // instruction.
5596 unsigned Opc = Cond.getOpcode();
5597 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5598 !Subtarget->isThumb1Only();
5599 if (Cond.getResNo() == 1 &&
5600 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5601 Opc == ISD::USUBO || OptimizeMul)) {
5602 // Only lower legal XALUO ops.
5603 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5604 return SDValue();
5605
5606 // The actual operation with overflow check.
5607 SDValue Value, OverflowCmp;
5608 SDValue ARMcc;
5609 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5610
5611 // Reverse the condition code.
5612 ARMCC::CondCodes CondCode =
5613 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5614 CondCode = ARMCC::getOppositeCondition(CondCode);
5615 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5616 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5617
5618 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5619 OverflowCmp);
5620 }
5621
5622 return SDValue();
5623}
5624
5625SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5626 SDValue Chain = Op.getOperand(0);
5627 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5628 SDValue LHS = Op.getOperand(2);
5629 SDValue RHS = Op.getOperand(3);
5630 SDValue Dest = Op.getOperand(4);
5631 SDLoc dl(Op);
5632
5633 if (isUnsupportedFloatingType(LHS.getValueType())) {
5634 DAG.getTargetLoweringInfo().softenSetCCOperands(
5635 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5636
5637 // If softenSetCCOperands only returned one value, we should compare it to
5638 // zero.
5639 if (!RHS.getNode()) {
5640 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5641 CC = ISD::SETNE;
5642 }
5643 }
5644
5645 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5646 // instruction.
5647 unsigned Opc = LHS.getOpcode();
5648 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5649 !Subtarget->isThumb1Only();
5650 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5651 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5652 Opc == ISD::USUBO || OptimizeMul) &&
5653 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5654 // Only lower legal XALUO ops.
5655 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5656 return SDValue();
5657
5658 // The actual operation with overflow check.
5659 SDValue Value, OverflowCmp;
5660 SDValue ARMcc;
5661 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5662
5663 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5664 // Reverse the condition code.
5665 ARMCC::CondCodes CondCode =
5666 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5667 CondCode = ARMCC::getOppositeCondition(CondCode);
5668 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5669 }
5670 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5671
5672 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5673 OverflowCmp);
5674 }
5675
5676 if (LHS.getValueType() == MVT::i32) {
5677 SDValue ARMcc;
5678 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5679 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5680 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5681 Chain, Dest, ARMcc, CCR, Cmp);
5682 }
5683
5684 if (getTargetMachine().Options.UnsafeFPMath &&
5685 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5686 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5687 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5688 return Result;
5689 }
5690
5691 ARMCC::CondCodes CondCode, CondCode2;
5692 FPCCToARMCC(CC, CondCode, CondCode2);
5693
5694 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5695 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5696 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5697 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5698 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5699 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5700 if (CondCode2 != ARMCC::AL) {
5701 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5702 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5703 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5704 }
5705 return Res;
5706}
5707
5708SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5709 SDValue Chain = Op.getOperand(0);
5710 SDValue Table = Op.getOperand(1);
5711 SDValue Index = Op.getOperand(2);
5712 SDLoc dl(Op);
5713
5714 EVT PTy = getPointerTy(DAG.getDataLayout());
5715 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5716 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5717 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5718 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5719 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5720 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5721 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5722 // which does another jump to the destination. This also makes it easier
5723 // to translate it to TBB / TBH later (Thumb2 only).
5724 // FIXME: This might not work if the function is extremely large.
5725 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5726 Addr, Op.getOperand(2), JTI);
5727 }
5728 if (isPositionIndependent() || Subtarget->isROPI()) {
5729 Addr =
5730 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5731 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5732 Chain = Addr.getValue(1);
5733 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5734 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5735 } else {
5736 Addr =
5737 DAG.getLoad(PTy, dl, Chain, Addr,
5738 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5739 Chain = Addr.getValue(1);
5740 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5741 }
5742}
5743
5744static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5745 EVT VT = Op.getValueType();
5746 SDLoc dl(Op);
5747
5748 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5749 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5750 return Op;
5751 return DAG.UnrollVectorOp(Op.getNode());
5752 }
5753
5754 const bool HasFullFP16 =
5755 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5756
5757 EVT NewTy;
5758 const EVT OpTy = Op.getOperand(0).getValueType();
5759 if (OpTy == MVT::v4f32)
5760 NewTy = MVT::v4i32;
5761 else if (OpTy == MVT::v4f16 && HasFullFP16)
5762 NewTy = MVT::v4i16;
5763 else if (OpTy == MVT::v8f16 && HasFullFP16)
5764 NewTy = MVT::v8i16;
5765 else
5766 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5766)
;
5767
5768 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5769 return DAG.UnrollVectorOp(Op.getNode());
5770
5771 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5772 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5773}
5774
5775SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5776 EVT VT = Op.getValueType();
5777 if (VT.isVector())
5778 return LowerVectorFP_TO_INT(Op, DAG);
5779
5780 bool IsStrict = Op->isStrictFPOpcode();
5781 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5782
5783 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5784 RTLIB::Libcall LC;
5785 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5786 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5787 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5788 Op.getValueType());
5789 else
5790 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5791 Op.getValueType());
5792 SDLoc Loc(Op);
5793 MakeLibCallOptions CallOptions;
5794 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5795 SDValue Result;
5796 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5797 CallOptions, Loc, Chain);
5798 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5799 }
5800
5801 // FIXME: Remove this when we have strict fp instruction selection patterns
5802 if (IsStrict) {
5803 SDLoc Loc(Op);
5804 SDValue Result =
5805 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5806 : ISD::FP_TO_UINT,
5807 Loc, Op.getValueType(), SrcVal);
5808 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5809 }
5810
5811 return Op;
5812}
5813
5814static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5815 EVT VT = Op.getValueType();
5816 SDLoc dl(Op);
5817
5818 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5819 if (VT.getVectorElementType() == MVT::f32)
5820 return Op;
5821 return DAG.UnrollVectorOp(Op.getNode());
5822 }
5823
5824 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5826, __extension__ __PRETTY_FUNCTION__))
5825 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5826, __extension__ __PRETTY_FUNCTION__))
5826 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5826, __extension__ __PRETTY_FUNCTION__))
;
5827
5828 const bool HasFullFP16 =
5829 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5830
5831 EVT DestVecType;
5832 if (VT == MVT::v4f32)
5833 DestVecType = MVT::v4i32;
5834 else if (VT == MVT::v4f16 && HasFullFP16)
5835 DestVecType = MVT::v4i16;
5836 else if (VT == MVT::v8f16 && HasFullFP16)
5837 DestVecType = MVT::v8i16;
5838 else
5839 return DAG.UnrollVectorOp(Op.getNode());
5840
5841 unsigned CastOpc;
5842 unsigned Opc;
5843 switch (Op.getOpcode()) {
5844 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5844)
;
5845 case ISD::SINT_TO_FP:
5846 CastOpc = ISD::SIGN_EXTEND;
5847 Opc = ISD::SINT_TO_FP;
5848 break;
5849 case ISD::UINT_TO_FP:
5850 CastOpc = ISD::ZERO_EXTEND;
5851 Opc = ISD::UINT_TO_FP;
5852 break;
5853 }
5854
5855 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5856 return DAG.getNode(Opc, dl, VT, Op);
5857}
5858
5859SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5860 EVT VT = Op.getValueType();
5861 if (VT.isVector())
5862 return LowerVectorINT_TO_FP(Op, DAG);
5863 if (isUnsupportedFloatingType(VT)) {
5864 RTLIB::Libcall LC;
5865 if (Op.getOpcode() == ISD::SINT_TO_FP)
5866 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5867 Op.getValueType());
5868 else
5869 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5870 Op.getValueType());
5871 MakeLibCallOptions CallOptions;
5872 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5873 CallOptions, SDLoc(Op)).first;
5874 }
5875
5876 return Op;
5877}
5878
5879SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5880 // Implement fcopysign with a fabs and a conditional fneg.
5881 SDValue Tmp0 = Op.getOperand(0);
5882 SDValue Tmp1 = Op.getOperand(1);
5883 SDLoc dl(Op);
5884 EVT VT = Op.getValueType();
5885 EVT SrcVT = Tmp1.getValueType();
5886 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5887 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5888 bool UseNEON = !InGPR && Subtarget->hasNEON();
5889
5890 if (UseNEON) {
5891 // Use VBSL to copy the sign bit.
5892 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5893 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5894 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5895 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5896 if (VT == MVT::f64)
5897 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5898 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5899 DAG.getConstant(32, dl, MVT::i32));
5900 else /*if (VT == MVT::f32)*/
5901 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5902 if (SrcVT == MVT::f32) {
5903 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5904 if (VT == MVT::f64)
5905 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5906 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5907 DAG.getConstant(32, dl, MVT::i32));
5908 } else if (VT == MVT::f32)
5909 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5910 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5911 DAG.getConstant(32, dl, MVT::i32));
5912 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5913 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5914
5915 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5916 dl, MVT::i32);
5917 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5918 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5919 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5920
5921 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5922 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5923 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5924 if (VT == MVT::f32) {
5925 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5926 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5927 DAG.getConstant(0, dl, MVT::i32));
5928 } else {
5929 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5930 }
5931
5932 return Res;
5933 }
5934
5935 // Bitcast operand 1 to i32.
5936 if (SrcVT == MVT::f64)
5937 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5938 Tmp1).getValue(1);
5939 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5940
5941 // Or in the signbit with integer operations.
5942 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5943 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5944 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5945 if (VT == MVT::f32) {
5946 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5947 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5948 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5949 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5950 }
5951
5952 // f64: Or the high part with signbit and then combine two parts.
5953 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5954 Tmp0);
5955 SDValue Lo = Tmp0.getValue(0);
5956 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5957 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5958 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5959}
5960
5961SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5962 MachineFunction &MF = DAG.getMachineFunction();
5963 MachineFrameInfo &MFI = MF.getFrameInfo();
5964 MFI.setReturnAddressIsTaken(true);
5965
5966 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5967 return SDValue();
5968
5969 EVT VT = Op.getValueType();
5970 SDLoc dl(Op);
5971 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5972 if (Depth) {
5973 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5974 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5975 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5976 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5977 MachinePointerInfo());
5978 }
5979
5980 // Return LR, which contains the return address. Mark it an implicit live-in.
5981 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5982 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5983}
5984
5985SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5986 const ARMBaseRegisterInfo &ARI =
5987 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5988 MachineFunction &MF = DAG.getMachineFunction();
5989 MachineFrameInfo &MFI = MF.getFrameInfo();
5990 MFI.setFrameAddressIsTaken(true);
5991
5992 EVT VT = Op.getValueType();
5993 SDLoc dl(Op); // FIXME probably not meaningful
5994 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5995 Register FrameReg = ARI.getFrameRegister(MF);
5996 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5997 while (Depth--)
5998 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5999 MachinePointerInfo());
6000 return FrameAddr;
6001}
6002
6003// FIXME? Maybe this could be a TableGen attribute on some registers and
6004// this table could be generated automatically from RegInfo.
6005Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
6006 const MachineFunction &MF) const {
6007 Register Reg = StringSwitch<unsigned>(RegName)
6008 .Case("sp", ARM::SP)
6009 .Default(0);
6010 if (Reg)
6011 return Reg;
6012 report_fatal_error(Twine("Invalid register name \""
6013 + StringRef(RegName) + "\"."));
6014}
6015
6016// Result is 64 bit value so split into two 32 bit values and return as a
6017// pair of values.
6018static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
6019 SelectionDAG &DAG) {
6020 SDLoc DL(N);
6021
6022 // This function is only supposed to be called for i64 type destination.
6023 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 6024, __extension__ __PRETTY_FUNCTION__))
6024 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-13~++20210724100615+c63dbd850182/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 6024, __extension__ __PRETTY_FUNCTION__))
;
6025
6026 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
6027 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
6028 N->getOperand(0),
6029 N->getOperand(1));
6030
6031 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
6032 Read.getValue(1)));
6033 Results.push_back(Read.getOperand(0));
6034}
6035
6036/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
6037/// When \p DstVT, the destination type of \p BC, is on the vector
6038/// register bank and the source of bitcast, \p Op, operates on the same bank,
6039/// it might be possible to combine them, such that everything stays on the
6040/// vector register bank.
6041/// \p return The node that would replace \p BT, if the combine
6042/// is possible.
6043static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
6044 SelectionDAG &DAG) {
6045 SDValue Op = BC->getOperand(0);
6046 EVT DstVT = BC->getValueType(0);
6047
6048 // The only vector instruction that can produce a scalar (remember,
6049 // since the bitcast was about to be turned into VMOVDRR, the source
6050 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
6051 // Moreover, we can do this combine only if there is one use.
6052 // Finally, if the destination type is not a vector, there is not
6053 // much point on forcing everything on the vector bank.
6054 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6055 !Op.hasOneUse())
6056 return SDValue();
6057
6058 // If the index is not constant, we will introduce an additional
6059 // multiply that will stick.
6060 // Give up in that case.
6061 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6062 if (!Index)
6063 return SDValue();
6064 unsigned DstNumElt = DstVT.getVectorNumElements();
6065
6066 // Compute the new index.
6067 const APInt &APIntIndex = Index->getAPIntValue();
6068 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
6069 NewIndex *= APIntIndex;
6070 // Check if the new constant index fits into i32.
6071 if (NewIndex.getBitWidth() > 32)
6072 return SDValue();
6073
6074 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
6075 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
6076 SDLoc dl(Op);
6077 SDValue ExtractSrc = Op.getOperand(0);
6078 EVT VecVT = EVT::getVectorVT(
6079 *DAG.getContext(), DstVT.getScalarType(),
6080 ExtractSrc.getValueType().getVe