Bug Summary

File:build/source/llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 5100, column 7
1st function call argument is an uninitialized value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-17/lib/clang/17 -D _DEBUG -D _GLIBCXX_ASSERTIONS -D _GNU_SOURCE -D _LIBCPP_ENABLE_ASSERTIONS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM -I /build/source/llvm/lib/Target/ARM -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-17/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1683717183 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-05-10-133810-16478-1 -x c++ /build/source/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/MachineValueType.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MathExtras.h"
103#include "llvm/Support/raw_ostream.h"
104#include "llvm/Target/TargetMachine.h"
105#include "llvm/Target/TargetOptions.h"
106#include "llvm/TargetParser/Triple.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <optional>
114#include <string>
115#include <tuple>
116#include <utility>
117#include <vector>
118
119using namespace llvm;
120using namespace llvm::PatternMatch;
121
122#define DEBUG_TYPE"arm-isel" "arm-isel"
123
124STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
125STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
126STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
127STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
128 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
129
130static cl::opt<bool>
131ARMInterworking("arm-interworking", cl::Hidden,
132 cl::desc("Enable / disable ARM interworking (for debugging only)"),
133 cl::init(true));
134
135static cl::opt<bool> EnableConstpoolPromotion(
136 "arm-promote-constant", cl::Hidden,
137 cl::desc("Enable / disable promotion of unnamed_addr constants into "
138 "constant pools"),
139 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
140static cl::opt<unsigned> ConstpoolPromotionMaxSize(
141 "arm-promote-constant-max-size", cl::Hidden,
142 cl::desc("Maximum size of constant to promote into a constant pool"),
143 cl::init(64));
144static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
145 "arm-promote-constant-max-total", cl::Hidden,
146 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
147 cl::init(128));
148
149cl::opt<unsigned>
150MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
151 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
152 cl::init(2));
153
154// The APCS parameter registers.
155static const MCPhysReg GPRArgRegs[] = {
156 ARM::R0, ARM::R1, ARM::R2, ARM::R3
157};
158
159void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
160 if (VT != PromotedLdStVT) {
161 setOperationAction(ISD::LOAD, VT, Promote);
162 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
163
164 setOperationAction(ISD::STORE, VT, Promote);
165 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
166 }
167
168 MVT ElemTy = VT.getVectorElementType();
169 if (ElemTy != MVT::f64)
170 setOperationAction(ISD::SETCC, VT, Custom);
171 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
172 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
173 if (ElemTy == MVT::i32) {
174 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
176 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
177 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
178 } else {
179 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
181 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
182 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
183 }
184 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
185 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
186 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
187 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
188 setOperationAction(ISD::SELECT, VT, Expand);
189 setOperationAction(ISD::SELECT_CC, VT, Expand);
190 setOperationAction(ISD::VSELECT, VT, Expand);
191 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
192 if (VT.isInteger()) {
193 setOperationAction(ISD::SHL, VT, Custom);
194 setOperationAction(ISD::SRA, VT, Custom);
195 setOperationAction(ISD::SRL, VT, Custom);
196 }
197
198 // Neon does not support vector divide/remainder operations.
199 setOperationAction(ISD::SDIV, VT, Expand);
200 setOperationAction(ISD::UDIV, VT, Expand);
201 setOperationAction(ISD::FDIV, VT, Expand);
202 setOperationAction(ISD::SREM, VT, Expand);
203 setOperationAction(ISD::UREM, VT, Expand);
204 setOperationAction(ISD::FREM, VT, Expand);
205 setOperationAction(ISD::SDIVREM, VT, Expand);
206 setOperationAction(ISD::UDIVREM, VT, Expand);
207
208 if (!VT.isFloatingPoint() &&
209 VT != MVT::v2i64 && VT != MVT::v1i64)
210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
211 setOperationAction(Opcode, VT, Legal);
212 if (!VT.isFloatingPoint())
213 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
214 setOperationAction(Opcode, VT, Legal);
215}
216
217void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
218 addRegisterClass(VT, &ARM::DPRRegClass);
219 addTypeForNEON(VT, MVT::f64);
220}
221
222void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
223 addRegisterClass(VT, &ARM::DPairRegClass);
224 addTypeForNEON(VT, MVT::v2f64);
225}
226
227void ARMTargetLowering::setAllExpand(MVT VT) {
228 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
229 setOperationAction(Opc, VT, Expand);
230
231 // We support these really simple operations even on types where all
232 // the actual arithmetic has to be broken down into simpler
233 // operations or turned into library calls.
234 setOperationAction(ISD::BITCAST, VT, Legal);
235 setOperationAction(ISD::LOAD, VT, Legal);
236 setOperationAction(ISD::STORE, VT, Legal);
237 setOperationAction(ISD::UNDEF, VT, Legal);
238}
239
240void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
241 LegalizeAction Action) {
242 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
244 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
245}
246
247void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
248 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
249
250 for (auto VT : IntTypes) {
251 addRegisterClass(VT, &ARM::MQPRRegClass);
252 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
253 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
255 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
256 setOperationAction(ISD::SHL, VT, Custom);
257 setOperationAction(ISD::SRA, VT, Custom);
258 setOperationAction(ISD::SRL, VT, Custom);
259 setOperationAction(ISD::SMIN, VT, Legal);
260 setOperationAction(ISD::SMAX, VT, Legal);
261 setOperationAction(ISD::UMIN, VT, Legal);
262 setOperationAction(ISD::UMAX, VT, Legal);
263 setOperationAction(ISD::ABS, VT, Legal);
264 setOperationAction(ISD::SETCC, VT, Custom);
265 setOperationAction(ISD::MLOAD, VT, Custom);
266 setOperationAction(ISD::MSTORE, VT, Legal);
267 setOperationAction(ISD::CTLZ, VT, Legal);
268 setOperationAction(ISD::CTTZ, VT, Custom);
269 setOperationAction(ISD::BITREVERSE, VT, Legal);
270 setOperationAction(ISD::BSWAP, VT, Legal);
271 setOperationAction(ISD::SADDSAT, VT, Legal);
272 setOperationAction(ISD::UADDSAT, VT, Legal);
273 setOperationAction(ISD::SSUBSAT, VT, Legal);
274 setOperationAction(ISD::USUBSAT, VT, Legal);
275 setOperationAction(ISD::ABDS, VT, Legal);
276 setOperationAction(ISD::ABDU, VT, Legal);
277 setOperationAction(ISD::AVGFLOORS, VT, Legal);
278 setOperationAction(ISD::AVGFLOORU, VT, Legal);
279 setOperationAction(ISD::AVGCEILS, VT, Legal);
280 setOperationAction(ISD::AVGCEILU, VT, Legal);
281
282 // No native support for these.
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SDIV, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
286 setOperationAction(ISD::SREM, VT, Expand);
287 setOperationAction(ISD::UDIVREM, VT, Expand);
288 setOperationAction(ISD::SDIVREM, VT, Expand);
289 setOperationAction(ISD::CTPOP, VT, Expand);
290 setOperationAction(ISD::SELECT, VT, Expand);
291 setOperationAction(ISD::SELECT_CC, VT, Expand);
292
293 // Vector reductions
294 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
299 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
302 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
303
304 if (!HasMVEFP) {
305 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 } else {
310 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
311 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
312 }
313
314 // Pre and Post inc are supported on loads and stores
315 for (unsigned im = (unsigned)ISD::PRE_INC;
316 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
317 setIndexedLoadAction(im, VT, Legal);
318 setIndexedStoreAction(im, VT, Legal);
319 setIndexedMaskedLoadAction(im, VT, Legal);
320 setIndexedMaskedStoreAction(im, VT, Legal);
321 }
322 }
323
324 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
325 for (auto VT : FloatTypes) {
326 addRegisterClass(VT, &ARM::MQPRRegClass);
327 if (!HasMVEFP)
328 setAllExpand(VT);
329
330 // These are legal or custom whether we have MVE.fp or not
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
336 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
337 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
338 setOperationAction(ISD::SETCC, VT, Custom);
339 setOperationAction(ISD::MLOAD, VT, Custom);
340 setOperationAction(ISD::MSTORE, VT, Legal);
341 setOperationAction(ISD::SELECT, VT, Expand);
342 setOperationAction(ISD::SELECT_CC, VT, Expand);
343
344 // Pre and Post inc are supported on loads and stores
345 for (unsigned im = (unsigned)ISD::PRE_INC;
346 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
347 setIndexedLoadAction(im, VT, Legal);
348 setIndexedStoreAction(im, VT, Legal);
349 setIndexedMaskedLoadAction(im, VT, Legal);
350 setIndexedMaskedStoreAction(im, VT, Legal);
351 }
352
353 if (HasMVEFP) {
354 setOperationAction(ISD::FMINNUM, VT, Legal);
355 setOperationAction(ISD::FMAXNUM, VT, Legal);
356 setOperationAction(ISD::FROUND, VT, Legal);
357 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
360 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
361
362 // No native support for these.
363 setOperationAction(ISD::FDIV, VT, Expand);
364 setOperationAction(ISD::FREM, VT, Expand);
365 setOperationAction(ISD::FSQRT, VT, Expand);
366 setOperationAction(ISD::FSIN, VT, Expand);
367 setOperationAction(ISD::FCOS, VT, Expand);
368 setOperationAction(ISD::FPOW, VT, Expand);
369 setOperationAction(ISD::FLOG, VT, Expand);
370 setOperationAction(ISD::FLOG2, VT, Expand);
371 setOperationAction(ISD::FLOG10, VT, Expand);
372 setOperationAction(ISD::FEXP, VT, Expand);
373 setOperationAction(ISD::FEXP2, VT, Expand);
374 setOperationAction(ISD::FNEARBYINT, VT, Expand);
375 }
376 }
377
378 // Custom Expand smaller than legal vector reductions to prevent false zero
379 // items being added.
380 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
387 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
388
389 // We 'support' these types up to bitcast/load/store level, regardless of
390 // MVE integer-only / float support. Only doing FP data processing on the FP
391 // vector types is inhibited at integer-only level.
392 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
393 for (auto VT : LongTypes) {
394 addRegisterClass(VT, &ARM::MQPRRegClass);
395 setAllExpand(VT);
396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
398 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
399 setOperationAction(ISD::VSELECT, VT, Legal);
400 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
401 }
402 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
403
404 // We can do bitwise operations on v2i64 vectors
405 setOperationAction(ISD::AND, MVT::v2i64, Legal);
406 setOperationAction(ISD::OR, MVT::v2i64, Legal);
407 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
408
409 // It is legal to extload from v4i8 to v4i16 or v4i32.
410 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
411 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
412 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
413
414 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
418 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
419 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
420
421 // Some truncating stores are legal too.
422 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
423 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
424 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
425
426 // Pre and Post inc on these are legal, given the correct extends
427 for (unsigned im = (unsigned)ISD::PRE_INC;
428 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
429 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
430 setIndexedLoadAction(im, VT, Legal);
431 setIndexedStoreAction(im, VT, Legal);
432 setIndexedMaskedLoadAction(im, VT, Legal);
433 setIndexedMaskedStoreAction(im, VT, Legal);
434 }
435 }
436
437 // Predicate types
438 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
439 for (auto VT : pTypes) {
440 addRegisterClass(VT, &ARM::VCCRRegClass);
441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
442 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
443 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
444 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
445 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
447 setOperationAction(ISD::SETCC, VT, Custom);
448 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
449 setOperationAction(ISD::LOAD, VT, Custom);
450 setOperationAction(ISD::STORE, VT, Custom);
451 setOperationAction(ISD::TRUNCATE, VT, Custom);
452 setOperationAction(ISD::VSELECT, VT, Expand);
453 setOperationAction(ISD::SELECT, VT, Expand);
454 setOperationAction(ISD::SELECT_CC, VT, Expand);
455
456 if (!HasMVEFP) {
457 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
458 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
459 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
460 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
461 }
462 }
463 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
464 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
465 setOperationAction(ISD::AND, MVT::v2i1, Expand);
466 setOperationAction(ISD::OR, MVT::v2i1, Expand);
467 setOperationAction(ISD::XOR, MVT::v2i1, Expand);
468 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand);
469 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand);
470 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand);
471 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand);
472
473 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
474 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
475 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
476 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
477 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
478 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
479 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
480 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
481}
482
483ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
484 const ARMSubtarget &STI)
485 : TargetLowering(TM), Subtarget(&STI) {
486 RegInfo = Subtarget->getRegisterInfo();
487 Itins = Subtarget->getInstrItineraryData();
488
489 setBooleanContents(ZeroOrOneBooleanContent);
490 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
491
492 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
493 !Subtarget->isTargetWatchOS() && !Subtarget->isTargetDriverKit()) {
494 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
495 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
496 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
497 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
498 : CallingConv::ARM_AAPCS);
499 }
500
501 if (Subtarget->isTargetMachO()) {
502 // Uses VFP for Thumb libfuncs if available.
503 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
504 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
505 static const struct {
506 const RTLIB::Libcall Op;
507 const char * const Name;
508 const ISD::CondCode Cond;
509 } LibraryCalls[] = {
510 // Single-precision floating-point arithmetic.
511 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
512 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
513 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
514 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
515
516 // Double-precision floating-point arithmetic.
517 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
518 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
519 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
520 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
521
522 // Single-precision comparisons.
523 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
524 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
525 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
526 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
527 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
528 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
529 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
530
531 // Double-precision comparisons.
532 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
533 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
534 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
535 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
536 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
537 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
538 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
539
540 // Floating-point to integer conversions.
541 // i64 conversions are done via library routines even when generating VFP
542 // instructions, so use the same ones.
543 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
544 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
545 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
546 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
547
548 // Conversions between floating types.
549 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
550 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
551
552 // Integer to floating-point conversions.
553 // i64 conversions are done via library routines even when generating VFP
554 // instructions, so use the same ones.
555 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
556 // e.g., __floatunsidf vs. __floatunssidfvfp.
557 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
558 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
559 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
560 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
561 };
562
563 for (const auto &LC : LibraryCalls) {
564 setLibcallName(LC.Op, LC.Name);
565 if (LC.Cond != ISD::SETCC_INVALID)
566 setCmpLibcallCC(LC.Op, LC.Cond);
567 }
568 }
569 }
570
571 // These libcalls are not available in 32-bit.
572 setLibcallName(RTLIB::SHL_I128, nullptr);
573 setLibcallName(RTLIB::SRL_I128, nullptr);
574 setLibcallName(RTLIB::SRA_I128, nullptr);
575 setLibcallName(RTLIB::MUL_I128, nullptr);
576 setLibcallName(RTLIB::MULO_I64, nullptr);
577 setLibcallName(RTLIB::MULO_I128, nullptr);
578
579 // RTLIB
580 if (Subtarget->isAAPCS_ABI() &&
581 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
582 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
583 static const struct {
584 const RTLIB::Libcall Op;
585 const char * const Name;
586 const CallingConv::ID CC;
587 const ISD::CondCode Cond;
588 } LibraryCalls[] = {
589 // Double-precision floating-point arithmetic helper functions
590 // RTABI chapter 4.1.2, Table 2
591 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
594 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
595
596 // Double-precision floating-point comparison helper functions
597 // RTABI chapter 4.1.2, Table 3
598 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
599 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
600 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
601 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
602 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
603 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
604 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
605
606 // Single-precision floating-point arithmetic helper functions
607 // RTABI chapter 4.1.2, Table 4
608 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
612
613 // Single-precision floating-point comparison helper functions
614 // RTABI chapter 4.1.2, Table 5
615 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
616 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
617 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
618 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
619 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
620 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
621 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
622
623 // Floating-point to integer conversions.
624 // RTABI chapter 4.1.2, Table 6
625 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633
634 // Conversions between floating types.
635 // RTABI chapter 4.1.2, Table 7
636 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
639
640 // Integer to floating-point conversions.
641 // RTABI chapter 4.1.2, Table 8
642 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
643 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
644 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
645 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
646 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
647 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
650
651 // Long long helper functions
652 // RTABI chapter 4.2, Table 9
653 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
654 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
655 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
656 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
657
658 // Integer division functions
659 // RTABI chapter 4.3.1
660 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
662 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
663 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
664 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
665 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
666 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
667 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
668 };
669
670 for (const auto &LC : LibraryCalls) {
671 setLibcallName(LC.Op, LC.Name);
672 setLibcallCallingConv(LC.Op, LC.CC);
673 if (LC.Cond != ISD::SETCC_INVALID)
674 setCmpLibcallCC(LC.Op, LC.Cond);
675 }
676
677 // EABI dependent RTLIB
678 if (TM.Options.EABIVersion == EABI::EABI4 ||
679 TM.Options.EABIVersion == EABI::EABI5) {
680 static const struct {
681 const RTLIB::Libcall Op;
682 const char *const Name;
683 const CallingConv::ID CC;
684 const ISD::CondCode Cond;
685 } MemOpsLibraryCalls[] = {
686 // Memory operations
687 // RTABI chapter 4.3.4
688 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
689 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
690 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
691 };
692
693 for (const auto &LC : MemOpsLibraryCalls) {
694 setLibcallName(LC.Op, LC.Name);
695 setLibcallCallingConv(LC.Op, LC.CC);
696 if (LC.Cond != ISD::SETCC_INVALID)
697 setCmpLibcallCC(LC.Op, LC.Cond);
698 }
699 }
700 }
701
702 if (Subtarget->isTargetWindows()) {
703 static const struct {
704 const RTLIB::Libcall Op;
705 const char * const Name;
706 const CallingConv::ID CC;
707 } LibraryCalls[] = {
708 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
709 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
710 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
711 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
712 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
713 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
714 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
715 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
716 };
717
718 for (const auto &LC : LibraryCalls) {
719 setLibcallName(LC.Op, LC.Name);
720 setLibcallCallingConv(LC.Op, LC.CC);
721 }
722 }
723
724 // Use divmod compiler-rt calls for iOS 5.0 and later.
725 if (Subtarget->isTargetMachO() &&
726 !(Subtarget->isTargetIOS() &&
727 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
728 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
729 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
730 }
731
732 // The half <-> float conversion functions are always soft-float on
733 // non-watchos platforms, but are needed for some targets which use a
734 // hard-float calling convention by default.
735 if (!Subtarget->isTargetWatchABI()) {
736 if (Subtarget->isAAPCS_ABI()) {
737 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
738 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
739 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
740 } else {
741 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
742 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
743 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
744 }
745 }
746
747 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
748 // a __gnu_ prefix (which is the default).
749 if (Subtarget->isTargetAEABI()) {
750 static const struct {
751 const RTLIB::Libcall Op;
752 const char * const Name;
753 const CallingConv::ID CC;
754 } LibraryCalls[] = {
755 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
756 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
757 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
758 };
759
760 for (const auto &LC : LibraryCalls) {
761 setLibcallName(LC.Op, LC.Name);
762 setLibcallCallingConv(LC.Op, LC.CC);
763 }
764 }
765
766 if (Subtarget->isThumb1Only())
767 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
768 else
769 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
770
771 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
772 Subtarget->hasFPRegs()) {
773 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
774 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
775
776 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
777 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
778 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
779 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
780
781 if (!Subtarget->hasVFP2Base())
782 setAllExpand(MVT::f32);
783 if (!Subtarget->hasFP64())
784 setAllExpand(MVT::f64);
785 }
786
787 if (Subtarget->hasFullFP16()) {
788 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
789 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
790 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
791
792 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
793 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
794 }
795
796 if (Subtarget->hasBF16()) {
797 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
798 setAllExpand(MVT::bf16);
799 if (!Subtarget->hasFullFP16())
800 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
801 }
802
803 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
804 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
805 setTruncStoreAction(VT, InnerVT, Expand);
806 addAllExtLoads(VT, InnerVT, Expand);
807 }
808
809 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
810 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
811
812 setOperationAction(ISD::BSWAP, VT, Expand);
813 }
814
815 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
816 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
817
818 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
819 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
820
821 if (Subtarget->hasMVEIntegerOps())
822 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
823
824 // Combine low-overhead loop intrinsics so that we can lower i1 types.
825 if (Subtarget->hasLOB()) {
826 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC});
827 }
828
829 if (Subtarget->hasNEON()) {
830 addDRTypeForNEON(MVT::v2f32);
831 addDRTypeForNEON(MVT::v8i8);
832 addDRTypeForNEON(MVT::v4i16);
833 addDRTypeForNEON(MVT::v2i32);
834 addDRTypeForNEON(MVT::v1i64);
835
836 addQRTypeForNEON(MVT::v4f32);
837 addQRTypeForNEON(MVT::v2f64);
838 addQRTypeForNEON(MVT::v16i8);
839 addQRTypeForNEON(MVT::v8i16);
840 addQRTypeForNEON(MVT::v4i32);
841 addQRTypeForNEON(MVT::v2i64);
842
843 if (Subtarget->hasFullFP16()) {
844 addQRTypeForNEON(MVT::v8f16);
845 addDRTypeForNEON(MVT::v4f16);
846 }
847
848 if (Subtarget->hasBF16()) {
849 addQRTypeForNEON(MVT::v8bf16);
850 addDRTypeForNEON(MVT::v4bf16);
851 }
852 }
853
854 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
855 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
856 // none of Neon, MVE or VFP supports any arithmetic operations on it.
857 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
858 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
859 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
860 // FIXME: Code duplication: FDIV and FREM are expanded always, see
861 // ARMTargetLowering::addTypeForNEON method for details.
862 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
863 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
864 // FIXME: Create unittest.
865 // In another words, find a way when "copysign" appears in DAG with vector
866 // operands.
867 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
868 // FIXME: Code duplication: SETCC has custom operation action, see
869 // ARMTargetLowering::addTypeForNEON method for details.
870 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
871 // FIXME: Create unittest for FNEG and for FABS.
872 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
873 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
874 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
875 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
876 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
877 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
878 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
879 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
880 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
881 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
882 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
883 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
884 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
885 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
886 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
887 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
888 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
889 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
890 }
891
892 if (Subtarget->hasNEON()) {
893 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
894 // supported for v4f32.
895 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
896 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
897 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
898 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
899 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
900 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
901 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
902 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
903 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
904 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
905 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
906 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
907 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
908 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
909
910 // Mark v2f32 intrinsics.
911 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
912 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
913 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
914 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
915 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
916 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
917 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
918 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
919 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
920 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
921 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
922 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
923 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
924 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
925
926 // Neon does not support some operations on v1i64 and v2i64 types.
927 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
928 // Custom handling for some quad-vector types to detect VMULL.
929 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
930 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
931 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
932 // Custom handling for some vector types to avoid expensive expansions
933 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
934 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
935 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
936 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
937 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
938 // a destination type that is wider than the source, and nor does
939 // it have a FP_TO_[SU]INT instruction with a narrower destination than
940 // source.
941 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
942 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
944 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
945 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
946 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
947 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
948 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
949
950 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
951 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
952
953 // NEON does not have single instruction CTPOP for vectors with element
954 // types wider than 8-bits. However, custom lowering can leverage the
955 // v8i8/v16i8 vcnt instruction.
956 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
957 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
958 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
959 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
960 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
961 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
962
963 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
964 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
965
966 // NEON does not have single instruction CTTZ for vectors.
967 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
968 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
969 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
970 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
971
972 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
973 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
974 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
975 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
976
977 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
978 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
979 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
980 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
981
982 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
983 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
984 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
985 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
986
987 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
988 setOperationAction(ISD::MULHS, VT, Expand);
989 setOperationAction(ISD::MULHU, VT, Expand);
990 }
991
992 // NEON only has FMA instructions as of VFP4.
993 if (!Subtarget->hasVFP4Base()) {
994 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
995 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
996 }
997
998 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
999 ISD::FP_TO_UINT, ISD::FDIV, ISD::LOAD});
1000
1001 // It is legal to extload from v4i8 to v4i16 or v4i32.
1002 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
1003 MVT::v2i32}) {
1004 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1005 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
1006 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
1007 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
1008 }
1009 }
1010
1011 for (auto VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v16i8, MVT::v8i16,
1012 MVT::v4i32}) {
1013 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
1014 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
1015 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1016 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1017 }
1018 }
1019
1020 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1021 setTargetDAGCombine(
1022 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR,
1023 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
1024 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND,
1025 ISD::ANY_EXTEND, ISD::INTRINSIC_WO_CHAIN, ISD::INTRINSIC_W_CHAIN,
1026 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST});
1027 }
1028 if (Subtarget->hasMVEIntegerOps()) {
1029 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX,
1030 ISD::FP_EXTEND, ISD::SELECT, ISD::SELECT_CC,
1031 ISD::SETCC});
1032 }
1033 if (Subtarget->hasMVEFloatOps()) {
1034 setTargetDAGCombine(ISD::FADD);
1035 }
1036
1037 if (!Subtarget->hasFP64()) {
1038 // When targeting a floating-point unit with only single-precision
1039 // operations, f64 is legal for the few double-precision instructions which
1040 // are present However, no double-precision operations other than moves,
1041 // loads and stores are provided by the hardware.
1042 setOperationAction(ISD::FADD, MVT::f64, Expand);
1043 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1044 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1045 setOperationAction(ISD::FMA, MVT::f64, Expand);
1046 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1047 setOperationAction(ISD::FREM, MVT::f64, Expand);
1048 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1049 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1050 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1051 setOperationAction(ISD::FABS, MVT::f64, Expand);
1052 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1053 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1054 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1055 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1056 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1057 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1058 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1059 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1060 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1061 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1062 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1063 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1064 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1065 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1066 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1068 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1069 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1070 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1071 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1073 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1074 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1075 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1076 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1077 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1078 }
1079
1080 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1081 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1082 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1083 if (Subtarget->hasFullFP16()) {
1084 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1085 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1086 }
1087 }
1088
1089 if (!Subtarget->hasFP16()) {
1090 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1091 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1092 }
1093
1094 computeRegisterProperties(Subtarget->getRegisterInfo());
1095
1096 // ARM does not have floating-point extending loads.
1097 for (MVT VT : MVT::fp_valuetypes()) {
1098 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1099 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1100 }
1101
1102 // ... or truncating stores
1103 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1104 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1105 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1106
1107 // ARM does not have i1 sign extending load.
1108 for (MVT VT : MVT::integer_valuetypes())
1109 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1110
1111 // ARM supports all 4 flavors of integer indexed load / store.
1112 if (!Subtarget->isThumb1Only()) {
1113 for (unsigned im = (unsigned)ISD::PRE_INC;
1114 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1115 setIndexedLoadAction(im, MVT::i1, Legal);
1116 setIndexedLoadAction(im, MVT::i8, Legal);
1117 setIndexedLoadAction(im, MVT::i16, Legal);
1118 setIndexedLoadAction(im, MVT::i32, Legal);
1119 setIndexedStoreAction(im, MVT::i1, Legal);
1120 setIndexedStoreAction(im, MVT::i8, Legal);
1121 setIndexedStoreAction(im, MVT::i16, Legal);
1122 setIndexedStoreAction(im, MVT::i32, Legal);
1123 }
1124 } else {
1125 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1126 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1127 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1128 }
1129
1130 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1131 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1132 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1133 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1134
1135 setOperationAction(ISD::UADDO_CARRY, MVT::i32, Custom);
1136 setOperationAction(ISD::USUBO_CARRY, MVT::i32, Custom);
1137 if (Subtarget->hasDSP()) {
1138 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1139 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1140 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1141 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1142 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1143 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1144 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1145 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1146 }
1147 if (Subtarget->hasBaseDSP()) {
1148 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1149 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1150 }
1151
1152 // i64 operation support.
1153 setOperationAction(ISD::MUL, MVT::i64, Expand);
1154 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1155 if (Subtarget->isThumb1Only()) {
1156 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1157 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1158 }
1159 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1160 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1161 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1162
1163 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1164 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1165 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1166 setOperationAction(ISD::SRL, MVT::i64, Custom);
1167 setOperationAction(ISD::SRA, MVT::i64, Custom);
1168 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1169 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1170 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1171 setOperationAction(ISD::STORE, MVT::i64, Custom);
1172
1173 // MVE lowers 64 bit shifts to lsll and lsrl
1174 // assuming that ISD::SRL and SRA of i64 are already marked custom
1175 if (Subtarget->hasMVEIntegerOps())
1176 setOperationAction(ISD::SHL, MVT::i64, Custom);
1177
1178 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1179 if (Subtarget->isThumb1Only()) {
1180 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1181 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1182 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1183 }
1184
1185 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1186 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1187
1188 // ARM does not have ROTL.
1189 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1190 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1191 setOperationAction(ISD::ROTL, VT, Expand);
1192 setOperationAction(ISD::ROTR, VT, Expand);
1193 }
1194 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1195 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1196 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1197 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1198 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1199 }
1200
1201 // @llvm.readcyclecounter requires the Performance Monitors extension.
1202 // Default to the 0 expansion on unsupported platforms.
1203 // FIXME: Technically there are older ARM CPUs that have
1204 // implementation-specific ways of obtaining this information.
1205 if (Subtarget->hasPerfMon())
1206 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1207
1208 // Only ARMv6 has BSWAP.
1209 if (!Subtarget->hasV6Ops())
1210 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1211
1212 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1213 : Subtarget->hasDivideInARMMode();
1214 if (!hasDivide) {
1215 // These are expanded into libcalls if the cpu doesn't have HW divider.
1216 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1217 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1218 }
1219
1220 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1221 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1222 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1223
1224 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1225 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1226 }
1227
1228 setOperationAction(ISD::SREM, MVT::i32, Expand);
1229 setOperationAction(ISD::UREM, MVT::i32, Expand);
1230
1231 // Register based DivRem for AEABI (RTABI 4.2)
1232 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1233 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1234 Subtarget->isTargetWindows()) {
1235 setOperationAction(ISD::SREM, MVT::i64, Custom);
1236 setOperationAction(ISD::UREM, MVT::i64, Custom);
1237 HasStandaloneRem = false;
1238
1239 if (Subtarget->isTargetWindows()) {
1240 const struct {
1241 const RTLIB::Libcall Op;
1242 const char * const Name;
1243 const CallingConv::ID CC;
1244 } LibraryCalls[] = {
1245 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1246 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1247 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1248 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1249
1250 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1251 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1252 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1253 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1254 };
1255
1256 for (const auto &LC : LibraryCalls) {
1257 setLibcallName(LC.Op, LC.Name);
1258 setLibcallCallingConv(LC.Op, LC.CC);
1259 }
1260 } else {
1261 const struct {
1262 const RTLIB::Libcall Op;
1263 const char * const Name;
1264 const CallingConv::ID CC;
1265 } LibraryCalls[] = {
1266 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1267 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1268 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1269 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1270
1271 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1272 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1273 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1274 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1275 };
1276
1277 for (const auto &LC : LibraryCalls) {
1278 setLibcallName(LC.Op, LC.Name);
1279 setLibcallCallingConv(LC.Op, LC.CC);
1280 }
1281 }
1282
1283 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1284 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1285 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1286 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1287 } else {
1288 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1289 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1290 }
1291
1292 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1293 // MSVCRT doesn't have powi; fall back to pow
1294 setLibcallName(RTLIB::POWI_F32, nullptr);
1295 setLibcallName(RTLIB::POWI_F64, nullptr);
1296 }
1297
1298 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1299 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1300 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1301 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1302
1303 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1304 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1305
1306 // Use the default implementation.
1307 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1308 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1309 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1310 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1311 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1312 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1313
1314 if (Subtarget->isTargetWindows())
1315 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1316 else
1317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1318
1319 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1320 // the default expansion.
1321 InsertFencesForAtomic = false;
1322 if (Subtarget->hasAnyDataBarrier() &&
1323 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1324 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1325 // to ldrex/strex loops already.
1326 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1327 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1328 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1329
1330 // On v8, we have particularly efficient implementations of atomic fences
1331 // if they can be combined with nearby atomic loads and stores.
1332 if (!Subtarget->hasAcquireRelease() ||
1333 getTargetMachine().getOptLevel() == 0) {
1334 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1335 InsertFencesForAtomic = true;
1336 }
1337 } else {
1338 // If there's anything we can use as a barrier, go through custom lowering
1339 // for ATOMIC_FENCE.
1340 // If target has DMB in thumb, Fences can be inserted.
1341 if (Subtarget->hasDataBarrier())
1342 InsertFencesForAtomic = true;
1343
1344 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1345 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1346
1347 // Set them all for expansion, which will force libcalls.
1348 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1349 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1350 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1351 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1352 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1353 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1354 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1355 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1356 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1357 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1358 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1359 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1360 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1361 // Unordered/Monotonic case.
1362 if (!InsertFencesForAtomic) {
1363 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1364 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1365 }
1366 }
1367
1368 // Compute supported atomic widths.
1369 if (Subtarget->isTargetLinux() ||
1370 (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
1371 // For targets where __sync_* routines are reliably available, we use them
1372 // if necessary.
1373 //
1374 // ARM Linux always supports 64-bit atomics through kernel-assisted atomic
1375 // routines (kernel 3.1 or later). FIXME: Not with compiler-rt?
1376 //
1377 // ARMv6 targets have native instructions in ARM mode. For Thumb mode,
1378 // such targets should provide __sync_* routines, which use the ARM mode
1379 // instructions. (ARMv6 doesn't have dmb, but it has an equivalent
1380 // encoding; see ARMISD::MEMBARRIER_MCR.)
1381 setMaxAtomicSizeInBitsSupported(64);
1382 } else if ((Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) ||
1383 Subtarget->hasForced32BitAtomics()) {
1384 // Cortex-M (besides Cortex-M0) have 32-bit atomics.
1385 setMaxAtomicSizeInBitsSupported(32);
1386 } else {
1387 // We can't assume anything about other targets; just use libatomic
1388 // routines.
1389 setMaxAtomicSizeInBitsSupported(0);
1390 }
1391
1392 setMaxDivRemBitWidthSupported(64);
1393
1394 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1395
1396 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1397 if (!Subtarget->hasV6Ops()) {
1398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1399 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1400 }
1401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1402
1403 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1404 !Subtarget->isThumb1Only()) {
1405 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1406 // iff target supports vfp2.
1407 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1408 setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
1409 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1410 }
1411
1412 // We want to custom lower some of our intrinsics.
1413 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1414 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1415 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1416 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1417 if (Subtarget->useSjLjEH())
1418 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1419
1420 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1421 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1422 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1423 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1424 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1425 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1426 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1427 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1428 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1429 if (Subtarget->hasFullFP16()) {
1430 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1431 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1432 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1433 }
1434
1435 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1436
1437 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1438 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1439 if (Subtarget->hasFullFP16())
1440 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1441 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1442 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1443 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1444
1445 // We don't support sin/cos/fmod/copysign/pow
1446 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1447 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1448 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1449 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1450 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1451 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1452 setOperationAction(ISD::FREM, MVT::f64, Expand);
1453 setOperationAction(ISD::FREM, MVT::f32, Expand);
1454 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1455 !Subtarget->isThumb1Only()) {
1456 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1457 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1458 }
1459 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1460 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1461
1462 if (!Subtarget->hasVFP4Base()) {
1463 setOperationAction(ISD::FMA, MVT::f64, Expand);
1464 setOperationAction(ISD::FMA, MVT::f32, Expand);
1465 }
1466
1467 // Various VFP goodness
1468 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1469 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1470 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1471 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1472 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1473 }
1474
1475 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1476 if (!Subtarget->hasFP16()) {
1477 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1478 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1479 }
1480
1481 // Strict floating-point comparisons need custom lowering.
1482 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1483 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1484 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1485 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1486 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1487 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1488 }
1489
1490 // Use __sincos_stret if available.
1491 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1492 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1493 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1494 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1495 }
1496
1497 // FP-ARMv8 implements a lot of rounding-like FP operations.
1498 if (Subtarget->hasFPARMv8Base()) {
1499 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1500 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1501 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1502 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1503 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1504 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1505 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1506 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1507 if (Subtarget->hasNEON()) {
1508 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1509 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1510 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1511 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1512 }
1513
1514 if (Subtarget->hasFP64()) {
1515 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1516 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1517 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1518 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1519 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1520 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1521 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1522 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1523 }
1524 }
1525
1526 // FP16 often need to be promoted to call lib functions
1527 if (Subtarget->hasFullFP16()) {
1528 setOperationAction(ISD::FREM, MVT::f16, Promote);
1529 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1530 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1531 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1532 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1533 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1534 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1535 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1536 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1537 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1538 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1539 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1540
1541 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1542 }
1543
1544 if (Subtarget->hasNEON()) {
1545 // vmin and vmax aren't available in a scalar form, so we can use
1546 // a NEON instruction with an undef lane instead. This has a performance
1547 // penalty on some cores, so we don't do this unless we have been
1548 // asked to by the core tuning model.
1549 if (Subtarget->useNEONForSinglePrecisionFP()) {
1550 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1551 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1552 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1553 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1554 }
1555 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1556 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1557 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1558 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1559
1560 if (Subtarget->hasFullFP16()) {
1561 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1562 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1563 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1564 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1565
1566 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1567 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1568 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1569 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1570 }
1571 }
1572
1573 // We have target-specific dag combine patterns for the following nodes:
1574 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1575 setTargetDAGCombine(
1576 {ISD::ADD, ISD::SUB, ISD::MUL, ISD::AND, ISD::OR, ISD::XOR});
1577
1578 if (Subtarget->hasMVEIntegerOps())
1579 setTargetDAGCombine(ISD::VSELECT);
1580
1581 if (Subtarget->hasV6Ops())
1582 setTargetDAGCombine(ISD::SRL);
1583 if (Subtarget->isThumb1Only())
1584 setTargetDAGCombine(ISD::SHL);
1585 // Attempt to lower smin/smax to ssat/usat
1586 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
1587 Subtarget->isThumb2()) {
1588 setTargetDAGCombine({ISD::SMIN, ISD::SMAX});
1589 }
1590
1591 setStackPointerRegisterToSaveRestore(ARM::SP);
1592
1593 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1594 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1595 setSchedulingPreference(Sched::RegPressure);
1596 else
1597 setSchedulingPreference(Sched::Hybrid);
1598
1599 //// temporary - rewrite interface to use type
1600 MaxStoresPerMemset = 8;
1601 MaxStoresPerMemsetOptSize = 4;
1602 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1603 MaxStoresPerMemcpyOptSize = 2;
1604 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1605 MaxStoresPerMemmoveOptSize = 2;
1606
1607 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1608 // are at least 4 bytes aligned.
1609 setMinStackArgumentAlignment(Align(4));
1610
1611 // Prefer likely predicted branches to selects on out-of-order cores.
1612 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1613
1614 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1615
1616 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1617
1618 if (Subtarget->isThumb() || Subtarget->isThumb2())
1619 setTargetDAGCombine(ISD::ABS);
1620}
1621
1622bool ARMTargetLowering::useSoftFloat() const {
1623 return Subtarget->useSoftFloat();
1624}
1625
1626// FIXME: It might make sense to define the representative register class as the
1627// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1628// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1629// SPR's representative would be DPR_VFP2. This should work well if register
1630// pressure tracking were modified such that a register use would increment the
1631// pressure of the register class's representative and all of it's super
1632// classes' representatives transitively. We have not implemented this because
1633// of the difficulty prior to coalescing of modeling operand register classes
1634// due to the common occurrence of cross class copies and subregister insertions
1635// and extractions.
1636std::pair<const TargetRegisterClass *, uint8_t>
1637ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1638 MVT VT) const {
1639 const TargetRegisterClass *RRC = nullptr;
1640 uint8_t Cost = 1;
1641 switch (VT.SimpleTy) {
1642 default:
1643 return TargetLowering::findRepresentativeClass(TRI, VT);
1644 // Use DPR as representative register class for all floating point
1645 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1646 // the cost is 1 for both f32 and f64.
1647 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1648 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1649 RRC = &ARM::DPRRegClass;
1650 // When NEON is used for SP, only half of the register file is available
1651 // because operations that define both SP and DP results will be constrained
1652 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1653 // coalescing by double-counting the SP regs. See the FIXME above.
1654 if (Subtarget->useNEONForSinglePrecisionFP())
1655 Cost = 2;
1656 break;
1657 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1658 case MVT::v4f32: case MVT::v2f64:
1659 RRC = &ARM::DPRRegClass;
1660 Cost = 2;
1661 break;
1662 case MVT::v4i64:
1663 RRC = &ARM::DPRRegClass;
1664 Cost = 4;
1665 break;
1666 case MVT::v8i64:
1667 RRC = &ARM::DPRRegClass;
1668 Cost = 8;
1669 break;
1670 }
1671 return std::make_pair(RRC, Cost);
1672}
1673
1674const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1675#define MAKE_CASE(V) \
1676 case V: \
1677 return #V;
1678 switch ((ARMISD::NodeType)Opcode) {
1679 case ARMISD::FIRST_NUMBER:
1680 break;
1681 MAKE_CASE(ARMISD::Wrapper)
1682 MAKE_CASE(ARMISD::WrapperPIC)
1683 MAKE_CASE(ARMISD::WrapperJT)
1684 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1685 MAKE_CASE(ARMISD::CALL)
1686 MAKE_CASE(ARMISD::CALL_PRED)
1687 MAKE_CASE(ARMISD::CALL_NOLINK)
1688 MAKE_CASE(ARMISD::tSECALL)
1689 MAKE_CASE(ARMISD::t2CALL_BTI)
1690 MAKE_CASE(ARMISD::BRCOND)
1691 MAKE_CASE(ARMISD::BR_JT)
1692 MAKE_CASE(ARMISD::BR2_JT)
1693 MAKE_CASE(ARMISD::RET_GLUE)
1694 MAKE_CASE(ARMISD::SERET_GLUE)
1695 MAKE_CASE(ARMISD::INTRET_GLUE)
1696 MAKE_CASE(ARMISD::PIC_ADD)
1697 MAKE_CASE(ARMISD::CMP)
1698 MAKE_CASE(ARMISD::CMN)
1699 MAKE_CASE(ARMISD::CMPZ)
1700 MAKE_CASE(ARMISD::CMPFP)
1701 MAKE_CASE(ARMISD::CMPFPE)
1702 MAKE_CASE(ARMISD::CMPFPw0)
1703 MAKE_CASE(ARMISD::CMPFPEw0)
1704 MAKE_CASE(ARMISD::BCC_i64)
1705 MAKE_CASE(ARMISD::FMSTAT)
1706 MAKE_CASE(ARMISD::CMOV)
1707 MAKE_CASE(ARMISD::SUBS)
1708 MAKE_CASE(ARMISD::SSAT)
1709 MAKE_CASE(ARMISD::USAT)
1710 MAKE_CASE(ARMISD::ASRL)
1711 MAKE_CASE(ARMISD::LSRL)
1712 MAKE_CASE(ARMISD::LSLL)
1713 MAKE_CASE(ARMISD::SRL_GLUE)
1714 MAKE_CASE(ARMISD::SRA_GLUE)
1715 MAKE_CASE(ARMISD::RRX)
1716 MAKE_CASE(ARMISD::ADDC)
1717 MAKE_CASE(ARMISD::ADDE)
1718 MAKE_CASE(ARMISD::SUBC)
1719 MAKE_CASE(ARMISD::SUBE)
1720 MAKE_CASE(ARMISD::LSLS)
1721 MAKE_CASE(ARMISD::VMOVRRD)
1722 MAKE_CASE(ARMISD::VMOVDRR)
1723 MAKE_CASE(ARMISD::VMOVhr)
1724 MAKE_CASE(ARMISD::VMOVrh)
1725 MAKE_CASE(ARMISD::VMOVSR)
1726 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1727 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1728 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1729 MAKE_CASE(ARMISD::TC_RETURN)
1730 MAKE_CASE(ARMISD::THREAD_POINTER)
1731 MAKE_CASE(ARMISD::DYN_ALLOC)
1732 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1733 MAKE_CASE(ARMISD::PRELOAD)
1734 MAKE_CASE(ARMISD::LDRD)
1735 MAKE_CASE(ARMISD::STRD)
1736 MAKE_CASE(ARMISD::WIN__CHKSTK)
1737 MAKE_CASE(ARMISD::WIN__DBZCHK)
1738 MAKE_CASE(ARMISD::PREDICATE_CAST)
1739 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1740 MAKE_CASE(ARMISD::MVESEXT)
1741 MAKE_CASE(ARMISD::MVEZEXT)
1742 MAKE_CASE(ARMISD::MVETRUNC)
1743 MAKE_CASE(ARMISD::VCMP)
1744 MAKE_CASE(ARMISD::VCMPZ)
1745 MAKE_CASE(ARMISD::VTST)
1746 MAKE_CASE(ARMISD::VSHLs)
1747 MAKE_CASE(ARMISD::VSHLu)
1748 MAKE_CASE(ARMISD::VSHLIMM)
1749 MAKE_CASE(ARMISD::VSHRsIMM)
1750 MAKE_CASE(ARMISD::VSHRuIMM)
1751 MAKE_CASE(ARMISD::VRSHRsIMM)
1752 MAKE_CASE(ARMISD::VRSHRuIMM)
1753 MAKE_CASE(ARMISD::VRSHRNIMM)
1754 MAKE_CASE(ARMISD::VQSHLsIMM)
1755 MAKE_CASE(ARMISD::VQSHLuIMM)
1756 MAKE_CASE(ARMISD::VQSHLsuIMM)
1757 MAKE_CASE(ARMISD::VQSHRNsIMM)
1758 MAKE_CASE(ARMISD::VQSHRNuIMM)
1759 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1760 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1761 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1762 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1763 MAKE_CASE(ARMISD::VSLIIMM)
1764 MAKE_CASE(ARMISD::VSRIIMM)
1765 MAKE_CASE(ARMISD::VGETLANEu)
1766 MAKE_CASE(ARMISD::VGETLANEs)
1767 MAKE_CASE(ARMISD::VMOVIMM)
1768 MAKE_CASE(ARMISD::VMVNIMM)
1769 MAKE_CASE(ARMISD::VMOVFPIMM)
1770 MAKE_CASE(ARMISD::VDUP)
1771 MAKE_CASE(ARMISD::VDUPLANE)
1772 MAKE_CASE(ARMISD::VEXT)
1773 MAKE_CASE(ARMISD::VREV64)
1774 MAKE_CASE(ARMISD::VREV32)
1775 MAKE_CASE(ARMISD::VREV16)
1776 MAKE_CASE(ARMISD::VZIP)
1777 MAKE_CASE(ARMISD::VUZP)
1778 MAKE_CASE(ARMISD::VTRN)
1779 MAKE_CASE(ARMISD::VTBL1)
1780 MAKE_CASE(ARMISD::VTBL2)
1781 MAKE_CASE(ARMISD::VMOVN)
1782 MAKE_CASE(ARMISD::VQMOVNs)
1783 MAKE_CASE(ARMISD::VQMOVNu)
1784 MAKE_CASE(ARMISD::VCVTN)
1785 MAKE_CASE(ARMISD::VCVTL)
1786 MAKE_CASE(ARMISD::VIDUP)
1787 MAKE_CASE(ARMISD::VMULLs)
1788 MAKE_CASE(ARMISD::VMULLu)
1789 MAKE_CASE(ARMISD::VQDMULH)
1790 MAKE_CASE(ARMISD::VADDVs)
1791 MAKE_CASE(ARMISD::VADDVu)
1792 MAKE_CASE(ARMISD::VADDVps)
1793 MAKE_CASE(ARMISD::VADDVpu)
1794 MAKE_CASE(ARMISD::VADDLVs)
1795 MAKE_CASE(ARMISD::VADDLVu)
1796 MAKE_CASE(ARMISD::VADDLVAs)
1797 MAKE_CASE(ARMISD::VADDLVAu)
1798 MAKE_CASE(ARMISD::VADDLVps)
1799 MAKE_CASE(ARMISD::VADDLVpu)
1800 MAKE_CASE(ARMISD::VADDLVAps)
1801 MAKE_CASE(ARMISD::VADDLVApu)
1802 MAKE_CASE(ARMISD::VMLAVs)
1803 MAKE_CASE(ARMISD::VMLAVu)
1804 MAKE_CASE(ARMISD::VMLAVps)
1805 MAKE_CASE(ARMISD::VMLAVpu)
1806 MAKE_CASE(ARMISD::VMLALVs)
1807 MAKE_CASE(ARMISD::VMLALVu)
1808 MAKE_CASE(ARMISD::VMLALVps)
1809 MAKE_CASE(ARMISD::VMLALVpu)
1810 MAKE_CASE(ARMISD::VMLALVAs)
1811 MAKE_CASE(ARMISD::VMLALVAu)
1812 MAKE_CASE(ARMISD::VMLALVAps)
1813 MAKE_CASE(ARMISD::VMLALVApu)
1814 MAKE_CASE(ARMISD::VMINVu)
1815 MAKE_CASE(ARMISD::VMINVs)
1816 MAKE_CASE(ARMISD::VMAXVu)
1817 MAKE_CASE(ARMISD::VMAXVs)
1818 MAKE_CASE(ARMISD::UMAAL)
1819 MAKE_CASE(ARMISD::UMLAL)
1820 MAKE_CASE(ARMISD::SMLAL)
1821 MAKE_CASE(ARMISD::SMLALBB)
1822 MAKE_CASE(ARMISD::SMLALBT)
1823 MAKE_CASE(ARMISD::SMLALTB)
1824 MAKE_CASE(ARMISD::SMLALTT)
1825 MAKE_CASE(ARMISD::SMULWB)
1826 MAKE_CASE(ARMISD::SMULWT)
1827 MAKE_CASE(ARMISD::SMLALD)
1828 MAKE_CASE(ARMISD::SMLALDX)
1829 MAKE_CASE(ARMISD::SMLSLD)
1830 MAKE_CASE(ARMISD::SMLSLDX)
1831 MAKE_CASE(ARMISD::SMMLAR)
1832 MAKE_CASE(ARMISD::SMMLSR)
1833 MAKE_CASE(ARMISD::QADD16b)
1834 MAKE_CASE(ARMISD::QSUB16b)
1835 MAKE_CASE(ARMISD::QADD8b)
1836 MAKE_CASE(ARMISD::QSUB8b)
1837 MAKE_CASE(ARMISD::UQADD16b)
1838 MAKE_CASE(ARMISD::UQSUB16b)
1839 MAKE_CASE(ARMISD::UQADD8b)
1840 MAKE_CASE(ARMISD::UQSUB8b)
1841 MAKE_CASE(ARMISD::BUILD_VECTOR)
1842 MAKE_CASE(ARMISD::BFI)
1843 MAKE_CASE(ARMISD::VORRIMM)
1844 MAKE_CASE(ARMISD::VBICIMM)
1845 MAKE_CASE(ARMISD::VBSP)
1846 MAKE_CASE(ARMISD::MEMCPY)
1847 MAKE_CASE(ARMISD::VLD1DUP)
1848 MAKE_CASE(ARMISD::VLD2DUP)
1849 MAKE_CASE(ARMISD::VLD3DUP)
1850 MAKE_CASE(ARMISD::VLD4DUP)
1851 MAKE_CASE(ARMISD::VLD1_UPD)
1852 MAKE_CASE(ARMISD::VLD2_UPD)
1853 MAKE_CASE(ARMISD::VLD3_UPD)
1854 MAKE_CASE(ARMISD::VLD4_UPD)
1855 MAKE_CASE(ARMISD::VLD1x2_UPD)
1856 MAKE_CASE(ARMISD::VLD1x3_UPD)
1857 MAKE_CASE(ARMISD::VLD1x4_UPD)
1858 MAKE_CASE(ARMISD::VLD2LN_UPD)
1859 MAKE_CASE(ARMISD::VLD3LN_UPD)
1860 MAKE_CASE(ARMISD::VLD4LN_UPD)
1861 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1862 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1863 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1864 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1865 MAKE_CASE(ARMISD::VST1_UPD)
1866 MAKE_CASE(ARMISD::VST2_UPD)
1867 MAKE_CASE(ARMISD::VST3_UPD)
1868 MAKE_CASE(ARMISD::VST4_UPD)
1869 MAKE_CASE(ARMISD::VST1x2_UPD)
1870 MAKE_CASE(ARMISD::VST1x3_UPD)
1871 MAKE_CASE(ARMISD::VST1x4_UPD)
1872 MAKE_CASE(ARMISD::VST2LN_UPD)
1873 MAKE_CASE(ARMISD::VST3LN_UPD)
1874 MAKE_CASE(ARMISD::VST4LN_UPD)
1875 MAKE_CASE(ARMISD::WLS)
1876 MAKE_CASE(ARMISD::WLSSETUP)
1877 MAKE_CASE(ARMISD::LE)
1878 MAKE_CASE(ARMISD::LOOP_DEC)
1879 MAKE_CASE(ARMISD::CSINV)
1880 MAKE_CASE(ARMISD::CSNEG)
1881 MAKE_CASE(ARMISD::CSINC)
1882 MAKE_CASE(ARMISD::MEMCPYLOOP)
1883 MAKE_CASE(ARMISD::MEMSETLOOP)
1884#undef MAKE_CASE
1885 }
1886 return nullptr;
1887}
1888
1889EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1890 EVT VT) const {
1891 if (!VT.isVector())
1892 return getPointerTy(DL);
1893
1894 // MVE has a predicate register.
1895 if ((Subtarget->hasMVEIntegerOps() &&
1896 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
1897 VT == MVT::v16i8)) ||
1898 (Subtarget->hasMVEFloatOps() &&
1899 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
1900 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1901 return VT.changeVectorElementTypeToInteger();
1902}
1903
1904/// getRegClassFor - Return the register class that should be used for the
1905/// specified value type.
1906const TargetRegisterClass *
1907ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1908 (void)isDivergent;
1909 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1910 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1911 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1912 // MVE Q registers.
1913 if (Subtarget->hasNEON()) {
1914 if (VT == MVT::v4i64)
1915 return &ARM::QQPRRegClass;
1916 if (VT == MVT::v8i64)
1917 return &ARM::QQQQPRRegClass;
1918 }
1919 if (Subtarget->hasMVEIntegerOps()) {
1920 if (VT == MVT::v4i64)
1921 return &ARM::MQQPRRegClass;
1922 if (VT == MVT::v8i64)
1923 return &ARM::MQQQQPRRegClass;
1924 }
1925 return TargetLowering::getRegClassFor(VT);
1926}
1927
1928// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1929// source/dest is aligned and the copy size is large enough. We therefore want
1930// to align such objects passed to memory intrinsics.
1931bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1932 Align &PrefAlign) const {
1933 if (!isa<MemIntrinsic>(CI))
1934 return false;
1935 MinSize = 8;
1936 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1937 // cycle faster than 4-byte aligned LDM.
1938 PrefAlign =
1939 (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));
1940 return true;
1941}
1942
1943// Create a fast isel object.
1944FastISel *
1945ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1946 const TargetLibraryInfo *libInfo) const {
1947 return ARM::createFastISel(funcInfo, libInfo);
1948}
1949
1950Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1951 unsigned NumVals = N->getNumValues();
1952 if (!NumVals)
1953 return Sched::RegPressure;
1954
1955 for (unsigned i = 0; i != NumVals; ++i) {
1956 EVT VT = N->getValueType(i);
1957 if (VT == MVT::Glue || VT == MVT::Other)
1958 continue;
1959 if (VT.isFloatingPoint() || VT.isVector())
1960 return Sched::ILP;
1961 }
1962
1963 if (!N->isMachineOpcode())
1964 return Sched::RegPressure;
1965
1966 // Load are scheduled for latency even if there instruction itinerary
1967 // is not available.
1968 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1969 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1970
1971 if (MCID.getNumDefs() == 0)
1972 return Sched::RegPressure;
1973 if (!Itins->isEmpty() &&
1974 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1975 return Sched::ILP;
1976
1977 return Sched::RegPressure;
1978}
1979
1980//===----------------------------------------------------------------------===//
1981// Lowering Code
1982//===----------------------------------------------------------------------===//
1983
1984static bool isSRL16(const SDValue &Op) {
1985 if (Op.getOpcode() != ISD::SRL)
1986 return false;
1987 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1988 return Const->getZExtValue() == 16;
1989 return false;
1990}
1991
1992static bool isSRA16(const SDValue &Op) {
1993 if (Op.getOpcode() != ISD::SRA)
1994 return false;
1995 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1996 return Const->getZExtValue() == 16;
1997 return false;
1998}
1999
2000static bool isSHL16(const SDValue &Op) {
2001 if (Op.getOpcode() != ISD::SHL)
2002 return false;
2003 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
2004 return Const->getZExtValue() == 16;
2005 return false;
2006}
2007
2008// Check for a signed 16-bit value. We special case SRA because it makes it
2009// more simple when also looking for SRAs that aren't sign extending a
2010// smaller value. Without the check, we'd need to take extra care with
2011// checking order for some operations.
2012static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
2013 if (isSRA16(Op))
2014 return isSHL16(Op.getOperand(0));
2015 return DAG.ComputeNumSignBits(Op) == 17;
2016}
2017
2018/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
2019static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2020 switch (CC) {
2021 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2021)
;
2022 case ISD::SETNE: return ARMCC::NE;
2023 case ISD::SETEQ: return ARMCC::EQ;
2024 case ISD::SETGT: return ARMCC::GT;
2025 case ISD::SETGE: return ARMCC::GE;
2026 case ISD::SETLT: return ARMCC::LT;
2027 case ISD::SETLE: return ARMCC::LE;
2028 case ISD::SETUGT: return ARMCC::HI;
2029 case ISD::SETUGE: return ARMCC::HS;
2030 case ISD::SETULT: return ARMCC::LO;
2031 case ISD::SETULE: return ARMCC::LS;
2032 }
2033}
2034
2035/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
2036static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2037 ARMCC::CondCodes &CondCode2) {
2038 CondCode2 = ARMCC::AL;
2039 switch (CC) {
2040 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2040)
;
2041 case ISD::SETEQ:
2042 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2043 case ISD::SETGT:
2044 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2045 case ISD::SETGE:
2046 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2047 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2048 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2049 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2050 case ISD::SETO: CondCode = ARMCC::VC; break;
2051 case ISD::SETUO: CondCode = ARMCC::VS; break;
2052 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2053 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2054 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2055 case ISD::SETLT:
2056 case ISD::SETULT: CondCode = ARMCC::LT; break;
2057 case ISD::SETLE:
2058 case ISD::SETULE: CondCode = ARMCC::LE; break;
2059 case ISD::SETNE:
2060 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2061 }
2062}
2063
2064//===----------------------------------------------------------------------===//
2065// Calling Convention Implementation
2066//===----------------------------------------------------------------------===//
2067
2068/// getEffectiveCallingConv - Get the effective calling convention, taking into
2069/// account presence of floating point hardware and calling convention
2070/// limitations, such as support for variadic functions.
2071CallingConv::ID
2072ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2073 bool isVarArg) const {
2074 switch (CC) {
2075 default:
2076 report_fatal_error("Unsupported calling convention");
2077 case CallingConv::ARM_AAPCS:
2078 case CallingConv::ARM_APCS:
2079 case CallingConv::GHC:
2080 case CallingConv::CFGuard_Check:
2081 return CC;
2082 case CallingConv::PreserveMost:
2083 return CallingConv::PreserveMost;
2084 case CallingConv::PreserveAll:
2085 return CallingConv::PreserveAll;
2086 case CallingConv::ARM_AAPCS_VFP:
2087 case CallingConv::Swift:
2088 case CallingConv::SwiftTail:
2089 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2090 case CallingConv::C:
2091 case CallingConv::Tail:
2092 if (!Subtarget->isAAPCS_ABI())
2093 return CallingConv::ARM_APCS;
2094 else if (Subtarget->hasFPRegs() && !Subtarget->isThumb1Only() &&
2095 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2096 !isVarArg)
2097 return CallingConv::ARM_AAPCS_VFP;
2098 else
2099 return CallingConv::ARM_AAPCS;
2100 case CallingConv::Fast:
2101 case CallingConv::CXX_FAST_TLS:
2102 if (!Subtarget->isAAPCS_ABI()) {
2103 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2104 return CallingConv::Fast;
2105 return CallingConv::ARM_APCS;
2106 } else if (Subtarget->hasVFP2Base() &&
2107 !Subtarget->isThumb1Only() && !isVarArg)
2108 return CallingConv::ARM_AAPCS_VFP;
2109 else
2110 return CallingConv::ARM_AAPCS;
2111 }
2112}
2113
2114CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2115 bool isVarArg) const {
2116 return CCAssignFnForNode(CC, false, isVarArg);
2117}
2118
2119CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2120 bool isVarArg) const {
2121 return CCAssignFnForNode(CC, true, isVarArg);
2122}
2123
2124/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2125/// CallingConvention.
2126CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2127 bool Return,
2128 bool isVarArg) const {
2129 switch (getEffectiveCallingConv(CC, isVarArg)) {
2130 default:
2131 report_fatal_error("Unsupported calling convention");
2132 case CallingConv::ARM_APCS:
2133 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2134 case CallingConv::ARM_AAPCS:
2135 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2136 case CallingConv::ARM_AAPCS_VFP:
2137 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2138 case CallingConv::Fast:
2139 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2140 case CallingConv::GHC:
2141 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2142 case CallingConv::PreserveMost:
2143 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2144 case CallingConv::PreserveAll:
2145 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2146 case CallingConv::CFGuard_Check:
2147 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2148 }
2149}
2150
2151SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2152 MVT LocVT, MVT ValVT, SDValue Val) const {
2153 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2154 Val);
2155 if (Subtarget->hasFullFP16()) {
2156 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2157 } else {
2158 Val = DAG.getNode(ISD::TRUNCATE, dl,
2159 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2160 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2161 }
2162 return Val;
2163}
2164
2165SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2166 MVT LocVT, MVT ValVT,
2167 SDValue Val) const {
2168 if (Subtarget->hasFullFP16()) {
2169 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2170 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2171 } else {
2172 Val = DAG.getNode(ISD::BITCAST, dl,
2173 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2174 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2175 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2176 }
2177 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2178}
2179
2180/// LowerCallResult - Lower the result values of a call into the
2181/// appropriate copies out of appropriate physical registers.
2182SDValue ARMTargetLowering::LowerCallResult(
2183 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
2184 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2185 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2186 SDValue ThisVal) const {
2187 // Assign locations to each value returned by this call.
2188 SmallVector<CCValAssign, 16> RVLocs;
2189 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2190 *DAG.getContext());
2191 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2192
2193 // Copy all of the result registers out of their specified physreg.
2194 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2195 CCValAssign VA = RVLocs[i];
2196
2197 // Pass 'this' value directly from the argument to return value, to avoid
2198 // reg unit interference
2199 if (i == 0 && isThisReturn) {
2200 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2201, __extension__
__PRETTY_FUNCTION__))
2201 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2201, __extension__
__PRETTY_FUNCTION__))
;
2202 InVals.push_back(ThisVal);
2203 continue;
2204 }
2205
2206 SDValue Val;
2207 if (VA.needsCustom() &&
2208 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2209 // Handle f64 or half of a v2f64.
2210 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2211 InGlue);
2212 Chain = Lo.getValue(1);
2213 InGlue = Lo.getValue(2);
2214 VA = RVLocs[++i]; // skip ahead to next loc
2215 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2216 InGlue);
2217 Chain = Hi.getValue(1);
2218 InGlue = Hi.getValue(2);
2219 if (!Subtarget->isLittle())
2220 std::swap (Lo, Hi);
2221 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2222
2223 if (VA.getLocVT() == MVT::v2f64) {
2224 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2225 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2226 DAG.getConstant(0, dl, MVT::i32));
2227
2228 VA = RVLocs[++i]; // skip ahead to next loc
2229 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InGlue);
2230 Chain = Lo.getValue(1);
2231 InGlue = Lo.getValue(2);
2232 VA = RVLocs[++i]; // skip ahead to next loc
2233 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InGlue);
2234 Chain = Hi.getValue(1);
2235 InGlue = Hi.getValue(2);
2236 if (!Subtarget->isLittle())
2237 std::swap (Lo, Hi);
2238 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2239 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2240 DAG.getConstant(1, dl, MVT::i32));
2241 }
2242 } else {
2243 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2244 InGlue);
2245 Chain = Val.getValue(1);
2246 InGlue = Val.getValue(2);
2247 }
2248
2249 switch (VA.getLocInfo()) {
2250 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2250)
;
2251 case CCValAssign::Full: break;
2252 case CCValAssign::BCvt:
2253 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2254 break;
2255 }
2256
2257 // f16 arguments have their size extended to 4 bytes and passed as if they
2258 // had been copied to the LSBs of a 32-bit register.
2259 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2260 if (VA.needsCustom() &&
2261 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2262 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2263
2264 InVals.push_back(Val);
2265 }
2266
2267 return Chain;
2268}
2269
2270std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2271 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2272 bool IsTailCall, int SPDiff) const {
2273 SDValue DstAddr;
2274 MachinePointerInfo DstInfo;
2275 int32_t Offset = VA.getLocMemOffset();
2276 MachineFunction &MF = DAG.getMachineFunction();
2277
2278 if (IsTailCall) {
2279 Offset += SPDiff;
2280 auto PtrVT = getPointerTy(DAG.getDataLayout());
2281 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2282 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2283 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2284 DstInfo =
2285 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2286 } else {
2287 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2288 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2289 StackPtr, PtrOff);
2290 DstInfo =
2291 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2292 }
2293
2294 return std::make_pair(DstAddr, DstInfo);
2295}
2296
2297void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2298 SDValue Chain, SDValue &Arg,
2299 RegsToPassVector &RegsToPass,
2300 CCValAssign &VA, CCValAssign &NextVA,
2301 SDValue &StackPtr,
2302 SmallVectorImpl<SDValue> &MemOpChains,
2303 bool IsTailCall,
2304 int SPDiff) const {
2305 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2306 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2307 unsigned id = Subtarget->isLittle() ? 0 : 1;
2308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2309
2310 if (NextVA.isRegLoc())
2311 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2312 else {
2313 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2313, __extension__ __PRETTY_FUNCTION__))
;
2314 if (!StackPtr.getNode())
2315 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2316 getPointerTy(DAG.getDataLayout()));
2317
2318 SDValue DstAddr;
2319 MachinePointerInfo DstInfo;
2320 std::tie(DstAddr, DstInfo) =
2321 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2322 MemOpChains.push_back(
2323 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2324 }
2325}
2326
2327static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2328 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2329 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2330}
2331
2332/// LowerCall - Lowering a call into a callseq_start <-
2333/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2334/// nodes.
2335SDValue
2336ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2337 SmallVectorImpl<SDValue> &InVals) const {
2338 SelectionDAG &DAG = CLI.DAG;
2339 SDLoc &dl = CLI.DL;
2340 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2341 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2342 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2343 SDValue Chain = CLI.Chain;
2344 SDValue Callee = CLI.Callee;
2345 bool &isTailCall = CLI.IsTailCall;
2346 CallingConv::ID CallConv = CLI.CallConv;
2347 bool doesNotRet = CLI.DoesNotReturn;
2348 bool isVarArg = CLI.IsVarArg;
2349
2350 MachineFunction &MF = DAG.getMachineFunction();
2351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2352 MachineFunction::CallSiteInfo CSInfo;
2353 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2354 bool isThisReturn = false;
2355 bool isCmseNSCall = false;
2356 bool isSibCall = false;
2357 bool PreferIndirect = false;
2358 bool GuardWithBTI = false;
2359
2360 // Lower 'returns_twice' calls to a pseudo-instruction.
2361 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
2362 !Subtarget->noBTIAtReturnTwice())
2363 GuardWithBTI = AFI->branchTargetEnforcement();
2364
2365 // Determine whether this is a non-secure function call.
2366 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
2367 isCmseNSCall = true;
2368
2369 // Disable tail calls if they're not supported.
2370 if (!Subtarget->supportsTailCall())
2371 isTailCall = false;
2372
2373 // For both the non-secure calls and the returns from a CMSE entry function,
2374 // the function needs to do some extra work afte r the call, or before the
2375 // return, respectively, thus it cannot end with atail call
2376 if (isCmseNSCall || AFI->isCmseNSEntryFunction())
2377 isTailCall = false;
2378
2379 if (isa<GlobalAddressSDNode>(Callee)) {
2380 // If we're optimizing for minimum size and the function is called three or
2381 // more times in this block, we can improve codesize by calling indirectly
2382 // as BLXr has a 16-bit encoding.
2383 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2384 if (CLI.CB) {
2385 auto *BB = CLI.CB->getParent();
2386 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2387 count_if(GV->users(), [&BB](const User *U) {
2388 return isa<Instruction>(U) &&
2389 cast<Instruction>(U)->getParent() == BB;
2390 }) > 2;
2391 }
2392 }
2393 if (isTailCall) {
2394 // Check if it's really possible to do a tail call.
2395 isTailCall = IsEligibleForTailCallOptimization(
2396 Callee, CallConv, isVarArg, isStructRet,
2397 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2398 PreferIndirect);
2399
2400 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2401 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2402 isSibCall = true;
2403
2404 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2405 // detected sibcalls.
2406 if (isTailCall)
2407 ++NumTailCalls;
2408 }
2409
2410 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2411 report_fatal_error("failed to perform tail call elimination on a call "
2412 "site marked musttail");
2413 // Analyze operands of the call, assigning locations to each operand.
2414 SmallVector<CCValAssign, 16> ArgLocs;
2415 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2416 *DAG.getContext());
2417 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2418
2419 // Get a count of how many bytes are to be pushed on the stack.
2420 unsigned NumBytes = CCInfo.getNextStackOffset();
2421
2422 // SPDiff is the byte offset of the call's argument area from the callee's.
2423 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2424 // by this amount for a tail call. In a sibling call it must be 0 because the
2425 // caller will deallocate the entire stack and the callee still expects its
2426 // arguments to begin at SP+0. Completely unused for non-tail calls.
2427 int SPDiff = 0;
2428
2429 if (isTailCall && !isSibCall) {
2430 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2431 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2432
2433 // Since callee will pop argument stack as a tail call, we must keep the
2434 // popped size 16-byte aligned.
2435 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2436 NumBytes = alignTo(NumBytes, StackAlign);
2437
2438 // SPDiff will be negative if this tail call requires more space than we
2439 // would automatically have in our incoming argument space. Positive if we
2440 // can actually shrink the stack.
2441 SPDiff = NumReusableBytes - NumBytes;
2442
2443 // If this call requires more stack than we have available from
2444 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2445 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2446 AFI->setArgRegsSaveSize(-SPDiff);
2447 }
2448
2449 if (isSibCall) {
2450 // For sibling tail calls, memory operands are available in our caller's stack.
2451 NumBytes = 0;
2452 } else {
2453 // Adjust the stack pointer for the new arguments...
2454 // These operations are automatically eliminated by the prolog/epilog pass
2455 Chain = DAG.getCALLSEQ_START(Chain, isTailCall ? 0 : NumBytes, 0, dl);
2456 }
2457
2458 SDValue StackPtr =
2459 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2460
2461 RegsToPassVector RegsToPass;
2462 SmallVector<SDValue, 8> MemOpChains;
2463
2464 // During a tail call, stores to the argument area must happen after all of
2465 // the function's incoming arguments have been loaded because they may alias.
2466 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2467 // there's no point in doing so repeatedly so this tracks whether that's
2468 // happened yet.
2469 bool AfterFormalArgLoads = false;
2470
2471 // Walk the register/memloc assignments, inserting copies/loads. In the case
2472 // of tail call optimization, arguments are handled later.
2473 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2474 i != e;
2475 ++i, ++realArgIdx) {
2476 CCValAssign &VA = ArgLocs[i];
2477 SDValue Arg = OutVals[realArgIdx];
2478 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2479 bool isByVal = Flags.isByVal();
2480
2481 // Promote the value if needed.
2482 switch (VA.getLocInfo()) {
2483 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2483)
;
2484 case CCValAssign::Full: break;
2485 case CCValAssign::SExt:
2486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2487 break;
2488 case CCValAssign::ZExt:
2489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2490 break;
2491 case CCValAssign::AExt:
2492 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2493 break;
2494 case CCValAssign::BCvt:
2495 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2496 break;
2497 }
2498
2499 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2500 Chain = DAG.getStackArgumentTokenFactor(Chain);
2501 AfterFormalArgLoads = true;
2502 }
2503
2504 // f16 arguments have their size extended to 4 bytes and passed as if they
2505 // had been copied to the LSBs of a 32-bit register.
2506 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2507 if (VA.needsCustom() &&
2508 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2509 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2510 } else {
2511 // f16 arguments could have been extended prior to argument lowering.
2512 // Mask them arguments if this is a CMSE nonsecure call.
2513 auto ArgVT = Outs[realArgIdx].ArgVT;
2514 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2515 auto LocBits = VA.getLocVT().getSizeInBits();
2516 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2517 SDValue Mask =
2518 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2519 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2520 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2521 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2522 }
2523 }
2524
2525 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2526 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2527 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2528 DAG.getConstant(0, dl, MVT::i32));
2529 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2530 DAG.getConstant(1, dl, MVT::i32));
2531
2532 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2533 StackPtr, MemOpChains, isTailCall, SPDiff);
2534
2535 VA = ArgLocs[++i]; // skip ahead to next loc
2536 if (VA.isRegLoc()) {
2537 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2538 StackPtr, MemOpChains, isTailCall, SPDiff);
2539 } else {
2540 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2540, __extension__ __PRETTY_FUNCTION__))
;
2541 SDValue DstAddr;
2542 MachinePointerInfo DstInfo;
2543 std::tie(DstAddr, DstInfo) =
2544 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2545 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2546 }
2547 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2548 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2549 StackPtr, MemOpChains, isTailCall, SPDiff);
2550 } else if (VA.isRegLoc()) {
2551 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2552 Outs[0].VT == MVT::i32) {
2553 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2554, __extension__
__PRETTY_FUNCTION__))
2554 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2554, __extension__
__PRETTY_FUNCTION__))
;
2555 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2556, __extension__
__PRETTY_FUNCTION__))
2556 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2556, __extension__
__PRETTY_FUNCTION__))
;
2557 isThisReturn = true;
2558 }
2559 const TargetOptions &Options = DAG.getTarget().Options;
2560 if (Options.EmitCallSiteInfo)
2561 CSInfo.emplace_back(VA.getLocReg(), i);
2562 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2563 } else if (isByVal) {
2564 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2564, __extension__ __PRETTY_FUNCTION__))
;
2565 unsigned offset = 0;
2566
2567 // True if this byval aggregate will be split between registers
2568 // and memory.
2569 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2570 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2571
2572 if (CurByValIdx < ByValArgsCount) {
2573
2574 unsigned RegBegin, RegEnd;
2575 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2576
2577 EVT PtrVT =
2578 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2579 unsigned int i, j;
2580 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2581 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2582 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2583 SDValue Load =
2584 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2585 DAG.InferPtrAlign(AddArg));
2586 MemOpChains.push_back(Load.getValue(1));
2587 RegsToPass.push_back(std::make_pair(j, Load));
2588 }
2589
2590 // If parameter size outsides register area, "offset" value
2591 // helps us to calculate stack slot for remained part properly.
2592 offset = RegEnd - RegBegin;
2593
2594 CCInfo.nextInRegsParam();
2595 }
2596
2597 if (Flags.getByValSize() > 4*offset) {
2598 auto PtrVT = getPointerTy(DAG.getDataLayout());
2599 SDValue Dst;
2600 MachinePointerInfo DstInfo;
2601 std::tie(Dst, DstInfo) =
2602 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2603 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2604 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2605 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2606 MVT::i32);
2607 SDValue AlignNode =
2608 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2609
2610 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2611 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2612 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2613 Ops));
2614 }
2615 } else {
2616 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2616, __extension__ __PRETTY_FUNCTION__))
;
2617 SDValue DstAddr;
2618 MachinePointerInfo DstInfo;
2619 std::tie(DstAddr, DstInfo) =
2620 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2621
2622 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2623 MemOpChains.push_back(Store);
2624 }
2625 }
2626
2627 if (!MemOpChains.empty())
2628 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2629
2630 // Build a sequence of copy-to-reg nodes chained together with token chain
2631 // and flag operands which copy the outgoing args into the appropriate regs.
2632 SDValue InGlue;
2633 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2634 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2635 RegsToPass[i].second, InGlue);
2636 InGlue = Chain.getValue(1);
2637 }
2638
2639 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2640 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2641 // node so that legalize doesn't hack it.
2642 bool isDirect = false;
2643
2644 const TargetMachine &TM = getTargetMachine();
2645 const Module *Mod = MF.getFunction().getParent();
2646 const GlobalValue *GVal = nullptr;
2647 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2648 GVal = G->getGlobal();
2649 bool isStub =
2650 !TM.shouldAssumeDSOLocal(*Mod, GVal) && Subtarget->isTargetMachO();
2651
2652 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2653 bool isLocalARMFunc = false;
2654 auto PtrVt = getPointerTy(DAG.getDataLayout());
2655
2656 if (Subtarget->genLongCalls()) {
2657 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2658, __extension__
__PRETTY_FUNCTION__))
2658 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2658, __extension__
__PRETTY_FUNCTION__))
;
2659 // Handle a global address or an external symbol. If it's not one of
2660 // those, the target's already in a register, so we don't need to do
2661 // anything extra.
2662 if (isa<GlobalAddressSDNode>(Callee)) {
2663 // When generating execute-only code we use movw movt pair.
2664 // Currently execute-only is only available for architectures that
2665 // support movw movt, so we are safe to assume that.
2666 if (Subtarget->genExecuteOnly()) {
2667 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2668, __extension__
__PRETTY_FUNCTION__))
2668 "long-calls with execute-only requires movt and movw!")(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2668, __extension__
__PRETTY_FUNCTION__))
;
2669 ++NumMovwMovt;
2670 Callee = DAG.getNode(ARMISD::Wrapper, dl, PtrVt,
2671 DAG.getTargetGlobalAddress(GVal, dl, PtrVt));
2672 } else {
2673 // Create a constant pool entry for the callee address
2674 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2675 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2676 GVal, ARMPCLabelIndex, ARMCP::CPValue, 0);
2677
2678 // Get the address of the callee into a register
2679 SDValue Addr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2680 Addr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Addr);
2681 Callee = DAG.getLoad(
2682 PtrVt, dl, DAG.getEntryNode(), Addr,
2683 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2684 }
2685 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2686 const char *Sym = S->getSymbol();
2687
2688 // When generating execute-only code we use movw movt pair.
2689 // Currently execute-only is only available for architectures that
2690 // support movw movt, so we are safe to assume that.
2691 if (Subtarget->genExecuteOnly()) {
2692 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2693, __extension__
__PRETTY_FUNCTION__))
2693 "long-calls with execute-only requires movt and movw!")(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2693, __extension__
__PRETTY_FUNCTION__))
;
2694 ++NumMovwMovt;
2695 Callee = DAG.getNode(ARMISD::Wrapper, dl, PtrVt,
2696 DAG.getTargetGlobalAddress(GVal, dl, PtrVt));
2697 } else {
2698 // Create a constant pool entry for the callee address
2699 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2700 ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
2701 *DAG.getContext(), Sym, ARMPCLabelIndex, 0);
2702
2703 // Get the address of the callee into a register
2704 SDValue Addr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2705 Addr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Addr);
2706 Callee = DAG.getLoad(
2707 PtrVt, dl, DAG.getEntryNode(), Addr,
2708 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2709 }
2710 }
2711 } else if (isa<GlobalAddressSDNode>(Callee)) {
2712 if (!PreferIndirect) {
2713 isDirect = true;
2714 bool isDef = GVal->isStrongDefinitionForLinker();
2715
2716 // ARM call to a local ARM function is predicable.
2717 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2718 // tBX takes a register source operand.
2719 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2720 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2720, __extension__
__PRETTY_FUNCTION__))
;
2721 Callee = DAG.getNode(
2722 ARMISD::WrapperPIC, dl, PtrVt,
2723 DAG.getTargetGlobalAddress(GVal, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2724 Callee = DAG.getLoad(
2725 PtrVt, dl, DAG.getEntryNode(), Callee,
2726 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2727 MachineMemOperand::MODereferenceable |
2728 MachineMemOperand::MOInvariant);
2729 } else if (Subtarget->isTargetCOFF()) {
2730 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2731, __extension__
__PRETTY_FUNCTION__))
2731 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2731, __extension__
__PRETTY_FUNCTION__))
;
2732 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2733 if (GVal->hasDLLImportStorageClass())
2734 TargetFlags = ARMII::MO_DLLIMPORT;
2735 else if (!TM.shouldAssumeDSOLocal(*GVal->getParent(), GVal))
2736 TargetFlags = ARMII::MO_COFFSTUB;
2737 Callee = DAG.getTargetGlobalAddress(GVal, dl, PtrVt, /*offset=*/0,
2738 TargetFlags);
2739 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2740 Callee =
2741 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2742 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2743 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2744 } else {
2745 Callee = DAG.getTargetGlobalAddress(GVal, dl, PtrVt, 0, 0);
2746 }
2747 }
2748 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2749 isDirect = true;
2750 // tBX takes a register source operand.
2751 const char *Sym = S->getSymbol();
2752 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2753 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2754 ARMConstantPoolValue *CPV =
2755 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2756 ARMPCLabelIndex, 4);
2757 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2758 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2759 Callee = DAG.getLoad(
2760 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2761 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2762 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2763 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2764 } else {
2765 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2766 }
2767 }
2768
2769 if (isCmseNSCall) {
2770 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2771, __extension__
__PRETTY_FUNCTION__))
2771 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2771, __extension__
__PRETTY_FUNCTION__))
;
2772 if (NumBytes > 0) {
2773 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2774 "call to non-secure function would "
2775 "require passing arguments on stack",
2776 dl.getDebugLoc());
2777 DAG.getContext()->diagnose(Diag);
2778 }
2779 if (isStructRet) {
2780 DiagnosticInfoUnsupported Diag(
2781 DAG.getMachineFunction().getFunction(),
2782 "call to non-secure function would return value through pointer",
2783 dl.getDebugLoc());
2784 DAG.getContext()->diagnose(Diag);
2785 }
2786 }
2787
2788 // FIXME: handle tail calls differently.
2789 unsigned CallOpc;
2790 if (Subtarget->isThumb()) {
2791 if (GuardWithBTI)
2792 CallOpc = ARMISD::t2CALL_BTI;
2793 else if (isCmseNSCall)
2794 CallOpc = ARMISD::tSECALL;
2795 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2796 CallOpc = ARMISD::CALL_NOLINK;
2797 else
2798 CallOpc = ARMISD::CALL;
2799 } else {
2800 if (!isDirect && !Subtarget->hasV5TOps())
2801 CallOpc = ARMISD::CALL_NOLINK;
2802 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2803 // Emit regular call when code size is the priority
2804 !Subtarget->hasMinSize())
2805 // "mov lr, pc; b _foo" to avoid confusing the RSP
2806 CallOpc = ARMISD::CALL_NOLINK;
2807 else
2808 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2809 }
2810
2811 // We don't usually want to end the call-sequence here because we would tidy
2812 // the frame up *after* the call, however in the ABI-changing tail-call case
2813 // we've carefully laid out the parameters so that when sp is reset they'll be
2814 // in the correct location.
2815 if (isTailCall && !isSibCall) {
2816 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InGlue, dl);
2817 InGlue = Chain.getValue(1);
2818 }
2819
2820 std::vector<SDValue> Ops;
2821 Ops.push_back(Chain);
2822 Ops.push_back(Callee);
2823
2824 if (isTailCall) {
2825 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2826 }
2827
2828 // Add argument registers to the end of the list so that they are known live
2829 // into the call.
2830 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2831 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2832 RegsToPass[i].second.getValueType()));
2833
2834 // Add a register mask operand representing the call-preserved registers.
2835 const uint32_t *Mask;
2836 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2837 if (isThisReturn) {
2838 // For 'this' returns, use the R0-preserving mask if applicable
2839 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2840 if (!Mask) {
2841 // Set isThisReturn to false if the calling convention is not one that
2842 // allows 'returned' to be modeled in this way, so LowerCallResult does
2843 // not try to pass 'this' straight through
2844 isThisReturn = false;
2845 Mask = ARI->getCallPreservedMask(MF, CallConv);
2846 }
2847 } else
2848 Mask = ARI->getCallPreservedMask(MF, CallConv);
2849
2850 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2850, __extension__
__PRETTY_FUNCTION__))
;
2851 Ops.push_back(DAG.getRegisterMask(Mask));
2852
2853 if (InGlue.getNode())
2854 Ops.push_back(InGlue);
2855
2856 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2857 if (isTailCall) {
2858 MF.getFrameInfo().setHasTailCall();
2859 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2860 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2861 return Ret;
2862 }
2863
2864 // Returns a chain and a flag for retval copy to use.
2865 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2866 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2867 InGlue = Chain.getValue(1);
2868 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2869
2870 // If we're guaranteeing tail-calls will be honoured, the callee must
2871 // pop its own argument stack on return. But this call is *not* a tail call so
2872 // we need to undo that after it returns to restore the status-quo.
2873 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2874 uint64_t CalleePopBytes =
2875 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2876
2877 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, CalleePopBytes, InGlue, dl);
2878 if (!Ins.empty())
2879 InGlue = Chain.getValue(1);
2880
2881 // Handle result values, copying them out of physregs into vregs that we
2882 // return.
2883 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2884 InVals, isThisReturn,
2885 isThisReturn ? OutVals[0] : SDValue());
2886}
2887
2888/// HandleByVal - Every parameter *after* a byval parameter is passed
2889/// on the stack. Remember the next parameter register to allocate,
2890/// and then confiscate the rest of the parameter registers to insure
2891/// this.
2892void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2893 Align Alignment) const {
2894 // Byval (as with any stack) slots are always at least 4 byte aligned.
2895 Alignment = std::max(Alignment, Align(4));
2896
2897 unsigned Reg = State->AllocateReg(GPRArgRegs);
2898 if (!Reg)
2899 return;
2900
2901 unsigned AlignInRegs = Alignment.value() / 4;
2902 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2903 for (unsigned i = 0; i < Waste; ++i)
2904 Reg = State->AllocateReg(GPRArgRegs);
2905
2906 if (!Reg)
2907 return;
2908
2909 unsigned Excess = 4 * (ARM::R4 - Reg);
2910
2911 // Special case when NSAA != SP and parameter size greater than size of
2912 // all remained GPR regs. In that case we can't split parameter, we must
2913 // send it to stack. We also must set NCRN to R4, so waste all
2914 // remained registers.
2915 const unsigned NSAAOffset = State->getNextStackOffset();
2916 if (NSAAOffset != 0 && Size > Excess) {
2917 while (State->AllocateReg(GPRArgRegs))
2918 ;
2919 return;
2920 }
2921
2922 // First register for byval parameter is the first register that wasn't
2923 // allocated before this method call, so it would be "reg".
2924 // If parameter is small enough to be saved in range [reg, r4), then
2925 // the end (first after last) register would be reg + param-size-in-regs,
2926 // else parameter would be splitted between registers and stack,
2927 // end register would be r4 in this case.
2928 unsigned ByValRegBegin = Reg;
2929 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2930 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2931 // Note, first register is allocated in the beginning of function already,
2932 // allocate remained amount of registers we need.
2933 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2934 State->AllocateReg(GPRArgRegs);
2935 // A byval parameter that is split between registers and memory needs its
2936 // size truncated here.
2937 // In the case where the entire structure fits in registers, we set the
2938 // size in memory to zero.
2939 Size = std::max<int>(Size - Excess, 0);
2940}
2941
2942/// MatchingStackOffset - Return true if the given stack call argument is
2943/// already available in the same position (relatively) of the caller's
2944/// incoming argument stack.
2945static
2946bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2947 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2948 const TargetInstrInfo *TII) {
2949 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2950 int FI = std::numeric_limits<int>::max();
2951 if (Arg.getOpcode() == ISD::CopyFromReg) {
2952 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2953 if (!VR.isVirtual())
2954 return false;
2955 MachineInstr *Def = MRI->getVRegDef(VR);
2956 if (!Def)
2957 return false;
2958 if (!Flags.isByVal()) {
2959 if (!TII->isLoadFromStackSlot(*Def, FI))
2960 return false;
2961 } else {
2962 return false;
2963 }
2964 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2965 if (Flags.isByVal())
2966 // ByVal argument is passed in as a pointer but it's now being
2967 // dereferenced. e.g.
2968 // define @foo(%struct.X* %A) {
2969 // tail call @bar(%struct.X* byval %A)
2970 // }
2971 return false;
2972 SDValue Ptr = Ld->getBasePtr();
2973 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2974 if (!FINode)
2975 return false;
2976 FI = FINode->getIndex();
2977 } else
2978 return false;
2979
2980 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2980, __extension__
__PRETTY_FUNCTION__))
;
2981 if (!MFI.isFixedObjectIndex(FI))
2982 return false;
2983 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2984}
2985
2986/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2987/// for tail call optimization. Targets which want to do tail call
2988/// optimization should implement this function.
2989bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2990 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2991 bool isCalleeStructRet, bool isCallerStructRet,
2992 const SmallVectorImpl<ISD::OutputArg> &Outs,
2993 const SmallVectorImpl<SDValue> &OutVals,
2994 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2995 const bool isIndirect) const {
2996 MachineFunction &MF = DAG.getMachineFunction();
2997 const Function &CallerF = MF.getFunction();
2998 CallingConv::ID CallerCC = CallerF.getCallingConv();
2999
3000 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3000, __extension__
__PRETTY_FUNCTION__))
;
3001
3002 // Indirect tail calls cannot be optimized for Thumb1 if the args
3003 // to the call take up r0-r3. The reason is that there are no legal registers
3004 // left to hold the pointer to the function to be called.
3005 // Similarly, if the function uses return address sign and authentication,
3006 // r12 is needed to hold the PAC and is not available to hold the callee
3007 // address.
3008 if (Outs.size() >= 4 &&
3009 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect)) {
3010 if (Subtarget->isThumb1Only())
3011 return false;
3012 // Conservatively assume the function spills LR.
3013 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true))
3014 return false;
3015 }
3016
3017 // Look for obvious safe cases to perform tail call optimization that do not
3018 // require ABI changes. This is what gcc calls sibcall.
3019
3020 // Exception-handling functions need a special set of instructions to indicate
3021 // a return to the hardware. Tail-calling another function would probably
3022 // break this.
3023 if (CallerF.hasFnAttribute("interrupt"))
3024 return false;
3025
3026 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
3027 return CalleeCC == CallerCC;
3028
3029 // Also avoid sibcall optimization if either caller or callee uses struct
3030 // return semantics.
3031 if (isCalleeStructRet || isCallerStructRet)
3032 return false;
3033
3034 // Externally-defined functions with weak linkage should not be
3035 // tail-called on ARM when the OS does not support dynamic
3036 // pre-emption of symbols, as the AAELF spec requires normal calls
3037 // to undefined weak functions to be replaced with a NOP or jump to the
3038 // next instruction. The behaviour of branch instructions in this
3039 // situation (as used for tail calls) is implementation-defined, so we
3040 // cannot rely on the linker replacing the tail call with a return.
3041 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3042 const GlobalValue *GV = G->getGlobal();
3043 const Triple &TT = getTargetMachine().getTargetTriple();
3044 if (GV->hasExternalWeakLinkage() &&
3045 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
3046 return false;
3047 }
3048
3049 // Check that the call results are passed in the same way.
3050 LLVMContext &C = *DAG.getContext();
3051 if (!CCState::resultsCompatible(
3052 getEffectiveCallingConv(CalleeCC, isVarArg),
3053 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
3054 CCAssignFnForReturn(CalleeCC, isVarArg),
3055 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
3056 return false;
3057 // The callee has to preserve all registers the caller needs to preserve.
3058 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3059 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3060 if (CalleeCC != CallerCC) {
3061 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3062 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3063 return false;
3064 }
3065
3066 // If Caller's vararg or byval argument has been split between registers and
3067 // stack, do not perform tail call, since part of the argument is in caller's
3068 // local frame.
3069 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
3070 if (AFI_Caller->getArgRegsSaveSize())
3071 return false;
3072
3073 // If the callee takes no arguments then go on to check the results of the
3074 // call.
3075 if (!Outs.empty()) {
3076 // Check if stack adjustment is needed. For now, do not do this if any
3077 // argument is passed on the stack.
3078 SmallVector<CCValAssign, 16> ArgLocs;
3079 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3080 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3081 if (CCInfo.getNextStackOffset()) {
3082 // Check if the arguments are already laid out in the right way as
3083 // the caller's fixed stack objects.
3084 MachineFrameInfo &MFI = MF.getFrameInfo();
3085 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3086 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3087 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
3088 i != e;
3089 ++i, ++realArgIdx) {
3090 CCValAssign &VA = ArgLocs[i];
3091 EVT RegVT = VA.getLocVT();
3092 SDValue Arg = OutVals[realArgIdx];
3093 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3094 if (VA.getLocInfo() == CCValAssign::Indirect)
3095 return false;
3096 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3097 // f64 and vector types are split into multiple registers or
3098 // register/stack-slot combinations. The types will not match
3099 // the registers; give up on memory f64 refs until we figure
3100 // out what to do about this.
3101 if (!VA.isRegLoc())
3102 return false;
3103 if (!ArgLocs[++i].isRegLoc())
3104 return false;
3105 if (RegVT == MVT::v2f64) {
3106 if (!ArgLocs[++i].isRegLoc())
3107 return false;
3108 if (!ArgLocs[++i].isRegLoc())
3109 return false;
3110 }
3111 } else if (!VA.isRegLoc()) {
3112 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3113 MFI, MRI, TII))
3114 return false;
3115 }
3116 }
3117 }
3118
3119 const MachineRegisterInfo &MRI = MF.getRegInfo();
3120 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3121 return false;
3122 }
3123
3124 return true;
3125}
3126
3127bool
3128ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3129 MachineFunction &MF, bool isVarArg,
3130 const SmallVectorImpl<ISD::OutputArg> &Outs,
3131 LLVMContext &Context) const {
3132 SmallVector<CCValAssign, 16> RVLocs;
3133 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3134 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3135}
3136
3137static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3138 const SDLoc &DL, SelectionDAG &DAG) {
3139 const MachineFunction &MF = DAG.getMachineFunction();
3140 const Function &F = MF.getFunction();
3141
3142 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3143
3144 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3145 // version of the "preferred return address". These offsets affect the return
3146 // instruction if this is a return from PL1 without hypervisor extensions.
3147 // IRQ/FIQ: +4 "subs pc, lr, #4"
3148 // SWI: 0 "subs pc, lr, #0"
3149 // ABORT: +4 "subs pc, lr, #4"
3150 // UNDEF: +4/+2 "subs pc, lr, #0"
3151 // UNDEF varies depending on where the exception came from ARM or Thumb
3152 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3153
3154 int64_t LROffset;
3155 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3156 IntKind == "ABORT")
3157 LROffset = 4;
3158 else if (IntKind == "SWI" || IntKind == "UNDEF")
3159 LROffset = 0;
3160 else
3161 report_fatal_error("Unsupported interrupt attribute. If present, value "
3162 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3163
3164 RetOps.insert(RetOps.begin() + 1,
3165 DAG.getConstant(LROffset, DL, MVT::i32, false));
3166
3167 return DAG.getNode(ARMISD::INTRET_GLUE, DL, MVT::Other, RetOps);
3168}
3169
3170SDValue
3171ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3172 bool isVarArg,
3173 const SmallVectorImpl<ISD::OutputArg> &Outs,
3174 const SmallVectorImpl<SDValue> &OutVals,
3175 const SDLoc &dl, SelectionDAG &DAG) const {
3176 // CCValAssign - represent the assignment of the return value to a location.
3177 SmallVector<CCValAssign, 16> RVLocs;
3178
3179 // CCState - Info about the registers and stack slots.
3180 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3181 *DAG.getContext());
3182
3183 // Analyze outgoing return values.
3184 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3185
3186 SDValue Glue;
3187 SmallVector<SDValue, 4> RetOps;
3188 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3189 bool isLittleEndian = Subtarget->isLittle();
3190
3191 MachineFunction &MF = DAG.getMachineFunction();
3192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3193 AFI->setReturnRegsCount(RVLocs.size());
3194
3195 // Report error if cmse entry function returns structure through first ptr arg.
3196 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3197 // Note: using an empty SDLoc(), as the first line of the function is a
3198 // better place to report than the last line.
3199 DiagnosticInfoUnsupported Diag(
3200 DAG.getMachineFunction().getFunction(),
3201 "secure entry function would return value through pointer",
3202 SDLoc().getDebugLoc());
3203 DAG.getContext()->diagnose(Diag);
3204 }
3205
3206 // Copy the result values into the output registers.
3207 for (unsigned i = 0, realRVLocIdx = 0;
3208 i != RVLocs.size();
3209 ++i, ++realRVLocIdx) {
3210 CCValAssign &VA = RVLocs[i];
3211 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3211, __extension__
__PRETTY_FUNCTION__))
;
3212
3213 SDValue Arg = OutVals[realRVLocIdx];
3214 bool ReturnF16 = false;
3215
3216 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3217 // Half-precision return values can be returned like this:
3218 //
3219 // t11 f16 = fadd ...
3220 // t12: i16 = bitcast t11
3221 // t13: i32 = zero_extend t12
3222 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3223 //
3224 // to avoid code generation for bitcasts, we simply set Arg to the node
3225 // that produces the f16 value, t11 in this case.
3226 //
3227 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3228 SDValue ZE = Arg.getOperand(0);
3229 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3230 SDValue BC = ZE.getOperand(0);
3231 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3232 Arg = BC.getOperand(0);
3233 ReturnF16 = true;
3234 }
3235 }
3236 }
3237 }
3238
3239 switch (VA.getLocInfo()) {
3240 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3240)
;
3241 case CCValAssign::Full: break;
3242 case CCValAssign::BCvt:
3243 if (!ReturnF16)
3244 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3245 break;
3246 }
3247
3248 // Mask f16 arguments if this is a CMSE nonsecure entry.
3249 auto RetVT = Outs[realRVLocIdx].ArgVT;
3250 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3251 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3252 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3253 } else {
3254 auto LocBits = VA.getLocVT().getSizeInBits();
3255 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3256 SDValue Mask =
3257 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3258 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3259 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3260 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3261 }
3262 }
3263
3264 if (VA.needsCustom() &&
3265 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3266 if (VA.getLocVT() == MVT::v2f64) {
3267 // Extract the first half and return it in two registers.
3268 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3269 DAG.getConstant(0, dl, MVT::i32));
3270 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3271 DAG.getVTList(MVT::i32, MVT::i32), Half);
3272
3273 Chain =
3274 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3275 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Glue);
3276 Glue = Chain.getValue(1);
3277 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3278 VA = RVLocs[++i]; // skip ahead to next loc
3279 Chain =
3280 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3281 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Glue);
3282 Glue = Chain.getValue(1);
3283 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3284 VA = RVLocs[++i]; // skip ahead to next loc
3285
3286 // Extract the 2nd half and fall through to handle it as an f64 value.
3287 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3288 DAG.getConstant(1, dl, MVT::i32));
3289 }
3290 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3291 // available.
3292 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3293 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3294 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3295 fmrrd.getValue(isLittleEndian ? 0 : 1), Glue);
3296 Glue = Chain.getValue(1);
3297 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3298 VA = RVLocs[++i]; // skip ahead to next loc
3299 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3300 fmrrd.getValue(isLittleEndian ? 1 : 0), Glue);
3301 } else
3302 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Glue);
3303
3304 // Guarantee that all emitted copies are
3305 // stuck together, avoiding something bad.
3306 Glue = Chain.getValue(1);
3307 RetOps.push_back(DAG.getRegister(
3308 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3309 }
3310 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3311 const MCPhysReg *I =
3312 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3313 if (I) {
3314 for (; *I; ++I) {
3315 if (ARM::GPRRegClass.contains(*I))
3316 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3317 else if (ARM::DPRRegClass.contains(*I))
3318 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3319 else
3320 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3320)
;
3321 }
3322 }
3323
3324 // Update chain and glue.
3325 RetOps[0] = Chain;
3326 if (Glue.getNode())
3327 RetOps.push_back(Glue);
3328
3329 // CPUs which aren't M-class use a special sequence to return from
3330 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3331 // though we use "subs pc, lr, #N").
3332 //
3333 // M-class CPUs actually use a normal return sequence with a special
3334 // (hardware-provided) value in LR, so the normal code path works.
3335 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3336 !Subtarget->isMClass()) {
3337 if (Subtarget->isThumb1Only())
3338 report_fatal_error("interrupt attribute is not supported in Thumb1");
3339 return LowerInterruptReturn(RetOps, dl, DAG);
3340 }
3341
3342 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_GLUE :
3343 ARMISD::RET_GLUE;
3344 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3345}
3346
3347bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3348 if (N->getNumValues() != 1)
3349 return false;
3350 if (!N->hasNUsesOfValue(1, 0))
3351 return false;
3352
3353 SDValue TCChain = Chain;
3354 SDNode *Copy = *N->use_begin();
3355 if (Copy->getOpcode() == ISD::CopyToReg) {
3356 // If the copy has a glue operand, we conservatively assume it isn't safe to
3357 // perform a tail call.
3358 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3359 return false;
3360 TCChain = Copy->getOperand(0);
3361 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3362 SDNode *VMov = Copy;
3363 // f64 returned in a pair of GPRs.
3364 SmallPtrSet<SDNode*, 2> Copies;
3365 for (SDNode *U : VMov->uses()) {
3366 if (U->getOpcode() != ISD::CopyToReg)
3367 return false;
3368 Copies.insert(U);
3369 }
3370 if (Copies.size() > 2)
3371 return false;
3372
3373 for (SDNode *U : VMov->uses()) {
3374 SDValue UseChain = U->getOperand(0);
3375 if (Copies.count(UseChain.getNode()))
3376 // Second CopyToReg
3377 Copy = U;
3378 else {
3379 // We are at the top of this chain.
3380 // If the copy has a glue operand, we conservatively assume it
3381 // isn't safe to perform a tail call.
3382 if (U->getOperand(U->getNumOperands() - 1).getValueType() == MVT::Glue)
3383 return false;
3384 // First CopyToReg
3385 TCChain = UseChain;
3386 }
3387 }
3388 } else if (Copy->getOpcode() == ISD::BITCAST) {
3389 // f32 returned in a single GPR.
3390 if (!Copy->hasOneUse())
3391 return false;
3392 Copy = *Copy->use_begin();
3393 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3394 return false;
3395 // If the copy has a glue operand, we conservatively assume it isn't safe to
3396 // perform a tail call.
3397 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3398 return false;
3399 TCChain = Copy->getOperand(0);
3400 } else {
3401 return false;
3402 }
3403
3404 bool HasRet = false;
3405 for (const SDNode *U : Copy->uses()) {
3406 if (U->getOpcode() != ARMISD::RET_GLUE &&
3407 U->getOpcode() != ARMISD::INTRET_GLUE)
3408 return false;
3409 HasRet = true;
3410 }
3411
3412 if (!HasRet)
3413 return false;
3414
3415 Chain = TCChain;
3416 return true;
3417}
3418
3419bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3420 if (!Subtarget->supportsTailCall())
3421 return false;
3422
3423 if (!CI->isTailCall())
3424 return false;
3425
3426 return true;
3427}
3428
3429// Trying to write a 64 bit value so need to split into two 32 bit values first,
3430// and pass the lower and high parts through.
3431static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3432 SDLoc DL(Op);
3433 SDValue WriteValue = Op->getOperand(2);
3434
3435 // This function is only supposed to be called for i64 type argument.
3436 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3437, __extension__
__PRETTY_FUNCTION__))
3437 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3437, __extension__
__PRETTY_FUNCTION__))
;
3438
3439 SDValue Lo, Hi;
3440 std::tie(Lo, Hi) = DAG.SplitScalar(WriteValue, DL, MVT::i32, MVT::i32);
3441 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3442 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3443}
3444
3445// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3446// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3447// one of the above mentioned nodes. It has to be wrapped because otherwise
3448// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3449// be used to form addressing mode. These wrapped nodes will be selected
3450// into MOVi.
3451SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3452 SelectionDAG &DAG) const {
3453 EVT PtrVT = Op.getValueType();
3454 // FIXME there is no actual debug info here
3455 SDLoc dl(Op);
3456 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3457 SDValue Res;
3458
3459 // When generating execute-only code Constant Pools must be promoted to the
3460 // global data section. It's a bit ugly that we can't share them across basic
3461 // blocks, but this way we guarantee that execute-only behaves correct with
3462 // position-independent addressing modes.
3463 if (Subtarget->genExecuteOnly()) {
3464 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3465 auto T = const_cast<Type*>(CP->getType());
3466 auto C = const_cast<Constant*>(CP->getConstVal());
3467 auto M = const_cast<Module*>(DAG.getMachineFunction().
3468 getFunction().getParent());
3469 auto GV = new GlobalVariable(
3470 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3471 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3472 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3473 Twine(AFI->createPICLabelUId())
3474 );
3475 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3476 dl, PtrVT);
3477 return LowerGlobalAddress(GA, DAG);
3478 }
3479
3480 // The 16-bit ADR instruction can only encode offsets that are multiples of 4,
3481 // so we need to align to at least 4 bytes when we don't have 32-bit ADR.
3482 Align CPAlign = CP->getAlign();
3483 if (Subtarget->isThumb1Only())
3484 CPAlign = std::max(CPAlign, Align(4));
3485 if (CP->isMachineConstantPoolEntry())
3486 Res =
3487 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CPAlign);
3488 else
3489 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CPAlign);
3490 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3491}
3492
3493unsigned ARMTargetLowering::getJumpTableEncoding() const {
3494 return MachineJumpTableInfo::EK_Inline;
3495}
3496
3497SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3498 SelectionDAG &DAG) const {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3501 unsigned ARMPCLabelIndex = 0;
3502 SDLoc DL(Op);
3503 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3504 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3505 SDValue CPAddr;
3506 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3507 if (!IsPositionIndependent) {
3508 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3509 } else {
3510 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3511 ARMPCLabelIndex = AFI->createPICLabelUId();
3512 ARMConstantPoolValue *CPV =
3513 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3514 ARMCP::CPBlockAddress, PCAdj);
3515 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3516 }
3517 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3518 SDValue Result = DAG.getLoad(
3519 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3520 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3521 if (!IsPositionIndependent)
3522 return Result;
3523 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3524 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3525}
3526
3527/// Convert a TLS address reference into the correct sequence of loads
3528/// and calls to compute the variable's address for Darwin, and return an
3529/// SDValue containing the final node.
3530
3531/// Darwin only has one TLS scheme which must be capable of dealing with the
3532/// fully general situation, in the worst case. This means:
3533/// + "extern __thread" declaration.
3534/// + Defined in a possibly unknown dynamic library.
3535///
3536/// The general system is that each __thread variable has a [3 x i32] descriptor
3537/// which contains information used by the runtime to calculate the address. The
3538/// only part of this the compiler needs to know about is the first word, which
3539/// contains a function pointer that must be called with the address of the
3540/// entire descriptor in "r0".
3541///
3542/// Since this descriptor may be in a different unit, in general access must
3543/// proceed along the usual ARM rules. A common sequence to produce is:
3544///
3545/// movw rT1, :lower16:_var$non_lazy_ptr
3546/// movt rT1, :upper16:_var$non_lazy_ptr
3547/// ldr r0, [rT1]
3548/// ldr rT2, [r0]
3549/// blx rT2
3550/// [...address now in r0...]
3551SDValue
3552ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3553 SelectionDAG &DAG) const {
3554 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3555, __extension__
__PRETTY_FUNCTION__))
3555 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3555, __extension__
__PRETTY_FUNCTION__))
;
3556 SDLoc DL(Op);
3557
3558 // First step is to get the address of the actua global symbol. This is where
3559 // the TLS descriptor lives.
3560 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3561
3562 // The first entry in the descriptor is a function pointer that we must call
3563 // to obtain the address of the variable.
3564 SDValue Chain = DAG.getEntryNode();
3565 SDValue FuncTLVGet = DAG.getLoad(
3566 MVT::i32, DL, Chain, DescAddr,
3567 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3568 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3569 MachineMemOperand::MOInvariant);
3570 Chain = FuncTLVGet.getValue(1);
3571
3572 MachineFunction &F = DAG.getMachineFunction();
3573 MachineFrameInfo &MFI = F.getFrameInfo();
3574 MFI.setAdjustsStack(true);
3575
3576 // TLS calls preserve all registers except those that absolutely must be
3577 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3578 // silly).
3579 auto TRI =
3580 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3581 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3582 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3583
3584 // Finally, we can make the call. This is just a degenerate version of a
3585 // normal AArch64 call node: r0 takes the address of the descriptor, and
3586 // returns the address of the variable in this thread.
3587 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3588 Chain =
3589 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3590 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3591 DAG.getRegisterMask(Mask), Chain.getValue(1));
3592 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3593}
3594
3595SDValue
3596ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3597 SelectionDAG &DAG) const {
3598 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3598, __extension__
__PRETTY_FUNCTION__))
;
3599
3600 SDValue Chain = DAG.getEntryNode();
3601 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3602 SDLoc DL(Op);
3603
3604 // Load the current TEB (thread environment block)
3605 SDValue Ops[] = {Chain,
3606 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3607 DAG.getTargetConstant(15, DL, MVT::i32),
3608 DAG.getTargetConstant(0, DL, MVT::i32),
3609 DAG.getTargetConstant(13, DL, MVT::i32),
3610 DAG.getTargetConstant(0, DL, MVT::i32),
3611 DAG.getTargetConstant(2, DL, MVT::i32)};
3612 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3613 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3614
3615 SDValue TEB = CurrentTEB.getValue(0);
3616 Chain = CurrentTEB.getValue(1);
3617
3618 // Load the ThreadLocalStoragePointer from the TEB
3619 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3620 SDValue TLSArray =
3621 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3622 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3623
3624 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3625 // offset into the TLSArray.
3626
3627 // Load the TLS index from the C runtime
3628 SDValue TLSIndex =
3629 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3630 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3631 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3632
3633 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3634 DAG.getConstant(2, DL, MVT::i32));
3635 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3636 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3637 MachinePointerInfo());
3638
3639 // Get the offset of the start of the .tls section (section base)
3640 const auto *GA = cast<GlobalAddressSDNode>(Op);
3641 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3642 SDValue Offset = DAG.getLoad(
3643 PtrVT, DL, Chain,
3644 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3645 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3646 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3647
3648 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3649}
3650
3651// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3652SDValue
3653ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3654 SelectionDAG &DAG) const {
3655 SDLoc dl(GA);
3656 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3657 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3658 MachineFunction &MF = DAG.getMachineFunction();
3659 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3660 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3661 ARMConstantPoolValue *CPV =
3662 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3663 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3664 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3665 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3666 Argument = DAG.getLoad(
3667 PtrVT, dl, DAG.getEntryNode(), Argument,
3668 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3669 SDValue Chain = Argument.getValue(1);
3670
3671 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3672 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3673
3674 // call __tls_get_addr.
3675 ArgListTy Args;
3676 ArgListEntry Entry;
3677 Entry.Node = Argument;
3678 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3679 Args.push_back(Entry);
3680
3681 // FIXME: is there useful debug info available here?
3682 TargetLowering::CallLoweringInfo CLI(DAG);
3683 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3684 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3685 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3686
3687 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3688 return CallResult.first;
3689}
3690
3691// Lower ISD::GlobalTLSAddress using the "initial exec" or
3692// "local exec" model.
3693SDValue
3694ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3695 SelectionDAG &DAG,
3696 TLSModel::Model model) const {
3697 const GlobalValue *GV = GA->getGlobal();
3698 SDLoc dl(GA);
3699 SDValue Offset;
3700 SDValue Chain = DAG.getEntryNode();
3701 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3702 // Get the Thread Pointer
3703 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3704
3705 if (model == TLSModel::InitialExec) {
3706 MachineFunction &MF = DAG.getMachineFunction();
3707 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3708 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3709 // Initial exec model.
3710 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3711 ARMConstantPoolValue *CPV =
3712 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3713 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3714 true);
3715 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3716 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3717 Offset = DAG.getLoad(
3718 PtrVT, dl, Chain, Offset,
3719 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3720 Chain = Offset.getValue(1);
3721
3722 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3723 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3724
3725 Offset = DAG.getLoad(
3726 PtrVT, dl, Chain, Offset,
3727 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3728 } else {
3729 // local exec model
3730 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3730, __extension__ __PRETTY_FUNCTION__))
;
3731 ARMConstantPoolValue *CPV =
3732 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3733 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3734 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3735 Offset = DAG.getLoad(
3736 PtrVT, dl, Chain, Offset,
3737 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3738 }
3739
3740 // The address of the thread local variable is the add of the thread
3741 // pointer with the offset of the variable.
3742 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3743}
3744
3745SDValue
3746ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3747 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3748 if (DAG.getTarget().useEmulatedTLS())
3749 return LowerToTLSEmulatedModel(GA, DAG);
3750
3751 if (Subtarget->isTargetDarwin())
3752 return LowerGlobalTLSAddressDarwin(Op, DAG);
3753
3754 if (Subtarget->isTargetWindows())
3755 return LowerGlobalTLSAddressWindows(Op, DAG);
3756
3757 // TODO: implement the "local dynamic" model
3758 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3758, __extension__
__PRETTY_FUNCTION__))
;
3759 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3760
3761 switch (model) {
3762 case TLSModel::GeneralDynamic:
3763 case TLSModel::LocalDynamic:
3764 return LowerToTLSGeneralDynamicModel(GA, DAG);
3765 case TLSModel::InitialExec:
3766 case TLSModel::LocalExec:
3767 return LowerToTLSExecModels(GA, DAG, model);
3768 }
3769 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3769)
;
3770}
3771
3772/// Return true if all users of V are within function F, looking through
3773/// ConstantExprs.
3774static bool allUsersAreInFunction(const Value *V, const Function *F) {
3775 SmallVector<const User*,4> Worklist(V->users());
3776 while (!Worklist.empty()) {
3777 auto *U = Worklist.pop_back_val();
3778 if (isa<ConstantExpr>(U)) {
3779 append_range(Worklist, U->users());
3780 continue;
3781 }
3782
3783 auto *I = dyn_cast<Instruction>(U);
3784 if (!I || I->getParent()->getParent() != F)
3785 return false;
3786 }
3787 return true;
3788}
3789
3790static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3791 const GlobalValue *GV, SelectionDAG &DAG,
3792 EVT PtrVT, const SDLoc &dl) {
3793 // If we're creating a pool entry for a constant global with unnamed address,
3794 // and the global is small enough, we can emit it inline into the constant pool
3795 // to save ourselves an indirection.
3796 //
3797 // This is a win if the constant is only used in one function (so it doesn't
3798 // need to be duplicated) or duplicating the constant wouldn't increase code
3799 // size (implying the constant is no larger than 4 bytes).
3800 const Function &F = DAG.getMachineFunction().getFunction();
3801
3802 // We rely on this decision to inline being idemopotent and unrelated to the
3803 // use-site. We know that if we inline a variable at one use site, we'll
3804 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3805 // doesn't know about this optimization, so bail out if it's enabled else
3806 // we could decide to inline here (and thus never emit the GV) but require
3807 // the GV from fast-isel generated code.
3808 if (!EnableConstpoolPromotion ||
3809 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3810 return SDValue();
3811
3812 auto *GVar = dyn_cast<GlobalVariable>(GV);
3813 if (!GVar || !GVar->hasInitializer() ||
3814 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3815 !GVar->hasLocalLinkage())
3816 return SDValue();
3817
3818 // If we inline a value that contains relocations, we move the relocations
3819 // from .data to .text. This is not allowed in position-independent code.
3820 auto *Init = GVar->getInitializer();
3821 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3822 Init->needsDynamicRelocation())
3823 return SDValue();
3824
3825 // The constant islands pass can only really deal with alignment requests
3826 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3827 // any type wanting greater alignment requirements than 4 bytes. We also
3828 // can only promote constants that are multiples of 4 bytes in size or
3829 // are paddable to a multiple of 4. Currently we only try and pad constants
3830 // that are strings for simplicity.
3831 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3832 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3833 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3834 unsigned RequiredPadding = 4 - (Size % 4);
3835 bool PaddingPossible =
3836 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3837 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3838 Size == 0)
3839 return SDValue();
3840
3841 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3842 MachineFunction &MF = DAG.getMachineFunction();
3843 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3844
3845 // We can't bloat the constant pool too much, else the ConstantIslands pass
3846 // may fail to converge. If we haven't promoted this global yet (it may have
3847 // multiple uses), and promoting it would increase the constant pool size (Sz
3848 // > 4), ensure we have space to do so up to MaxTotal.
3849 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3850 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3851 ConstpoolPromotionMaxTotal)
3852 return SDValue();
3853
3854 // This is only valid if all users are in a single function; we can't clone
3855 // the constant in general. The LLVM IR unnamed_addr allows merging
3856 // constants, but not cloning them.
3857 //
3858 // We could potentially allow cloning if we could prove all uses of the
3859 // constant in the current function don't care about the address, like
3860 // printf format strings. But that isn't implemented for now.
3861 if (!allUsersAreInFunction(GVar, &F))
3862 return SDValue();
3863
3864 // We're going to inline this global. Pad it out if needed.
3865 if (RequiredPadding != 4) {
3866 StringRef S = CDAInit->getAsString();
3867
3868 SmallVector<uint8_t,16> V(S.size());
3869 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3870 while (RequiredPadding--)
3871 V.push_back(0);
3872 Init = ConstantDataArray::get(*DAG.getContext(), V);
3873 }
3874
3875 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3876 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3877 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3878 AFI->markGlobalAsPromotedToConstantPool(GVar);
3879 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3880 PaddedSize - 4);
3881 }
3882 ++NumConstpoolPromoted;
3883 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3884}
3885
3886bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3887 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3888 if (!(GV = GA->getAliaseeObject()))
3889 return false;
3890 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3891 return V->isConstant();
3892 return isa<Function>(GV);
3893}
3894
3895SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3896 SelectionDAG &DAG) const {
3897 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3898 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3898)
;
3899 case Triple::COFF:
3900 return LowerGlobalAddressWindows(Op, DAG);
3901 case Triple::ELF:
3902 return LowerGlobalAddressELF(Op, DAG);
3903 case Triple::MachO:
3904 return LowerGlobalAddressDarwin(Op, DAG);
3905 }
3906}
3907
3908SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3909 SelectionDAG &DAG) const {
3910 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3911 SDLoc dl(Op);
3912 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3913 const TargetMachine &TM = getTargetMachine();
3914 bool IsRO = isReadOnly(GV);
3915
3916 // promoteToConstantPool only if not generating XO text section
3917 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3918 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3919 return V;
3920
3921 if (isPositionIndependent()) {
3922 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3923 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3924 UseGOT_PREL ? ARMII::MO_GOT : 0);
3925 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3926 if (UseGOT_PREL)
3927 Result =
3928 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3929 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3930 return Result;
3931 } else if (Subtarget->isROPI() && IsRO) {
3932 // PC-relative.
3933 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3934 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3935 return Result;
3936 } else if (Subtarget->isRWPI() && !IsRO) {
3937 // SB-relative.
3938 SDValue RelAddr;
3939 if (Subtarget->useMovt()) {
3940 ++NumMovwMovt;
3941 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3942 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3943 } else { // use literal pool for address constant
3944 ARMConstantPoolValue *CPV =
3945 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3946 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3947 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3948 RelAddr = DAG.getLoad(
3949 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3950 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3951 }
3952 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3953 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3954 return Result;
3955 }
3956
3957 // If we have T2 ops, we can materialize the address directly via movt/movw
3958 // pair. This is always cheaper.
3959 if (Subtarget->useMovt()) {
3960 ++NumMovwMovt;
3961 // FIXME: Once remat is capable of dealing with instructions with register
3962 // operands, expand this into two nodes.
3963 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3964 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3965 } else {
3966 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3967 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3968 return DAG.getLoad(
3969 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3970 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3971 }
3972}
3973
3974SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3975 SelectionDAG &DAG) const {
3976 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3977, __extension__
__PRETTY_FUNCTION__))
3977 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3977, __extension__
__PRETTY_FUNCTION__))
;
3978 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3979 SDLoc dl(Op);
3980 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3981
3982 if (Subtarget->useMovt())
3983 ++NumMovwMovt;
3984
3985 // FIXME: Once remat is capable of dealing with instructions with register
3986 // operands, expand this into multiple nodes
3987 unsigned Wrapper =
3988 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3989
3990 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3991 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3992
3993 if (Subtarget->isGVIndirectSymbol(GV))
3994 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3995 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3996 return Result;
3997}
3998
3999SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
4000 SelectionDAG &DAG) const {
4001 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4001, __extension__
__PRETTY_FUNCTION__))
;
4002 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4003, __extension__
__PRETTY_FUNCTION__))
4003 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4003, __extension__
__PRETTY_FUNCTION__))
;
4004 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4005, __extension__
__PRETTY_FUNCTION__))
4005 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4005, __extension__
__PRETTY_FUNCTION__))
;
4006
4007 const TargetMachine &TM = getTargetMachine();
4008 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4009 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
4010 if (GV->hasDLLImportStorageClass())
4011 TargetFlags = ARMII::MO_DLLIMPORT;
4012 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
4013 TargetFlags = ARMII::MO_COFFSTUB;
4014 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4015 SDValue Result;
4016 SDLoc DL(Op);
4017
4018 ++NumMovwMovt;
4019
4020 // FIXME: Once remat is capable of dealing with instructions with register
4021 // operands, expand this into two nodes.
4022 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
4023 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
4024 TargetFlags));
4025 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
4026 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
4027 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
4028 return Result;
4029}
4030
4031SDValue
4032ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
4033 SDLoc dl(Op);
4034 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
4035 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
4036 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
4037 Op.getOperand(1), Val);
4038}
4039
4040SDValue
4041ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
4042 SDLoc dl(Op);
4043 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
4044 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
4045}
4046
4047SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
4048 SelectionDAG &DAG) const {
4049 SDLoc dl(Op);
4050 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
4051 Op.getOperand(0));
4052}
4053
4054SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4055 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
4056 unsigned IntNo =
4057 cast<ConstantSDNode>(
4058 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4059 ->getZExtValue();
4060 switch (IntNo) {
4061 default:
4062 return SDValue(); // Don't custom lower most intrinsics.
4063 case Intrinsic::arm_gnu_eabi_mcount: {
4064 MachineFunction &MF = DAG.getMachineFunction();
4065 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4066 SDLoc dl(Op);
4067 SDValue Chain = Op.getOperand(0);
4068 // call "\01__gnu_mcount_nc"
4069 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
4070 const uint32_t *Mask =
4071 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
4072 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4072, __extension__
__PRETTY_FUNCTION__))
;
4073 // Mark LR an implicit live-in.
4074 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4075 SDValue ReturnAddress =
4076 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
4077 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
4078 SDValue Callee =
4079 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
4080 SDValue RegisterMask = DAG.getRegisterMask(Mask);
4081 if (Subtarget->isThumb())
4082 return SDValue(
4083 DAG.getMachineNode(
4084 ARM::tBL_PUSHLR, dl, ResultTys,
4085 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
4086 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4087 0);
4088 return SDValue(
4089 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
4090 {ReturnAddress, Callee, RegisterMask, Chain}),
4091 0);
4092 }
4093 }
4094}
4095
4096SDValue
4097ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4098 const ARMSubtarget *Subtarget) const {
4099 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4100 SDLoc dl(Op);
4101 switch (IntNo) {
4102 default: return SDValue(); // Don't custom lower most intrinsics.
4103 case Intrinsic::thread_pointer: {
4104 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4105 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4106 }
4107 case Intrinsic::arm_cls: {
4108 const SDValue &Operand = Op.getOperand(1);
4109 const EVT VTy = Op.getValueType();
4110 SDValue SRA =
4111 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4112 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4113 SDValue SHL =
4114 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4115 SDValue OR =
4116 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4117 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4118 return Result;
4119 }
4120 case Intrinsic::arm_cls64: {
4121 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4122 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4123 const SDValue &Operand = Op.getOperand(1);
4124 const EVT VTy = Op.getValueType();
4125 SDValue Lo, Hi;
4126 std::tie(Lo, Hi) = DAG.SplitScalar(Operand, dl, VTy, VTy);
4127 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4128 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4129 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4130 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4131 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4132 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4133 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4134 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4135 SDValue CheckLo =
4136 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4137 SDValue HiIsZero =
4138 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4139 SDValue AdjustedLo =
4140 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4141 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4142 SDValue Result =
4143 DAG.getSelect(dl, VTy, CheckLo,
4144 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4145 return Result;
4146 }
4147 case Intrinsic::eh_sjlj_lsda: {
4148 MachineFunction &MF = DAG.getMachineFunction();
4149 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4150 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4151 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4152 SDValue CPAddr;
4153 bool IsPositionIndependent = isPositionIndependent();
4154 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4155 ARMConstantPoolValue *CPV =
4156 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4157 ARMCP::CPLSDA, PCAdj);
4158 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4159 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4160 SDValue Result = DAG.getLoad(
4161 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4162 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4163
4164 if (IsPositionIndependent) {
4165 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4166 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4167 }
4168 return Result;
4169 }
4170 case Intrinsic::arm_neon_vabs:
4171 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4172 Op.getOperand(1));
4173 case Intrinsic::arm_neon_vmulls:
4174 case Intrinsic::arm_neon_vmullu: {
4175 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4176 ? ARMISD::VMULLs : ARMISD::VMULLu;
4177 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4178 Op.getOperand(1), Op.getOperand(2));
4179 }
4180 case Intrinsic::arm_neon_vminnm:
4181 case Intrinsic::arm_neon_vmaxnm: {
4182 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4183 ? ISD::FMINNUM : ISD::FMAXNUM;
4184 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4185 Op.getOperand(1), Op.getOperand(2));
4186 }
4187 case Intrinsic::arm_neon_vminu:
4188 case Intrinsic::arm_neon_vmaxu: {
4189 if (Op.getValueType().isFloatingPoint())
4190 return SDValue();
4191 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4192 ? ISD::UMIN : ISD::UMAX;
4193 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4194 Op.getOperand(1), Op.getOperand(2));
4195 }
4196 case Intrinsic::arm_neon_vmins:
4197 case Intrinsic::arm_neon_vmaxs: {
4198 // v{min,max}s is overloaded between signed integers and floats.
4199 if (!Op.getValueType().isFloatingPoint()) {
4200 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4201 ? ISD::SMIN : ISD::SMAX;
4202 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4203 Op.getOperand(1), Op.getOperand(2));
4204 }
4205 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4206 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4207 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4208 Op.getOperand(1), Op.getOperand(2));
4209 }
4210 case Intrinsic::arm_neon_vtbl1:
4211 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4212 Op.getOperand(1), Op.getOperand(2));
4213 case Intrinsic::arm_neon_vtbl2:
4214 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4215 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4216 case Intrinsic::arm_mve_pred_i2v:
4217 case Intrinsic::arm_mve_pred_v2i:
4218 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4219 Op.getOperand(1));
4220 case Intrinsic::arm_mve_vreinterpretq:
4221 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4222 Op.getOperand(1));
4223 case Intrinsic::arm_mve_lsll:
4224 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4225 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4226 case Intrinsic::arm_mve_asrl:
4227 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4228 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4229 }
4230}
4231
4232static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4233 const ARMSubtarget *Subtarget) {
4234 SDLoc dl(Op);
4235 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4236 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4237 if (SSID == SyncScope::SingleThread)
4238 return Op;
4239
4240 if (!Subtarget->hasDataBarrier()) {
4241 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4242 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4243 // here.
4244 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4245, __extension__
__PRETTY_FUNCTION__))
4245 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4245, __extension__
__PRETTY_FUNCTION__))
;
4246 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4247 DAG.getConstant(0, dl, MVT::i32));
4248 }
4249
4250 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4251 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4252 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4253 if (Subtarget->isMClass()) {
4254 // Only a full system barrier exists in the M-class architectures.
4255 Domain = ARM_MB::SY;
4256 } else if (Subtarget->preferISHSTBarriers() &&
4257 Ord == AtomicOrdering::Release) {
4258 // Swift happens to implement ISHST barriers in a way that's compatible with
4259 // Release semantics but weaker than ISH so we'd be fools not to use
4260 // it. Beware: other processors probably don't!
4261 Domain = ARM_MB::ISHST;
4262 }
4263
4264 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4265 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4266 DAG.getConstant(Domain, dl, MVT::i32));
4267}
4268
4269static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4270 const ARMSubtarget *Subtarget) {
4271 // ARM pre v5TE and Thumb1 does not have preload instructions.
4272 if (!(Subtarget->isThumb2() ||
4273 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4274 // Just preserve the chain.
4275 return Op.getOperand(0);
4276
4277 SDLoc dl(Op);
4278 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4279 if (!isRead &&
4280 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4281 // ARMv7 with MP extension has PLDW.
4282 return Op.getOperand(0);
4283
4284 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4285 if (Subtarget->isThumb()) {
4286 // Invert the bits.
4287 isRead = ~isRead & 1;
4288 isData = ~isData & 1;
4289 }
4290
4291 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4292 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4293 DAG.getConstant(isData, dl, MVT::i32));
4294}
4295
4296static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4297 MachineFunction &MF = DAG.getMachineFunction();
4298 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4299
4300 // vastart just stores the address of the VarArgsFrameIndex slot into the
4301 // memory location argument.
4302 SDLoc dl(Op);
4303 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4304 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4305 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4306 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4307 MachinePointerInfo(SV));
4308}
4309
4310SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4311 CCValAssign &NextVA,
4312 SDValue &Root,
4313 SelectionDAG &DAG,
4314 const SDLoc &dl) const {
4315 MachineFunction &MF = DAG.getMachineFunction();
4316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4317
4318 const TargetRegisterClass *RC;
4319 if (AFI->isThumb1OnlyFunction())
4320 RC = &ARM::tGPRRegClass;
4321 else
4322 RC = &ARM::GPRRegClass;
4323
4324 // Transform the arguments stored in physical registers into virtual ones.
4325 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4326 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4327
4328 SDValue ArgValue2;
4329 if (NextVA.isMemLoc()) {
4330 MachineFrameInfo &MFI = MF.getFrameInfo();
4331 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4332
4333 // Create load node to retrieve arguments from the stack.
4334 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4335 ArgValue2 = DAG.getLoad(
4336 MVT::i32, dl, Root, FIN,
4337 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4338 } else {
4339 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4340 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4341 }
4342 if (!Subtarget->isLittle())
4343 std::swap (ArgValue, ArgValue2);
4344 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4345}
4346
4347// The remaining GPRs hold either the beginning of variable-argument
4348// data, or the beginning of an aggregate passed by value (usually
4349// byval). Either way, we allocate stack slots adjacent to the data
4350// provided by our caller, and store the unallocated registers there.
4351// If this is a variadic function, the va_list pointer will begin with
4352// these values; otherwise, this reassembles a (byval) structure that
4353// was split between registers and memory.
4354// Return: The frame index registers were stored into.
4355int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4356 const SDLoc &dl, SDValue &Chain,
4357 const Value *OrigArg,
4358 unsigned InRegsParamRecordIdx,
4359 int ArgOffset, unsigned ArgSize) const {
4360 // Currently, two use-cases possible:
4361 // Case #1. Non-var-args function, and we meet first byval parameter.
4362 // Setup first unallocated register as first byval register;
4363 // eat all remained registers
4364 // (these two actions are performed by HandleByVal method).
4365 // Then, here, we initialize stack frame with
4366 // "store-reg" instructions.
4367 // Case #2. Var-args function, that doesn't contain byval parameters.
4368 // The same: eat all remained unallocated registers,
4369 // initialize stack frame.
4370
4371 MachineFunction &MF = DAG.getMachineFunction();
4372 MachineFrameInfo &MFI = MF.getFrameInfo();
4373 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4374 unsigned RBegin, REnd;
4375 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4376 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4377 } else {
4378 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4379 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4380 REnd = ARM::R4;
4381 }
4382
4383 if (REnd != RBegin)
4384 ArgOffset = -4 * (ARM::R4 - RBegin);
4385
4386 auto PtrVT = getPointerTy(DAG.getDataLayout());
4387 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4388 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4389
4390 SmallVector<SDValue, 4> MemOps;
4391 const TargetRegisterClass *RC =
4392 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4393
4394 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4395 Register VReg = MF.addLiveIn(Reg, RC);
4396 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4397 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4398 MachinePointerInfo(OrigArg, 4 * i));
4399 MemOps.push_back(Store);
4400 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4401 }
4402
4403 if (!MemOps.empty())
4404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4405 return FrameIndex;
4406}
4407
4408// Setup stack frame, the va_list pointer will start from.
4409void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4410 const SDLoc &dl, SDValue &Chain,
4411 unsigned ArgOffset,
4412 unsigned TotalArgRegsSaveSize,
4413 bool ForceMutable) const {
4414 MachineFunction &MF = DAG.getMachineFunction();
4415 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4416
4417 // Try to store any remaining integer argument regs
4418 // to their spots on the stack so that they may be loaded by dereferencing
4419 // the result of va_next.
4420 // If there is no regs to be stored, just point address after last
4421 // argument passed via stack.
4422 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4423 CCInfo.getInRegsParamsCount(),
4424 CCInfo.getNextStackOffset(),
4425 std::max(4U, TotalArgRegsSaveSize));
4426 AFI->setVarArgsFrameIndex(FrameIndex);
4427}
4428
4429bool ARMTargetLowering::splitValueIntoRegisterParts(
4430 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4431 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
4432 EVT ValueVT = Val.getValueType();
4433 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) {
4434 unsigned ValueBits = ValueVT.getSizeInBits();
4435 unsigned PartBits = PartVT.getSizeInBits();
4436 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4437 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4438 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4439 Parts[0] = Val;
4440 return true;
4441 }
4442 return false;
4443}
4444
4445SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4446 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4447 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
4448 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) {
4449 unsigned ValueBits = ValueVT.getSizeInBits();
4450 unsigned PartBits = PartVT.getSizeInBits();
4451 SDValue Val = Parts[0];
4452
4453 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4454 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4455 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4456 return Val;
4457 }
4458 return SDValue();
4459}
4460
4461SDValue ARMTargetLowering::LowerFormalArguments(
4462 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4463 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4464 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4465 MachineFunction &MF = DAG.getMachineFunction();
4466 MachineFrameInfo &MFI = MF.getFrameInfo();
4467
4468 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4469
4470 // Assign locations to all of the incoming arguments.
4471 SmallVector<CCValAssign, 16> ArgLocs;
4472 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4473 *DAG.getContext());
4474 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4475
4476 SmallVector<SDValue, 16> ArgValues;
4477 SDValue ArgValue;
4478 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4479 unsigned CurArgIdx = 0;
4480
4481 // Initially ArgRegsSaveSize is zero.
4482 // Then we increase this value each time we meet byval parameter.
4483 // We also increase this value in case of varargs function.
4484 AFI->setArgRegsSaveSize(0);
4485
4486 // Calculate the amount of stack space that we need to allocate to store
4487 // byval and variadic arguments that are passed in registers.
4488 // We need to know this before we allocate the first byval or variadic
4489 // argument, as they will be allocated a stack slot below the CFA (Canonical
4490 // Frame Address, the stack pointer at entry to the function).
4491 unsigned ArgRegBegin = ARM::R4;
4492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4493 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4494 break;
4495
4496 CCValAssign &VA = ArgLocs[i];
4497 unsigned Index = VA.getValNo();
4498 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4499 if (!Flags.isByVal())
4500 continue;
4501
4502 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4502, __extension__
__PRETTY_FUNCTION__))
;
4503 unsigned RBegin, REnd;
4504 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4505 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4506
4507 CCInfo.nextInRegsParam();
4508 }
4509 CCInfo.rewindByValRegsInfo();
4510
4511 int lastInsIndex = -1;
4512 if (isVarArg && MFI.hasVAStart()) {
4513 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4514 if (RegIdx != std::size(GPRArgRegs))
4515 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4516 }
4517
4518 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4519 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4520 auto PtrVT = getPointerTy(DAG.getDataLayout());
4521
4522 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4523 CCValAssign &VA = ArgLocs[i];
4524 if (Ins[VA.getValNo()].isOrigArg()) {
4525 std::advance(CurOrigArg,
4526 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4527 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4528 }
4529 // Arguments stored in registers.
4530 if (VA.isRegLoc()) {
4531 EVT RegVT = VA.getLocVT();
4532
4533 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4534 // f64 and vector types are split up into multiple registers or
4535 // combinations of registers and stack slots.
4536 SDValue ArgValue1 =
4537 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4538 VA = ArgLocs[++i]; // skip ahead to next loc
4539 SDValue ArgValue2;
4540 if (VA.isMemLoc()) {
4541 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4542 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4543 ArgValue2 = DAG.getLoad(
4544 MVT::f64, dl, Chain, FIN,
4545 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4546 } else {
4547 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4548 }
4549 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4550 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4551 ArgValue1, DAG.getIntPtrConstant(0, dl));
4552 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4553 ArgValue2, DAG.getIntPtrConstant(1, dl));
4554 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4555 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4556 } else {
4557 const TargetRegisterClass *RC;
4558
4559 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4560 RC = &ARM::HPRRegClass;
4561 else if (RegVT == MVT::f32)
4562 RC = &ARM::SPRRegClass;
4563 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4564 RegVT == MVT::v4bf16)
4565 RC = &ARM::DPRRegClass;
4566 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4567 RegVT == MVT::v8bf16)
4568 RC = &ARM::QPRRegClass;
4569 else if (RegVT == MVT::i32)
4570 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4571 : &ARM::GPRRegClass;
4572 else
4573 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4573)
;
4574
4575 // Transform the arguments in physical registers into virtual ones.
4576 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4577 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4578
4579 // If this value is passed in r0 and has the returned attribute (e.g.
4580 // C++ 'structors), record this fact for later use.
4581 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4582 AFI->setPreservesR0();
4583 }
4584 }
4585
4586 // If this is an 8 or 16-bit value, it is really passed promoted
4587 // to 32 bits. Insert an assert[sz]ext to capture this, then
4588 // truncate to the right size.
4589 switch (VA.getLocInfo()) {
4590 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4590)
;
4591 case CCValAssign::Full: break;
4592 case CCValAssign::BCvt:
4593 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4594 break;
4595 case CCValAssign::SExt:
4596 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4597 DAG.getValueType(VA.getValVT()));
4598 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4599 break;
4600 case CCValAssign::ZExt:
4601 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4602 DAG.getValueType(VA.getValVT()));
4603 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4604 break;
4605 }
4606
4607 // f16 arguments have their size extended to 4 bytes and passed as if they
4608 // had been copied to the LSBs of a 32-bit register.
4609 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4610 if (VA.needsCustom() &&
4611 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4612 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4613
4614 InVals.push_back(ArgValue);
4615 } else { // VA.isRegLoc()
4616 // Only arguments passed on the stack should make it here.
4617 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
4617, __extension__ __PRETTY_FUNCTION__))
;
4618 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4618, __extension__
__PRETTY_FUNCTION__))
;
4619
4620 int index = VA.getValNo();
4621
4622 // Some Ins[] entries become multiple ArgLoc[] entries.
4623 // Process them only once.
4624 if (index != lastInsIndex)
4625 {
4626 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4627 // FIXME: For now, all byval parameter objects are marked mutable.
4628 // This can be changed with more analysis.
4629 // In case of tail call optimization mark all arguments mutable.
4630 // Since they could be overwritten by lowering of arguments in case of
4631 // a tail call.
4632 if (Flags.isByVal()) {
4633 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4634, __extension__
__PRETTY_FUNCTION__))
4634 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4634, __extension__
__PRETTY_FUNCTION__))
;
4635 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4636
4637 int FrameIndex = StoreByValRegs(
4638 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4639 VA.getLocMemOffset(), Flags.getByValSize());
4640 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4641 CCInfo.nextInRegsParam();
4642 } else {
4643 unsigned FIOffset = VA.getLocMemOffset();
4644 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4645 FIOffset, true);
4646
4647 // Create load nodes to retrieve arguments from the stack.
4648 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4649 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4650 MachinePointerInfo::getFixedStack(
4651 DAG.getMachineFunction(), FI)));
4652 }
4653 lastInsIndex = index;
4654 }
4655 }
4656 }
4657
4658 // varargs
4659 if (isVarArg && MFI.hasVAStart()) {
4660 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4661 TotalArgRegsSaveSize);
4662 if (AFI->isCmseNSEntryFunction()) {
4663 DiagnosticInfoUnsupported Diag(
4664 DAG.getMachineFunction().getFunction(),
4665 "secure entry function must not be variadic", dl.getDebugLoc());
4666 DAG.getContext()->diagnose(Diag);
4667 }
4668 }
4669
4670 unsigned StackArgSize = CCInfo.getNextStackOffset();
4671 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4672 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4673 // The only way to guarantee a tail call is if the callee restores its
4674 // argument area, but it must also keep the stack aligned when doing so.
4675 const DataLayout &DL = DAG.getDataLayout();
4676 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4677
4678 AFI->setArgumentStackToRestore(StackArgSize);
4679 }
4680 AFI->setArgumentStackSize(StackArgSize);
4681
4682 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4683 DiagnosticInfoUnsupported Diag(
4684 DAG.getMachineFunction().getFunction(),
4685 "secure entry function requires arguments on stack", dl.getDebugLoc());
4686 DAG.getContext()->diagnose(Diag);
4687 }
4688
4689 return Chain;
4690}
4691
4692/// isFloatingPointZero - Return true if this is +0.0.
4693static bool isFloatingPointZero(SDValue Op) {
4694 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4695 return CFP->getValueAPF().isPosZero();
4696 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4697 // Maybe this has already been legalized into the constant pool?
4698 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4699 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4700 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4701 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4702 return CFP->getValueAPF().isPosZero();
4703 }
4704 } else if (Op->getOpcode() == ISD::BITCAST &&
4705 Op->getValueType(0) == MVT::f64) {
4706 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4707 // created by LowerConstantFP().
4708 SDValue BitcastOp = Op->getOperand(0);
4709 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4710 isNullConstant(BitcastOp->getOperand(0)))
4711 return true;
4712 }
4713 return false;
4714}
4715
4716/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4717/// the given operands.
4718SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4719 SDValue &ARMcc, SelectionDAG &DAG,
4720 const SDLoc &dl) const {
4721 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4722 unsigned C = RHSC->getZExtValue();
4723 if (!isLegalICmpImmediate((int32_t)C)) {
4724 // Constant does not fit, try adjusting it by one.
4725 switch (CC) {
4726 default: break;
4727 case ISD::SETLT:
4728 case ISD::SETGE:
4729 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4730 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4731 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4732 }
4733 break;
4734 case ISD::SETULT:
4735 case ISD::SETUGE:
4736 if (C != 0 && isLegalICmpImmediate(C-1)) {
4737 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4738 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4739 }
4740 break;
4741 case ISD::SETLE:
4742 case ISD::SETGT:
4743 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4744 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4745 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4746 }
4747 break;
4748 case ISD::SETULE:
4749 case ISD::SETUGT:
4750 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4751 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4752 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4753 }
4754 break;
4755 }
4756 }
4757 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4758 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4759 // In ARM and Thumb-2, the compare instructions can shift their second
4760 // operand.
4761 CC = ISD::getSetCCSwappedOperands(CC);
4762 std::swap(LHS, RHS);
4763 }
4764
4765 // Thumb1 has very limited immediate modes, so turning an "and" into a
4766 // shift can save multiple instructions.
4767 //
4768 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4769 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4770 // own. If it's the operand to an unsigned comparison with an immediate,
4771 // we can eliminate one of the shifts: we transform
4772 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4773 //
4774 // We avoid transforming cases which aren't profitable due to encoding
4775 // details:
4776 //
4777 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4778 // would not; in that case, we're essentially trading one immediate load for
4779 // another.
4780 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4781 // 3. C2 is zero; we have other code for this special case.
4782 //
4783 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4784 // instruction, since the AND is always one instruction anyway, but we could
4785 // use narrow instructions in some cases.
4786 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4787 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4788 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4789 !isSignedIntSetCC(CC)) {
4790 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4791 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4792 uint64_t RHSV = RHSC->getZExtValue();
4793 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4794 unsigned ShiftBits = llvm::countl_zero(Mask);
4795 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4796 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4797 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4798 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4799 }
4800 }
4801 }
4802
4803 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4804 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4805 // way a cmp would.
4806 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4807 // some tweaks to the heuristics for the previous and->shift transform.
4808 // FIXME: Optimize cases where the LHS isn't a shift.
4809 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4810 isa<ConstantSDNode>(RHS) &&
4811 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4812 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4813 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4814 unsigned ShiftAmt =
4815 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4816 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4817 DAG.getVTList(MVT::i32, MVT::i32),
4818 LHS.getOperand(0),
4819 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4820 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4821 Shift.getValue(1), SDValue());
4822 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4823 return Chain.getValue(1);
4824 }
4825
4826 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4827
4828 // If the RHS is a constant zero then the V (overflow) flag will never be
4829 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4830 // simpler for other passes (like the peephole optimiser) to deal with.
4831 if (isNullConstant(RHS)) {
4832 switch (CondCode) {
4833 default: break;
4834 case ARMCC::GE:
4835 CondCode = ARMCC::PL;
4836 break;
4837 case ARMCC::LT:
4838 CondCode = ARMCC::MI;
4839 break;
4840 }
4841 }
4842
4843 ARMISD::NodeType CompareType;
4844 switch (CondCode) {
4845 default:
4846 CompareType = ARMISD::CMP;
4847 break;
4848 case ARMCC::EQ:
4849 case ARMCC::NE:
4850 // Uses only Z Flag
4851 CompareType = ARMISD::CMPZ;
4852 break;
4853 }
4854 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4855 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4856}
4857
4858/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4859SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4860 SelectionDAG &DAG, const SDLoc &dl,
4861 bool Signaling) const {
4862 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4862, __extension__
__PRETTY_FUNCTION__))
;
4863 SDValue Cmp;
4864 if (!isFloatingPointZero(RHS))
4865 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4866 dl, MVT::Glue, LHS, RHS);
4867 else
4868 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4869 dl, MVT::Glue, LHS);
4870 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4871}
4872
4873/// duplicateCmp - Glue values can have only one use, so this function
4874/// duplicates a comparison node.
4875SDValue
4876ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4877 unsigned Opc = Cmp.getOpcode();
4878 SDLoc DL(Cmp);
4879 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4880 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4881
4882 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4882, __extension__
__PRETTY_FUNCTION__))
;
4883 Cmp = Cmp.getOperand(0);
4884 Opc = Cmp.getOpcode();
4885 if (Opc == ARMISD::CMPFP)
4886 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4887 else {
4888 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4888, __extension__
__PRETTY_FUNCTION__))
;
4889 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4890 }
4891 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4892}
4893
4894// This function returns three things: the arithmetic computation itself
4895// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4896// comparison and the condition code define the case in which the arithmetic
4897// computation *does not* overflow.
4898std::pair<SDValue, SDValue>
4899ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4900 SDValue &ARMcc) const {
4901 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4901, __extension__
__PRETTY_FUNCTION__))
;
4902
4903 SDValue Value, OverflowCmp;
4904 SDValue LHS = Op.getOperand(0);
4905 SDValue RHS = Op.getOperand(1);
4906 SDLoc dl(Op);
4907
4908 // FIXME: We are currently always generating CMPs because we don't support
4909 // generating CMN through the backend. This is not as good as the natural
4910 // CMP case because it causes a register dependency and cannot be folded
4911 // later.
4912
4913 switch (Op.getOpcode()) {
4914 default:
4915 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4915)
;
4916 case ISD::SADDO:
4917 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4918 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4919 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4920 break;
4921 case ISD::UADDO:
4922 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4923 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4924 // We do not use it in the USUBO case as Value may not be used.
4925 Value = DAG.getNode(ARMISD::ADDC, dl,
4926 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4927 .getValue(0);
4928 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4929 break;
4930 case ISD::SSUBO:
4931 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4932 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4933 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4934 break;
4935 case ISD::USUBO:
4936 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4937 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4938 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4939 break;
4940 case ISD::UMULO:
4941 // We generate a UMUL_LOHI and then check if the high word is 0.
4942 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4943 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4944 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4945 LHS, RHS);
4946 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4947 DAG.getConstant(0, dl, MVT::i32));
4948 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4949 break;
4950 case ISD::SMULO:
4951 // We generate a SMUL_LOHI and then check if all the bits of the high word
4952 // are the same as the sign bit of the low word.
4953 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4954 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4955 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4956 LHS, RHS);
4957 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4958 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4959 Value.getValue(0),
4960 DAG.getConstant(31, dl, MVT::i32)));
4961 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4962 break;
4963 } // switch (...)
4964
4965 return std::make_pair(Value, OverflowCmp);
4966}
4967
4968SDValue
4969ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4970 // Let legalize expand this if it isn't a legal type yet.
4971 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4972 return SDValue();
4973
4974 SDValue Value, OverflowCmp;
4975 SDValue ARMcc;
4976 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4977 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4978 SDLoc dl(Op);
4979 // We use 0 and 1 as false and true values.
4980 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4981 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4982 EVT VT = Op.getValueType();
4983
4984 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4985 ARMcc, CCR, OverflowCmp);
4986
4987 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4988 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4989}
4990
4991static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4992 SelectionDAG &DAG) {
4993 SDLoc DL(BoolCarry);
4994 EVT CarryVT = BoolCarry.getValueType();
4995
4996 // This converts the boolean value carry into the carry flag by doing
4997 // ARMISD::SUBC Carry, 1
4998 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4999 DAG.getVTList(CarryVT, MVT::i32),
5000 BoolCarry, DAG.getConstant(1, DL, CarryVT));
5001 return Carry.getValue(1);
5002}
5003
5004static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
5005 SelectionDAG &DAG) {
5006 SDLoc DL(Flags);
5007
5008 // Now convert the carry flag into a boolean carry. We do this
5009 // using ARMISD:ADDE 0, 0, Carry
5010 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
5011 DAG.getConstant(0, DL, MVT::i32),
5012 DAG.getConstant(0, DL, MVT::i32), Flags);
5013}
5014
5015SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
5016 SelectionDAG &DAG) const {
5017 // Let legalize expand this if it isn't a legal type yet.
5018 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
5019 return SDValue();
5020
5021 SDValue LHS = Op.getOperand(0);
5022 SDValue RHS = Op.getOperand(1);
5023 SDLoc dl(Op);
5024
5025 EVT VT = Op.getValueType();
5026 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5027 SDValue Value;
5028 SDValue Overflow;
5029 switch (Op.getOpcode()) {
5030 default:
5031 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5031)
;
5032 case ISD::UADDO:
5033 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
5034 // Convert the carry flag into a boolean value.
5035 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5036 break;
5037 case ISD::USUBO: {
5038 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
5039 // Convert the carry flag into a boolean value.
5040 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5041 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
5042 // value. So compute 1 - C.
5043 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
5044 DAG.getConstant(1, dl, MVT::i32), Overflow);
5045 break;
5046 }
5047 }
5048
5049 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5050}
5051
5052static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
5053 const ARMSubtarget *Subtarget) {
5054 EVT VT = Op.getValueType();
5055 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP() || Subtarget->isThumb1Only())
3
Assuming the condition is false
4
Assuming the condition is false
5
Taking false branch
5056 return SDValue();
5057 if (!VT.isSimple())
6
Taking false branch
5058 return SDValue();
5059
5060 unsigned NewOpcode;
7
'NewOpcode' declared without an initial value
5061 switch (VT.getSimpleVT().SimpleTy) {
8
Control jumps to 'case i16:' at line 5080
5062 default:
5063 return SDValue();
5064 case MVT::i8:
5065 switch (Op->getOpcode()) {
5066 case ISD::UADDSAT:
5067 NewOpcode = ARMISD::UQADD8b;
5068 break;
5069 case ISD::SADDSAT:
5070 NewOpcode = ARMISD::QADD8b;
5071 break;
5072 case ISD::USUBSAT:
5073 NewOpcode = ARMISD::UQSUB8b;
5074 break;
5075 case ISD::SSUBSAT:
5076 NewOpcode = ARMISD::QSUB8b;
5077 break;
5078 }
5079 break;
5080 case MVT::i16:
5081 switch (Op->getOpcode()) {
9
'Default' branch taken. Execution continues on line 5095
5082 case ISD::UADDSAT:
5083 NewOpcode = ARMISD::UQADD16b;
5084 break;
5085 case ISD::SADDSAT:
5086 NewOpcode = ARMISD::QADD16b;
5087 break;
5088 case ISD::USUBSAT:
5089 NewOpcode = ARMISD::UQSUB16b;
5090 break;
5091 case ISD::SSUBSAT:
5092 NewOpcode = ARMISD::QSUB16b;
5093 break;
5094 }
5095 break;
10
Execution continues on line 5098
5096 }
5097
5098 SDLoc dl(Op);
5099 SDValue Add =
5100 DAG.getNode(NewOpcode, dl, MVT::i32,
11
1st function call argument is an uninitialized value
5101 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5102 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5103 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5104}
5105
5106SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5107 SDValue Cond = Op.getOperand(0);
5108 SDValue SelectTrue = Op.getOperand(1);
5109 SDValue SelectFalse = Op.getOperand(2);
5110 SDLoc dl(Op);
5111 unsigned Opc = Cond.getOpcode();
5112
5113 if (Cond.getResNo() == 1 &&
5114 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5115 Opc == ISD::USUBO)) {
5116 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5117 return SDValue();
5118
5119 SDValue Value, OverflowCmp;
5120 SDValue ARMcc;
5121 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5122 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5123 EVT VT = Op.getValueType();
5124
5125 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5126 OverflowCmp, DAG);
5127 }
5128
5129 // Convert:
5130 //
5131 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5132 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5133 //
5134 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5135 const ConstantSDNode *CMOVTrue =
5136 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5137 const ConstantSDNode *CMOVFalse =
5138 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5139
5140 if (CMOVTrue && CMOVFalse) {
5141 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5142 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5143
5144 SDValue True;
5145 SDValue False;
5146 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5147 True = SelectTrue;
5148 False = SelectFalse;
5149 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5150 True = SelectFalse;
5151 False = SelectTrue;
5152 }
5153
5154 if (True.getNode() && False.getNode()) {
5155 EVT VT = Op.getValueType();
5156 SDValue ARMcc = Cond.getOperand(2);
5157 SDValue CCR = Cond.getOperand(3);
5158 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5159 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5159, __extension__ __PRETTY_FUNCTION__))
;
5160 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5161 }
5162 }
5163 }
5164
5165 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5166 // undefined bits before doing a full-word comparison with zero.
5167 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5168 DAG.getConstant(1, dl, Cond.getValueType()));
5169
5170 return DAG.getSelectCC(dl, Cond,
5171 DAG.getConstant(0, dl, Cond.getValueType()),
5172 SelectTrue, SelectFalse, ISD::SETNE);
5173}
5174
5175static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5176 bool &swpCmpOps, bool &swpVselOps) {
5177 // Start by selecting the GE condition code for opcodes that return true for
5178 // 'equality'
5179 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5180 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5181 CondCode = ARMCC::GE;
5182
5183 // and GT for opcodes that return false for 'equality'.
5184 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5185 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5186 CondCode = ARMCC::GT;
5187
5188 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5189 // to swap the compare operands.
5190 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5191 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5192 swpCmpOps = true;
5193
5194 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5195 // If we have an unordered opcode, we need to swap the operands to the VSEL
5196 // instruction (effectively negating the condition).
5197 //
5198 // This also has the effect of swapping which one of 'less' or 'greater'
5199 // returns true, so we also swap the compare operands. It also switches
5200 // whether we return true for 'equality', so we compensate by picking the
5201 // opposite condition code to our original choice.
5202 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5203 CC == ISD::SETUGT) {
5204 swpCmpOps = !swpCmpOps;
5205 swpVselOps = !swpVselOps;
5206 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5207 }
5208
5209 // 'ordered' is 'anything but unordered', so use the VS condition code and
5210 // swap the VSEL operands.
5211 if (CC == ISD::SETO) {
5212 CondCode = ARMCC::VS;
5213 swpVselOps = true;
5214 }
5215
5216 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5217 // code and swap the VSEL operands. Also do this if we don't care about the
5218 // unordered case.
5219 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5220 CondCode = ARMCC::EQ;
5221 swpVselOps = true;
5222 }
5223}
5224
5225SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5226 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5227 SDValue Cmp, SelectionDAG &DAG) const {
5228 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5229 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5230 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5231 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5232 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5233
5234 SDValue TrueLow = TrueVal.getValue(0);
5235 SDValue TrueHigh = TrueVal.getValue(1);
5236 SDValue FalseLow = FalseVal.getValue(0);
5237 SDValue FalseHigh = FalseVal.getValue(1);
5238
5239 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5240 ARMcc, CCR, Cmp);
5241 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5242 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5243
5244 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5245 } else {
5246 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5247 Cmp);
5248 }
5249}
5250
5251static bool isGTorGE(ISD::CondCode CC) {
5252 return CC == ISD::SETGT || CC == ISD::SETGE;
5253}
5254
5255static bool isLTorLE(ISD::CondCode CC) {
5256 return CC == ISD::SETLT || CC == ISD::SETLE;
5257}
5258
5259// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5260// All of these conditions (and their <= and >= counterparts) will do:
5261// x < k ? k : x
5262// x > k ? x : k
5263// k < x ? x : k
5264// k > x ? k : x
5265static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5266 const SDValue TrueVal, const SDValue FalseVal,
5267 const ISD::CondCode CC, const SDValue K) {
5268 return (isGTorGE(CC) &&
5269 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5270 (isLTorLE(CC) &&
5271 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5272}
5273
5274// Check if two chained conditionals could be converted into SSAT or USAT.
5275//
5276// SSAT can replace a set of two conditional selectors that bound a number to an
5277// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5278//
5279// x < -k ? -k : (x > k ? k : x)
5280// x < -k ? -k : (x < k ? x : k)
5281// x > -k ? (x > k ? k : x) : -k
5282// x < k ? (x < -k ? -k : x) : k
5283// etc.
5284//
5285// LLVM canonicalizes these to either a min(max()) or a max(min())
5286// pattern. This function tries to match one of these and will return a SSAT
5287// node if successful.
5288//
5289// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5290// is a power of 2.
5291static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5292 EVT VT = Op.getValueType();
5293 SDValue V1 = Op.getOperand(0);
5294 SDValue K1 = Op.getOperand(1);
5295 SDValue TrueVal1 = Op.getOperand(2);
5296 SDValue FalseVal1 = Op.getOperand(3);
5297 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5298
5299 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5300 if (Op2.getOpcode() != ISD::SELECT_CC)
5301 return SDValue();
5302
5303 SDValue V2 = Op2.getOperand(0);
5304 SDValue K2 = Op2.getOperand(1);
5305 SDValue TrueVal2 = Op2.getOperand(2);
5306 SDValue FalseVal2 = Op2.getOperand(3);
5307 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5308
5309 SDValue V1Tmp = V1;
5310 SDValue V2Tmp = V2;
5311
5312 // Check that the registers and the constants match a max(min()) or min(max())
5313 // pattern
5314 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5315 K2 != FalseVal2 ||
5316 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5317 return SDValue();
5318
5319 // Check that the constant in the lower-bound check is
5320 // the opposite of the constant in the upper-bound check
5321 // in 1's complement.
5322 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5323 return SDValue();
5324
5325 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5326 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5327 int64_t PosVal = std::max(Val1, Val2);
5328 int64_t NegVal = std::min(Val1, Val2);
5329
5330 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5331 !isPowerOf2_64(PosVal + 1))
5332 return SDValue();
5333
5334 // Handle the difference between USAT (unsigned) and SSAT (signed)
5335 // saturation
5336 // At this point, PosVal is guaranteed to be positive
5337 uint64_t K = PosVal;
5338 SDLoc dl(Op);
5339 if (Val1 == ~Val2)
5340 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5341 DAG.getConstant(llvm::countr_one(K), dl, VT));
5342 if (NegVal == 0)
5343 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5344 DAG.getConstant(llvm::countr_one(K), dl, VT));
5345
5346 return SDValue();
5347}
5348
5349// Check if a condition of the type x < k ? k : x can be converted into a
5350// bit operation instead of conditional moves.
5351// Currently this is allowed given:
5352// - The conditions and values match up
5353// - k is 0 or -1 (all ones)
5354// This function will not check the last condition, thats up to the caller
5355// It returns true if the transformation can be made, and in such case
5356// returns x in V, and k in SatK.
5357static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5358 SDValue &SatK)
5359{
5360 SDValue LHS = Op.getOperand(0);
5361 SDValue RHS = Op.getOperand(1);
5362 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5363 SDValue TrueVal = Op.getOperand(2);
5364 SDValue FalseVal = Op.getOperand(3);
5365
5366 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5367 ? &RHS
5368 : nullptr;
5369
5370 // No constant operation in comparison, early out
5371 if (!K)
5372 return false;
5373
5374 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5375 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5376 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5377
5378 // If the constant on left and right side, or variable on left and right,
5379 // does not match, early out
5380 if (*K != KTmp || V != VTmp)
5381 return false;
5382
5383 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5384 SatK = *K;
5385 return true;
5386 }
5387
5388 return false;
5389}
5390
5391bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5392 if (VT == MVT::f32)
5393 return !Subtarget->hasVFP2Base();
5394 if (VT == MVT::f64)
5395 return !Subtarget->hasFP64();
5396 if (VT == MVT::f16)
5397 return !Subtarget->hasFullFP16();
5398 return false;
5399}
5400
5401SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5402 EVT VT = Op.getValueType();
5403 SDLoc dl(Op);
5404
5405 // Try to convert two saturating conditional selects into a single SSAT
5406 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5407 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5408 return SatValue;
5409
5410 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5411 // into more efficient bit operations, which is possible when k is 0 or -1
5412 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5413 // single instructions. On Thumb the shift and the bit operation will be two
5414 // instructions.
5415 // Only allow this transformation on full-width (32-bit) operations
5416 SDValue LowerSatConstant;
5417 SDValue SatValue;
5418 if (VT == MVT::i32 &&
5419 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5420 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5421 DAG.getConstant(31, dl, VT));
5422 if (isNullConstant(LowerSatConstant)) {
5423 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5424 DAG.getAllOnesConstant(dl, VT));
5425 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5426 } else if (isAllOnesConstant(LowerSatConstant))
5427 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5428 }
5429
5430 SDValue LHS = Op.getOperand(0);
5431 SDValue RHS = Op.getOperand(1);
5432 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5433 SDValue TrueVal = Op.getOperand(2);
5434 SDValue FalseVal = Op.getOperand(3);
5435 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5436 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5437
5438 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5439 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5440 unsigned TVal = CTVal->getZExtValue();
5441 unsigned FVal = CFVal->getZExtValue();
5442 unsigned Opcode = 0;
5443
5444 if (TVal == ~FVal) {
5445 Opcode = ARMISD::CSINV;
5446 } else if (TVal == ~FVal + 1) {
5447 Opcode = ARMISD::CSNEG;
5448 } else if (TVal + 1 == FVal) {
5449 Opcode = ARMISD::CSINC;
5450 } else if (TVal == FVal + 1) {
5451 Opcode = ARMISD::CSINC;
5452 std::swap(TrueVal, FalseVal);
5453 std::swap(TVal, FVal);
5454 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5455 }
5456
5457 if (Opcode) {
5458 // If one of the constants is cheaper than another, materialise the
5459 // cheaper one and let the csel generate the other.
5460 if (Opcode != ARMISD::CSINC &&
5461 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5462 std::swap(TrueVal, FalseVal);
5463 std::swap(TVal, FVal);
5464 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5465 }
5466
5467 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5468 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5469 // -(-a) == a, but (a+1)+1 != a).
5470 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5471 std::swap(TrueVal, FalseVal);
5472 std::swap(TVal, FVal);
5473 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5474 }
5475
5476 // Drops F's value because we can get it by inverting/negating TVal.
5477 FalseVal = TrueVal;
5478
5479 SDValue ARMcc;
5480 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5481 EVT VT = TrueVal.getValueType();
5482 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5483 }
5484 }
5485
5486 if (isUnsupportedFloatingType(LHS.getValueType())) {
5487 DAG.getTargetLoweringInfo().softenSetCCOperands(
5488 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5489
5490 // If softenSetCCOperands only returned one value, we should compare it to
5491 // zero.
5492 if (!RHS.getNode()) {
5493 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5494 CC = ISD::SETNE;
5495 }
5496 }
5497
5498 if (LHS.getValueType() == MVT::i32) {
5499 // Try to generate VSEL on ARMv8.
5500 // The VSEL instruction can't use all the usual ARM condition
5501 // codes: it only has two bits to select the condition code, so it's
5502 // constrained to use only GE, GT, VS and EQ.
5503 //
5504 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5505 // swap the operands of the previous compare instruction (effectively
5506 // inverting the compare condition, swapping 'less' and 'greater') and
5507 // sometimes need to swap the operands to the VSEL (which inverts the
5508 // condition in the sense of firing whenever the previous condition didn't)
5509 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5510 TrueVal.getValueType() == MVT::f32 ||
5511 TrueVal.getValueType() == MVT::f64)) {
5512 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5513 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5514 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5515 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5516 std::swap(TrueVal, FalseVal);
5517 }
5518 }
5519
5520 SDValue ARMcc;
5521 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5522 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5523 // Choose GE over PL, which vsel does now support
5524 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5525 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5526 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5527 }
5528
5529 ARMCC::CondCodes CondCode, CondCode2;
5530 FPCCToARMCC(CC, CondCode, CondCode2);
5531
5532 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5533 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5534 // must use VSEL (limited condition codes), due to not having conditional f16
5535 // moves.
5536 if (Subtarget->hasFPARMv8Base() &&
5537 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5538 (TrueVal.getValueType() == MVT::f16 ||
5539 TrueVal.getValueType() == MVT::f32 ||
5540 TrueVal.getValueType() == MVT::f64)) {
5541 bool swpCmpOps = false;
5542 bool swpVselOps = false;
5543 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5544
5545 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5546 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5547 if (swpCmpOps)
5548 std::swap(LHS, RHS);
5549 if (swpVselOps)
5550 std::swap(TrueVal, FalseVal);
5551 }
5552 }
5553
5554 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5555 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5556 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5557 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5558 if (CondCode2 != ARMCC::AL) {
5559 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5560 // FIXME: Needs another CMP because flag can have but one use.
5561 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5562 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5563 }
5564 return Result;
5565}
5566
5567/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5568/// to morph to an integer compare sequence.
5569static bool canChangeToInt(SDValue Op, bool &SeenZero,
5570 const ARMSubtarget *Subtarget) {
5571 SDNode *N = Op.getNode();
5572 if (!N->hasOneUse())
5573 // Otherwise it requires moving the value from fp to integer registers.
5574 return false;
5575 if (!N->getNumValues())
5576 return false;
5577 EVT VT = Op.getValueType();
5578 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5579 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5580 // vmrs are very slow, e.g. cortex-a8.
5581 return false;
5582
5583 if (isFloatingPointZero(Op)) {
5584 SeenZero = true;
5585 return true;
5586 }
5587 return ISD::isNormalLoad(N);
5588}
5589
5590static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5591 if (isFloatingPointZero(Op))
5592 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5593
5594 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5595 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5596 Ld->getPointerInfo(), Ld->getAlign(),
5597 Ld->getMemOperand()->getFlags());
5598
5599 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5599)
;
5600}
5601
5602static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5603 SDValue &RetVal1, SDValue &RetVal2) {
5604 SDLoc dl(Op);
5605
5606 if (isFloatingPointZero(Op)) {
5607 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5608 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5609 return;
5610 }
5611
5612 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5613 SDValue Ptr = Ld->getBasePtr();
5614 RetVal1 =
5615 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5616 Ld->getAlign(), Ld->getMemOperand()->getFlags());
5617
5618 EVT PtrType = Ptr.getValueType();
5619 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5620 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5621 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5622 Ld->getPointerInfo().getWithOffset(4),
5623 commonAlignment(Ld->getAlign(), 4),
5624 Ld->getMemOperand()->getFlags());
5625 return;
5626 }
5627
5628 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5628)
;
5629}
5630
5631/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5632/// f32 and even f64 comparisons to integer ones.
5633SDValue
5634ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5635 SDValue Chain = Op.getOperand(0);
5636 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5637 SDValue LHS = Op.getOperand(2);
5638 SDValue RHS = Op.getOperand(3);
5639 SDValue Dest = Op.getOperand(4);
5640 SDLoc dl(Op);
5641
5642 bool LHSSeenZero = false;
5643 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5644 bool RHSSeenZero = false;
5645 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5646 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5647 // If unsafe fp math optimization is enabled and there are no other uses of
5648 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5649 // to an integer comparison.
5650 if (CC == ISD::SETOEQ)
5651 CC = ISD::SETEQ;
5652 else if (CC == ISD::SETUNE)
5653 CC = ISD::SETNE;
5654
5655 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5656 SDValue ARMcc;
5657 if (LHS.getValueType() == MVT::f32) {
5658 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5659 bitcastf32Toi32(LHS, DAG), Mask);
5660 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5661 bitcastf32Toi32(RHS, DAG), Mask);
5662 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5663 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5664 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5665 Chain, Dest, ARMcc, CCR, Cmp);
5666 }
5667
5668 SDValue LHS1, LHS2;
5669 SDValue RHS1, RHS2;
5670 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5671 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5672 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5673 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5674 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5675 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5676 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5677 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5678 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5679 }
5680
5681 return SDValue();
5682}
5683
5684SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5685 SDValue Chain = Op.getOperand(0);
5686 SDValue Cond = Op.getOperand(1);
5687 SDValue Dest = Op.getOperand(2);
5688 SDLoc dl(Op);
5689
5690 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5691 // instruction.
5692 unsigned Opc = Cond.getOpcode();
5693 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5694 !Subtarget->isThumb1Only();
5695 if (Cond.getResNo() == 1 &&
5696 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5697 Opc == ISD::USUBO || OptimizeMul)) {
5698 // Only lower legal XALUO ops.
5699 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5700 return SDValue();
5701
5702 // The actual operation with overflow check.
5703 SDValue Value, OverflowCmp;
5704 SDValue ARMcc;
5705 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5706
5707 // Reverse the condition code.
5708 ARMCC::CondCodes CondCode =
5709 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5710 CondCode = ARMCC::getOppositeCondition(CondCode);
5711 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5712 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5713
5714 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5715 OverflowCmp);
5716 }
5717
5718 return SDValue();
5719}
5720
5721SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5722 SDValue Chain = Op.getOperand(0);
5723 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5724 SDValue LHS = Op.getOperand(2);
5725 SDValue RHS = Op.getOperand(3);
5726 SDValue Dest = Op.getOperand(4);
5727 SDLoc dl(Op);
5728
5729 if (isUnsupportedFloatingType(LHS.getValueType())) {
5730 DAG.getTargetLoweringInfo().softenSetCCOperands(
5731 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5732
5733 // If softenSetCCOperands only returned one value, we should compare it to
5734 // zero.
5735 if (!RHS.getNode()) {
5736 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5737 CC = ISD::SETNE;
5738 }
5739 }
5740
5741 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5742 // instruction.
5743 unsigned Opc = LHS.getOpcode();
5744 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5745 !Subtarget->isThumb1Only();
5746 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5747 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5748 Opc == ISD::USUBO || OptimizeMul) &&
5749 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5750 // Only lower legal XALUO ops.
5751 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5752 return SDValue();
5753
5754 // The actual operation with overflow check.
5755 SDValue Value, OverflowCmp;
5756 SDValue ARMcc;
5757 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5758
5759 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5760 // Reverse the condition code.
5761 ARMCC::CondCodes CondCode =
5762 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5763 CondCode = ARMCC::getOppositeCondition(CondCode);
5764 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5765 }
5766 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5767
5768 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5769 OverflowCmp);
5770 }
5771
5772 if (LHS.getValueType() == MVT::i32) {
5773 SDValue ARMcc;
5774 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5775 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5776 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5777 Chain, Dest, ARMcc, CCR, Cmp);
5778 }
5779
5780 if (getTargetMachine().Options.UnsafeFPMath &&
5781 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5782 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5783 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5784 return Result;
5785 }
5786
5787 ARMCC::CondCodes CondCode, CondCode2;
5788 FPCCToARMCC(CC, CondCode, CondCode2);
5789
5790 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5791 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5792 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5793 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5794 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5795 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5796 if (CondCode2 != ARMCC::AL) {
5797 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5798 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5799 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5800 }
5801 return Res;
5802}
5803
5804SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5805 SDValue Chain = Op.getOperand(0);
5806 SDValue Table = Op.getOperand(1);
5807 SDValue Index = Op.getOperand(2);
5808 SDLoc dl(Op);
5809
5810 EVT PTy = getPointerTy(DAG.getDataLayout());
5811 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5812 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5813 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5814 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5815 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5816 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5817 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5818 // which does another jump to the destination. This also makes it easier
5819 // to translate it to TBB / TBH later (Thumb2 only).
5820 // FIXME: This might not work if the function is extremely large.
5821 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5822 Addr, Op.getOperand(2), JTI);
5823 }
5824 if (isPositionIndependent() || Subtarget->isROPI()) {
5825 Addr =
5826 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5827 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5828 Chain = Addr.getValue(1);
5829 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5830 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5831 } else {
5832 Addr =
5833 DAG.getLoad(PTy, dl, Chain, Addr,
5834 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5835 Chain = Addr.getValue(1);
5836 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5837 }
5838}
5839
5840static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5841 EVT VT = Op.getValueType();
5842 SDLoc dl(Op);
5843
5844 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5845 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5846 return Op;
5847 return DAG.UnrollVectorOp(Op.getNode());
5848 }
5849
5850 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5851
5852 EVT NewTy;
5853 const EVT OpTy = Op.getOperand(0).getValueType();
5854 if (OpTy == MVT::v4f32)
5855 NewTy = MVT::v4i32;
5856 else if (OpTy == MVT::v4f16 && HasFullFP16)
5857 NewTy = MVT::v4i16;
5858 else if (OpTy == MVT::v8f16 && HasFullFP16)
5859 NewTy = MVT::v8i16;
5860 else
5861 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5861)
;
5862
5863 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5864 return DAG.UnrollVectorOp(Op.getNode());
5865
5866 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5867 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5868}
5869
5870SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5871 EVT VT = Op.getValueType();
5872 if (VT.isVector())
5873 return LowerVectorFP_TO_INT(Op, DAG);
5874
5875 bool IsStrict = Op->isStrictFPOpcode();
5876 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5877
5878 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5879 RTLIB::Libcall LC;
5880 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5881 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5882 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5883 Op.getValueType());
5884 else
5885 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5886 Op.getValueType());
5887 SDLoc Loc(Op);
5888 MakeLibCallOptions CallOptions;
5889 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5890 SDValue Result;
5891 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5892 CallOptions, Loc, Chain);
5893 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5894 }
5895
5896 // FIXME: Remove this when we have strict fp instruction selection patterns
5897 if (IsStrict) {
5898 SDLoc Loc(Op);
5899 SDValue Result =
5900 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5901 : ISD::FP_TO_UINT,
5902 Loc, Op.getValueType(), SrcVal);
5903 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5904 }
5905
5906 return Op;
5907}
5908
5909static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
5910 const ARMSubtarget *Subtarget) {
5911 EVT VT = Op.getValueType();
5912 EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5913 EVT FromVT = Op.getOperand(0).getValueType();
5914
5915 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f32)
5916 return Op;
5917 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f64 &&
5918 Subtarget->hasFP64())
5919 return Op;
5920 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f16 &&
5921 Subtarget->hasFullFP16())
5922 return Op;
5923 if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32 &&
5924 Subtarget->hasMVEFloatOps())
5925 return Op;
5926 if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16 &&
5927 Subtarget->hasMVEFloatOps())
5928 return Op;
5929
5930 if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
5931 return SDValue();
5932
5933 SDLoc DL(Op);
5934 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
5935 unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
5936 SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
5937 DAG.getValueType(VT.getScalarType()));
5938 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
5939 DAG.getConstant((1 << BW) - 1, DL, VT));
5940 if (IsSigned)
5941 Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
5942 DAG.getConstant(-(1 << BW), DL, VT));
5943 return Max;
5944}
5945
5946static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5947 EVT VT = Op.getValueType();
5948 SDLoc dl(Op);
5949
5950 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5951 if (VT.getVectorElementType() == MVT::f32)
5952 return Op;
5953 return DAG.UnrollVectorOp(Op.getNode());
5954 }
5955
5956 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5958, __extension__
__PRETTY_FUNCTION__))
5957 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5958, __extension__
__PRETTY_FUNCTION__))
5958 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5958, __extension__
__PRETTY_FUNCTION__))
;
5959
5960 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5961
5962 EVT DestVecType;
5963 if (VT == MVT::v4f32)
5964 DestVecType = MVT::v4i32;
5965 else if (VT == MVT::v4f16 && HasFullFP16)
5966 DestVecType = MVT::v4i16;
5967 else if (VT == MVT::v8f16 && HasFullFP16)
5968 DestVecType = MVT::v8i16;
5969 else
5970 return DAG.UnrollVectorOp(Op.getNode());
5971
5972 unsigned CastOpc;
5973 unsigned Opc;
5974 switch (Op.getOpcode()) {
5975 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5975)
;
5976 case ISD::SINT_TO_FP:
5977 CastOpc = ISD::SIGN_EXTEND;
5978 Opc = ISD::SINT_TO_FP;
5979 break;
5980 case ISD::UINT_TO_FP:
5981 CastOpc = ISD::ZERO_EXTEND;
5982 Opc = ISD::UINT_TO_FP;
5983 break;
5984 }
5985
5986 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5987 return DAG.getNode(Opc, dl, VT, Op);
5988}
5989
5990SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5991 EVT VT = Op.getValueType();
5992 if (VT.isVector())
5993 return LowerVectorINT_TO_FP(Op, DAG);
5994 if (isUnsupportedFloatingType(VT)) {
5995 RTLIB::Libcall LC;
5996 if (Op.getOpcode() == ISD::SINT_TO_FP)
5997 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5998 Op.getValueType());
5999 else
6000 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
6001 Op.getValueType());
6002 MakeLibCallOptions CallOptions;
6003 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
6004 CallOptions, SDLoc(Op)).first;
6005 }
6006
6007 return Op;
6008}
6009
6010SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6011 // Implement fcopysign with a fabs and a conditional fneg.
6012 SDValue Tmp0 = Op.getOperand(0);
6013 SDValue Tmp1 = Op.getOperand(1);
6014 SDLoc dl(Op);
6015 EVT VT = Op.getValueType();
6016 EVT SrcVT = Tmp1.getValueType();
6017 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
6018 Tmp0.getOpcode() == ARMISD::VMOVDRR;
6019 bool UseNEON = !InGPR && Subtarget->hasNEON();
6020
6021 if (UseNEON) {
6022 // Use VBSL to copy the sign bit.
6023 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
6024 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
6025 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
6026 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
6027 if (VT == MVT::f64)
6028 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
6029 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
6030 DAG.getConstant(32, dl, MVT::i32));
6031 else /*if (VT == MVT::f32)*/
6032 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
6033 if (SrcVT == MVT::f32) {
6034 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
6035 if (VT == MVT::f64)
6036 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,