Bug Summary

File:build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 5074, column 7
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/ARM -I include -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-10-03-140002-15933-1 -x c++ /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MachineValueType.h"
103#include "llvm/Support/MathExtras.h"
104#include "llvm/Support/raw_ostream.h"
105#include "llvm/Target/TargetMachine.h"
106#include "llvm/Target/TargetOptions.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <string>
114#include <tuple>
115#include <utility>
116#include <vector>
117
118using namespace llvm;
119using namespace llvm::PatternMatch;
120
121#define DEBUG_TYPE"arm-isel" "arm-isel"
122
123STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
124STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
125STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
126STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
127 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
128
129static cl::opt<bool>
130ARMInterworking("arm-interworking", cl::Hidden,
131 cl::desc("Enable / disable ARM interworking (for debugging only)"),
132 cl::init(true));
133
134static cl::opt<bool> EnableConstpoolPromotion(
135 "arm-promote-constant", cl::Hidden,
136 cl::desc("Enable / disable promotion of unnamed_addr constants into "
137 "constant pools"),
138 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
139static cl::opt<unsigned> ConstpoolPromotionMaxSize(
140 "arm-promote-constant-max-size", cl::Hidden,
141 cl::desc("Maximum size of constant to promote into a constant pool"),
142 cl::init(64));
143static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
144 "arm-promote-constant-max-total", cl::Hidden,
145 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
146 cl::init(128));
147
148cl::opt<unsigned>
149MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
150 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
151 cl::init(2));
152
153// The APCS parameter registers.
154static const MCPhysReg GPRArgRegs[] = {
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156};
157
158void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Neon does not support vector divide/remainder operations.
198 setOperationAction(ISD::SDIV, VT, Expand);
199 setOperationAction(ISD::UDIV, VT, Expand);
200 setOperationAction(ISD::FDIV, VT, Expand);
201 setOperationAction(ISD::SREM, VT, Expand);
202 setOperationAction(ISD::UREM, VT, Expand);
203 setOperationAction(ISD::FREM, VT, Expand);
204 setOperationAction(ISD::SDIVREM, VT, Expand);
205 setOperationAction(ISD::UDIVREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211 if (!VT.isFloatingPoint())
212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
213 setOperationAction(Opcode, VT, Legal);
214}
215
216void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
217 addRegisterClass(VT, &ARM::DPRRegClass);
218 addTypeForNEON(VT, MVT::f64);
219}
220
221void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
222 addRegisterClass(VT, &ARM::DPairRegClass);
223 addTypeForNEON(VT, MVT::v2f64);
224}
225
226void ARMTargetLowering::setAllExpand(MVT VT) {
227 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
228 setOperationAction(Opc, VT, Expand);
229
230 // We support these really simple operations even on types where all
231 // the actual arithmetic has to be broken down into simpler
232 // operations or turned into library calls.
233 setOperationAction(ISD::BITCAST, VT, Legal);
234 setOperationAction(ISD::LOAD, VT, Legal);
235 setOperationAction(ISD::STORE, VT, Legal);
236 setOperationAction(ISD::UNDEF, VT, Legal);
237}
238
239void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
240 LegalizeAction Action) {
241 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
244}
245
246void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
247 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
248
249 for (auto VT : IntTypes) {
250 addRegisterClass(VT, &ARM::MQPRRegClass);
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
255 setOperationAction(ISD::SHL, VT, Custom);
256 setOperationAction(ISD::SRA, VT, Custom);
257 setOperationAction(ISD::SRL, VT, Custom);
258 setOperationAction(ISD::SMIN, VT, Legal);
259 setOperationAction(ISD::SMAX, VT, Legal);
260 setOperationAction(ISD::UMIN, VT, Legal);
261 setOperationAction(ISD::UMAX, VT, Legal);
262 setOperationAction(ISD::ABS, VT, Legal);
263 setOperationAction(ISD::SETCC, VT, Custom);
264 setOperationAction(ISD::MLOAD, VT, Custom);
265 setOperationAction(ISD::MSTORE, VT, Legal);
266 setOperationAction(ISD::CTLZ, VT, Legal);
267 setOperationAction(ISD::CTTZ, VT, Custom);
268 setOperationAction(ISD::BITREVERSE, VT, Legal);
269 setOperationAction(ISD::BSWAP, VT, Legal);
270 setOperationAction(ISD::SADDSAT, VT, Legal);
271 setOperationAction(ISD::UADDSAT, VT, Legal);
272 setOperationAction(ISD::SSUBSAT, VT, Legal);
273 setOperationAction(ISD::USUBSAT, VT, Legal);
274 setOperationAction(ISD::ABDS, VT, Legal);
275 setOperationAction(ISD::ABDU, VT, Legal);
276 setOperationAction(ISD::AVGFLOORS, VT, Legal);
277 setOperationAction(ISD::AVGFLOORU, VT, Legal);
278 setOperationAction(ISD::AVGCEILS, VT, Legal);
279 setOperationAction(ISD::AVGCEILU, VT, Legal);
280
281 // No native support for these.
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
285 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::UDIVREM, VT, Expand);
287 setOperationAction(ISD::SDIVREM, VT, Expand);
288 setOperationAction(ISD::CTPOP, VT, Expand);
289 setOperationAction(ISD::SELECT, VT, Expand);
290 setOperationAction(ISD::SELECT_CC, VT, Expand);
291
292 // Vector reductions
293 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
299 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
302
303 if (!HasMVEFP) {
304 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
305 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
307 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
308 } else {
309 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
310 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
311 }
312
313 // Pre and Post inc are supported on loads and stores
314 for (unsigned im = (unsigned)ISD::PRE_INC;
315 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
316 setIndexedLoadAction(im, VT, Legal);
317 setIndexedStoreAction(im, VT, Legal);
318 setIndexedMaskedLoadAction(im, VT, Legal);
319 setIndexedMaskedStoreAction(im, VT, Legal);
320 }
321 }
322
323 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
324 for (auto VT : FloatTypes) {
325 addRegisterClass(VT, &ARM::MQPRRegClass);
326 if (!HasMVEFP)
327 setAllExpand(VT);
328
329 // These are legal or custom whether we have MVE.fp or not
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
336 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
337 setOperationAction(ISD::SETCC, VT, Custom);
338 setOperationAction(ISD::MLOAD, VT, Custom);
339 setOperationAction(ISD::MSTORE, VT, Legal);
340 setOperationAction(ISD::SELECT, VT, Expand);
341 setOperationAction(ISD::SELECT_CC, VT, Expand);
342
343 // Pre and Post inc are supported on loads and stores
344 for (unsigned im = (unsigned)ISD::PRE_INC;
345 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
346 setIndexedLoadAction(im, VT, Legal);
347 setIndexedStoreAction(im, VT, Legal);
348 setIndexedMaskedLoadAction(im, VT, Legal);
349 setIndexedMaskedStoreAction(im, VT, Legal);
350 }
351
352 if (HasMVEFP) {
353 setOperationAction(ISD::FMINNUM, VT, Legal);
354 setOperationAction(ISD::FMAXNUM, VT, Legal);
355 setOperationAction(ISD::FROUND, VT, Legal);
356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
357 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
360
361 // No native support for these.
362 setOperationAction(ISD::FDIV, VT, Expand);
363 setOperationAction(ISD::FREM, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FSIN, VT, Expand);
366 setOperationAction(ISD::FCOS, VT, Expand);
367 setOperationAction(ISD::FPOW, VT, Expand);
368 setOperationAction(ISD::FLOG, VT, Expand);
369 setOperationAction(ISD::FLOG2, VT, Expand);
370 setOperationAction(ISD::FLOG10, VT, Expand);
371 setOperationAction(ISD::FEXP, VT, Expand);
372 setOperationAction(ISD::FEXP2, VT, Expand);
373 setOperationAction(ISD::FNEARBYINT, VT, Expand);
374 }
375 }
376
377 // Custom Expand smaller than legal vector reductions to prevent false zero
378 // items being added.
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
387
388 // We 'support' these types up to bitcast/load/store level, regardless of
389 // MVE integer-only / float support. Only doing FP data processing on the FP
390 // vector types is inhibited at integer-only level.
391 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
392 for (auto VT : LongTypes) {
393 addRegisterClass(VT, &ARM::MQPRRegClass);
394 setAllExpand(VT);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
398 setOperationAction(ISD::VSELECT, VT, Legal);
399 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
400 }
401 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
402
403 // We can do bitwise operations on v2i64 vectors
404 setOperationAction(ISD::AND, MVT::v2i64, Legal);
405 setOperationAction(ISD::OR, MVT::v2i64, Legal);
406 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
407
408 // It is legal to extload from v4i8 to v4i16 or v4i32.
409 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
410 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
411 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
412
413 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
418 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
419
420 // Some truncating stores are legal too.
421 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
422 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
423 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
424
425 // Pre and Post inc on these are legal, given the correct extends
426 for (unsigned im = (unsigned)ISD::PRE_INC;
427 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
428 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
429 setIndexedLoadAction(im, VT, Legal);
430 setIndexedStoreAction(im, VT, Legal);
431 setIndexedMaskedLoadAction(im, VT, Legal);
432 setIndexedMaskedStoreAction(im, VT, Legal);
433 }
434 }
435
436 // Predicate types
437 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
438 for (auto VT : pTypes) {
439 addRegisterClass(VT, &ARM::VCCRRegClass);
440 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
442 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
443 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
444 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
446 setOperationAction(ISD::SETCC, VT, Custom);
447 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
448 setOperationAction(ISD::LOAD, VT, Custom);
449 setOperationAction(ISD::STORE, VT, Custom);
450 setOperationAction(ISD::TRUNCATE, VT, Custom);
451 setOperationAction(ISD::VSELECT, VT, Expand);
452 setOperationAction(ISD::SELECT, VT, Expand);
453 setOperationAction(ISD::SELECT_CC, VT, Expand);
454
455 if (!HasMVEFP) {
456 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
457 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
458 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
459 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
460 }
461 }
462 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
463 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
464 setOperationAction(ISD::AND, MVT::v2i1, Expand);
465 setOperationAction(ISD::OR, MVT::v2i1, Expand);
466 setOperationAction(ISD::XOR, MVT::v2i1, Expand);
467 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand);
468 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand);
469 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand);
470 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand);
471
472 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
473 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
474 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
475 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
476 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
477 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
478 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
479 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
480}
481
482ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
483 const ARMSubtarget &STI)
484 : TargetLowering(TM), Subtarget(&STI) {
485 RegInfo = Subtarget->getRegisterInfo();
486 Itins = Subtarget->getInstrItineraryData();
487
488 setBooleanContents(ZeroOrOneBooleanContent);
489 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
490
491 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
492 !Subtarget->isTargetWatchOS() && !Subtarget->isTargetDriverKit()) {
493 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
494 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
495 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
496 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
497 : CallingConv::ARM_AAPCS);
498 }
499
500 if (Subtarget->isTargetMachO()) {
501 // Uses VFP for Thumb libfuncs if available.
502 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
503 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
504 static const struct {
505 const RTLIB::Libcall Op;
506 const char * const Name;
507 const ISD::CondCode Cond;
508 } LibraryCalls[] = {
509 // Single-precision floating-point arithmetic.
510 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
511 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
512 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
513 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
514
515 // Double-precision floating-point arithmetic.
516 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
517 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
518 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
519 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
520
521 // Single-precision comparisons.
522 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
523 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
524 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
525 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
526 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
527 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
528 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
529
530 // Double-precision comparisons.
531 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
532 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
533 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
534 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
535 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
536 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
537 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
538
539 // Floating-point to integer conversions.
540 // i64 conversions are done via library routines even when generating VFP
541 // instructions, so use the same ones.
542 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
543 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
544 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
545 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
546
547 // Conversions between floating types.
548 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
549 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
550
551 // Integer to floating-point conversions.
552 // i64 conversions are done via library routines even when generating VFP
553 // instructions, so use the same ones.
554 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
555 // e.g., __floatunsidf vs. __floatunssidfvfp.
556 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
557 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
558 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
559 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
560 };
561
562 for (const auto &LC : LibraryCalls) {
563 setLibcallName(LC.Op, LC.Name);
564 if (LC.Cond != ISD::SETCC_INVALID)
565 setCmpLibcallCC(LC.Op, LC.Cond);
566 }
567 }
568 }
569
570 // These libcalls are not available in 32-bit.
571 setLibcallName(RTLIB::SHL_I128, nullptr);
572 setLibcallName(RTLIB::SRL_I128, nullptr);
573 setLibcallName(RTLIB::SRA_I128, nullptr);
574 setLibcallName(RTLIB::MUL_I128, nullptr);
575 setLibcallName(RTLIB::MULO_I64, nullptr);
576 setLibcallName(RTLIB::MULO_I128, nullptr);
577
578 // RTLIB
579 if (Subtarget->isAAPCS_ABI() &&
580 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
581 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
582 static const struct {
583 const RTLIB::Libcall Op;
584 const char * const Name;
585 const CallingConv::ID CC;
586 const ISD::CondCode Cond;
587 } LibraryCalls[] = {
588 // Double-precision floating-point arithmetic helper functions
589 // RTABI chapter 4.1.2, Table 2
590 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
594
595 // Double-precision floating-point comparison helper functions
596 // RTABI chapter 4.1.2, Table 3
597 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
598 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
599 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
600 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
601 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
602 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
603 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
604
605 // Single-precision floating-point arithmetic helper functions
606 // RTABI chapter 4.1.2, Table 4
607 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611
612 // Single-precision floating-point comparison helper functions
613 // RTABI chapter 4.1.2, Table 5
614 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
615 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
616 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
617 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
618 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
619 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
620 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
621
622 // Floating-point to integer conversions.
623 // RTABI chapter 4.1.2, Table 6
624 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632
633 // Conversions between floating types.
634 // RTABI chapter 4.1.2, Table 7
635 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638
639 // Integer to floating-point conversions.
640 // RTABI chapter 4.1.2, Table 8
641 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
642 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
643 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
644 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
645 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
646 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
647 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649
650 // Long long helper functions
651 // RTABI chapter 4.2, Table 9
652 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
653 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
654 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
655 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
656
657 // Integer division functions
658 // RTABI chapter 4.3.1
659 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
660 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
662 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
663 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
664 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
665 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
666 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
667 };
668
669 for (const auto &LC : LibraryCalls) {
670 setLibcallName(LC.Op, LC.Name);
671 setLibcallCallingConv(LC.Op, LC.CC);
672 if (LC.Cond != ISD::SETCC_INVALID)
673 setCmpLibcallCC(LC.Op, LC.Cond);
674 }
675
676 // EABI dependent RTLIB
677 if (TM.Options.EABIVersion == EABI::EABI4 ||
678 TM.Options.EABIVersion == EABI::EABI5) {
679 static const struct {
680 const RTLIB::Libcall Op;
681 const char *const Name;
682 const CallingConv::ID CC;
683 const ISD::CondCode Cond;
684 } MemOpsLibraryCalls[] = {
685 // Memory operations
686 // RTABI chapter 4.3.4
687 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
688 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
689 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
690 };
691
692 for (const auto &LC : MemOpsLibraryCalls) {
693 setLibcallName(LC.Op, LC.Name);
694 setLibcallCallingConv(LC.Op, LC.CC);
695 if (LC.Cond != ISD::SETCC_INVALID)
696 setCmpLibcallCC(LC.Op, LC.Cond);
697 }
698 }
699 }
700
701 if (Subtarget->isTargetWindows()) {
702 static const struct {
703 const RTLIB::Libcall Op;
704 const char * const Name;
705 const CallingConv::ID CC;
706 } LibraryCalls[] = {
707 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
708 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
709 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
710 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
711 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
712 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
713 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
714 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
715 };
716
717 for (const auto &LC : LibraryCalls) {
718 setLibcallName(LC.Op, LC.Name);
719 setLibcallCallingConv(LC.Op, LC.CC);
720 }
721 }
722
723 // Use divmod compiler-rt calls for iOS 5.0 and later.
724 if (Subtarget->isTargetMachO() &&
725 !(Subtarget->isTargetIOS() &&
726 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
727 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
728 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
729 }
730
731 // The half <-> float conversion functions are always soft-float on
732 // non-watchos platforms, but are needed for some targets which use a
733 // hard-float calling convention by default.
734 if (!Subtarget->isTargetWatchABI()) {
735 if (Subtarget->isAAPCS_ABI()) {
736 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
737 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
738 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
739 } else {
740 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
741 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
742 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
743 }
744 }
745
746 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
747 // a __gnu_ prefix (which is the default).
748 if (Subtarget->isTargetAEABI()) {
749 static const struct {
750 const RTLIB::Libcall Op;
751 const char * const Name;
752 const CallingConv::ID CC;
753 } LibraryCalls[] = {
754 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
755 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
756 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
757 };
758
759 for (const auto &LC : LibraryCalls) {
760 setLibcallName(LC.Op, LC.Name);
761 setLibcallCallingConv(LC.Op, LC.CC);
762 }
763 }
764
765 if (Subtarget->isThumb1Only())
766 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
767 else
768 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
769
770 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
771 Subtarget->hasFPRegs()) {
772 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
773 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
774
775 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
776 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
777 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
778 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
779
780 if (!Subtarget->hasVFP2Base())
781 setAllExpand(MVT::f32);
782 if (!Subtarget->hasFP64())
783 setAllExpand(MVT::f64);
784 }
785
786 if (Subtarget->hasFullFP16()) {
787 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
788 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
789 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
790
791 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
792 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
793 }
794
795 if (Subtarget->hasBF16()) {
796 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
797 setAllExpand(MVT::bf16);
798 if (!Subtarget->hasFullFP16())
799 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
800 }
801
802 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
803 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
804 setTruncStoreAction(VT, InnerVT, Expand);
805 addAllExtLoads(VT, InnerVT, Expand);
806 }
807
808 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
809 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
810
811 setOperationAction(ISD::BSWAP, VT, Expand);
812 }
813
814 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
815 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
816
817 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
818 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
819
820 if (Subtarget->hasMVEIntegerOps())
821 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
822
823 // Combine low-overhead loop intrinsics so that we can lower i1 types.
824 if (Subtarget->hasLOB()) {
825 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC});
826 }
827
828 if (Subtarget->hasNEON()) {
829 addDRTypeForNEON(MVT::v2f32);
830 addDRTypeForNEON(MVT::v8i8);
831 addDRTypeForNEON(MVT::v4i16);
832 addDRTypeForNEON(MVT::v2i32);
833 addDRTypeForNEON(MVT::v1i64);
834
835 addQRTypeForNEON(MVT::v4f32);
836 addQRTypeForNEON(MVT::v2f64);
837 addQRTypeForNEON(MVT::v16i8);
838 addQRTypeForNEON(MVT::v8i16);
839 addQRTypeForNEON(MVT::v4i32);
840 addQRTypeForNEON(MVT::v2i64);
841
842 if (Subtarget->hasFullFP16()) {
843 addQRTypeForNEON(MVT::v8f16);
844 addDRTypeForNEON(MVT::v4f16);
845 }
846
847 if (Subtarget->hasBF16()) {
848 addQRTypeForNEON(MVT::v8bf16);
849 addDRTypeForNEON(MVT::v4bf16);
850 }
851 }
852
853 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
854 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
855 // none of Neon, MVE or VFP supports any arithmetic operations on it.
856 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
857 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
858 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
859 // FIXME: Code duplication: FDIV and FREM are expanded always, see
860 // ARMTargetLowering::addTypeForNEON method for details.
861 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
862 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
863 // FIXME: Create unittest.
864 // In another words, find a way when "copysign" appears in DAG with vector
865 // operands.
866 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
867 // FIXME: Code duplication: SETCC has custom operation action, see
868 // ARMTargetLowering::addTypeForNEON method for details.
869 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
870 // FIXME: Create unittest for FNEG and for FABS.
871 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
872 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
873 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
874 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
875 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
876 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
877 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
878 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
879 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
880 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
881 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
882 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
883 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
884 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
885 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
886 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
887 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
888 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
889 }
890
891 if (Subtarget->hasNEON()) {
892 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
893 // supported for v4f32.
894 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
895 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
896 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
897 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
898 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
899 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
900 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
901 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
902 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
903 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
904 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
905 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
906 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
907 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
908
909 // Mark v2f32 intrinsics.
910 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
911 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
912 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
913 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
914 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
915 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
916 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
917 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
918 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
919 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
920 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
921 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
922 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
923 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
924
925 // Neon does not support some operations on v1i64 and v2i64 types.
926 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
927 // Custom handling for some quad-vector types to detect VMULL.
928 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
929 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
930 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
931 // Custom handling for some vector types to avoid expensive expansions
932 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
933 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
934 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
935 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
936 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
937 // a destination type that is wider than the source, and nor does
938 // it have a FP_TO_[SU]INT instruction with a narrower destination than
939 // source.
940 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
941 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
942 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
945 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
946 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
947 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
948
949 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
950 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
951
952 // NEON does not have single instruction CTPOP for vectors with element
953 // types wider than 8-bits. However, custom lowering can leverage the
954 // v8i8/v16i8 vcnt instruction.
955 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
956 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
957 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
958 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
959 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
960 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
961
962 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
963 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
964
965 // NEON does not have single instruction CTTZ for vectors.
966 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
967 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
968 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
969 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
970
971 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
972 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
973 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
974 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
975
976 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
977 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
978 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
979 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
980
981 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
982 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
983 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
984 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
985
986 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
987 setOperationAction(ISD::MULHS, VT, Expand);
988 setOperationAction(ISD::MULHU, VT, Expand);
989 }
990
991 // NEON only has FMA instructions as of VFP4.
992 if (!Subtarget->hasVFP4Base()) {
993 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
994 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
995 }
996
997 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
998 ISD::FP_TO_UINT, ISD::FDIV, ISD::LOAD});
999
1000 // It is legal to extload from v4i8 to v4i16 or v4i32.
1001 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
1002 MVT::v2i32}) {
1003 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1004 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
1005 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
1006 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
1007 }
1008 }
1009 }
1010
1011 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1012 setTargetDAGCombine(
1013 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR,
1014 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
1015 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND,
1016 ISD::ANY_EXTEND, ISD::INTRINSIC_WO_CHAIN, ISD::INTRINSIC_W_CHAIN,
1017 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST});
1018 }
1019 if (Subtarget->hasMVEIntegerOps()) {
1020 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX,
1021 ISD::FP_EXTEND, ISD::SELECT, ISD::SELECT_CC,
1022 ISD::SETCC});
1023 }
1024 if (Subtarget->hasMVEFloatOps()) {
1025 setTargetDAGCombine(ISD::FADD);
1026 }
1027
1028 if (!Subtarget->hasFP64()) {
1029 // When targeting a floating-point unit with only single-precision
1030 // operations, f64 is legal for the few double-precision instructions which
1031 // are present However, no double-precision operations other than moves,
1032 // loads and stores are provided by the hardware.
1033 setOperationAction(ISD::FADD, MVT::f64, Expand);
1034 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1035 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1036 setOperationAction(ISD::FMA, MVT::f64, Expand);
1037 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1038 setOperationAction(ISD::FREM, MVT::f64, Expand);
1039 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1040 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1041 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1042 setOperationAction(ISD::FABS, MVT::f64, Expand);
1043 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1044 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1045 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1046 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1047 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1048 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1049 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1050 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1051 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1052 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1053 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1054 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1055 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1056 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1058 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1060 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1062 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1063 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1064 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1065 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1066 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1067 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1068 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1069 }
1070
1071 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1072 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1073 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1074 if (Subtarget->hasFullFP16()) {
1075 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1076 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1077 }
1078 }
1079
1080 if (!Subtarget->hasFP16()) {
1081 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1082 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1083 }
1084
1085 computeRegisterProperties(Subtarget->getRegisterInfo());
1086
1087 // ARM does not have floating-point extending loads.
1088 for (MVT VT : MVT::fp_valuetypes()) {
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1090 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1091 }
1092
1093 // ... or truncating stores
1094 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1095 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1096 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1097
1098 // ARM does not have i1 sign extending load.
1099 for (MVT VT : MVT::integer_valuetypes())
1100 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1101
1102 // ARM supports all 4 flavors of integer indexed load / store.
1103 if (!Subtarget->isThumb1Only()) {
1104 for (unsigned im = (unsigned)ISD::PRE_INC;
1105 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1106 setIndexedLoadAction(im, MVT::i1, Legal);
1107 setIndexedLoadAction(im, MVT::i8, Legal);
1108 setIndexedLoadAction(im, MVT::i16, Legal);
1109 setIndexedLoadAction(im, MVT::i32, Legal);
1110 setIndexedStoreAction(im, MVT::i1, Legal);
1111 setIndexedStoreAction(im, MVT::i8, Legal);
1112 setIndexedStoreAction(im, MVT::i16, Legal);
1113 setIndexedStoreAction(im, MVT::i32, Legal);
1114 }
1115 } else {
1116 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1117 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1118 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1119 }
1120
1121 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1122 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1123 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1124 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1125
1126 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1127 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1128 if (Subtarget->hasDSP()) {
1129 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1130 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1131 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1132 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1133 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1134 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1135 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1136 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1137 }
1138 if (Subtarget->hasBaseDSP()) {
1139 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1140 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1141 }
1142
1143 // i64 operation support.
1144 setOperationAction(ISD::MUL, MVT::i64, Expand);
1145 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1146 if (Subtarget->isThumb1Only()) {
1147 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1148 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1149 }
1150 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1151 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1152 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1153
1154 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1155 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1156 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1157 setOperationAction(ISD::SRL, MVT::i64, Custom);
1158 setOperationAction(ISD::SRA, MVT::i64, Custom);
1159 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1160 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1161 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1162 setOperationAction(ISD::STORE, MVT::i64, Custom);
1163
1164 // MVE lowers 64 bit shifts to lsll and lsrl
1165 // assuming that ISD::SRL and SRA of i64 are already marked custom
1166 if (Subtarget->hasMVEIntegerOps())
1167 setOperationAction(ISD::SHL, MVT::i64, Custom);
1168
1169 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1170 if (Subtarget->isThumb1Only()) {
1171 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1172 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1173 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1174 }
1175
1176 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1177 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1178
1179 // ARM does not have ROTL.
1180 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1181 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1182 setOperationAction(ISD::ROTL, VT, Expand);
1183 setOperationAction(ISD::ROTR, VT, Expand);
1184 }
1185 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1186 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1187 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1188 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1189 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1190 }
1191
1192 // @llvm.readcyclecounter requires the Performance Monitors extension.
1193 // Default to the 0 expansion on unsupported platforms.
1194 // FIXME: Technically there are older ARM CPUs that have
1195 // implementation-specific ways of obtaining this information.
1196 if (Subtarget->hasPerfMon())
1197 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1198
1199 // Only ARMv6 has BSWAP.
1200 if (!Subtarget->hasV6Ops())
1201 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1202
1203 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1204 : Subtarget->hasDivideInARMMode();
1205 if (!hasDivide) {
1206 // These are expanded into libcalls if the cpu doesn't have HW divider.
1207 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1208 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1209 }
1210
1211 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1212 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1213 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1214
1215 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1216 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1217 }
1218
1219 setOperationAction(ISD::SREM, MVT::i32, Expand);
1220 setOperationAction(ISD::UREM, MVT::i32, Expand);
1221
1222 // Register based DivRem for AEABI (RTABI 4.2)
1223 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1224 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1225 Subtarget->isTargetWindows()) {
1226 setOperationAction(ISD::SREM, MVT::i64, Custom);
1227 setOperationAction(ISD::UREM, MVT::i64, Custom);
1228 HasStandaloneRem = false;
1229
1230 if (Subtarget->isTargetWindows()) {
1231 const struct {
1232 const RTLIB::Libcall Op;
1233 const char * const Name;
1234 const CallingConv::ID CC;
1235 } LibraryCalls[] = {
1236 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1237 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1238 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1239 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1240
1241 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1242 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1243 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1244 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1245 };
1246
1247 for (const auto &LC : LibraryCalls) {
1248 setLibcallName(LC.Op, LC.Name);
1249 setLibcallCallingConv(LC.Op, LC.CC);
1250 }
1251 } else {
1252 const struct {
1253 const RTLIB::Libcall Op;
1254 const char * const Name;
1255 const CallingConv::ID CC;
1256 } LibraryCalls[] = {
1257 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1258 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1259 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1260 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1261
1262 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1263 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1264 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1265 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1266 };
1267
1268 for (const auto &LC : LibraryCalls) {
1269 setLibcallName(LC.Op, LC.Name);
1270 setLibcallCallingConv(LC.Op, LC.CC);
1271 }
1272 }
1273
1274 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1275 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1276 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1277 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1278 } else {
1279 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1280 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1281 }
1282
1283 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1284 // MSVCRT doesn't have powi; fall back to pow
1285 setLibcallName(RTLIB::POWI_F32, nullptr);
1286 setLibcallName(RTLIB::POWI_F64, nullptr);
1287 }
1288
1289 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1290 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1291 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1292 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1293
1294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1295 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1296
1297 // Use the default implementation.
1298 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1299 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1300 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1301 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1302 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1303 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1304
1305 if (Subtarget->isTargetWindows())
1306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1307 else
1308 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1309
1310 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1311 // the default expansion.
1312 InsertFencesForAtomic = false;
1313 if (Subtarget->hasAnyDataBarrier() &&
1314 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1315 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1316 // to ldrex/strex loops already.
1317 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1318 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1320
1321 // On v8, we have particularly efficient implementations of atomic fences
1322 // if they can be combined with nearby atomic loads and stores.
1323 if (!Subtarget->hasAcquireRelease() ||
1324 getTargetMachine().getOptLevel() == 0) {
1325 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1326 InsertFencesForAtomic = true;
1327 }
1328 } else {
1329 // If there's anything we can use as a barrier, go through custom lowering
1330 // for ATOMIC_FENCE.
1331 // If target has DMB in thumb, Fences can be inserted.
1332 if (Subtarget->hasDataBarrier())
1333 InsertFencesForAtomic = true;
1334
1335 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1336 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1337
1338 // Set them all for expansion, which will force libcalls.
1339 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1340 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1347 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1348 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1349 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1350 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1351 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1352 // Unordered/Monotonic case.
1353 if (!InsertFencesForAtomic) {
1354 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1355 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1356 }
1357 }
1358
1359 // Compute supported atomic widths.
1360 if (Subtarget->isTargetLinux() ||
1361 (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
1362 // For targets where __sync_* routines are reliably available, we use them
1363 // if necessary.
1364 //
1365 // ARM Linux always supports 64-bit atomics through kernel-assisted atomic
1366 // routines (kernel 3.1 or later). FIXME: Not with compiler-rt?
1367 //
1368 // ARMv6 targets have native instructions in ARM mode. For Thumb mode,
1369 // such targets should provide __sync_* routines, which use the ARM mode
1370 // instructions. (ARMv6 doesn't have dmb, but it has an equivalent
1371 // encoding; see ARMISD::MEMBARRIER_MCR.)
1372 setMaxAtomicSizeInBitsSupported(64);
1373 } else if ((Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) ||
1374 Subtarget->hasForced32BitAtomics()) {
1375 // Cortex-M (besides Cortex-M0) have 32-bit atomics.
1376 setMaxAtomicSizeInBitsSupported(32);
1377 } else {
1378 // We can't assume anything about other targets; just use libatomic
1379 // routines.
1380 setMaxAtomicSizeInBitsSupported(0);
1381 }
1382
1383 setMaxDivRemBitWidthSupported(64);
1384
1385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1386
1387 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1388 if (!Subtarget->hasV6Ops()) {
1389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1391 }
1392 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1393
1394 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1395 !Subtarget->isThumb1Only()) {
1396 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1397 // iff target supports vfp2.
1398 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1399 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1400 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1401 }
1402
1403 // We want to custom lower some of our intrinsics.
1404 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1405 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1406 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1407 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1408 if (Subtarget->useSjLjEH())
1409 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1410
1411 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1412 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1413 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1414 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1415 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1416 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1417 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1418 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1419 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1420 if (Subtarget->hasFullFP16()) {
1421 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1422 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1423 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1424 }
1425
1426 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1427
1428 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1429 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1430 if (Subtarget->hasFullFP16())
1431 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1432 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1433 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1434 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1435
1436 // We don't support sin/cos/fmod/copysign/pow
1437 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1438 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1439 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1440 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1441 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1442 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1443 setOperationAction(ISD::FREM, MVT::f64, Expand);
1444 setOperationAction(ISD::FREM, MVT::f32, Expand);
1445 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1446 !Subtarget->isThumb1Only()) {
1447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1449 }
1450 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1451 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1452
1453 if (!Subtarget->hasVFP4Base()) {
1454 setOperationAction(ISD::FMA, MVT::f64, Expand);
1455 setOperationAction(ISD::FMA, MVT::f32, Expand);
1456 }
1457
1458 // Various VFP goodness
1459 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1460 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1461 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1462 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1463 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1464 }
1465
1466 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1467 if (!Subtarget->hasFP16()) {
1468 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1469 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1470 }
1471
1472 // Strict floating-point comparisons need custom lowering.
1473 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1474 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1475 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1476 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1477 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1478 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1479 }
1480
1481 // Use __sincos_stret if available.
1482 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1483 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1484 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1485 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1486 }
1487
1488 // FP-ARMv8 implements a lot of rounding-like FP operations.
1489 if (Subtarget->hasFPARMv8Base()) {
1490 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1491 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1492 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1493 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1494 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1495 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1496 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1497 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1498 if (Subtarget->hasNEON()) {
1499 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1500 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1501 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1502 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1503 }
1504
1505 if (Subtarget->hasFP64()) {
1506 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1507 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1508 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1509 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1510 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1511 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1512 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1513 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1514 }
1515 }
1516
1517 // FP16 often need to be promoted to call lib functions
1518 if (Subtarget->hasFullFP16()) {
1519 setOperationAction(ISD::FREM, MVT::f16, Promote);
1520 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1521 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1522 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1523 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1524 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1525 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1526 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1527 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1528 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1529 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1530 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1531
1532 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1533 }
1534
1535 if (Subtarget->hasNEON()) {
1536 // vmin and vmax aren't available in a scalar form, so we can use
1537 // a NEON instruction with an undef lane instead. This has a performance
1538 // penalty on some cores, so we don't do this unless we have been
1539 // asked to by the core tuning model.
1540 if (Subtarget->useNEONForSinglePrecisionFP()) {
1541 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1542 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1543 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1544 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1545 }
1546 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1547 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1548 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1549 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1550
1551 if (Subtarget->hasFullFP16()) {
1552 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1553 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1554 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1555 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1556
1557 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1558 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1559 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1560 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1561 }
1562 }
1563
1564 // We have target-specific dag combine patterns for the following nodes:
1565 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1566 setTargetDAGCombine(
1567 {ISD::ADD, ISD::SUB, ISD::MUL, ISD::AND, ISD::OR, ISD::XOR});
1568
1569 if (Subtarget->hasMVEIntegerOps())
1570 setTargetDAGCombine(ISD::VSELECT);
1571
1572 if (Subtarget->hasV6Ops())
1573 setTargetDAGCombine(ISD::SRL);
1574 if (Subtarget->isThumb1Only())
1575 setTargetDAGCombine(ISD::SHL);
1576 // Attempt to lower smin/smax to ssat/usat
1577 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
1578 Subtarget->isThumb2()) {
1579 setTargetDAGCombine({ISD::SMIN, ISD::SMAX});
1580 }
1581
1582 setStackPointerRegisterToSaveRestore(ARM::SP);
1583
1584 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1585 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1586 setSchedulingPreference(Sched::RegPressure);
1587 else
1588 setSchedulingPreference(Sched::Hybrid);
1589
1590 //// temporary - rewrite interface to use type
1591 MaxStoresPerMemset = 8;
1592 MaxStoresPerMemsetOptSize = 4;
1593 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1594 MaxStoresPerMemcpyOptSize = 2;
1595 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1596 MaxStoresPerMemmoveOptSize = 2;
1597
1598 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1599 // are at least 4 bytes aligned.
1600 setMinStackArgumentAlignment(Align(4));
1601
1602 // Prefer likely predicted branches to selects on out-of-order cores.
1603 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1604
1605 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1606
1607 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1608
1609 if (Subtarget->isThumb() || Subtarget->isThumb2())
1610 setTargetDAGCombine(ISD::ABS);
1611}
1612
1613bool ARMTargetLowering::useSoftFloat() const {
1614 return Subtarget->useSoftFloat();
1615}
1616
1617// FIXME: It might make sense to define the representative register class as the
1618// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1619// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1620// SPR's representative would be DPR_VFP2. This should work well if register
1621// pressure tracking were modified such that a register use would increment the
1622// pressure of the register class's representative and all of it's super
1623// classes' representatives transitively. We have not implemented this because
1624// of the difficulty prior to coalescing of modeling operand register classes
1625// due to the common occurrence of cross class copies and subregister insertions
1626// and extractions.
1627std::pair<const TargetRegisterClass *, uint8_t>
1628ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1629 MVT VT) const {
1630 const TargetRegisterClass *RRC = nullptr;
1631 uint8_t Cost = 1;
1632 switch (VT.SimpleTy) {
1633 default:
1634 return TargetLowering::findRepresentativeClass(TRI, VT);
1635 // Use DPR as representative register class for all floating point
1636 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1637 // the cost is 1 for both f32 and f64.
1638 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1639 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1640 RRC = &ARM::DPRRegClass;
1641 // When NEON is used for SP, only half of the register file is available
1642 // because operations that define both SP and DP results will be constrained
1643 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1644 // coalescing by double-counting the SP regs. See the FIXME above.
1645 if (Subtarget->useNEONForSinglePrecisionFP())
1646 Cost = 2;
1647 break;
1648 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1649 case MVT::v4f32: case MVT::v2f64:
1650 RRC = &ARM::DPRRegClass;
1651 Cost = 2;
1652 break;
1653 case MVT::v4i64:
1654 RRC = &ARM::DPRRegClass;
1655 Cost = 4;
1656 break;
1657 case MVT::v8i64:
1658 RRC = &ARM::DPRRegClass;
1659 Cost = 8;
1660 break;
1661 }
1662 return std::make_pair(RRC, Cost);
1663}
1664
1665const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1666#define MAKE_CASE(V) \
1667 case V: \
1668 return #V;
1669 switch ((ARMISD::NodeType)Opcode) {
1670 case ARMISD::FIRST_NUMBER:
1671 break;
1672 MAKE_CASE(ARMISD::Wrapper)
1673 MAKE_CASE(ARMISD::WrapperPIC)
1674 MAKE_CASE(ARMISD::WrapperJT)
1675 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1676 MAKE_CASE(ARMISD::CALL)
1677 MAKE_CASE(ARMISD::CALL_PRED)
1678 MAKE_CASE(ARMISD::CALL_NOLINK)
1679 MAKE_CASE(ARMISD::tSECALL)
1680 MAKE_CASE(ARMISD::t2CALL_BTI)
1681 MAKE_CASE(ARMISD::BRCOND)
1682 MAKE_CASE(ARMISD::BR_JT)
1683 MAKE_CASE(ARMISD::BR2_JT)
1684 MAKE_CASE(ARMISD::RET_FLAG)
1685 MAKE_CASE(ARMISD::SERET_FLAG)
1686 MAKE_CASE(ARMISD::INTRET_FLAG)
1687 MAKE_CASE(ARMISD::PIC_ADD)
1688 MAKE_CASE(ARMISD::CMP)
1689 MAKE_CASE(ARMISD::CMN)
1690 MAKE_CASE(ARMISD::CMPZ)
1691 MAKE_CASE(ARMISD::CMPFP)
1692 MAKE_CASE(ARMISD::CMPFPE)
1693 MAKE_CASE(ARMISD::CMPFPw0)
1694 MAKE_CASE(ARMISD::CMPFPEw0)
1695 MAKE_CASE(ARMISD::BCC_i64)
1696 MAKE_CASE(ARMISD::FMSTAT)
1697 MAKE_CASE(ARMISD::CMOV)
1698 MAKE_CASE(ARMISD::SUBS)
1699 MAKE_CASE(ARMISD::SSAT)
1700 MAKE_CASE(ARMISD::USAT)
1701 MAKE_CASE(ARMISD::ASRL)
1702 MAKE_CASE(ARMISD::LSRL)
1703 MAKE_CASE(ARMISD::LSLL)
1704 MAKE_CASE(ARMISD::SRL_FLAG)
1705 MAKE_CASE(ARMISD::SRA_FLAG)
1706 MAKE_CASE(ARMISD::RRX)
1707 MAKE_CASE(ARMISD::ADDC)
1708 MAKE_CASE(ARMISD::ADDE)
1709 MAKE_CASE(ARMISD::SUBC)
1710 MAKE_CASE(ARMISD::SUBE)
1711 MAKE_CASE(ARMISD::LSLS)
1712 MAKE_CASE(ARMISD::VMOVRRD)
1713 MAKE_CASE(ARMISD::VMOVDRR)
1714 MAKE_CASE(ARMISD::VMOVhr)
1715 MAKE_CASE(ARMISD::VMOVrh)
1716 MAKE_CASE(ARMISD::VMOVSR)
1717 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1718 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1719 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1720 MAKE_CASE(ARMISD::TC_RETURN)
1721 MAKE_CASE(ARMISD::THREAD_POINTER)
1722 MAKE_CASE(ARMISD::DYN_ALLOC)
1723 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1724 MAKE_CASE(ARMISD::PRELOAD)
1725 MAKE_CASE(ARMISD::LDRD)
1726 MAKE_CASE(ARMISD::STRD)
1727 MAKE_CASE(ARMISD::WIN__CHKSTK)
1728 MAKE_CASE(ARMISD::WIN__DBZCHK)
1729 MAKE_CASE(ARMISD::PREDICATE_CAST)
1730 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1731 MAKE_CASE(ARMISD::MVESEXT)
1732 MAKE_CASE(ARMISD::MVEZEXT)
1733 MAKE_CASE(ARMISD::MVETRUNC)
1734 MAKE_CASE(ARMISD::VCMP)
1735 MAKE_CASE(ARMISD::VCMPZ)
1736 MAKE_CASE(ARMISD::VTST)
1737 MAKE_CASE(ARMISD::VSHLs)
1738 MAKE_CASE(ARMISD::VSHLu)
1739 MAKE_CASE(ARMISD::VSHLIMM)
1740 MAKE_CASE(ARMISD::VSHRsIMM)
1741 MAKE_CASE(ARMISD::VSHRuIMM)
1742 MAKE_CASE(ARMISD::VRSHRsIMM)
1743 MAKE_CASE(ARMISD::VRSHRuIMM)
1744 MAKE_CASE(ARMISD::VRSHRNIMM)
1745 MAKE_CASE(ARMISD::VQSHLsIMM)
1746 MAKE_CASE(ARMISD::VQSHLuIMM)
1747 MAKE_CASE(ARMISD::VQSHLsuIMM)
1748 MAKE_CASE(ARMISD::VQSHRNsIMM)
1749 MAKE_CASE(ARMISD::VQSHRNuIMM)
1750 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1751 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1752 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1753 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1754 MAKE_CASE(ARMISD::VSLIIMM)
1755 MAKE_CASE(ARMISD::VSRIIMM)
1756 MAKE_CASE(ARMISD::VGETLANEu)
1757 MAKE_CASE(ARMISD::VGETLANEs)
1758 MAKE_CASE(ARMISD::VMOVIMM)
1759 MAKE_CASE(ARMISD::VMVNIMM)
1760 MAKE_CASE(ARMISD::VMOVFPIMM)
1761 MAKE_CASE(ARMISD::VDUP)
1762 MAKE_CASE(ARMISD::VDUPLANE)
1763 MAKE_CASE(ARMISD::VEXT)
1764 MAKE_CASE(ARMISD::VREV64)
1765 MAKE_CASE(ARMISD::VREV32)
1766 MAKE_CASE(ARMISD::VREV16)
1767 MAKE_CASE(ARMISD::VZIP)
1768 MAKE_CASE(ARMISD::VUZP)
1769 MAKE_CASE(ARMISD::VTRN)
1770 MAKE_CASE(ARMISD::VTBL1)
1771 MAKE_CASE(ARMISD::VTBL2)
1772 MAKE_CASE(ARMISD::VMOVN)
1773 MAKE_CASE(ARMISD::VQMOVNs)
1774 MAKE_CASE(ARMISD::VQMOVNu)
1775 MAKE_CASE(ARMISD::VCVTN)
1776 MAKE_CASE(ARMISD::VCVTL)
1777 MAKE_CASE(ARMISD::VIDUP)
1778 MAKE_CASE(ARMISD::VMULLs)
1779 MAKE_CASE(ARMISD::VMULLu)
1780 MAKE_CASE(ARMISD::VQDMULH)
1781 MAKE_CASE(ARMISD::VADDVs)
1782 MAKE_CASE(ARMISD::VADDVu)
1783 MAKE_CASE(ARMISD::VADDVps)
1784 MAKE_CASE(ARMISD::VADDVpu)
1785 MAKE_CASE(ARMISD::VADDLVs)
1786 MAKE_CASE(ARMISD::VADDLVu)
1787 MAKE_CASE(ARMISD::VADDLVAs)
1788 MAKE_CASE(ARMISD::VADDLVAu)
1789 MAKE_CASE(ARMISD::VADDLVps)
1790 MAKE_CASE(ARMISD::VADDLVpu)
1791 MAKE_CASE(ARMISD::VADDLVAps)
1792 MAKE_CASE(ARMISD::VADDLVApu)
1793 MAKE_CASE(ARMISD::VMLAVs)
1794 MAKE_CASE(ARMISD::VMLAVu)
1795 MAKE_CASE(ARMISD::VMLAVps)
1796 MAKE_CASE(ARMISD::VMLAVpu)
1797 MAKE_CASE(ARMISD::VMLALVs)
1798 MAKE_CASE(ARMISD::VMLALVu)
1799 MAKE_CASE(ARMISD::VMLALVps)
1800 MAKE_CASE(ARMISD::VMLALVpu)
1801 MAKE_CASE(ARMISD::VMLALVAs)
1802 MAKE_CASE(ARMISD::VMLALVAu)
1803 MAKE_CASE(ARMISD::VMLALVAps)
1804 MAKE_CASE(ARMISD::VMLALVApu)
1805 MAKE_CASE(ARMISD::VMINVu)
1806 MAKE_CASE(ARMISD::VMINVs)
1807 MAKE_CASE(ARMISD::VMAXVu)
1808 MAKE_CASE(ARMISD::VMAXVs)
1809 MAKE_CASE(ARMISD::UMAAL)
1810 MAKE_CASE(ARMISD::UMLAL)
1811 MAKE_CASE(ARMISD::SMLAL)
1812 MAKE_CASE(ARMISD::SMLALBB)
1813 MAKE_CASE(ARMISD::SMLALBT)
1814 MAKE_CASE(ARMISD::SMLALTB)
1815 MAKE_CASE(ARMISD::SMLALTT)
1816 MAKE_CASE(ARMISD::SMULWB)
1817 MAKE_CASE(ARMISD::SMULWT)
1818 MAKE_CASE(ARMISD::SMLALD)
1819 MAKE_CASE(ARMISD::SMLALDX)
1820 MAKE_CASE(ARMISD::SMLSLD)
1821 MAKE_CASE(ARMISD::SMLSLDX)
1822 MAKE_CASE(ARMISD::SMMLAR)
1823 MAKE_CASE(ARMISD::SMMLSR)
1824 MAKE_CASE(ARMISD::QADD16b)
1825 MAKE_CASE(ARMISD::QSUB16b)
1826 MAKE_CASE(ARMISD::QADD8b)
1827 MAKE_CASE(ARMISD::QSUB8b)
1828 MAKE_CASE(ARMISD::UQADD16b)
1829 MAKE_CASE(ARMISD::UQSUB16b)
1830 MAKE_CASE(ARMISD::UQADD8b)
1831 MAKE_CASE(ARMISD::UQSUB8b)
1832 MAKE_CASE(ARMISD::BUILD_VECTOR)
1833 MAKE_CASE(ARMISD::BFI)
1834 MAKE_CASE(ARMISD::VORRIMM)
1835 MAKE_CASE(ARMISD::VBICIMM)
1836 MAKE_CASE(ARMISD::VBSP)
1837 MAKE_CASE(ARMISD::MEMCPY)
1838 MAKE_CASE(ARMISD::VLD1DUP)
1839 MAKE_CASE(ARMISD::VLD2DUP)
1840 MAKE_CASE(ARMISD::VLD3DUP)
1841 MAKE_CASE(ARMISD::VLD4DUP)
1842 MAKE_CASE(ARMISD::VLD1_UPD)
1843 MAKE_CASE(ARMISD::VLD2_UPD)
1844 MAKE_CASE(ARMISD::VLD3_UPD)
1845 MAKE_CASE(ARMISD::VLD4_UPD)
1846 MAKE_CASE(ARMISD::VLD1x2_UPD)
1847 MAKE_CASE(ARMISD::VLD1x3_UPD)
1848 MAKE_CASE(ARMISD::VLD1x4_UPD)
1849 MAKE_CASE(ARMISD::VLD2LN_UPD)
1850 MAKE_CASE(ARMISD::VLD3LN_UPD)
1851 MAKE_CASE(ARMISD::VLD4LN_UPD)
1852 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1853 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1854 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1855 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1856 MAKE_CASE(ARMISD::VST1_UPD)
1857 MAKE_CASE(ARMISD::VST2_UPD)
1858 MAKE_CASE(ARMISD::VST3_UPD)
1859 MAKE_CASE(ARMISD::VST4_UPD)
1860 MAKE_CASE(ARMISD::VST1x2_UPD)
1861 MAKE_CASE(ARMISD::VST1x3_UPD)
1862 MAKE_CASE(ARMISD::VST1x4_UPD)
1863 MAKE_CASE(ARMISD::VST2LN_UPD)
1864 MAKE_CASE(ARMISD::VST3LN_UPD)
1865 MAKE_CASE(ARMISD::VST4LN_UPD)
1866 MAKE_CASE(ARMISD::WLS)
1867 MAKE_CASE(ARMISD::WLSSETUP)
1868 MAKE_CASE(ARMISD::LE)
1869 MAKE_CASE(ARMISD::LOOP_DEC)
1870 MAKE_CASE(ARMISD::CSINV)
1871 MAKE_CASE(ARMISD::CSNEG)
1872 MAKE_CASE(ARMISD::CSINC)
1873 MAKE_CASE(ARMISD::MEMCPYLOOP)
1874 MAKE_CASE(ARMISD::MEMSETLOOP)
1875#undef MAKE_CASE
1876 }
1877 return nullptr;
1878}
1879
1880EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1881 EVT VT) const {
1882 if (!VT.isVector())
1883 return getPointerTy(DL);
1884
1885 // MVE has a predicate register.
1886 if ((Subtarget->hasMVEIntegerOps() &&
1887 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
1888 VT == MVT::v16i8)) ||
1889 (Subtarget->hasMVEFloatOps() &&
1890 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
1891 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1892 return VT.changeVectorElementTypeToInteger();
1893}
1894
1895/// getRegClassFor - Return the register class that should be used for the
1896/// specified value type.
1897const TargetRegisterClass *
1898ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1899 (void)isDivergent;
1900 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1901 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1902 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1903 // MVE Q registers.
1904 if (Subtarget->hasNEON()) {
1905 if (VT == MVT::v4i64)
1906 return &ARM::QQPRRegClass;
1907 if (VT == MVT::v8i64)
1908 return &ARM::QQQQPRRegClass;
1909 }
1910 if (Subtarget->hasMVEIntegerOps()) {
1911 if (VT == MVT::v4i64)
1912 return &ARM::MQQPRRegClass;
1913 if (VT == MVT::v8i64)
1914 return &ARM::MQQQQPRRegClass;
1915 }
1916 return TargetLowering::getRegClassFor(VT);
1917}
1918
1919// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1920// source/dest is aligned and the copy size is large enough. We therefore want
1921// to align such objects passed to memory intrinsics.
1922bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1923 Align &PrefAlign) const {
1924 if (!isa<MemIntrinsic>(CI))
1925 return false;
1926 MinSize = 8;
1927 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1928 // cycle faster than 4-byte aligned LDM.
1929 PrefAlign =
1930 (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));
1931 return true;
1932}
1933
1934// Create a fast isel object.
1935FastISel *
1936ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1937 const TargetLibraryInfo *libInfo) const {
1938 return ARM::createFastISel(funcInfo, libInfo);
1939}
1940
1941Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1942 unsigned NumVals = N->getNumValues();
1943 if (!NumVals)
1944 return Sched::RegPressure;
1945
1946 for (unsigned i = 0; i != NumVals; ++i) {
1947 EVT VT = N->getValueType(i);
1948 if (VT == MVT::Glue || VT == MVT::Other)
1949 continue;
1950 if (VT.isFloatingPoint() || VT.isVector())
1951 return Sched::ILP;
1952 }
1953
1954 if (!N->isMachineOpcode())
1955 return Sched::RegPressure;
1956
1957 // Load are scheduled for latency even if there instruction itinerary
1958 // is not available.
1959 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1960 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1961
1962 if (MCID.getNumDefs() == 0)
1963 return Sched::RegPressure;
1964 if (!Itins->isEmpty() &&
1965 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1966 return Sched::ILP;
1967
1968 return Sched::RegPressure;
1969}
1970
1971//===----------------------------------------------------------------------===//
1972// Lowering Code
1973//===----------------------------------------------------------------------===//
1974
1975static bool isSRL16(const SDValue &Op) {
1976 if (Op.getOpcode() != ISD::SRL)
1977 return false;
1978 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1979 return Const->getZExtValue() == 16;
1980 return false;
1981}
1982
1983static bool isSRA16(const SDValue &Op) {
1984 if (Op.getOpcode() != ISD::SRA)
1985 return false;
1986 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1987 return Const->getZExtValue() == 16;
1988 return false;
1989}
1990
1991static bool isSHL16(const SDValue &Op) {
1992 if (Op.getOpcode() != ISD::SHL)
1993 return false;
1994 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1995 return Const->getZExtValue() == 16;
1996 return false;
1997}
1998
1999// Check for a signed 16-bit value. We special case SRA because it makes it
2000// more simple when also looking for SRAs that aren't sign extending a
2001// smaller value. Without the check, we'd need to take extra care with
2002// checking order for some operations.
2003static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
2004 if (isSRA16(Op))
2005 return isSHL16(Op.getOperand(0));
2006 return DAG.ComputeNumSignBits(Op) == 17;
2007}
2008
2009/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
2010static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2011 switch (CC) {
2012 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2012)
;
2013 case ISD::SETNE: return ARMCC::NE;
2014 case ISD::SETEQ: return ARMCC::EQ;
2015 case ISD::SETGT: return ARMCC::GT;
2016 case ISD::SETGE: return ARMCC::GE;
2017 case ISD::SETLT: return ARMCC::LT;
2018 case ISD::SETLE: return ARMCC::LE;
2019 case ISD::SETUGT: return ARMCC::HI;
2020 case ISD::SETUGE: return ARMCC::HS;
2021 case ISD::SETULT: return ARMCC::LO;
2022 case ISD::SETULE: return ARMCC::LS;
2023 }
2024}
2025
2026/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
2027static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2028 ARMCC::CondCodes &CondCode2) {
2029 CondCode2 = ARMCC::AL;
2030 switch (CC) {
2031 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2031)
;
2032 case ISD::SETEQ:
2033 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2034 case ISD::SETGT:
2035 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2036 case ISD::SETGE:
2037 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2038 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2039 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2040 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2041 case ISD::SETO: CondCode = ARMCC::VC; break;
2042 case ISD::SETUO: CondCode = ARMCC::VS; break;
2043 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2044 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2045 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2046 case ISD::SETLT:
2047 case ISD::SETULT: CondCode = ARMCC::LT; break;
2048 case ISD::SETLE:
2049 case ISD::SETULE: CondCode = ARMCC::LE; break;
2050 case ISD::SETNE:
2051 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2052 }
2053}
2054
2055//===----------------------------------------------------------------------===//
2056// Calling Convention Implementation
2057//===----------------------------------------------------------------------===//
2058
2059/// getEffectiveCallingConv - Get the effective calling convention, taking into
2060/// account presence of floating point hardware and calling convention
2061/// limitations, such as support for variadic functions.
2062CallingConv::ID
2063ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2064 bool isVarArg) const {
2065 switch (CC) {
2066 default:
2067 report_fatal_error("Unsupported calling convention");
2068 case CallingConv::ARM_AAPCS:
2069 case CallingConv::ARM_APCS:
2070 case CallingConv::GHC:
2071 case CallingConv::CFGuard_Check:
2072 return CC;
2073 case CallingConv::PreserveMost:
2074 return CallingConv::PreserveMost;
2075 case CallingConv::ARM_AAPCS_VFP:
2076 case CallingConv::Swift:
2077 case CallingConv::SwiftTail:
2078 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2079 case CallingConv::C:
2080 case CallingConv::Tail:
2081 if (!Subtarget->isAAPCS_ABI())
2082 return CallingConv::ARM_APCS;
2083 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2084 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2085 !isVarArg)
2086 return CallingConv::ARM_AAPCS_VFP;
2087 else
2088 return CallingConv::ARM_AAPCS;
2089 case CallingConv::Fast:
2090 case CallingConv::CXX_FAST_TLS:
2091 if (!Subtarget->isAAPCS_ABI()) {
2092 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2093 return CallingConv::Fast;
2094 return CallingConv::ARM_APCS;
2095 } else if (Subtarget->hasVFP2Base() &&
2096 !Subtarget->isThumb1Only() && !isVarArg)
2097 return CallingConv::ARM_AAPCS_VFP;
2098 else
2099 return CallingConv::ARM_AAPCS;
2100 }
2101}
2102
2103CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2104 bool isVarArg) const {
2105 return CCAssignFnForNode(CC, false, isVarArg);
2106}
2107
2108CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2109 bool isVarArg) const {
2110 return CCAssignFnForNode(CC, true, isVarArg);
2111}
2112
2113/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2114/// CallingConvention.
2115CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2116 bool Return,
2117 bool isVarArg) const {
2118 switch (getEffectiveCallingConv(CC, isVarArg)) {
2119 default:
2120 report_fatal_error("Unsupported calling convention");
2121 case CallingConv::ARM_APCS:
2122 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2123 case CallingConv::ARM_AAPCS:
2124 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2125 case CallingConv::ARM_AAPCS_VFP:
2126 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2127 case CallingConv::Fast:
2128 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2129 case CallingConv::GHC:
2130 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2131 case CallingConv::PreserveMost:
2132 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2133 case CallingConv::CFGuard_Check:
2134 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2135 }
2136}
2137
2138SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2139 MVT LocVT, MVT ValVT, SDValue Val) const {
2140 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2141 Val);
2142 if (Subtarget->hasFullFP16()) {
2143 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2144 } else {
2145 Val = DAG.getNode(ISD::TRUNCATE, dl,
2146 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2147 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2148 }
2149 return Val;
2150}
2151
2152SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2153 MVT LocVT, MVT ValVT,
2154 SDValue Val) const {
2155 if (Subtarget->hasFullFP16()) {
2156 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2157 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2158 } else {
2159 Val = DAG.getNode(ISD::BITCAST, dl,
2160 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2161 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2162 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2163 }
2164 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2165}
2166
2167/// LowerCallResult - Lower the result values of a call into the
2168/// appropriate copies out of appropriate physical registers.
2169SDValue ARMTargetLowering::LowerCallResult(
2170 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2171 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2172 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2173 SDValue ThisVal) const {
2174 // Assign locations to each value returned by this call.
2175 SmallVector<CCValAssign, 16> RVLocs;
2176 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2177 *DAG.getContext());
2178 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2179
2180 // Copy all of the result registers out of their specified physreg.
2181 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2182 CCValAssign VA = RVLocs[i];
2183
2184 // Pass 'this' value directly from the argument to return value, to avoid
2185 // reg unit interference
2186 if (i == 0 && isThisReturn) {
2187 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2188, __extension__
__PRETTY_FUNCTION__))
2188 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2188, __extension__
__PRETTY_FUNCTION__))
;
2189 InVals.push_back(ThisVal);
2190 continue;
2191 }
2192
2193 SDValue Val;
2194 if (VA.needsCustom() &&
2195 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2196 // Handle f64 or half of a v2f64.
2197 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2198 InFlag);
2199 Chain = Lo.getValue(1);
2200 InFlag = Lo.getValue(2);
2201 VA = RVLocs[++i]; // skip ahead to next loc
2202 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2203 InFlag);
2204 Chain = Hi.getValue(1);
2205 InFlag = Hi.getValue(2);
2206 if (!Subtarget->isLittle())
2207 std::swap (Lo, Hi);
2208 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2209
2210 if (VA.getLocVT() == MVT::v2f64) {
2211 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2212 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2213 DAG.getConstant(0, dl, MVT::i32));
2214
2215 VA = RVLocs[++i]; // skip ahead to next loc
2216 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2217 Chain = Lo.getValue(1);
2218 InFlag = Lo.getValue(2);
2219 VA = RVLocs[++i]; // skip ahead to next loc
2220 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2221 Chain = Hi.getValue(1);
2222 InFlag = Hi.getValue(2);
2223 if (!Subtarget->isLittle())
2224 std::swap (Lo, Hi);
2225 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2226 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2227 DAG.getConstant(1, dl, MVT::i32));
2228 }
2229 } else {
2230 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2231 InFlag);
2232 Chain = Val.getValue(1);
2233 InFlag = Val.getValue(2);
2234 }
2235
2236 switch (VA.getLocInfo()) {
2237 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2237)
;
2238 case CCValAssign::Full: break;
2239 case CCValAssign::BCvt:
2240 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2241 break;
2242 }
2243
2244 // f16 arguments have their size extended to 4 bytes and passed as if they
2245 // had been copied to the LSBs of a 32-bit register.
2246 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2247 if (VA.needsCustom() &&
2248 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2249 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2250
2251 InVals.push_back(Val);
2252 }
2253
2254 return Chain;
2255}
2256
2257std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2258 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2259 bool IsTailCall, int SPDiff) const {
2260 SDValue DstAddr;
2261 MachinePointerInfo DstInfo;
2262 int32_t Offset = VA.getLocMemOffset();
2263 MachineFunction &MF = DAG.getMachineFunction();
2264
2265 if (IsTailCall) {
2266 Offset += SPDiff;
2267 auto PtrVT = getPointerTy(DAG.getDataLayout());
2268 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2269 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2270 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2271 DstInfo =
2272 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2273 } else {
2274 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2275 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2276 StackPtr, PtrOff);
2277 DstInfo =
2278 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2279 }
2280
2281 return std::make_pair(DstAddr, DstInfo);
2282}
2283
2284void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2285 SDValue Chain, SDValue &Arg,
2286 RegsToPassVector &RegsToPass,
2287 CCValAssign &VA, CCValAssign &NextVA,
2288 SDValue &StackPtr,
2289 SmallVectorImpl<SDValue> &MemOpChains,
2290 bool IsTailCall,
2291 int SPDiff) const {
2292 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2293 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2294 unsigned id = Subtarget->isLittle() ? 0 : 1;
2295 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2296
2297 if (NextVA.isRegLoc())
2298 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2299 else {
2300 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2300, __extension__ __PRETTY_FUNCTION__))
;
2301 if (!StackPtr.getNode())
2302 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2303 getPointerTy(DAG.getDataLayout()));
2304
2305 SDValue DstAddr;
2306 MachinePointerInfo DstInfo;
2307 std::tie(DstAddr, DstInfo) =
2308 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2309 MemOpChains.push_back(
2310 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2311 }
2312}
2313
2314static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2315 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2316 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2317}
2318
2319/// LowerCall - Lowering a call into a callseq_start <-
2320/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2321/// nodes.
2322SDValue
2323ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2324 SmallVectorImpl<SDValue> &InVals) const {
2325 SelectionDAG &DAG = CLI.DAG;
2326 SDLoc &dl = CLI.DL;
2327 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2328 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2329 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2330 SDValue Chain = CLI.Chain;
2331 SDValue Callee = CLI.Callee;
2332 bool &isTailCall = CLI.IsTailCall;
2333 CallingConv::ID CallConv = CLI.CallConv;
2334 bool doesNotRet = CLI.DoesNotReturn;
2335 bool isVarArg = CLI.IsVarArg;
2336
2337 MachineFunction &MF = DAG.getMachineFunction();
2338 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2339 MachineFunction::CallSiteInfo CSInfo;
2340 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2341 bool isThisReturn = false;
2342 bool isCmseNSCall = false;
2343 bool isSibCall = false;
2344 bool PreferIndirect = false;
2345 bool GuardWithBTI = false;
2346
2347 // Lower 'returns_twice' calls to a pseudo-instruction.
2348 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
2349 !Subtarget->noBTIAtReturnTwice())
2350 GuardWithBTI = AFI->branchTargetEnforcement();
2351
2352 // Determine whether this is a non-secure function call.
2353 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
2354 isCmseNSCall = true;
2355
2356 // Disable tail calls if they're not supported.
2357 if (!Subtarget->supportsTailCall())
2358 isTailCall = false;
2359
2360 // For both the non-secure calls and the returns from a CMSE entry function,
2361 // the function needs to do some extra work afte r the call, or before the
2362 // return, respectively, thus it cannot end with atail call
2363 if (isCmseNSCall || AFI->isCmseNSEntryFunction())
2364 isTailCall = false;
2365
2366 if (isa<GlobalAddressSDNode>(Callee)) {
2367 // If we're optimizing for minimum size and the function is called three or
2368 // more times in this block, we can improve codesize by calling indirectly
2369 // as BLXr has a 16-bit encoding.
2370 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2371 if (CLI.CB) {
2372 auto *BB = CLI.CB->getParent();
2373 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2374 count_if(GV->users(), [&BB](const User *U) {
2375 return isa<Instruction>(U) &&
2376 cast<Instruction>(U)->getParent() == BB;
2377 }) > 2;
2378 }
2379 }
2380 if (isTailCall) {
2381 // Check if it's really possible to do a tail call.
2382 isTailCall = IsEligibleForTailCallOptimization(
2383 Callee, CallConv, isVarArg, isStructRet,
2384 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2385 PreferIndirect);
2386
2387 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2388 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2389 isSibCall = true;
2390
2391 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2392 // detected sibcalls.
2393 if (isTailCall)
2394 ++NumTailCalls;
2395 }
2396
2397 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2398 report_fatal_error("failed to perform tail call elimination on a call "
2399 "site marked musttail");
2400 // Analyze operands of the call, assigning locations to each operand.
2401 SmallVector<CCValAssign, 16> ArgLocs;
2402 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2403 *DAG.getContext());
2404 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2405
2406 // Get a count of how many bytes are to be pushed on the stack.
2407 unsigned NumBytes = CCInfo.getNextStackOffset();
2408
2409 // SPDiff is the byte offset of the call's argument area from the callee's.
2410 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2411 // by this amount for a tail call. In a sibling call it must be 0 because the
2412 // caller will deallocate the entire stack and the callee still expects its
2413 // arguments to begin at SP+0. Completely unused for non-tail calls.
2414 int SPDiff = 0;
2415
2416 if (isTailCall && !isSibCall) {
2417 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2418 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2419
2420 // Since callee will pop argument stack as a tail call, we must keep the
2421 // popped size 16-byte aligned.
2422 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2423 NumBytes = alignTo(NumBytes, StackAlign);
2424
2425 // SPDiff will be negative if this tail call requires more space than we
2426 // would automatically have in our incoming argument space. Positive if we
2427 // can actually shrink the stack.
2428 SPDiff = NumReusableBytes - NumBytes;
2429
2430 // If this call requires more stack than we have available from
2431 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2432 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2433 AFI->setArgRegsSaveSize(-SPDiff);
2434 }
2435
2436 if (isSibCall) {
2437 // For sibling tail calls, memory operands are available in our caller's stack.
2438 NumBytes = 0;
2439 } else {
2440 // Adjust the stack pointer for the new arguments...
2441 // These operations are automatically eliminated by the prolog/epilog pass
2442 Chain = DAG.getCALLSEQ_START(Chain, isTailCall ? 0 : NumBytes, 0, dl);
2443 }
2444
2445 SDValue StackPtr =
2446 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2447
2448 RegsToPassVector RegsToPass;
2449 SmallVector<SDValue, 8> MemOpChains;
2450
2451 // During a tail call, stores to the argument area must happen after all of
2452 // the function's incoming arguments have been loaded because they may alias.
2453 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2454 // there's no point in doing so repeatedly so this tracks whether that's
2455 // happened yet.
2456 bool AfterFormalArgLoads = false;
2457
2458 // Walk the register/memloc assignments, inserting copies/loads. In the case
2459 // of tail call optimization, arguments are handled later.
2460 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2461 i != e;
2462 ++i, ++realArgIdx) {
2463 CCValAssign &VA = ArgLocs[i];
2464 SDValue Arg = OutVals[realArgIdx];
2465 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2466 bool isByVal = Flags.isByVal();
2467
2468 // Promote the value if needed.
2469 switch (VA.getLocInfo()) {
2470 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2470)
;
2471 case CCValAssign::Full: break;
2472 case CCValAssign::SExt:
2473 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2474 break;
2475 case CCValAssign::ZExt:
2476 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2477 break;
2478 case CCValAssign::AExt:
2479 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2480 break;
2481 case CCValAssign::BCvt:
2482 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2483 break;
2484 }
2485
2486 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2487 Chain = DAG.getStackArgumentTokenFactor(Chain);
2488 AfterFormalArgLoads = true;
2489 }
2490
2491 // f16 arguments have their size extended to 4 bytes and passed as if they
2492 // had been copied to the LSBs of a 32-bit register.
2493 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2494 if (VA.needsCustom() &&
2495 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2496 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2497 } else {
2498 // f16 arguments could have been extended prior to argument lowering.
2499 // Mask them arguments if this is a CMSE nonsecure call.
2500 auto ArgVT = Outs[realArgIdx].ArgVT;
2501 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2502 auto LocBits = VA.getLocVT().getSizeInBits();
2503 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2504 SDValue Mask =
2505 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2506 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2507 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2508 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2509 }
2510 }
2511
2512 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2513 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2514 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2515 DAG.getConstant(0, dl, MVT::i32));
2516 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2517 DAG.getConstant(1, dl, MVT::i32));
2518
2519 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2520 StackPtr, MemOpChains, isTailCall, SPDiff);
2521
2522 VA = ArgLocs[++i]; // skip ahead to next loc
2523 if (VA.isRegLoc()) {
2524 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2525 StackPtr, MemOpChains, isTailCall, SPDiff);
2526 } else {
2527 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2527, __extension__ __PRETTY_FUNCTION__))
;
2528 SDValue DstAddr;
2529 MachinePointerInfo DstInfo;
2530 std::tie(DstAddr, DstInfo) =
2531 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2532 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2533 }
2534 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2535 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2536 StackPtr, MemOpChains, isTailCall, SPDiff);
2537 } else if (VA.isRegLoc()) {
2538 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2539 Outs[0].VT == MVT::i32) {
2540 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
2541 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
;
2542 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2543, __extension__
__PRETTY_FUNCTION__))
2543 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2543, __extension__
__PRETTY_FUNCTION__))
;
2544 isThisReturn = true;
2545 }
2546 const TargetOptions &Options = DAG.getTarget().Options;
2547 if (Options.EmitCallSiteInfo)
2548 CSInfo.emplace_back(VA.getLocReg(), i);
2549 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2550 } else if (isByVal) {
2551 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2551, __extension__ __PRETTY_FUNCTION__))
;
2552 unsigned offset = 0;
2553
2554 // True if this byval aggregate will be split between registers
2555 // and memory.
2556 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2557 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2558
2559 if (CurByValIdx < ByValArgsCount) {
2560
2561 unsigned RegBegin, RegEnd;
2562 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2563
2564 EVT PtrVT =
2565 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2566 unsigned int i, j;
2567 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2568 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2569 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2570 SDValue Load =
2571 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2572 DAG.InferPtrAlign(AddArg));
2573 MemOpChains.push_back(Load.getValue(1));
2574 RegsToPass.push_back(std::make_pair(j, Load));
2575 }
2576
2577 // If parameter size outsides register area, "offset" value
2578 // helps us to calculate stack slot for remained part properly.
2579 offset = RegEnd - RegBegin;
2580
2581 CCInfo.nextInRegsParam();
2582 }
2583
2584 if (Flags.getByValSize() > 4*offset) {
2585 auto PtrVT = getPointerTy(DAG.getDataLayout());
2586 SDValue Dst;
2587 MachinePointerInfo DstInfo;
2588 std::tie(Dst, DstInfo) =
2589 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2590 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2591 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2592 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2593 MVT::i32);
2594 SDValue AlignNode =
2595 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2596
2597 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2598 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2599 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2600 Ops));
2601 }
2602 } else {
2603 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2603, __extension__ __PRETTY_FUNCTION__))
;
2604 SDValue DstAddr;
2605 MachinePointerInfo DstInfo;
2606 std::tie(DstAddr, DstInfo) =
2607 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2608
2609 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2610 MemOpChains.push_back(Store);
2611 }
2612 }
2613
2614 if (!MemOpChains.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2616
2617 // Build a sequence of copy-to-reg nodes chained together with token chain
2618 // and flag operands which copy the outgoing args into the appropriate regs.
2619 SDValue InFlag;
2620 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2621 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2622 RegsToPass[i].second, InFlag);
2623 InFlag = Chain.getValue(1);
2624 }
2625
2626 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2627 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2628 // node so that legalize doesn't hack it.
2629 bool isDirect = false;
2630
2631 const TargetMachine &TM = getTargetMachine();
2632 const Module *Mod = MF.getFunction().getParent();
2633 const GlobalValue *GV = nullptr;
2634 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2635 GV = G->getGlobal();
2636 bool isStub =
2637 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2638
2639 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2640 bool isLocalARMFunc = false;
2641 auto PtrVt = getPointerTy(DAG.getDataLayout());
2642
2643 if (Subtarget->genLongCalls()) {
2644 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2645, __extension__
__PRETTY_FUNCTION__))
2645 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2645, __extension__
__PRETTY_FUNCTION__))
;
2646 // Handle a global address or an external symbol. If it's not one of
2647 // those, the target's already in a register, so we don't need to do
2648 // anything extra.
2649 if (isa<GlobalAddressSDNode>(Callee)) {
2650 // Create a constant pool entry for the callee address
2651 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2652 ARMConstantPoolValue *CPV =
2653 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2654
2655 // Get the address of the callee into a register
2656 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2657 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2658 Callee = DAG.getLoad(
2659 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2660 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2661 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2662 const char *Sym = S->getSymbol();
2663
2664 // Create a constant pool entry for the callee address
2665 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2666 ARMConstantPoolValue *CPV =
2667 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2668 ARMPCLabelIndex, 0);
2669 // Get the address of the callee into a register
2670 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2671 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2672 Callee = DAG.getLoad(
2673 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2674 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2675 }
2676 } else if (isa<GlobalAddressSDNode>(Callee)) {
2677 if (!PreferIndirect) {
2678 isDirect = true;
2679 bool isDef = GV->isStrongDefinitionForLinker();
2680
2681 // ARM call to a local ARM function is predicable.
2682 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2683 // tBX takes a register source operand.
2684 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2685 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2685, __extension__
__PRETTY_FUNCTION__))
;
2686 Callee = DAG.getNode(
2687 ARMISD::WrapperPIC, dl, PtrVt,
2688 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2689 Callee = DAG.getLoad(
2690 PtrVt, dl, DAG.getEntryNode(), Callee,
2691 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2692 MachineMemOperand::MODereferenceable |
2693 MachineMemOperand::MOInvariant);
2694 } else if (Subtarget->isTargetCOFF()) {
2695 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2696, __extension__
__PRETTY_FUNCTION__))
2696 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2696, __extension__
__PRETTY_FUNCTION__))
;
2697 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2698 if (GV->hasDLLImportStorageClass())
2699 TargetFlags = ARMII::MO_DLLIMPORT;
2700 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2701 TargetFlags = ARMII::MO_COFFSTUB;
2702 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2703 TargetFlags);
2704 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2705 Callee =
2706 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2707 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2708 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2709 } else {
2710 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2711 }
2712 }
2713 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2714 isDirect = true;
2715 // tBX takes a register source operand.
2716 const char *Sym = S->getSymbol();
2717 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2718 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2719 ARMConstantPoolValue *CPV =
2720 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2721 ARMPCLabelIndex, 4);
2722 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2723 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2724 Callee = DAG.getLoad(
2725 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2726 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2727 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2728 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2729 } else {
2730 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2731 }
2732 }
2733
2734 if (isCmseNSCall) {
2735 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2736, __extension__
__PRETTY_FUNCTION__))
2736 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2736, __extension__
__PRETTY_FUNCTION__))
;
2737 if (NumBytes > 0) {
2738 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2739 "call to non-secure function would "
2740 "require passing arguments on stack",
2741 dl.getDebugLoc());
2742 DAG.getContext()->diagnose(Diag);
2743 }
2744 if (isStructRet) {
2745 DiagnosticInfoUnsupported Diag(
2746 DAG.getMachineFunction().getFunction(),
2747 "call to non-secure function would return value through pointer",
2748 dl.getDebugLoc());
2749 DAG.getContext()->diagnose(Diag);
2750 }
2751 }
2752
2753 // FIXME: handle tail calls differently.
2754 unsigned CallOpc;
2755 if (Subtarget->isThumb()) {
2756 if (GuardWithBTI)
2757 CallOpc = ARMISD::t2CALL_BTI;
2758 else if (isCmseNSCall)
2759 CallOpc = ARMISD::tSECALL;
2760 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2761 CallOpc = ARMISD::CALL_NOLINK;
2762 else
2763 CallOpc = ARMISD::CALL;
2764 } else {
2765 if (!isDirect && !Subtarget->hasV5TOps())
2766 CallOpc = ARMISD::CALL_NOLINK;
2767 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2768 // Emit regular call when code size is the priority
2769 !Subtarget->hasMinSize())
2770 // "mov lr, pc; b _foo" to avoid confusing the RSP
2771 CallOpc = ARMISD::CALL_NOLINK;
2772 else
2773 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2774 }
2775
2776 // We don't usually want to end the call-sequence here because we would tidy
2777 // the frame up *after* the call, however in the ABI-changing tail-call case
2778 // we've carefully laid out the parameters so that when sp is reset they'll be
2779 // in the correct location.
2780 if (isTailCall && !isSibCall) {
2781 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InFlag, dl);
2782 InFlag = Chain.getValue(1);
2783 }
2784
2785 std::vector<SDValue> Ops;
2786 Ops.push_back(Chain);
2787 Ops.push_back(Callee);
2788
2789 if (isTailCall) {
2790 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2791 }
2792
2793 // Add argument registers to the end of the list so that they are known live
2794 // into the call.
2795 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2796 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2797 RegsToPass[i].second.getValueType()));
2798
2799 // Add a register mask operand representing the call-preserved registers.
2800 const uint32_t *Mask;
2801 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2802 if (isThisReturn) {
2803 // For 'this' returns, use the R0-preserving mask if applicable
2804 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2805 if (!Mask) {
2806 // Set isThisReturn to false if the calling convention is not one that
2807 // allows 'returned' to be modeled in this way, so LowerCallResult does
2808 // not try to pass 'this' straight through
2809 isThisReturn = false;
2810 Mask = ARI->getCallPreservedMask(MF, CallConv);
2811 }
2812 } else
2813 Mask = ARI->getCallPreservedMask(MF, CallConv);
2814
2815 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2815, __extension__
__PRETTY_FUNCTION__))
;
2816 Ops.push_back(DAG.getRegisterMask(Mask));
2817
2818 if (InFlag.getNode())
2819 Ops.push_back(InFlag);
2820
2821 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2822 if (isTailCall) {
2823 MF.getFrameInfo().setHasTailCall();
2824 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2825 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2826 return Ret;
2827 }
2828
2829 // Returns a chain and a flag for retval copy to use.
2830 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2831 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2832 InFlag = Chain.getValue(1);
2833 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2834
2835 // If we're guaranteeing tail-calls will be honoured, the callee must
2836 // pop its own argument stack on return. But this call is *not* a tail call so
2837 // we need to undo that after it returns to restore the status-quo.
2838 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2839 uint64_t CalleePopBytes =
2840 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2841
2842 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, CalleePopBytes, InFlag, dl);
2843 if (!Ins.empty())
2844 InFlag = Chain.getValue(1);
2845
2846 // Handle result values, copying them out of physregs into vregs that we
2847 // return.
2848 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2849 InVals, isThisReturn,
2850 isThisReturn ? OutVals[0] : SDValue());
2851}
2852
2853/// HandleByVal - Every parameter *after* a byval parameter is passed
2854/// on the stack. Remember the next parameter register to allocate,
2855/// and then confiscate the rest of the parameter registers to insure
2856/// this.
2857void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2858 Align Alignment) const {
2859 // Byval (as with any stack) slots are always at least 4 byte aligned.
2860 Alignment = std::max(Alignment, Align(4));
2861
2862 unsigned Reg = State->AllocateReg(GPRArgRegs);
2863 if (!Reg)
2864 return;
2865
2866 unsigned AlignInRegs = Alignment.value() / 4;
2867 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2868 for (unsigned i = 0; i < Waste; ++i)
2869 Reg = State->AllocateReg(GPRArgRegs);
2870
2871 if (!Reg)
2872 return;
2873
2874 unsigned Excess = 4 * (ARM::R4 - Reg);
2875
2876 // Special case when NSAA != SP and parameter size greater than size of
2877 // all remained GPR regs. In that case we can't split parameter, we must
2878 // send it to stack. We also must set NCRN to R4, so waste all
2879 // remained registers.
2880 const unsigned NSAAOffset = State->getNextStackOffset();
2881 if (NSAAOffset != 0 && Size > Excess) {
2882 while (State->AllocateReg(GPRArgRegs))
2883 ;
2884 return;
2885 }
2886
2887 // First register for byval parameter is the first register that wasn't
2888 // allocated before this method call, so it would be "reg".
2889 // If parameter is small enough to be saved in range [reg, r4), then
2890 // the end (first after last) register would be reg + param-size-in-regs,
2891 // else parameter would be splitted between registers and stack,
2892 // end register would be r4 in this case.
2893 unsigned ByValRegBegin = Reg;
2894 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2895 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2896 // Note, first register is allocated in the beginning of function already,
2897 // allocate remained amount of registers we need.
2898 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2899 State->AllocateReg(GPRArgRegs);
2900 // A byval parameter that is split between registers and memory needs its
2901 // size truncated here.
2902 // In the case where the entire structure fits in registers, we set the
2903 // size in memory to zero.
2904 Size = std::max<int>(Size - Excess, 0);
2905}
2906
2907/// MatchingStackOffset - Return true if the given stack call argument is
2908/// already available in the same position (relatively) of the caller's
2909/// incoming argument stack.
2910static
2911bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2912 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2913 const TargetInstrInfo *TII) {
2914 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2915 int FI = std::numeric_limits<int>::max();
2916 if (Arg.getOpcode() == ISD::CopyFromReg) {
2917 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2918 if (!Register::isVirtualRegister(VR))
2919 return false;
2920 MachineInstr *Def = MRI->getVRegDef(VR);
2921 if (!Def)
2922 return false;
2923 if (!Flags.isByVal()) {
2924 if (!TII->isLoadFromStackSlot(*Def, FI))
2925 return false;
2926 } else {
2927 return false;
2928 }
2929 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2930 if (Flags.isByVal())
2931 // ByVal argument is passed in as a pointer but it's now being
2932 // dereferenced. e.g.
2933 // define @foo(%struct.X* %A) {
2934 // tail call @bar(%struct.X* byval %A)
2935 // }
2936 return false;
2937 SDValue Ptr = Ld->getBasePtr();
2938 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2939 if (!FINode)
2940 return false;
2941 FI = FINode->getIndex();
2942 } else
2943 return false;
2944
2945 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2945, __extension__
__PRETTY_FUNCTION__))
;
2946 if (!MFI.isFixedObjectIndex(FI))
2947 return false;
2948 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2949}
2950
2951/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2952/// for tail call optimization. Targets which want to do tail call
2953/// optimization should implement this function.
2954bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2955 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2956 bool isCalleeStructRet, bool isCallerStructRet,
2957 const SmallVectorImpl<ISD::OutputArg> &Outs,
2958 const SmallVectorImpl<SDValue> &OutVals,
2959 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2960 const bool isIndirect) const {
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 const Function &CallerF = MF.getFunction();
2963 CallingConv::ID CallerCC = CallerF.getCallingConv();
2964
2965 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2965, __extension__
__PRETTY_FUNCTION__))
;
2966
2967 // Indirect tail calls cannot be optimized for Thumb1 if the args
2968 // to the call take up r0-r3. The reason is that there are no legal registers
2969 // left to hold the pointer to the function to be called.
2970 // Similarly, if the function uses return address sign and authentication,
2971 // r12 is needed to hold the PAC and is not available to hold the callee
2972 // address.
2973 if (Outs.size() >= 4 &&
2974 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect)) {
2975 if (Subtarget->isThumb1Only())
2976 return false;
2977 // Conservatively assume the function spills LR.
2978 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true))
2979 return false;
2980 }
2981
2982 // Look for obvious safe cases to perform tail call optimization that do not
2983 // require ABI changes. This is what gcc calls sibcall.
2984
2985 // Exception-handling functions need a special set of instructions to indicate
2986 // a return to the hardware. Tail-calling another function would probably
2987 // break this.
2988 if (CallerF.hasFnAttribute("interrupt"))
2989 return false;
2990
2991 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2992 return CalleeCC == CallerCC;
2993
2994 // Also avoid sibcall optimization if either caller or callee uses struct
2995 // return semantics.
2996 if (isCalleeStructRet || isCallerStructRet)
2997 return false;
2998
2999 // Externally-defined functions with weak linkage should not be
3000 // tail-called on ARM when the OS does not support dynamic
3001 // pre-emption of symbols, as the AAELF spec requires normal calls
3002 // to undefined weak functions to be replaced with a NOP or jump to the
3003 // next instruction. The behaviour of branch instructions in this
3004 // situation (as used for tail calls) is implementation-defined, so we
3005 // cannot rely on the linker replacing the tail call with a return.
3006 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3007 const GlobalValue *GV = G->getGlobal();
3008 const Triple &TT = getTargetMachine().getTargetTriple();
3009 if (GV->hasExternalWeakLinkage() &&
3010 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
3011 return false;
3012 }
3013
3014 // Check that the call results are passed in the same way.
3015 LLVMContext &C = *DAG.getContext();
3016 if (!CCState::resultsCompatible(
3017 getEffectiveCallingConv(CalleeCC, isVarArg),
3018 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
3019 CCAssignFnForReturn(CalleeCC, isVarArg),
3020 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
3021 return false;
3022 // The callee has to preserve all registers the caller needs to preserve.
3023 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3024 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3025 if (CalleeCC != CallerCC) {
3026 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3027 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3028 return false;
3029 }
3030
3031 // If Caller's vararg or byval argument has been split between registers and
3032 // stack, do not perform tail call, since part of the argument is in caller's
3033 // local frame.
3034 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
3035 if (AFI_Caller->getArgRegsSaveSize())
3036 return false;
3037
3038 // If the callee takes no arguments then go on to check the results of the
3039 // call.
3040 if (!Outs.empty()) {
3041 // Check if stack adjustment is needed. For now, do not do this if any
3042 // argument is passed on the stack.
3043 SmallVector<CCValAssign, 16> ArgLocs;
3044 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3045 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3046 if (CCInfo.getNextStackOffset()) {
3047 // Check if the arguments are already laid out in the right way as
3048 // the caller's fixed stack objects.
3049 MachineFrameInfo &MFI = MF.getFrameInfo();
3050 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3051 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3052 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
3053 i != e;
3054 ++i, ++realArgIdx) {
3055 CCValAssign &VA = ArgLocs[i];
3056 EVT RegVT = VA.getLocVT();
3057 SDValue Arg = OutVals[realArgIdx];
3058 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3059 if (VA.getLocInfo() == CCValAssign::Indirect)
3060 return false;
3061 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3062 // f64 and vector types are split into multiple registers or
3063 // register/stack-slot combinations. The types will not match
3064 // the registers; give up on memory f64 refs until we figure
3065 // out what to do about this.
3066 if (!VA.isRegLoc())
3067 return false;
3068 if (!ArgLocs[++i].isRegLoc())
3069 return false;
3070 if (RegVT == MVT::v2f64) {
3071 if (!ArgLocs[++i].isRegLoc())
3072 return false;
3073 if (!ArgLocs[++i].isRegLoc())
3074 return false;
3075 }
3076 } else if (!VA.isRegLoc()) {
3077 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3078 MFI, MRI, TII))
3079 return false;
3080 }
3081 }
3082 }
3083
3084 const MachineRegisterInfo &MRI = MF.getRegInfo();
3085 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3086 return false;
3087 }
3088
3089 return true;
3090}
3091
3092bool
3093ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3094 MachineFunction &MF, bool isVarArg,
3095 const SmallVectorImpl<ISD::OutputArg> &Outs,
3096 LLVMContext &Context) const {
3097 SmallVector<CCValAssign, 16> RVLocs;
3098 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3099 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3100}
3101
3102static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3103 const SDLoc &DL, SelectionDAG &DAG) {
3104 const MachineFunction &MF = DAG.getMachineFunction();
3105 const Function &F = MF.getFunction();
3106
3107 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3108
3109 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3110 // version of the "preferred return address". These offsets affect the return
3111 // instruction if this is a return from PL1 without hypervisor extensions.
3112 // IRQ/FIQ: +4 "subs pc, lr, #4"
3113 // SWI: 0 "subs pc, lr, #0"
3114 // ABORT: +4 "subs pc, lr, #4"
3115 // UNDEF: +4/+2 "subs pc, lr, #0"
3116 // UNDEF varies depending on where the exception came from ARM or Thumb
3117 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3118
3119 int64_t LROffset;
3120 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3121 IntKind == "ABORT")
3122 LROffset = 4;
3123 else if (IntKind == "SWI" || IntKind == "UNDEF")
3124 LROffset = 0;
3125 else
3126 report_fatal_error("Unsupported interrupt attribute. If present, value "
3127 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3128
3129 RetOps.insert(RetOps.begin() + 1,
3130 DAG.getConstant(LROffset, DL, MVT::i32, false));
3131
3132 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3133}
3134
3135SDValue
3136ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3137 bool isVarArg,
3138 const SmallVectorImpl<ISD::OutputArg> &Outs,
3139 const SmallVectorImpl<SDValue> &OutVals,
3140 const SDLoc &dl, SelectionDAG &DAG) const {
3141 // CCValAssign - represent the assignment of the return value to a location.
3142 SmallVector<CCValAssign, 16> RVLocs;
3143
3144 // CCState - Info about the registers and stack slots.
3145 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3146 *DAG.getContext());
3147
3148 // Analyze outgoing return values.
3149 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3150
3151 SDValue Flag;
3152 SmallVector<SDValue, 4> RetOps;
3153 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3154 bool isLittleEndian = Subtarget->isLittle();
3155
3156 MachineFunction &MF = DAG.getMachineFunction();
3157 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3158 AFI->setReturnRegsCount(RVLocs.size());
3159
3160 // Report error if cmse entry function returns structure through first ptr arg.
3161 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3162 // Note: using an empty SDLoc(), as the first line of the function is a
3163 // better place to report than the last line.
3164 DiagnosticInfoUnsupported Diag(
3165 DAG.getMachineFunction().getFunction(),
3166 "secure entry function would return value through pointer",
3167 SDLoc().getDebugLoc());
3168 DAG.getContext()->diagnose(Diag);
3169 }
3170
3171 // Copy the result values into the output registers.
3172 for (unsigned i = 0, realRVLocIdx = 0;
3173 i != RVLocs.size();
3174 ++i, ++realRVLocIdx) {
3175 CCValAssign &VA = RVLocs[i];
3176 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3176, __extension__
__PRETTY_FUNCTION__))
;
3177
3178 SDValue Arg = OutVals[realRVLocIdx];
3179 bool ReturnF16 = false;
3180
3181 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3182 // Half-precision return values can be returned like this:
3183 //
3184 // t11 f16 = fadd ...
3185 // t12: i16 = bitcast t11
3186 // t13: i32 = zero_extend t12
3187 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3188 //
3189 // to avoid code generation for bitcasts, we simply set Arg to the node
3190 // that produces the f16 value, t11 in this case.
3191 //
3192 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3193 SDValue ZE = Arg.getOperand(0);
3194 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3195 SDValue BC = ZE.getOperand(0);
3196 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3197 Arg = BC.getOperand(0);
3198 ReturnF16 = true;
3199 }
3200 }
3201 }
3202 }
3203
3204 switch (VA.getLocInfo()) {
3205 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3205)
;
3206 case CCValAssign::Full: break;
3207 case CCValAssign::BCvt:
3208 if (!ReturnF16)
3209 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3210 break;
3211 }
3212
3213 // Mask f16 arguments if this is a CMSE nonsecure entry.
3214 auto RetVT = Outs[realRVLocIdx].ArgVT;
3215 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3216 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3217 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3218 } else {
3219 auto LocBits = VA.getLocVT().getSizeInBits();
3220 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3221 SDValue Mask =
3222 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3223 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3224 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3225 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3226 }
3227 }
3228
3229 if (VA.needsCustom() &&
3230 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3231 if (VA.getLocVT() == MVT::v2f64) {
3232 // Extract the first half and return it in two registers.
3233 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3234 DAG.getConstant(0, dl, MVT::i32));
3235 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3236 DAG.getVTList(MVT::i32, MVT::i32), Half);
3237
3238 Chain =
3239 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3240 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3241 Flag = Chain.getValue(1);
3242 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3243 VA = RVLocs[++i]; // skip ahead to next loc
3244 Chain =
3245 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3246 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3247 Flag = Chain.getValue(1);
3248 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3249 VA = RVLocs[++i]; // skip ahead to next loc
3250
3251 // Extract the 2nd half and fall through to handle it as an f64 value.
3252 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3253 DAG.getConstant(1, dl, MVT::i32));
3254 }
3255 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3256 // available.
3257 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3258 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3259 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3260 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3261 Flag = Chain.getValue(1);
3262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3263 VA = RVLocs[++i]; // skip ahead to next loc
3264 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3265 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3266 } else
3267 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3268
3269 // Guarantee that all emitted copies are
3270 // stuck together, avoiding something bad.
3271 Flag = Chain.getValue(1);
3272 RetOps.push_back(DAG.getRegister(
3273 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3274 }
3275 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3276 const MCPhysReg *I =
3277 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3278 if (I) {
3279 for (; *I; ++I) {
3280 if (ARM::GPRRegClass.contains(*I))
3281 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3282 else if (ARM::DPRRegClass.contains(*I))
3283 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3284 else
3285 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3285)
;
3286 }
3287 }
3288
3289 // Update chain and glue.
3290 RetOps[0] = Chain;
3291 if (Flag.getNode())
3292 RetOps.push_back(Flag);
3293
3294 // CPUs which aren't M-class use a special sequence to return from
3295 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3296 // though we use "subs pc, lr, #N").
3297 //
3298 // M-class CPUs actually use a normal return sequence with a special
3299 // (hardware-provided) value in LR, so the normal code path works.
3300 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3301 !Subtarget->isMClass()) {
3302 if (Subtarget->isThumb1Only())
3303 report_fatal_error("interrupt attribute is not supported in Thumb1");
3304 return LowerInterruptReturn(RetOps, dl, DAG);
3305 }
3306
3307 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3308 ARMISD::RET_FLAG;
3309 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3310}
3311
3312bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3313 if (N->getNumValues() != 1)
3314 return false;
3315 if (!N->hasNUsesOfValue(1, 0))
3316 return false;
3317
3318 SDValue TCChain = Chain;
3319 SDNode *Copy = *N->use_begin();
3320 if (Copy->getOpcode() == ISD::CopyToReg) {
3321 // If the copy has a glue operand, we conservatively assume it isn't safe to
3322 // perform a tail call.
3323 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3324 return false;
3325 TCChain = Copy->getOperand(0);
3326 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3327 SDNode *VMov = Copy;
3328 // f64 returned in a pair of GPRs.
3329 SmallPtrSet<SDNode*, 2> Copies;
3330 for (SDNode *U : VMov->uses()) {
3331 if (U->getOpcode() != ISD::CopyToReg)
3332 return false;
3333 Copies.insert(U);
3334 }
3335 if (Copies.size() > 2)
3336 return false;
3337
3338 for (SDNode *U : VMov->uses()) {
3339 SDValue UseChain = U->getOperand(0);
3340 if (Copies.count(UseChain.getNode()))
3341 // Second CopyToReg
3342 Copy = U;
3343 else {
3344 // We are at the top of this chain.
3345 // If the copy has a glue operand, we conservatively assume it
3346 // isn't safe to perform a tail call.
3347 if (U->getOperand(U->getNumOperands() - 1).getValueType() == MVT::Glue)
3348 return false;
3349 // First CopyToReg
3350 TCChain = UseChain;
3351 }
3352 }
3353 } else if (Copy->getOpcode() == ISD::BITCAST) {
3354 // f32 returned in a single GPR.
3355 if (!Copy->hasOneUse())
3356 return false;
3357 Copy = *Copy->use_begin();
3358 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3359 return false;
3360 // If the copy has a glue operand, we conservatively assume it isn't safe to
3361 // perform a tail call.
3362 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3363 return false;
3364 TCChain = Copy->getOperand(0);
3365 } else {
3366 return false;
3367 }
3368
3369 bool HasRet = false;
3370 for (const SDNode *U : Copy->uses()) {
3371 if (U->getOpcode() != ARMISD::RET_FLAG &&
3372 U->getOpcode() != ARMISD::INTRET_FLAG)
3373 return false;
3374 HasRet = true;
3375 }
3376
3377 if (!HasRet)
3378 return false;
3379
3380 Chain = TCChain;
3381 return true;
3382}
3383
3384bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3385 if (!Subtarget->supportsTailCall())
3386 return false;
3387
3388 if (!CI->isTailCall())
3389 return false;
3390
3391 return true;
3392}
3393
3394// Trying to write a 64 bit value so need to split into two 32 bit values first,
3395// and pass the lower and high parts through.
3396static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3397 SDLoc DL(Op);
3398 SDValue WriteValue = Op->getOperand(2);
3399
3400 // This function is only supposed to be called for i64 type argument.
3401 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3402, __extension__
__PRETTY_FUNCTION__))
3402 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3402, __extension__
__PRETTY_FUNCTION__))
;
3403
3404 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3405 DAG.getConstant(0, DL, MVT::i32));
3406 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3407 DAG.getConstant(1, DL, MVT::i32));
3408 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3409 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3410}
3411
3412// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3413// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3414// one of the above mentioned nodes. It has to be wrapped because otherwise
3415// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3416// be used to form addressing mode. These wrapped nodes will be selected
3417// into MOVi.
3418SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3419 SelectionDAG &DAG) const {
3420 EVT PtrVT = Op.getValueType();
3421 // FIXME there is no actual debug info here
3422 SDLoc dl(Op);
3423 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3424 SDValue Res;
3425
3426 // When generating execute-only code Constant Pools must be promoted to the
3427 // global data section. It's a bit ugly that we can't share them across basic
3428 // blocks, but this way we guarantee that execute-only behaves correct with
3429 // position-independent addressing modes.
3430 if (Subtarget->genExecuteOnly()) {
3431 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3432 auto T = const_cast<Type*>(CP->getType());
3433 auto C = const_cast<Constant*>(CP->getConstVal());
3434 auto M = const_cast<Module*>(DAG.getMachineFunction().
3435 getFunction().getParent());
3436 auto GV = new GlobalVariable(
3437 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3438 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3439 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3440 Twine(AFI->createPICLabelUId())
3441 );
3442 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3443 dl, PtrVT);
3444 return LowerGlobalAddress(GA, DAG);
3445 }
3446
3447 // The 16-bit ADR instruction can only encode offsets that are multiples of 4,
3448 // so we need to align to at least 4 bytes when we don't have 32-bit ADR.
3449 Align CPAlign = CP->getAlign();
3450 if (Subtarget->isThumb1Only())
3451 CPAlign = std::max(CPAlign, Align(4));
3452 if (CP->isMachineConstantPoolEntry())
3453 Res =
3454 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CPAlign);
3455 else
3456 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CPAlign);
3457 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3458}
3459
3460unsigned ARMTargetLowering::getJumpTableEncoding() const {
3461 return MachineJumpTableInfo::EK_Inline;
3462}
3463
3464SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3465 SelectionDAG &DAG) const {
3466 MachineFunction &MF = DAG.getMachineFunction();
3467 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3468 unsigned ARMPCLabelIndex = 0;
3469 SDLoc DL(Op);
3470 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3471 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3472 SDValue CPAddr;
3473 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3474 if (!IsPositionIndependent) {
3475 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3476 } else {
3477 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3478 ARMPCLabelIndex = AFI->createPICLabelUId();
3479 ARMConstantPoolValue *CPV =
3480 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3481 ARMCP::CPBlockAddress, PCAdj);
3482 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3483 }
3484 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3485 SDValue Result = DAG.getLoad(
3486 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3487 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3488 if (!IsPositionIndependent)
3489 return Result;
3490 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3491 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3492}
3493
3494/// Convert a TLS address reference into the correct sequence of loads
3495/// and calls to compute the variable's address for Darwin, and return an
3496/// SDValue containing the final node.
3497
3498/// Darwin only has one TLS scheme which must be capable of dealing with the
3499/// fully general situation, in the worst case. This means:
3500/// + "extern __thread" declaration.
3501/// + Defined in a possibly unknown dynamic library.
3502///
3503/// The general system is that each __thread variable has a [3 x i32] descriptor
3504/// which contains information used by the runtime to calculate the address. The
3505/// only part of this the compiler needs to know about is the first word, which
3506/// contains a function pointer that must be called with the address of the
3507/// entire descriptor in "r0".
3508///
3509/// Since this descriptor may be in a different unit, in general access must
3510/// proceed along the usual ARM rules. A common sequence to produce is:
3511///
3512/// movw rT1, :lower16:_var$non_lazy_ptr
3513/// movt rT1, :upper16:_var$non_lazy_ptr
3514/// ldr r0, [rT1]
3515/// ldr rT2, [r0]
3516/// blx rT2
3517/// [...address now in r0...]
3518SDValue
3519ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3520 SelectionDAG &DAG) const {
3521 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3522, __extension__
__PRETTY_FUNCTION__))
3522 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3522, __extension__
__PRETTY_FUNCTION__))
;
3523 SDLoc DL(Op);
3524
3525 // First step is to get the address of the actua global symbol. This is where
3526 // the TLS descriptor lives.
3527 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3528
3529 // The first entry in the descriptor is a function pointer that we must call
3530 // to obtain the address of the variable.
3531 SDValue Chain = DAG.getEntryNode();
3532 SDValue FuncTLVGet = DAG.getLoad(
3533 MVT::i32, DL, Chain, DescAddr,
3534 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3535 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3536 MachineMemOperand::MOInvariant);
3537 Chain = FuncTLVGet.getValue(1);
3538
3539 MachineFunction &F = DAG.getMachineFunction();
3540 MachineFrameInfo &MFI = F.getFrameInfo();
3541 MFI.setAdjustsStack(true);
3542
3543 // TLS calls preserve all registers except those that absolutely must be
3544 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3545 // silly).
3546 auto TRI =
3547 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3548 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3549 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3550
3551 // Finally, we can make the call. This is just a degenerate version of a
3552 // normal AArch64 call node: r0 takes the address of the descriptor, and
3553 // returns the address of the variable in this thread.
3554 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3555 Chain =
3556 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3557 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3558 DAG.getRegisterMask(Mask), Chain.getValue(1));
3559 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3560}
3561
3562SDValue
3563ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3564 SelectionDAG &DAG) const {
3565 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3565, __extension__
__PRETTY_FUNCTION__))
;
3566
3567 SDValue Chain = DAG.getEntryNode();
3568 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3569 SDLoc DL(Op);
3570
3571 // Load the current TEB (thread environment block)
3572 SDValue Ops[] = {Chain,
3573 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3574 DAG.getTargetConstant(15, DL, MVT::i32),
3575 DAG.getTargetConstant(0, DL, MVT::i32),
3576 DAG.getTargetConstant(13, DL, MVT::i32),
3577 DAG.getTargetConstant(0, DL, MVT::i32),
3578 DAG.getTargetConstant(2, DL, MVT::i32)};
3579 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3580 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3581
3582 SDValue TEB = CurrentTEB.getValue(0);
3583 Chain = CurrentTEB.getValue(1);
3584
3585 // Load the ThreadLocalStoragePointer from the TEB
3586 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3587 SDValue TLSArray =
3588 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3589 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3590
3591 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3592 // offset into the TLSArray.
3593
3594 // Load the TLS index from the C runtime
3595 SDValue TLSIndex =
3596 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3597 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3598 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3599
3600 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3601 DAG.getConstant(2, DL, MVT::i32));
3602 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3603 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3604 MachinePointerInfo());
3605
3606 // Get the offset of the start of the .tls section (section base)
3607 const auto *GA = cast<GlobalAddressSDNode>(Op);
3608 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3609 SDValue Offset = DAG.getLoad(
3610 PtrVT, DL, Chain,
3611 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3612 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3613 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3614
3615 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3616}
3617
3618// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3619SDValue
3620ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3621 SelectionDAG &DAG) const {
3622 SDLoc dl(GA);
3623 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3624 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3627 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3628 ARMConstantPoolValue *CPV =
3629 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3630 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3631 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3632 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3633 Argument = DAG.getLoad(
3634 PtrVT, dl, DAG.getEntryNode(), Argument,
3635 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3636 SDValue Chain = Argument.getValue(1);
3637
3638 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3639 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3640
3641 // call __tls_get_addr.
3642 ArgListTy Args;
3643 ArgListEntry Entry;
3644 Entry.Node = Argument;
3645 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3646 Args.push_back(Entry);
3647
3648 // FIXME: is there useful debug info available here?
3649 TargetLowering::CallLoweringInfo CLI(DAG);
3650 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3651 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3652 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3653
3654 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3655 return CallResult.first;
3656}
3657
3658// Lower ISD::GlobalTLSAddress using the "initial exec" or
3659// "local exec" model.
3660SDValue
3661ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3662 SelectionDAG &DAG,
3663 TLSModel::Model model) const {
3664 const GlobalValue *GV = GA->getGlobal();
3665 SDLoc dl(GA);
3666 SDValue Offset;
3667 SDValue Chain = DAG.getEntryNode();
3668 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3669 // Get the Thread Pointer
3670 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3671
3672 if (model == TLSModel::InitialExec) {
3673 MachineFunction &MF = DAG.getMachineFunction();
3674 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3675 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3676 // Initial exec model.
3677 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3678 ARMConstantPoolValue *CPV =
3679 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3680 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3681 true);
3682 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3683 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3684 Offset = DAG.getLoad(
3685 PtrVT, dl, Chain, Offset,
3686 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3687 Chain = Offset.getValue(1);
3688
3689 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3690 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3691
3692 Offset = DAG.getLoad(
3693 PtrVT, dl, Chain, Offset,
3694 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3695 } else {
3696 // local exec model
3697 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3697, __extension__ __PRETTY_FUNCTION__))
;
3698 ARMConstantPoolValue *CPV =
3699 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3700 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3701 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3702 Offset = DAG.getLoad(
3703 PtrVT, dl, Chain, Offset,
3704 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3705 }
3706
3707 // The address of the thread local variable is the add of the thread
3708 // pointer with the offset of the variable.
3709 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3710}
3711
3712SDValue
3713ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3714 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3715 if (DAG.getTarget().useEmulatedTLS())
3716 return LowerToTLSEmulatedModel(GA, DAG);
3717
3718 if (Subtarget->isTargetDarwin())
3719 return LowerGlobalTLSAddressDarwin(Op, DAG);
3720
3721 if (Subtarget->isTargetWindows())
3722 return LowerGlobalTLSAddressWindows(Op, DAG);
3723
3724 // TODO: implement the "local dynamic" model
3725 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3725, __extension__
__PRETTY_FUNCTION__))
;
3726 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3727
3728 switch (model) {
3729 case TLSModel::GeneralDynamic:
3730 case TLSModel::LocalDynamic:
3731 return LowerToTLSGeneralDynamicModel(GA, DAG);
3732 case TLSModel::InitialExec:
3733 case TLSModel::LocalExec:
3734 return LowerToTLSExecModels(GA, DAG, model);
3735 }
3736 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3736)
;
3737}
3738
3739/// Return true if all users of V are within function F, looking through
3740/// ConstantExprs.
3741static bool allUsersAreInFunction(const Value *V, const Function *F) {
3742 SmallVector<const User*,4> Worklist(V->users());
3743 while (!Worklist.empty()) {
3744 auto *U = Worklist.pop_back_val();
3745 if (isa<ConstantExpr>(U)) {
3746 append_range(Worklist, U->users());
3747 continue;
3748 }
3749
3750 auto *I = dyn_cast<Instruction>(U);
3751 if (!I || I->getParent()->getParent() != F)
3752 return false;
3753 }
3754 return true;
3755}
3756
3757static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3758 const GlobalValue *GV, SelectionDAG &DAG,
3759 EVT PtrVT, const SDLoc &dl) {
3760 // If we're creating a pool entry for a constant global with unnamed address,
3761 // and the global is small enough, we can emit it inline into the constant pool
3762 // to save ourselves an indirection.
3763 //
3764 // This is a win if the constant is only used in one function (so it doesn't
3765 // need to be duplicated) or duplicating the constant wouldn't increase code
3766 // size (implying the constant is no larger than 4 bytes).
3767 const Function &F = DAG.getMachineFunction().getFunction();
3768
3769 // We rely on this decision to inline being idemopotent and unrelated to the
3770 // use-site. We know that if we inline a variable at one use site, we'll
3771 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3772 // doesn't know about this optimization, so bail out if it's enabled else
3773 // we could decide to inline here (and thus never emit the GV) but require
3774 // the GV from fast-isel generated code.
3775 if (!EnableConstpoolPromotion ||
3776 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3777 return SDValue();
3778
3779 auto *GVar = dyn_cast<GlobalVariable>(GV);
3780 if (!GVar || !GVar->hasInitializer() ||
3781 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3782 !GVar->hasLocalLinkage())
3783 return SDValue();
3784
3785 // If we inline a value that contains relocations, we move the relocations
3786 // from .data to .text. This is not allowed in position-independent code.
3787 auto *Init = GVar->getInitializer();
3788 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3789 Init->needsDynamicRelocation())
3790 return SDValue();
3791
3792 // The constant islands pass can only really deal with alignment requests
3793 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3794 // any type wanting greater alignment requirements than 4 bytes. We also
3795 // can only promote constants that are multiples of 4 bytes in size or
3796 // are paddable to a multiple of 4. Currently we only try and pad constants
3797 // that are strings for simplicity.
3798 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3799 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3800 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3801 unsigned RequiredPadding = 4 - (Size % 4);
3802 bool PaddingPossible =
3803 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3804 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3805 Size == 0)
3806 return SDValue();
3807
3808 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3809 MachineFunction &MF = DAG.getMachineFunction();
3810 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3811
3812 // We can't bloat the constant pool too much, else the ConstantIslands pass
3813 // may fail to converge. If we haven't promoted this global yet (it may have
3814 // multiple uses), and promoting it would increase the constant pool size (Sz
3815 // > 4), ensure we have space to do so up to MaxTotal.
3816 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3817 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3818 ConstpoolPromotionMaxTotal)
3819 return SDValue();
3820
3821 // This is only valid if all users are in a single function; we can't clone
3822 // the constant in general. The LLVM IR unnamed_addr allows merging
3823 // constants, but not cloning them.
3824 //
3825 // We could potentially allow cloning if we could prove all uses of the
3826 // constant in the current function don't care about the address, like
3827 // printf format strings. But that isn't implemented for now.
3828 if (!allUsersAreInFunction(GVar, &F))
3829 return SDValue();
3830
3831 // We're going to inline this global. Pad it out if needed.
3832 if (RequiredPadding != 4) {
3833 StringRef S = CDAInit->getAsString();
3834
3835 SmallVector<uint8_t,16> V(S.size());
3836 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3837 while (RequiredPadding--)
3838 V.push_back(0);
3839 Init = ConstantDataArray::get(*DAG.getContext(), V);
3840 }
3841
3842 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3843 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3844 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3845 AFI->markGlobalAsPromotedToConstantPool(GVar);
3846 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3847 PaddedSize - 4);
3848 }
3849 ++NumConstpoolPromoted;
3850 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3851}
3852
3853bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3854 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3855 if (!(GV = GA->getAliaseeObject()))
3856 return false;
3857 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3858 return V->isConstant();
3859 return isa<Function>(GV);
3860}
3861
3862SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3863 SelectionDAG &DAG) const {
3864 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3865 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3865)
;
3866 case Triple::COFF:
3867 return LowerGlobalAddressWindows(Op, DAG);
3868 case Triple::ELF:
3869 return LowerGlobalAddressELF(Op, DAG);
3870 case Triple::MachO:
3871 return LowerGlobalAddressDarwin(Op, DAG);
3872 }
3873}
3874
3875SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3876 SelectionDAG &DAG) const {
3877 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3878 SDLoc dl(Op);
3879 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3880 const TargetMachine &TM = getTargetMachine();
3881 bool IsRO = isReadOnly(GV);
3882
3883 // promoteToConstantPool only if not generating XO text section
3884 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3885 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3886 return V;
3887
3888 if (isPositionIndependent()) {
3889 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3890 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3891 UseGOT_PREL ? ARMII::MO_GOT : 0);
3892 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3893 if (UseGOT_PREL)
3894 Result =
3895 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3896 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3897 return Result;
3898 } else if (Subtarget->isROPI() && IsRO) {
3899 // PC-relative.
3900 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3901 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3902 return Result;
3903 } else if (Subtarget->isRWPI() && !IsRO) {
3904 // SB-relative.
3905 SDValue RelAddr;
3906 if (Subtarget->useMovt()) {
3907 ++NumMovwMovt;
3908 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3909 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3910 } else { // use literal pool for address constant
3911 ARMConstantPoolValue *CPV =
3912 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3913 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3914 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3915 RelAddr = DAG.getLoad(
3916 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3917 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3918 }
3919 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3920 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3921 return Result;
3922 }
3923
3924 // If we have T2 ops, we can materialize the address directly via movt/movw
3925 // pair. This is always cheaper.
3926 if (Subtarget->useMovt()) {
3927 ++NumMovwMovt;
3928 // FIXME: Once remat is capable of dealing with instructions with register
3929 // operands, expand this into two nodes.
3930 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3931 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3932 } else {
3933 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3934 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3935 return DAG.getLoad(
3936 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3937 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3938 }
3939}
3940
3941SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3942 SelectionDAG &DAG) const {
3943 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3944, __extension__
__PRETTY_FUNCTION__))
3944 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3944, __extension__
__PRETTY_FUNCTION__))
;
3945 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3946 SDLoc dl(Op);
3947 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3948
3949 if (Subtarget->useMovt())
3950 ++NumMovwMovt;
3951
3952 // FIXME: Once remat is capable of dealing with instructions with register
3953 // operands, expand this into multiple nodes
3954 unsigned Wrapper =
3955 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3956
3957 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3958 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3959
3960 if (Subtarget->isGVIndirectSymbol(GV))
3961 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3962 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3963 return Result;
3964}
3965
3966SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3967 SelectionDAG &DAG) const {
3968 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3968, __extension__
__PRETTY_FUNCTION__))
;
3969 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3970, __extension__
__PRETTY_FUNCTION__))
3970 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3970, __extension__
__PRETTY_FUNCTION__))
;
3971 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3972, __extension__
__PRETTY_FUNCTION__))
3972 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3972, __extension__
__PRETTY_FUNCTION__))
;
3973
3974 const TargetMachine &TM = getTargetMachine();
3975 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3976 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3977 if (GV->hasDLLImportStorageClass())
3978 TargetFlags = ARMII::MO_DLLIMPORT;
3979 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3980 TargetFlags = ARMII::MO_COFFSTUB;
3981 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3982 SDValue Result;
3983 SDLoc DL(Op);
3984
3985 ++NumMovwMovt;
3986
3987 // FIXME: Once remat is capable of dealing with instructions with register
3988 // operands, expand this into two nodes.
3989 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3990 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3991 TargetFlags));
3992 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3993 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3994 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3995 return Result;
3996}
3997
3998SDValue
3999ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
4000 SDLoc dl(Op);
4001 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
4002 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
4003 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
4004 Op.getOperand(1), Val);
4005}
4006
4007SDValue
4008ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
4009 SDLoc dl(Op);
4010 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
4011 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
4012}
4013
4014SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
4015 SelectionDAG &DAG) const {
4016 SDLoc dl(Op);
4017 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
4018 Op.getOperand(0));
4019}
4020
4021SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4022 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
4023 unsigned IntNo =
4024 cast<ConstantSDNode>(
4025 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4026 ->getZExtValue();
4027 switch (IntNo) {
4028 default:
4029 return SDValue(); // Don't custom lower most intrinsics.
4030 case Intrinsic::arm_gnu_eabi_mcount: {
4031 MachineFunction &MF = DAG.getMachineFunction();
4032 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4033 SDLoc dl(Op);
4034 SDValue Chain = Op.getOperand(0);
4035 // call "\01__gnu_mcount_nc"
4036 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
4037 const uint32_t *Mask =
4038 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
4039 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4039, __extension__
__PRETTY_FUNCTION__))
;
4040 // Mark LR an implicit live-in.
4041 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4042 SDValue ReturnAddress =
4043 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
4044 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
4045 SDValue Callee =
4046 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
4047 SDValue RegisterMask = DAG.getRegisterMask(Mask);
4048 if (Subtarget->isThumb())
4049 return SDValue(
4050 DAG.getMachineNode(
4051 ARM::tBL_PUSHLR, dl, ResultTys,
4052 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
4053 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4054 0);
4055 return SDValue(
4056 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
4057 {ReturnAddress, Callee, RegisterMask, Chain}),
4058 0);
4059 }
4060 }
4061}
4062
4063SDValue
4064ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4065 const ARMSubtarget *Subtarget) const {
4066 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4067 SDLoc dl(Op);
4068 switch (IntNo) {
4069 default: return SDValue(); // Don't custom lower most intrinsics.
4070 case Intrinsic::thread_pointer: {
4071 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4072 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4073 }
4074 case Intrinsic::arm_cls: {
4075 const SDValue &Operand = Op.getOperand(1);
4076 const EVT VTy = Op.getValueType();
4077 SDValue SRA =
4078 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4079 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4080 SDValue SHL =
4081 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4082 SDValue OR =
4083 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4084 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4085 return Result;
4086 }
4087 case Intrinsic::arm_cls64: {
4088 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4089 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4090 const SDValue &Operand = Op.getOperand(1);
4091 const EVT VTy = Op.getValueType();
4092
4093 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4094 DAG.getConstant(1, dl, VTy));
4095 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4096 DAG.getConstant(0, dl, VTy));
4097 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4098 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4099 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4100 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4101 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4102 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4103 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4104 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4105 SDValue CheckLo =
4106 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4107 SDValue HiIsZero =
4108 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4109 SDValue AdjustedLo =
4110 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4111 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4112 SDValue Result =
4113 DAG.getSelect(dl, VTy, CheckLo,
4114 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4115 return Result;
4116 }
4117 case Intrinsic::eh_sjlj_lsda: {
4118 MachineFunction &MF = DAG.getMachineFunction();
4119 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4120 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4121 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4122 SDValue CPAddr;
4123 bool IsPositionIndependent = isPositionIndependent();
4124 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4125 ARMConstantPoolValue *CPV =
4126 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4127 ARMCP::CPLSDA, PCAdj);
4128 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4129 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4130 SDValue Result = DAG.getLoad(
4131 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4132 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4133
4134 if (IsPositionIndependent) {
4135 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4136 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4137 }
4138 return Result;
4139 }
4140 case Intrinsic::arm_neon_vabs:
4141 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4142 Op.getOperand(1));
4143 case Intrinsic::arm_neon_vmulls:
4144 case Intrinsic::arm_neon_vmullu: {
4145 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4146 ? ARMISD::VMULLs : ARMISD::VMULLu;
4147 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4148 Op.getOperand(1), Op.getOperand(2));
4149 }
4150 case Intrinsic::arm_neon_vminnm:
4151 case Intrinsic::arm_neon_vmaxnm: {
4152 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4153 ? ISD::FMINNUM : ISD::FMAXNUM;
4154 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4155 Op.getOperand(1), Op.getOperand(2));
4156 }
4157 case Intrinsic::arm_neon_vminu:
4158 case Intrinsic::arm_neon_vmaxu: {
4159 if (Op.getValueType().isFloatingPoint())
4160 return SDValue();
4161 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4162 ? ISD::UMIN : ISD::UMAX;
4163 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4164 Op.getOperand(1), Op.getOperand(2));
4165 }
4166 case Intrinsic::arm_neon_vmins:
4167 case Intrinsic::arm_neon_vmaxs: {
4168 // v{min,max}s is overloaded between signed integers and floats.
4169 if (!Op.getValueType().isFloatingPoint()) {
4170 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4171 ? ISD::SMIN : ISD::SMAX;
4172 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4173 Op.getOperand(1), Op.getOperand(2));
4174 }
4175 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4176 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4177 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4178 Op.getOperand(1), Op.getOperand(2));
4179 }
4180 case Intrinsic::arm_neon_vtbl1:
4181 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4182 Op.getOperand(1), Op.getOperand(2));
4183 case Intrinsic::arm_neon_vtbl2:
4184 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4185 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4186 case Intrinsic::arm_mve_pred_i2v:
4187 case Intrinsic::arm_mve_pred_v2i:
4188 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4189 Op.getOperand(1));
4190 case Intrinsic::arm_mve_vreinterpretq:
4191 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4192 Op.getOperand(1));
4193 case Intrinsic::arm_mve_lsll:
4194 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4195 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4196 case Intrinsic::arm_mve_asrl:
4197 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4198 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4199 }
4200}
4201
4202static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4203 const ARMSubtarget *Subtarget) {
4204 SDLoc dl(Op);
4205 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4206 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4207 if (SSID == SyncScope::SingleThread)
4208 return Op;
4209
4210 if (!Subtarget->hasDataBarrier()) {
4211 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4212 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4213 // here.
4214 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4215, __extension__
__PRETTY_FUNCTION__))
4215 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4215, __extension__
__PRETTY_FUNCTION__))
;
4216 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4217 DAG.getConstant(0, dl, MVT::i32));
4218 }
4219
4220 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4221 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4222 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4223 if (Subtarget->isMClass()) {
4224 // Only a full system barrier exists in the M-class architectures.
4225 Domain = ARM_MB::SY;
4226 } else if (Subtarget->preferISHSTBarriers() &&
4227 Ord == AtomicOrdering::Release) {
4228 // Swift happens to implement ISHST barriers in a way that's compatible with
4229 // Release semantics but weaker than ISH so we'd be fools not to use
4230 // it. Beware: other processors probably don't!
4231 Domain = ARM_MB::ISHST;
4232 }
4233
4234 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4235 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4236 DAG.getConstant(Domain, dl, MVT::i32));
4237}
4238
4239static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4240 const ARMSubtarget *Subtarget) {
4241 // ARM pre v5TE and Thumb1 does not have preload instructions.
4242 if (!(Subtarget->isThumb2() ||
4243 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4244 // Just preserve the chain.
4245 return Op.getOperand(0);
4246
4247 SDLoc dl(Op);
4248 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4249 if (!isRead &&
4250 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4251 // ARMv7 with MP extension has PLDW.
4252 return Op.getOperand(0);
4253
4254 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4255 if (Subtarget->isThumb()) {
4256 // Invert the bits.
4257 isRead = ~isRead & 1;
4258 isData = ~isData & 1;
4259 }
4260
4261 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4262 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4263 DAG.getConstant(isData, dl, MVT::i32));
4264}
4265
4266static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4267 MachineFunction &MF = DAG.getMachineFunction();
4268 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4269
4270 // vastart just stores the address of the VarArgsFrameIndex slot into the
4271 // memory location argument.
4272 SDLoc dl(Op);
4273 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4274 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4275 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4276 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4277 MachinePointerInfo(SV));
4278}
4279
4280SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4281 CCValAssign &NextVA,
4282 SDValue &Root,
4283 SelectionDAG &DAG,
4284 const SDLoc &dl) const {
4285 MachineFunction &MF = DAG.getMachineFunction();
4286 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4287
4288 const TargetRegisterClass *RC;
4289 if (AFI->isThumb1OnlyFunction())
4290 RC = &ARM::tGPRRegClass;
4291 else
4292 RC = &ARM::GPRRegClass;
4293
4294 // Transform the arguments stored in physical registers into virtual ones.
4295 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4296 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4297
4298 SDValue ArgValue2;
4299 if (NextVA.isMemLoc()) {
4300 MachineFrameInfo &MFI = MF.getFrameInfo();
4301 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4302
4303 // Create load node to retrieve arguments from the stack.
4304 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4305 ArgValue2 = DAG.getLoad(
4306 MVT::i32, dl, Root, FIN,
4307 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4308 } else {
4309 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4310 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4311 }
4312 if (!Subtarget->isLittle())
4313 std::swap (ArgValue, ArgValue2);
4314 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4315}
4316
4317// The remaining GPRs hold either the beginning of variable-argument
4318// data, or the beginning of an aggregate passed by value (usually
4319// byval). Either way, we allocate stack slots adjacent to the data
4320// provided by our caller, and store the unallocated registers there.
4321// If this is a variadic function, the va_list pointer will begin with
4322// these values; otherwise, this reassembles a (byval) structure that
4323// was split between registers and memory.
4324// Return: The frame index registers were stored into.
4325int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4326 const SDLoc &dl, SDValue &Chain,
4327 const Value *OrigArg,
4328 unsigned InRegsParamRecordIdx,
4329 int ArgOffset, unsigned ArgSize) const {
4330 // Currently, two use-cases possible:
4331 // Case #1. Non-var-args function, and we meet first byval parameter.
4332 // Setup first unallocated register as first byval register;
4333 // eat all remained registers
4334 // (these two actions are performed by HandleByVal method).
4335 // Then, here, we initialize stack frame with
4336 // "store-reg" instructions.
4337 // Case #2. Var-args function, that doesn't contain byval parameters.
4338 // The same: eat all remained unallocated registers,
4339 // initialize stack frame.
4340
4341 MachineFunction &MF = DAG.getMachineFunction();
4342 MachineFrameInfo &MFI = MF.getFrameInfo();
4343 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4344 unsigned RBegin, REnd;
4345 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4346 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4347 } else {
4348 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4349 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4350 REnd = ARM::R4;
4351 }
4352
4353 if (REnd != RBegin)
4354 ArgOffset = -4 * (ARM::R4 - RBegin);
4355
4356 auto PtrVT = getPointerTy(DAG.getDataLayout());
4357 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4358 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4359
4360 SmallVector<SDValue, 4> MemOps;
4361 const TargetRegisterClass *RC =
4362 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4363
4364 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4365 Register VReg = MF.addLiveIn(Reg, RC);
4366 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4367 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4368 MachinePointerInfo(OrigArg, 4 * i));
4369 MemOps.push_back(Store);
4370 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4371 }
4372
4373 if (!MemOps.empty())
4374 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4375 return FrameIndex;
4376}
4377
4378// Setup stack frame, the va_list pointer will start from.
4379void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4380 const SDLoc &dl, SDValue &Chain,
4381 unsigned ArgOffset,
4382 unsigned TotalArgRegsSaveSize,
4383 bool ForceMutable) const {
4384 MachineFunction &MF = DAG.getMachineFunction();
4385 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4386
4387 // Try to store any remaining integer argument regs
4388 // to their spots on the stack so that they may be loaded by dereferencing
4389 // the result of va_next.
4390 // If there is no regs to be stored, just point address after last
4391 // argument passed via stack.
4392 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4393 CCInfo.getInRegsParamsCount(),
4394 CCInfo.getNextStackOffset(),
4395 std::max(4U, TotalArgRegsSaveSize));
4396 AFI->setVarArgsFrameIndex(FrameIndex);
4397}
4398
4399bool ARMTargetLowering::splitValueIntoRegisterParts(
4400 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4401 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4402 bool IsABIRegCopy = CC.has_value();
4403 EVT ValueVT = Val.getValueType();
4404 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4405 PartVT == MVT::f32) {
4406 unsigned ValueBits = ValueVT.getSizeInBits();
4407 unsigned PartBits = PartVT.getSizeInBits();
4408 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4409 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4410 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4411 Parts[0] = Val;
4412 return true;
4413 }
4414 return false;
4415}
4416
4417SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4418 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4419 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4420 bool IsABIRegCopy = CC.has_value();
4421 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4422 PartVT == MVT::f32) {
4423 unsigned ValueBits = ValueVT.getSizeInBits();
4424 unsigned PartBits = PartVT.getSizeInBits();
4425 SDValue Val = Parts[0];
4426
4427 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4428 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4429 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4430 return Val;
4431 }
4432 return SDValue();
4433}
4434
4435SDValue ARMTargetLowering::LowerFormalArguments(
4436 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4437 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4438 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4439 MachineFunction &MF = DAG.getMachineFunction();
4440 MachineFrameInfo &MFI = MF.getFrameInfo();
4441
4442 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4443
4444 // Assign locations to all of the incoming arguments.
4445 SmallVector<CCValAssign, 16> ArgLocs;
4446 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4447 *DAG.getContext());
4448 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4449
4450 SmallVector<SDValue, 16> ArgValues;
4451 SDValue ArgValue;
4452 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4453 unsigned CurArgIdx = 0;
4454
4455 // Initially ArgRegsSaveSize is zero.
4456 // Then we increase this value each time we meet byval parameter.
4457 // We also increase this value in case of varargs function.
4458 AFI->setArgRegsSaveSize(0);
4459
4460 // Calculate the amount of stack space that we need to allocate to store
4461 // byval and variadic arguments that are passed in registers.
4462 // We need to know this before we allocate the first byval or variadic
4463 // argument, as they will be allocated a stack slot below the CFA (Canonical
4464 // Frame Address, the stack pointer at entry to the function).
4465 unsigned ArgRegBegin = ARM::R4;
4466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4467 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4468 break;
4469
4470 CCValAssign &VA = ArgLocs[i];
4471 unsigned Index = VA.getValNo();
4472 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4473 if (!Flags.isByVal())
4474 continue;
4475
4476 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4476, __extension__
__PRETTY_FUNCTION__))
;
4477 unsigned RBegin, REnd;
4478 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4479 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4480
4481 CCInfo.nextInRegsParam();
4482 }
4483 CCInfo.rewindByValRegsInfo();
4484
4485 int lastInsIndex = -1;
4486 if (isVarArg && MFI.hasVAStart()) {
4487 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4488 if (RegIdx != std::size(GPRArgRegs))
4489 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4490 }
4491
4492 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4493 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4494 auto PtrVT = getPointerTy(DAG.getDataLayout());
4495
4496 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4497 CCValAssign &VA = ArgLocs[i];
4498 if (Ins[VA.getValNo()].isOrigArg()) {
4499 std::advance(CurOrigArg,
4500 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4501 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4502 }
4503 // Arguments stored in registers.
4504 if (VA.isRegLoc()) {
4505 EVT RegVT = VA.getLocVT();
4506
4507 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4508 // f64 and vector types are split up into multiple registers or
4509 // combinations of registers and stack slots.
4510 SDValue ArgValue1 =
4511 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4512 VA = ArgLocs[++i]; // skip ahead to next loc
4513 SDValue ArgValue2;
4514 if (VA.isMemLoc()) {
4515 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4516 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4517 ArgValue2 = DAG.getLoad(
4518 MVT::f64, dl, Chain, FIN,
4519 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4520 } else {
4521 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4522 }
4523 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4524 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4525 ArgValue1, DAG.getIntPtrConstant(0, dl));
4526 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4527 ArgValue2, DAG.getIntPtrConstant(1, dl));
4528 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4529 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4530 } else {
4531 const TargetRegisterClass *RC;
4532
4533 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4534 RC = &ARM::HPRRegClass;
4535 else if (RegVT == MVT::f32)
4536 RC = &ARM::SPRRegClass;
4537 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4538 RegVT == MVT::v4bf16)
4539 RC = &ARM::DPRRegClass;
4540 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4541 RegVT == MVT::v8bf16)
4542 RC = &ARM::QPRRegClass;
4543 else if (RegVT == MVT::i32)
4544 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4545 : &ARM::GPRRegClass;
4546 else
4547 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4547)
;
4548
4549 // Transform the arguments in physical registers into virtual ones.
4550 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4551 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4552
4553 // If this value is passed in r0 and has the returned attribute (e.g.
4554 // C++ 'structors), record this fact for later use.
4555 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4556 AFI->setPreservesR0();
4557 }
4558 }
4559
4560 // If this is an 8 or 16-bit value, it is really passed promoted
4561 // to 32 bits. Insert an assert[sz]ext to capture this, then
4562 // truncate to the right size.
4563 switch (VA.getLocInfo()) {
4564 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4564)
;
4565 case CCValAssign::Full: break;
4566 case CCValAssign::BCvt:
4567 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4568 break;
4569 case CCValAssign::SExt:
4570 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4571 DAG.getValueType(VA.getValVT()));
4572 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4573 break;
4574 case CCValAssign::ZExt:
4575 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4576 DAG.getValueType(VA.getValVT()));
4577 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4578 break;
4579 }
4580
4581 // f16 arguments have their size extended to 4 bytes and passed as if they
4582 // had been copied to the LSBs of a 32-bit register.
4583 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4584 if (VA.needsCustom() &&
4585 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4586 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4587
4588 InVals.push_back(ArgValue);
4589 } else { // VA.isRegLoc()
4590 // Only arguments passed on the stack should make it here.
4591 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
4591, __extension__ __PRETTY_FUNCTION__))
;
4592 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4592, __extension__
__PRETTY_FUNCTION__))
;
4593
4594 int index = VA.getValNo();
4595
4596 // Some Ins[] entries become multiple ArgLoc[] entries.
4597 // Process them only once.
4598 if (index != lastInsIndex)
4599 {
4600 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4601 // FIXME: For now, all byval parameter objects are marked mutable.
4602 // This can be changed with more analysis.
4603 // In case of tail call optimization mark all arguments mutable.
4604 // Since they could be overwritten by lowering of arguments in case of
4605 // a tail call.
4606 if (Flags.isByVal()) {
4607 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4608, __extension__
__PRETTY_FUNCTION__))
4608 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4608, __extension__
__PRETTY_FUNCTION__))
;
4609 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4610
4611 int FrameIndex = StoreByValRegs(
4612 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4613 VA.getLocMemOffset(), Flags.getByValSize());
4614 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4615 CCInfo.nextInRegsParam();
4616 } else {
4617 unsigned FIOffset = VA.getLocMemOffset();
4618 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4619 FIOffset, true);
4620
4621 // Create load nodes to retrieve arguments from the stack.
4622 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4623 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4624 MachinePointerInfo::getFixedStack(
4625 DAG.getMachineFunction(), FI)));
4626 }
4627 lastInsIndex = index;
4628 }
4629 }
4630 }
4631
4632 // varargs
4633 if (isVarArg && MFI.hasVAStart()) {
4634 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4635 TotalArgRegsSaveSize);
4636 if (AFI->isCmseNSEntryFunction()) {
4637 DiagnosticInfoUnsupported Diag(
4638 DAG.getMachineFunction().getFunction(),
4639 "secure entry function must not be variadic", dl.getDebugLoc());
4640 DAG.getContext()->diagnose(Diag);
4641 }
4642 }
4643
4644 unsigned StackArgSize = CCInfo.getNextStackOffset();
4645 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4646 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4647 // The only way to guarantee a tail call is if the callee restores its
4648 // argument area, but it must also keep the stack aligned when doing so.
4649 const DataLayout &DL = DAG.getDataLayout();
4650 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4651
4652 AFI->setArgumentStackToRestore(StackArgSize);
4653 }
4654 AFI->setArgumentStackSize(StackArgSize);
4655
4656 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4657 DiagnosticInfoUnsupported Diag(
4658 DAG.getMachineFunction().getFunction(),
4659 "secure entry function requires arguments on stack", dl.getDebugLoc());
4660 DAG.getContext()->diagnose(Diag);
4661 }
4662
4663 return Chain;
4664}
4665
4666/// isFloatingPointZero - Return true if this is +0.0.
4667static bool isFloatingPointZero(SDValue Op) {
4668 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4669 return CFP->getValueAPF().isPosZero();
4670 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4671 // Maybe this has already been legalized into the constant pool?
4672 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4673 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4674 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4675 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4676 return CFP->getValueAPF().isPosZero();
4677 }
4678 } else if (Op->getOpcode() == ISD::BITCAST &&
4679 Op->getValueType(0) == MVT::f64) {
4680 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4681 // created by LowerConstantFP().
4682 SDValue BitcastOp = Op->getOperand(0);
4683 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4684 isNullConstant(BitcastOp->getOperand(0)))
4685 return true;
4686 }
4687 return false;
4688}
4689
4690/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4691/// the given operands.
4692SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4693 SDValue &ARMcc, SelectionDAG &DAG,
4694 const SDLoc &dl) const {
4695 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4696 unsigned C = RHSC->getZExtValue();
4697 if (!isLegalICmpImmediate((int32_t)C)) {
4698 // Constant does not fit, try adjusting it by one.
4699 switch (CC) {
4700 default: break;
4701 case ISD::SETLT:
4702 case ISD::SETGE:
4703 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4704 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4705 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4706 }
4707 break;
4708 case ISD::SETULT:
4709 case ISD::SETUGE:
4710 if (C != 0 && isLegalICmpImmediate(C-1)) {
4711 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4712 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4713 }
4714 break;
4715 case ISD::SETLE:
4716 case ISD::SETGT:
4717 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4718 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4719 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4720 }
4721 break;
4722 case ISD::SETULE:
4723 case ISD::SETUGT:
4724 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4725 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4726 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4727 }
4728 break;
4729 }
4730 }
4731 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4732 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4733 // In ARM and Thumb-2, the compare instructions can shift their second
4734 // operand.
4735 CC = ISD::getSetCCSwappedOperands(CC);
4736 std::swap(LHS, RHS);
4737 }
4738
4739 // Thumb1 has very limited immediate modes, so turning an "and" into a
4740 // shift can save multiple instructions.
4741 //
4742 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4743 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4744 // own. If it's the operand to an unsigned comparison with an immediate,
4745 // we can eliminate one of the shifts: we transform
4746 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4747 //
4748 // We avoid transforming cases which aren't profitable due to encoding
4749 // details:
4750 //
4751 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4752 // would not; in that case, we're essentially trading one immediate load for
4753 // another.
4754 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4755 // 3. C2 is zero; we have other code for this special case.
4756 //
4757 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4758 // instruction, since the AND is always one instruction anyway, but we could
4759 // use narrow instructions in some cases.
4760 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4761 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4762 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4763 !isSignedIntSetCC(CC)) {
4764 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4765 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4766 uint64_t RHSV = RHSC->getZExtValue();
4767 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4768 unsigned ShiftBits = countLeadingZeros(Mask);
4769 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4770 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4771 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4772 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4773 }
4774 }
4775 }
4776
4777 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4778 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4779 // way a cmp would.
4780 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4781 // some tweaks to the heuristics for the previous and->shift transform.
4782 // FIXME: Optimize cases where the LHS isn't a shift.
4783 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4784 isa<ConstantSDNode>(RHS) &&
4785 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4786 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4787 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4788 unsigned ShiftAmt =
4789 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4790 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4791 DAG.getVTList(MVT::i32, MVT::i32),
4792 LHS.getOperand(0),
4793 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4794 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4795 Shift.getValue(1), SDValue());
4796 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4797 return Chain.getValue(1);
4798 }
4799
4800 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4801
4802 // If the RHS is a constant zero then the V (overflow) flag will never be
4803 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4804 // simpler for other passes (like the peephole optimiser) to deal with.
4805 if (isNullConstant(RHS)) {
4806 switch (CondCode) {
4807 default: break;
4808 case ARMCC::GE:
4809 CondCode = ARMCC::PL;
4810 break;
4811 case ARMCC::LT:
4812 CondCode = ARMCC::MI;
4813 break;
4814 }
4815 }
4816
4817 ARMISD::NodeType CompareType;
4818 switch (CondCode) {
4819 default:
4820 CompareType = ARMISD::CMP;
4821 break;
4822 case ARMCC::EQ:
4823 case ARMCC::NE:
4824 // Uses only Z Flag
4825 CompareType = ARMISD::CMPZ;
4826 break;
4827 }
4828 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4829 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4830}
4831
4832/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4833SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4834 SelectionDAG &DAG, const SDLoc &dl,
4835 bool Signaling) const {
4836 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4836, __extension__
__PRETTY_FUNCTION__))
;
4837 SDValue Cmp;
4838 if (!isFloatingPointZero(RHS))
4839 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4840 dl, MVT::Glue, LHS, RHS);
4841 else
4842 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4843 dl, MVT::Glue, LHS);
4844 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4845}
4846
4847/// duplicateCmp - Glue values can have only one use, so this function
4848/// duplicates a comparison node.
4849SDValue
4850ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4851 unsigned Opc = Cmp.getOpcode();
4852 SDLoc DL(Cmp);
4853 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4854 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4855
4856 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4856, __extension__
__PRETTY_FUNCTION__))
;
4857 Cmp = Cmp.getOperand(0);
4858 Opc = Cmp.getOpcode();
4859 if (Opc == ARMISD::CMPFP)
4860 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4861 else {
4862 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4862, __extension__
__PRETTY_FUNCTION__))
;
4863 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4864 }
4865 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4866}
4867
4868// This function returns three things: the arithmetic computation itself
4869// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4870// comparison and the condition code define the case in which the arithmetic
4871// computation *does not* overflow.
4872std::pair<SDValue, SDValue>
4873ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4874 SDValue &ARMcc) const {
4875 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4875, __extension__
__PRETTY_FUNCTION__))
;
4876
4877 SDValue Value, OverflowCmp;
4878 SDValue LHS = Op.getOperand(0);
4879 SDValue RHS = Op.getOperand(1);
4880 SDLoc dl(Op);
4881
4882 // FIXME: We are currently always generating CMPs because we don't support
4883 // generating CMN through the backend. This is not as good as the natural
4884 // CMP case because it causes a register dependency and cannot be folded
4885 // later.
4886
4887 switch (Op.getOpcode()) {
4888 default:
4889 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4889)
;
4890 case ISD::SADDO:
4891 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4892 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4893 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4894 break;
4895 case ISD::UADDO:
4896 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4897 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4898 // We do not use it in the USUBO case as Value may not be used.
4899 Value = DAG.getNode(ARMISD::ADDC, dl,
4900 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4901 .getValue(0);
4902 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4903 break;
4904 case ISD::SSUBO:
4905 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4906 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4907 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4908 break;
4909 case ISD::USUBO:
4910 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4911 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4912 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4913 break;
4914 case ISD::UMULO:
4915 // We generate a UMUL_LOHI and then check if the high word is 0.
4916 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4917 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4918 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4919 LHS, RHS);
4920 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4921 DAG.getConstant(0, dl, MVT::i32));
4922 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4923 break;
4924 case ISD::SMULO:
4925 // We generate a SMUL_LOHI and then check if all the bits of the high word
4926 // are the same as the sign bit of the low word.
4927 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4928 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4929 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4930 LHS, RHS);
4931 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4932 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4933 Value.getValue(0),
4934 DAG.getConstant(31, dl, MVT::i32)));
4935 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4936 break;
4937 } // switch (...)
4938
4939 return std::make_pair(Value, OverflowCmp);
4940}
4941
4942SDValue
4943ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4944 // Let legalize expand this if it isn't a legal type yet.
4945 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4946 return SDValue();
4947
4948 SDValue Value, OverflowCmp;
4949 SDValue ARMcc;
4950 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4951 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4952 SDLoc dl(Op);
4953 // We use 0 and 1 as false and true values.
4954 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4955 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4956 EVT VT = Op.getValueType();
4957
4958 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4959 ARMcc, CCR, OverflowCmp);
4960
4961 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4962 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4963}
4964
4965static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4966 SelectionDAG &DAG) {
4967 SDLoc DL(BoolCarry);
4968 EVT CarryVT = BoolCarry.getValueType();
4969
4970 // This converts the boolean value carry into the carry flag by doing
4971 // ARMISD::SUBC Carry, 1
4972 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4973 DAG.getVTList(CarryVT, MVT::i32),
4974 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4975 return Carry.getValue(1);
4976}
4977
4978static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4979 SelectionDAG &DAG) {
4980 SDLoc DL(Flags);
4981
4982 // Now convert the carry flag into a boolean carry. We do this
4983 // using ARMISD:ADDE 0, 0, Carry
4984 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4985 DAG.getConstant(0, DL, MVT::i32),
4986 DAG.getConstant(0, DL, MVT::i32), Flags);
4987}
4988
4989SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4990 SelectionDAG &DAG) const {
4991 // Let legalize expand this if it isn't a legal type yet.
4992 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4993 return SDValue();
4994
4995 SDValue LHS = Op.getOperand(0);
4996 SDValue RHS = Op.getOperand(1);
4997 SDLoc dl(Op);
4998
4999 EVT VT = Op.getValueType();
5000 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5001 SDValue Value;
5002 SDValue Overflow;
5003 switch (Op.getOpcode()) {
5004 default:
5005 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5005)
;
5006 case ISD::UADDO:
5007 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
5008 // Convert the carry flag into a boolean value.
5009 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5010 break;
5011 case ISD::USUBO: {
5012 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
5013 // Convert the carry flag into a boolean value.
5014 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5015 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
5016 // value. So compute 1 - C.
5017 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
5018 DAG.getConstant(1, dl, MVT::i32), Overflow);
5019 break;
5020 }
5021 }
5022
5023 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5024}
5025
5026static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
5027 const ARMSubtarget *Subtarget) {
5028 EVT VT = Op.getValueType();
5029 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
3
Assuming the condition is false
4
Assuming the condition is false
5
Taking false branch
5030 return SDValue();
5031 if (!VT.isSimple())
6
Taking false branch
5032 return SDValue();
5033
5034 unsigned NewOpcode;
7
'NewOpcode' declared without an initial value
5035 switch (VT.getSimpleVT().SimpleTy) {
8
Control jumps to 'case i16:' at line 5054
5036 default:
5037 return SDValue();
5038 case MVT::i8:
5039 switch (Op->getOpcode()) {
5040 case ISD::UADDSAT:
5041 NewOpcode = ARMISD::UQADD8b;
5042 break;
5043 case ISD::SADDSAT:
5044 NewOpcode = ARMISD::QADD8b;
5045 break;
5046 case ISD::USUBSAT:
5047 NewOpcode = ARMISD::UQSUB8b;
5048 break;
5049 case ISD::SSUBSAT:
5050 NewOpcode = ARMISD::QSUB8b;
5051 break;
5052 }
5053 break;
5054 case MVT::i16:
5055 switch (Op->getOpcode()) {
9
'Default' branch taken. Execution continues on line 5069
5056 case ISD::UADDSAT:
5057 NewOpcode = ARMISD::UQADD16b;
5058 break;
5059 case ISD::SADDSAT:
5060 NewOpcode = ARMISD::QADD16b;
5061 break;
5062 case ISD::USUBSAT:
5063 NewOpcode = ARMISD::UQSUB16b;
5064 break;
5065 case ISD::SSUBSAT:
5066 NewOpcode = ARMISD::QSUB16b;
5067 break;
5068 }
5069 break;
10
Execution continues on line 5072
5070 }
5071
5072 SDLoc dl(Op);
5073 SDValue Add =
5074 DAG.getNode(NewOpcode, dl, MVT::i32,
11
1st function call argument is an uninitialized value
5075 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5076 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5077 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5078}
5079
5080SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5081 SDValue Cond = Op.getOperand(0);
5082 SDValue SelectTrue = Op.getOperand(1);
5083 SDValue SelectFalse = Op.getOperand(2);
5084 SDLoc dl(Op);
5085 unsigned Opc = Cond.getOpcode();
5086
5087 if (Cond.getResNo() == 1 &&
5088 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5089 Opc == ISD::USUBO)) {
5090 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5091 return SDValue();
5092
5093 SDValue Value, OverflowCmp;
5094 SDValue ARMcc;
5095 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5096 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5097 EVT VT = Op.getValueType();
5098
5099 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5100 OverflowCmp, DAG);
5101 }
5102
5103 // Convert:
5104 //
5105 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5106 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5107 //
5108 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5109 const ConstantSDNode *CMOVTrue =
5110 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5111 const ConstantSDNode *CMOVFalse =
5112 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5113
5114 if (CMOVTrue && CMOVFalse) {
5115 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5116 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5117
5118 SDValue True;
5119 SDValue False;
5120 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5121 True = SelectTrue;
5122 False = SelectFalse;
5123 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5124 True = SelectFalse;
5125 False = SelectTrue;
5126 }
5127
5128 if (True.getNode() && False.getNode()) {
5129 EVT VT = Op.getValueType();
5130 SDValue ARMcc = Cond.getOperand(2);
5131 SDValue CCR = Cond.getOperand(3);
5132 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5133 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5133, __extension__ __PRETTY_FUNCTION__))
;
5134 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5135 }
5136 }
5137 }
5138
5139 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5140 // undefined bits before doing a full-word comparison with zero.
5141 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5142 DAG.getConstant(1, dl, Cond.getValueType()));
5143
5144 return DAG.getSelectCC(dl, Cond,
5145 DAG.getConstant(0, dl, Cond.getValueType()),
5146 SelectTrue, SelectFalse, ISD::SETNE);
5147}
5148
5149static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5150 bool &swpCmpOps, bool &swpVselOps) {
5151 // Start by selecting the GE condition code for opcodes that return true for
5152 // 'equality'
5153 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5154 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5155 CondCode = ARMCC::GE;
5156
5157 // and GT for opcodes that return false for 'equality'.
5158 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5159 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5160 CondCode = ARMCC::GT;
5161
5162 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5163 // to swap the compare operands.
5164 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5165 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5166 swpCmpOps = true;
5167
5168 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5169 // If we have an unordered opcode, we need to swap the operands to the VSEL
5170 // instruction (effectively negating the condition).
5171 //
5172 // This also has the effect of swapping which one of 'less' or 'greater'
5173 // returns true, so we also swap the compare operands. It also switches
5174 // whether we return true for 'equality', so we compensate by picking the
5175 // opposite condition code to our original choice.
5176 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5177 CC == ISD::SETUGT) {
5178 swpCmpOps = !swpCmpOps;
5179 swpVselOps = !swpVselOps;
5180 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5181 }
5182
5183 // 'ordered' is 'anything but unordered', so use the VS condition code and
5184 // swap the VSEL operands.
5185 if (CC == ISD::SETO) {
5186 CondCode = ARMCC::VS;
5187 swpVselOps = true;
5188 }
5189
5190 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5191 // code and swap the VSEL operands. Also do this if we don't care about the
5192 // unordered case.
5193 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5194 CondCode = ARMCC::EQ;
5195 swpVselOps = true;
5196 }
5197}
5198
5199SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5200 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5201 SDValue Cmp, SelectionDAG &DAG) const {
5202 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5203 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5204 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5205 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5206 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5207
5208 SDValue TrueLow = TrueVal.getValue(0);
5209 SDValue TrueHigh = TrueVal.getValue(1);
5210 SDValue FalseLow = FalseVal.getValue(0);
5211 SDValue FalseHigh = FalseVal.getValue(1);
5212
5213 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5214 ARMcc, CCR, Cmp);
5215 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5216 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5217
5218 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5219 } else {
5220 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5221 Cmp);
5222 }
5223}
5224
5225static bool isGTorGE(ISD::CondCode CC) {
5226 return CC == ISD::SETGT || CC == ISD::SETGE;
5227}
5228
5229static bool isLTorLE(ISD::CondCode CC) {
5230 return CC == ISD::SETLT || CC == ISD::SETLE;
5231}
5232
5233// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5234// All of these conditions (and their <= and >= counterparts) will do:
5235// x < k ? k : x
5236// x > k ? x : k
5237// k < x ? x : k
5238// k > x ? k : x
5239static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5240 const SDValue TrueVal, const SDValue FalseVal,
5241 const ISD::CondCode CC, const SDValue K) {
5242 return (isGTorGE(CC) &&
5243 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5244 (isLTorLE(CC) &&
5245 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5246}
5247
5248// Check if two chained conditionals could be converted into SSAT or USAT.
5249//
5250// SSAT can replace a set of two conditional selectors that bound a number to an
5251// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5252//
5253// x < -k ? -k : (x > k ? k : x)
5254// x < -k ? -k : (x < k ? x : k)
5255// x > -k ? (x > k ? k : x) : -k
5256// x < k ? (x < -k ? -k : x) : k
5257// etc.
5258//
5259// LLVM canonicalizes these to either a min(max()) or a max(min())
5260// pattern. This function tries to match one of these and will return a SSAT
5261// node if successful.
5262//
5263// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5264// is a power of 2.
5265static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5266 EVT VT = Op.getValueType();
5267 SDValue V1 = Op.getOperand(0);
5268 SDValue K1 = Op.getOperand(1);
5269 SDValue TrueVal1 = Op.getOperand(2);
5270 SDValue FalseVal1 = Op.getOperand(3);
5271 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5272
5273 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5274 if (Op2.getOpcode() != ISD::SELECT_CC)
5275 return SDValue();
5276
5277 SDValue V2 = Op2.getOperand(0);
5278 SDValue K2 = Op2.getOperand(1);
5279 SDValue TrueVal2 = Op2.getOperand(2);
5280 SDValue FalseVal2 = Op2.getOperand(3);
5281 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5282
5283 SDValue V1Tmp = V1;
5284 SDValue V2Tmp = V2;
5285
5286 // Check that the registers and the constants match a max(min()) or min(max())
5287 // pattern
5288 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5289 K2 != FalseVal2 ||
5290 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5291 return SDValue();
5292
5293 // Check that the constant in the lower-bound check is
5294 // the opposite of the constant in the upper-bound check
5295 // in 1's complement.
5296 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5297 return SDValue();
5298
5299 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5300 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5301 int64_t PosVal = std::max(Val1, Val2);
5302 int64_t NegVal = std::min(Val1, Val2);
5303
5304 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5305 !isPowerOf2_64(PosVal + 1))
5306 return SDValue();
5307
5308 // Handle the difference between USAT (unsigned) and SSAT (signed)
5309 // saturation
5310 // At this point, PosVal is guaranteed to be positive
5311 uint64_t K = PosVal;
5312 SDLoc dl(Op);
5313 if (Val1 == ~Val2)
5314 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5315 DAG.getConstant(countTrailingOnes(K), dl, VT));
5316 if (NegVal == 0)
5317 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5318 DAG.getConstant(countTrailingOnes(K), dl, VT));
5319
5320 return SDValue();
5321}
5322
5323// Check if a condition of the type x < k ? k : x can be converted into a
5324// bit operation instead of conditional moves.
5325// Currently this is allowed given:
5326// - The conditions and values match up
5327// - k is 0 or -1 (all ones)
5328// This function will not check the last condition, thats up to the caller
5329// It returns true if the transformation can be made, and in such case
5330// returns x in V, and k in SatK.
5331static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5332 SDValue &SatK)
5333{
5334 SDValue LHS = Op.getOperand(0);
5335 SDValue RHS = Op.getOperand(1);
5336 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5337 SDValue TrueVal = Op.getOperand(2);
5338 SDValue FalseVal = Op.getOperand(3);
5339
5340 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5341 ? &RHS
5342 : nullptr;
5343
5344 // No constant operation in comparison, early out
5345 if (!K)
5346 return false;
5347
5348 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5349 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5350 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5351
5352 // If the constant on left and right side, or variable on left and right,
5353 // does not match, early out
5354 if (*K != KTmp || V != VTmp)
5355 return false;
5356
5357 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5358 SatK = *K;
5359 return true;
5360 }
5361
5362 return false;
5363}
5364
5365bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5366 if (VT == MVT::f32)
5367 return !Subtarget->hasVFP2Base();
5368 if (VT == MVT::f64)
5369 return !Subtarget->hasFP64();
5370 if (VT == MVT::f16)
5371 return !Subtarget->hasFullFP16();
5372 return false;
5373}
5374
5375SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5376 EVT VT = Op.getValueType();
5377 SDLoc dl(Op);
5378
5379 // Try to convert two saturating conditional selects into a single SSAT
5380 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5381 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5382 return SatValue;
5383
5384 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5385 // into more efficient bit operations, which is possible when k is 0 or -1
5386 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5387 // single instructions. On Thumb the shift and the bit operation will be two
5388 // instructions.
5389 // Only allow this transformation on full-width (32-bit) operations
5390 SDValue LowerSatConstant;
5391 SDValue SatValue;
5392 if (VT == MVT::i32 &&
5393 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5394 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5395 DAG.getConstant(31, dl, VT));
5396 if (isNullConstant(LowerSatConstant)) {
5397 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5398 DAG.getAllOnesConstant(dl, VT));
5399 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5400 } else if (isAllOnesConstant(LowerSatConstant))
5401 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5402 }
5403
5404 SDValue LHS = Op.getOperand(0);
5405 SDValue RHS = Op.getOperand(1);
5406 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5407 SDValue TrueVal = Op.getOperand(2);
5408 SDValue FalseVal = Op.getOperand(3);
5409 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5410 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5411
5412 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5413 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5414 unsigned TVal = CTVal->getZExtValue();
5415 unsigned FVal = CFVal->getZExtValue();
5416 unsigned Opcode = 0;
5417
5418 if (TVal == ~FVal) {
5419 Opcode = ARMISD::CSINV;
5420 } else if (TVal == ~FVal + 1) {
5421 Opcode = ARMISD::CSNEG;
5422 } else if (TVal + 1 == FVal) {
5423 Opcode = ARMISD::CSINC;
5424 } else if (TVal == FVal + 1) {
5425 Opcode = ARMISD::CSINC;
5426 std::swap(TrueVal, FalseVal);
5427 std::swap(TVal, FVal);
5428 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5429 }
5430
5431 if (Opcode) {
5432 // If one of the constants is cheaper than another, materialise the
5433 // cheaper one and let the csel generate the other.
5434 if (Opcode != ARMISD::CSINC &&
5435 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5436 std::swap(TrueVal, FalseVal);
5437 std::swap(TVal, FVal);
5438 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5439 }
5440
5441 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5442 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5443 // -(-a) == a, but (a+1)+1 != a).
5444 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5445 std::swap(TrueVal, FalseVal);
5446 std::swap(TVal, FVal);
5447 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5448 }
5449
5450 // Drops F's value because we can get it by inverting/negating TVal.
5451 FalseVal = TrueVal;
5452
5453 SDValue ARMcc;
5454 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5455 EVT VT = TrueVal.getValueType();
5456 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5457 }
5458 }
5459
5460 if (isUnsupportedFloatingType(LHS.getValueType())) {
5461 DAG.getTargetLoweringInfo().softenSetCCOperands(
5462 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5463
5464 // If softenSetCCOperands only returned one value, we should compare it to
5465 // zero.
5466 if (!RHS.getNode()) {
5467 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5468 CC = ISD::SETNE;
5469 }
5470 }
5471
5472 if (LHS.getValueType() == MVT::i32) {
5473 // Try to generate VSEL on ARMv8.
5474 // The VSEL instruction can't use all the usual ARM condition
5475 // codes: it only has two bits to select the condition code, so it's
5476 // constrained to use only GE, GT, VS and EQ.
5477 //
5478 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5479 // swap the operands of the previous compare instruction (effectively
5480 // inverting the compare condition, swapping 'less' and 'greater') and
5481 // sometimes need to swap the operands to the VSEL (which inverts the
5482 // condition in the sense of firing whenever the previous condition didn't)
5483 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5484 TrueVal.getValueType() == MVT::f32 ||
5485 TrueVal.getValueType() == MVT::f64)) {
5486 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5487 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5488 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5489 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5490 std::swap(TrueVal, FalseVal);
5491 }
5492 }
5493
5494 SDValue ARMcc;
5495 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5496 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5497 // Choose GE over PL, which vsel does now support
5498 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5499 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5500 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5501 }
5502
5503 ARMCC::CondCodes CondCode, CondCode2;
5504 FPCCToARMCC(CC, CondCode, CondCode2);
5505
5506 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5507 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5508 // must use VSEL (limited condition codes), due to not having conditional f16
5509 // moves.
5510 if (Subtarget->hasFPARMv8Base() &&
5511 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5512 (TrueVal.getValueType() == MVT::f16 ||
5513 TrueVal.getValueType() == MVT::f32 ||
5514 TrueVal.getValueType() == MVT::f64)) {
5515 bool swpCmpOps = false;
5516 bool swpVselOps = false;
5517 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5518
5519 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5520 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5521 if (swpCmpOps)
5522 std::swap(LHS, RHS);
5523 if (swpVselOps)
5524 std::swap(TrueVal, FalseVal);
5525 }
5526 }
5527
5528 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5529 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5530 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5531 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5532 if (CondCode2 != ARMCC::AL) {
5533 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5534 // FIXME: Needs another CMP because flag can have but one use.
5535 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5536 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5537 }
5538 return Result;
5539}
5540
5541/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5542/// to morph to an integer compare sequence.
5543static bool canChangeToInt(SDValue Op, bool &SeenZero,
5544 const ARMSubtarget *Subtarget) {
5545 SDNode *N = Op.getNode();
5546 if (!N->hasOneUse())
5547 // Otherwise it requires moving the value from fp to integer registers.
5548 return false;
5549 if (!N->getNumValues())
5550 return false;
5551 EVT VT = Op.getValueType();
5552 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5553 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5554 // vmrs are very slow, e.g. cortex-a8.
5555 return false;
5556
5557 if (isFloatingPointZero(Op)) {
5558 SeenZero = true;
5559 return true;
5560 }
5561 return ISD::isNormalLoad(N);
5562}
5563
5564static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5565 if (isFloatingPointZero(Op))
5566 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5567
5568 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5569 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5570 Ld->getPointerInfo(), Ld->getAlign(),
5571 Ld->getMemOperand()->getFlags());
5572
5573 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5573)
;
5574}
5575
5576static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5577 SDValue &RetVal1, SDValue &RetVal2) {
5578 SDLoc dl(Op);
5579
5580 if (isFloatingPointZero(Op)) {
5581 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5582 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5583 return;
5584 }
5585
5586 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5587 SDValue Ptr = Ld->getBasePtr();
5588 RetVal1 =
5589 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5590 Ld->getAlign(), Ld->getMemOperand()->getFlags());
5591
5592 EVT PtrType = Ptr.getValueType();
5593 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5594 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5595 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5596 Ld->getPointerInfo().getWithOffset(4),
5597 commonAlignment(Ld->getAlign(), 4),
5598 Ld->getMemOperand()->getFlags());
5599 return;
5600 }
5601
5602 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5602)
;
5603}
5604
5605/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5606/// f32 and even f64 comparisons to integer ones.
5607SDValue
5608ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5609 SDValue Chain = Op.getOperand(0);
5610 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5611 SDValue LHS = Op.getOperand(2);
5612 SDValue RHS = Op.getOperand(3);
5613 SDValue Dest = Op.getOperand(4);
5614 SDLoc dl(Op);
5615
5616 bool LHSSeenZero = false;
5617 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5618 bool RHSSeenZero = false;
5619 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5620 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5621 // If unsafe fp math optimization is enabled and there are no other uses of
5622 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5623 // to an integer comparison.
5624 if (CC == ISD::SETOEQ)
5625 CC = ISD::SETEQ;
5626 else if (CC == ISD::SETUNE)
5627 CC = ISD::SETNE;
5628
5629 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5630 SDValue ARMcc;
5631 if (LHS.getValueType() == MVT::f32) {
5632 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5633 bitcastf32Toi32(LHS, DAG), Mask);
5634 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5635 bitcastf32Toi32(RHS, DAG), Mask);
5636 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5637 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5638 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5639 Chain, Dest, ARMcc, CCR, Cmp);
5640 }
5641
5642 SDValue LHS1, LHS2;
5643 SDValue RHS1, RHS2;
5644 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5645 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5646 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5647 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5648 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5649 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5650 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5651 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5652 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5653 }
5654
5655 return SDValue();
5656}
5657
5658SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5659 SDValue Chain = Op.getOperand(0);
5660 SDValue Cond = Op.getOperand(1);
5661 SDValue Dest = Op.getOperand(2);
5662 SDLoc dl(Op);
5663
5664 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5665 // instruction.
5666 unsigned Opc = Cond.getOpcode();
5667 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5668 !Subtarget->isThumb1Only();
5669 if (Cond.getResNo() == 1 &&
5670 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5671 Opc == ISD::USUBO || OptimizeMul)) {
5672 // Only lower legal XALUO ops.
5673 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5674 return SDValue();
5675
5676 // The actual operation with overflow check.
5677 SDValue Value, OverflowCmp;
5678 SDValue ARMcc;
5679 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5680
5681 // Reverse the condition code.
5682 ARMCC::CondCodes CondCode =
5683 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5684 CondCode = ARMCC::getOppositeCondition(CondCode);
5685 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5686 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5687
5688 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5689 OverflowCmp);
5690 }
5691
5692 return SDValue();
5693}
5694
5695SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5696 SDValue Chain = Op.getOperand(0);
5697 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5698 SDValue LHS = Op.getOperand(2);
5699 SDValue RHS = Op.getOperand(3);
5700 SDValue Dest = Op.getOperand(4);
5701 SDLoc dl(Op);
5702
5703 if (isUnsupportedFloatingType(LHS.getValueType())) {
5704 DAG.getTargetLoweringInfo().softenSetCCOperands(
5705 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5706
5707 // If softenSetCCOperands only returned one value, we should compare it to
5708 // zero.
5709 if (!RHS.getNode()) {
5710 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5711 CC = ISD::SETNE;
5712 }
5713 }
5714
5715 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5716 // instruction.
5717 unsigned Opc = LHS.getOpcode();
5718 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5719 !Subtarget->isThumb1Only();
5720 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5721 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5722 Opc == ISD::USUBO || OptimizeMul) &&
5723 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5724 // Only lower legal XALUO ops.
5725 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5726 return SDValue();
5727
5728 // The actual operation with overflow check.
5729 SDValue Value, OverflowCmp;
5730 SDValue ARMcc;
5731 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5732
5733 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5734 // Reverse the condition code.
5735 ARMCC::CondCodes CondCode =
5736 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5737 CondCode = ARMCC::getOppositeCondition(CondCode);
5738 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5739 }
5740 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5741
5742 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5743 OverflowCmp);
5744 }
5745
5746 if (LHS.getValueType() == MVT::i32) {
5747 SDValue ARMcc;
5748 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5749 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5750 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5751 Chain, Dest, ARMcc, CCR, Cmp);
5752 }
5753
5754 if (getTargetMachine().Options.UnsafeFPMath &&
5755 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5756 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5757 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5758 return Result;
5759 }
5760
5761 ARMCC::CondCodes CondCode, CondCode2;
5762 FPCCToARMCC(CC, CondCode, CondCode2);
5763
5764 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5765 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5766 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5767 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5768 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5769 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5770 if (CondCode2 != ARMCC::AL) {
5771 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5772 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5773 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5774 }
5775 return Res;
5776}
5777
5778SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5779 SDValue Chain = Op.getOperand(0);
5780 SDValue Table = Op.getOperand(1);
5781 SDValue Index = Op.getOperand(2);
5782 SDLoc dl(Op);
5783
5784 EVT PTy = getPointerTy(DAG.getDataLayout());
5785 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5786 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5787 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5788 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5789 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5790 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5791 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5792 // which does another jump to the destination. This also makes it easier
5793 // to translate it to TBB / TBH later (Thumb2 only).
5794 // FIXME: This might not work if the function is extremely large.
5795 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5796 Addr, Op.getOperand(2), JTI);
5797 }
5798 if (isPositionIndependent() || Subtarget->isROPI()) {
5799 Addr =
5800 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5801 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5802 Chain = Addr.getValue(1);
5803 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5804 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5805 } else {
5806 Addr =
5807 DAG.getLoad(PTy, dl, Chain, Addr,
5808 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5809 Chain = Addr.getValue(1);
5810 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5811 }
5812}
5813
5814static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5815 EVT VT = Op.getValueType();
5816 SDLoc dl(Op);
5817
5818 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5819 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5820 return Op;
5821 return DAG.UnrollVectorOp(Op.getNode());
5822 }
5823
5824 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5825
5826 EVT NewTy;
5827 const EVT OpTy = Op.getOperand(0).getValueType();
5828 if (OpTy == MVT::v4f32)
5829 NewTy = MVT::v4i32;
5830 else if (OpTy == MVT::v4f16 && HasFullFP16)
5831 NewTy = MVT::v4i16;
5832 else if (OpTy == MVT::v8f16 && HasFullFP16)
5833 NewTy = MVT::v8i16;
5834 else
5835 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5835)
;
5836
5837 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5838 return DAG.UnrollVectorOp(Op.getNode());
5839
5840 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5841 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5842}
5843
5844SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5845 EVT VT = Op.getValueType();
5846 if (VT.isVector())
5847 return LowerVectorFP_TO_INT(Op, DAG);
5848
5849 bool IsStrict = Op->isStrictFPOpcode();
5850 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5851
5852 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5853 RTLIB::Libcall LC;
5854 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5855 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5856 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5857 Op.getValueType());
5858 else
5859 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5860 Op.getValueType());
5861 SDLoc Loc(Op);
5862 MakeLibCallOptions CallOptions;
5863 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5864 SDValue Result;
5865 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5866 CallOptions, Loc, Chain);
5867 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5868 }
5869
5870 // FIXME: Remove this when we have strict fp instruction selection patterns
5871 if (IsStrict) {
5872 SDLoc Loc(Op);
5873 SDValue Result =
5874 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5875 : ISD::FP_TO_UINT,
5876 Loc, Op.getValueType(), SrcVal);
5877 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5878 }
5879
5880 return Op;
5881}
5882
5883static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
5884 const ARMSubtarget *Subtarget) {
5885 EVT VT = Op.getValueType();
5886 EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5887 EVT FromVT = Op.getOperand(0).getValueType();
5888
5889 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f32)
5890 return Op;
5891 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f64 &&
5892 Subtarget->hasFP64())
5893 return Op;
5894 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f16 &&
5895 Subtarget->hasFullFP16())
5896 return Op;
5897 if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32 &&
5898 Subtarget->hasMVEFloatOps())
5899 return Op;
5900 if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16 &&
5901 Subtarget->hasMVEFloatOps())
5902 return Op;
5903
5904 if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
5905 return SDValue();
5906
5907 SDLoc DL(Op);
5908 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
5909 unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
5910 SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
5911 DAG.getValueType(VT.getScalarType()));
5912 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
5913 DAG.getConstant((1 << BW) - 1, DL, VT));
5914 if (IsSigned)
5915 Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
5916 DAG.getConstant(-(1 << BW), DL, VT));
5917 return Max;
5918}
5919
5920static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5921 EVT VT = Op.getValueType();
5922 SDLoc dl(Op);
5923
5924 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5925 if (VT.getVectorElementType() == MVT::f32)
5926 return Op;
5927 return DAG.UnrollVectorOp(Op.getNode());
5928 }
5929
5930 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5932, __extension__
__PRETTY_FUNCTION__))
5931 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5932, __extension__
__PRETTY_FUNCTION__))
5932 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5932, __extension__
__PRETTY_FUNCTION__))
;
5933
5934 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5935
5936 EVT DestVecType;
5937 if (VT == MVT::v4f32)
5938 DestVecType = MVT::v4i32;
5939 else if (VT == MVT::v4f16 && HasFullFP16)
5940 DestVecType = MVT::v4i16;
5941 else if (VT == MVT::v8f16 && HasFullFP16)
5942 DestVecType = MVT::v8i16;
5943 else
5944 return DAG.UnrollVectorOp(Op.getNode());
5945
5946 unsigned CastOpc;
5947 unsigned Opc;
5948 switch (Op.getOpcode()) {
5949 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5949)
;
5950 case ISD::SINT_TO_FP:
5951 CastOpc = ISD::SIGN_EXTEND;
5952 Opc = ISD::SINT_TO_FP;
5953 break;
5954 case ISD::UINT_TO_FP:
5955 CastOpc = ISD::ZERO_EXTEND;
5956 Opc = ISD::UINT_TO_FP;
5957 break;
5958 }
5959
5960 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5961 return DAG.getNode(Opc, dl, VT, Op);
5962}
5963
5964SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5965 EVT VT = Op.getValueType();
5966 if (VT.isVector())
5967 return LowerVectorINT_TO_FP(Op, DAG);
5968 if (isUnsupportedFloatingType(VT)) {
5969 RTLIB::Libcall LC;
5970 if (Op.getOpcode() == ISD::SINT_TO_FP)
5971 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5972 Op.getValueType());
5973 else
5974 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5975 Op.getValueType());
5976 MakeLibCallOptions CallOptions;
5977 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5978 CallOptions, SDLoc(Op)).first;
5979 }
5980
5981 return Op;
5982}
5983
5984SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5985 // Implement fcopysign with a fabs and a conditional fneg.
5986 SDValue Tmp0 = Op.getOperand(0);
5987 SDValue Tmp1 = Op.getOperand(1);
5988 SDLoc dl(Op);
5989 EVT VT = Op.getValueType();
5990 EVT SrcVT = Tmp1.getValueType();
5991 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5992 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5993 bool UseNEON = !InGPR && Subtarget->hasNEON();
5994
5995 if (UseNEON) {
5996 // Use VBSL to copy the sign bit.
5997 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5998 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5999 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
6000 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
6001 if (VT == MVT::f64)
6002 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
6003 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
6004 DAG.getConstant(32, dl, MVT::i32));
6005 else /*if (VT == MVT::f32)*/
6006 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
6007 if (SrcVT == MVT::f32) {
6008 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
6009 if (VT == MVT::f64)
6010 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
6011 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
6012 DAG.getConstant(32, dl, MVT::i32));
6013 } else if (VT == MVT::f32)
6014 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
6015 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
6016 DAG.getConstant(32, dl, MVT::i32));
6017 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
6018 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
6019
6020 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
6021 dl, MVT::i32);
6022 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
6023 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
6024 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
6025
6026 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
6027 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
6028 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
6029 if (VT == MVT::f32) {
6030 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
6031 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
6032 DAG.getConstant(0, dl, MVT::i32));
6033 } else {
6034 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
6035 }
6036
6037 return Res;
6038 }
6039
6040 // Bitcast operand 1 to i32.
6041 if (SrcVT == MVT::f64)
6042 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
6043 Tmp1).getValue(1);
6044 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
6045
6046