Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2522, column 20
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2021-01-24-223304-31662-1 -x c++ /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/IntrinsicsARM.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/PatternMatch.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MachineValueType.h"
101#include "llvm/Support/MathExtras.h"
102#include "llvm/Support/raw_ostream.h"
103#include "llvm/Target/TargetMachine.h"
104#include "llvm/Target/TargetOptions.h"
105#include <algorithm>
106#include <cassert>
107#include <cstdint>
108#include <cstdlib>
109#include <iterator>
110#include <limits>
111#include <string>
112#include <tuple>
113#include <utility>
114#include <vector>
115
116using namespace llvm;
117using namespace llvm::PatternMatch;
118
119#define DEBUG_TYPE"arm-isel" "arm-isel"
120
121STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
122STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
123STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
124STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
125 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
126
127static cl::opt<bool>
128ARMInterworking("arm-interworking", cl::Hidden,
129 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 cl::init(true));
131
132static cl::opt<bool> EnableConstpoolPromotion(
133 "arm-promote-constant", cl::Hidden,
134 cl::desc("Enable / disable promotion of unnamed_addr constants into "
135 "constant pools"),
136 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
137static cl::opt<unsigned> ConstpoolPromotionMaxSize(
138 "arm-promote-constant-max-size", cl::Hidden,
139 cl::desc("Maximum size of constant to promote into a constant pool"),
140 cl::init(64));
141static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
142 "arm-promote-constant-max-total", cl::Hidden,
143 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 cl::init(128));
145
146cl::opt<unsigned>
147MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
148 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
149 cl::init(2));
150
151// The APCS parameter registers.
152static const MCPhysReg GPRArgRegs[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154};
155
156void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
157 MVT PromotedBitwiseVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Promote all bit-wise operations.
197 if (VT.isInteger() && VT != PromotedBitwiseVT) {
198 setOperationAction(ISD::AND, VT, Promote);
199 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
200 setOperationAction(ISD::OR, VT, Promote);
201 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
202 setOperationAction(ISD::XOR, VT, Promote);
203 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
204 }
205
206 // Neon does not support vector divide/remainder operations.
207 setOperationAction(ISD::SDIV, VT, Expand);
208 setOperationAction(ISD::UDIV, VT, Expand);
209 setOperationAction(ISD::FDIV, VT, Expand);
210 setOperationAction(ISD::SREM, VT, Expand);
211 setOperationAction(ISD::UREM, VT, Expand);
212 setOperationAction(ISD::FREM, VT, Expand);
213 setOperationAction(ISD::SDIVREM, VT, Expand);
214 setOperationAction(ISD::UDIVREM, VT, Expand);
215
216 if (!VT.isFloatingPoint() &&
217 VT != MVT::v2i64 && VT != MVT::v1i64)
218 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
219 setOperationAction(Opcode, VT, Legal);
220 if (!VT.isFloatingPoint())
221 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
222 setOperationAction(Opcode, VT, Legal);
223}
224
225void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
226 addRegisterClass(VT, &ARM::DPRRegClass);
227 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
228}
229
230void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
231 addRegisterClass(VT, &ARM::DPairRegClass);
232 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
233}
234
235void ARMTargetLowering::setAllExpand(MVT VT) {
236 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
237 setOperationAction(Opc, VT, Expand);
238
239 // We support these really simple operations even on types where all
240 // the actual arithmetic has to be broken down into simpler
241 // operations or turned into library calls.
242 setOperationAction(ISD::BITCAST, VT, Legal);
243 setOperationAction(ISD::LOAD, VT, Legal);
244 setOperationAction(ISD::STORE, VT, Legal);
245 setOperationAction(ISD::UNDEF, VT, Legal);
246}
247
248void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
249 LegalizeAction Action) {
250 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
251 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
252 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
253}
254
255void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
256 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
257
258 for (auto VT : IntTypes) {
259 addRegisterClass(VT, &ARM::MQPRRegClass);
260 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
261 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
262 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
263 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
264 setOperationAction(ISD::SHL, VT, Custom);
265 setOperationAction(ISD::SRA, VT, Custom);
266 setOperationAction(ISD::SRL, VT, Custom);
267 setOperationAction(ISD::SMIN, VT, Legal);
268 setOperationAction(ISD::SMAX, VT, Legal);
269 setOperationAction(ISD::UMIN, VT, Legal);
270 setOperationAction(ISD::UMAX, VT, Legal);
271 setOperationAction(ISD::ABS, VT, Legal);
272 setOperationAction(ISD::SETCC, VT, Custom);
273 setOperationAction(ISD::MLOAD, VT, Custom);
274 setOperationAction(ISD::MSTORE, VT, Legal);
275 setOperationAction(ISD::CTLZ, VT, Legal);
276 setOperationAction(ISD::CTTZ, VT, Custom);
277 setOperationAction(ISD::BITREVERSE, VT, Legal);
278 setOperationAction(ISD::BSWAP, VT, Legal);
279 setOperationAction(ISD::SADDSAT, VT, Legal);
280 setOperationAction(ISD::UADDSAT, VT, Legal);
281 setOperationAction(ISD::SSUBSAT, VT, Legal);
282 setOperationAction(ISD::USUBSAT, VT, Legal);
283
284 // No native support for these.
285 setOperationAction(ISD::UDIV, VT, Expand);
286 setOperationAction(ISD::SDIV, VT, Expand);
287 setOperationAction(ISD::UREM, VT, Expand);
288 setOperationAction(ISD::SREM, VT, Expand);
289 setOperationAction(ISD::UDIVREM, VT, Expand);
290 setOperationAction(ISD::SDIVREM, VT, Expand);
291 setOperationAction(ISD::CTPOP, VT, Expand);
292 setOperationAction(ISD::SELECT, VT, Expand);
293 setOperationAction(ISD::SELECT_CC, VT, Expand);
294
295 // Vector reductions
296 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
299 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
300 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
301 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
302 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
303 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
304 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
305
306 if (!HasMVEFP) {
307 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
308 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
309 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
310 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
311 }
312
313 // Pre and Post inc are supported on loads and stores
314 for (unsigned im = (unsigned)ISD::PRE_INC;
315 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
316 setIndexedLoadAction(im, VT, Legal);
317 setIndexedStoreAction(im, VT, Legal);
318 setIndexedMaskedLoadAction(im, VT, Legal);
319 setIndexedMaskedStoreAction(im, VT, Legal);
320 }
321 }
322
323 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
324 for (auto VT : FloatTypes) {
325 addRegisterClass(VT, &ARM::MQPRRegClass);
326 if (!HasMVEFP)
327 setAllExpand(VT);
328
329 // These are legal or custom whether we have MVE.fp or not
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
336 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
337 setOperationAction(ISD::SETCC, VT, Custom);
338 setOperationAction(ISD::MLOAD, VT, Custom);
339 setOperationAction(ISD::MSTORE, VT, Legal);
340 setOperationAction(ISD::SELECT, VT, Expand);
341 setOperationAction(ISD::SELECT_CC, VT, Expand);
342
343 // Pre and Post inc are supported on loads and stores
344 for (unsigned im = (unsigned)ISD::PRE_INC;
345 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
346 setIndexedLoadAction(im, VT, Legal);
347 setIndexedStoreAction(im, VT, Legal);
348 setIndexedMaskedLoadAction(im, VT, Legal);
349 setIndexedMaskedStoreAction(im, VT, Legal);
350 }
351
352 if (HasMVEFP) {
353 setOperationAction(ISD::FMINNUM, VT, Legal);
354 setOperationAction(ISD::FMAXNUM, VT, Legal);
355 setOperationAction(ISD::FROUND, VT, Legal);
356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
357 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
360
361 // No native support for these.
362 setOperationAction(ISD::FDIV, VT, Expand);
363 setOperationAction(ISD::FREM, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FSIN, VT, Expand);
366 setOperationAction(ISD::FCOS, VT, Expand);
367 setOperationAction(ISD::FPOW, VT, Expand);
368 setOperationAction(ISD::FLOG, VT, Expand);
369 setOperationAction(ISD::FLOG2, VT, Expand);
370 setOperationAction(ISD::FLOG10, VT, Expand);
371 setOperationAction(ISD::FEXP, VT, Expand);
372 setOperationAction(ISD::FEXP2, VT, Expand);
373 setOperationAction(ISD::FNEARBYINT, VT, Expand);
374 }
375 }
376
377 // Custom Expand smaller than legal vector reductions to prevent false zero
378 // items being added.
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
387
388 // We 'support' these types up to bitcast/load/store level, regardless of
389 // MVE integer-only / float support. Only doing FP data processing on the FP
390 // vector types is inhibited at integer-only level.
391 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
392 for (auto VT : LongTypes) {
393 addRegisterClass(VT, &ARM::MQPRRegClass);
394 setAllExpand(VT);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
398 }
399 // We can do bitwise operations on v2i64 vectors
400 setOperationAction(ISD::AND, MVT::v2i64, Legal);
401 setOperationAction(ISD::OR, MVT::v2i64, Legal);
402 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
403
404 // It is legal to extload from v4i8 to v4i16 or v4i32.
405 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
406 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
407 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
408
409 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
410 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
411 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
412 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
415
416 // Some truncating stores are legal too.
417 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
418 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
419 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
420
421 // Pre and Post inc on these are legal, given the correct extends
422 for (unsigned im = (unsigned)ISD::PRE_INC;
423 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
424 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
425 setIndexedLoadAction(im, VT, Legal);
426 setIndexedStoreAction(im, VT, Legal);
427 setIndexedMaskedLoadAction(im, VT, Legal);
428 setIndexedMaskedStoreAction(im, VT, Legal);
429 }
430 }
431
432 // Predicate types
433 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
434 for (auto VT : pTypes) {
435 addRegisterClass(VT, &ARM::VCCRRegClass);
436 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
437 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
438 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
439 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
442 setOperationAction(ISD::SETCC, VT, Custom);
443 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
444 setOperationAction(ISD::LOAD, VT, Custom);
445 setOperationAction(ISD::STORE, VT, Custom);
446 setOperationAction(ISD::TRUNCATE, VT, Custom);
447 setOperationAction(ISD::VSELECT, VT, Expand);
448 setOperationAction(ISD::SELECT, VT, Expand);
449 }
450}
451
452ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
453 const ARMSubtarget &STI)
454 : TargetLowering(TM), Subtarget(&STI) {
455 RegInfo = Subtarget->getRegisterInfo();
456 Itins = Subtarget->getInstrItineraryData();
457
458 setBooleanContents(ZeroOrOneBooleanContent);
459 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
460
461 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
462 !Subtarget->isTargetWatchOS()) {
463 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
464 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
465 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
466 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
467 : CallingConv::ARM_AAPCS);
468 }
469
470 if (Subtarget->isTargetMachO()) {
471 // Uses VFP for Thumb libfuncs if available.
472 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
473 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
474 static const struct {
475 const RTLIB::Libcall Op;
476 const char * const Name;
477 const ISD::CondCode Cond;
478 } LibraryCalls[] = {
479 // Single-precision floating-point arithmetic.
480 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
481 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
482 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
483 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
484
485 // Double-precision floating-point arithmetic.
486 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
487 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
488 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
489 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
490
491 // Single-precision comparisons.
492 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
493 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
494 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
495 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
496 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
497 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
498 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
499
500 // Double-precision comparisons.
501 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
502 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
503 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
504 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
505 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
506 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
507 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
508
509 // Floating-point to integer conversions.
510 // i64 conversions are done via library routines even when generating VFP
511 // instructions, so use the same ones.
512 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
513 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
514 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
515 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
516
517 // Conversions between floating types.
518 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
519 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
520
521 // Integer to floating-point conversions.
522 // i64 conversions are done via library routines even when generating VFP
523 // instructions, so use the same ones.
524 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
525 // e.g., __floatunsidf vs. __floatunssidfvfp.
526 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
527 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
528 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
529 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
530 };
531
532 for (const auto &LC : LibraryCalls) {
533 setLibcallName(LC.Op, LC.Name);
534 if (LC.Cond != ISD::SETCC_INVALID)
535 setCmpLibcallCC(LC.Op, LC.Cond);
536 }
537 }
538 }
539
540 // These libcalls are not available in 32-bit.
541 setLibcallName(RTLIB::SHL_I128, nullptr);
542 setLibcallName(RTLIB::SRL_I128, nullptr);
543 setLibcallName(RTLIB::SRA_I128, nullptr);
544
545 // RTLIB
546 if (Subtarget->isAAPCS_ABI() &&
547 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
548 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
549 static const struct {
550 const RTLIB::Libcall Op;
551 const char * const Name;
552 const CallingConv::ID CC;
553 const ISD::CondCode Cond;
554 } LibraryCalls[] = {
555 // Double-precision floating-point arithmetic helper functions
556 // RTABI chapter 4.1.2, Table 2
557 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
558 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
559 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
560 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
561
562 // Double-precision floating-point comparison helper functions
563 // RTABI chapter 4.1.2, Table 3
564 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
565 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
566 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
567 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
568 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
569 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
570 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
571
572 // Single-precision floating-point arithmetic helper functions
573 // RTABI chapter 4.1.2, Table 4
574 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
575 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
576 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
577 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
578
579 // Single-precision floating-point comparison helper functions
580 // RTABI chapter 4.1.2, Table 5
581 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
582 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
583 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
584 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
585 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
586 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
587 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
588
589 // Floating-point to integer conversions.
590 // RTABI chapter 4.1.2, Table 6
591 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
594 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
595 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599
600 // Conversions between floating types.
601 // RTABI chapter 4.1.2, Table 7
602 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
605
606 // Integer to floating-point conversions.
607 // RTABI chapter 4.1.2, Table 8
608 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
612 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616
617 // Long long helper functions
618 // RTABI chapter 4.2, Table 9
619 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
620 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
621 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
622 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
623
624 // Integer division functions
625 // RTABI chapter 4.3.1
626 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
634 };
635
636 for (const auto &LC : LibraryCalls) {
637 setLibcallName(LC.Op, LC.Name);
638 setLibcallCallingConv(LC.Op, LC.CC);
639 if (LC.Cond != ISD::SETCC_INVALID)
640 setCmpLibcallCC(LC.Op, LC.Cond);
641 }
642
643 // EABI dependent RTLIB
644 if (TM.Options.EABIVersion == EABI::EABI4 ||
645 TM.Options.EABIVersion == EABI::EABI5) {
646 static const struct {
647 const RTLIB::Libcall Op;
648 const char *const Name;
649 const CallingConv::ID CC;
650 const ISD::CondCode Cond;
651 } MemOpsLibraryCalls[] = {
652 // Memory operations
653 // RTABI chapter 4.3.4
654 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
655 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
656 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
657 };
658
659 for (const auto &LC : MemOpsLibraryCalls) {
660 setLibcallName(LC.Op, LC.Name);
661 setLibcallCallingConv(LC.Op, LC.CC);
662 if (LC.Cond != ISD::SETCC_INVALID)
663 setCmpLibcallCC(LC.Op, LC.Cond);
664 }
665 }
666 }
667
668 if (Subtarget->isTargetWindows()) {
669 static const struct {
670 const RTLIB::Libcall Op;
671 const char * const Name;
672 const CallingConv::ID CC;
673 } LibraryCalls[] = {
674 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
675 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
676 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
677 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
678 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
679 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
680 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
681 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
682 };
683
684 for (const auto &LC : LibraryCalls) {
685 setLibcallName(LC.Op, LC.Name);
686 setLibcallCallingConv(LC.Op, LC.CC);
687 }
688 }
689
690 // Use divmod compiler-rt calls for iOS 5.0 and later.
691 if (Subtarget->isTargetMachO() &&
692 !(Subtarget->isTargetIOS() &&
693 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
694 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
695 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
696 }
697
698 // The half <-> float conversion functions are always soft-float on
699 // non-watchos platforms, but are needed for some targets which use a
700 // hard-float calling convention by default.
701 if (!Subtarget->isTargetWatchABI()) {
702 if (Subtarget->isAAPCS_ABI()) {
703 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
704 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
705 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
706 } else {
707 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
708 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
709 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
710 }
711 }
712
713 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
714 // a __gnu_ prefix (which is the default).
715 if (Subtarget->isTargetAEABI()) {
716 static const struct {
717 const RTLIB::Libcall Op;
718 const char * const Name;
719 const CallingConv::ID CC;
720 } LibraryCalls[] = {
721 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
722 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
723 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
724 };
725
726 for (const auto &LC : LibraryCalls) {
727 setLibcallName(LC.Op, LC.Name);
728 setLibcallCallingConv(LC.Op, LC.CC);
729 }
730 }
731
732 if (Subtarget->isThumb1Only())
733 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
734 else
735 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
736
737 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
738 Subtarget->hasFPRegs()) {
739 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
740 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
741 if (!Subtarget->hasVFP2Base())
742 setAllExpand(MVT::f32);
743 if (!Subtarget->hasFP64())
744 setAllExpand(MVT::f64);
745 }
746
747 if (Subtarget->hasFullFP16()) {
748 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
749 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
750 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
751
752 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
753 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
754 }
755
756 if (Subtarget->hasBF16()) {
757 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
758 setAllExpand(MVT::bf16);
759 if (!Subtarget->hasFullFP16())
760 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
761 }
762
763 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
764 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
765 setTruncStoreAction(VT, InnerVT, Expand);
766 addAllExtLoads(VT, InnerVT, Expand);
767 }
768
769 setOperationAction(ISD::MULHS, VT, Expand);
770 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
771 setOperationAction(ISD::MULHU, VT, Expand);
772 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
773
774 setOperationAction(ISD::BSWAP, VT, Expand);
775 }
776
777 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
778 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
779
780 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
781 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
782
783 if (Subtarget->hasMVEIntegerOps())
784 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
785
786 // Combine low-overhead loop intrinsics so that we can lower i1 types.
787 if (Subtarget->hasLOB()) {
788 setTargetDAGCombine(ISD::BRCOND);
789 setTargetDAGCombine(ISD::BR_CC);
790 }
791
792 if (Subtarget->hasNEON()) {
793 addDRTypeForNEON(MVT::v2f32);
794 addDRTypeForNEON(MVT::v8i8);
795 addDRTypeForNEON(MVT::v4i16);
796 addDRTypeForNEON(MVT::v2i32);
797 addDRTypeForNEON(MVT::v1i64);
798
799 addQRTypeForNEON(MVT::v4f32);
800 addQRTypeForNEON(MVT::v2f64);
801 addQRTypeForNEON(MVT::v16i8);
802 addQRTypeForNEON(MVT::v8i16);
803 addQRTypeForNEON(MVT::v4i32);
804 addQRTypeForNEON(MVT::v2i64);
805
806 if (Subtarget->hasFullFP16()) {
807 addQRTypeForNEON(MVT::v8f16);
808 addDRTypeForNEON(MVT::v4f16);
809 }
810
811 if (Subtarget->hasBF16()) {
812 addQRTypeForNEON(MVT::v8bf16);
813 addDRTypeForNEON(MVT::v4bf16);
814 }
815 }
816
817 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
818 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
819 // none of Neon, MVE or VFP supports any arithmetic operations on it.
820 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
823 // FIXME: Code duplication: FDIV and FREM are expanded always, see
824 // ARMTargetLowering::addTypeForNEON method for details.
825 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
826 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
827 // FIXME: Create unittest.
828 // In another words, find a way when "copysign" appears in DAG with vector
829 // operands.
830 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
831 // FIXME: Code duplication: SETCC has custom operation action, see
832 // ARMTargetLowering::addTypeForNEON method for details.
833 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
834 // FIXME: Create unittest for FNEG and for FABS.
835 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
836 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
837 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
838 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
839 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
840 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
841 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
842 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
843 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
844 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
845 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
846 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
847 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
848 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
849 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
850 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
851 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
852 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
853 }
854
855 if (Subtarget->hasNEON()) {
856 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
857 // supported for v4f32.
858 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
859 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
860 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
861 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
862 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
863 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
864 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
865 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
866 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
867 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
868 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
869 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
870 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
871 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
872
873 // Mark v2f32 intrinsics.
874 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
875 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
876 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
877 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
878 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
879 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
880 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
881 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
882 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
883 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
884 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
885 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
886 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
887 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
888
889 // Neon does not support some operations on v1i64 and v2i64 types.
890 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
891 // Custom handling for some quad-vector types to detect VMULL.
892 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
893 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
894 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
895 // Custom handling for some vector types to avoid expensive expansions
896 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
897 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
898 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
899 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
900 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
901 // a destination type that is wider than the source, and nor does
902 // it have a FP_TO_[SU]INT instruction with a narrower destination than
903 // source.
904 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
905 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
906 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
907 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
908 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
909 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
910 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
911 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
912
913 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
914 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
915
916 // NEON does not have single instruction CTPOP for vectors with element
917 // types wider than 8-bits. However, custom lowering can leverage the
918 // v8i8/v16i8 vcnt instruction.
919 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
920 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
921 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
922 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
923 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
924 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
925
926 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
927 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
928
929 // NEON does not have single instruction CTTZ for vectors.
930 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
931 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
932 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
933 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
934
935 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
936 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
937 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
938 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
939
940 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
941 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
942 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
943 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
944
945 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
946 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
947 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
948 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
949
950 // NEON only has FMA instructions as of VFP4.
951 if (!Subtarget->hasVFP4Base()) {
952 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
953 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
954 }
955
956 setTargetDAGCombine(ISD::SHL);
957 setTargetDAGCombine(ISD::SRL);
958 setTargetDAGCombine(ISD::SRA);
959 setTargetDAGCombine(ISD::FP_TO_SINT);
960 setTargetDAGCombine(ISD::FP_TO_UINT);
961 setTargetDAGCombine(ISD::FDIV);
962 setTargetDAGCombine(ISD::LOAD);
963
964 // It is legal to extload from v4i8 to v4i16 or v4i32.
965 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
966 MVT::v2i32}) {
967 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
968 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
970 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
971 }
972 }
973 }
974
975 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
976 setTargetDAGCombine(ISD::BUILD_VECTOR);
977 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
978 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
979 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
980 setTargetDAGCombine(ISD::STORE);
981 setTargetDAGCombine(ISD::SIGN_EXTEND);
982 setTargetDAGCombine(ISD::ZERO_EXTEND);
983 setTargetDAGCombine(ISD::ANY_EXTEND);
984 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
985 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
986 setTargetDAGCombine(ISD::INTRINSIC_VOID);
987 setTargetDAGCombine(ISD::VECREDUCE_ADD);
988 setTargetDAGCombine(ISD::ADD);
989 setTargetDAGCombine(ISD::BITCAST);
990 }
991 if (Subtarget->hasMVEIntegerOps()) {
992 setTargetDAGCombine(ISD::SMIN);
993 setTargetDAGCombine(ISD::UMIN);
994 setTargetDAGCombine(ISD::SMAX);
995 setTargetDAGCombine(ISD::UMAX);
996 setTargetDAGCombine(ISD::FP_EXTEND);
997 setTargetDAGCombine(ISD::SELECT);
998 setTargetDAGCombine(ISD::SELECT_CC);
999 }
1000
1001 if (!Subtarget->hasFP64()) {
1002 // When targeting a floating-point unit with only single-precision
1003 // operations, f64 is legal for the few double-precision instructions which
1004 // are present However, no double-precision operations other than moves,
1005 // loads and stores are provided by the hardware.
1006 setOperationAction(ISD::FADD, MVT::f64, Expand);
1007 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1008 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1009 setOperationAction(ISD::FMA, MVT::f64, Expand);
1010 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1011 setOperationAction(ISD::FREM, MVT::f64, Expand);
1012 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1013 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1014 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1015 setOperationAction(ISD::FABS, MVT::f64, Expand);
1016 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1017 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1018 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1019 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1020 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1021 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1022 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1023 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1024 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1025 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1026 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1027 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1028 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1029 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1030 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1031 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1032 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1033 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1034 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1035 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1036 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1037 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1038 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1039 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1040 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1041 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1042 }
1043
1044 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1045 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1046 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1047 if (Subtarget->hasFullFP16()) {
1048 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1049 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1050 }
1051 }
1052
1053 if (!Subtarget->hasFP16()) {
1054 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1055 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1056 }
1057
1058 computeRegisterProperties(Subtarget->getRegisterInfo());
1059
1060 // ARM does not have floating-point extending loads.
1061 for (MVT VT : MVT::fp_valuetypes()) {
1062 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1063 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1064 }
1065
1066 // ... or truncating stores
1067 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1068 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1069 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1070
1071 // ARM does not have i1 sign extending load.
1072 for (MVT VT : MVT::integer_valuetypes())
1073 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1074
1075 // ARM supports all 4 flavors of integer indexed load / store.
1076 if (!Subtarget->isThumb1Only()) {
1077 for (unsigned im = (unsigned)ISD::PRE_INC;
1078 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1079 setIndexedLoadAction(im, MVT::i1, Legal);
1080 setIndexedLoadAction(im, MVT::i8, Legal);
1081 setIndexedLoadAction(im, MVT::i16, Legal);
1082 setIndexedLoadAction(im, MVT::i32, Legal);
1083 setIndexedStoreAction(im, MVT::i1, Legal);
1084 setIndexedStoreAction(im, MVT::i8, Legal);
1085 setIndexedStoreAction(im, MVT::i16, Legal);
1086 setIndexedStoreAction(im, MVT::i32, Legal);
1087 }
1088 } else {
1089 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1090 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1091 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1092 }
1093
1094 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1095 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1096 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1097 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1098
1099 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1100 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1101 if (Subtarget->hasDSP()) {
1102 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1103 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1104 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1105 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1106 }
1107 if (Subtarget->hasBaseDSP()) {
1108 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1109 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1110 }
1111
1112 // i64 operation support.
1113 setOperationAction(ISD::MUL, MVT::i64, Expand);
1114 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1115 if (Subtarget->isThumb1Only()) {
1116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1118 }
1119 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1120 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1121 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1122
1123 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1124 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1125 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1126 setOperationAction(ISD::SRL, MVT::i64, Custom);
1127 setOperationAction(ISD::SRA, MVT::i64, Custom);
1128 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1130 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1131 setOperationAction(ISD::STORE, MVT::i64, Custom);
1132
1133 // MVE lowers 64 bit shifts to lsll and lsrl
1134 // assuming that ISD::SRL and SRA of i64 are already marked custom
1135 if (Subtarget->hasMVEIntegerOps())
1136 setOperationAction(ISD::SHL, MVT::i64, Custom);
1137
1138 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1139 if (Subtarget->isThumb1Only()) {
1140 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1141 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1142 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1143 }
1144
1145 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1146 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1147
1148 // ARM does not have ROTL.
1149 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1150 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1151 setOperationAction(ISD::ROTL, VT, Expand);
1152 setOperationAction(ISD::ROTR, VT, Expand);
1153 }
1154 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1155 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1156 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1157 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1158 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1159 }
1160
1161 // @llvm.readcyclecounter requires the Performance Monitors extension.
1162 // Default to the 0 expansion on unsupported platforms.
1163 // FIXME: Technically there are older ARM CPUs that have
1164 // implementation-specific ways of obtaining this information.
1165 if (Subtarget->hasPerfMon())
1166 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1167
1168 // Only ARMv6 has BSWAP.
1169 if (!Subtarget->hasV6Ops())
1170 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1171
1172 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1173 : Subtarget->hasDivideInARMMode();
1174 if (!hasDivide) {
1175 // These are expanded into libcalls if the cpu doesn't have HW divider.
1176 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1177 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1178 }
1179
1180 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1181 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1182 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1183
1184 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1185 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1186 }
1187
1188 setOperationAction(ISD::SREM, MVT::i32, Expand);
1189 setOperationAction(ISD::UREM, MVT::i32, Expand);
1190
1191 // Register based DivRem for AEABI (RTABI 4.2)
1192 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1193 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1194 Subtarget->isTargetWindows()) {
1195 setOperationAction(ISD::SREM, MVT::i64, Custom);
1196 setOperationAction(ISD::UREM, MVT::i64, Custom);
1197 HasStandaloneRem = false;
1198
1199 if (Subtarget->isTargetWindows()) {
1200 const struct {
1201 const RTLIB::Libcall Op;
1202 const char * const Name;
1203 const CallingConv::ID CC;
1204 } LibraryCalls[] = {
1205 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1206 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1207 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1208 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1209
1210 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1211 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1212 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1213 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1214 };
1215
1216 for (const auto &LC : LibraryCalls) {
1217 setLibcallName(LC.Op, LC.Name);
1218 setLibcallCallingConv(LC.Op, LC.CC);
1219 }
1220 } else {
1221 const struct {
1222 const RTLIB::Libcall Op;
1223 const char * const Name;
1224 const CallingConv::ID CC;
1225 } LibraryCalls[] = {
1226 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1227 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1228 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1229 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1230
1231 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1232 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1233 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1234 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1235 };
1236
1237 for (const auto &LC : LibraryCalls) {
1238 setLibcallName(LC.Op, LC.Name);
1239 setLibcallCallingConv(LC.Op, LC.CC);
1240 }
1241 }
1242
1243 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1244 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1245 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1246 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1247 } else {
1248 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1249 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1250 }
1251
1252 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1253 // MSVCRT doesn't have powi; fall back to pow
1254 setLibcallName(RTLIB::POWI_F32, nullptr);
1255 setLibcallName(RTLIB::POWI_F64, nullptr);
1256 }
1257
1258 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1259 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1260 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1261 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1262
1263 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1264 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1265
1266 // Use the default implementation.
1267 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1268 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1269 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1270 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1271 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1272 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1273
1274 if (Subtarget->isTargetWindows())
1275 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1276 else
1277 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1278
1279 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1280 // the default expansion.
1281 InsertFencesForAtomic = false;
1282 if (Subtarget->hasAnyDataBarrier() &&
1283 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1284 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1285 // to ldrex/strex loops already.
1286 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1287 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1288 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1289
1290 // On v8, we have particularly efficient implementations of atomic fences
1291 // if they can be combined with nearby atomic loads and stores.
1292 if (!Subtarget->hasAcquireRelease() ||
1293 getTargetMachine().getOptLevel() == 0) {
1294 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1295 InsertFencesForAtomic = true;
1296 }
1297 } else {
1298 // If there's anything we can use as a barrier, go through custom lowering
1299 // for ATOMIC_FENCE.
1300 // If target has DMB in thumb, Fences can be inserted.
1301 if (Subtarget->hasDataBarrier())
1302 InsertFencesForAtomic = true;
1303
1304 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1305 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1306
1307 // Set them all for expansion, which will force libcalls.
1308 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1309 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1310 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1311 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1312 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1313 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1314 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1315 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1316 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1317 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1318 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1319 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1320 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1321 // Unordered/Monotonic case.
1322 if (!InsertFencesForAtomic) {
1323 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1324 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1325 }
1326 }
1327
1328 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1329
1330 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1331 if (!Subtarget->hasV6Ops()) {
1332 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1333 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1334 }
1335 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1336
1337 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1338 !Subtarget->isThumb1Only()) {
1339 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1340 // iff target supports vfp2.
1341 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1342 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1343 }
1344
1345 // We want to custom lower some of our intrinsics.
1346 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1347 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1348 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1349 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1350 if (Subtarget->useSjLjEH())
1351 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1352
1353 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1354 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1355 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1356 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1357 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1358 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1359 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1360 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1361 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1362 if (Subtarget->hasFullFP16()) {
1363 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1364 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1365 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1366 }
1367
1368 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1369
1370 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1371 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1372 if (Subtarget->hasFullFP16())
1373 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1374 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1375 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1376 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1377
1378 // We don't support sin/cos/fmod/copysign/pow
1379 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1380 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1381 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1382 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1383 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1384 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1385 setOperationAction(ISD::FREM, MVT::f64, Expand);
1386 setOperationAction(ISD::FREM, MVT::f32, Expand);
1387 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1388 !Subtarget->isThumb1Only()) {
1389 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1390 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1391 }
1392 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1393 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1394
1395 if (!Subtarget->hasVFP4Base()) {
1396 setOperationAction(ISD::FMA, MVT::f64, Expand);
1397 setOperationAction(ISD::FMA, MVT::f32, Expand);
1398 }
1399
1400 // Various VFP goodness
1401 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1402 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1403 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1404 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1405 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1406 }
1407
1408 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1409 if (!Subtarget->hasFP16()) {
1410 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1411 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1412 }
1413
1414 // Strict floating-point comparisons need custom lowering.
1415 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1416 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1417 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1418 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1419 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1420 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1421 }
1422
1423 // Use __sincos_stret if available.
1424 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1425 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1426 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1427 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1428 }
1429
1430 // FP-ARMv8 implements a lot of rounding-like FP operations.
1431 if (Subtarget->hasFPARMv8Base()) {
1432 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1433 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1434 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1435 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1436 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1437 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1438 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1439 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1440 if (Subtarget->hasNEON()) {
1441 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1442 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1443 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1444 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1445 }
1446
1447 if (Subtarget->hasFP64()) {
1448 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1449 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1450 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1451 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1453 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1454 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1455 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1456 }
1457 }
1458
1459 // FP16 often need to be promoted to call lib functions
1460 if (Subtarget->hasFullFP16()) {
1461 setOperationAction(ISD::FREM, MVT::f16, Promote);
1462 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1463 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1464 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1465 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1466 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1467 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1468 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1469 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1470 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1471 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1472 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1473
1474 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1475 }
1476
1477 if (Subtarget->hasNEON()) {
1478 // vmin and vmax aren't available in a scalar form, so we can use
1479 // a NEON instruction with an undef lane instead. This has a performance
1480 // penalty on some cores, so we don't do this unless we have been
1481 // asked to by the core tuning model.
1482 if (Subtarget->useNEONForSinglePrecisionFP()) {
1483 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1484 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1485 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1486 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1487 }
1488 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1489 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1490 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1491 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1492
1493 if (Subtarget->hasFullFP16()) {
1494 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1495 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1496 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1497 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1498
1499 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1500 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1501 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1502 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1503 }
1504 }
1505
1506 // We have target-specific dag combine patterns for the following nodes:
1507 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1508 setTargetDAGCombine(ISD::ADD);
1509 setTargetDAGCombine(ISD::SUB);
1510 setTargetDAGCombine(ISD::MUL);
1511 setTargetDAGCombine(ISD::AND);
1512 setTargetDAGCombine(ISD::OR);
1513 setTargetDAGCombine(ISD::XOR);
1514
1515 if (Subtarget->hasMVEIntegerOps())
1516 setTargetDAGCombine(ISD::VSELECT);
1517
1518 if (Subtarget->hasV6Ops())
1519 setTargetDAGCombine(ISD::SRL);
1520 if (Subtarget->isThumb1Only())
1521 setTargetDAGCombine(ISD::SHL);
1522
1523 setStackPointerRegisterToSaveRestore(ARM::SP);
1524
1525 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1526 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1527 setSchedulingPreference(Sched::RegPressure);
1528 else
1529 setSchedulingPreference(Sched::Hybrid);
1530
1531 //// temporary - rewrite interface to use type
1532 MaxStoresPerMemset = 8;
1533 MaxStoresPerMemsetOptSize = 4;
1534 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1535 MaxStoresPerMemcpyOptSize = 2;
1536 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1537 MaxStoresPerMemmoveOptSize = 2;
1538
1539 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1540 // are at least 4 bytes aligned.
1541 setMinStackArgumentAlignment(Align(4));
1542
1543 // Prefer likely predicted branches to selects on out-of-order cores.
1544 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1545
1546 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1547
1548 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1549
1550 if (Subtarget->isThumb() || Subtarget->isThumb2())
1551 setTargetDAGCombine(ISD::ABS);
1552}
1553
1554bool ARMTargetLowering::useSoftFloat() const {
1555 return Subtarget->useSoftFloat();
1556}
1557
1558// FIXME: It might make sense to define the representative register class as the
1559// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1560// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1561// SPR's representative would be DPR_VFP2. This should work well if register
1562// pressure tracking were modified such that a register use would increment the
1563// pressure of the register class's representative and all of it's super
1564// classes' representatives transitively. We have not implemented this because
1565// of the difficulty prior to coalescing of modeling operand register classes
1566// due to the common occurrence of cross class copies and subregister insertions
1567// and extractions.
1568std::pair<const TargetRegisterClass *, uint8_t>
1569ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1570 MVT VT) const {
1571 const TargetRegisterClass *RRC = nullptr;
1572 uint8_t Cost = 1;
1573 switch (VT.SimpleTy) {
1574 default:
1575 return TargetLowering::findRepresentativeClass(TRI, VT);
1576 // Use DPR as representative register class for all floating point
1577 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1578 // the cost is 1 for both f32 and f64.
1579 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1580 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1581 RRC = &ARM::DPRRegClass;
1582 // When NEON is used for SP, only half of the register file is available
1583 // because operations that define both SP and DP results will be constrained
1584 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1585 // coalescing by double-counting the SP regs. See the FIXME above.
1586 if (Subtarget->useNEONForSinglePrecisionFP())
1587 Cost = 2;
1588 break;
1589 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1590 case MVT::v4f32: case MVT::v2f64:
1591 RRC = &ARM::DPRRegClass;
1592 Cost = 2;
1593 break;
1594 case MVT::v4i64:
1595 RRC = &ARM::DPRRegClass;
1596 Cost = 4;
1597 break;
1598 case MVT::v8i64:
1599 RRC = &ARM::DPRRegClass;
1600 Cost = 8;
1601 break;
1602 }
1603 return std::make_pair(RRC, Cost);
1604}
1605
1606const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1607 switch ((ARMISD::NodeType)Opcode) {
1608 case ARMISD::FIRST_NUMBER: break;
1609 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1610 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1611 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1612 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1613 case ARMISD::CALL: return "ARMISD::CALL";
1614 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1615 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1616 case ARMISD::tSECALL: return "ARMISD::tSECALL";
1617 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1618 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1619 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1620 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1621 case ARMISD::SERET_FLAG: return "ARMISD::SERET_FLAG";
1622 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1623 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1624 case ARMISD::CMP: return "ARMISD::CMP";
1625 case ARMISD::CMN: return "ARMISD::CMN";
1626 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1627 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1628 case ARMISD::CMPFPE: return "ARMISD::CMPFPE";
1629 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1630 case ARMISD::CMPFPEw0: return "ARMISD::CMPFPEw0";
1631 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1632 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1633
1634 case ARMISD::CMOV: return "ARMISD::CMOV";
1635 case ARMISD::SUBS: return "ARMISD::SUBS";
1636
1637 case ARMISD::SSAT: return "ARMISD::SSAT";
1638 case ARMISD::USAT: return "ARMISD::USAT";
1639
1640 case ARMISD::ASRL: return "ARMISD::ASRL";
1641 case ARMISD::LSRL: return "ARMISD::LSRL";
1642 case ARMISD::LSLL: return "ARMISD::LSLL";
1643
1644 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1645 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1646 case ARMISD::RRX: return "ARMISD::RRX";
1647
1648 case ARMISD::ADDC: return "ARMISD::ADDC";
1649 case ARMISD::ADDE: return "ARMISD::ADDE";
1650 case ARMISD::SUBC: return "ARMISD::SUBC";
1651 case ARMISD::SUBE: return "ARMISD::SUBE";
1652 case ARMISD::LSLS: return "ARMISD::LSLS";
1653
1654 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1655 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1656 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1657 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1658 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1659
1660 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1661 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1662 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1663
1664 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1665
1666 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1667
1668 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1669
1670 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1671
1672 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1673
1674 case ARMISD::LDRD: return "ARMISD::LDRD";
1675 case ARMISD::STRD: return "ARMISD::STRD";
1676
1677 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1678 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1679
1680 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1681 case ARMISD::VECTOR_REG_CAST: return "ARMISD::VECTOR_REG_CAST";
1682 case ARMISD::VCMP: return "ARMISD::VCMP";
1683 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1684 case ARMISD::VTST: return "ARMISD::VTST";
1685
1686 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1687 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1688 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1689 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1690 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1691 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1692 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1693 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1694 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1695 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1696 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1697 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1698 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1699 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1700 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1701 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1702 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1703 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1704 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1705 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1706 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1707 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1708 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1709 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1710 case ARMISD::VDUP: return "ARMISD::VDUP";
1711 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1712 case ARMISD::VEXT: return "ARMISD::VEXT";
1713 case ARMISD::VREV64: return "ARMISD::VREV64";
1714 case ARMISD::VREV32: return "ARMISD::VREV32";
1715 case ARMISD::VREV16: return "ARMISD::VREV16";
1716 case ARMISD::VZIP: return "ARMISD::VZIP";
1717 case ARMISD::VUZP: return "ARMISD::VUZP";
1718 case ARMISD::VTRN: return "ARMISD::VTRN";
1719 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1720 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1721 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1722 case ARMISD::VQMOVNs: return "ARMISD::VQMOVNs";
1723 case ARMISD::VQMOVNu: return "ARMISD::VQMOVNu";
1724 case ARMISD::VCVTN: return "ARMISD::VCVTN";
1725 case ARMISD::VCVTL: return "ARMISD::VCVTL";
1726 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1727 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1728 case ARMISD::VQDMULH: return "ARMISD::VQDMULH";
1729 case ARMISD::VADDVs: return "ARMISD::VADDVs";
1730 case ARMISD::VADDVu: return "ARMISD::VADDVu";
1731 case ARMISD::VADDVps: return "ARMISD::VADDVps";
1732 case ARMISD::VADDVpu: return "ARMISD::VADDVpu";
1733 case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
1734 case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
1735 case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
1736 case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu";
1737 case ARMISD::VADDLVps: return "ARMISD::VADDLVps";
1738 case ARMISD::VADDLVpu: return "ARMISD::VADDLVpu";
1739 case ARMISD::VADDLVAps: return "ARMISD::VADDLVAps";
1740 case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu";
1741 case ARMISD::VMLAVs: return "ARMISD::VMLAVs";
1742 case ARMISD::VMLAVu: return "ARMISD::VMLAVu";
1743 case ARMISD::VMLAVps: return "ARMISD::VMLAVps";
1744 case ARMISD::VMLAVpu: return "ARMISD::VMLAVpu";
1745 case ARMISD::VMLALVs: return "ARMISD::VMLALVs";
1746 case ARMISD::VMLALVu: return "ARMISD::VMLALVu";
1747 case ARMISD::VMLALVps: return "ARMISD::VMLALVps";
1748 case ARMISD::VMLALVpu: return "ARMISD::VMLALVpu";
1749 case ARMISD::VMLALVAs: return "ARMISD::VMLALVAs";
1750 case ARMISD::VMLALVAu: return "ARMISD::VMLALVAu";
1751 case ARMISD::VMLALVAps: return "ARMISD::VMLALVAps";
1752 case ARMISD::VMLALVApu: return "ARMISD::VMLALVApu";
1753 case ARMISD::VMINVu: return "ARMISD::VMINVu";
1754 case ARMISD::VMINVs: return "ARMISD::VMINVs";
1755 case ARMISD::VMAXVu: return "ARMISD::VMAXVu";
1756 case ARMISD::VMAXVs: return "ARMISD::VMAXVs";
1757 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1758 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1759 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1760 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1761 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1762 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1763 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1764 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1765 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1766 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1767 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1768 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1769 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1770 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1771 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1772 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1773 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1774 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1775 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1776 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1777 case ARMISD::BFI: return "ARMISD::BFI";
1778 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1779 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1780 case ARMISD::VBSP: return "ARMISD::VBSP";
1781 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1782 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1783 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1784 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1785 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1786 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1787 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1788 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1789 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1790 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1791 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1792 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1793 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1794 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1795 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1796 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1797 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1798 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1799 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1800 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1801 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1802 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1803 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1804 case ARMISD::WLS: return "ARMISD::WLS";
1805 case ARMISD::LE: return "ARMISD::LE";
1806 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1807 case ARMISD::CSINV: return "ARMISD::CSINV";
1808 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1809 case ARMISD::CSINC: return "ARMISD::CSINC";
1810 }
1811 return nullptr;
1812}
1813
1814EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1815 EVT VT) const {
1816 if (!VT.isVector())
1817 return getPointerTy(DL);
1818
1819 // MVE has a predicate register.
1820 if (Subtarget->hasMVEIntegerOps() &&
1821 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1822 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1823 return VT.changeVectorElementTypeToInteger();
1824}
1825
1826/// getRegClassFor - Return the register class that should be used for the
1827/// specified value type.
1828const TargetRegisterClass *
1829ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1830 (void)isDivergent;
1831 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1832 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1833 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1834 // MVE Q registers.
1835 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1836 if (VT == MVT::v4i64)
1837 return &ARM::QQPRRegClass;
1838 if (VT == MVT::v8i64)
1839 return &ARM::QQQQPRRegClass;
1840 }
1841 return TargetLowering::getRegClassFor(VT);
1842}
1843
1844// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1845// source/dest is aligned and the copy size is large enough. We therefore want
1846// to align such objects passed to memory intrinsics.
1847bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1848 unsigned &PrefAlign) const {
1849 if (!isa<MemIntrinsic>(CI))
1850 return false;
1851 MinSize = 8;
1852 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1853 // cycle faster than 4-byte aligned LDM.
1854 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1855 return true;
1856}
1857
1858// Create a fast isel object.
1859FastISel *
1860ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1861 const TargetLibraryInfo *libInfo) const {
1862 return ARM::createFastISel(funcInfo, libInfo);
1863}
1864
1865Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1866 unsigned NumVals = N->getNumValues();
1867 if (!NumVals)
1868 return Sched::RegPressure;
1869
1870 for (unsigned i = 0; i != NumVals; ++i) {
1871 EVT VT = N->getValueType(i);
1872 if (VT == MVT::Glue || VT == MVT::Other)
1873 continue;
1874 if (VT.isFloatingPoint() || VT.isVector())
1875 return Sched::ILP;
1876 }
1877
1878 if (!N->isMachineOpcode())
1879 return Sched::RegPressure;
1880
1881 // Load are scheduled for latency even if there instruction itinerary
1882 // is not available.
1883 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1884 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1885
1886 if (MCID.getNumDefs() == 0)
1887 return Sched::RegPressure;
1888 if (!Itins->isEmpty() &&
1889 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1890 return Sched::ILP;
1891
1892 return Sched::RegPressure;
1893}
1894
1895//===----------------------------------------------------------------------===//
1896// Lowering Code
1897//===----------------------------------------------------------------------===//
1898
1899static bool isSRL16(const SDValue &Op) {
1900 if (Op.getOpcode() != ISD::SRL)
1901 return false;
1902 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1903 return Const->getZExtValue() == 16;
1904 return false;
1905}
1906
1907static bool isSRA16(const SDValue &Op) {
1908 if (Op.getOpcode() != ISD::SRA)
1909 return false;
1910 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1911 return Const->getZExtValue() == 16;
1912 return false;
1913}
1914
1915static bool isSHL16(const SDValue &Op) {
1916 if (Op.getOpcode() != ISD::SHL)
1917 return false;
1918 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1919 return Const->getZExtValue() == 16;
1920 return false;
1921}
1922
1923// Check for a signed 16-bit value. We special case SRA because it makes it
1924// more simple when also looking for SRAs that aren't sign extending a
1925// smaller value. Without the check, we'd need to take extra care with
1926// checking order for some operations.
1927static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1928 if (isSRA16(Op))
1929 return isSHL16(Op.getOperand(0));
1930 return DAG.ComputeNumSignBits(Op) == 17;
1931}
1932
1933/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1934static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1935 switch (CC) {
1936 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1936)
;
1937 case ISD::SETNE: return ARMCC::NE;
1938 case ISD::SETEQ: return ARMCC::EQ;
1939 case ISD::SETGT: return ARMCC::GT;
1940 case ISD::SETGE: return ARMCC::GE;
1941 case ISD::SETLT: return ARMCC::LT;
1942 case ISD::SETLE: return ARMCC::LE;
1943 case ISD::SETUGT: return ARMCC::HI;
1944 case ISD::SETUGE: return ARMCC::HS;
1945 case ISD::SETULT: return ARMCC::LO;
1946 case ISD::SETULE: return ARMCC::LS;
1947 }
1948}
1949
1950/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1951static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1952 ARMCC::CondCodes &CondCode2) {
1953 CondCode2 = ARMCC::AL;
1954 switch (CC) {
1955 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1955)
;
1956 case ISD::SETEQ:
1957 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1958 case ISD::SETGT:
1959 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1960 case ISD::SETGE:
1961 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1962 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1963 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1964 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1965 case ISD::SETO: CondCode = ARMCC::VC; break;
1966 case ISD::SETUO: CondCode = ARMCC::VS; break;
1967 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1968 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1969 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1970 case ISD::SETLT:
1971 case ISD::SETULT: CondCode = ARMCC::LT; break;
1972 case ISD::SETLE:
1973 case ISD::SETULE: CondCode = ARMCC::LE; break;
1974 case ISD::SETNE:
1975 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1976 }
1977}
1978
1979//===----------------------------------------------------------------------===//
1980// Calling Convention Implementation
1981//===----------------------------------------------------------------------===//
1982
1983/// getEffectiveCallingConv - Get the effective calling convention, taking into
1984/// account presence of floating point hardware and calling convention
1985/// limitations, such as support for variadic functions.
1986CallingConv::ID
1987ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1988 bool isVarArg) const {
1989 switch (CC) {
1990 default:
1991 report_fatal_error("Unsupported calling convention");
1992 case CallingConv::ARM_AAPCS:
1993 case CallingConv::ARM_APCS:
1994 case CallingConv::GHC:
1995 case CallingConv::CFGuard_Check:
1996 return CC;
1997 case CallingConv::PreserveMost:
1998 return CallingConv::PreserveMost;
1999 case CallingConv::ARM_AAPCS_VFP:
2000 case CallingConv::Swift:
2001 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2002 case CallingConv::C:
2003 if (!Subtarget->isAAPCS_ABI())
2004 return CallingConv::ARM_APCS;
2005 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2006 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2007 !isVarArg)
2008 return CallingConv::ARM_AAPCS_VFP;
2009 else
2010 return CallingConv::ARM_AAPCS;
2011 case CallingConv::Fast:
2012 case CallingConv::CXX_FAST_TLS:
2013 if (!Subtarget->isAAPCS_ABI()) {
2014 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2015 return CallingConv::Fast;
2016 return CallingConv::ARM_APCS;
2017 } else if (Subtarget->hasVFP2Base() &&
2018 !Subtarget->isThumb1Only() && !isVarArg)
2019 return CallingConv::ARM_AAPCS_VFP;
2020 else
2021 return CallingConv::ARM_AAPCS;
2022 }
2023}
2024
2025CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2026 bool isVarArg) const {
2027 return CCAssignFnForNode(CC, false, isVarArg);
2028}
2029
2030CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2031 bool isVarArg) const {
2032 return CCAssignFnForNode(CC, true, isVarArg);
2033}
2034
2035/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2036/// CallingConvention.
2037CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2038 bool Return,
2039 bool isVarArg) const {
2040 switch (getEffectiveCallingConv(CC, isVarArg)) {
2041 default:
2042 report_fatal_error("Unsupported calling convention");
2043 case CallingConv::ARM_APCS:
2044 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2045 case CallingConv::ARM_AAPCS:
2046 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2047 case CallingConv::ARM_AAPCS_VFP:
2048 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2049 case CallingConv::Fast:
2050 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2051 case CallingConv::GHC:
2052 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2053 case CallingConv::PreserveMost:
2054 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2055 case CallingConv::CFGuard_Check:
2056 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2057 }
2058}
2059
2060SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2061 MVT LocVT, MVT ValVT, SDValue Val) const {
2062 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2063 Val);
2064 if (Subtarget->hasFullFP16()) {
2065 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2066 } else {
2067 Val = DAG.getNode(ISD::TRUNCATE, dl,
2068 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2069 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2070 }
2071 return Val;
2072}
2073
2074SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2075 MVT LocVT, MVT ValVT,
2076 SDValue Val) const {
2077 if (Subtarget->hasFullFP16()) {
2078 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2079 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2080 } else {
2081 Val = DAG.getNode(ISD::BITCAST, dl,
2082 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2083 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2084 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2085 }
2086 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2087}
2088
2089/// LowerCallResult - Lower the result values of a call into the
2090/// appropriate copies out of appropriate physical registers.
2091SDValue ARMTargetLowering::LowerCallResult(
2092 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2093 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2094 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2095 SDValue ThisVal) const {
2096 // Assign locations to each value returned by this call.
2097 SmallVector<CCValAssign, 16> RVLocs;
2098 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2099 *DAG.getContext());
2100 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2101
2102 // Copy all of the result registers out of their specified physreg.
2103 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2104 CCValAssign VA = RVLocs[i];
2105
2106 // Pass 'this' value directly from the argument to return value, to avoid
2107 // reg unit interference
2108 if (i == 0 && isThisReturn) {
2109 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2110, __PRETTY_FUNCTION__))
2110 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2110, __PRETTY_FUNCTION__))
;
2111 InVals.push_back(ThisVal);
2112 continue;
2113 }
2114
2115 SDValue Val;
2116 if (VA.needsCustom() &&
2117 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2118 // Handle f64 or half of a v2f64.
2119 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2120 InFlag);
2121 Chain = Lo.getValue(1);
2122 InFlag = Lo.getValue(2);
2123 VA = RVLocs[++i]; // skip ahead to next loc
2124 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2125 InFlag);
2126 Chain = Hi.getValue(1);
2127 InFlag = Hi.getValue(2);
2128 if (!Subtarget->isLittle())
2129 std::swap (Lo, Hi);
2130 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2131
2132 if (VA.getLocVT() == MVT::v2f64) {
2133 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2134 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2135 DAG.getConstant(0, dl, MVT::i32));
2136
2137 VA = RVLocs[++i]; // skip ahead to next loc
2138 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2139 Chain = Lo.getValue(1);
2140 InFlag = Lo.getValue(2);
2141 VA = RVLocs[++i]; // skip ahead to next loc
2142 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2143 Chain = Hi.getValue(1);
2144 InFlag = Hi.getValue(2);
2145 if (!Subtarget->isLittle())
2146 std::swap (Lo, Hi);
2147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2149 DAG.getConstant(1, dl, MVT::i32));
2150 }
2151 } else {
2152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2153 InFlag);
2154 Chain = Val.getValue(1);
2155 InFlag = Val.getValue(2);
2156 }
2157
2158 switch (VA.getLocInfo()) {
2159 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2159)
;
2160 case CCValAssign::Full: break;
2161 case CCValAssign::BCvt:
2162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2163 break;
2164 }
2165
2166 // f16 arguments have their size extended to 4 bytes and passed as if they
2167 // had been copied to the LSBs of a 32-bit register.
2168 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2169 if (VA.needsCustom() &&
2170 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2171 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2172
2173 InVals.push_back(Val);
2174 }
2175
2176 return Chain;
2177}
2178
2179/// LowerMemOpCallTo - Store the argument to the stack.
2180SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2181 SDValue Arg, const SDLoc &dl,
2182 SelectionDAG &DAG,
2183 const CCValAssign &VA,
2184 ISD::ArgFlagsTy Flags) const {
2185 unsigned LocMemOffset = VA.getLocMemOffset();
2186 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2187 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2188 StackPtr, PtrOff);
2189 return DAG.getStore(
2190 Chain, dl, Arg, PtrOff,
2191 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2192}
2193
2194void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2195 SDValue Chain, SDValue &Arg,
2196 RegsToPassVector &RegsToPass,
2197 CCValAssign &VA, CCValAssign &NextVA,
2198 SDValue &StackPtr,
2199 SmallVectorImpl<SDValue> &MemOpChains,
2200 ISD::ArgFlagsTy Flags) const {
2201 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2202 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2203 unsigned id = Subtarget->isLittle() ? 0 : 1;
2204 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2205
2206 if (NextVA.isRegLoc())
2207 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2208 else {
2209 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2209, __PRETTY_FUNCTION__))
;
2210 if (!StackPtr.getNode())
2211 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2212 getPointerTy(DAG.getDataLayout()));
2213
2214 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2215 dl, DAG, NextVA,
2216 Flags));
2217 }
2218}
2219
2220/// LowerCall - Lowering a call into a callseq_start <-
2221/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2222/// nodes.
2223SDValue
2224ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2225 SmallVectorImpl<SDValue> &InVals) const {
2226 SelectionDAG &DAG = CLI.DAG;
2227 SDLoc &dl = CLI.DL;
2228 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2229 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2230 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2231 SDValue Chain = CLI.Chain;
2232 SDValue Callee = CLI.Callee;
2233 bool &isTailCall = CLI.IsTailCall;
2234 CallingConv::ID CallConv = CLI.CallConv;
2235 bool doesNotRet = CLI.DoesNotReturn;
2236 bool isVarArg = CLI.IsVarArg;
2237
2238 MachineFunction &MF = DAG.getMachineFunction();
2239 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2240 MachineFunction::CallSiteInfo CSInfo;
2241 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2242 bool isThisReturn = false;
2243 bool isCmseNSCall = false;
2244 bool PreferIndirect = false;
2245
2246 // Determine whether this is a non-secure function call.
2247 if (CLI.CB && CLI.CB->getAttributes().hasFnAttribute("cmse_nonsecure_call"))
2
Assuming field 'CB' is null
3
Taking false branch
2248 isCmseNSCall = true;
2249
2250 // Disable tail calls if they're not supported.
2251 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
5
Taking false branch
2252 isTailCall = false;
2253
2254 // For both the non-secure calls and the returns from a CMSE entry function,
2255 // the function needs to do some extra work afte r the call, or before the
2256 // return, respectively, thus it cannot end with atail call
2257 if (isCmseNSCall
5.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
6
Assuming the condition is false
7
Taking false branch
2258 isTailCall = false;
2259
2260 if (isa<GlobalAddressSDNode>(Callee)) {
8
Assuming 'Callee' is not a 'GlobalAddressSDNode'
9
Taking false branch
2261 // If we're optimizing for minimum size and the function is called three or
2262 // more times in this block, we can improve codesize by calling indirectly
2263 // as BLXr has a 16-bit encoding.
2264 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2265 if (CLI.CB) {
2266 auto *BB = CLI.CB->getParent();
2267 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2268 count_if(GV->users(), [&BB](const User *U) {
2269 return isa<Instruction>(U) &&
2270 cast<Instruction>(U)->getParent() == BB;
2271 }) > 2;
2272 }
2273 }
2274 if (isTailCall) {
10
Assuming 'isTailCall' is false
11
Taking false branch
2275 // Check if it's really possible to do a tail call.
2276 isTailCall = IsEligibleForTailCallOptimization(
2277 Callee, CallConv, isVarArg, isStructRet,
2278 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2279 PreferIndirect);
2280 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2281 report_fatal_error("failed to perform tail call elimination on a call "
2282 "site marked musttail");
2283 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2284 // detected sibcalls.
2285 if (isTailCall)
2286 ++NumTailCalls;
2287 }
2288
2289 // Analyze operands of the call, assigning locations to each operand.
2290 SmallVector<CCValAssign, 16> ArgLocs;
2291 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2292 *DAG.getContext());
2293 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2294
2295 // Get a count of how many bytes are to be pushed on the stack.
2296 unsigned NumBytes = CCInfo.getNextStackOffset();
2297
2298 if (isTailCall) {
12
Assuming 'isTailCall' is false
13
Taking false branch
2299 // For tail calls, memory operands are available in our caller's stack.
2300 NumBytes = 0;
2301 } else {
2302 // Adjust the stack pointer for the new arguments...
2303 // These operations are automatically eliminated by the prolog/epilog pass
2304 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2305 }
2306
2307 SDValue StackPtr =
2308 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2309
2310 RegsToPassVector RegsToPass;
2311 SmallVector<SDValue, 8> MemOpChains;
2312
2313 // Walk the register/memloc assignments, inserting copies/loads. In the case
2314 // of tail call optimization, arguments are handled later.
2315 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
15
Loop condition is false. Execution continues on line 2457
2316 i != e;
14
Assuming 'i' is equal to 'e'
2317 ++i, ++realArgIdx) {
2318 CCValAssign &VA = ArgLocs[i];
2319 SDValue Arg = OutVals[realArgIdx];
2320 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2321 bool isByVal = Flags.isByVal();
2322
2323 // Promote the value if needed.
2324 switch (VA.getLocInfo()) {
2325 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2325)
;
2326 case CCValAssign::Full: break;
2327 case CCValAssign::SExt:
2328 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2329 break;
2330 case CCValAssign::ZExt:
2331 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2332 break;
2333 case CCValAssign::AExt:
2334 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2335 break;
2336 case CCValAssign::BCvt:
2337 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2338 break;
2339 }
2340
2341 // f16 arguments have their size extended to 4 bytes and passed as if they
2342 // had been copied to the LSBs of a 32-bit register.
2343 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2344 if (VA.needsCustom() &&
2345 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2346 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2347 } else {
2348 // f16 arguments could have been extended prior to argument lowering.
2349 // Mask them arguments if this is a CMSE nonsecure call.
2350 auto ArgVT = Outs[realArgIdx].ArgVT;
2351 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2352 auto LocBits = VA.getLocVT().getSizeInBits();
2353 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2354 SDValue Mask =
2355 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2356 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2357 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2358 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2359 }
2360 }
2361
2362 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2363 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2364 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2365 DAG.getConstant(0, dl, MVT::i32));
2366 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2367 DAG.getConstant(1, dl, MVT::i32));
2368
2369 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2370 StackPtr, MemOpChains, Flags);
2371
2372 VA = ArgLocs[++i]; // skip ahead to next loc
2373 if (VA.isRegLoc()) {
2374 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2375 StackPtr, MemOpChains, Flags);
2376 } else {
2377 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2377, __PRETTY_FUNCTION__))
;
2378
2379 MemOpChains.push_back(
2380 LowerMemOpCallTo(Chain, StackPtr, Op1, dl, DAG, VA, Flags));
2381 }
2382 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2383 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2384 StackPtr, MemOpChains, Flags);
2385 } else if (VA.isRegLoc()) {
2386 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2387 Outs[0].VT == MVT::i32) {
2388 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2389, __PRETTY_FUNCTION__))
2389 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2389, __PRETTY_FUNCTION__))
;
2390 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2391, __PRETTY_FUNCTION__))
2391 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2391, __PRETTY_FUNCTION__))
;
2392 isThisReturn = true;
2393 }
2394 const TargetOptions &Options = DAG.getTarget().Options;
2395 if (Options.EmitCallSiteInfo)
2396 CSInfo.emplace_back(VA.getLocReg(), i);
2397 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2398 } else if (isByVal) {
2399 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2399, __PRETTY_FUNCTION__))
;
2400 unsigned offset = 0;
2401
2402 // True if this byval aggregate will be split between registers
2403 // and memory.
2404 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2405 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2406
2407 if (CurByValIdx < ByValArgsCount) {
2408
2409 unsigned RegBegin, RegEnd;
2410 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2411
2412 EVT PtrVT =
2413 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2414 unsigned int i, j;
2415 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2416 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2417 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2418 SDValue Load =
2419 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2420 DAG.InferPtrAlign(AddArg));
2421 MemOpChains.push_back(Load.getValue(1));
2422 RegsToPass.push_back(std::make_pair(j, Load));
2423 }
2424
2425 // If parameter size outsides register area, "offset" value
2426 // helps us to calculate stack slot for remained part properly.
2427 offset = RegEnd - RegBegin;
2428
2429 CCInfo.nextInRegsParam();
2430 }
2431
2432 if (Flags.getByValSize() > 4*offset) {
2433 auto PtrVT = getPointerTy(DAG.getDataLayout());
2434 unsigned LocMemOffset = VA.getLocMemOffset();
2435 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2436 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2437 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2438 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2439 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2440 MVT::i32);
2441 SDValue AlignNode =
2442 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2443
2444 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2445 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2446 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2447 Ops));
2448 }
2449 } else if (!isTailCall) {
2450 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2450, __PRETTY_FUNCTION__))
;
2451
2452 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2453 dl, DAG, VA, Flags));
2454 }
2455 }
2456
2457 if (!MemOpChains.empty())
16
Taking true branch
2458 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2459
2460 // Build a sequence of copy-to-reg nodes chained together with token chain
2461 // and flag operands which copy the outgoing args into the appropriate regs.
2462 SDValue InFlag;
2463 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
17
Assuming 'i' is equal to 'e'
18
Loop condition is false. Execution continues on line 2472
2464 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2465 RegsToPass[i].second, InFlag);
2466 InFlag = Chain.getValue(1);
2467 }
2468
2469 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2470 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2471 // node so that legalize doesn't hack it.
2472 bool isDirect = false;
2473
2474 const TargetMachine &TM = getTargetMachine();
2475 const Module *Mod = MF.getFunction().getParent();
2476 const GlobalValue *GV = nullptr;
19
'GV' initialized to a null pointer value
2477 if (GlobalAddressSDNode *G
19.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
20
Taking false branch
2478 GV = G->getGlobal();
2479 bool isStub =
2480 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
21
Assuming the condition is false
2481
2482 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
22
Assuming the condition is true
2483 bool isLocalARMFunc = false;
2484 auto PtrVt = getPointerTy(DAG.getDataLayout());
2485
2486 if (Subtarget->genLongCalls()) {
23
Assuming the condition is false
24
Taking false branch
2487 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2488, __PRETTY_FUNCTION__))
2488 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2488, __PRETTY_FUNCTION__))
;
2489 // Handle a global address or an external symbol. If it's not one of
2490 // those, the target's already in a register, so we don't need to do
2491 // anything extra.
2492 if (isa<GlobalAddressSDNode>(Callee)) {
2493 // Create a constant pool entry for the callee address
2494 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2495 ARMConstantPoolValue *CPV =
2496 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2497
2498 // Get the address of the callee into a register
2499 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2500 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2501 Callee = DAG.getLoad(
2502 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2503 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2504 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2505 const char *Sym = S->getSymbol();
2506
2507 // Create a constant pool entry for the callee address
2508 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2509 ARMConstantPoolValue *CPV =
2510 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2511 ARMPCLabelIndex, 0);
2512 // Get the address of the callee into a register
2513 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2514 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2515 Callee = DAG.getLoad(
2516 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2517 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2518 }
2519 } else if (isa<GlobalAddressSDNode>(Callee)) {
25
Assuming 'Callee' is a 'GlobalAddressSDNode'
26
Taking true branch
2520 if (!PreferIndirect
26.1
'PreferIndirect' is false
) {
27
Taking true branch
2521 isDirect = true;
2522 bool isDef = GV->isStrongDefinitionForLinker();
28
Called C++ object pointer is null
2523
2524 // ARM call to a local ARM function is predicable.
2525 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2526 // tBX takes a register source operand.
2527 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2528 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2528, __PRETTY_FUNCTION__))
;
2529 Callee = DAG.getNode(
2530 ARMISD::WrapperPIC, dl, PtrVt,
2531 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2532 Callee = DAG.getLoad(
2533 PtrVt, dl, DAG.getEntryNode(), Callee,
2534 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2535 MachineMemOperand::MODereferenceable |
2536 MachineMemOperand::MOInvariant);
2537 } else if (Subtarget->isTargetCOFF()) {
2538 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2539, __PRETTY_FUNCTION__))
2539 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2539, __PRETTY_FUNCTION__))
;
2540 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2541 if (GV->hasDLLImportStorageClass())
2542 TargetFlags = ARMII::MO_DLLIMPORT;
2543 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2544 TargetFlags = ARMII::MO_COFFSTUB;
2545 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2546 TargetFlags);
2547 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2548 Callee =
2549 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2550 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2551 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2552 } else {
2553 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2554 }
2555 }
2556 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2557 isDirect = true;
2558 // tBX takes a register source operand.
2559 const char *Sym = S->getSymbol();
2560 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2561 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2562 ARMConstantPoolValue *CPV =
2563 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2564 ARMPCLabelIndex, 4);
2565 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2566 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2567 Callee = DAG.getLoad(
2568 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2569 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2570 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2571 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2572 } else {
2573 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2574 }
2575 }
2576
2577 if (isCmseNSCall) {
2578 assert(!isARMFunc && !isDirect &&((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2579, __PRETTY_FUNCTION__))
2579 "Cannot handle call to ARM function or direct call")((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2579, __PRETTY_FUNCTION__))
;
2580 if (NumBytes > 0) {
2581 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2582 "call to non-secure function would "
2583 "require passing arguments on stack",
2584 dl.getDebugLoc());
2585 DAG.getContext()->diagnose(Diag);
2586 }
2587 if (isStructRet) {
2588 DiagnosticInfoUnsupported Diag(
2589 DAG.getMachineFunction().getFunction(),
2590 "call to non-secure function would return value through pointer",
2591 dl.getDebugLoc());
2592 DAG.getContext()->diagnose(Diag);
2593 }
2594 }
2595
2596 // FIXME: handle tail calls differently.
2597 unsigned CallOpc;
2598 if (Subtarget->isThumb()) {
2599 if (isCmseNSCall)
2600 CallOpc = ARMISD::tSECALL;
2601 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2602 CallOpc = ARMISD::CALL_NOLINK;
2603 else
2604 CallOpc = ARMISD::CALL;
2605 } else {
2606 if (!isDirect && !Subtarget->hasV5TOps())
2607 CallOpc = ARMISD::CALL_NOLINK;
2608 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2609 // Emit regular call when code size is the priority
2610 !Subtarget->hasMinSize())
2611 // "mov lr, pc; b _foo" to avoid confusing the RSP
2612 CallOpc = ARMISD::CALL_NOLINK;
2613 else
2614 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2615 }
2616
2617 std::vector<SDValue> Ops;
2618 Ops.push_back(Chain);
2619 Ops.push_back(Callee);
2620
2621 // Add argument registers to the end of the list so that they are known live
2622 // into the call.
2623 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2624 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2625 RegsToPass[i].second.getValueType()));
2626
2627 // Add a register mask operand representing the call-preserved registers.
2628 if (!isTailCall) {
2629 const uint32_t *Mask;
2630 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2631 if (isThisReturn) {
2632 // For 'this' returns, use the R0-preserving mask if applicable
2633 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2634 if (!Mask) {
2635 // Set isThisReturn to false if the calling convention is not one that
2636 // allows 'returned' to be modeled in this way, so LowerCallResult does
2637 // not try to pass 'this' straight through
2638 isThisReturn = false;
2639 Mask = ARI->getCallPreservedMask(MF, CallConv);
2640 }
2641 } else
2642 Mask = ARI->getCallPreservedMask(MF, CallConv);
2643
2644 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2644, __PRETTY_FUNCTION__))
;
2645 Ops.push_back(DAG.getRegisterMask(Mask));
2646 }
2647
2648 if (InFlag.getNode())
2649 Ops.push_back(InFlag);
2650
2651 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2652 if (isTailCall) {
2653 MF.getFrameInfo().setHasTailCall();
2654 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2655 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2656 return Ret;
2657 }
2658
2659 // Returns a chain and a flag for retval copy to use.
2660 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2661 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2662 InFlag = Chain.getValue(1);
2663 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2664
2665 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2666 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2667 if (!Ins.empty())
2668 InFlag = Chain.getValue(1);
2669
2670 // Handle result values, copying them out of physregs into vregs that we
2671 // return.
2672 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2673 InVals, isThisReturn,
2674 isThisReturn ? OutVals[0] : SDValue());
2675}
2676
2677/// HandleByVal - Every parameter *after* a byval parameter is passed
2678/// on the stack. Remember the next parameter register to allocate,
2679/// and then confiscate the rest of the parameter registers to insure
2680/// this.
2681void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2682 Align Alignment) const {
2683 // Byval (as with any stack) slots are always at least 4 byte aligned.
2684 Alignment = std::max(Alignment, Align(4));
2685
2686 unsigned Reg = State->AllocateReg(GPRArgRegs);
2687 if (!Reg)
2688 return;
2689
2690 unsigned AlignInRegs = Alignment.value() / 4;
2691 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2692 for (unsigned i = 0; i < Waste; ++i)
2693 Reg = State->AllocateReg(GPRArgRegs);
2694
2695 if (!Reg)
2696 return;
2697
2698 unsigned Excess = 4 * (ARM::R4 - Reg);
2699
2700 // Special case when NSAA != SP and parameter size greater than size of
2701 // all remained GPR regs. In that case we can't split parameter, we must
2702 // send it to stack. We also must set NCRN to R4, so waste all
2703 // remained registers.
2704 const unsigned NSAAOffset = State->getNextStackOffset();
2705 if (NSAAOffset != 0 && Size > Excess) {
2706 while (State->AllocateReg(GPRArgRegs))
2707 ;
2708 return;
2709 }
2710
2711 // First register for byval parameter is the first register that wasn't
2712 // allocated before this method call, so it would be "reg".
2713 // If parameter is small enough to be saved in range [reg, r4), then
2714 // the end (first after last) register would be reg + param-size-in-regs,
2715 // else parameter would be splitted between registers and stack,
2716 // end register would be r4 in this case.
2717 unsigned ByValRegBegin = Reg;
2718 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2719 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2720 // Note, first register is allocated in the beginning of function already,
2721 // allocate remained amount of registers we need.
2722 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2723 State->AllocateReg(GPRArgRegs);
2724 // A byval parameter that is split between registers and memory needs its
2725 // size truncated here.
2726 // In the case where the entire structure fits in registers, we set the
2727 // size in memory to zero.
2728 Size = std::max<int>(Size - Excess, 0);
2729}
2730
2731/// MatchingStackOffset - Return true if the given stack call argument is
2732/// already available in the same position (relatively) of the caller's
2733/// incoming argument stack.
2734static
2735bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2736 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2737 const TargetInstrInfo *TII) {
2738 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2739 int FI = std::numeric_limits<int>::max();
2740 if (Arg.getOpcode() == ISD::CopyFromReg) {
2741 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2742 if (!Register::isVirtualRegister(VR))
2743 return false;
2744 MachineInstr *Def = MRI->getVRegDef(VR);
2745 if (!Def)
2746 return false;
2747 if (!Flags.isByVal()) {
2748 if (!TII->isLoadFromStackSlot(*Def, FI))
2749 return false;
2750 } else {
2751 return false;
2752 }
2753 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2754 if (Flags.isByVal())
2755 // ByVal argument is passed in as a pointer but it's now being
2756 // dereferenced. e.g.
2757 // define @foo(%struct.X* %A) {
2758 // tail call @bar(%struct.X* byval %A)
2759 // }
2760 return false;
2761 SDValue Ptr = Ld->getBasePtr();
2762 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2763 if (!FINode)
2764 return false;
2765 FI = FINode->getIndex();
2766 } else
2767 return false;
2768
2769 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2769, __PRETTY_FUNCTION__))
;
2770 if (!MFI.isFixedObjectIndex(FI))
2771 return false;
2772 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2773}
2774
2775/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2776/// for tail call optimization. Targets which want to do tail call
2777/// optimization should implement this function.
2778bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2779 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2780 bool isCalleeStructRet, bool isCallerStructRet,
2781 const SmallVectorImpl<ISD::OutputArg> &Outs,
2782 const SmallVectorImpl<SDValue> &OutVals,
2783 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2784 const bool isIndirect) const {
2785 MachineFunction &MF = DAG.getMachineFunction();
2786 const Function &CallerF = MF.getFunction();
2787 CallingConv::ID CallerCC = CallerF.getCallingConv();
2788
2789 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2789, __PRETTY_FUNCTION__))
;
2790
2791 // Indirect tail calls cannot be optimized for Thumb1 if the args
2792 // to the call take up r0-r3. The reason is that there are no legal registers
2793 // left to hold the pointer to the function to be called.
2794 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2795 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2796 return false;
2797
2798 // Look for obvious safe cases to perform tail call optimization that do not
2799 // require ABI changes. This is what gcc calls sibcall.
2800
2801 // Exception-handling functions need a special set of instructions to indicate
2802 // a return to the hardware. Tail-calling another function would probably
2803 // break this.
2804 if (CallerF.hasFnAttribute("interrupt"))
2805 return false;
2806
2807 // Also avoid sibcall optimization if either caller or callee uses struct
2808 // return semantics.
2809 if (isCalleeStructRet || isCallerStructRet)
2810 return false;
2811
2812 // Externally-defined functions with weak linkage should not be
2813 // tail-called on ARM when the OS does not support dynamic
2814 // pre-emption of symbols, as the AAELF spec requires normal calls
2815 // to undefined weak functions to be replaced with a NOP or jump to the
2816 // next instruction. The behaviour of branch instructions in this
2817 // situation (as used for tail calls) is implementation-defined, so we
2818 // cannot rely on the linker replacing the tail call with a return.
2819 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2820 const GlobalValue *GV = G->getGlobal();
2821 const Triple &TT = getTargetMachine().getTargetTriple();
2822 if (GV->hasExternalWeakLinkage() &&
2823 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2824 return false;
2825 }
2826
2827 // Check that the call results are passed in the same way.
2828 LLVMContext &C = *DAG.getContext();
2829 if (!CCState::resultsCompatible(
2830 getEffectiveCallingConv(CalleeCC, isVarArg),
2831 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2832 CCAssignFnForReturn(CalleeCC, isVarArg),
2833 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2834 return false;
2835 // The callee has to preserve all registers the caller needs to preserve.
2836 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2837 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2838 if (CalleeCC != CallerCC) {
2839 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2840 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2841 return false;
2842 }
2843
2844 // If Caller's vararg or byval argument has been split between registers and
2845 // stack, do not perform tail call, since part of the argument is in caller's
2846 // local frame.
2847 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2848 if (AFI_Caller->getArgRegsSaveSize())
2849 return false;
2850
2851 // If the callee takes no arguments then go on to check the results of the
2852 // call.
2853 if (!Outs.empty()) {
2854 // Check if stack adjustment is needed. For now, do not do this if any
2855 // argument is passed on the stack.
2856 SmallVector<CCValAssign, 16> ArgLocs;
2857 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2858 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2859 if (CCInfo.getNextStackOffset()) {
2860 // Check if the arguments are already laid out in the right way as
2861 // the caller's fixed stack objects.
2862 MachineFrameInfo &MFI = MF.getFrameInfo();
2863 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2864 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2865 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2866 i != e;
2867 ++i, ++realArgIdx) {
2868 CCValAssign &VA = ArgLocs[i];
2869 EVT RegVT = VA.getLocVT();
2870 SDValue Arg = OutVals[realArgIdx];
2871 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2872 if (VA.getLocInfo() == CCValAssign::Indirect)
2873 return false;
2874 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2875 // f64 and vector types are split into multiple registers or
2876 // register/stack-slot combinations. The types will not match
2877 // the registers; give up on memory f64 refs until we figure
2878 // out what to do about this.
2879 if (!VA.isRegLoc())
2880 return false;
2881 if (!ArgLocs[++i].isRegLoc())
2882 return false;
2883 if (RegVT == MVT::v2f64) {
2884 if (!ArgLocs[++i].isRegLoc())
2885 return false;
2886 if (!ArgLocs[++i].isRegLoc())
2887 return false;
2888 }
2889 } else if (!VA.isRegLoc()) {
2890 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2891 MFI, MRI, TII))
2892 return false;
2893 }
2894 }
2895 }
2896
2897 const MachineRegisterInfo &MRI = MF.getRegInfo();
2898 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2899 return false;
2900 }
2901
2902 return true;
2903}
2904
2905bool
2906ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2907 MachineFunction &MF, bool isVarArg,
2908 const SmallVectorImpl<ISD::OutputArg> &Outs,
2909 LLVMContext &Context) const {
2910 SmallVector<CCValAssign, 16> RVLocs;
2911 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2912 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2913}
2914
2915static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2916 const SDLoc &DL, SelectionDAG &DAG) {
2917 const MachineFunction &MF = DAG.getMachineFunction();
2918 const Function &F = MF.getFunction();
2919
2920 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2921
2922 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2923 // version of the "preferred return address". These offsets affect the return
2924 // instruction if this is a return from PL1 without hypervisor extensions.
2925 // IRQ/FIQ: +4 "subs pc, lr, #4"
2926 // SWI: 0 "subs pc, lr, #0"
2927 // ABORT: +4 "subs pc, lr, #4"
2928 // UNDEF: +4/+2 "subs pc, lr, #0"
2929 // UNDEF varies depending on where the exception came from ARM or Thumb
2930 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2931
2932 int64_t LROffset;
2933 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2934 IntKind == "ABORT")
2935 LROffset = 4;
2936 else if (IntKind == "SWI" || IntKind == "UNDEF")
2937 LROffset = 0;
2938 else
2939 report_fatal_error("Unsupported interrupt attribute. If present, value "
2940 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2941
2942 RetOps.insert(RetOps.begin() + 1,
2943 DAG.getConstant(LROffset, DL, MVT::i32, false));
2944
2945 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2946}
2947
2948SDValue
2949ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2950 bool isVarArg,
2951 const SmallVectorImpl<ISD::OutputArg> &Outs,
2952 const SmallVectorImpl<SDValue> &OutVals,
2953 const SDLoc &dl, SelectionDAG &DAG) const {
2954 // CCValAssign - represent the assignment of the return value to a location.
2955 SmallVector<CCValAssign, 16> RVLocs;
2956
2957 // CCState - Info about the registers and stack slots.
2958 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2959 *DAG.getContext());
2960
2961 // Analyze outgoing return values.
2962 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2963
2964 SDValue Flag;
2965 SmallVector<SDValue, 4> RetOps;
2966 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2967 bool isLittleEndian = Subtarget->isLittle();
2968
2969 MachineFunction &MF = DAG.getMachineFunction();
2970 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2971 AFI->setReturnRegsCount(RVLocs.size());
2972
2973 // Report error if cmse entry function returns structure through first ptr arg.
2974 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
2975 // Note: using an empty SDLoc(), as the first line of the function is a
2976 // better place to report than the last line.
2977 DiagnosticInfoUnsupported Diag(
2978 DAG.getMachineFunction().getFunction(),
2979 "secure entry function would return value through pointer",
2980 SDLoc().getDebugLoc());
2981 DAG.getContext()->diagnose(Diag);
2982 }
2983
2984 // Copy the result values into the output registers.
2985 for (unsigned i = 0, realRVLocIdx = 0;
2986 i != RVLocs.size();
2987 ++i, ++realRVLocIdx) {
2988 CCValAssign &VA = RVLocs[i];
2989 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2989, __PRETTY_FUNCTION__))
;
2990
2991 SDValue Arg = OutVals[realRVLocIdx];
2992 bool ReturnF16 = false;
2993
2994 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2995 // Half-precision return values can be returned like this:
2996 //
2997 // t11 f16 = fadd ...
2998 // t12: i16 = bitcast t11
2999 // t13: i32 = zero_extend t12
3000 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3001 //
3002 // to avoid code generation for bitcasts, we simply set Arg to the node
3003 // that produces the f16 value, t11 in this case.
3004 //
3005 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3006 SDValue ZE = Arg.getOperand(0);
3007 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3008 SDValue BC = ZE.getOperand(0);
3009 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3010 Arg = BC.getOperand(0);
3011 ReturnF16 = true;
3012 }
3013 }
3014 }
3015 }
3016
3017 switch (VA.getLocInfo()) {
3018 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3018)
;
3019 case CCValAssign::Full: break;
3020 case CCValAssign::BCvt:
3021 if (!ReturnF16)
3022 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3023 break;
3024 }
3025
3026 // Mask f16 arguments if this is a CMSE nonsecure entry.
3027 auto RetVT = Outs[realRVLocIdx].ArgVT;
3028 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3029 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3030 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3031 } else {
3032 auto LocBits = VA.getLocVT().getSizeInBits();
3033 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3034 SDValue Mask =
3035 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3036 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3037 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3038 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3039 }
3040 }
3041
3042 if (VA.needsCustom() &&
3043 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3044 if (VA.getLocVT() == MVT::v2f64) {
3045 // Extract the first half and return it in two registers.
3046 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3047 DAG.getConstant(0, dl, MVT::i32));
3048 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3049 DAG.getVTList(MVT::i32, MVT::i32), Half);
3050
3051 Chain =
3052 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3053 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3054 Flag = Chain.getValue(1);
3055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3056 VA = RVLocs[++i]; // skip ahead to next loc
3057 Chain =
3058 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3059 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3060 Flag = Chain.getValue(1);
3061 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3062 VA = RVLocs[++i]; // skip ahead to next loc
3063
3064 // Extract the 2nd half and fall through to handle it as an f64 value.
3065 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3066 DAG.getConstant(1, dl, MVT::i32));
3067 }
3068 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3069 // available.
3070 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3071 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3072 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3073 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3074 Flag = Chain.getValue(1);
3075 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3076 VA = RVLocs[++i]; // skip ahead to next loc
3077 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3078 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3079 } else
3080 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3081
3082 // Guarantee that all emitted copies are
3083 // stuck together, avoiding something bad.
3084 Flag = Chain.getValue(1);
3085 RetOps.push_back(DAG.getRegister(
3086 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3087 }
3088 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3089 const MCPhysReg *I =
3090 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3091 if (I) {
3092 for (; *I; ++I) {
3093 if (ARM::GPRRegClass.contains(*I))
3094 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3095 else if (ARM::DPRRegClass.contains(*I))
3096 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3097 else
3098 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3098)
;
3099 }
3100 }
3101
3102 // Update chain and glue.
3103 RetOps[0] = Chain;
3104 if (Flag.getNode())
3105 RetOps.push_back(Flag);
3106
3107 // CPUs which aren't M-class use a special sequence to return from
3108 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3109 // though we use "subs pc, lr, #N").
3110 //
3111 // M-class CPUs actually use a normal return sequence with a special
3112 // (hardware-provided) value in LR, so the normal code path works.
3113 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3114 !Subtarget->isMClass()) {
3115 if (Subtarget->isThumb1Only())
3116 report_fatal_error("interrupt attribute is not supported in Thumb1");
3117 return LowerInterruptReturn(RetOps, dl, DAG);
3118 }
3119
3120 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3121 ARMISD::RET_FLAG;
3122 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3123}
3124
3125bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3126 if (N->getNumValues() != 1)
3127 return false;
3128 if (!N->hasNUsesOfValue(1, 0))
3129 return false;
3130
3131 SDValue TCChain = Chain;
3132 SDNode *Copy = *N->use_begin();
3133 if (Copy->getOpcode() == ISD::CopyToReg) {
3134 // If the copy has a glue operand, we conservatively assume it isn't safe to
3135 // perform a tail call.
3136 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3137 return false;
3138 TCChain = Copy->getOperand(0);
3139 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3140 SDNode *VMov = Copy;
3141 // f64 returned in a pair of GPRs.
3142 SmallPtrSet<SDNode*, 2> Copies;
3143 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3144 UI != UE; ++UI) {
3145 if (UI->getOpcode() != ISD::CopyToReg)
3146 return false;
3147 Copies.insert(*UI);
3148 }
3149 if (Copies.size() > 2)
3150 return false;
3151
3152 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3153 UI != UE; ++UI) {
3154 SDValue UseChain = UI->getOperand(0);
3155 if (Copies.count(UseChain.getNode()))
3156 // Second CopyToReg
3157 Copy = *UI;
3158 else {
3159 // We are at the top of this chain.
3160 // If the copy has a glue operand, we conservatively assume it
3161 // isn't safe to perform a tail call.
3162 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3163 return false;
3164 // First CopyToReg
3165 TCChain = UseChain;
3166 }
3167 }
3168 } else if (Copy->getOpcode() == ISD::BITCAST) {
3169 // f32 returned in a single GPR.
3170 if (!Copy->hasOneUse())
3171 return false;
3172 Copy = *Copy->use_begin();
3173 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3174 return false;
3175 // If the copy has a glue operand, we conservatively assume it isn't safe to
3176 // perform a tail call.
3177 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3178 return false;
3179 TCChain = Copy->getOperand(0);
3180 } else {
3181 return false;
3182 }
3183
3184 bool HasRet = false;
3185 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3186 UI != UE; ++UI) {
3187 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3188 UI->getOpcode() != ARMISD::INTRET_FLAG)
3189 return false;
3190 HasRet = true;
3191 }
3192
3193 if (!HasRet)
3194 return false;
3195
3196 Chain = TCChain;
3197 return true;
3198}
3199
3200bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3201 if (!Subtarget->supportsTailCall())
3202 return false;
3203
3204 if (!CI->isTailCall())
3205 return false;
3206
3207 return true;
3208}
3209
3210// Trying to write a 64 bit value so need to split into two 32 bit values first,
3211// and pass the lower and high parts through.
3212static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3213 SDLoc DL(Op);
3214 SDValue WriteValue = Op->getOperand(2);
3215
3216 // This function is only supposed to be called for i64 type argument.
3217 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3218, __PRETTY_FUNCTION__))
3218 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3218, __PRETTY_FUNCTION__))
;
3219
3220 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3221 DAG.getConstant(0, DL, MVT::i32));
3222 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3223 DAG.getConstant(1, DL, MVT::i32));
3224 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3225 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3226}
3227
3228// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3229// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3230// one of the above mentioned nodes. It has to be wrapped because otherwise
3231// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3232// be used to form addressing mode. These wrapped nodes will be selected
3233// into MOVi.
3234SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3235 SelectionDAG &DAG) const {
3236 EVT PtrVT = Op.getValueType();
3237 // FIXME there is no actual debug info here
3238 SDLoc dl(Op);
3239 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3240 SDValue Res;
3241
3242 // When generating execute-only code Constant Pools must be promoted to the
3243 // global data section. It's a bit ugly that we can't share them across basic
3244 // blocks, but this way we guarantee that execute-only behaves correct with
3245 // position-independent addressing modes.
3246 if (Subtarget->genExecuteOnly()) {
3247 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3248 auto T = const_cast<Type*>(CP->getType());
3249 auto C = const_cast<Constant*>(CP->getConstVal());
3250 auto M = const_cast<Module*>(DAG.getMachineFunction().
3251 getFunction().getParent());
3252 auto GV = new GlobalVariable(
3253 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3254 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3255 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3256 Twine(AFI->createPICLabelUId())
3257 );
3258 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3259 dl, PtrVT);
3260 return LowerGlobalAddress(GA, DAG);
3261 }
3262
3263 if (CP->isMachineConstantPoolEntry())
3264 Res =
3265 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3266 else
3267 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3268 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3269}
3270
3271unsigned ARMTargetLowering::getJumpTableEncoding() const {
3272 return MachineJumpTableInfo::EK_Inline;
3273}
3274
3275SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3276 SelectionDAG &DAG) const {
3277 MachineFunction &MF = DAG.getMachineFunction();
3278 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3279 unsigned ARMPCLabelIndex = 0;
3280 SDLoc DL(Op);
3281 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3282 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3283 SDValue CPAddr;
3284 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3285 if (!IsPositionIndependent) {
3286 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3287 } else {
3288 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3289 ARMPCLabelIndex = AFI->createPICLabelUId();
3290 ARMConstantPoolValue *CPV =
3291 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3292 ARMCP::CPBlockAddress, PCAdj);
3293 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3294 }
3295 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3296 SDValue Result = DAG.getLoad(
3297 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3298 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3299 if (!IsPositionIndependent)
3300 return Result;
3301 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3302 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3303}
3304
3305/// Convert a TLS address reference into the correct sequence of loads
3306/// and calls to compute the variable's address for Darwin, and return an
3307/// SDValue containing the final node.
3308
3309/// Darwin only has one TLS scheme which must be capable of dealing with the
3310/// fully general situation, in the worst case. This means:
3311/// + "extern __thread" declaration.
3312/// + Defined in a possibly unknown dynamic library.
3313///
3314/// The general system is that each __thread variable has a [3 x i32] descriptor
3315/// which contains information used by the runtime to calculate the address. The
3316/// only part of this the compiler needs to know about is the first word, which
3317/// contains a function pointer that must be called with the address of the
3318/// entire descriptor in "r0".
3319///
3320/// Since this descriptor may be in a different unit, in general access must
3321/// proceed along the usual ARM rules. A common sequence to produce is:
3322///
3323/// movw rT1, :lower16:_var$non_lazy_ptr
3324/// movt rT1, :upper16:_var$non_lazy_ptr
3325/// ldr r0, [rT1]
3326/// ldr rT2, [r0]
3327/// blx rT2
3328/// [...address now in r0...]
3329SDValue
3330ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3331 SelectionDAG &DAG) const {
3332 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3333, __PRETTY_FUNCTION__))
3333 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3333, __PRETTY_FUNCTION__))
;
3334 SDLoc DL(Op);
3335
3336 // First step is to get the address of the actua global symbol. This is where
3337 // the TLS descriptor lives.
3338 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3339
3340 // The first entry in the descriptor is a function pointer that we must call
3341 // to obtain the address of the variable.
3342 SDValue Chain = DAG.getEntryNode();
3343 SDValue FuncTLVGet = DAG.getLoad(
3344 MVT::i32, DL, Chain, DescAddr,
3345 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3346 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3347 MachineMemOperand::MOInvariant);
3348 Chain = FuncTLVGet.getValue(1);
3349
3350 MachineFunction &F = DAG.getMachineFunction();
3351 MachineFrameInfo &MFI = F.getFrameInfo();
3352 MFI.setAdjustsStack(true);
3353
3354 // TLS calls preserve all registers except those that absolutely must be
3355 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3356 // silly).
3357 auto TRI =
3358 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3359 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3360 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3361
3362 // Finally, we can make the call. This is just a degenerate version of a
3363 // normal AArch64 call node: r0 takes the address of the descriptor, and
3364 // returns the address of the variable in this thread.
3365 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3366 Chain =
3367 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3368 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3369 DAG.getRegisterMask(Mask), Chain.getValue(1));
3370 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3371}
3372
3373SDValue
3374ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3375 SelectionDAG &DAG) const {
3376 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3376, __PRETTY_FUNCTION__))
;
3377
3378 SDValue Chain = DAG.getEntryNode();
3379 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3380 SDLoc DL(Op);
3381
3382 // Load the current TEB (thread environment block)
3383 SDValue Ops[] = {Chain,
3384 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3385 DAG.getTargetConstant(15, DL, MVT::i32),
3386 DAG.getTargetConstant(0, DL, MVT::i32),
3387 DAG.getTargetConstant(13, DL, MVT::i32),
3388 DAG.getTargetConstant(0, DL, MVT::i32),
3389 DAG.getTargetConstant(2, DL, MVT::i32)};
3390 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3391 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3392
3393 SDValue TEB = CurrentTEB.getValue(0);
3394 Chain = CurrentTEB.getValue(1);
3395
3396 // Load the ThreadLocalStoragePointer from the TEB
3397 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3398 SDValue TLSArray =
3399 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3400 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3401
3402 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3403 // offset into the TLSArray.
3404
3405 // Load the TLS index from the C runtime
3406 SDValue TLSIndex =
3407 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3408 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3409 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3410
3411 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3412 DAG.getConstant(2, DL, MVT::i32));
3413 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3414 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3415 MachinePointerInfo());
3416
3417 // Get the offset of the start of the .tls section (section base)
3418 const auto *GA = cast<GlobalAddressSDNode>(Op);
3419 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3420 SDValue Offset = DAG.getLoad(
3421 PtrVT, DL, Chain,
3422 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3423 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3424 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3425
3426 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3427}
3428
3429// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3430SDValue
3431ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3432 SelectionDAG &DAG) const {
3433 SDLoc dl(GA);
3434 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3435 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3436 MachineFunction &MF = DAG.getMachineFunction();
3437 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3438 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3439 ARMConstantPoolValue *CPV =
3440 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3441 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3442 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3443 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3444 Argument = DAG.getLoad(
3445 PtrVT, dl, DAG.getEntryNode(), Argument,
3446 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3447 SDValue Chain = Argument.getValue(1);
3448
3449 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3450 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3451
3452 // call __tls_get_addr.
3453 ArgListTy Args;
3454 ArgListEntry Entry;
3455 Entry.Node = Argument;
3456 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3457 Args.push_back(Entry);
3458
3459 // FIXME: is there useful debug info available here?
3460 TargetLowering::CallLoweringInfo CLI(DAG);
3461 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3462 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3463 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3464
3465 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3466 return CallResult.first;
3467}
3468
3469// Lower ISD::GlobalTLSAddress using the "initial exec" or
3470// "local exec" model.
3471SDValue
3472ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3473 SelectionDAG &DAG,
3474 TLSModel::Model model) const {
3475 const GlobalValue *GV = GA->getGlobal();
3476 SDLoc dl(GA);
3477 SDValue Offset;
3478 SDValue Chain = DAG.getEntryNode();
3479 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3480 // Get the Thread Pointer
3481 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3482
3483 if (model == TLSModel::InitialExec) {
3484 MachineFunction &MF = DAG.getMachineFunction();
3485 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3487 // Initial exec model.
3488 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3489 ARMConstantPoolValue *CPV =
3490 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3491 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3492 true);
3493 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3494 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3495 Offset = DAG.getLoad(
3496 PtrVT, dl, Chain, Offset,
3497 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3498 Chain = Offset.getValue(1);
3499
3500 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3501 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3502
3503 Offset = DAG.getLoad(
3504 PtrVT, dl, Chain, Offset,
3505 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3506 } else {
3507 // local exec model
3508 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3508, __PRETTY_FUNCTION__))
;
3509 ARMConstantPoolValue *CPV =
3510 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3511 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3512 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3513 Offset = DAG.getLoad(
3514 PtrVT, dl, Chain, Offset,
3515 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3516 }
3517
3518 // The address of the thread local variable is the add of the thread
3519 // pointer with the offset of the variable.
3520 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3521}
3522
3523SDValue
3524ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3525 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3526 if (DAG.getTarget().useEmulatedTLS())
3527 return LowerToTLSEmulatedModel(GA, DAG);
3528
3529 if (Subtarget->isTargetDarwin())
3530 return LowerGlobalTLSAddressDarwin(Op, DAG);
3531
3532 if (Subtarget->isTargetWindows())
3533 return LowerGlobalTLSAddressWindows(Op, DAG);
3534
3535 // TODO: implement the "local dynamic" model
3536 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3536, __PRETTY_FUNCTION__))
;
3537 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3538
3539 switch (model) {
3540 case TLSModel::GeneralDynamic:
3541 case TLSModel::LocalDynamic:
3542 return LowerToTLSGeneralDynamicModel(GA, DAG);
3543 case TLSModel::InitialExec:
3544 case TLSModel::LocalExec:
3545 return LowerToTLSExecModels(GA, DAG, model);
3546 }
3547 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3547)
;
3548}
3549
3550/// Return true if all users of V are within function F, looking through
3551/// ConstantExprs.
3552static bool allUsersAreInFunction(const Value *V, const Function *F) {
3553 SmallVector<const User*,4> Worklist;
3554 for (auto *U : V->users())
3555 Worklist.push_back(U);
3556 while (!Worklist.empty()) {
3557 auto *U = Worklist.pop_back_val();
3558 if (isa<ConstantExpr>(U)) {
3559 append_range(Worklist, U->users());
3560 continue;
3561 }
3562
3563 auto *I = dyn_cast<Instruction>(U);
3564 if (!I || I->getParent()->getParent() != F)
3565 return false;
3566 }
3567 return true;
3568}
3569
3570static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3571 const GlobalValue *GV, SelectionDAG &DAG,
3572 EVT PtrVT, const SDLoc &dl) {
3573 // If we're creating a pool entry for a constant global with unnamed address,
3574 // and the global is small enough, we can emit it inline into the constant pool
3575 // to save ourselves an indirection.
3576 //
3577 // This is a win if the constant is only used in one function (so it doesn't
3578 // need to be duplicated) or duplicating the constant wouldn't increase code
3579 // size (implying the constant is no larger than 4 bytes).
3580 const Function &F = DAG.getMachineFunction().getFunction();
3581
3582 // We rely on this decision to inline being idemopotent and unrelated to the
3583 // use-site. We know that if we inline a variable at one use site, we'll
3584 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3585 // doesn't know about this optimization, so bail out if it's enabled else
3586 // we could decide to inline here (and thus never emit the GV) but require
3587 // the GV from fast-isel generated code.
3588 if (!EnableConstpoolPromotion ||
3589 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3590 return SDValue();
3591
3592 auto *GVar = dyn_cast<GlobalVariable>(GV);
3593 if (!GVar || !GVar->hasInitializer() ||
3594 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3595 !GVar->hasLocalLinkage())
3596 return SDValue();
3597
3598 // If we inline a value that contains relocations, we move the relocations
3599 // from .data to .text. This is not allowed in position-independent code.
3600 auto *Init = GVar->getInitializer();
3601 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3602 Init->needsRelocation())
3603 return SDValue();
3604
3605 // The constant islands pass can only really deal with alignment requests
3606 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3607 // any type wanting greater alignment requirements than 4 bytes. We also
3608 // can only promote constants that are multiples of 4 bytes in size or
3609 // are paddable to a multiple of 4. Currently we only try and pad constants
3610 // that are strings for simplicity.
3611 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3612 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3613 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3614 unsigned RequiredPadding = 4 - (Size % 4);
3615 bool PaddingPossible =
3616 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3617 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3618 Size == 0)
3619 return SDValue();
3620
3621 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3624
3625 // We can't bloat the constant pool too much, else the ConstantIslands pass
3626 // may fail to converge. If we haven't promoted this global yet (it may have
3627 // multiple uses), and promoting it would increase the constant pool size (Sz
3628 // > 4), ensure we have space to do so up to MaxTotal.
3629 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3630 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3631 ConstpoolPromotionMaxTotal)
3632 return SDValue();
3633
3634 // This is only valid if all users are in a single function; we can't clone
3635 // the constant in general. The LLVM IR unnamed_addr allows merging
3636 // constants, but not cloning them.
3637 //
3638 // We could potentially allow cloning if we could prove all uses of the
3639 // constant in the current function don't care about the address, like
3640 // printf format strings. But that isn't implemented for now.
3641 if (!allUsersAreInFunction(GVar, &F))
3642 return SDValue();
3643
3644 // We're going to inline this global. Pad it out if needed.
3645 if (RequiredPadding != 4) {
3646 StringRef S = CDAInit->getAsString();
3647
3648 SmallVector<uint8_t,16> V(S.size());
3649 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3650 while (RequiredPadding--)
3651 V.push_back(0);
3652 Init = ConstantDataArray::get(*DAG.getContext(), V);
3653 }
3654
3655 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3656 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3657 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3658 AFI->markGlobalAsPromotedToConstantPool(GVar);
3659 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3660 PaddedSize - 4);
3661 }
3662 ++NumConstpoolPromoted;
3663 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3664}
3665
3666bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3667 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3668 if (!(GV = GA->getBaseObject()))
3669 return false;
3670 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3671 return V->isConstant();
3672 return isa<Function>(GV);
3673}
3674
3675SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3676 SelectionDAG &DAG) const {
3677 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3678 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3678)
;
3679 case Triple::COFF:
3680 return LowerGlobalAddressWindows(Op, DAG);
3681 case Triple::ELF:
3682 return LowerGlobalAddressELF(Op, DAG);
3683 case Triple::MachO:
3684 return LowerGlobalAddressDarwin(Op, DAG);
3685 }
3686}
3687
3688SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3689 SelectionDAG &DAG) const {
3690 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3691 SDLoc dl(Op);
3692 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3693 const TargetMachine &TM = getTargetMachine();
3694 bool IsRO = isReadOnly(GV);
3695
3696 // promoteToConstantPool only if not generating XO text section
3697 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3698 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3699 return V;
3700
3701 if (isPositionIndependent()) {
3702 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3703 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3704 UseGOT_PREL ? ARMII::MO_GOT : 0);
3705 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3706 if (UseGOT_PREL)
3707 Result =
3708 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3709 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3710 return Result;
3711 } else if (Subtarget->isROPI() && IsRO) {
3712 // PC-relative.
3713 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3714 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3715 return Result;
3716 } else if (Subtarget->isRWPI() && !IsRO) {
3717 // SB-relative.
3718 SDValue RelAddr;
3719 if (Subtarget->useMovt()) {
3720 ++NumMovwMovt;
3721 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3722 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3723 } else { // use literal pool for address constant
3724 ARMConstantPoolValue *CPV =
3725 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3726 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3727 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3728 RelAddr = DAG.getLoad(
3729 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3730 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3731 }
3732 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3733 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3734 return Result;
3735 }
3736
3737 // If we have T2 ops, we can materialize the address directly via movt/movw
3738 // pair. This is always cheaper.
3739 if (Subtarget->useMovt()) {
3740 ++NumMovwMovt;
3741 // FIXME: Once remat is capable of dealing with instructions with register
3742 // operands, expand this into two nodes.
3743 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3744 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3745 } else {
3746 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3747 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3748 return DAG.getLoad(
3749 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3750 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3751 }
3752}
3753
3754SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3755 SelectionDAG &DAG) const {
3756 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3757, __PRETTY_FUNCTION__))
3757 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3757, __PRETTY_FUNCTION__))
;
3758 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3759 SDLoc dl(Op);
3760 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3761
3762 if (Subtarget->useMovt())
3763 ++NumMovwMovt;
3764
3765 // FIXME: Once remat is capable of dealing with instructions with register
3766 // operands, expand this into multiple nodes
3767 unsigned Wrapper =
3768 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3769
3770 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3771 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3772
3773 if (Subtarget->isGVIndirectSymbol(GV))
3774 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3775 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3776 return Result;
3777}
3778
3779SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3780 SelectionDAG &DAG) const {
3781 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3781, __PRETTY_FUNCTION__))
;
3782 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3783, __PRETTY_FUNCTION__))
3783 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3783, __PRETTY_FUNCTION__))
;
3784 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __PRETTY_FUNCTION__))
3785 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __PRETTY_FUNCTION__))
;
3786
3787 const TargetMachine &TM = getTargetMachine();
3788 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3789 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3790 if (GV->hasDLLImportStorageClass())
3791 TargetFlags = ARMII::MO_DLLIMPORT;
3792 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3793 TargetFlags = ARMII::MO_COFFSTUB;
3794 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3795 SDValue Result;
3796 SDLoc DL(Op);
3797
3798 ++NumMovwMovt;
3799
3800 // FIXME: Once remat is capable of dealing with instructions with register
3801 // operands, expand this into two nodes.
3802 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3803 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3804 TargetFlags));
3805 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3806 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3807 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3808 return Result;
3809}
3810
3811SDValue
3812ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3813 SDLoc dl(Op);
3814 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3815 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3816 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3817 Op.getOperand(1), Val);
3818}
3819
3820SDValue
3821ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3822 SDLoc dl(Op);
3823 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3824 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3825}
3826
3827SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3828 SelectionDAG &DAG) const {
3829 SDLoc dl(Op);
3830 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3831 Op.getOperand(0));
3832}
3833
3834SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3835 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3836 unsigned IntNo =
3837 cast<ConstantSDNode>(
3838 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3839 ->getZExtValue();
3840 switch (IntNo) {
3841 default:
3842 return SDValue(); // Don't custom lower most intrinsics.
3843 case Intrinsic::arm_gnu_eabi_mcount: {
3844 MachineFunction &MF = DAG.getMachineFunction();
3845 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3846 SDLoc dl(Op);
3847 SDValue Chain = Op.getOperand(0);
3848 // call "\01__gnu_mcount_nc"
3849 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3850 const uint32_t *Mask =
3851 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3852 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3852, __PRETTY_FUNCTION__))
;
3853 // Mark LR an implicit live-in.
3854 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3855 SDValue ReturnAddress =
3856 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3857 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3858 SDValue Callee =
3859 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3860 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3861 if (Subtarget->isThumb())
3862 return SDValue(
3863 DAG.getMachineNode(
3864 ARM::tBL_PUSHLR, dl, ResultTys,
3865 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3866 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3867 0);
3868 return SDValue(
3869 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3870 {ReturnAddress, Callee, RegisterMask, Chain}),
3871 0);
3872 }
3873 }
3874}
3875
3876SDValue
3877ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3878 const ARMSubtarget *Subtarget) const {
3879 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3880 SDLoc dl(Op);
3881 switch (IntNo) {
3882 default: return SDValue(); // Don't custom lower most intrinsics.
3883 case Intrinsic::thread_pointer: {
3884 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3885 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3886 }
3887 case Intrinsic::arm_cls: {
3888 const SDValue &Operand = Op.getOperand(1);
3889 const EVT VTy = Op.getValueType();
3890 SDValue SRA =
3891 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3892 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3893 SDValue SHL =
3894 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3895 SDValue OR =
3896 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3897 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3898 return Result;
3899 }
3900 case Intrinsic::arm_cls64: {
3901 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3902 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3903 const SDValue &Operand = Op.getOperand(1);
3904 const EVT VTy = Op.getValueType();
3905
3906 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3907 DAG.getConstant(1, dl, VTy));
3908 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3909 DAG.getConstant(0, dl, VTy));
3910 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3911 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3912 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3913 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3914 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3915 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3916 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3917 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3918 SDValue CheckLo =
3919 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3920 SDValue HiIsZero =
3921 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3922 SDValue AdjustedLo =
3923 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3924 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3925 SDValue Result =
3926 DAG.getSelect(dl, VTy, CheckLo,
3927 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3928 return Result;
3929 }
3930 case Intrinsic::eh_sjlj_lsda: {
3931 MachineFunction &MF = DAG.getMachineFunction();
3932 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3933 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3934 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3935 SDValue CPAddr;
3936 bool IsPositionIndependent = isPositionIndependent();
3937 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3938 ARMConstantPoolValue *CPV =
3939 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3940 ARMCP::CPLSDA, PCAdj);
3941 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3942 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3943 SDValue Result = DAG.getLoad(
3944 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3945 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3946
3947 if (IsPositionIndependent) {
3948 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3949 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3950 }
3951 return Result;
3952 }
3953 case Intrinsic::arm_neon_vabs:
3954 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3955 Op.getOperand(1));
3956 case Intrinsic::arm_neon_vmulls:
3957 case Intrinsic::arm_neon_vmullu: {
3958 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3959 ? ARMISD::VMULLs : ARMISD::VMULLu;
3960 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3961 Op.getOperand(1), Op.getOperand(2));
3962 }
3963 case Intrinsic::arm_neon_vminnm:
3964 case Intrinsic::arm_neon_vmaxnm: {
3965 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3966 ? ISD::FMINNUM : ISD::FMAXNUM;
3967 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3968 Op.getOperand(1), Op.getOperand(2));
3969 }
3970 case Intrinsic::arm_neon_vminu:
3971 case Intrinsic::arm_neon_vmaxu: {
3972 if (Op.getValueType().isFloatingPoint())
3973 return SDValue();
3974 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3975 ? ISD::UMIN : ISD::UMAX;
3976 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3977 Op.getOperand(1), Op.getOperand(2));
3978 }
3979 case Intrinsic::arm_neon_vmins:
3980 case Intrinsic::arm_neon_vmaxs: {
3981 // v{min,max}s is overloaded between signed integers and floats.
3982 if (!Op.getValueType().isFloatingPoint()) {
3983 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3984 ? ISD::SMIN : ISD::SMAX;
3985 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3986 Op.getOperand(1), Op.getOperand(2));
3987 }
3988 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3989 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3990 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3991 Op.getOperand(1), Op.getOperand(2));
3992 }
3993 case Intrinsic::arm_neon_vtbl1:
3994 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3995 Op.getOperand(1), Op.getOperand(2));
3996 case Intrinsic::arm_neon_vtbl2:
3997 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3998 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3999 case Intrinsic::arm_mve_pred_i2v:
4000 case Intrinsic::arm_mve_pred_v2i:
4001 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4002 Op.getOperand(1));
4003 case Intrinsic::arm_mve_vreinterpretq:
4004 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4005 Op.getOperand(1));
4006 case Intrinsic::arm_mve_lsll:
4007 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4008 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4009 case Intrinsic::arm_mve_asrl:
4010 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4011 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4012 }
4013}
4014
4015static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4016 const ARMSubtarget *Subtarget) {
4017 SDLoc dl(Op);
4018 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4019 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4020 if (SSID == SyncScope::SingleThread)
4021 return Op;
4022
4023 if (!Subtarget->hasDataBarrier()) {
4024 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4025 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4026 // here.
4027 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4028, __PRETTY_FUNCTION__))
4028 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4028, __PRETTY_FUNCTION__))
;
4029 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4030 DAG.getConstant(0, dl, MVT::i32));
4031 }
4032
4033 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4034 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4035 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4036 if (Subtarget->isMClass()) {
4037 // Only a full system barrier exists in the M-class architectures.
4038 Domain = ARM_MB::SY;
4039 } else if (Subtarget->preferISHSTBarriers() &&
4040 Ord == AtomicOrdering::Release) {
4041 // Swift happens to implement ISHST barriers in a way that's compatible with
4042 // Release semantics but weaker than ISH so we'd be fools not to use
4043 // it. Beware: other processors probably don't!
4044 Domain = ARM_MB::ISHST;
4045 }
4046
4047 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4048 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4049 DAG.getConstant(Domain, dl, MVT::i32));
4050}
4051
4052static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4053 const ARMSubtarget *Subtarget) {
4054 // ARM pre v5TE and Thumb1 does not have preload instructions.
4055 if (!(Subtarget->isThumb2() ||
4056 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4057 // Just preserve the chain.
4058 return Op.getOperand(0);
4059
4060 SDLoc dl(Op);
4061 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4062 if (!isRead &&
4063 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4064 // ARMv7 with MP extension has PLDW.
4065 return Op.getOperand(0);
4066
4067 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4068 if (Subtarget->isThumb()) {
4069 // Invert the bits.
4070 isRead = ~isRead & 1;
4071 isData = ~isData & 1;
4072 }
4073
4074 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4075 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4076 DAG.getConstant(isData, dl, MVT::i32));
4077}
4078
4079static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4080 MachineFunction &MF = DAG.getMachineFunction();
4081 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4082
4083 // vastart just stores the address of the VarArgsFrameIndex slot into the
4084 // memory location argument.
4085 SDLoc dl(Op);
4086 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4087 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4088 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4089 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4090 MachinePointerInfo(SV));
4091}
4092
4093SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4094 CCValAssign &NextVA,
4095 SDValue &Root,
4096 SelectionDAG &DAG,
4097 const SDLoc &dl) const {
4098 MachineFunction &MF = DAG.getMachineFunction();
4099 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4100
4101 const TargetRegisterClass *RC;
4102 if (AFI->isThumb1OnlyFunction())
4103 RC = &ARM::tGPRRegClass;
4104 else
4105 RC = &ARM::GPRRegClass;
4106
4107 // Transform the arguments stored in physical registers into virtual ones.
4108 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4109 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4110
4111 SDValue ArgValue2;
4112 if (NextVA.isMemLoc()) {
4113 MachineFrameInfo &MFI = MF.getFrameInfo();
4114 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4115
4116 // Create load node to retrieve arguments from the stack.
4117 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4118 ArgValue2 = DAG.getLoad(
4119 MVT::i32, dl, Root, FIN,
4120 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4121 } else {
4122 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4123 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4124 }
4125 if (!Subtarget->isLittle())
4126 std::swap (ArgValue, ArgValue2);
4127 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4128}
4129
4130// The remaining GPRs hold either the beginning of variable-argument
4131// data, or the beginning of an aggregate passed by value (usually
4132// byval). Either way, we allocate stack slots adjacent to the data
4133// provided by our caller, and store the unallocated registers there.
4134// If this is a variadic function, the va_list pointer will begin with
4135// these values; otherwise, this reassembles a (byval) structure that
4136// was split between registers and memory.
4137// Return: The frame index registers were stored into.
4138int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4139 const SDLoc &dl, SDValue &Chain,
4140 const Value *OrigArg,
4141 unsigned InRegsParamRecordIdx,
4142 int ArgOffset, unsigned ArgSize) const {
4143 // Currently, two use-cases possible:
4144 // Case #1. Non-var-args function, and we meet first byval parameter.
4145 // Setup first unallocated register as first byval register;
4146 // eat all remained registers
4147 // (these two actions are performed by HandleByVal method).
4148 // Then, here, we initialize stack frame with
4149 // "store-reg" instructions.
4150 // Case #2. Var-args function, that doesn't contain byval parameters.
4151 // The same: eat all remained unallocated registers,
4152 // initialize stack frame.
4153
4154 MachineFunction &MF = DAG.getMachineFunction();
4155 MachineFrameInfo &MFI = MF.getFrameInfo();
4156 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4157 unsigned RBegin, REnd;
4158 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4159 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4160 } else {
4161 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4162 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4163 REnd = ARM::R4;
4164 }
4165
4166 if (REnd != RBegin)
4167 ArgOffset = -4 * (ARM::R4 - RBegin);
4168
4169 auto PtrVT = getPointerTy(DAG.getDataLayout());
4170 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4171 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4172
4173 SmallVector<SDValue, 4> MemOps;
4174 const TargetRegisterClass *RC =
4175 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4176
4177 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4178 unsigned VReg = MF.addLiveIn(Reg, RC);
4179 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4180 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4181 MachinePointerInfo(OrigArg, 4 * i));
4182 MemOps.push_back(Store);
4183 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4184 }
4185
4186 if (!MemOps.empty())
4187 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4188 return FrameIndex;
4189}
4190
4191// Setup stack frame, the va_list pointer will start from.
4192void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4193 const SDLoc &dl, SDValue &Chain,
4194 unsigned ArgOffset,
4195 unsigned TotalArgRegsSaveSize,
4196 bool ForceMutable) const {
4197 MachineFunction &MF = DAG.getMachineFunction();
4198 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4199
4200 // Try to store any remaining integer argument regs
4201 // to their spots on the stack so that they may be loaded by dereferencing
4202 // the result of va_next.
4203 // If there is no regs to be stored, just point address after last
4204 // argument passed via stack.
4205 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4206 CCInfo.getInRegsParamsCount(),
4207 CCInfo.getNextStackOffset(),
4208 std::max(4U, TotalArgRegsSaveSize));
4209 AFI->setVarArgsFrameIndex(FrameIndex);
4210}
4211
4212bool ARMTargetLowering::splitValueIntoRegisterParts(
4213 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4214 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4215 bool IsABIRegCopy = CC.hasValue();
4216 EVT ValueVT = Val.getValueType();
4217 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4218 PartVT == MVT::f32) {
4219 unsigned ValueBits = ValueVT.getSizeInBits();
4220 unsigned PartBits = PartVT.getSizeInBits();
4221 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4222 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4223 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4224 Parts[0] = Val;
4225 return true;
4226 }
4227 return false;
4228}
4229
4230SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4231 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4232 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4233 bool IsABIRegCopy = CC.hasValue();
4234 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4235 PartVT == MVT::f32) {
4236 unsigned ValueBits = ValueVT.getSizeInBits();
4237 unsigned PartBits = PartVT.getSizeInBits();
4238 SDValue Val = Parts[0];
4239
4240 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4241 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4242 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4243 return Val;
4244 }
4245 return SDValue();
4246}
4247
4248SDValue ARMTargetLowering::LowerFormalArguments(
4249 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4250 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4251 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4252 MachineFunction &MF = DAG.getMachineFunction();
4253 MachineFrameInfo &MFI = MF.getFrameInfo();
4254
4255 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4256
4257 // Assign locations to all of the incoming arguments.
4258 SmallVector<CCValAssign, 16> ArgLocs;
4259 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4260 *DAG.getContext());
4261 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4262
4263 SmallVector<SDValue, 16> ArgValues;
4264 SDValue ArgValue;
4265 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4266 unsigned CurArgIdx = 0;
4267
4268 // Initially ArgRegsSaveSize is zero.
4269 // Then we increase this value each time we meet byval parameter.
4270 // We also increase this value in case of varargs function.
4271 AFI->setArgRegsSaveSize(0);
4272
4273 // Calculate the amount of stack space that we need to allocate to store
4274 // byval and variadic arguments that are passed in registers.
4275 // We need to know this before we allocate the first byval or variadic
4276 // argument, as they will be allocated a stack slot below the CFA (Canonical
4277 // Frame Address, the stack pointer at entry to the function).
4278 unsigned ArgRegBegin = ARM::R4;
4279 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4280 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4281 break;
4282
4283 CCValAssign &VA = ArgLocs[i];
4284 unsigned Index = VA.getValNo();
4285 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4286 if (!Flags.isByVal())
4287 continue;
4288
4289 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4289, __PRETTY_FUNCTION__))
;
4290 unsigned RBegin, REnd;
4291 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4292 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4293
4294 CCInfo.nextInRegsParam();
4295 }
4296 CCInfo.rewindByValRegsInfo();
4297
4298 int lastInsIndex = -1;
4299 if (isVarArg && MFI.hasVAStart()) {
4300 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4301 if (RegIdx != array_lengthof(GPRArgRegs))
4302 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4303 }
4304
4305 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4306 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4307 auto PtrVT = getPointerTy(DAG.getDataLayout());
4308
4309 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4310 CCValAssign &VA = ArgLocs[i];
4311 if (Ins[VA.getValNo()].isOrigArg()) {
4312 std::advance(CurOrigArg,
4313 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4314 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4315 }
4316 // Arguments stored in registers.
4317 if (VA.isRegLoc()) {
4318 EVT RegVT = VA.getLocVT();
4319
4320 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4321 // f64 and vector types are split up into multiple registers or
4322 // combinations of registers and stack slots.
4323 SDValue ArgValue1 =
4324 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4325 VA = ArgLocs[++i]; // skip ahead to next loc
4326 SDValue ArgValue2;
4327 if (VA.isMemLoc()) {
4328 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4329 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4330 ArgValue2 = DAG.getLoad(
4331 MVT::f64, dl, Chain, FIN,
4332 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4333 } else {
4334 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4335 }
4336 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4337 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4338 ArgValue1, DAG.getIntPtrConstant(0, dl));
4339 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4340 ArgValue2, DAG.getIntPtrConstant(1, dl));
4341 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4342 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4343 } else {
4344 const TargetRegisterClass *RC;
4345
4346 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4347 RC = &ARM::HPRRegClass;
4348 else if (RegVT == MVT::f32)
4349 RC = &ARM::SPRRegClass;
4350 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4351 RegVT == MVT::v4bf16)
4352 RC = &ARM::DPRRegClass;
4353 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4354 RegVT == MVT::v8bf16)
4355 RC = &ARM::QPRRegClass;
4356 else if (RegVT == MVT::i32)
4357 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4358 : &ARM::GPRRegClass;
4359 else
4360 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4360)
;
4361
4362 // Transform the arguments in physical registers into virtual ones.
4363 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4364 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4365
4366 // If this value is passed in r0 and has the returned attribute (e.g.
4367 // C++ 'structors), record this fact for later use.
4368 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4369 AFI->setPreservesR0();
4370 }
4371 }
4372
4373 // If this is an 8 or 16-bit value, it is really passed promoted
4374 // to 32 bits. Insert an assert[sz]ext to capture this, then
4375 // truncate to the right size.
4376 switch (VA.getLocInfo()) {
4377 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4377)
;
4378 case CCValAssign::Full: break;
4379 case CCValAssign::BCvt:
4380 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4381 break;
4382 case CCValAssign::SExt:
4383 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4384 DAG.getValueType(VA.getValVT()));
4385 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4386 break;
4387 case CCValAssign::ZExt:
4388 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4389 DAG.getValueType(VA.getValVT()));
4390 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4391 break;
4392 }
4393
4394 // f16 arguments have their size extended to 4 bytes and passed as if they
4395 // had been copied to the LSBs of a 32-bit register.
4396 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4397 if (VA.needsCustom() &&
4398 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4399 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4400
4401 InVals.push_back(ArgValue);
4402 } else { // VA.isRegLoc()
4403 // sanity check
4404 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4404, __PRETTY_FUNCTION__))
;
4405 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4405, __PRETTY_FUNCTION__))
;
4406
4407 int index = VA.getValNo();
4408
4409 // Some Ins[] entries become multiple ArgLoc[] entries.
4410 // Process them only once.
4411 if (index != lastInsIndex)
4412 {
4413 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4414 // FIXME: For now, all byval parameter objects are marked mutable.
4415 // This can be changed with more analysis.
4416 // In case of tail call optimization mark all arguments mutable.
4417 // Since they could be overwritten by lowering of arguments in case of
4418 // a tail call.
4419 if (Flags.isByVal()) {
4420 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4421, __PRETTY_FUNCTION__))
4421 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4421, __PRETTY_FUNCTION__))
;
4422 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4423
4424 int FrameIndex = StoreByValRegs(
4425 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4426 VA.getLocMemOffset(), Flags.getByValSize());
4427 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4428 CCInfo.nextInRegsParam();
4429 } else {
4430 unsigned FIOffset = VA.getLocMemOffset();
4431 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4432 FIOffset, true);
4433
4434 // Create load nodes to retrieve arguments from the stack.
4435 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4436 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4437 MachinePointerInfo::getFixedStack(
4438 DAG.getMachineFunction(), FI)));
4439 }
4440 lastInsIndex = index;
4441 }
4442 }
4443 }
4444
4445 // varargs
4446 if (isVarArg && MFI.hasVAStart()) {
4447 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4448 TotalArgRegsSaveSize);
4449 if (AFI->isCmseNSEntryFunction()) {
4450 DiagnosticInfoUnsupported Diag(
4451 DAG.getMachineFunction().getFunction(),
4452 "secure entry function must not be variadic", dl.getDebugLoc());
4453 DAG.getContext()->diagnose(Diag);
4454 }
4455 }
4456
4457 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4458
4459 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4460 DiagnosticInfoUnsupported Diag(
4461 DAG.getMachineFunction().getFunction(),
4462 "secure entry function requires arguments on stack", dl.getDebugLoc());
4463 DAG.getContext()->diagnose(Diag);
4464 }
4465
4466 return Chain;
4467}
4468
4469/// isFloatingPointZero - Return true if this is +0.0.
4470static bool isFloatingPointZero(SDValue Op) {
4471 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4472 return CFP->getValueAPF().isPosZero();
4473 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4474 // Maybe this has already been legalized into the constant pool?
4475 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4476 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4477 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4478 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4479 return CFP->getValueAPF().isPosZero();
4480 }
4481 } else if (Op->getOpcode() == ISD::BITCAST &&
4482 Op->getValueType(0) == MVT::f64) {
4483 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4484 // created by LowerConstantFP().
4485 SDValue BitcastOp = Op->getOperand(0);
4486 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4487 isNullConstant(BitcastOp->getOperand(0)))
4488 return true;
4489 }
4490 return false;
4491}
4492
4493/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4494/// the given operands.
4495SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4496 SDValue &ARMcc, SelectionDAG &DAG,
4497 const SDLoc &dl) const {
4498 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4499 unsigned C = RHSC->getZExtValue();
4500 if (!isLegalICmpImmediate((int32_t)C)) {
4501 // Constant does not fit, try adjusting it by one.
4502 switch (CC) {
4503 default: break;
4504 case ISD::SETLT:
4505 case ISD::SETGE:
4506 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4507 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4508 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4509 }
4510 break;
4511 case ISD::SETULT:
4512 case ISD::SETUGE:
4513 if (C != 0 && isLegalICmpImmediate(C-1)) {
4514 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4515 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4516 }
4517 break;
4518 case ISD::SETLE:
4519 case ISD::SETGT:
4520 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4521 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4522 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4523 }
4524 break;
4525 case ISD::SETULE:
4526 case ISD::SETUGT:
4527 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4528 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4529 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4530 }
4531 break;
4532 }
4533 }
4534 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4535 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4536 // In ARM and Thumb-2, the compare instructions can shift their second
4537 // operand.
4538 CC = ISD::getSetCCSwappedOperands(CC);
4539 std::swap(LHS, RHS);
4540 }
4541
4542 // Thumb1 has very limited immediate modes, so turning an "and" into a
4543 // shift can save multiple instructions.
4544 //
4545 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4546 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4547 // own. If it's the operand to an unsigned comparison with an immediate,
4548 // we can eliminate one of the shifts: we transform
4549 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4550 //
4551 // We avoid transforming cases which aren't profitable due to encoding
4552 // details:
4553 //
4554 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4555 // would not; in that case, we're essentially trading one immediate load for
4556 // another.
4557 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4558 // 3. C2 is zero; we have other code for this special case.
4559 //
4560 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4561 // instruction, since the AND is always one instruction anyway, but we could
4562 // use narrow instructions in some cases.
4563 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4564 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4565 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4566 !isSignedIntSetCC(CC)) {
4567 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4568 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4569 uint64_t RHSV = RHSC->getZExtValue();
4570 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4571 unsigned ShiftBits = countLeadingZeros(Mask);
4572 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4573 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4574 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4575 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4576 }
4577 }
4578 }
4579
4580 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4581 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4582 // way a cmp would.
4583 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4584 // some tweaks to the heuristics for the previous and->shift transform.
4585 // FIXME: Optimize cases where the LHS isn't a shift.
4586 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4587 isa<ConstantSDNode>(RHS) &&
4588 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4589 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4590 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4591 unsigned ShiftAmt =
4592 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4593 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4594 DAG.getVTList(MVT::i32, MVT::i32),
4595 LHS.getOperand(0),
4596 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4597 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4598 Shift.getValue(1), SDValue());
4599 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4600 return Chain.getValue(1);
4601 }
4602
4603 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4604
4605 // If the RHS is a constant zero then the V (overflow) flag will never be
4606 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4607 // simpler for other passes (like the peephole optimiser) to deal with.
4608 if (isNullConstant(RHS)) {
4609 switch (CondCode) {
4610 default: break;
4611 case ARMCC::GE:
4612 CondCode = ARMCC::PL;
4613 break;
4614 case ARMCC::LT:
4615 CondCode = ARMCC::MI;
4616 break;
4617 }
4618 }
4619
4620 ARMISD::NodeType CompareType;
4621 switch (CondCode) {
4622 default:
4623 CompareType = ARMISD::CMP;
4624 break;
4625 case ARMCC::EQ:
4626 case ARMCC::NE:
4627 // Uses only Z Flag
4628 CompareType = ARMISD::CMPZ;
4629 break;
4630 }
4631 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4632 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4633}
4634
4635/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4636SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4637 SelectionDAG &DAG, const SDLoc &dl,
4638 bool Signaling) const {
4639 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4639, __PRETTY_FUNCTION__))
;
4640 SDValue Cmp;
4641 if (!isFloatingPointZero(RHS))
4642 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4643 dl, MVT::Glue, LHS, RHS);
4644 else
4645 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4646 dl, MVT::Glue, LHS);
4647 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4648}
4649
4650/// duplicateCmp - Glue values can have only one use, so this function
4651/// duplicates a comparison node.
4652SDValue
4653ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4654 unsigned Opc = Cmp.getOpcode();
4655 SDLoc DL(Cmp);
4656 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4657 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4658
4659 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4659, __PRETTY_FUNCTION__))
;
4660 Cmp = Cmp.getOperand(0);
4661 Opc = Cmp.getOpcode();
4662 if (Opc == ARMISD::CMPFP)
4663 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4664 else {
4665 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4665, __PRETTY_FUNCTION__))
;
4666 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4667 }
4668 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4669}
4670
4671// This function returns three things: the arithmetic computation itself
4672// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4673// comparison and the condition code define the case in which the arithmetic
4674// computation *does not* overflow.
4675std::pair<SDValue, SDValue>
4676ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4677 SDValue &ARMcc) const {
4678 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4678, __PRETTY_FUNCTION__))
;
4679
4680 SDValue Value, OverflowCmp;
4681 SDValue LHS = Op.getOperand(0);
4682 SDValue RHS = Op.getOperand(1);
4683 SDLoc dl(Op);
4684
4685 // FIXME: We are currently always generating CMPs because we don't support
4686 // generating CMN through the backend. This is not as good as the natural
4687 // CMP case because it causes a register dependency and cannot be folded
4688 // later.
4689
4690 switch (Op.getOpcode()) {
4691 default:
4692 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4692)
;
4693 case ISD::SADDO:
4694 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4695 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4696 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4697 break;
4698 case ISD::UADDO:
4699 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4700 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4701 // We do not use it in the USUBO case as Value may not be used.
4702 Value = DAG.getNode(ARMISD::ADDC, dl,
4703 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4704 .getValue(0);
4705 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4706 break;
4707 case ISD::SSUBO:
4708 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4709 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4710 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4711 break;
4712 case ISD::USUBO:
4713 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4714 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4715 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4716 break;
4717 case ISD::UMULO:
4718 // We generate a UMUL_LOHI and then check if the high word is 0.
4719 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4720 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4721 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4722 LHS, RHS);
4723 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4724 DAG.getConstant(0, dl, MVT::i32));
4725 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4726 break;
4727 case ISD::SMULO:
4728 // We generate a SMUL_LOHI and then check if all the bits of the high word
4729 // are the same as the sign bit of the low word.
4730 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4731 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4732 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4733 LHS, RHS);
4734 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4735 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4736 Value.getValue(0),
4737 DAG.getConstant(31, dl, MVT::i32)));
4738 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4739 break;
4740 } // switch (...)
4741
4742 return std::make_pair(Value, OverflowCmp);
4743}
4744
4745SDValue
4746ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4747 // Let legalize expand this if it isn't a legal type yet.
4748 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4749 return SDValue();
4750
4751 SDValue Value, OverflowCmp;
4752 SDValue ARMcc;
4753 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4754 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4755 SDLoc dl(Op);
4756 // We use 0 and 1 as false and true values.
4757 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4758 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4759 EVT VT = Op.getValueType();
4760
4761 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4762 ARMcc, CCR, OverflowCmp);
4763
4764 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4765 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4766}
4767
4768static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4769 SelectionDAG &DAG) {
4770 SDLoc DL(BoolCarry);
4771 EVT CarryVT = BoolCarry.getValueType();
4772
4773 // This converts the boolean value carry into the carry flag by doing
4774 // ARMISD::SUBC Carry, 1
4775 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4776 DAG.getVTList(CarryVT, MVT::i32),
4777 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4778 return Carry.getValue(1);
4779}
4780
4781static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4782 SelectionDAG &DAG) {
4783 SDLoc DL(Flags);
4784
4785 // Now convert the carry flag into a boolean carry. We do this
4786 // using ARMISD:ADDE 0, 0, Carry
4787 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4788 DAG.getConstant(0, DL, MVT::i32),
4789 DAG.getConstant(0, DL, MVT::i32), Flags);
4790}
4791
4792SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4793 SelectionDAG &DAG) const {
4794 // Let legalize expand this if it isn't a legal type yet.
4795 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4796 return SDValue();
4797
4798 SDValue LHS = Op.getOperand(0);
4799 SDValue RHS = Op.getOperand(1);
4800 SDLoc dl(Op);
4801
4802 EVT VT = Op.getValueType();
4803 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4804 SDValue Value;
4805 SDValue Overflow;
4806 switch (Op.getOpcode()) {
4807 default:
4808 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4808)
;
4809 case ISD::UADDO:
4810 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4811 // Convert the carry flag into a boolean value.
4812 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4813 break;
4814 case ISD::USUBO: {
4815 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4816 // Convert the carry flag into a boolean value.
4817 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4818 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4819 // value. So compute 1 - C.
4820 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4821 DAG.getConstant(1, dl, MVT::i32), Overflow);
4822 break;
4823 }
4824 }
4825
4826 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4827}
4828
4829static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4830 const ARMSubtarget *Subtarget) {
4831 EVT VT = Op.getValueType();
4832 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
4833 return SDValue();
4834 if (!VT.isSimple())
4835 return SDValue();
4836
4837 unsigned NewOpcode;
4838 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4839 switch (VT.getSimpleVT().SimpleTy) {
4840 default:
4841 return SDValue();
4842 case MVT::i8:
4843 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4844 break;
4845 case MVT::i16:
4846 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4847 break;
4848 }
4849
4850 SDLoc dl(Op);
4851 SDValue Add =
4852 DAG.getNode(NewOpcode, dl, MVT::i32,
4853 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4854 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4855 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4856}
4857
4858SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4859 SDValue Cond = Op.getOperand(0);
4860 SDValue SelectTrue = Op.getOperand(1);
4861 SDValue SelectFalse = Op.getOperand(2);
4862 SDLoc dl(Op);
4863 unsigned Opc = Cond.getOpcode();
4864
4865 if (Cond.getResNo() == 1 &&
4866 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4867 Opc == ISD::USUBO)) {
4868 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4869 return SDValue();
4870
4871 SDValue Value, OverflowCmp;
4872 SDValue ARMcc;
4873 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4874 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4875 EVT VT = Op.getValueType();
4876
4877 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4878 OverflowCmp, DAG);
4879 }
4880
4881 // Convert:
4882 //
4883 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4884 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4885 //
4886 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4887 const ConstantSDNode *CMOVTrue =
4888 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4889 const ConstantSDNode *CMOVFalse =
4890 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4891
4892 if (CMOVTrue && CMOVFalse) {
4893 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4894 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4895
4896 SDValue True;
4897 SDValue False;
4898 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4899 True = SelectTrue;
4900 False = SelectFalse;
4901 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4902 True = SelectFalse;
4903 False = SelectTrue;
4904 }
4905
4906 if (True.getNode() && False.getNode()) {
4907 EVT VT = Op.getValueType();
4908 SDValue ARMcc = Cond.getOperand(2);
4909 SDValue CCR = Cond.getOperand(3);
4910 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4911 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4911, __PRETTY_FUNCTION__))
;
4912 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4913 }
4914 }
4915 }
4916
4917 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4918 // undefined bits before doing a full-word comparison with zero.
4919 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4920 DAG.getConstant(1, dl, Cond.getValueType()));
4921
4922 return DAG.getSelectCC(dl, Cond,
4923 DAG.getConstant(0, dl, Cond.getValueType()),
4924 SelectTrue, SelectFalse, ISD::SETNE);
4925}
4926
4927static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4928 bool &swpCmpOps, bool &swpVselOps) {
4929 // Start by selecting the GE condition code for opcodes that return true for
4930 // 'equality'
4931 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4932 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4933 CondCode = ARMCC::GE;
4934
4935 // and GT for opcodes that return false for 'equality'.
4936 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4937 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4938 CondCode = ARMCC::GT;
4939
4940 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4941 // to swap the compare operands.
4942 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4943 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4944 swpCmpOps = true;
4945
4946 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4947 // If we have an unordered opcode, we need to swap the operands to the VSEL
4948 // instruction (effectively negating the condition).
4949 //
4950 // This also has the effect of swapping which one of 'less' or 'greater'
4951 // returns true, so we also swap the compare operands. It also switches
4952 // whether we return true for 'equality', so we compensate by picking the
4953 // opposite condition code to our original choice.
4954 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4955 CC == ISD::SETUGT) {
4956 swpCmpOps = !swpCmpOps;
4957 swpVselOps = !swpVselOps;
4958 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4959 }
4960
4961 // 'ordered' is 'anything but unordered', so use the VS condition code and
4962 // swap the VSEL operands.
4963 if (CC == ISD::SETO) {
4964 CondCode = ARMCC::VS;
4965 swpVselOps = true;
4966 }
4967
4968 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4969 // code and swap the VSEL operands. Also do this if we don't care about the
4970 // unordered case.
4971 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4972 CondCode = ARMCC::EQ;
4973 swpVselOps = true;
4974 }
4975}
4976
4977SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4978 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4979 SDValue Cmp, SelectionDAG &DAG) const {
4980 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4981 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4982 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4983 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4984 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4985
4986 SDValue TrueLow = TrueVal.getValue(0);
4987 SDValue TrueHigh = TrueVal.getValue(1);
4988 SDValue FalseLow = FalseVal.getValue(0);
4989 SDValue FalseHigh = FalseVal.getValue(1);
4990
4991 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4992 ARMcc, CCR, Cmp);
4993 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4994 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4995
4996 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4997 } else {
4998 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4999 Cmp);
5000 }
5001}
5002
5003static bool isGTorGE(ISD::CondCode CC) {
5004 return CC == ISD::SETGT || CC == ISD::SETGE;
5005}
5006
5007static bool isLTorLE(ISD::CondCode CC) {
5008 return CC == ISD::SETLT || CC == ISD::SETLE;
5009}
5010
5011// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5012// All of these conditions (and their <= and >= counterparts) will do:
5013// x < k ? k : x
5014// x > k ? x : k
5015// k < x ? x : k
5016// k > x ? k : x
5017static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5018 const SDValue TrueVal, const SDValue FalseVal,
5019 const ISD::CondCode CC, const SDValue K) {
5020 return (isGTorGE(CC) &&
5021 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5022 (isLTorLE(CC) &&
5023 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5024}
5025
5026// Check if two chained conditionals could be converted into SSAT or USAT.
5027//
5028// SSAT can replace a set of two conditional selectors that bound a number to an
5029// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5030//
5031// x < -k ? -k : (x > k ? k : x)
5032// x < -k ? -k : (x < k ? x : k)
5033// x > -k ? (x > k ? k : x) : -k
5034// x < k ? (x < -k ? -k : x) : k
5035// etc.
5036//
5037// LLVM canonicalizes these to either a min(max()) or a max(min())
5038// pattern. This function tries to match one of these and will return a SSAT
5039// node if successful.
5040//
5041// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5042// is a power of 2.
5043static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5044 EVT VT = Op.getValueType();
5045 SDValue V1 = Op.getOperand(0);
5046 SDValue K1 = Op.getOperand(1);
5047 SDValue TrueVal1 = Op.getOperand(2);
5048 SDValue FalseVal1 = Op.getOperand(3);
5049 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5050
5051 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5052 if (Op2.getOpcode() != ISD::SELECT_CC)
5053 return SDValue();
5054
5055 SDValue V2 = Op2.getOperand(0);
5056 SDValue K2 = Op2.getOperand(1);
5057 SDValue TrueVal2 = Op2.getOperand(2);
5058 SDValue FalseVal2 = Op2.getOperand(3);
5059 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5060
5061 SDValue V1Tmp = V1;
5062 SDValue V2Tmp = V2;
5063
5064 // Check that the registers and the constants match a max(min()) or min(max())
5065 // pattern
5066 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5067 K2 != FalseVal2 ||
5068 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5069 return SDValue();
5070
5071 // Check that the constant in the lower-bound check is
5072 // the opposite of the constant in the upper-bound check
5073 // in 1's complement.
5074 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5075 return SDValue();
5076
5077 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5078 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5079 int64_t PosVal = std::max(Val1, Val2);
5080 int64_t NegVal = std::min(Val1, Val2);
5081
5082 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5083 !isPowerOf2_64(PosVal + 1))
5084 return SDValue();
5085
5086 // Handle the difference between USAT (unsigned) and SSAT (signed)
5087 // saturation
5088 // At this point, PosVal is guaranteed to be positive
5089 uint64_t K = PosVal;
5090 SDLoc dl(Op);
5091 if (Val1 == ~Val2)
5092 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5093 DAG.getConstant(countTrailingOnes(K), dl, VT));
5094 if (NegVal == 0)
5095 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5096 DAG.getConstant(countTrailingOnes(K), dl, VT));
5097
5098 return SDValue();
5099}
5100
5101// Check if a condition of the type x < k ? k : x can be converted into a
5102// bit operation instead of conditional moves.
5103// Currently this is allowed given:
5104// - The conditions and values match up
5105// - k is 0 or -1 (all ones)
5106// This function will not check the last condition, thats up to the caller
5107// It returns true if the transformation can be made, and in such case
5108// returns x in V, and k in SatK.
5109static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5110 SDValue &SatK)
5111{
5112 SDValue LHS = Op.getOperand(0);
5113 SDValue RHS = Op.getOperand(1);
5114 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5115 SDValue TrueVal = Op.getOperand(2);
5116 SDValue FalseVal = Op.getOperand(3);
5117
5118 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5119 ? &RHS
5120 : nullptr;
5121
5122 // No constant operation in comparison, early out
5123 if (!K)
5124 return false;
5125
5126 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5127 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5128 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5129
5130 // If the constant on left and right side, or variable on left and right,
5131 // does not match, early out
5132 if (*K != KTmp || V != VTmp)
5133 return false;
5134
5135 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5136 SatK = *K;
5137 return true;
5138 }
5139
5140 return false;
5141}
5142
5143bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5144 if (VT == MVT::f32)
5145 return !Subtarget->hasVFP2Base();
5146 if (VT == MVT::f64)
5147 return !Subtarget->hasFP64();
5148 if (VT == MVT::f16)
5149 return !Subtarget->hasFullFP16();
5150 return false;
5151}
5152
5153SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5154 EVT VT = Op.getValueType();
5155 SDLoc dl(Op);
5156
5157 // Try to convert two saturating conditional selects into a single SSAT
5158 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5159 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5160 return SatValue;
5161
5162 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5163 // into more efficient bit operations, which is possible when k is 0 or -1
5164 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5165 // single instructions. On Thumb the shift and the bit operation will be two
5166 // instructions.
5167 // Only allow this transformation on full-width (32-bit) operations
5168 SDValue LowerSatConstant;
5169 SDValue SatValue;
5170 if (VT == MVT::i32 &&
5171 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5172 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5173 DAG.getConstant(31, dl, VT));
5174 if (isNullConstant(LowerSatConstant)) {
5175 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5176 DAG.getAllOnesConstant(dl, VT));
5177 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5178 } else if (isAllOnesConstant(LowerSatConstant))
5179 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5180 }
5181
5182 SDValue LHS = Op.getOperand(0);
5183 SDValue RHS = Op.getOperand(1);
5184 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5185 SDValue TrueVal = Op.getOperand(2);
5186 SDValue FalseVal = Op.getOperand(3);
5187 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5188 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5189
5190 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5191 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5192 unsigned TVal = CTVal->getZExtValue();
5193 unsigned FVal = CFVal->getZExtValue();
5194 unsigned Opcode = 0;
5195
5196 if (TVal == ~FVal) {
5197 Opcode = ARMISD::CSINV;
5198 } else if (TVal == ~FVal + 1) {
5199 Opcode = ARMISD::CSNEG;
5200 } else if (TVal + 1 == FVal) {
5201 Opcode = ARMISD::CSINC;
5202 } else if (TVal == FVal + 1) {
5203 Opcode = ARMISD::CSINC;
5204 std::swap(TrueVal, FalseVal);
5205 std::swap(TVal, FVal);
5206 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5207 }
5208
5209 if (Opcode) {
5210 // If one of the constants is cheaper than another, materialise the
5211 // cheaper one and let the csel generate the other.
5212 if (Opcode != ARMISD::CSINC &&
5213 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5214 std::swap(TrueVal, FalseVal);
5215 std::swap(TVal, FVal);
5216 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5217 }
5218
5219 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5220 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5221 // -(-a) == a, but (a+1)+1 != a).
5222 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5223 std::swap(TrueVal, FalseVal);
5224 std::swap(TVal, FVal);
5225 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5226 }
5227 if (TVal == 0)
5228 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
5229
5230 // Drops F's value because we can get it by inverting/negating TVal.
5231 FalseVal = TrueVal;
5232
5233 SDValue ARMcc;
5234 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5235 EVT VT = TrueVal.getValueType();
5236 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5237 }
5238 }
5239
5240 if (isUnsupportedFloatingType(LHS.getValueType())) {
5241 DAG.getTargetLoweringInfo().softenSetCCOperands(
5242 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5243
5244 // If softenSetCCOperands only returned one value, we should compare it to
5245 // zero.
5246 if (!RHS.getNode()) {
5247 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5248 CC = ISD::SETNE;
5249 }
5250 }
5251
5252 if (LHS.getValueType() == MVT::i32) {
5253 // Try to generate VSEL on ARMv8.
5254 // The VSEL instruction can't use all the usual ARM condition
5255 // codes: it only has two bits to select the condition code, so it's
5256 // constrained to use only GE, GT, VS and EQ.
5257 //
5258 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5259 // swap the operands of the previous compare instruction (effectively
5260 // inverting the compare condition, swapping 'less' and 'greater') and
5261 // sometimes need to swap the operands to the VSEL (which inverts the
5262 // condition in the sense of firing whenever the previous condition didn't)
5263 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5264 TrueVal.getValueType() == MVT::f32 ||
5265 TrueVal.getValueType() == MVT::f64)) {
5266 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5267 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5268 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5269 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5270 std::swap(TrueVal, FalseVal);
5271 }
5272 }
5273
5274 SDValue ARMcc;
5275 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5276 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5277 // Choose GE over PL, which vsel does now support
5278 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5279 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5280 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5281 }
5282
5283 ARMCC::CondCodes CondCode, CondCode2;
5284 FPCCToARMCC(CC, CondCode, CondCode2);
5285
5286 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5287 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5288 // must use VSEL (limited condition codes), due to not having conditional f16
5289 // moves.
5290 if (Subtarget->hasFPARMv8Base() &&
5291 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5292 (TrueVal.getValueType() == MVT::f16 ||
5293 TrueVal.getValueType() == MVT::f32 ||
5294 TrueVal.getValueType() == MVT::f64)) {
5295 bool swpCmpOps = false;
5296 bool swpVselOps = false;
5297 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5298
5299 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5300 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5301 if (swpCmpOps)
5302 std::swap(LHS, RHS);
5303 if (swpVselOps)
5304 std::swap(TrueVal, FalseVal);
5305 }
5306 }
5307
5308 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5309 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5310 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5311 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5312 if (CondCode2 != ARMCC::AL) {
5313 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5314 // FIXME: Needs another CMP because flag can have but one use.
5315 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5316 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5317 }
5318 return Result;
5319}
5320
5321/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5322/// to morph to an integer compare sequence.
5323static bool canChangeToInt(SDValue Op, bool &SeenZero,
5324 const ARMSubtarget *Subtarget) {
5325 SDNode *N = Op.getNode();
5326 if (!N->hasOneUse())
5327 // Otherwise it requires moving the value from fp to integer registers.
5328 return false;
5329 if (!N->getNumValues())
5330 return false;
5331 EVT VT = Op.getValueType();
5332 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5333 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5334 // vmrs are very slow, e.g. cortex-a8.
5335 return false;
5336
5337 if (isFloatingPointZero(Op)) {
5338 SeenZero = true;
5339 return true;
5340 }
5341 return ISD::isNormalLoad(N);
5342}
5343
5344static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5345 if (isFloatingPointZero(Op))
5346 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5347
5348 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5349 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5350 Ld->getPointerInfo(), Ld->getAlignment(),
5351 Ld->getMemOperand()->getFlags());
5352
5353 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5353)
;
5354}
5355
5356static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5357 SDValue &RetVal1, SDValue &RetVal2) {
5358 SDLoc dl(Op);
5359
5360 if (isFloatingPointZero(Op)) {
5361 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5362 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5363 return;
5364 }
5365
5366 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5367 SDValue Ptr = Ld->getBasePtr();
5368 RetVal1 =
5369 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5370 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5371
5372 EVT PtrType = Ptr.getValueType();
5373 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5374 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5375 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5376 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5377 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5378 Ld->getMemOperand()->getFlags());
5379 return;
5380 }
5381
5382 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5382)
;
5383}
5384
5385/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5386/// f32 and even f64 comparisons to integer ones.
5387SDValue
5388ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5389 SDValue Chain = Op.getOperand(0);
5390 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5391 SDValue LHS = Op.getOperand(2);
5392 SDValue RHS = Op.getOperand(3);
5393 SDValue Dest = Op.getOperand(4);
5394 SDLoc dl(Op);
5395
5396 bool LHSSeenZero = false;
5397 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5398 bool RHSSeenZero = false;
5399 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5400 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5401 // If unsafe fp math optimization is enabled and there are no other uses of
5402 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5403 // to an integer comparison.
5404 if (CC == ISD::SETOEQ)
5405 CC = ISD::SETEQ;
5406 else if (CC == ISD::SETUNE)
5407 CC = ISD::SETNE;
5408
5409 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5410 SDValue ARMcc;
5411 if (LHS.getValueType() == MVT::f32) {
5412 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5413 bitcastf32Toi32(LHS, DAG), Mask);
5414 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5415 bitcastf32Toi32(RHS, DAG), Mask);
5416 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5417 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5418 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5419 Chain, Dest, ARMcc, CCR, Cmp);
5420 }
5421
5422 SDValue LHS1, LHS2;
5423 SDValue RHS1, RHS2;
5424 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5425 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5426 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5427 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5428 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5429 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5430 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5431 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5432 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5433 }
5434
5435 return SDValue();
5436}
5437
5438SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5439 SDValue Chain = Op.getOperand(0);
5440 SDValue Cond = Op.getOperand(1);
5441 SDValue Dest = Op.getOperand(2);
5442 SDLoc dl(Op);
5443
5444 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5445 // instruction.
5446 unsigned Opc = Cond.getOpcode();
5447 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5448 !Subtarget->isThumb1Only();
5449 if (Cond.getResNo() == 1 &&
5450 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5451 Opc == ISD::USUBO || OptimizeMul)) {
5452 // Only lower legal XALUO ops.
5453 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5454 return SDValue();
5455
5456 // The actual operation with overflow check.
5457 SDValue Value, OverflowCmp;
5458 SDValue ARMcc;
5459 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5460
5461 // Reverse the condition code.
5462 ARMCC::CondCodes CondCode =
5463 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5464 CondCode = ARMCC::getOppositeCondition(CondCode);
5465 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5466 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5467
5468 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5469 OverflowCmp);
5470 }
5471
5472 return SDValue();
5473}
5474
5475SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5476 SDValue Chain = Op.getOperand(0);
5477 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5478 SDValue LHS = Op.getOperand(2);
5479 SDValue RHS = Op.getOperand(3);
5480 SDValue Dest = Op.getOperand(4);
5481 SDLoc dl(Op);
5482
5483 if (isUnsupportedFloatingType(LHS.getValueType())) {
5484 DAG.getTargetLoweringInfo().softenSetCCOperands(
5485 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5486
5487 // If softenSetCCOperands only returned one value, we should compare it to
5488 // zero.
5489 if (!RHS.getNode()) {
5490 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5491 CC = ISD::SETNE;
5492 }
5493 }
5494
5495 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5496 // instruction.
5497 unsigned Opc = LHS.getOpcode();
5498 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5499 !Subtarget->isThumb1Only();
5500 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5501 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5502 Opc == ISD::USUBO || OptimizeMul) &&
5503 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5504 // Only lower legal XALUO ops.
5505 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5506 return SDValue();
5507
5508 // The actual operation with overflow check.
5509 SDValue Value, OverflowCmp;
5510 SDValue ARMcc;
5511 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5512
5513 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5514 // Reverse the condition code.
5515 ARMCC::CondCodes CondCode =
5516 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5517 CondCode = ARMCC::getOppositeCondition(CondCode);
5518 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5519 }
5520 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5521
5522 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5523 OverflowCmp);
5524 }
5525
5526 if (LHS.getValueType() == MVT::i32) {
5527 SDValue ARMcc;
5528 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5529 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5530 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5531 Chain, Dest, ARMcc, CCR, Cmp);
5532 }
5533
5534 if (getTargetMachine().Options.UnsafeFPMath &&
5535 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5536 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5537 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5538 return Result;
5539 }
5540
5541 ARMCC::CondCodes CondCode, CondCode2;
5542 FPCCToARMCC(CC, CondCode, CondCode2);
5543
5544 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5545 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5546 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5547 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5548 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5549 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5550 if (CondCode2 != ARMCC::AL) {
5551 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5552 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5553 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5554 }
5555 return Res;
5556}
5557
5558SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5559 SDValue Chain = Op.getOperand(0);
5560 SDValue Table = Op.getOperand(1);
5561 SDValue Index = Op.getOperand(2);
5562 SDLoc dl(Op);
5563
5564 EVT PTy = getPointerTy(DAG.getDataLayout());
5565 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5566 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5567 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5568 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5569 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5570 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5571 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5572 // which does another jump to the destination. This also makes it easier
5573 // to translate it to TBB / TBH later (Thumb2 only).
5574 // FIXME: This might not work if the function is extremely large.
5575 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5576 Addr, Op.getOperand(2), JTI);
5577 }
5578 if (isPositionIndependent() || Subtarget->isROPI()) {
5579 Addr =
5580 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5581 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5582 Chain = Addr.getValue(1);
5583 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5584 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5585 } else {
5586 Addr =
5587 DAG.getLoad(PTy, dl, Chain, Addr,
5588 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5589 Chain = Addr.getValue(1);
5590 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5591 }
5592}
5593
5594static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5595 EVT VT = Op.getValueType();
5596 SDLoc dl(Op);
5597
5598 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5599 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5600 return Op;
5601 return DAG.UnrollVectorOp(Op.getNode());
5602 }
5603
5604 const bool HasFullFP16 =
5605 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5606
5607 EVT NewTy;
5608 const EVT OpTy = Op.getOperand(0).getValueType();
5609 if (OpTy == MVT::v4f32)
5610 NewTy = MVT::v4i32;
5611 else if (OpTy == MVT::v4f16 && HasFullFP16)
5612 NewTy = MVT::v4i16;
5613 else if (OpTy == MVT::v8f16 && HasFullFP16)
5614 NewTy = MVT::v8i16;
5615 else
5616 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5616)
;
5617
5618 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5619 return DAG.UnrollVectorOp(Op.getNode());
5620
5621 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5622 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5623}
5624
5625SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5626 EVT VT = Op.getValueType();
5627 if (VT.isVector())
5628 return LowerVectorFP_TO_INT(Op, DAG);
5629
5630 bool IsStrict = Op->isStrictFPOpcode();
5631 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5632
5633 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5634 RTLIB::Libcall LC;
5635 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5636 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5637 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5638 Op.getValueType());
5639 else
5640 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5641 Op.getValueType());
5642 SDLoc Loc(Op);
5643 MakeLibCallOptions CallOptions;
5644 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5645 SDValue Result;
5646 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5647 CallOptions, Loc, Chain);
5648 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5649 }
5650
5651 // FIXME: Remove this when we have strict fp instruction selection patterns
5652 if (IsStrict) {
5653 SDLoc Loc(Op);
5654 SDValue Result =
5655 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5656 : ISD::FP_TO_UINT,
5657 Loc, Op.getValueType(), SrcVal);
5658 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5659 }
5660
5661 return Op;
5662}
5663
5664static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5665 EVT VT = Op.getValueType();
5666 SDLoc dl(Op);
5667
5668 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5669 if (VT.getVectorElementType() == MVT::f32)
5670 return Op;
5671 return DAG.UnrollVectorOp(Op.getNode());
5672 }
5673
5674 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5676, __PRETTY_FUNCTION__))
5675 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5676, __PRETTY_FUNCTION__))
5676 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5676, __PRETTY_FUNCTION__))
;
5677
5678 const bool HasFullFP16 =
5679 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5680
5681 EVT DestVecType;
5682 if (VT == MVT::v4f32)
5683 DestVecType = MVT::v4i32;
5684 else if (VT == MVT::v4f16 && HasFullFP16)
5685 DestVecType = MVT::v4i16;
5686 else if (VT == MVT::v8f16 && HasFullFP16)
5687 DestVecType = MVT::v8i16;
5688 else
5689 return DAG.UnrollVectorOp(Op.getNode());
5690
5691 unsigned CastOpc;
5692 unsigned Opc;
5693 switch (Op.getOpcode()) {
5694 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5694)
;
5695 case ISD::SINT_TO_FP:
5696 CastOpc = ISD::SIGN_EXTEND;
5697 Opc = ISD::SINT_TO_FP;
5698 break;
5699 case ISD::UINT_TO_FP:
5700 CastOpc = ISD::ZERO_EXTEND;
5701 Opc = ISD::UINT_TO_FP;
5702 break;
5703 }
5704
5705 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5706 return DAG.getNode(Opc, dl, VT, Op);
5707}
5708
5709SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5710 EVT VT = Op.getValueType();
5711 if (VT.isVector())
5712 return LowerVectorINT_TO_FP(Op, DAG);
5713 if (isUnsupportedFloatingType(VT)) {
5714 RTLIB::Libcall LC;
5715 if (Op.getOpcode() == ISD::SINT_TO_FP)
5716 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5717 Op.getValueType());
5718 else
5719 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5720 Op.getValueType());
5721 MakeLibCallOptions CallOptions;
5722 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5723 CallOptions, SDLoc(Op)).first;
5724 }
5725
5726 return Op;
5727}
5728
5729SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5730 // Implement fcopysign with a fabs and a conditional fneg.
5731 SDValue Tmp0 = Op.getOperand(0);
5732 SDValue Tmp1 = Op.getOperand(1);
5733 SDLoc dl(Op);
5734 EVT VT = Op.getValueType();
5735 EVT SrcVT = Tmp1.getValueType();
5736 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5737 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5738 bool UseNEON = !InGPR && Subtarget->hasNEON();
5739
5740 if (UseNEON) {
5741 // Use VBSL to copy the sign bit.
5742 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5743 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5744 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5745 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5746 if (VT == MVT::f64)
5747 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5748 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5749 DAG.getConstant(32, dl, MVT::i32));
5750 else /*if (VT == MVT::f32)*/
5751 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5752 if (SrcVT == MVT::f32) {
5753 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5754 if (VT == MVT::f64)
5755 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5756 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5757 DAG.getConstant(32, dl, MVT::i32));
5758 } else if (VT == MVT::f32)
5759 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5760 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5761 DAG.getConstant(32, dl, MVT::i32));
5762 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5763 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5764
5765 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5766 dl, MVT::i32);
5767 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5768 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5769 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5770
5771 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5772 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5773 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5774 if (VT == MVT::f32) {
5775 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5776 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5777 DAG.getConstant(0, dl, MVT::i32));
5778 } else {
5779 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5780 }
5781
5782 return Res;
5783 }
5784
5785 // Bitcast operand 1 to i32.
5786 if (SrcVT == MVT::f64)
5787 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5788 Tmp1).getValue(1);
5789 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5790
5791 // Or in the signbit with integer operations.
5792 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5793 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5794 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5795 if (VT == MVT::f32) {
5796 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5797 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5798 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5799 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5800 }
5801
5802 // f64: Or the high part with signbit and then combine two parts.
5803 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5804 Tmp0);
5805 SDValue Lo = Tmp0.getValue(0);
5806 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5807 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5808 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5809}
5810
5811SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5812 MachineFunction &MF = DAG.getMachineFunction();
5813 MachineFrameInfo &MFI = MF.getFrameInfo();
5814 MFI.setReturnAddressIsTaken(true);
5815
5816 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5817 return SDValue();
5818
5819 EVT VT = Op.getValueType();
5820 SDLoc dl(Op);
5821 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5822 if (Depth) {
5823 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5824 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5825 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5826 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5827 MachinePointerInfo());
5828 }
5829
5830 // Return LR, which contains the return address. Mark it an implicit live-in.
5831 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5832 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5833}
5834
5835SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5836 const ARMBaseRegisterInfo &ARI =
5837 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5838 MachineFunction &MF = DAG.getMachineFunction();
5839 MachineFrameInfo &MFI = MF.getFrameInfo();
5840 MFI.setFrameAddressIsTaken(true);
5841
5842 EVT VT = Op.getValueType();
5843 SDLoc dl(Op); // FIXME probably not meaningful
5844 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5845 Register FrameReg = ARI.getFrameRegister(MF);
5846 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5847 while (Depth--)
5848 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5849 MachinePointerInfo());
5850 return FrameAddr;
5851}
5852
5853// FIXME? Maybe this could be a TableGen attribute on some registers and
5854// this table could be generated automatically from RegInfo.
5855Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5856 const MachineFunction &MF) const {
5857 Register Reg = StringSwitch<unsigned>(RegName)
5858 .Case("sp", ARM::SP)
5859 .Default(0);
5860 if (Reg)
5861 return Reg;
5862 report_fatal_error(Twine("Invalid register name \""
5863 + StringRef(RegName) + "\"."));
5864}
5865
5866// Result is 64 bit value so split into two 32 bit values and return as a
5867// pair of values.
5868static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5869 SelectionDAG &DAG) {
5870 SDLoc DL(N);
5871
5872 // This function is only supposed to be called for i64 type destination.
5873 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5874, __PRETTY_FUNCTION__))
5874 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5874, __PRETTY_FUNCTION__))
;
5875
5876 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5877 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5878 N->getOperand(0),
5879 N->getOperand(1));
5880
5881 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5882 Read.getValue(1)));
5883 Results.push_back(Read.getOperand(0));
5884}
5885
5886/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5887/// When \p DstVT, the destination type of \p BC, is on the vector
5888/// register bank and the source of bitcast, \p Op, operates on the same bank,
5889/// it might be possible to combine them, such that everything stays on the
5890/// vector register bank.
5891/// \p return The node that would replace \p BT, if the combine
5892/// is possible.
5893static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5894 SelectionDAG &DAG) {
5895 SDValue Op = BC->getOperand(0);
5896 EVT DstVT = BC->getValueType(0);
5897
5898 // The only vector instruction that can produce a scalar (remember,
5899 // since the bitcast was about to be turned into VMOVDRR, the source
5900 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5901 // Moreover, we can do this combine only if there is one use.
5902 // Finally, if the destination type is not a vector, there is not
5903 // much point on forcing everything on the vector bank.