Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2605, column 20
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/build-llvm/lib/Target/ARM -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-06-13-111025-38230-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/IntrinsicsARM.h"
83#include "llvm/IR/Module.h"
84#include "llvm/IR/PatternMatch.h"
85#include "llvm/IR/Type.h"
86#include "llvm/IR/User.h"
87#include "llvm/IR/Value.h"
88#include "llvm/MC/MCInstrDesc.h"
89#include "llvm/MC/MCInstrItineraries.h"
90#include "llvm/MC/MCRegisterInfo.h"
91#include "llvm/MC/MCSchedule.h"
92#include "llvm/Support/AtomicOrdering.h"
93#include "llvm/Support/BranchProbability.h"
94#include "llvm/Support/Casting.h"
95#include "llvm/Support/CodeGen.h"
96#include "llvm/Support/CommandLine.h"
97#include "llvm/Support/Compiler.h"
98#include "llvm/Support/Debug.h"
99#include "llvm/Support/ErrorHandling.h"
100#include "llvm/Support/KnownBits.h"
101#include "llvm/Support/MachineValueType.h"
102#include "llvm/Support/MathExtras.h"
103#include "llvm/Support/raw_ostream.h"
104#include "llvm/Target/TargetMachine.h"
105#include "llvm/Target/TargetOptions.h"
106#include <algorithm>
107#include <cassert>
108#include <cstdint>
109#include <cstdlib>
110#include <iterator>
111#include <limits>
112#include <string>
113#include <tuple>
114#include <utility>
115#include <vector>
116
117using namespace llvm;
118using namespace llvm::PatternMatch;
119
120#define DEBUG_TYPE"arm-isel" "arm-isel"
121
122STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
123STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
124STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
125STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
126 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
127
128static cl::opt<bool>
129ARMInterworking("arm-interworking", cl::Hidden,
130 cl::desc("Enable / disable ARM interworking (for debugging only)"),
131 cl::init(true));
132
133static cl::opt<bool> EnableConstpoolPromotion(
134 "arm-promote-constant", cl::Hidden,
135 cl::desc("Enable / disable promotion of unnamed_addr constants into "
136 "constant pools"),
137 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
138static cl::opt<unsigned> ConstpoolPromotionMaxSize(
139 "arm-promote-constant-max-size", cl::Hidden,
140 cl::desc("Maximum size of constant to promote into a constant pool"),
141 cl::init(64));
142static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
143 "arm-promote-constant-max-total", cl::Hidden,
144 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
145 cl::init(128));
146
147cl::opt<unsigned>
148MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
149 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
150 cl::init(2));
151
152// The APCS parameter registers.
153static const MCPhysReg GPRArgRegs[] = {
154 ARM::R0, ARM::R1, ARM::R2, ARM::R3
155};
156
157void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
158 MVT PromotedBitwiseVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Promote all bit-wise operations.
198 if (VT.isInteger() && VT != PromotedBitwiseVT) {
199 setOperationAction(ISD::AND, VT, Promote);
200 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
201 setOperationAction(ISD::OR, VT, Promote);
202 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
203 setOperationAction(ISD::XOR, VT, Promote);
204 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
205 }
206
207 // Neon does not support vector divide/remainder operations.
208 setOperationAction(ISD::SDIV, VT, Expand);
209 setOperationAction(ISD::UDIV, VT, Expand);
210 setOperationAction(ISD::FDIV, VT, Expand);
211 setOperationAction(ISD::SREM, VT, Expand);
212 setOperationAction(ISD::UREM, VT, Expand);
213 setOperationAction(ISD::FREM, VT, Expand);
214 setOperationAction(ISD::SDIVREM, VT, Expand);
215 setOperationAction(ISD::UDIVREM, VT, Expand);
216
217 if (!VT.isFloatingPoint() &&
218 VT != MVT::v2i64 && VT != MVT::v1i64)
219 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
220 setOperationAction(Opcode, VT, Legal);
221 if (!VT.isFloatingPoint())
222 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
223 setOperationAction(Opcode, VT, Legal);
224}
225
226void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
227 addRegisterClass(VT, &ARM::DPRRegClass);
228 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
229}
230
231void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
232 addRegisterClass(VT, &ARM::DPairRegClass);
233 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
234}
235
236void ARMTargetLowering::setAllExpand(MVT VT) {
237 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
238 setOperationAction(Opc, VT, Expand);
239
240 // We support these really simple operations even on types where all
241 // the actual arithmetic has to be broken down into simpler
242 // operations or turned into library calls.
243 setOperationAction(ISD::BITCAST, VT, Legal);
244 setOperationAction(ISD::LOAD, VT, Legal);
245 setOperationAction(ISD::STORE, VT, Legal);
246 setOperationAction(ISD::UNDEF, VT, Legal);
247}
248
249void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
250 LegalizeAction Action) {
251 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
252 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
253 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
254}
255
256void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
257 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
258
259 for (auto VT : IntTypes) {
260 addRegisterClass(VT, &ARM::MQPRRegClass);
261 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
262 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
263 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
264 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
265 setOperationAction(ISD::SHL, VT, Custom);
266 setOperationAction(ISD::SRA, VT, Custom);
267 setOperationAction(ISD::SRL, VT, Custom);
268 setOperationAction(ISD::SMIN, VT, Legal);
269 setOperationAction(ISD::SMAX, VT, Legal);
270 setOperationAction(ISD::UMIN, VT, Legal);
271 setOperationAction(ISD::UMAX, VT, Legal);
272 setOperationAction(ISD::ABS, VT, Legal);
273 setOperationAction(ISD::SETCC, VT, Custom);
274 setOperationAction(ISD::MLOAD, VT, Custom);
275 setOperationAction(ISD::MSTORE, VT, Legal);
276 setOperationAction(ISD::CTLZ, VT, Legal);
277 setOperationAction(ISD::CTTZ, VT, Custom);
278 setOperationAction(ISD::BITREVERSE, VT, Legal);
279 setOperationAction(ISD::BSWAP, VT, Legal);
280 setOperationAction(ISD::SADDSAT, VT, Legal);
281 setOperationAction(ISD::UADDSAT, VT, Legal);
282 setOperationAction(ISD::SSUBSAT, VT, Legal);
283 setOperationAction(ISD::USUBSAT, VT, Legal);
284
285 // No native support for these.
286 setOperationAction(ISD::UDIV, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UREM, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UDIVREM, VT, Expand);
291 setOperationAction(ISD::SDIVREM, VT, Expand);
292 setOperationAction(ISD::CTPOP, VT, Expand);
293 setOperationAction(ISD::SELECT, VT, Expand);
294 setOperationAction(ISD::SELECT_CC, VT, Expand);
295
296 // Vector reductions
297 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
299 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
300 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
301 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
302 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
303 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
304 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
305 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
306
307 if (!HasMVEFP) {
308 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
309 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
310 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
311 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
312 }
313
314 // Pre and Post inc are supported on loads and stores
315 for (unsigned im = (unsigned)ISD::PRE_INC;
316 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
317 setIndexedLoadAction(im, VT, Legal);
318 setIndexedStoreAction(im, VT, Legal);
319 setIndexedMaskedLoadAction(im, VT, Legal);
320 setIndexedMaskedStoreAction(im, VT, Legal);
321 }
322 }
323
324 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
325 for (auto VT : FloatTypes) {
326 addRegisterClass(VT, &ARM::MQPRRegClass);
327 if (!HasMVEFP)
328 setAllExpand(VT);
329
330 // These are legal or custom whether we have MVE.fp or not
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
336 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
337 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
338 setOperationAction(ISD::SETCC, VT, Custom);
339 setOperationAction(ISD::MLOAD, VT, Custom);
340 setOperationAction(ISD::MSTORE, VT, Legal);
341 setOperationAction(ISD::SELECT, VT, Expand);
342 setOperationAction(ISD::SELECT_CC, VT, Expand);
343
344 // Pre and Post inc are supported on loads and stores
345 for (unsigned im = (unsigned)ISD::PRE_INC;
346 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
347 setIndexedLoadAction(im, VT, Legal);
348 setIndexedStoreAction(im, VT, Legal);
349 setIndexedMaskedLoadAction(im, VT, Legal);
350 setIndexedMaskedStoreAction(im, VT, Legal);
351 }
352
353 if (HasMVEFP) {
354 setOperationAction(ISD::FMINNUM, VT, Legal);
355 setOperationAction(ISD::FMAXNUM, VT, Legal);
356 setOperationAction(ISD::FROUND, VT, Legal);
357 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
360 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
361
362 // No native support for these.
363 setOperationAction(ISD::FDIV, VT, Expand);
364 setOperationAction(ISD::FREM, VT, Expand);
365 setOperationAction(ISD::FSQRT, VT, Expand);
366 setOperationAction(ISD::FSIN, VT, Expand);
367 setOperationAction(ISD::FCOS, VT, Expand);
368 setOperationAction(ISD::FPOW, VT, Expand);
369 setOperationAction(ISD::FLOG, VT, Expand);
370 setOperationAction(ISD::FLOG2, VT, Expand);
371 setOperationAction(ISD::FLOG10, VT, Expand);
372 setOperationAction(ISD::FEXP, VT, Expand);
373 setOperationAction(ISD::FEXP2, VT, Expand);
374 setOperationAction(ISD::FNEARBYINT, VT, Expand);
375 }
376 }
377
378 // Custom Expand smaller than legal vector reductions to prevent false zero
379 // items being added.
380 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
387 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
388
389 // We 'support' these types up to bitcast/load/store level, regardless of
390 // MVE integer-only / float support. Only doing FP data processing on the FP
391 // vector types is inhibited at integer-only level.
392 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
393 for (auto VT : LongTypes) {
394 addRegisterClass(VT, &ARM::MQPRRegClass);
395 setAllExpand(VT);
396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
398 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
399 }
400 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
401
402 // We can do bitwise operations on v2i64 vectors
403 setOperationAction(ISD::AND, MVT::v2i64, Legal);
404 setOperationAction(ISD::OR, MVT::v2i64, Legal);
405 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
406
407 // It is legal to extload from v4i8 to v4i16 or v4i32.
408 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
409 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
410 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
411
412 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
418
419 // Some truncating stores are legal too.
420 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
421 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
422 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
423
424 // Pre and Post inc on these are legal, given the correct extends
425 for (unsigned im = (unsigned)ISD::PRE_INC;
426 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
427 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
428 setIndexedLoadAction(im, VT, Legal);
429 setIndexedStoreAction(im, VT, Legal);
430 setIndexedMaskedLoadAction(im, VT, Legal);
431 setIndexedMaskedStoreAction(im, VT, Legal);
432 }
433 }
434
435 // Predicate types
436 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
437 for (auto VT : pTypes) {
438 addRegisterClass(VT, &ARM::VCCRRegClass);
439 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
440 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
442 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
443 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
444 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
445 setOperationAction(ISD::SETCC, VT, Custom);
446 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
447 setOperationAction(ISD::LOAD, VT, Custom);
448 setOperationAction(ISD::STORE, VT, Custom);
449 setOperationAction(ISD::TRUNCATE, VT, Custom);
450 setOperationAction(ISD::VSELECT, VT, Expand);
451 setOperationAction(ISD::SELECT, VT, Expand);
452 }
453}
454
455ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
456 const ARMSubtarget &STI)
457 : TargetLowering(TM), Subtarget(&STI) {
458 RegInfo = Subtarget->getRegisterInfo();
459 Itins = Subtarget->getInstrItineraryData();
460
461 setBooleanContents(ZeroOrOneBooleanContent);
462 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
463
464 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
465 !Subtarget->isTargetWatchOS()) {
466 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
467 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
468 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
469 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
470 : CallingConv::ARM_AAPCS);
471 }
472
473 if (Subtarget->isTargetMachO()) {
474 // Uses VFP for Thumb libfuncs if available.
475 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
476 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
477 static const struct {
478 const RTLIB::Libcall Op;
479 const char * const Name;
480 const ISD::CondCode Cond;
481 } LibraryCalls[] = {
482 // Single-precision floating-point arithmetic.
483 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
484 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
485 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
486 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
487
488 // Double-precision floating-point arithmetic.
489 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
490 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
491 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
492 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
493
494 // Single-precision comparisons.
495 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
496 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
497 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
498 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
499 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
500 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
501 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
502
503 // Double-precision comparisons.
504 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
505 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
506 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
507 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
508 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
509 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
510 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
511
512 // Floating-point to integer conversions.
513 // i64 conversions are done via library routines even when generating VFP
514 // instructions, so use the same ones.
515 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
516 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
517 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
518 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
519
520 // Conversions between floating types.
521 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
522 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
523
524 // Integer to floating-point conversions.
525 // i64 conversions are done via library routines even when generating VFP
526 // instructions, so use the same ones.
527 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
528 // e.g., __floatunsidf vs. __floatunssidfvfp.
529 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
530 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
531 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
532 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
533 };
534
535 for (const auto &LC : LibraryCalls) {
536 setLibcallName(LC.Op, LC.Name);
537 if (LC.Cond != ISD::SETCC_INVALID)
538 setCmpLibcallCC(LC.Op, LC.Cond);
539 }
540 }
541 }
542
543 // These libcalls are not available in 32-bit.
544 setLibcallName(RTLIB::SHL_I128, nullptr);
545 setLibcallName(RTLIB::SRL_I128, nullptr);
546 setLibcallName(RTLIB::SRA_I128, nullptr);
547 setLibcallName(RTLIB::MUL_I128, nullptr);
548
549 // RTLIB
550 if (Subtarget->isAAPCS_ABI() &&
551 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
552 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
553 static const struct {
554 const RTLIB::Libcall Op;
555 const char * const Name;
556 const CallingConv::ID CC;
557 const ISD::CondCode Cond;
558 } LibraryCalls[] = {
559 // Double-precision floating-point arithmetic helper functions
560 // RTABI chapter 4.1.2, Table 2
561 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
562 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
563 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
565
566 // Double-precision floating-point comparison helper functions
567 // RTABI chapter 4.1.2, Table 3
568 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
569 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
570 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
571 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
572 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
573 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
574 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
575
576 // Single-precision floating-point arithmetic helper functions
577 // RTABI chapter 4.1.2, Table 4
578 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
579 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
580 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
582
583 // Single-precision floating-point comparison helper functions
584 // RTABI chapter 4.1.2, Table 5
585 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
586 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
587 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
588 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
589 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
590 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
591 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
592
593 // Floating-point to integer conversions.
594 // RTABI chapter 4.1.2, Table 6
595 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
600 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
601 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603
604 // Conversions between floating types.
605 // RTABI chapter 4.1.2, Table 7
606 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
607 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609
610 // Integer to floating-point conversions.
611 // RTABI chapter 4.1.2, Table 8
612 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
617 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
618 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
619 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
620
621 // Long long helper functions
622 // RTABI chapter 4.2, Table 9
623 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
624 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627
628 // Integer division functions
629 // RTABI chapter 4.3.1
630 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
634 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
635 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638 };
639
640 for (const auto &LC : LibraryCalls) {
641 setLibcallName(LC.Op, LC.Name);
642 setLibcallCallingConv(LC.Op, LC.CC);
643 if (LC.Cond != ISD::SETCC_INVALID)
644 setCmpLibcallCC(LC.Op, LC.Cond);
645 }
646
647 // EABI dependent RTLIB
648 if (TM.Options.EABIVersion == EABI::EABI4 ||
649 TM.Options.EABIVersion == EABI::EABI5) {
650 static const struct {
651 const RTLIB::Libcall Op;
652 const char *const Name;
653 const CallingConv::ID CC;
654 const ISD::CondCode Cond;
655 } MemOpsLibraryCalls[] = {
656 // Memory operations
657 // RTABI chapter 4.3.4
658 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
659 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
660 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 };
662
663 for (const auto &LC : MemOpsLibraryCalls) {
664 setLibcallName(LC.Op, LC.Name);
665 setLibcallCallingConv(LC.Op, LC.CC);
666 if (LC.Cond != ISD::SETCC_INVALID)
667 setCmpLibcallCC(LC.Op, LC.Cond);
668 }
669 }
670 }
671
672 if (Subtarget->isTargetWindows()) {
673 static const struct {
674 const RTLIB::Libcall Op;
675 const char * const Name;
676 const CallingConv::ID CC;
677 } LibraryCalls[] = {
678 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
679 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
680 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
681 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
682 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
683 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
684 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
685 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
686 };
687
688 for (const auto &LC : LibraryCalls) {
689 setLibcallName(LC.Op, LC.Name);
690 setLibcallCallingConv(LC.Op, LC.CC);
691 }
692 }
693
694 // Use divmod compiler-rt calls for iOS 5.0 and later.
695 if (Subtarget->isTargetMachO() &&
696 !(Subtarget->isTargetIOS() &&
697 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
698 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
699 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
700 }
701
702 // The half <-> float conversion functions are always soft-float on
703 // non-watchos platforms, but are needed for some targets which use a
704 // hard-float calling convention by default.
705 if (!Subtarget->isTargetWatchABI()) {
706 if (Subtarget->isAAPCS_ABI()) {
707 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
708 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
709 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
710 } else {
711 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
712 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
713 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
714 }
715 }
716
717 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
718 // a __gnu_ prefix (which is the default).
719 if (Subtarget->isTargetAEABI()) {
720 static const struct {
721 const RTLIB::Libcall Op;
722 const char * const Name;
723 const CallingConv::ID CC;
724 } LibraryCalls[] = {
725 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
726 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
727 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
728 };
729
730 for (const auto &LC : LibraryCalls) {
731 setLibcallName(LC.Op, LC.Name);
732 setLibcallCallingConv(LC.Op, LC.CC);
733 }
734 }
735
736 if (Subtarget->isThumb1Only())
737 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
738 else
739 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
740
741 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
742 Subtarget->hasFPRegs()) {
743 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
744 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
745 if (!Subtarget->hasVFP2Base())
746 setAllExpand(MVT::f32);
747 if (!Subtarget->hasFP64())
748 setAllExpand(MVT::f64);
749 }
750
751 if (Subtarget->hasFullFP16()) {
752 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
753 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
754 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
755
756 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
757 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
758 }
759
760 if (Subtarget->hasBF16()) {
761 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
762 setAllExpand(MVT::bf16);
763 if (!Subtarget->hasFullFP16())
764 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
765 }
766
767 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
768 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
769 setTruncStoreAction(VT, InnerVT, Expand);
770 addAllExtLoads(VT, InnerVT, Expand);
771 }
772
773 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
774 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
775
776 setOperationAction(ISD::BSWAP, VT, Expand);
777 }
778
779 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
780 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
781
782 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
783 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
784
785 if (Subtarget->hasMVEIntegerOps())
786 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
787
788 // Combine low-overhead loop intrinsics so that we can lower i1 types.
789 if (Subtarget->hasLOB()) {
790 setTargetDAGCombine(ISD::BRCOND);
791 setTargetDAGCombine(ISD::BR_CC);
792 }
793
794 if (Subtarget->hasNEON()) {
795 addDRTypeForNEON(MVT::v2f32);
796 addDRTypeForNEON(MVT::v8i8);
797 addDRTypeForNEON(MVT::v4i16);
798 addDRTypeForNEON(MVT::v2i32);
799 addDRTypeForNEON(MVT::v1i64);
800
801 addQRTypeForNEON(MVT::v4f32);
802 addQRTypeForNEON(MVT::v2f64);
803 addQRTypeForNEON(MVT::v16i8);
804 addQRTypeForNEON(MVT::v8i16);
805 addQRTypeForNEON(MVT::v4i32);
806 addQRTypeForNEON(MVT::v2i64);
807
808 if (Subtarget->hasFullFP16()) {
809 addQRTypeForNEON(MVT::v8f16);
810 addDRTypeForNEON(MVT::v4f16);
811 }
812
813 if (Subtarget->hasBF16()) {
814 addQRTypeForNEON(MVT::v8bf16);
815 addDRTypeForNEON(MVT::v4bf16);
816 }
817 }
818
819 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
820 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
821 // none of Neon, MVE or VFP supports any arithmetic operations on it.
822 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
825 // FIXME: Code duplication: FDIV and FREM are expanded always, see
826 // ARMTargetLowering::addTypeForNEON method for details.
827 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
828 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
829 // FIXME: Create unittest.
830 // In another words, find a way when "copysign" appears in DAG with vector
831 // operands.
832 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
833 // FIXME: Code duplication: SETCC has custom operation action, see
834 // ARMTargetLowering::addTypeForNEON method for details.
835 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
836 // FIXME: Create unittest for FNEG and for FABS.
837 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
838 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
839 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
840 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
841 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
842 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
843 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
844 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
845 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
846 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
847 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
848 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
849 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
850 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
851 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
852 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
853 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
854 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
855 }
856
857 if (Subtarget->hasNEON()) {
858 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
859 // supported for v4f32.
860 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
861 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
862 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
863 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
864 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
865 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
866 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
867 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
868 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
869 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
870 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
871 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
872 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
873 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
874
875 // Mark v2f32 intrinsics.
876 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
877 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
878 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
879 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
880 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
881 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
882 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
883 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
884 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
885 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
886 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
887 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
888 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
889 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
890
891 // Neon does not support some operations on v1i64 and v2i64 types.
892 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
893 // Custom handling for some quad-vector types to detect VMULL.
894 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
895 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
896 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
897 // Custom handling for some vector types to avoid expensive expansions
898 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
899 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
900 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
901 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
902 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
903 // a destination type that is wider than the source, and nor does
904 // it have a FP_TO_[SU]INT instruction with a narrower destination than
905 // source.
906 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
907 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
908 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
909 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
910 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
911 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
912 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
913 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
914
915 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
916 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
917
918 // NEON does not have single instruction CTPOP for vectors with element
919 // types wider than 8-bits. However, custom lowering can leverage the
920 // v8i8/v16i8 vcnt instruction.
921 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
922 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
923 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
924 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
925 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
926 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
927
928 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
929 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
930
931 // NEON does not have single instruction CTTZ for vectors.
932 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
933 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
934 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
935 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
936
937 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
938 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
939 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
940 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
941
942 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
943 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
944 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
945 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
946
947 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
948 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
949 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
950 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
951
952 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
953 setOperationAction(ISD::MULHS, VT, Expand);
954 setOperationAction(ISD::MULHU, VT, Expand);
955 }
956
957 // NEON only has FMA instructions as of VFP4.
958 if (!Subtarget->hasVFP4Base()) {
959 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
960 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
961 }
962
963 setTargetDAGCombine(ISD::SHL);
964 setTargetDAGCombine(ISD::SRL);
965 setTargetDAGCombine(ISD::SRA);
966 setTargetDAGCombine(ISD::FP_TO_SINT);
967 setTargetDAGCombine(ISD::FP_TO_UINT);
968 setTargetDAGCombine(ISD::FDIV);
969 setTargetDAGCombine(ISD::LOAD);
970
971 // It is legal to extload from v4i8 to v4i16 or v4i32.
972 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
973 MVT::v2i32}) {
974 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
975 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
976 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
978 }
979 }
980 }
981
982 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
983 setTargetDAGCombine(ISD::BUILD_VECTOR);
984 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
985 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
986 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
987 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
988 setTargetDAGCombine(ISD::STORE);
989 setTargetDAGCombine(ISD::SIGN_EXTEND);
990 setTargetDAGCombine(ISD::ZERO_EXTEND);
991 setTargetDAGCombine(ISD::ANY_EXTEND);
992 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
993 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
994 setTargetDAGCombine(ISD::INTRINSIC_VOID);
995 setTargetDAGCombine(ISD::VECREDUCE_ADD);
996 setTargetDAGCombine(ISD::ADD);
997 setTargetDAGCombine(ISD::BITCAST);
998 }
999 if (Subtarget->hasMVEIntegerOps()) {
1000 setTargetDAGCombine(ISD::SMIN);
1001 setTargetDAGCombine(ISD::UMIN);
1002 setTargetDAGCombine(ISD::SMAX);
1003 setTargetDAGCombine(ISD::UMAX);
1004 setTargetDAGCombine(ISD::FP_EXTEND);
1005 setTargetDAGCombine(ISD::SELECT);
1006 setTargetDAGCombine(ISD::SELECT_CC);
1007 }
1008
1009 if (!Subtarget->hasFP64()) {
1010 // When targeting a floating-point unit with only single-precision
1011 // operations, f64 is legal for the few double-precision instructions which
1012 // are present However, no double-precision operations other than moves,
1013 // loads and stores are provided by the hardware.
1014 setOperationAction(ISD::FADD, MVT::f64, Expand);
1015 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1016 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1017 setOperationAction(ISD::FMA, MVT::f64, Expand);
1018 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1019 setOperationAction(ISD::FREM, MVT::f64, Expand);
1020 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1021 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1022 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1023 setOperationAction(ISD::FABS, MVT::f64, Expand);
1024 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1025 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1026 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1027 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1028 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1029 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1030 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1031 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1032 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1033 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1034 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1035 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1036 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1037 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1038 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1039 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1041 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1042 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1043 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1044 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1045 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1046 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1047 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1048 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1049 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1050 }
1051
1052 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1053 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1054 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1055 if (Subtarget->hasFullFP16()) {
1056 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1057 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1058 }
1059 }
1060
1061 if (!Subtarget->hasFP16()) {
1062 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1063 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1064 }
1065
1066 computeRegisterProperties(Subtarget->getRegisterInfo());
1067
1068 // ARM does not have floating-point extending loads.
1069 for (MVT VT : MVT::fp_valuetypes()) {
1070 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1071 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1072 }
1073
1074 // ... or truncating stores
1075 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1076 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1077 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1078
1079 // ARM does not have i1 sign extending load.
1080 for (MVT VT : MVT::integer_valuetypes())
1081 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1082
1083 // ARM supports all 4 flavors of integer indexed load / store.
1084 if (!Subtarget->isThumb1Only()) {
1085 for (unsigned im = (unsigned)ISD::PRE_INC;
1086 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1087 setIndexedLoadAction(im, MVT::i1, Legal);
1088 setIndexedLoadAction(im, MVT::i8, Legal);
1089 setIndexedLoadAction(im, MVT::i16, Legal);
1090 setIndexedLoadAction(im, MVT::i32, Legal);
1091 setIndexedStoreAction(im, MVT::i1, Legal);
1092 setIndexedStoreAction(im, MVT::i8, Legal);
1093 setIndexedStoreAction(im, MVT::i16, Legal);
1094 setIndexedStoreAction(im, MVT::i32, Legal);
1095 }
1096 } else {
1097 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1098 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1099 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1100 }
1101
1102 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1103 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1104 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1105 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1106
1107 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1108 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1109 if (Subtarget->hasDSP()) {
1110 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1111 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1112 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1113 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1114 }
1115 if (Subtarget->hasBaseDSP()) {
1116 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1117 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1118 }
1119
1120 // i64 operation support.
1121 setOperationAction(ISD::MUL, MVT::i64, Expand);
1122 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1123 if (Subtarget->isThumb1Only()) {
1124 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1125 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1126 }
1127 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1128 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1129 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1130
1131 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1132 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1133 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1134 setOperationAction(ISD::SRL, MVT::i64, Custom);
1135 setOperationAction(ISD::SRA, MVT::i64, Custom);
1136 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1138 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1139 setOperationAction(ISD::STORE, MVT::i64, Custom);
1140
1141 // MVE lowers 64 bit shifts to lsll and lsrl
1142 // assuming that ISD::SRL and SRA of i64 are already marked custom
1143 if (Subtarget->hasMVEIntegerOps())
1144 setOperationAction(ISD::SHL, MVT::i64, Custom);
1145
1146 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1147 if (Subtarget->isThumb1Only()) {
1148 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1149 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1150 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1151 }
1152
1153 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1154 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1155
1156 // ARM does not have ROTL.
1157 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1158 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1159 setOperationAction(ISD::ROTL, VT, Expand);
1160 setOperationAction(ISD::ROTR, VT, Expand);
1161 }
1162 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1163 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1164 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1165 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1166 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1167 }
1168
1169 // @llvm.readcyclecounter requires the Performance Monitors extension.
1170 // Default to the 0 expansion on unsupported platforms.
1171 // FIXME: Technically there are older ARM CPUs that have
1172 // implementation-specific ways of obtaining this information.
1173 if (Subtarget->hasPerfMon())
1174 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1175
1176 // Only ARMv6 has BSWAP.
1177 if (!Subtarget->hasV6Ops())
1178 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1179
1180 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1181 : Subtarget->hasDivideInARMMode();
1182 if (!hasDivide) {
1183 // These are expanded into libcalls if the cpu doesn't have HW divider.
1184 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1185 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1186 }
1187
1188 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1189 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1190 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1191
1192 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1193 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1194 }
1195
1196 setOperationAction(ISD::SREM, MVT::i32, Expand);
1197 setOperationAction(ISD::UREM, MVT::i32, Expand);
1198
1199 // Register based DivRem for AEABI (RTABI 4.2)
1200 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1201 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1202 Subtarget->isTargetWindows()) {
1203 setOperationAction(ISD::SREM, MVT::i64, Custom);
1204 setOperationAction(ISD::UREM, MVT::i64, Custom);
1205 HasStandaloneRem = false;
1206
1207 if (Subtarget->isTargetWindows()) {
1208 const struct {
1209 const RTLIB::Libcall Op;
1210 const char * const Name;
1211 const CallingConv::ID CC;
1212 } LibraryCalls[] = {
1213 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1214 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1215 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1216 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1217
1218 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1219 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1220 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1221 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1222 };
1223
1224 for (const auto &LC : LibraryCalls) {
1225 setLibcallName(LC.Op, LC.Name);
1226 setLibcallCallingConv(LC.Op, LC.CC);
1227 }
1228 } else {
1229 const struct {
1230 const RTLIB::Libcall Op;
1231 const char * const Name;
1232 const CallingConv::ID CC;
1233 } LibraryCalls[] = {
1234 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1235 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1236 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1237 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1238
1239 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1240 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1241 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1242 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1243 };
1244
1245 for (const auto &LC : LibraryCalls) {
1246 setLibcallName(LC.Op, LC.Name);
1247 setLibcallCallingConv(LC.Op, LC.CC);
1248 }
1249 }
1250
1251 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1252 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1253 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1254 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1255 } else {
1256 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1258 }
1259
1260 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1261 // MSVCRT doesn't have powi; fall back to pow
1262 setLibcallName(RTLIB::POWI_F32, nullptr);
1263 setLibcallName(RTLIB::POWI_F64, nullptr);
1264 }
1265
1266 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1267 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1268 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1269 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1270
1271 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1272 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1273
1274 // Use the default implementation.
1275 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1276 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1277 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1278 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1279 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1280 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1281
1282 if (Subtarget->isTargetWindows())
1283 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1284 else
1285 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1286
1287 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1288 // the default expansion.
1289 InsertFencesForAtomic = false;
1290 if (Subtarget->hasAnyDataBarrier() &&
1291 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1292 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1293 // to ldrex/strex loops already.
1294 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1295 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1296 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1297
1298 // On v8, we have particularly efficient implementations of atomic fences
1299 // if they can be combined with nearby atomic loads and stores.
1300 if (!Subtarget->hasAcquireRelease() ||
1301 getTargetMachine().getOptLevel() == 0) {
1302 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1303 InsertFencesForAtomic = true;
1304 }
1305 } else {
1306 // If there's anything we can use as a barrier, go through custom lowering
1307 // for ATOMIC_FENCE.
1308 // If target has DMB in thumb, Fences can be inserted.
1309 if (Subtarget->hasDataBarrier())
1310 InsertFencesForAtomic = true;
1311
1312 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1313 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1314
1315 // Set them all for expansion, which will force libcalls.
1316 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1317 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1318 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1319 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1320 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1321 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1322 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1323 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1324 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1325 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1326 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1327 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1328 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1329 // Unordered/Monotonic case.
1330 if (!InsertFencesForAtomic) {
1331 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1332 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1333 }
1334 }
1335
1336 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1337
1338 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1339 if (!Subtarget->hasV6Ops()) {
1340 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1341 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1342 }
1343 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1344
1345 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1346 !Subtarget->isThumb1Only()) {
1347 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1348 // iff target supports vfp2.
1349 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1350 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1351 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1352 }
1353
1354 // We want to custom lower some of our intrinsics.
1355 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1356 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1357 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1358 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1359 if (Subtarget->useSjLjEH())
1360 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1361
1362 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1363 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1364 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1365 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1366 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1367 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1368 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1369 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1370 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1371 if (Subtarget->hasFullFP16()) {
1372 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1373 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1374 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1375 }
1376
1377 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1378
1379 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1380 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1381 if (Subtarget->hasFullFP16())
1382 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1383 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1384 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1385 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1386
1387 // We don't support sin/cos/fmod/copysign/pow
1388 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1389 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1390 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1391 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1392 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1393 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1394 setOperationAction(ISD::FREM, MVT::f64, Expand);
1395 setOperationAction(ISD::FREM, MVT::f32, Expand);
1396 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1397 !Subtarget->isThumb1Only()) {
1398 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1399 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1400 }
1401 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1402 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1403
1404 if (!Subtarget->hasVFP4Base()) {
1405 setOperationAction(ISD::FMA, MVT::f64, Expand);
1406 setOperationAction(ISD::FMA, MVT::f32, Expand);
1407 }
1408
1409 // Various VFP goodness
1410 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1411 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1412 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1413 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1414 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1415 }
1416
1417 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1418 if (!Subtarget->hasFP16()) {
1419 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1420 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1421 }
1422
1423 // Strict floating-point comparisons need custom lowering.
1424 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1425 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1426 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1427 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1428 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1429 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1430 }
1431
1432 // Use __sincos_stret if available.
1433 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1434 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1435 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1436 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1437 }
1438
1439 // FP-ARMv8 implements a lot of rounding-like FP operations.
1440 if (Subtarget->hasFPARMv8Base()) {
1441 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1442 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1443 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1444 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1445 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1446 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1447 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1448 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1449 if (Subtarget->hasNEON()) {
1450 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1451 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1452 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1453 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1454 }
1455
1456 if (Subtarget->hasFP64()) {
1457 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1458 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1459 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1460 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1461 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1462 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1463 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1464 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1465 }
1466 }
1467
1468 // FP16 often need to be promoted to call lib functions
1469 if (Subtarget->hasFullFP16()) {
1470 setOperationAction(ISD::FREM, MVT::f16, Promote);
1471 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1472 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1473 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1474 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1475 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1476 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1477 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1478 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1479 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1480 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1481 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1482
1483 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1484 }
1485
1486 if (Subtarget->hasNEON()) {
1487 // vmin and vmax aren't available in a scalar form, so we can use
1488 // a NEON instruction with an undef lane instead. This has a performance
1489 // penalty on some cores, so we don't do this unless we have been
1490 // asked to by the core tuning model.
1491 if (Subtarget->useNEONForSinglePrecisionFP()) {
1492 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1493 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1494 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1495 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1496 }
1497 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1498 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1499 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1500 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1501
1502 if (Subtarget->hasFullFP16()) {
1503 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1504 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1505 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1506 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1507
1508 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1509 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1510 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1511 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1512 }
1513 }
1514
1515 // We have target-specific dag combine patterns for the following nodes:
1516 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1517 setTargetDAGCombine(ISD::ADD);
1518 setTargetDAGCombine(ISD::SUB);
1519 setTargetDAGCombine(ISD::MUL);
1520 setTargetDAGCombine(ISD::AND);
1521 setTargetDAGCombine(ISD::OR);
1522 setTargetDAGCombine(ISD::XOR);
1523
1524 if (Subtarget->hasMVEIntegerOps())
1525 setTargetDAGCombine(ISD::VSELECT);
1526
1527 if (Subtarget->hasV6Ops())
1528 setTargetDAGCombine(ISD::SRL);
1529 if (Subtarget->isThumb1Only())
1530 setTargetDAGCombine(ISD::SHL);
1531
1532 setStackPointerRegisterToSaveRestore(ARM::SP);
1533
1534 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1535 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1536 setSchedulingPreference(Sched::RegPressure);
1537 else
1538 setSchedulingPreference(Sched::Hybrid);
1539
1540 //// temporary - rewrite interface to use type
1541 MaxStoresPerMemset = 8;
1542 MaxStoresPerMemsetOptSize = 4;
1543 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1544 MaxStoresPerMemcpyOptSize = 2;
1545 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1546 MaxStoresPerMemmoveOptSize = 2;
1547
1548 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1549 // are at least 4 bytes aligned.
1550 setMinStackArgumentAlignment(Align(4));
1551
1552 // Prefer likely predicted branches to selects on out-of-order cores.
1553 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1554
1555 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1556
1557 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1558
1559 if (Subtarget->isThumb() || Subtarget->isThumb2())
1560 setTargetDAGCombine(ISD::ABS);
1561}
1562
1563bool ARMTargetLowering::useSoftFloat() const {
1564 return Subtarget->useSoftFloat();
1565}
1566
1567// FIXME: It might make sense to define the representative register class as the
1568// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1569// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1570// SPR's representative would be DPR_VFP2. This should work well if register
1571// pressure tracking were modified such that a register use would increment the
1572// pressure of the register class's representative and all of it's super
1573// classes' representatives transitively. We have not implemented this because
1574// of the difficulty prior to coalescing of modeling operand register classes
1575// due to the common occurrence of cross class copies and subregister insertions
1576// and extractions.
1577std::pair<const TargetRegisterClass *, uint8_t>
1578ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1579 MVT VT) const {
1580 const TargetRegisterClass *RRC = nullptr;
1581 uint8_t Cost = 1;
1582 switch (VT.SimpleTy) {
1583 default:
1584 return TargetLowering::findRepresentativeClass(TRI, VT);
1585 // Use DPR as representative register class for all floating point
1586 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1587 // the cost is 1 for both f32 and f64.
1588 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1589 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1590 RRC = &ARM::DPRRegClass;
1591 // When NEON is used for SP, only half of the register file is available
1592 // because operations that define both SP and DP results will be constrained
1593 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1594 // coalescing by double-counting the SP regs. See the FIXME above.
1595 if (Subtarget->useNEONForSinglePrecisionFP())
1596 Cost = 2;
1597 break;
1598 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1599 case MVT::v4f32: case MVT::v2f64:
1600 RRC = &ARM::DPRRegClass;
1601 Cost = 2;
1602 break;
1603 case MVT::v4i64:
1604 RRC = &ARM::DPRRegClass;
1605 Cost = 4;
1606 break;
1607 case MVT::v8i64:
1608 RRC = &ARM::DPRRegClass;
1609 Cost = 8;
1610 break;
1611 }
1612 return std::make_pair(RRC, Cost);
1613}
1614
1615const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1616#define MAKE_CASE(V) \
1617 case V: \
1618 return #V;
1619 switch ((ARMISD::NodeType)Opcode) {
1620 case ARMISD::FIRST_NUMBER:
1621 break;
1622 MAKE_CASE(ARMISD::Wrapper)
1623 MAKE_CASE(ARMISD::WrapperPIC)
1624 MAKE_CASE(ARMISD::WrapperJT)
1625 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1626 MAKE_CASE(ARMISD::CALL)
1627 MAKE_CASE(ARMISD::CALL_PRED)
1628 MAKE_CASE(ARMISD::CALL_NOLINK)
1629 MAKE_CASE(ARMISD::tSECALL)
1630 MAKE_CASE(ARMISD::BRCOND)
1631 MAKE_CASE(ARMISD::BR_JT)
1632 MAKE_CASE(ARMISD::BR2_JT)
1633 MAKE_CASE(ARMISD::RET_FLAG)
1634 MAKE_CASE(ARMISD::SERET_FLAG)
1635 MAKE_CASE(ARMISD::INTRET_FLAG)
1636 MAKE_CASE(ARMISD::PIC_ADD)
1637 MAKE_CASE(ARMISD::CMP)
1638 MAKE_CASE(ARMISD::CMN)
1639 MAKE_CASE(ARMISD::CMPZ)
1640 MAKE_CASE(ARMISD::CMPFP)
1641 MAKE_CASE(ARMISD::CMPFPE)
1642 MAKE_CASE(ARMISD::CMPFPw0)
1643 MAKE_CASE(ARMISD::CMPFPEw0)
1644 MAKE_CASE(ARMISD::BCC_i64)
1645 MAKE_CASE(ARMISD::FMSTAT)
1646 MAKE_CASE(ARMISD::CMOV)
1647 MAKE_CASE(ARMISD::SUBS)
1648 MAKE_CASE(ARMISD::SSAT)
1649 MAKE_CASE(ARMISD::USAT)
1650 MAKE_CASE(ARMISD::ASRL)
1651 MAKE_CASE(ARMISD::LSRL)
1652 MAKE_CASE(ARMISD::LSLL)
1653 MAKE_CASE(ARMISD::SRL_FLAG)
1654 MAKE_CASE(ARMISD::SRA_FLAG)
1655 MAKE_CASE(ARMISD::RRX)
1656 MAKE_CASE(ARMISD::ADDC)
1657 MAKE_CASE(ARMISD::ADDE)
1658 MAKE_CASE(ARMISD::SUBC)
1659 MAKE_CASE(ARMISD::SUBE)
1660 MAKE_CASE(ARMISD::LSLS)
1661 MAKE_CASE(ARMISD::VMOVRRD)
1662 MAKE_CASE(ARMISD::VMOVDRR)
1663 MAKE_CASE(ARMISD::VMOVhr)
1664 MAKE_CASE(ARMISD::VMOVrh)
1665 MAKE_CASE(ARMISD::VMOVSR)
1666 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1667 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1668 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1669 MAKE_CASE(ARMISD::TC_RETURN)
1670 MAKE_CASE(ARMISD::THREAD_POINTER)
1671 MAKE_CASE(ARMISD::DYN_ALLOC)
1672 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1673 MAKE_CASE(ARMISD::PRELOAD)
1674 MAKE_CASE(ARMISD::LDRD)
1675 MAKE_CASE(ARMISD::STRD)
1676 MAKE_CASE(ARMISD::WIN__CHKSTK)
1677 MAKE_CASE(ARMISD::WIN__DBZCHK)
1678 MAKE_CASE(ARMISD::PREDICATE_CAST)
1679 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1680 MAKE_CASE(ARMISD::VCMP)
1681 MAKE_CASE(ARMISD::VCMPZ)
1682 MAKE_CASE(ARMISD::VTST)
1683 MAKE_CASE(ARMISD::VSHLs)
1684 MAKE_CASE(ARMISD::VSHLu)
1685 MAKE_CASE(ARMISD::VSHLIMM)
1686 MAKE_CASE(ARMISD::VSHRsIMM)
1687 MAKE_CASE(ARMISD::VSHRuIMM)
1688 MAKE_CASE(ARMISD::VRSHRsIMM)
1689 MAKE_CASE(ARMISD::VRSHRuIMM)
1690 MAKE_CASE(ARMISD::VRSHRNIMM)
1691 MAKE_CASE(ARMISD::VQSHLsIMM)
1692 MAKE_CASE(ARMISD::VQSHLuIMM)
1693 MAKE_CASE(ARMISD::VQSHLsuIMM)
1694 MAKE_CASE(ARMISD::VQSHRNsIMM)
1695 MAKE_CASE(ARMISD::VQSHRNuIMM)
1696 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1697 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1698 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1699 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1700 MAKE_CASE(ARMISD::VSLIIMM)
1701 MAKE_CASE(ARMISD::VSRIIMM)
1702 MAKE_CASE(ARMISD::VGETLANEu)
1703 MAKE_CASE(ARMISD::VGETLANEs)
1704 MAKE_CASE(ARMISD::VMOVIMM)
1705 MAKE_CASE(ARMISD::VMVNIMM)
1706 MAKE_CASE(ARMISD::VMOVFPIMM)
1707 MAKE_CASE(ARMISD::VDUP)
1708 MAKE_CASE(ARMISD::VDUPLANE)
1709 MAKE_CASE(ARMISD::VEXT)
1710 MAKE_CASE(ARMISD::VREV64)
1711 MAKE_CASE(ARMISD::VREV32)
1712 MAKE_CASE(ARMISD::VREV16)
1713 MAKE_CASE(ARMISD::VZIP)
1714 MAKE_CASE(ARMISD::VUZP)
1715 MAKE_CASE(ARMISD::VTRN)
1716 MAKE_CASE(ARMISD::VTBL1)
1717 MAKE_CASE(ARMISD::VTBL2)
1718 MAKE_CASE(ARMISD::VMOVN)
1719 MAKE_CASE(ARMISD::VQMOVNs)
1720 MAKE_CASE(ARMISD::VQMOVNu)
1721 MAKE_CASE(ARMISD::VCVTN)
1722 MAKE_CASE(ARMISD::VCVTL)
1723 MAKE_CASE(ARMISD::VIDUP)
1724 MAKE_CASE(ARMISD::VMULLs)
1725 MAKE_CASE(ARMISD::VMULLu)
1726 MAKE_CASE(ARMISD::VQDMULH)
1727 MAKE_CASE(ARMISD::VADDVs)
1728 MAKE_CASE(ARMISD::VADDVu)
1729 MAKE_CASE(ARMISD::VADDVps)
1730 MAKE_CASE(ARMISD::VADDVpu)
1731 MAKE_CASE(ARMISD::VADDLVs)
1732 MAKE_CASE(ARMISD::VADDLVu)
1733 MAKE_CASE(ARMISD::VADDLVAs)
1734 MAKE_CASE(ARMISD::VADDLVAu)
1735 MAKE_CASE(ARMISD::VADDLVps)
1736 MAKE_CASE(ARMISD::VADDLVpu)
1737 MAKE_CASE(ARMISD::VADDLVAps)
1738 MAKE_CASE(ARMISD::VADDLVApu)
1739 MAKE_CASE(ARMISD::VMLAVs)
1740 MAKE_CASE(ARMISD::VMLAVu)
1741 MAKE_CASE(ARMISD::VMLAVps)
1742 MAKE_CASE(ARMISD::VMLAVpu)
1743 MAKE_CASE(ARMISD::VMLALVs)
1744 MAKE_CASE(ARMISD::VMLALVu)
1745 MAKE_CASE(ARMISD::VMLALVps)
1746 MAKE_CASE(ARMISD::VMLALVpu)
1747 MAKE_CASE(ARMISD::VMLALVAs)
1748 MAKE_CASE(ARMISD::VMLALVAu)
1749 MAKE_CASE(ARMISD::VMLALVAps)
1750 MAKE_CASE(ARMISD::VMLALVApu)
1751 MAKE_CASE(ARMISD::VMINVu)
1752 MAKE_CASE(ARMISD::VMINVs)
1753 MAKE_CASE(ARMISD::VMAXVu)
1754 MAKE_CASE(ARMISD::VMAXVs)
1755 MAKE_CASE(ARMISD::UMAAL)
1756 MAKE_CASE(ARMISD::UMLAL)
1757 MAKE_CASE(ARMISD::SMLAL)
1758 MAKE_CASE(ARMISD::SMLALBB)
1759 MAKE_CASE(ARMISD::SMLALBT)
1760 MAKE_CASE(ARMISD::SMLALTB)
1761 MAKE_CASE(ARMISD::SMLALTT)
1762 MAKE_CASE(ARMISD::SMULWB)
1763 MAKE_CASE(ARMISD::SMULWT)
1764 MAKE_CASE(ARMISD::SMLALD)
1765 MAKE_CASE(ARMISD::SMLALDX)
1766 MAKE_CASE(ARMISD::SMLSLD)
1767 MAKE_CASE(ARMISD::SMLSLDX)
1768 MAKE_CASE(ARMISD::SMMLAR)
1769 MAKE_CASE(ARMISD::SMMLSR)
1770 MAKE_CASE(ARMISD::QADD16b)
1771 MAKE_CASE(ARMISD::QSUB16b)
1772 MAKE_CASE(ARMISD::QADD8b)
1773 MAKE_CASE(ARMISD::QSUB8b)
1774 MAKE_CASE(ARMISD::BUILD_VECTOR)
1775 MAKE_CASE(ARMISD::BFI)
1776 MAKE_CASE(ARMISD::VORRIMM)
1777 MAKE_CASE(ARMISD::VBICIMM)
1778 MAKE_CASE(ARMISD::VBSP)
1779 MAKE_CASE(ARMISD::MEMCPY)
1780 MAKE_CASE(ARMISD::VLD1DUP)
1781 MAKE_CASE(ARMISD::VLD2DUP)
1782 MAKE_CASE(ARMISD::VLD3DUP)
1783 MAKE_CASE(ARMISD::VLD4DUP)
1784 MAKE_CASE(ARMISD::VLD1_UPD)
1785 MAKE_CASE(ARMISD::VLD2_UPD)
1786 MAKE_CASE(ARMISD::VLD3_UPD)
1787 MAKE_CASE(ARMISD::VLD4_UPD)
1788 MAKE_CASE(ARMISD::VLD1x2_UPD)
1789 MAKE_CASE(ARMISD::VLD1x3_UPD)
1790 MAKE_CASE(ARMISD::VLD1x4_UPD)
1791 MAKE_CASE(ARMISD::VLD2LN_UPD)
1792 MAKE_CASE(ARMISD::VLD3LN_UPD)
1793 MAKE_CASE(ARMISD::VLD4LN_UPD)
1794 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1795 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1796 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1797 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1798 MAKE_CASE(ARMISD::VST1_UPD)
1799 MAKE_CASE(ARMISD::VST2_UPD)
1800 MAKE_CASE(ARMISD::VST3_UPD)
1801 MAKE_CASE(ARMISD::VST4_UPD)
1802 MAKE_CASE(ARMISD::VST1x2_UPD)
1803 MAKE_CASE(ARMISD::VST1x3_UPD)
1804 MAKE_CASE(ARMISD::VST1x4_UPD)
1805 MAKE_CASE(ARMISD::VST2LN_UPD)
1806 MAKE_CASE(ARMISD::VST3LN_UPD)
1807 MAKE_CASE(ARMISD::VST4LN_UPD)
1808 MAKE_CASE(ARMISD::WLS)
1809 MAKE_CASE(ARMISD::WLSSETUP)
1810 MAKE_CASE(ARMISD::LE)
1811 MAKE_CASE(ARMISD::LOOP_DEC)
1812 MAKE_CASE(ARMISD::CSINV)
1813 MAKE_CASE(ARMISD::CSNEG)
1814 MAKE_CASE(ARMISD::CSINC)
1815 MAKE_CASE(ARMISD::MEMCPYLOOP)
1816 MAKE_CASE(ARMISD::MEMSETLOOP)
1817#undef MAKE_CASE
1818 }
1819 return nullptr;
1820}
1821
1822EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1823 EVT VT) const {
1824 if (!VT.isVector())
1825 return getPointerTy(DL);
1826
1827 // MVE has a predicate register.
1828 if (Subtarget->hasMVEIntegerOps() &&
1829 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1830 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1831 return VT.changeVectorElementTypeToInteger();
1832}
1833
1834/// getRegClassFor - Return the register class that should be used for the
1835/// specified value type.
1836const TargetRegisterClass *
1837ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1838 (void)isDivergent;
1839 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1840 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1841 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1842 // MVE Q registers.
1843 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1844 if (VT == MVT::v4i64)
1845 return &ARM::QQPRRegClass;
1846 if (VT == MVT::v8i64)
1847 return &ARM::QQQQPRRegClass;
1848 }
1849 return TargetLowering::getRegClassFor(VT);
1850}
1851
1852// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1853// source/dest is aligned and the copy size is large enough. We therefore want
1854// to align such objects passed to memory intrinsics.
1855bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1856 unsigned &PrefAlign) const {
1857 if (!isa<MemIntrinsic>(CI))
1858 return false;
1859 MinSize = 8;
1860 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1861 // cycle faster than 4-byte aligned LDM.
1862 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1863 return true;
1864}
1865
1866// Create a fast isel object.
1867FastISel *
1868ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1869 const TargetLibraryInfo *libInfo) const {
1870 return ARM::createFastISel(funcInfo, libInfo);
1871}
1872
1873Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1874 unsigned NumVals = N->getNumValues();
1875 if (!NumVals)
1876 return Sched::RegPressure;
1877
1878 for (unsigned i = 0; i != NumVals; ++i) {
1879 EVT VT = N->getValueType(i);
1880 if (VT == MVT::Glue || VT == MVT::Other)
1881 continue;
1882 if (VT.isFloatingPoint() || VT.isVector())
1883 return Sched::ILP;
1884 }
1885
1886 if (!N->isMachineOpcode())
1887 return Sched::RegPressure;
1888
1889 // Load are scheduled for latency even if there instruction itinerary
1890 // is not available.
1891 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1892 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1893
1894 if (MCID.getNumDefs() == 0)
1895 return Sched::RegPressure;
1896 if (!Itins->isEmpty() &&
1897 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1898 return Sched::ILP;
1899
1900 return Sched::RegPressure;
1901}
1902
1903//===----------------------------------------------------------------------===//
1904// Lowering Code
1905//===----------------------------------------------------------------------===//
1906
1907static bool isSRL16(const SDValue &Op) {
1908 if (Op.getOpcode() != ISD::SRL)
1909 return false;
1910 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1911 return Const->getZExtValue() == 16;
1912 return false;
1913}
1914
1915static bool isSRA16(const SDValue &Op) {
1916 if (Op.getOpcode() != ISD::SRA)
1917 return false;
1918 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1919 return Const->getZExtValue() == 16;
1920 return false;
1921}
1922
1923static bool isSHL16(const SDValue &Op) {
1924 if (Op.getOpcode() != ISD::SHL)
1925 return false;
1926 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1927 return Const->getZExtValue() == 16;
1928 return false;
1929}
1930
1931// Check for a signed 16-bit value. We special case SRA because it makes it
1932// more simple when also looking for SRAs that aren't sign extending a
1933// smaller value. Without the check, we'd need to take extra care with
1934// checking order for some operations.
1935static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1936 if (isSRA16(Op))
1937 return isSHL16(Op.getOperand(0));
1938 return DAG.ComputeNumSignBits(Op) == 17;
1939}
1940
1941/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1942static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1943 switch (CC) {
1944 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1944)
;
1945 case ISD::SETNE: return ARMCC::NE;
1946 case ISD::SETEQ: return ARMCC::EQ;
1947 case ISD::SETGT: return ARMCC::GT;
1948 case ISD::SETGE: return ARMCC::GE;
1949 case ISD::SETLT: return ARMCC::LT;
1950 case ISD::SETLE: return ARMCC::LE;
1951 case ISD::SETUGT: return ARMCC::HI;
1952 case ISD::SETUGE: return ARMCC::HS;
1953 case ISD::SETULT: return ARMCC::LO;
1954 case ISD::SETULE: return ARMCC::LS;
1955 }
1956}
1957
1958/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1959static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1960 ARMCC::CondCodes &CondCode2) {
1961 CondCode2 = ARMCC::AL;
1962 switch (CC) {
1963 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1963)
;
1964 case ISD::SETEQ:
1965 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1966 case ISD::SETGT:
1967 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1968 case ISD::SETGE:
1969 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1970 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1971 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1972 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1973 case ISD::SETO: CondCode = ARMCC::VC; break;
1974 case ISD::SETUO: CondCode = ARMCC::VS; break;
1975 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1976 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1977 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1978 case ISD::SETLT:
1979 case ISD::SETULT: CondCode = ARMCC::LT; break;
1980 case ISD::SETLE:
1981 case ISD::SETULE: CondCode = ARMCC::LE; break;
1982 case ISD::SETNE:
1983 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1984 }
1985}
1986
1987//===----------------------------------------------------------------------===//
1988// Calling Convention Implementation
1989//===----------------------------------------------------------------------===//
1990
1991/// getEffectiveCallingConv - Get the effective calling convention, taking into
1992/// account presence of floating point hardware and calling convention
1993/// limitations, such as support for variadic functions.
1994CallingConv::ID
1995ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1996 bool isVarArg) const {
1997 switch (CC) {
1998 default:
1999 report_fatal_error("Unsupported calling convention");
2000 case CallingConv::ARM_AAPCS:
2001 case CallingConv::ARM_APCS:
2002 case CallingConv::GHC:
2003 case CallingConv::CFGuard_Check:
2004 return CC;
2005 case CallingConv::PreserveMost:
2006 return CallingConv::PreserveMost;
2007 case CallingConv::ARM_AAPCS_VFP:
2008 case CallingConv::Swift:
2009 case CallingConv::SwiftTail:
2010 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2011 case CallingConv::C:
2012 case CallingConv::Tail:
2013 if (!Subtarget->isAAPCS_ABI())
2014 return CallingConv::ARM_APCS;
2015 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2016 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2017 !isVarArg)
2018 return CallingConv::ARM_AAPCS_VFP;
2019 else
2020 return CallingConv::ARM_AAPCS;
2021 case CallingConv::Fast:
2022 case CallingConv::CXX_FAST_TLS:
2023 if (!Subtarget->isAAPCS_ABI()) {
2024 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2025 return CallingConv::Fast;
2026 return CallingConv::ARM_APCS;
2027 } else if (Subtarget->hasVFP2Base() &&
2028 !Subtarget->isThumb1Only() && !isVarArg)
2029 return CallingConv::ARM_AAPCS_VFP;
2030 else
2031 return CallingConv::ARM_AAPCS;
2032 }
2033}
2034
2035CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2036 bool isVarArg) const {
2037 return CCAssignFnForNode(CC, false, isVarArg);
2038}
2039
2040CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2041 bool isVarArg) const {
2042 return CCAssignFnForNode(CC, true, isVarArg);
2043}
2044
2045/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2046/// CallingConvention.
2047CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2048 bool Return,
2049 bool isVarArg) const {
2050 switch (getEffectiveCallingConv(CC, isVarArg)) {
2051 default:
2052 report_fatal_error("Unsupported calling convention");
2053 case CallingConv::ARM_APCS:
2054 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2055 case CallingConv::ARM_AAPCS:
2056 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2057 case CallingConv::ARM_AAPCS_VFP:
2058 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2059 case CallingConv::Fast:
2060 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2061 case CallingConv::GHC:
2062 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2063 case CallingConv::PreserveMost:
2064 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2065 case CallingConv::CFGuard_Check:
2066 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2067 }
2068}
2069
2070SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2071 MVT LocVT, MVT ValVT, SDValue Val) const {
2072 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2073 Val);
2074 if (Subtarget->hasFullFP16()) {
2075 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2076 } else {
2077 Val = DAG.getNode(ISD::TRUNCATE, dl,
2078 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2079 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2080 }
2081 return Val;
2082}
2083
2084SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2085 MVT LocVT, MVT ValVT,
2086 SDValue Val) const {
2087 if (Subtarget->hasFullFP16()) {
2088 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2089 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2090 } else {
2091 Val = DAG.getNode(ISD::BITCAST, dl,
2092 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2093 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2094 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2095 }
2096 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2097}
2098
2099/// LowerCallResult - Lower the result values of a call into the
2100/// appropriate copies out of appropriate physical registers.
2101SDValue ARMTargetLowering::LowerCallResult(
2102 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2103 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2104 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2105 SDValue ThisVal) const {
2106 // Assign locations to each value returned by this call.
2107 SmallVector<CCValAssign, 16> RVLocs;
2108 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2109 *DAG.getContext());
2110 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2111
2112 // Copy all of the result registers out of their specified physreg.
2113 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2114 CCValAssign VA = RVLocs[i];
2115
2116 // Pass 'this' value directly from the argument to return value, to avoid
2117 // reg unit interference
2118 if (i == 0 && isThisReturn) {
2119 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2120, __extension__ __PRETTY_FUNCTION__))
2120 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2120, __extension__ __PRETTY_FUNCTION__))
;
2121 InVals.push_back(ThisVal);
2122 continue;
2123 }
2124
2125 SDValue Val;
2126 if (VA.needsCustom() &&
2127 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2128 // Handle f64 or half of a v2f64.
2129 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2130 InFlag);
2131 Chain = Lo.getValue(1);
2132 InFlag = Lo.getValue(2);
2133 VA = RVLocs[++i]; // skip ahead to next loc
2134 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2135 InFlag);
2136 Chain = Hi.getValue(1);
2137 InFlag = Hi.getValue(2);
2138 if (!Subtarget->isLittle())
2139 std::swap (Lo, Hi);
2140 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2141
2142 if (VA.getLocVT() == MVT::v2f64) {
2143 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2144 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2145 DAG.getConstant(0, dl, MVT::i32));
2146
2147 VA = RVLocs[++i]; // skip ahead to next loc
2148 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2149 Chain = Lo.getValue(1);
2150 InFlag = Lo.getValue(2);
2151 VA = RVLocs[++i]; // skip ahead to next loc
2152 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2153 Chain = Hi.getValue(1);
2154 InFlag = Hi.getValue(2);
2155 if (!Subtarget->isLittle())
2156 std::swap (Lo, Hi);
2157 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2158 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2159 DAG.getConstant(1, dl, MVT::i32));
2160 }
2161 } else {
2162 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2163 InFlag);
2164 Chain = Val.getValue(1);
2165 InFlag = Val.getValue(2);
2166 }
2167
2168 switch (VA.getLocInfo()) {
2169 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2169)
;
2170 case CCValAssign::Full: break;
2171 case CCValAssign::BCvt:
2172 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2173 break;
2174 }
2175
2176 // f16 arguments have their size extended to 4 bytes and passed as if they
2177 // had been copied to the LSBs of a 32-bit register.
2178 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2179 if (VA.needsCustom() &&
2180 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2181 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2182
2183 InVals.push_back(Val);
2184 }
2185
2186 return Chain;
2187}
2188
2189std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2190 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2191 bool IsTailCall, int SPDiff) const {
2192 SDValue DstAddr;
2193 MachinePointerInfo DstInfo;
2194 int32_t Offset = VA.getLocMemOffset();
2195 MachineFunction &MF = DAG.getMachineFunction();
2196
2197 if (IsTailCall) {
2198 Offset += SPDiff;
2199 auto PtrVT = getPointerTy(DAG.getDataLayout());
2200 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2201 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2202 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2203 DstInfo =
2204 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2205 } else {
2206 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2207 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2208 StackPtr, PtrOff);
2209 DstInfo =
2210 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2211 }
2212
2213 return std::make_pair(DstAddr, DstInfo);
2214}
2215
2216void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2217 SDValue Chain, SDValue &Arg,
2218 RegsToPassVector &RegsToPass,
2219 CCValAssign &VA, CCValAssign &NextVA,
2220 SDValue &StackPtr,
2221 SmallVectorImpl<SDValue> &MemOpChains,
2222 bool IsTailCall,
2223 int SPDiff) const {
2224 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2225 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2226 unsigned id = Subtarget->isLittle() ? 0 : 1;
2227 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2228
2229 if (NextVA.isRegLoc())
2230 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2231 else {
2232 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2232, __extension__ __PRETTY_FUNCTION__))
;
2233 if (!StackPtr.getNode())
2234 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2235 getPointerTy(DAG.getDataLayout()));
2236
2237 SDValue DstAddr;
2238 MachinePointerInfo DstInfo;
2239 std::tie(DstAddr, DstInfo) =
2240 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2241 MemOpChains.push_back(
2242 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2243 }
2244}
2245
2246static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2247 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2248 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2249}
2250
2251/// LowerCall - Lowering a call into a callseq_start <-
2252/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2253/// nodes.
2254SDValue
2255ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2256 SmallVectorImpl<SDValue> &InVals) const {
2257 SelectionDAG &DAG = CLI.DAG;
2258 SDLoc &dl = CLI.DL;
2259 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2260 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2261 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2262 SDValue Chain = CLI.Chain;
2263 SDValue Callee = CLI.Callee;
2264 bool &isTailCall = CLI.IsTailCall;
2265 CallingConv::ID CallConv = CLI.CallConv;
2266 bool doesNotRet = CLI.DoesNotReturn;
2267 bool isVarArg = CLI.IsVarArg;
2268
2269 MachineFunction &MF = DAG.getMachineFunction();
2270 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2271 MachineFunction::CallSiteInfo CSInfo;
2272 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2273 bool isThisReturn = false;
2274 bool isCmseNSCall = false;
2275 bool isSibCall = false;
2276 bool PreferIndirect = false;
2277
2278 // Determine whether this is a non-secure function call.
2279 if (CLI.CB && CLI.CB->getAttributes().hasFnAttribute("cmse_nonsecure_call"))
2
Assuming field 'CB' is null
3
Taking false branch
2280 isCmseNSCall = true;
2281
2282 // Disable tail calls if they're not supported.
2283 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
5
Taking false branch
2284 isTailCall = false;
2285
2286 // For both the non-secure calls and the returns from a CMSE entry function,
2287 // the function needs to do some extra work afte r the call, or before the
2288 // return, respectively, thus it cannot end with atail call
2289 if (isCmseNSCall
5.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
6
Assuming the condition is false
7
Taking false branch
2290 isTailCall = false;
2291
2292 if (isa<GlobalAddressSDNode>(Callee)) {
8
Assuming 'Callee' is not a 'GlobalAddressSDNode'
9
Taking false branch
2293 // If we're optimizing for minimum size and the function is called three or
2294 // more times in this block, we can improve codesize by calling indirectly
2295 // as BLXr has a 16-bit encoding.
2296 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2297 if (CLI.CB) {
2298 auto *BB = CLI.CB->getParent();
2299 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2300 count_if(GV->users(), [&BB](const User *U) {
2301 return isa<Instruction>(U) &&
2302 cast<Instruction>(U)->getParent() == BB;
2303 }) > 2;
2304 }
2305 }
2306 if (isTailCall) {
10
Assuming 'isTailCall' is false
11
Taking false branch
2307 // Check if it's really possible to do a tail call.
2308 isTailCall = IsEligibleForTailCallOptimization(
2309 Callee, CallConv, isVarArg, isStructRet,
2310 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2311 PreferIndirect);
2312
2313 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2314 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2315 isSibCall = true;
2316
2317 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2318 // detected sibcalls.
2319 if (isTailCall)
2320 ++NumTailCalls;
2321 }
2322
2323 if (!isTailCall
11.1
'isTailCall' is false
&& CLI.CB
11.2
Field 'CB' is null
&& CLI.CB->isMustTailCall())
2324 report_fatal_error("failed to perform tail call elimination on a call "
2325 "site marked musttail");
2326 // Analyze operands of the call, assigning locations to each operand.
2327 SmallVector<CCValAssign, 16> ArgLocs;
2328 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2329 *DAG.getContext());
2330 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2331
2332 // Get a count of how many bytes are to be pushed on the stack.
2333 unsigned NumBytes = CCInfo.getNextStackOffset();
2334
2335 // SPDiff is the byte offset of the call's argument area from the callee's.
2336 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2337 // by this amount for a tail call. In a sibling call it must be 0 because the
2338 // caller will deallocate the entire stack and the callee still expects its
2339 // arguments to begin at SP+0. Completely unused for non-tail calls.
2340 int SPDiff = 0;
2341
2342 if (isTailCall && !isSibCall) {
12
Assuming 'isTailCall' is false
2343 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2344 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2345
2346 // Since callee will pop argument stack as a tail call, we must keep the
2347 // popped size 16-byte aligned.
2348 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2349 NumBytes = alignTo(NumBytes, StackAlign);
2350
2351 // SPDiff will be negative if this tail call requires more space than we
2352 // would automatically have in our incoming argument space. Positive if we
2353 // can actually shrink the stack.
2354 SPDiff = NumReusableBytes - NumBytes;
2355
2356 // If this call requires more stack than we have available from
2357 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2358 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2359 AFI->setArgRegsSaveSize(-SPDiff);
2360 }
2361
2362 if (isSibCall
12.1
'isSibCall' is false
) {
13
Taking false branch
2363 // For sibling tail calls, memory operands are available in our caller's stack.
2364 NumBytes = 0;
2365 } else {
2366 // Adjust the stack pointer for the new arguments...
2367 // These operations are automatically eliminated by the prolog/epilog pass
2368 Chain = DAG.getCALLSEQ_START(Chain, isTailCall
13.1
'isTailCall' is false
? 0 : NumBytes, 0, dl);
14
'?' condition is false
2369 }
2370
2371 SDValue StackPtr =
2372 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2373
2374 RegsToPassVector RegsToPass;
2375 SmallVector<SDValue, 8> MemOpChains;
2376
2377 // During a tail call, stores to the argument area must happen after all of
2378 // the function's incoming arguments have been loaded because they may alias.
2379 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2380 // there's no point in doing so repeatedly so this tracks whether that's
2381 // happened yet.
2382 bool AfterFormalArgLoads = false;
2383
2384 // Walk the register/memloc assignments, inserting copies/loads. In the case
2385 // of tail call optimization, arguments are handled later.
2386 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
16
Loop condition is false. Execution continues on line 2540
2387 i != e;
15
Assuming 'i' is equal to 'e'
2388 ++i, ++realArgIdx) {
2389 CCValAssign &VA = ArgLocs[i];
2390 SDValue Arg = OutVals[realArgIdx];
2391 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2392 bool isByVal = Flags.isByVal();
2393
2394 // Promote the value if needed.
2395 switch (VA.getLocInfo()) {
2396 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2396)
;
2397 case CCValAssign::Full: break;
2398 case CCValAssign::SExt:
2399 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2400 break;
2401 case CCValAssign::ZExt:
2402 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2403 break;
2404 case CCValAssign::AExt:
2405 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2406 break;
2407 case CCValAssign::BCvt:
2408 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2409 break;
2410 }
2411
2412 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2413 Chain = DAG.getStackArgumentTokenFactor(Chain);
2414 AfterFormalArgLoads = true;
2415 }
2416
2417 // f16 arguments have their size extended to 4 bytes and passed as if they
2418 // had been copied to the LSBs of a 32-bit register.
2419 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2420 if (VA.needsCustom() &&
2421 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2422 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2423 } else {
2424 // f16 arguments could have been extended prior to argument lowering.
2425 // Mask them arguments if this is a CMSE nonsecure call.
2426 auto ArgVT = Outs[realArgIdx].ArgVT;
2427 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2428 auto LocBits = VA.getLocVT().getSizeInBits();
2429 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2430 SDValue Mask =
2431 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2432 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2433 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2434 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2435 }
2436 }
2437
2438 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2439 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2440 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2441 DAG.getConstant(0, dl, MVT::i32));
2442 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2443 DAG.getConstant(1, dl, MVT::i32));
2444
2445 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2446 StackPtr, MemOpChains, isTailCall, SPDiff);
2447
2448 VA = ArgLocs[++i]; // skip ahead to next loc
2449 if (VA.isRegLoc()) {
2450 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2451 StackPtr, MemOpChains, isTailCall, SPDiff);
2452 } else {
2453 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2453, __extension__ __PRETTY_FUNCTION__))
;
2454 SDValue DstAddr;
2455 MachinePointerInfo DstInfo;
2456 std::tie(DstAddr, DstInfo) =
2457 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2458 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2459 }
2460 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2461 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2462 StackPtr, MemOpChains, isTailCall, SPDiff);
2463 } else if (VA.isRegLoc()) {
2464 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2465 Outs[0].VT == MVT::i32) {
2466 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2467, __extension__ __PRETTY_FUNCTION__))
2467 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2467, __extension__ __PRETTY_FUNCTION__))
;
2468 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2469, __extension__ __PRETTY_FUNCTION__))
2469 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2469, __extension__ __PRETTY_FUNCTION__))
;
2470 isThisReturn = true;
2471 }
2472 const TargetOptions &Options = DAG.getTarget().Options;
2473 if (Options.EmitCallSiteInfo)
2474 CSInfo.emplace_back(VA.getLocReg(), i);
2475 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2476 } else if (isByVal) {
2477 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2477, __extension__ __PRETTY_FUNCTION__))
;
2478 unsigned offset = 0;
2479
2480 // True if this byval aggregate will be split between registers
2481 // and memory.
2482 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2483 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2484
2485 if (CurByValIdx < ByValArgsCount) {
2486
2487 unsigned RegBegin, RegEnd;
2488 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2489
2490 EVT PtrVT =
2491 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2492 unsigned int i, j;
2493 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2494 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2495 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2496 SDValue Load =
2497 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2498 DAG.InferPtrAlign(AddArg));
2499 MemOpChains.push_back(Load.getValue(1));
2500 RegsToPass.push_back(std::make_pair(j, Load));
2501 }
2502
2503 // If parameter size outsides register area, "offset" value
2504 // helps us to calculate stack slot for remained part properly.
2505 offset = RegEnd - RegBegin;
2506
2507 CCInfo.nextInRegsParam();
2508 }
2509
2510 if (Flags.getByValSize() > 4*offset) {
2511 auto PtrVT = getPointerTy(DAG.getDataLayout());
2512 SDValue Dst;
2513 MachinePointerInfo DstInfo;
2514 std::tie(Dst, DstInfo) =
2515 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2516 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2517 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2518 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2519 MVT::i32);
2520 SDValue AlignNode =
2521 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2522
2523 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2524 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2525 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2526 Ops));
2527 }
2528 } else {
2529 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2529, __extension__ __PRETTY_FUNCTION__))
;
2530 SDValue DstAddr;
2531 MachinePointerInfo DstInfo;
2532 std::tie(DstAddr, DstInfo) =
2533 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2534
2535 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2536 MemOpChains.push_back(Store);
2537 }
2538 }
2539
2540 if (!MemOpChains.empty())
17
Taking false branch
2541 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2542
2543 // Build a sequence of copy-to-reg nodes chained together with token chain
2544 // and flag operands which copy the outgoing args into the appropriate regs.
2545 SDValue InFlag;
2546 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
18
Assuming 'i' is equal to 'e'
19
Loop condition is false. Execution continues on line 2555
2547 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2548 RegsToPass[i].second, InFlag);
2549 InFlag = Chain.getValue(1);
2550 }
2551
2552 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2553 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2554 // node so that legalize doesn't hack it.
2555 bool isDirect = false;
2556
2557 const TargetMachine &TM = getTargetMachine();
2558 const Module *Mod = MF.getFunction().getParent();
2559 const GlobalValue *GV = nullptr;
20
'GV' initialized to a null pointer value
2560 if (GlobalAddressSDNode *G
20.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
21
Taking false branch
2561 GV = G->getGlobal();
2562 bool isStub =
2563 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
22
Assuming the condition is false
2564
2565 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
23
Assuming the condition is true
2566 bool isLocalARMFunc = false;
2567 auto PtrVt = getPointerTy(DAG.getDataLayout());
2568
2569 if (Subtarget->genLongCalls()) {
24
Assuming the condition is false
25
Taking false branch
2570 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2571, __extension__ __PRETTY_FUNCTION__))
2571 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2571, __extension__ __PRETTY_FUNCTION__))
;
2572 // Handle a global address or an external symbol. If it's not one of
2573 // those, the target's already in a register, so we don't need to do
2574 // anything extra.
2575 if (isa<GlobalAddressSDNode>(Callee)) {
2576 // Create a constant pool entry for the callee address
2577 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2578 ARMConstantPoolValue *CPV =
2579 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2580
2581 // Get the address of the callee into a register
2582 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2583 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2584 Callee = DAG.getLoad(
2585 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2586 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2587 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2588 const char *Sym = S->getSymbol();
2589
2590 // Create a constant pool entry for the callee address
2591 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2592 ARMConstantPoolValue *CPV =
2593 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2594 ARMPCLabelIndex, 0);
2595 // Get the address of the callee into a register
2596 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2597 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2598 Callee = DAG.getLoad(
2599 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2600 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2601 }
2602 } else if (isa<GlobalAddressSDNode>(Callee)) {
26
Assuming 'Callee' is a 'GlobalAddressSDNode'
27
Taking true branch
2603 if (!PreferIndirect
27.1
'PreferIndirect' is false
) {
28
Taking true branch
2604 isDirect = true;
2605 bool isDef = GV->isStrongDefinitionForLinker();
29
Called C++ object pointer is null
2606
2607 // ARM call to a local ARM function is predicable.
2608 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2609 // tBX takes a register source operand.
2610 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2611 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2611, __extension__ __PRETTY_FUNCTION__))
;
2612 Callee = DAG.getNode(
2613 ARMISD::WrapperPIC, dl, PtrVt,
2614 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2615 Callee = DAG.getLoad(
2616 PtrVt, dl, DAG.getEntryNode(), Callee,
2617 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2618 MachineMemOperand::MODereferenceable |
2619 MachineMemOperand::MOInvariant);
2620 } else if (Subtarget->isTargetCOFF()) {
2621 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2622, __extension__ __PRETTY_FUNCTION__))
2622 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2622, __extension__ __PRETTY_FUNCTION__))
;
2623 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2624 if (GV->hasDLLImportStorageClass())
2625 TargetFlags = ARMII::MO_DLLIMPORT;
2626 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2627 TargetFlags = ARMII::MO_COFFSTUB;
2628 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2629 TargetFlags);
2630 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2631 Callee =
2632 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2633 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2634 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2635 } else {
2636 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2637 }
2638 }
2639 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2640 isDirect = true;
2641 // tBX takes a register source operand.
2642 const char *Sym = S->getSymbol();
2643 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2644 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2645 ARMConstantPoolValue *CPV =
2646 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2647 ARMPCLabelIndex, 4);
2648 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2649 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2650 Callee = DAG.getLoad(
2651 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2652 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2653 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2654 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2655 } else {
2656 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2657 }
2658 }
2659
2660 if (isCmseNSCall) {
2661 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2662, __extension__ __PRETTY_FUNCTION__))
2662 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2662, __extension__ __PRETTY_FUNCTION__))
;
2663 if (NumBytes > 0) {
2664 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2665 "call to non-secure function would "
2666 "require passing arguments on stack",
2667 dl.getDebugLoc());
2668 DAG.getContext()->diagnose(Diag);
2669 }
2670 if (isStructRet) {
2671 DiagnosticInfoUnsupported Diag(
2672 DAG.getMachineFunction().getFunction(),
2673 "call to non-secure function would return value through pointer",
2674 dl.getDebugLoc());
2675 DAG.getContext()->diagnose(Diag);
2676 }
2677 }
2678
2679 // FIXME: handle tail calls differently.
2680 unsigned CallOpc;
2681 if (Subtarget->isThumb()) {
2682 if (isCmseNSCall)
2683 CallOpc = ARMISD::tSECALL;
2684 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2685 CallOpc = ARMISD::CALL_NOLINK;
2686 else
2687 CallOpc = ARMISD::CALL;
2688 } else {
2689 if (!isDirect && !Subtarget->hasV5TOps())
2690 CallOpc = ARMISD::CALL_NOLINK;
2691 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2692 // Emit regular call when code size is the priority
2693 !Subtarget->hasMinSize())
2694 // "mov lr, pc; b _foo" to avoid confusing the RSP
2695 CallOpc = ARMISD::CALL_NOLINK;
2696 else
2697 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2698 }
2699
2700 // We don't usually want to end the call-sequence here because we would tidy
2701 // the frame up *after* the call, however in the ABI-changing tail-call case
2702 // we've carefully laid out the parameters so that when sp is reset they'll be
2703 // in the correct location.
2704 if (isTailCall && !isSibCall) {
2705 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
2706 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2707 InFlag = Chain.getValue(1);
2708 }
2709
2710 std::vector<SDValue> Ops;
2711 Ops.push_back(Chain);
2712 Ops.push_back(Callee);
2713
2714 if (isTailCall) {
2715 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2716 }
2717
2718 // Add argument registers to the end of the list so that they are known live
2719 // into the call.
2720 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2721 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2722 RegsToPass[i].second.getValueType()));
2723
2724 // Add a register mask operand representing the call-preserved registers.
2725 if (!isTailCall) {
2726 const uint32_t *Mask;
2727 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2728 if (isThisReturn) {
2729 // For 'this' returns, use the R0-preserving mask if applicable
2730 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2731 if (!Mask) {
2732 // Set isThisReturn to false if the calling convention is not one that
2733 // allows 'returned' to be modeled in this way, so LowerCallResult does
2734 // not try to pass 'this' straight through
2735 isThisReturn = false;
2736 Mask = ARI->getCallPreservedMask(MF, CallConv);
2737 }
2738 } else
2739 Mask = ARI->getCallPreservedMask(MF, CallConv);
2740
2741 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2741, __extension__ __PRETTY_FUNCTION__))
;
2742 Ops.push_back(DAG.getRegisterMask(Mask));
2743 }
2744
2745 if (InFlag.getNode())
2746 Ops.push_back(InFlag);
2747
2748 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2749 if (isTailCall) {
2750 MF.getFrameInfo().setHasTailCall();
2751 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2752 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2753 return Ret;
2754 }
2755
2756 // Returns a chain and a flag for retval copy to use.
2757 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2758 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2759 InFlag = Chain.getValue(1);
2760 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2761
2762 // If we're guaranteeing tail-calls will be honoured, the callee must
2763 // pop its own argument stack on return. But this call is *not* a tail call so
2764 // we need to undo that after it returns to restore the status-quo.
2765 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2766 uint64_t CalleePopBytes =
2767 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2768
2769 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2770 DAG.getIntPtrConstant(CalleePopBytes, dl, true),
2771 InFlag, dl);
2772 if (!Ins.empty())
2773 InFlag = Chain.getValue(1);
2774
2775 // Handle result values, copying them out of physregs into vregs that we
2776 // return.
2777 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2778 InVals, isThisReturn,
2779 isThisReturn ? OutVals[0] : SDValue());
2780}
2781
2782/// HandleByVal - Every parameter *after* a byval parameter is passed
2783/// on the stack. Remember the next parameter register to allocate,
2784/// and then confiscate the rest of the parameter registers to insure
2785/// this.
2786void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2787 Align Alignment) const {
2788 // Byval (as with any stack) slots are always at least 4 byte aligned.
2789 Alignment = std::max(Alignment, Align(4));
2790
2791 unsigned Reg = State->AllocateReg(GPRArgRegs);
2792 if (!Reg)
2793 return;
2794
2795 unsigned AlignInRegs = Alignment.value() / 4;
2796 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2797 for (unsigned i = 0; i < Waste; ++i)
2798 Reg = State->AllocateReg(GPRArgRegs);
2799
2800 if (!Reg)
2801 return;
2802
2803 unsigned Excess = 4 * (ARM::R4 - Reg);
2804
2805 // Special case when NSAA != SP and parameter size greater than size of
2806 // all remained GPR regs. In that case we can't split parameter, we must
2807 // send it to stack. We also must set NCRN to R4, so waste all
2808 // remained registers.
2809 const unsigned NSAAOffset = State->getNextStackOffset();
2810 if (NSAAOffset != 0 && Size > Excess) {
2811 while (State->AllocateReg(GPRArgRegs))
2812 ;
2813 return;
2814 }
2815
2816 // First register for byval parameter is the first register that wasn't
2817 // allocated before this method call, so it would be "reg".
2818 // If parameter is small enough to be saved in range [reg, r4), then
2819 // the end (first after last) register would be reg + param-size-in-regs,
2820 // else parameter would be splitted between registers and stack,
2821 // end register would be r4 in this case.
2822 unsigned ByValRegBegin = Reg;
2823 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2824 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2825 // Note, first register is allocated in the beginning of function already,
2826 // allocate remained amount of registers we need.
2827 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2828 State->AllocateReg(GPRArgRegs);
2829 // A byval parameter that is split between registers and memory needs its
2830 // size truncated here.
2831 // In the case where the entire structure fits in registers, we set the
2832 // size in memory to zero.
2833 Size = std::max<int>(Size - Excess, 0);
2834}
2835
2836/// MatchingStackOffset - Return true if the given stack call argument is
2837/// already available in the same position (relatively) of the caller's
2838/// incoming argument stack.
2839static
2840bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2841 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2842 const TargetInstrInfo *TII) {
2843 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2844 int FI = std::numeric_limits<int>::max();
2845 if (Arg.getOpcode() == ISD::CopyFromReg) {
2846 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2847 if (!Register::isVirtualRegister(VR))
2848 return false;
2849 MachineInstr *Def = MRI->getVRegDef(VR);
2850 if (!Def)
2851 return false;
2852 if (!Flags.isByVal()) {
2853 if (!TII->isLoadFromStackSlot(*Def, FI))
2854 return false;
2855 } else {
2856 return false;
2857 }
2858 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2859 if (Flags.isByVal())
2860 // ByVal argument is passed in as a pointer but it's now being
2861 // dereferenced. e.g.
2862 // define @foo(%struct.X* %A) {
2863 // tail call @bar(%struct.X* byval %A)
2864 // }
2865 return false;
2866 SDValue Ptr = Ld->getBasePtr();
2867 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2868 if (!FINode)
2869 return false;
2870 FI = FINode->getIndex();
2871 } else
2872 return false;
2873
2874 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2874, __extension__ __PRETTY_FUNCTION__))
;
2875 if (!MFI.isFixedObjectIndex(FI))
2876 return false;
2877 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2878}
2879
2880/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2881/// for tail call optimization. Targets which want to do tail call
2882/// optimization should implement this function.
2883bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2884 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2885 bool isCalleeStructRet, bool isCallerStructRet,
2886 const SmallVectorImpl<ISD::OutputArg> &Outs,
2887 const SmallVectorImpl<SDValue> &OutVals,
2888 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2889 const bool isIndirect) const {
2890 MachineFunction &MF = DAG.getMachineFunction();
2891 const Function &CallerF = MF.getFunction();
2892 CallingConv::ID CallerCC = CallerF.getCallingConv();
2893
2894 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2894, __extension__ __PRETTY_FUNCTION__))
;
2895
2896 // Indirect tail calls cannot be optimized for Thumb1 if the args
2897 // to the call take up r0-r3. The reason is that there are no legal registers
2898 // left to hold the pointer to the function to be called.
2899 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2900 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2901 return false;
2902
2903 // Look for obvious safe cases to perform tail call optimization that do not
2904 // require ABI changes. This is what gcc calls sibcall.
2905
2906 // Exception-handling functions need a special set of instructions to indicate
2907 // a return to the hardware. Tail-calling another function would probably
2908 // break this.
2909 if (CallerF.hasFnAttribute("interrupt"))
2910 return false;
2911
2912 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2913 return CalleeCC == CallerCC;
2914
2915 // Also avoid sibcall optimization if either caller or callee uses struct
2916 // return semantics.
2917 if (isCalleeStructRet || isCallerStructRet)
2918 return false;
2919
2920 // Externally-defined functions with weak linkage should not be
2921 // tail-called on ARM when the OS does not support dynamic
2922 // pre-emption of symbols, as the AAELF spec requires normal calls
2923 // to undefined weak functions to be replaced with a NOP or jump to the
2924 // next instruction. The behaviour of branch instructions in this
2925 // situation (as used for tail calls) is implementation-defined, so we
2926 // cannot rely on the linker replacing the tail call with a return.
2927 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2928 const GlobalValue *GV = G->getGlobal();
2929 const Triple &TT = getTargetMachine().getTargetTriple();
2930 if (GV->hasExternalWeakLinkage() &&
2931 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2932 return false;
2933 }
2934
2935 // Check that the call results are passed in the same way.
2936 LLVMContext &C = *DAG.getContext();
2937 if (!CCState::resultsCompatible(
2938 getEffectiveCallingConv(CalleeCC, isVarArg),
2939 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2940 CCAssignFnForReturn(CalleeCC, isVarArg),
2941 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2942 return false;
2943 // The callee has to preserve all registers the caller needs to preserve.
2944 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2945 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2946 if (CalleeCC != CallerCC) {
2947 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2948 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2949 return false;
2950 }
2951
2952 // If Caller's vararg or byval argument has been split between registers and
2953 // stack, do not perform tail call, since part of the argument is in caller's
2954 // local frame.
2955 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2956 if (AFI_Caller->getArgRegsSaveSize())
2957 return false;
2958
2959 // If the callee takes no arguments then go on to check the results of the
2960 // call.
2961 if (!Outs.empty()) {
2962 // Check if stack adjustment is needed. For now, do not do this if any
2963 // argument is passed on the stack.
2964 SmallVector<CCValAssign, 16> ArgLocs;
2965 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2966 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2967 if (CCInfo.getNextStackOffset()) {
2968 // Check if the arguments are already laid out in the right way as
2969 // the caller's fixed stack objects.
2970 MachineFrameInfo &MFI = MF.getFrameInfo();
2971 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2972 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2973 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2974 i != e;
2975 ++i, ++realArgIdx) {
2976 CCValAssign &VA = ArgLocs[i];
2977 EVT RegVT = VA.getLocVT();
2978 SDValue Arg = OutVals[realArgIdx];
2979 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2980 if (VA.getLocInfo() == CCValAssign::Indirect)
2981 return false;
2982 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2983 // f64 and vector types are split into multiple registers or
2984 // register/stack-slot combinations. The types will not match
2985 // the registers; give up on memory f64 refs until we figure
2986 // out what to do about this.
2987 if (!VA.isRegLoc())
2988 return false;
2989 if (!ArgLocs[++i].isRegLoc())
2990 return false;
2991 if (RegVT == MVT::v2f64) {
2992 if (!ArgLocs[++i].isRegLoc())
2993 return false;
2994 if (!ArgLocs[++i].isRegLoc())
2995 return false;
2996 }
2997 } else if (!VA.isRegLoc()) {
2998 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2999 MFI, MRI, TII))
3000 return false;
3001 }
3002 }
3003 }
3004
3005 const MachineRegisterInfo &MRI = MF.getRegInfo();
3006 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3007 return false;
3008 }
3009
3010 return true;
3011}
3012
3013bool
3014ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3015 MachineFunction &MF, bool isVarArg,
3016 const SmallVectorImpl<ISD::OutputArg> &Outs,
3017 LLVMContext &Context) const {
3018 SmallVector<CCValAssign, 16> RVLocs;
3019 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3020 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3021}
3022
3023static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3024 const SDLoc &DL, SelectionDAG &DAG) {
3025 const MachineFunction &MF = DAG.getMachineFunction();
3026 const Function &F = MF.getFunction();
3027
3028 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3029
3030 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3031 // version of the "preferred return address". These offsets affect the return
3032 // instruction if this is a return from PL1 without hypervisor extensions.
3033 // IRQ/FIQ: +4 "subs pc, lr, #4"
3034 // SWI: 0 "subs pc, lr, #0"
3035 // ABORT: +4 "subs pc, lr, #4"
3036 // UNDEF: +4/+2 "subs pc, lr, #0"
3037 // UNDEF varies depending on where the exception came from ARM or Thumb
3038 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3039
3040 int64_t LROffset;
3041 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3042 IntKind == "ABORT")
3043 LROffset = 4;
3044 else if (IntKind == "SWI" || IntKind == "UNDEF")
3045 LROffset = 0;
3046 else
3047 report_fatal_error("Unsupported interrupt attribute. If present, value "
3048 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3049
3050 RetOps.insert(RetOps.begin() + 1,
3051 DAG.getConstant(LROffset, DL, MVT::i32, false));
3052
3053 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3054}
3055
3056SDValue
3057ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3058 bool isVarArg,
3059 const SmallVectorImpl<ISD::OutputArg> &Outs,
3060 const SmallVectorImpl<SDValue> &OutVals,
3061 const SDLoc &dl, SelectionDAG &DAG) const {
3062 // CCValAssign - represent the assignment of the return value to a location.
3063 SmallVector<CCValAssign, 16> RVLocs;
3064
3065 // CCState - Info about the registers and stack slots.
3066 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3067 *DAG.getContext());
3068
3069 // Analyze outgoing return values.
3070 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3071
3072 SDValue Flag;
3073 SmallVector<SDValue, 4> RetOps;
3074 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3075 bool isLittleEndian = Subtarget->isLittle();
3076
3077 MachineFunction &MF = DAG.getMachineFunction();
3078 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3079 AFI->setReturnRegsCount(RVLocs.size());
3080
3081 // Report error if cmse entry function returns structure through first ptr arg.
3082 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3083 // Note: using an empty SDLoc(), as the first line of the function is a
3084 // better place to report than the last line.
3085 DiagnosticInfoUnsupported Diag(
3086 DAG.getMachineFunction().getFunction(),
3087 "secure entry function would return value through pointer",
3088 SDLoc().getDebugLoc());
3089 DAG.getContext()->diagnose(Diag);
3090 }
3091
3092 // Copy the result values into the output registers.
3093 for (unsigned i = 0, realRVLocIdx = 0;
3094 i != RVLocs.size();
3095 ++i, ++realRVLocIdx) {
3096 CCValAssign &VA = RVLocs[i];
3097 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3097, __extension__ __PRETTY_FUNCTION__))
;
3098
3099 SDValue Arg = OutVals[realRVLocIdx];
3100 bool ReturnF16 = false;
3101
3102 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3103 // Half-precision return values can be returned like this:
3104 //
3105 // t11 f16 = fadd ...
3106 // t12: i16 = bitcast t11
3107 // t13: i32 = zero_extend t12
3108 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3109 //
3110 // to avoid code generation for bitcasts, we simply set Arg to the node
3111 // that produces the f16 value, t11 in this case.
3112 //
3113 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3114 SDValue ZE = Arg.getOperand(0);
3115 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3116 SDValue BC = ZE.getOperand(0);
3117 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3118 Arg = BC.getOperand(0);
3119 ReturnF16 = true;
3120 }
3121 }
3122 }
3123 }
3124
3125 switch (VA.getLocInfo()) {
3126 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3126)
;
3127 case CCValAssign::Full: break;
3128 case CCValAssign::BCvt:
3129 if (!ReturnF16)
3130 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3131 break;
3132 }
3133
3134 // Mask f16 arguments if this is a CMSE nonsecure entry.
3135 auto RetVT = Outs[realRVLocIdx].ArgVT;
3136 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3137 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3138 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3139 } else {
3140 auto LocBits = VA.getLocVT().getSizeInBits();
3141 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3142 SDValue Mask =
3143 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3144 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3145 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3146 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3147 }
3148 }
3149
3150 if (VA.needsCustom() &&
3151 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3152 if (VA.getLocVT() == MVT::v2f64) {
3153 // Extract the first half and return it in two registers.
3154 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3155 DAG.getConstant(0, dl, MVT::i32));
3156 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3157 DAG.getVTList(MVT::i32, MVT::i32), Half);
3158
3159 Chain =
3160 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3161 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3162 Flag = Chain.getValue(1);
3163 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3164 VA = RVLocs[++i]; // skip ahead to next loc
3165 Chain =
3166 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3167 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3168 Flag = Chain.getValue(1);
3169 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3170 VA = RVLocs[++i]; // skip ahead to next loc
3171
3172 // Extract the 2nd half and fall through to handle it as an f64 value.
3173 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3174 DAG.getConstant(1, dl, MVT::i32));
3175 }
3176 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3177 // available.
3178 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3179 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3180 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3181 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3182 Flag = Chain.getValue(1);
3183 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3184 VA = RVLocs[++i]; // skip ahead to next loc
3185 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3186 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3187 } else
3188 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3189
3190 // Guarantee that all emitted copies are
3191 // stuck together, avoiding something bad.
3192 Flag = Chain.getValue(1);
3193 RetOps.push_back(DAG.getRegister(
3194 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3195 }
3196 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3197 const MCPhysReg *I =
3198 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3199 if (I) {
3200 for (; *I; ++I) {
3201 if (ARM::GPRRegClass.contains(*I))
3202 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3203 else if (ARM::DPRRegClass.contains(*I))
3204 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3205 else
3206 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3206)
;
3207 }
3208 }
3209
3210 // Update chain and glue.
3211 RetOps[0] = Chain;
3212 if (Flag.getNode())
3213 RetOps.push_back(Flag);
3214
3215 // CPUs which aren't M-class use a special sequence to return from
3216 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3217 // though we use "subs pc, lr, #N").
3218 //
3219 // M-class CPUs actually use a normal return sequence with a special
3220 // (hardware-provided) value in LR, so the normal code path works.
3221 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3222 !Subtarget->isMClass()) {
3223 if (Subtarget->isThumb1Only())
3224 report_fatal_error("interrupt attribute is not supported in Thumb1");
3225 return LowerInterruptReturn(RetOps, dl, DAG);
3226 }
3227
3228 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3229 ARMISD::RET_FLAG;
3230 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3231}
3232
3233bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3234 if (N->getNumValues() != 1)
3235 return false;
3236 if (!N->hasNUsesOfValue(1, 0))
3237 return false;
3238
3239 SDValue TCChain = Chain;
3240 SDNode *Copy = *N->use_begin();
3241 if (Copy->getOpcode() == ISD::CopyToReg) {
3242 // If the copy has a glue operand, we conservatively assume it isn't safe to
3243 // perform a tail call.
3244 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3245 return false;
3246 TCChain = Copy->getOperand(0);
3247 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3248 SDNode *VMov = Copy;
3249 // f64 returned in a pair of GPRs.
3250 SmallPtrSet<SDNode*, 2> Copies;
3251 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3252 UI != UE; ++UI) {
3253 if (UI->getOpcode() != ISD::CopyToReg)
3254 return false;
3255 Copies.insert(*UI);
3256 }
3257 if (Copies.size() > 2)
3258 return false;
3259
3260 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3261 UI != UE; ++UI) {
3262 SDValue UseChain = UI->getOperand(0);
3263 if (Copies.count(UseChain.getNode()))
3264 // Second CopyToReg
3265 Copy = *UI;
3266 else {
3267 // We are at the top of this chain.
3268 // If the copy has a glue operand, we conservatively assume it
3269 // isn't safe to perform a tail call.
3270 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3271 return false;
3272 // First CopyToReg
3273 TCChain = UseChain;
3274 }
3275 }
3276 } else if (Copy->getOpcode() == ISD::BITCAST) {
3277 // f32 returned in a single GPR.
3278 if (!Copy->hasOneUse())
3279 return false;
3280 Copy = *Copy->use_begin();
3281 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3282 return false;
3283 // If the copy has a glue operand, we conservatively assume it isn't safe to
3284 // perform a tail call.
3285 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3286 return false;
3287 TCChain = Copy->getOperand(0);
3288 } else {
3289 return false;
3290 }
3291
3292 bool HasRet = false;
3293 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3294 UI != UE; ++UI) {
3295 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3296 UI->getOpcode() != ARMISD::INTRET_FLAG)
3297 return false;
3298 HasRet = true;
3299 }
3300
3301 if (!HasRet)
3302 return false;
3303
3304 Chain = TCChain;
3305 return true;
3306}
3307
3308bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3309 if (!Subtarget->supportsTailCall())
3310 return false;
3311
3312 if (!CI->isTailCall())
3313 return false;
3314
3315 return true;
3316}
3317
3318// Trying to write a 64 bit value so need to split into two 32 bit values first,
3319// and pass the lower and high parts through.
3320static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3321 SDLoc DL(Op);
3322 SDValue WriteValue = Op->getOperand(2);
3323
3324 // This function is only supposed to be called for i64 type argument.
3325 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3326, __extension__ __PRETTY_FUNCTION__))
3326 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3326, __extension__ __PRETTY_FUNCTION__))
;
3327
3328 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3329 DAG.getConstant(0, DL, MVT::i32));
3330 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3331 DAG.getConstant(1, DL, MVT::i32));
3332 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3333 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3334}
3335
3336// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3337// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3338// one of the above mentioned nodes. It has to be wrapped because otherwise
3339// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3340// be used to form addressing mode. These wrapped nodes will be selected
3341// into MOVi.
3342SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3343 SelectionDAG &DAG) const {
3344 EVT PtrVT = Op.getValueType();
3345 // FIXME there is no actual debug info here
3346 SDLoc dl(Op);
3347 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3348 SDValue Res;
3349
3350 // When generating execute-only code Constant Pools must be promoted to the
3351 // global data section. It's a bit ugly that we can't share them across basic
3352 // blocks, but this way we guarantee that execute-only behaves correct with
3353 // position-independent addressing modes.
3354 if (Subtarget->genExecuteOnly()) {
3355 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3356 auto T = const_cast<Type*>(CP->getType());
3357 auto C = const_cast<Constant*>(CP->getConstVal());
3358 auto M = const_cast<Module*>(DAG.getMachineFunction().
3359 getFunction().getParent());
3360 auto GV = new GlobalVariable(
3361 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3362 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3363 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3364 Twine(AFI->createPICLabelUId())
3365 );
3366 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3367 dl, PtrVT);
3368 return LowerGlobalAddress(GA, DAG);
3369 }
3370
3371 if (CP->isMachineConstantPoolEntry())
3372 Res =
3373 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3374 else
3375 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3376 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3377}
3378
3379unsigned ARMTargetLowering::getJumpTableEncoding() const {
3380 return MachineJumpTableInfo::EK_Inline;
3381}
3382
3383SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3384 SelectionDAG &DAG) const {
3385 MachineFunction &MF = DAG.getMachineFunction();
3386 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3387 unsigned ARMPCLabelIndex = 0;
3388 SDLoc DL(Op);
3389 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3390 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3391 SDValue CPAddr;
3392 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3393 if (!IsPositionIndependent) {
3394 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3395 } else {
3396 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3397 ARMPCLabelIndex = AFI->createPICLabelUId();
3398 ARMConstantPoolValue *CPV =
3399 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3400 ARMCP::CPBlockAddress, PCAdj);
3401 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3402 }
3403 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3404 SDValue Result = DAG.getLoad(
3405 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3406 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3407 if (!IsPositionIndependent)
3408 return Result;
3409 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3410 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3411}
3412
3413/// Convert a TLS address reference into the correct sequence of loads
3414/// and calls to compute the variable's address for Darwin, and return an
3415/// SDValue containing the final node.
3416
3417/// Darwin only has one TLS scheme which must be capable of dealing with the
3418/// fully general situation, in the worst case. This means:
3419/// + "extern __thread" declaration.
3420/// + Defined in a possibly unknown dynamic library.
3421///
3422/// The general system is that each __thread variable has a [3 x i32] descriptor
3423/// which contains information used by the runtime to calculate the address. The
3424/// only part of this the compiler needs to know about is the first word, which
3425/// contains a function pointer that must be called with the address of the
3426/// entire descriptor in "r0".
3427///
3428/// Since this descriptor may be in a different unit, in general access must
3429/// proceed along the usual ARM rules. A common sequence to produce is:
3430///
3431/// movw rT1, :lower16:_var$non_lazy_ptr
3432/// movt rT1, :upper16:_var$non_lazy_ptr
3433/// ldr r0, [rT1]
3434/// ldr rT2, [r0]
3435/// blx rT2
3436/// [...address now in r0...]
3437SDValue
3438ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3439 SelectionDAG &DAG) const {
3440 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3441, __extension__ __PRETTY_FUNCTION__))
3441 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3441, __extension__ __PRETTY_FUNCTION__))
;
3442 SDLoc DL(Op);
3443
3444 // First step is to get the address of the actua global symbol. This is where
3445 // the TLS descriptor lives.
3446 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3447
3448 // The first entry in the descriptor is a function pointer that we must call
3449 // to obtain the address of the variable.
3450 SDValue Chain = DAG.getEntryNode();
3451 SDValue FuncTLVGet = DAG.getLoad(
3452 MVT::i32, DL, Chain, DescAddr,
3453 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3454 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3455 MachineMemOperand::MOInvariant);
3456 Chain = FuncTLVGet.getValue(1);
3457
3458 MachineFunction &F = DAG.getMachineFunction();
3459 MachineFrameInfo &MFI = F.getFrameInfo();
3460 MFI.setAdjustsStack(true);
3461
3462 // TLS calls preserve all registers except those that absolutely must be
3463 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3464 // silly).
3465 auto TRI =
3466 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3467 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3468 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3469
3470 // Finally, we can make the call. This is just a degenerate version of a
3471 // normal AArch64 call node: r0 takes the address of the descriptor, and
3472 // returns the address of the variable in this thread.
3473 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3474 Chain =
3475 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3476 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3477 DAG.getRegisterMask(Mask), Chain.getValue(1));
3478 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3479}
3480
3481SDValue
3482ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3483 SelectionDAG &DAG) const {
3484 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3484, __extension__ __PRETTY_FUNCTION__))
;
3485
3486 SDValue Chain = DAG.getEntryNode();
3487 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3488 SDLoc DL(Op);
3489
3490 // Load the current TEB (thread environment block)
3491 SDValue Ops[] = {Chain,
3492 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3493 DAG.getTargetConstant(15, DL, MVT::i32),
3494 DAG.getTargetConstant(0, DL, MVT::i32),
3495 DAG.getTargetConstant(13, DL, MVT::i32),
3496 DAG.getTargetConstant(0, DL, MVT::i32),
3497 DAG.getTargetConstant(2, DL, MVT::i32)};
3498 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3499 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3500
3501 SDValue TEB = CurrentTEB.getValue(0);
3502 Chain = CurrentTEB.getValue(1);
3503
3504 // Load the ThreadLocalStoragePointer from the TEB
3505 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3506 SDValue TLSArray =
3507 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3508 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3509
3510 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3511 // offset into the TLSArray.
3512
3513 // Load the TLS index from the C runtime
3514 SDValue TLSIndex =
3515 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3516 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3517 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3518
3519 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3520 DAG.getConstant(2, DL, MVT::i32));
3521 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3522 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3523 MachinePointerInfo());
3524
3525 // Get the offset of the start of the .tls section (section base)
3526 const auto *GA = cast<GlobalAddressSDNode>(Op);
3527 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3528 SDValue Offset = DAG.getLoad(
3529 PtrVT, DL, Chain,
3530 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3531 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3532 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3533
3534 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3535}
3536
3537// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3538SDValue
3539ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3540 SelectionDAG &DAG) const {
3541 SDLoc dl(GA);
3542 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3543 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3544 MachineFunction &MF = DAG.getMachineFunction();
3545 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3546 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3547 ARMConstantPoolValue *CPV =
3548 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3549 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3550 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3551 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3552 Argument = DAG.getLoad(
3553 PtrVT, dl, DAG.getEntryNode(), Argument,
3554 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3555 SDValue Chain = Argument.getValue(1);
3556
3557 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3558 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3559
3560 // call __tls_get_addr.
3561 ArgListTy Args;
3562 ArgListEntry Entry;
3563 Entry.Node = Argument;
3564 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3565 Args.push_back(Entry);
3566
3567 // FIXME: is there useful debug info available here?
3568 TargetLowering::CallLoweringInfo CLI(DAG);
3569 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3570 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3571 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3572
3573 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3574 return CallResult.first;
3575}
3576
3577// Lower ISD::GlobalTLSAddress using the "initial exec" or
3578// "local exec" model.
3579SDValue
3580ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3581 SelectionDAG &DAG,
3582 TLSModel::Model model) const {
3583 const GlobalValue *GV = GA->getGlobal();
3584 SDLoc dl(GA);
3585 SDValue Offset;
3586 SDValue Chain = DAG.getEntryNode();
3587 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3588 // Get the Thread Pointer
3589 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3590
3591 if (model == TLSModel::InitialExec) {
3592 MachineFunction &MF = DAG.getMachineFunction();
3593 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3594 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3595 // Initial exec model.
3596 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3597 ARMConstantPoolValue *CPV =
3598 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3599 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3600 true);
3601 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3602 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3603 Offset = DAG.getLoad(
3604 PtrVT, dl, Chain, Offset,
3605 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3606 Chain = Offset.getValue(1);
3607
3608 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3609 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3610
3611 Offset = DAG.getLoad(
3612 PtrVT, dl, Chain, Offset,
3613 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3614 } else {
3615 // local exec model
3616 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3616, __extension__ __PRETTY_FUNCTION__))
;
3617 ARMConstantPoolValue *CPV =
3618 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3619 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3620 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3621 Offset = DAG.getLoad(
3622 PtrVT, dl, Chain, Offset,
3623 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3624 }
3625
3626 // The address of the thread local variable is the add of the thread
3627 // pointer with the offset of the variable.
3628 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3629}
3630
3631SDValue
3632ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3633 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3634 if (DAG.getTarget().useEmulatedTLS())
3635 return LowerToTLSEmulatedModel(GA, DAG);
3636
3637 if (Subtarget->isTargetDarwin())
3638 return LowerGlobalTLSAddressDarwin(Op, DAG);
3639
3640 if (Subtarget->isTargetWindows())
3641 return LowerGlobalTLSAddressWindows(Op, DAG);
3642
3643 // TODO: implement the "local dynamic" model
3644 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3644, __extension__ __PRETTY_FUNCTION__))
;
3645 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3646
3647 switch (model) {
3648 case TLSModel::GeneralDynamic:
3649 case TLSModel::LocalDynamic:
3650 return LowerToTLSGeneralDynamicModel(GA, DAG);
3651 case TLSModel::InitialExec:
3652 case TLSModel::LocalExec:
3653 return LowerToTLSExecModels(GA, DAG, model);
3654 }
3655 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3655)
;
3656}
3657
3658/// Return true if all users of V are within function F, looking through
3659/// ConstantExprs.
3660static bool allUsersAreInFunction(const Value *V, const Function *F) {
3661 SmallVector<const User*,4> Worklist(V->users());
3662 while (!Worklist.empty()) {
3663 auto *U = Worklist.pop_back_val();
3664 if (isa<ConstantExpr>(U)) {
3665 append_range(Worklist, U->users());
3666 continue;
3667 }
3668
3669 auto *I = dyn_cast<Instruction>(U);
3670 if (!I || I->getParent()->getParent() != F)
3671 return false;
3672 }
3673 return true;
3674}
3675
3676static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3677 const GlobalValue *GV, SelectionDAG &DAG,
3678 EVT PtrVT, const SDLoc &dl) {
3679 // If we're creating a pool entry for a constant global with unnamed address,
3680 // and the global is small enough, we can emit it inline into the constant pool
3681 // to save ourselves an indirection.
3682 //
3683 // This is a win if the constant is only used in one function (so it doesn't
3684 // need to be duplicated) or duplicating the constant wouldn't increase code
3685 // size (implying the constant is no larger than 4 bytes).
3686 const Function &F = DAG.getMachineFunction().getFunction();
3687
3688 // We rely on this decision to inline being idemopotent and unrelated to the
3689 // use-site. We know that if we inline a variable at one use site, we'll
3690 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3691 // doesn't know about this optimization, so bail out if it's enabled else
3692 // we could decide to inline here (and thus never emit the GV) but require
3693 // the GV from fast-isel generated code.
3694 if (!EnableConstpoolPromotion ||
3695 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3696 return SDValue();
3697
3698 auto *GVar = dyn_cast<GlobalVariable>(GV);
3699 if (!GVar || !GVar->hasInitializer() ||
3700 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3701 !GVar->hasLocalLinkage())
3702 return SDValue();
3703
3704 // If we inline a value that contains relocations, we move the relocations
3705 // from .data to .text. This is not allowed in position-independent code.
3706 auto *Init = GVar->getInitializer();
3707 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3708 Init->needsDynamicRelocation())
3709 return SDValue();
3710
3711 // The constant islands pass can only really deal with alignment requests
3712 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3713 // any type wanting greater alignment requirements than 4 bytes. We also
3714 // can only promote constants that are multiples of 4 bytes in size or
3715 // are paddable to a multiple of 4. Currently we only try and pad constants
3716 // that are strings for simplicity.
3717 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3718 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3719 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3720 unsigned RequiredPadding = 4 - (Size % 4);
3721 bool PaddingPossible =
3722 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3723 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3724 Size == 0)
3725 return SDValue();
3726
3727 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3728 MachineFunction &MF = DAG.getMachineFunction();
3729 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3730
3731 // We can't bloat the constant pool too much, else the ConstantIslands pass
3732 // may fail to converge. If we haven't promoted this global yet (it may have
3733 // multiple uses), and promoting it would increase the constant pool size (Sz
3734 // > 4), ensure we have space to do so up to MaxTotal.
3735 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3736 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3737 ConstpoolPromotionMaxTotal)
3738 return SDValue();
3739
3740 // This is only valid if all users are in a single function; we can't clone
3741 // the constant in general. The LLVM IR unnamed_addr allows merging
3742 // constants, but not cloning them.
3743 //
3744 // We could potentially allow cloning if we could prove all uses of the
3745 // constant in the current function don't care about the address, like
3746 // printf format strings. But that isn't implemented for now.
3747 if (!allUsersAreInFunction(GVar, &F))
3748 return SDValue();
3749
3750 // We're going to inline this global. Pad it out if needed.
3751 if (RequiredPadding != 4) {
3752 StringRef S = CDAInit->getAsString();
3753
3754 SmallVector<uint8_t,16> V(S.size());
3755 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3756 while (RequiredPadding--)
3757 V.push_back(0);
3758 Init = ConstantDataArray::get(*DAG.getContext(), V);
3759 }
3760
3761 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3762 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3763 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3764 AFI->markGlobalAsPromotedToConstantPool(GVar);
3765 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3766 PaddedSize - 4);
3767 }
3768 ++NumConstpoolPromoted;
3769 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3770}
3771
3772bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3773 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3774 if (!(GV = GA->getBaseObject()))
3775 return false;
3776 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3777 return V->isConstant();
3778 return isa<Function>(GV);
3779}
3780
3781SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3782 SelectionDAG &DAG) const {
3783 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3784 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3784)
;
3785 case Triple::COFF:
3786 return LowerGlobalAddressWindows(Op, DAG);
3787 case Triple::ELF:
3788 return LowerGlobalAddressELF(Op, DAG);
3789 case Triple::MachO:
3790 return LowerGlobalAddressDarwin(Op, DAG);
3791 }
3792}
3793
3794SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3795 SelectionDAG &DAG) const {
3796 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3797 SDLoc dl(Op);
3798 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3799 const TargetMachine &TM = getTargetMachine();
3800 bool IsRO = isReadOnly(GV);
3801
3802 // promoteToConstantPool only if not generating XO text section
3803 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3804 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3805 return V;
3806
3807 if (isPositionIndependent()) {
3808 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3809 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3810 UseGOT_PREL ? ARMII::MO_GOT : 0);
3811 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3812 if (UseGOT_PREL)
3813 Result =
3814 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3815 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3816 return Result;
3817 } else if (Subtarget->isROPI() && IsRO) {
3818 // PC-relative.
3819 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3820 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3821 return Result;
3822 } else if (Subtarget->isRWPI() && !IsRO) {
3823 // SB-relative.
3824 SDValue RelAddr;
3825 if (Subtarget->useMovt()) {
3826 ++NumMovwMovt;
3827 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3828 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3829 } else { // use literal pool for address constant
3830 ARMConstantPoolValue *CPV =
3831 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3832 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3833 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3834 RelAddr = DAG.getLoad(
3835 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3836 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3837 }
3838 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3839 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3840 return Result;
3841 }
3842
3843 // If we have T2 ops, we can materialize the address directly via movt/movw
3844 // pair. This is always cheaper.
3845 if (Subtarget->useMovt()) {
3846 ++NumMovwMovt;
3847 // FIXME: Once remat is capable of dealing with instructions with register
3848 // operands, expand this into two nodes.
3849 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3850 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3851 } else {
3852 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3853 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3854 return DAG.getLoad(
3855 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3856 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3857 }
3858}
3859
3860SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3861 SelectionDAG &DAG) const {
3862 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3863, __extension__ __PRETTY_FUNCTION__))
3863 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3863, __extension__ __PRETTY_FUNCTION__))
;
3864 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3865 SDLoc dl(Op);
3866 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3867
3868 if (Subtarget->useMovt())
3869 ++NumMovwMovt;
3870
3871 // FIXME: Once remat is capable of dealing with instructions with register
3872 // operands, expand this into multiple nodes
3873 unsigned Wrapper =
3874 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3875
3876 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3877 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3878
3879 if (Subtarget->isGVIndirectSymbol(GV))
3880 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3881 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3882 return Result;
3883}
3884
3885SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3886 SelectionDAG &DAG) const {
3887 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3887, __extension__ __PRETTY_FUNCTION__))
;
3888 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3889, __extension__ __PRETTY_FUNCTION__))
3889 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3889, __extension__ __PRETTY_FUNCTION__))
;
3890 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3891, __extension__ __PRETTY_FUNCTION__))
3891 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3891, __extension__ __PRETTY_FUNCTION__))
;
3892
3893 const TargetMachine &TM = getTargetMachine();
3894 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3895 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3896 if (GV->hasDLLImportStorageClass())
3897 TargetFlags = ARMII::MO_DLLIMPORT;
3898 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3899 TargetFlags = ARMII::MO_COFFSTUB;
3900 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3901 SDValue Result;
3902 SDLoc DL(Op);
3903
3904 ++NumMovwMovt;
3905
3906 // FIXME: Once remat is capable of dealing with instructions with register
3907 // operands, expand this into two nodes.
3908 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3909 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3910 TargetFlags));
3911 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3912 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3913 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3914 return Result;
3915}
3916
3917SDValue
3918ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3919 SDLoc dl(Op);
3920 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3921 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3922 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3923 Op.getOperand(1), Val);
3924}
3925
3926SDValue
3927ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3928 SDLoc dl(Op);
3929 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3930 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3931}
3932
3933SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3934 SelectionDAG &DAG) const {
3935 SDLoc dl(Op);
3936 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3937 Op.getOperand(0));
3938}
3939
3940SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3941 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3942 unsigned IntNo =
3943 cast<ConstantSDNode>(
3944 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3945 ->getZExtValue();
3946 switch (IntNo) {
3947 default:
3948 return SDValue(); // Don't custom lower most intrinsics.
3949 case Intrinsic::arm_gnu_eabi_mcount: {
3950 MachineFunction &MF = DAG.getMachineFunction();
3951 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3952 SDLoc dl(Op);
3953 SDValue Chain = Op.getOperand(0);
3954 // call "\01__gnu_mcount_nc"
3955 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3956 const uint32_t *Mask =
3957 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3958 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3958, __extension__ __PRETTY_FUNCTION__))
;
3959 // Mark LR an implicit live-in.
3960 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3961 SDValue ReturnAddress =
3962 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3963 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3964 SDValue Callee =
3965 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3966 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3967 if (Subtarget->isThumb())
3968 return SDValue(
3969 DAG.getMachineNode(
3970 ARM::tBL_PUSHLR, dl, ResultTys,
3971 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3972 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3973 0);
3974 return SDValue(
3975 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3976 {ReturnAddress, Callee, RegisterMask, Chain}),
3977 0);
3978 }
3979 }
3980}
3981
3982SDValue
3983ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3984 const ARMSubtarget *Subtarget) const {
3985 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3986 SDLoc dl(Op);
3987 switch (IntNo) {
3988 default: return SDValue(); // Don't custom lower most intrinsics.
3989 case Intrinsic::thread_pointer: {
3990 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3991 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3992 }
3993 case Intrinsic::arm_cls: {
3994 const SDValue &Operand = Op.getOperand(1);
3995 const EVT VTy = Op.getValueType();
3996 SDValue SRA =
3997 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3998 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3999 SDValue SHL =
4000 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4001 SDValue OR =
4002 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4003 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4004 return Result;
4005 }
4006 case Intrinsic::arm_cls64: {
4007 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4008 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4009 const SDValue &Operand = Op.getOperand(1);
4010 const EVT VTy = Op.getValueType();
4011
4012 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4013 DAG.getConstant(1, dl, VTy));
4014 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4015 DAG.getConstant(0, dl, VTy));
4016 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4017 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4018 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4019 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4020 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4021 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4022 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4023 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4024 SDValue CheckLo =
4025 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4026 SDValue HiIsZero =
4027 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4028 SDValue AdjustedLo =
4029 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4030 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4031 SDValue Result =
4032 DAG.getSelect(dl, VTy, CheckLo,
4033 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4034 return Result;
4035 }
4036 case Intrinsic::eh_sjlj_lsda: {
4037 MachineFunction &MF = DAG.getMachineFunction();
4038 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4039 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4040 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4041 SDValue CPAddr;
4042 bool IsPositionIndependent = isPositionIndependent();
4043 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4044 ARMConstantPoolValue *CPV =
4045 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4046 ARMCP::CPLSDA, PCAdj);
4047 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4048 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4049 SDValue Result = DAG.getLoad(
4050 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4051 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4052
4053 if (IsPositionIndependent) {
4054 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4055 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4056 }
4057 return Result;
4058 }
4059 case Intrinsic::arm_neon_vabs:
4060 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4061 Op.getOperand(1));
4062 case Intrinsic::arm_neon_vmulls:
4063 case Intrinsic::arm_neon_vmullu: {
4064 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4065 ? ARMISD::VMULLs : ARMISD::VMULLu;
4066 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4067 Op.getOperand(1), Op.getOperand(2));
4068 }
4069 case Intrinsic::arm_neon_vminnm:
4070 case Intrinsic::arm_neon_vmaxnm: {
4071 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4072 ? ISD::FMINNUM : ISD::FMAXNUM;
4073 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4074 Op.getOperand(1), Op.getOperand(2));
4075 }
4076 case Intrinsic::arm_neon_vminu:
4077 case Intrinsic::arm_neon_vmaxu: {
4078 if (Op.getValueType().isFloatingPoint())
4079 return SDValue();
4080 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4081 ? ISD::UMIN : ISD::UMAX;
4082 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4083 Op.getOperand(1), Op.getOperand(2));
4084 }
4085 case Intrinsic::arm_neon_vmins:
4086 case Intrinsic::arm_neon_vmaxs: {
4087 // v{min,max}s is overloaded between signed integers and floats.
4088 if (!Op.getValueType().isFloatingPoint()) {
4089 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4090 ? ISD::SMIN : ISD::SMAX;
4091 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4092 Op.getOperand(1), Op.getOperand(2));
4093 }
4094 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4095 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4096 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4097 Op.getOperand(1), Op.getOperand(2));
4098 }
4099 case Intrinsic::arm_neon_vtbl1:
4100 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4101 Op.getOperand(1), Op.getOperand(2));
4102 case Intrinsic::arm_neon_vtbl2:
4103 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4104 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4105 case Intrinsic::arm_mve_pred_i2v:
4106 case Intrinsic::arm_mve_pred_v2i:
4107 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4108 Op.getOperand(1));
4109 case Intrinsic::arm_mve_vreinterpretq:
4110 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4111 Op.getOperand(1));
4112 case Intrinsic::arm_mve_lsll:
4113 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4114 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4115 case Intrinsic::arm_mve_asrl:
4116 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4117 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4118 }
4119}
4120
4121static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4122 const ARMSubtarget *Subtarget) {
4123 SDLoc dl(Op);
4124 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4125 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4126 if (SSID == SyncScope::SingleThread)
4127 return Op;
4128
4129 if (!Subtarget->hasDataBarrier()) {
4130 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4131 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4132 // here.
4133 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4134, __extension__ __PRETTY_FUNCTION__))
4134 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4134, __extension__ __PRETTY_FUNCTION__))
;
4135 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4136 DAG.getConstant(0, dl, MVT::i32));
4137 }
4138
4139 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4140 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4141 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4142 if (Subtarget->isMClass()) {
4143 // Only a full system barrier exists in the M-class architectures.
4144 Domain = ARM_MB::SY;
4145 } else if (Subtarget->preferISHSTBarriers() &&
4146 Ord == AtomicOrdering::Release) {
4147 // Swift happens to implement ISHST barriers in a way that's compatible with
4148 // Release semantics but weaker than ISH so we'd be fools not to use
4149 // it. Beware: other processors probably don't!
4150 Domain = ARM_MB::ISHST;
4151 }
4152
4153 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4154 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4155 DAG.getConstant(Domain, dl, MVT::i32));
4156}
4157
4158static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4159 const ARMSubtarget *Subtarget) {
4160 // ARM pre v5TE and Thumb1 does not have preload instructions.
4161 if (!(Subtarget->isThumb2() ||
4162 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4163 // Just preserve the chain.
4164 return Op.getOperand(0);
4165
4166 SDLoc dl(Op);
4167 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4168 if (!isRead &&
4169 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4170 // ARMv7 with MP extension has PLDW.
4171 return Op.getOperand(0);
4172
4173 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4174 if (Subtarget->isThumb()) {
4175 // Invert the bits.
4176 isRead = ~isRead & 1;
4177 isData = ~isData & 1;
4178 }
4179
4180 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4181 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4182 DAG.getConstant(isData, dl, MVT::i32));
4183}
4184
4185static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4186 MachineFunction &MF = DAG.getMachineFunction();
4187 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4188
4189 // vastart just stores the address of the VarArgsFrameIndex slot into the
4190 // memory location argument.
4191 SDLoc dl(Op);
4192 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4193 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4194 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4195 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4196 MachinePointerInfo(SV));
4197}
4198
4199SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4200 CCValAssign &NextVA,
4201 SDValue &Root,
4202 SelectionDAG &DAG,
4203 const SDLoc &dl) const {
4204 MachineFunction &MF = DAG.getMachineFunction();
4205 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4206
4207 const TargetRegisterClass *RC;
4208 if (AFI->isThumb1OnlyFunction())
4209 RC = &ARM::tGPRRegClass;
4210 else
4211 RC = &ARM::GPRRegClass;
4212
4213 // Transform the arguments stored in physical registers into virtual ones.
4214 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4215 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4216
4217 SDValue ArgValue2;
4218 if (NextVA.isMemLoc()) {
4219 MachineFrameInfo &MFI = MF.getFrameInfo();
4220 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4221
4222 // Create load node to retrieve arguments from the stack.
4223 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4224 ArgValue2 = DAG.getLoad(
4225 MVT::i32, dl, Root, FIN,
4226 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4227 } else {
4228 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4229 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4230 }
4231 if (!Subtarget->isLittle())
4232 std::swap (ArgValue, ArgValue2);
4233 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4234}
4235
4236// The remaining GPRs hold either the beginning of variable-argument
4237// data, or the beginning of an aggregate passed by value (usually
4238// byval). Either way, we allocate stack slots adjacent to the data
4239// provided by our caller, and store the unallocated registers there.
4240// If this is a variadic function, the va_list pointer will begin with
4241// these values; otherwise, this reassembles a (byval) structure that
4242// was split between registers and memory.
4243// Return: The frame index registers were stored into.
4244int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4245 const SDLoc &dl, SDValue &Chain,
4246 const Value *OrigArg,
4247 unsigned InRegsParamRecordIdx,
4248 int ArgOffset, unsigned ArgSize) const {
4249 // Currently, two use-cases possible:
4250 // Case #1. Non-var-args function, and we meet first byval parameter.
4251 // Setup first unallocated register as first byval register;
4252 // eat all remained registers
4253 // (these two actions are performed by HandleByVal method).
4254 // Then, here, we initialize stack frame with
4255 // "store-reg" instructions.
4256 // Case #2. Var-args function, that doesn't contain byval parameters.
4257 // The same: eat all remained unallocated registers,
4258 // initialize stack frame.
4259
4260 MachineFunction &MF = DAG.getMachineFunction();
4261 MachineFrameInfo &MFI = MF.getFrameInfo();
4262 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4263 unsigned RBegin, REnd;
4264 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4265 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4266 } else {
4267 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4268 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4269 REnd = ARM::R4;
4270 }
4271
4272 if (REnd != RBegin)
4273 ArgOffset = -4 * (ARM::R4 - RBegin);
4274
4275 auto PtrVT = getPointerTy(DAG.getDataLayout());
4276 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4277 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4278
4279 SmallVector<SDValue, 4> MemOps;
4280 const TargetRegisterClass *RC =
4281 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4282
4283 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4284 unsigned VReg = MF.addLiveIn(Reg, RC);
4285 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4286 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4287 MachinePointerInfo(OrigArg, 4 * i));
4288 MemOps.push_back(Store);
4289 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4290 }
4291
4292 if (!MemOps.empty())
4293 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4294 return FrameIndex;
4295}
4296
4297// Setup stack frame, the va_list pointer will start from.
4298void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4299 const SDLoc &dl, SDValue &Chain,
4300 unsigned ArgOffset,
4301 unsigned TotalArgRegsSaveSize,
4302 bool ForceMutable) const {
4303 MachineFunction &MF = DAG.getMachineFunction();
4304 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4305
4306 // Try to store any remaining integer argument regs
4307 // to their spots on the stack so that they may be loaded by dereferencing
4308 // the result of va_next.
4309 // If there is no regs to be stored, just point address after last
4310 // argument passed via stack.
4311 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4312 CCInfo.getInRegsParamsCount(),
4313 CCInfo.getNextStackOffset(),
4314 std::max(4U, TotalArgRegsSaveSize));
4315 AFI->setVarArgsFrameIndex(FrameIndex);
4316}
4317
4318bool ARMTargetLowering::splitValueIntoRegisterParts(
4319 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4320 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4321 bool IsABIRegCopy = CC.hasValue();
4322 EVT ValueVT = Val.getValueType();
4323 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4324 PartVT == MVT::f32) {
4325 unsigned ValueBits = ValueVT.getSizeInBits();
4326 unsigned PartBits = PartVT.getSizeInBits();
4327 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4328 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4329 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4330 Parts[0] = Val;
4331 return true;
4332 }
4333 return false;
4334}
4335
4336SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4337 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4338 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4339 bool IsABIRegCopy = CC.hasValue();
4340 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4341 PartVT == MVT::f32) {
4342 unsigned ValueBits = ValueVT.getSizeInBits();
4343 unsigned PartBits = PartVT.getSizeInBits();
4344 SDValue Val = Parts[0];
4345
4346 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4347 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4348 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4349 return Val;
4350 }
4351 return SDValue();
4352}
4353
4354SDValue ARMTargetLowering::LowerFormalArguments(
4355 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4356 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4357 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4358 MachineFunction &MF = DAG.getMachineFunction();
4359 MachineFrameInfo &MFI = MF.getFrameInfo();
4360
4361 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4362
4363 // Assign locations to all of the incoming arguments.
4364 SmallVector<CCValAssign, 16> ArgLocs;
4365 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4366 *DAG.getContext());
4367 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4368
4369 SmallVector<SDValue, 16> ArgValues;
4370 SDValue ArgValue;
4371 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4372 unsigned CurArgIdx = 0;
4373
4374 // Initially ArgRegsSaveSize is zero.
4375 // Then we increase this value each time we meet byval parameter.
4376 // We also increase this value in case of varargs function.
4377 AFI->setArgRegsSaveSize(0);
4378
4379 // Calculate the amount of stack space that we need to allocate to store
4380 // byval and variadic arguments that are passed in registers.
4381 // We need to know this before we allocate the first byval or variadic
4382 // argument, as they will be allocated a stack slot below the CFA (Canonical
4383 // Frame Address, the stack pointer at entry to the function).
4384 unsigned ArgRegBegin = ARM::R4;
4385 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4386 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4387 break;
4388
4389 CCValAssign &VA = ArgLocs[i];
4390 unsigned Index = VA.getValNo();
4391 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4392 if (!Flags.isByVal())
4393 continue;
4394
4395 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4395, __extension__ __PRETTY_FUNCTION__))
;
4396 unsigned RBegin, REnd;
4397 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4398 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4399
4400 CCInfo.nextInRegsParam();
4401 }
4402 CCInfo.rewindByValRegsInfo();
4403
4404 int lastInsIndex = -1;
4405 if (isVarArg && MFI.hasVAStart()) {
4406 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4407 if (RegIdx != array_lengthof(GPRArgRegs))
4408 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4409 }
4410
4411 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4412 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4413 auto PtrVT = getPointerTy(DAG.getDataLayout());
4414
4415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4416 CCValAssign &VA = ArgLocs[i];
4417 if (Ins[VA.getValNo()].isOrigArg()) {
4418 std::advance(CurOrigArg,
4419 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4420 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4421 }
4422 // Arguments stored in registers.
4423 if (VA.isRegLoc()) {
4424 EVT RegVT = VA.getLocVT();
4425
4426 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4427 // f64 and vector types are split up into multiple registers or
4428 // combinations of registers and stack slots.
4429 SDValue ArgValue1 =
4430 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4431 VA = ArgLocs[++i]; // skip ahead to next loc
4432 SDValue ArgValue2;
4433 if (VA.isMemLoc()) {
4434 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4435 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4436 ArgValue2 = DAG.getLoad(
4437 MVT::f64, dl, Chain, FIN,
4438 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4439 } else {
4440 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4441 }
4442 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4443 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4444 ArgValue1, DAG.getIntPtrConstant(0, dl));
4445 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4446 ArgValue2, DAG.getIntPtrConstant(1, dl));
4447 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4448 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4449 } else {
4450 const TargetRegisterClass *RC;
4451
4452 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4453 RC = &ARM::HPRRegClass;
4454 else if (RegVT == MVT::f32)
4455 RC = &ARM::SPRRegClass;
4456 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4457 RegVT == MVT::v4bf16)
4458 RC = &ARM::DPRRegClass;
4459 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4460 RegVT == MVT::v8bf16)
4461 RC = &ARM::QPRRegClass;
4462 else if (RegVT == MVT::i32)
4463 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4464 : &ARM::GPRRegClass;
4465 else
4466 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4466)
;
4467
4468 // Transform the arguments in physical registers into virtual ones.
4469 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4470 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4471
4472 // If this value is passed in r0 and has the returned attribute (e.g.
4473 // C++ 'structors), record this fact for later use.
4474 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4475 AFI->setPreservesR0();
4476 }
4477 }
4478
4479 // If this is an 8 or 16-bit value, it is really passed promoted
4480 // to 32 bits. Insert an assert[sz]ext to capture this, then
4481 // truncate to the right size.
4482 switch (VA.getLocInfo()) {
4483 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4483)
;
4484 case CCValAssign::Full: break;
4485 case CCValAssign::BCvt:
4486 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4487 break;
4488 case CCValAssign::SExt:
4489 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4490 DAG.getValueType(VA.getValVT()));
4491 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4492 break;
4493 case CCValAssign::ZExt:
4494 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4495 DAG.getValueType(VA.getValVT()));
4496 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4497 break;
4498 }
4499
4500 // f16 arguments have their size extended to 4 bytes and passed as if they
4501 // had been copied to the LSBs of a 32-bit register.
4502 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4503 if (VA.needsCustom() &&
4504 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4505 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4506
4507 InVals.push_back(ArgValue);
4508 } else { // VA.isRegLoc()
4509 // sanity check
4510 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4510, __extension__ __PRETTY_FUNCTION__))
;
4511 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4511, __extension__ __PRETTY_FUNCTION__))
;
4512
4513 int index = VA.getValNo();
4514
4515 // Some Ins[] entries become multiple ArgLoc[] entries.
4516 // Process them only once.
4517 if (index != lastInsIndex)
4518 {
4519 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4520 // FIXME: For now, all byval parameter objects are marked mutable.
4521 // This can be changed with more analysis.
4522 // In case of tail call optimization mark all arguments mutable.
4523 // Since they could be overwritten by lowering of arguments in case of
4524 // a tail call.
4525 if (Flags.isByVal()) {
4526 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4527, __extension__ __PRETTY_FUNCTION__))
4527 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4527, __extension__ __PRETTY_FUNCTION__))
;
4528 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4529
4530 int FrameIndex = StoreByValRegs(
4531 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4532 VA.getLocMemOffset(), Flags.getByValSize());
4533 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4534 CCInfo.nextInRegsParam();
4535 } else {
4536 unsigned FIOffset = VA.getLocMemOffset();
4537 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4538 FIOffset, true);
4539
4540 // Create load nodes to retrieve arguments from the stack.
4541 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4542 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4543 MachinePointerInfo::getFixedStack(
4544 DAG.getMachineFunction(), FI)));
4545 }
4546 lastInsIndex = index;
4547 }
4548 }
4549 }
4550
4551 // varargs
4552 if (isVarArg && MFI.hasVAStart()) {
4553 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4554 TotalArgRegsSaveSize);
4555 if (AFI->isCmseNSEntryFunction()) {
4556 DiagnosticInfoUnsupported Diag(
4557 DAG.getMachineFunction().getFunction(),
4558 "secure entry function must not be variadic", dl.getDebugLoc());
4559 DAG.getContext()->diagnose(Diag);
4560 }
4561 }
4562
4563 unsigned StackArgSize = CCInfo.getNextStackOffset();
4564 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4565 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4566 // The only way to guarantee a tail call is if the callee restores its
4567 // argument area, but it must also keep the stack aligned when doing so.
4568 const DataLayout &DL = DAG.getDataLayout();
4569 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4570
4571 AFI->setArgumentStackToRestore(StackArgSize);
4572 }
4573 AFI->setArgumentStackSize(StackArgSize);
4574
4575 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4576 DiagnosticInfoUnsupported Diag(
4577 DAG.getMachineFunction().getFunction(),
4578 "secure entry function requires arguments on stack", dl.getDebugLoc());
4579 DAG.getContext()->diagnose(Diag);
4580 }
4581
4582 return Chain;
4583}
4584
4585/// isFloatingPointZero - Return true if this is +0.0.
4586static bool isFloatingPointZero(SDValue Op) {
4587 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4588 return CFP->getValueAPF().isPosZero();
4589 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4590 // Maybe this has already been legalized into the constant pool?
4591 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4592 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4593 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4594 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4595 return CFP->getValueAPF().isPosZero();
4596 }
4597 } else if (Op->getOpcode() == ISD::BITCAST &&
4598 Op->getValueType(0) == MVT::f64) {
4599 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4600 // created by LowerConstantFP().
4601 SDValue BitcastOp = Op->getOperand(0);
4602 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4603 isNullConstant(BitcastOp->getOperand(0)))
4604 return true;
4605 }
4606 return false;
4607}
4608
4609/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4610/// the given operands.
4611SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4612 SDValue &ARMcc, SelectionDAG &DAG,
4613 const SDLoc &dl) const {
4614 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4615 unsigned C = RHSC->getZExtValue();
4616 if (!isLegalICmpImmediate((int32_t)C)) {
4617 // Constant does not fit, try adjusting it by one.
4618 switch (CC) {
4619 default: break;
4620 case ISD::SETLT:
4621 case ISD::SETGE:
4622 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4623 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4624 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4625 }
4626 break;
4627 case ISD::SETULT:
4628 case ISD::SETUGE:
4629 if (C != 0 && isLegalICmpImmediate(C-1)) {
4630 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4631 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4632 }
4633 break;
4634 case ISD::SETLE:
4635 case ISD::SETGT:
4636 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4637 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4638 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4639 }
4640 break;
4641 case ISD::SETULE:
4642 case ISD::SETUGT:
4643 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4644 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4645 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4646 }
4647 break;
4648 }
4649 }
4650 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4651 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4652 // In ARM and Thumb-2, the compare instructions can shift their second
4653 // operand.
4654 CC = ISD::getSetCCSwappedOperands(CC);
4655 std::swap(LHS, RHS);
4656 }
4657
4658 // Thumb1 has very limited immediate modes, so turning an "and" into a
4659 // shift can save multiple instructions.
4660 //
4661 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4662 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4663 // own. If it's the operand to an unsigned comparison with an immediate,
4664 // we can eliminate one of the shifts: we transform
4665 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4666 //
4667 // We avoid transforming cases which aren't profitable due to encoding
4668 // details:
4669 //
4670 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4671 // would not; in that case, we're essentially trading one immediate load for
4672 // another.
4673 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4674 // 3. C2 is zero; we have other code for this special case.
4675 //
4676 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4677 // instruction, since the AND is always one instruction anyway, but we could
4678 // use narrow instructions in some cases.
4679 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4680 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4681 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4682 !isSignedIntSetCC(CC)) {
4683 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4684 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4685 uint64_t RHSV = RHSC->getZExtValue();
4686 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4687 unsigned ShiftBits = countLeadingZeros(Mask);
4688 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4689 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4690 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4691 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4692 }
4693 }
4694 }
4695
4696 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4697 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4698 // way a cmp would.
4699 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4700 // some tweaks to the heuristics for the previous and->shift transform.
4701 // FIXME: Optimize cases where the LHS isn't a shift.
4702 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4703 isa<ConstantSDNode>(RHS) &&
4704 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4705 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4706 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4707 unsigned ShiftAmt =
4708 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4709 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4710 DAG.getVTList(MVT::i32, MVT::i32),
4711 LHS.getOperand(0),
4712 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4713 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4714 Shift.getValue(1), SDValue());
4715 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4716 return Chain.getValue(1);
4717 }
4718
4719 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4720
4721 // If the RHS is a constant zero then the V (overflow) flag will never be
4722 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4723 // simpler for other passes (like the peephole optimiser) to deal with.
4724 if (isNullConstant(RHS)) {
4725 switch (CondCode) {
4726 default: break;
4727 case ARMCC::GE:
4728 CondCode = ARMCC::PL;
4729 break;
4730 case ARMCC::LT:
4731 CondCode = ARMCC::MI;
4732 break;
4733 }
4734 }
4735
4736 ARMISD::NodeType CompareType;
4737 switch (CondCode) {
4738 default:
4739 CompareType = ARMISD::CMP;
4740 break;
4741 case ARMCC::EQ:
4742 case ARMCC::NE:
4743 // Uses only Z Flag
4744 CompareType = ARMISD::CMPZ;
4745 break;
4746 }
4747 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4748 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4749}
4750
4751/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4752SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4753 SelectionDAG &DAG, const SDLoc &dl,
4754 bool Signaling) const {
4755 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4755, __extension__ __PRETTY_FUNCTION__))
;
4756 SDValue Cmp;
4757 if (!isFloatingPointZero(RHS))
4758 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4759 dl, MVT::Glue, LHS, RHS);
4760 else
4761 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4762 dl, MVT::Glue, LHS);
4763 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4764}
4765
4766/// duplicateCmp - Glue values can have only one use, so this function
4767/// duplicates a comparison node.
4768SDValue
4769ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4770 unsigned Opc = Cmp.getOpcode();
4771 SDLoc DL(Cmp);
4772 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4773 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4774
4775 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4775, __extension__ __PRETTY_FUNCTION__))
;
4776 Cmp = Cmp.getOperand(0);
4777 Opc = Cmp.getOpcode();
4778 if (Opc == ARMISD::CMPFP)
4779 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4780 else {
4781 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4781, __extension__ __PRETTY_FUNCTION__))
;
4782 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4783 }
4784 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4785}
4786
4787// This function returns three things: the arithmetic computation itself
4788// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4789// comparison and the condition code define the case in which the arithmetic
4790// computation *does not* overflow.
4791std::pair<SDValue, SDValue>
4792ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4793 SDValue &ARMcc) const {
4794 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4794, __extension__ __PRETTY_FUNCTION__))
;
4795
4796 SDValue Value, OverflowCmp;
4797 SDValue LHS = Op.getOperand(0);
4798 SDValue RHS = Op.getOperand(1);
4799 SDLoc dl(Op);
4800
4801 // FIXME: We are currently always generating CMPs because we don't support
4802 // generating CMN through the backend. This is not as good as the natural
4803 // CMP case because it causes a register dependency and cannot be folded
4804 // later.
4805
4806 switch (Op.getOpcode()) {
4807 default:
4808 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4808)
;
4809 case ISD::SADDO:
4810 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4811 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4812 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4813 break;
4814 case ISD::UADDO:
4815 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4816 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4817 // We do not use it in the USUBO case as Value may not be used.
4818 Value = DAG.getNode(ARMISD::ADDC, dl,
4819 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4820 .getValue(0);
4821 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4822 break;
4823 case ISD::SSUBO:
4824 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4825 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4826 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4827 break;
4828 case ISD::USUBO:
4829 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4830 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4831 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4832 break;
4833 case ISD::UMULO:
4834 // We generate a UMUL_LOHI and then check if the high word is 0.
4835 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4836 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4837 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4838 LHS, RHS);
4839 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4840 DAG.getConstant(0, dl, MVT::i32));
4841 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4842 break;
4843 case ISD::SMULO:
4844 // We generate a SMUL_LOHI and then check if all the bits of the high word
4845 // are the same as the sign bit of the low word.
4846 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4847 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4848 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4849 LHS, RHS);
4850 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4851 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4852 Value.getValue(0),
4853 DAG.getConstant(31, dl, MVT::i32)));
4854 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4855 break;
4856 } // switch (...)
4857
4858 return std::make_pair(Value, OverflowCmp);
4859}
4860
4861SDValue
4862ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4863 // Let legalize expand this if it isn't a legal type yet.
4864 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4865 return SDValue();
4866
4867 SDValue Value, OverflowCmp;
4868 SDValue ARMcc;
4869 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4870 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4871 SDLoc dl(Op);
4872 // We use 0 and 1 as false and true values.
4873 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4874 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4875 EVT VT = Op.getValueType();
4876
4877 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4878 ARMcc, CCR, OverflowCmp);
4879
4880 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4881 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4882}
4883
4884static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4885 SelectionDAG &DAG) {
4886 SDLoc DL(BoolCarry);
4887 EVT CarryVT = BoolCarry.getValueType();
4888
4889 // This converts the boolean value carry into the carry flag by doing
4890 // ARMISD::SUBC Carry, 1
4891 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4892 DAG.getVTList(CarryVT, MVT::i32),
4893 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4894 return Carry.getValue(1);
4895}
4896
4897static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4898 SelectionDAG &DAG) {
4899 SDLoc DL(Flags);
4900
4901 // Now convert the carry flag into a boolean carry. We do this
4902 // using ARMISD:ADDE 0, 0, Carry
4903 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4904 DAG.getConstant(0, DL, MVT::i32),
4905 DAG.getConstant(0, DL, MVT::i32), Flags);
4906}
4907
4908SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4909 SelectionDAG &DAG) const {
4910 // Let legalize expand this if it isn't a legal type yet.
4911 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4912 return SDValue();
4913
4914 SDValue LHS = Op.getOperand(0);
4915 SDValue RHS = Op.getOperand(1);
4916 SDLoc dl(Op);
4917
4918 EVT VT = Op.getValueType();
4919 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4920 SDValue Value;
4921 SDValue Overflow;
4922 switch (Op.getOpcode()) {
4923 default:
4924 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4924)
;
4925 case ISD::UADDO:
4926 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4927 // Convert the carry flag into a boolean value.
4928 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4929 break;
4930 case ISD::USUBO: {
4931 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4932 // Convert the carry flag into a boolean value.
4933 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4934 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4935 // value. So compute 1 - C.
4936 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4937 DAG.getConstant(1, dl, MVT::i32), Overflow);
4938 break;
4939 }
4940 }
4941
4942 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4943}
4944
4945static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4946 const ARMSubtarget *Subtarget) {
4947 EVT VT = Op.getValueType();
4948 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
4949 return SDValue();
4950 if (!VT.isSimple())
4951 return SDValue();
4952
4953 unsigned NewOpcode;
4954 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4955 switch (VT.getSimpleVT().SimpleTy) {
4956 default:
4957 return SDValue();
4958 case MVT::i8:
4959 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4960 break;
4961 case MVT::i16:
4962 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4963 break;
4964 }
4965
4966 SDLoc dl(Op);
4967 SDValue Add =
4968 DAG.getNode(NewOpcode, dl, MVT::i32,
4969 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4970 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4971 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4972}
4973
4974SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4975 SDValue Cond = Op.getOperand(0);
4976 SDValue SelectTrue = Op.getOperand(1);
4977 SDValue SelectFalse = Op.getOperand(2);
4978 SDLoc dl(Op);
4979 unsigned Opc = Cond.getOpcode();
4980
4981 if (Cond.getResNo() == 1 &&
4982 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4983 Opc == ISD::USUBO)) {
4984 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4985 return SDValue();
4986
4987 SDValue Value, OverflowCmp;
4988 SDValue ARMcc;
4989 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4990 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4991 EVT VT = Op.getValueType();
4992
4993 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4994 OverflowCmp, DAG);
4995 }
4996
4997 // Convert:
4998 //
4999 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5000 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5001 //
5002 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5003 const ConstantSDNode *CMOVTrue =
5004 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5005 const ConstantSDNode *CMOVFalse =
5006 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5007
5008 if (CMOVTrue && CMOVFalse) {
5009 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5010 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5011
5012 SDValue True;
5013 SDValue False;
5014 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5015 True = SelectTrue;
5016 False = SelectFalse;
5017 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5018 True = SelectFalse;
5019 False = SelectTrue;
5020 }
5021
5022 if (True.getNode() && False.getNode()) {
5023 EVT VT = Op.getValueType();
5024 SDValue ARMcc = Cond.getOperand(2);
5025 SDValue CCR = Cond.getOperand(3);
5026 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5027 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5027, __extension__ __PRETTY_FUNCTION__))
;
5028 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5029 }
5030 }
5031 }
5032
5033 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5034 // undefined bits before doing a full-word comparison with zero.
5035 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5036 DAG.getConstant(1, dl, Cond.getValueType()));
5037
5038 return DAG.getSelectCC(dl, Cond,
5039 DAG.getConstant(0, dl, Cond.getValueType()),
5040 SelectTrue, SelectFalse, ISD::SETNE);
5041}
5042
5043static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5044 bool &swpCmpOps, bool &swpVselOps) {
5045 // Start by selecting the GE condition code for opcodes that return true for
5046 // 'equality'
5047 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5048 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5049 CondCode = ARMCC::GE;
5050
5051 // and GT for opcodes that return false for 'equality'.
5052 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5053 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5054 CondCode = ARMCC::GT;
5055
5056 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5057 // to swap the compare operands.
5058 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5059 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5060 swpCmpOps = true;
5061
5062 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5063 // If we have an unordered opcode, we need to swap the operands to the VSEL
5064 // instruction (effectively negating the condition).
5065 //
5066 // This also has the effect of swapping which one of 'less' or 'greater'
5067 // returns true, so we also swap the compare operands. It also switches
5068 // whether we return true for 'equality', so we compensate by picking the
5069 // opposite condition code to our original choice.
5070 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5071 CC == ISD::SETUGT) {
5072 swpCmpOps = !swpCmpOps;
5073 swpVselOps = !swpVselOps;
5074 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5075 }
5076
5077 // 'ordered' is 'anything but unordered', so use the VS condition code and
5078 // swap the VSEL operands.
5079 if (CC == ISD::SETO) {
5080 CondCode = ARMCC::VS;
5081 swpVselOps = true;
5082 }
5083
5084 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5085 // code and swap the VSEL operands. Also do this if we don't care about the
5086 // unordered case.
5087 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5088 CondCode = ARMCC::EQ;
5089 swpVselOps = true;
5090 }
5091}
5092
5093SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5094 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5095 SDValue Cmp, SelectionDAG &DAG) const {
5096 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5097 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5098 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5099 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5100 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5101
5102 SDValue TrueLow = TrueVal.getValue(0);
5103 SDValue TrueHigh = TrueVal.getValue(1);
5104 SDValue FalseLow = FalseVal.getValue(0);
5105 SDValue FalseHigh = FalseVal.getValue(1);
5106
5107 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5108 ARMcc, CCR, Cmp);
5109 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5110 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5111
5112 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5113 } else {
5114 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5115 Cmp);
5116 }
5117}
5118
5119static bool isGTorGE(ISD::CondCode CC) {
5120 return CC == ISD::SETGT || CC == ISD::SETGE;
5121}
5122
5123static bool isLTorLE(ISD::CondCode CC) {
5124 return CC == ISD::SETLT || CC == ISD::SETLE;
5125}
5126
5127// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5128// All of these conditions (and their <= and >= counterparts) will do:
5129// x < k ? k : x
5130// x > k ? x : k
5131// k < x ? x : k
5132// k > x ? k : x
5133static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5134 const SDValue TrueVal, const SDValue FalseVal,
5135 const ISD::CondCode CC, const SDValue K) {
5136 return (isGTorGE(CC) &&
5137 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5138 (isLTorLE(CC) &&
5139 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5140}
5141
5142// Check if two chained conditionals could be converted into SSAT or USAT.
5143//
5144// SSAT can replace a set of two conditional selectors that bound a number to an
5145// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5146//
5147// x < -k ? -k : (x > k ? k : x)
5148// x < -k ? -k : (x < k ? x : k)
5149// x > -k ? (x > k ? k : x) : -k
5150// x < k ? (x < -k ? -k : x) : k
5151// etc.
5152//
5153// LLVM canonicalizes these to either a min(max()) or a max(min())
5154// pattern. This function tries to match one of these and will return a SSAT
5155// node if successful.
5156//
5157// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5158// is a power of 2.
5159static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5160 EVT VT = Op.getValueType();
5161 SDValue V1 = Op.getOperand(0);
5162 SDValue K1 = Op.getOperand(1);
5163 SDValue TrueVal1 = Op.getOperand(2);
5164 SDValue FalseVal1 = Op.getOperand(3);
5165 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5166
5167 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5168 if (Op2.getOpcode() != ISD::SELECT_CC)
5169 return SDValue();
5170
5171 SDValue V2 = Op2.getOperand(0);
5172 SDValue K2 = Op2.getOperand(1);
5173 SDValue TrueVal2 = Op2.getOperand(2);
5174 SDValue FalseVal2 = Op2.getOperand(3);
5175 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5176
5177 SDValue V1Tmp = V1;
5178 SDValue V2Tmp = V2;
5179
5180 // Check that the registers and the constants match a max(min()) or min(max())
5181 // pattern
5182 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5183 K2 != FalseVal2 ||
5184 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5185 return SDValue();
5186
5187 // Check that the constant in the lower-bound check is
5188 // the opposite of the constant in the upper-bound check
5189 // in 1's complement.
5190 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5191 return SDValue();
5192
5193 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5194 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5195 int64_t PosVal = std::max(Val1, Val2);
5196 int64_t NegVal = std::min(Val1, Val2);
5197
5198 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5199 !isPowerOf2_64(PosVal + 1))
5200 return SDValue();
5201
5202 // Handle the difference between USAT (unsigned) and SSAT (signed)
5203 // saturation
5204 // At this point, PosVal is guaranteed to be positive
5205 uint64_t K = PosVal;
5206 SDLoc dl(Op);
5207 if (Val1 == ~Val2)
5208 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5209 DAG.getConstant(countTrailingOnes(K), dl, VT));
5210 if (NegVal == 0)
5211 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5212 DAG.getConstant(countTrailingOnes(K), dl, VT));
5213
5214 return SDValue();
5215}
5216
5217// Check if a condition of the type x < k ? k : x can be converted into a
5218// bit operation instead of conditional moves.
5219// Currently this is allowed given:
5220// - The conditions and values match up
5221// - k is 0 or -1 (all ones)
5222// This function will not check the last condition, thats up to the caller
5223// It returns true if the transformation can be made, and in such case
5224// returns x in V, and k in SatK.
5225static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5226 SDValue &SatK)
5227{
5228 SDValue LHS = Op.getOperand(0);
5229 SDValue RHS = Op.getOperand(1);
5230 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5231 SDValue TrueVal = Op.getOperand(2);
5232 SDValue FalseVal = Op.getOperand(3);
5233
5234 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5235 ? &RHS
5236 : nullptr;
5237
5238 // No constant operation in comparison, early out
5239 if (!K)
5240 return false;
5241
5242 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5243 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5244 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5245
5246 // If the constant on left and right side, or variable on left and right,
5247 // does not match, early out
5248 if (*K != KTmp || V != VTmp)
5249 return false;
5250
5251 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5252 SatK = *K;
5253 return true;
5254 }
5255
5256 return false;
5257}
5258
5259bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5260 if (VT == MVT::f32)
5261 return !Subtarget->hasVFP2Base();
5262 if (VT == MVT::f64)
5263 return !Subtarget->hasFP64();
5264 if (VT == MVT::f16)
5265 return !Subtarget->hasFullFP16();
5266 return false;
5267}
5268
5269SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5270 EVT VT = Op.getValueType();
5271 SDLoc dl(Op);
5272
5273 // Try to convert two saturating conditional selects into a single SSAT
5274 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5275 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5276 return SatValue;
5277
5278 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5279 // into more efficient bit operations, which is possible when k is 0 or -1
5280 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5281 // single instructions. On Thumb the shift and the bit operation will be two
5282 // instructions.
5283 // Only allow this transformation on full-width (32-bit) operations
5284 SDValue LowerSatConstant;
5285 SDValue SatValue;
5286 if (VT == MVT::i32 &&
5287 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5288 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5289 DAG.getConstant(31, dl, VT));
5290 if (isNullConstant(LowerSatConstant)) {
5291 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5292 DAG.getAllOnesConstant(dl, VT));
5293 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5294 } else if (isAllOnesConstant(LowerSatConstant))
5295 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5296 }
5297
5298 SDValue LHS = Op.getOperand(0);
5299 SDValue RHS = Op.getOperand(1);
5300 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5301 SDValue TrueVal = Op.getOperand(2);
5302 SDValue FalseVal = Op.getOperand(3);
5303 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5304 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5305
5306 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5307 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5308 unsigned TVal = CTVal->getZExtValue();
5309 unsigned FVal = CFVal->getZExtValue();
5310 unsigned Opcode = 0;
5311
5312 if (TVal == ~FVal) {
5313 Opcode = ARMISD::CSINV;
5314 } else if (TVal == ~FVal + 1) {
5315 Opcode = ARMISD::CSNEG;
5316 } else if (TVal + 1 == FVal) {
5317 Opcode = ARMISD::CSINC;
5318 } else if (TVal == FVal + 1) {
5319 Opcode = ARMISD::CSINC;
5320 std::swap(TrueVal, FalseVal);
5321 std::swap(TVal, FVal);
5322 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5323 }
5324
5325 if (Opcode) {
5326 // If one of the constants is cheaper than another, materialise the
5327 // cheaper one and let the csel generate the other.
5328 if (Opcode != ARMISD::CSINC &&
5329 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5330 std::swap(TrueVal, FalseVal);
5331 std::swap(TVal, FVal);
5332 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5333 }
5334
5335 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5336 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5337 // -(-a) == a, but (a+1)+1 != a).
5338 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5339 std::swap(TrueVal, FalseVal);
5340 std::swap(TVal, FVal);
5341 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5342 }
5343
5344 // Drops F's value because we can get it by inverting/negating TVal.
5345 FalseVal = TrueVal;
5346
5347 SDValue ARMcc;
5348 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5349 EVT VT = TrueVal.getValueType();
5350 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5351 }
5352 }
5353
5354 if (isUnsupportedFloatingType(LHS.getValueType())) {
5355 DAG.getTargetLoweringInfo().softenSetCCOperands(
5356 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5357
5358 // If softenSetCCOperands only returned one value, we should compare it to
5359 // zero.
5360 if (!RHS.getNode()) {
5361 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5362 CC = ISD::SETNE;
5363 }
5364 }
5365
5366 if (LHS.getValueType() == MVT::i32) {
5367 // Try to generate VSEL on ARMv8.
5368 // The VSEL instruction can't use all the usual ARM condition
5369 // codes: it only has two bits to select the condition code, so it's
5370 // constrained to use only GE, GT, VS and EQ.
5371 //
5372 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5373 // swap the operands of the previous compare instruction (effectively
5374 // inverting the compare condition, swapping 'less' and 'greater') and
5375 // sometimes need to swap the operands to the VSEL (which inverts the
5376 // condition in the sense of firing whenever the previous condition didn't)
5377 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5378 TrueVal.getValueType() == MVT::f32 ||
5379 TrueVal.getValueType() == MVT::f64)) {
5380 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5381 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5382 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5383 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5384 std::swap(TrueVal, FalseVal);
5385 }
5386 }
5387
5388 SDValue ARMcc;
5389 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5390 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5391 // Choose GE over PL, which vsel does now support
5392 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5393 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5394 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5395 }
5396
5397 ARMCC::CondCodes CondCode, CondCode2;
5398 FPCCToARMCC(CC, CondCode, CondCode2);
5399
5400 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5401 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5402 // must use VSEL (limited condition codes), due to not having conditional f16
5403 // moves.
5404 if (Subtarget->hasFPARMv8Base() &&
5405 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5406 (TrueVal.getValueType() == MVT::f16 ||
5407 TrueVal.getValueType() == MVT::f32 ||
5408 TrueVal.getValueType() == MVT::f64)) {
5409 bool swpCmpOps = false;
5410 bool swpVselOps = false;
5411 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5412
5413 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5414 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5415 if (swpCmpOps)
5416 std::swap(LHS, RHS);
5417 if (swpVselOps)
5418 std::swap(TrueVal, FalseVal);
5419 }
5420 }
5421
5422 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5423 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5424 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5425 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5426 if (CondCode2 != ARMCC::AL) {
5427 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5428 // FIXME: Needs another CMP because flag can have but one use.
5429 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5430 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5431 }
5432 return Result;
5433}
5434
5435/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5436/// to morph to an integer compare sequence.
5437static bool canChangeToInt(SDValue Op, bool &SeenZero,
5438 const ARMSubtarget *Subtarget) {
5439 SDNode *N = Op.getNode();
5440 if (!N->hasOneUse())
5441 // Otherwise it requires moving the value from fp to integer registers.
5442 return false;
5443 if (!N->getNumValues())
5444 return false;
5445 EVT VT = Op.getValueType();
5446 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5447 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5448 // vmrs are very slow, e.g. cortex-a8.
5449 return false;
5450
5451 if (isFloatingPointZero(Op)) {
5452 SeenZero = true;
5453 return true;
5454 }
5455 return ISD::isNormalLoad(N);
5456}
5457
5458static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5459 if (isFloatingPointZero(Op))
5460 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5461
5462 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5463 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5464 Ld->getPointerInfo(), Ld->getAlignment(),
5465 Ld->getMemOperand()->getFlags());
5466
5467 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5467)
;
5468}
5469
5470static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5471 SDValue &RetVal1, SDValue &RetVal2) {
5472 SDLoc dl(Op);
5473
5474 if (isFloatingPointZero(Op)) {
5475 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5476 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5477 return;
5478 }
5479
5480 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5481 SDValue Ptr = Ld->getBasePtr();
5482 RetVal1 =
5483 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5484 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5485
5486 EVT PtrType = Ptr.getValueType();
5487 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5488 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5489 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5490 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5491 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5492 Ld->getMemOperand()->getFlags());
5493 return;
5494 }
5495
5496 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5496)
;
5497}
5498
5499/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5500/// f32 and even f64 comparisons to integer ones.
5501SDValue
5502ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5503 SDValue Chain = Op.getOperand(0);
5504 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5505 SDValue LHS = Op.getOperand(2);
5506 SDValue RHS = Op.getOperand(3);
5507 SDValue Dest = Op.getOperand(4);
5508 SDLoc dl(Op);
5509
5510 bool LHSSeenZero = false;
5511 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5512 bool RHSSeenZero = false;
5513 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5514 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5515 // If unsafe fp math optimization is enabled and there are no other uses of
5516 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5517 // to an integer comparison.
5518 if (CC == ISD::SETOEQ)
5519 CC = ISD::SETEQ;
5520 else if (CC == ISD::SETUNE)
5521 CC = ISD::SETNE;
5522
5523 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5524 SDValue ARMcc;
5525 if (LHS.getValueType() == MVT::f32) {
5526 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5527 bitcastf32Toi32(LHS, DAG), Mask);
5528 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5529 bitcastf32Toi32(RHS, DAG), Mask);
5530 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5531 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5532 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5533 Chain, Dest, ARMcc, CCR, Cmp);
5534 }
5535
5536 SDValue LHS1, LHS2;
5537 SDValue RHS1, RHS2;
5538 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5539 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5540 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5541 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5542 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5543 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5544 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5545 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5546 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5547 }
5548
5549 return SDValue();
5550}
5551
5552SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5553 SDValue Chain = Op.getOperand(0);
5554 SDValue Cond = Op.getOperand(1);
5555 SDValue Dest = Op.getOperand(2);
5556 SDLoc dl(Op);
5557
5558 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5559 // instruction.
5560 unsigned Opc = Cond.getOpcode();
5561 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5562 !Subtarget->isThumb1Only();
5563 if (Cond.getResNo() == 1 &&
5564 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5565 Opc == ISD::USUBO || OptimizeMul)) {
5566 // Only lower legal XALUO ops.
5567 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5568 return SDValue();
5569
5570 // The actual operation with overflow check.
5571 SDValue Value, OverflowCmp;
5572 SDValue ARMcc;
5573 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5574
5575 // Reverse the condition code.
5576 ARMCC::CondCodes CondCode =
5577 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5578 CondCode = ARMCC::getOppositeCondition(CondCode);
5579 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5580 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5581
5582 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5583 OverflowCmp);
5584 }
5585
5586 return SDValue();
5587}
5588
5589SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5590 SDValue Chain = Op.getOperand(0);
5591 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5592 SDValue LHS = Op.getOperand(2);
5593 SDValue RHS = Op.getOperand(3);
5594 SDValue Dest = Op.getOperand(4);
5595 SDLoc dl(Op);
5596
5597 if (isUnsupportedFloatingType(LHS.getValueType())) {
5598 DAG.getTargetLoweringInfo().softenSetCCOperands(
5599 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5600
5601 // If softenSetCCOperands only returned one value, we should compare it to
5602 // zero.
5603 if (!RHS.getNode()) {
5604 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5605 CC = ISD::SETNE;
5606 }
5607 }
5608
5609 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5610 // instruction.
5611 unsigned Opc = LHS.getOpcode();
5612 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5613 !Subtarget->isThumb1Only();
5614 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5615 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5616 Opc == ISD::USUBO || OptimizeMul) &&
5617 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5618 // Only lower legal XALUO ops.
5619 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5620 return SDValue();
5621
5622 // The actual operation with overflow check.
5623 SDValue Value, OverflowCmp;
5624 SDValue ARMcc;
5625 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5626
5627 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5628 // Reverse the condition code.
5629 ARMCC::CondCodes CondCode =
5630 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5631 CondCode = ARMCC::getOppositeCondition(CondCode);
5632 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5633 }
5634 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5635
5636 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5637 OverflowCmp);
5638 }
5639
5640 if (LHS.getValueType() == MVT::i32) {
5641 SDValue ARMcc;
5642 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5643 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5644 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5645 Chain, Dest, ARMcc, CCR, Cmp);
5646 }
5647
5648 if (getTargetMachine().Options.UnsafeFPMath &&
5649 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5650 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5651 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5652 return Result;
5653 }
5654
5655 ARMCC::CondCodes CondCode, CondCode2;
5656 FPCCToARMCC(CC, CondCode, CondCode2);
5657
5658 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5659 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5660 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5661 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5662 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5663 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5664 if (CondCode2 != ARMCC::AL) {
5665 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5666 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5667 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5668 }
5669 return Res;
5670}
5671
5672SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5673 SDValue Chain = Op.getOperand(0);
5674 SDValue Table = Op.getOperand(1);
5675 SDValue Index = Op.getOperand(2);
5676 SDLoc dl(Op);
5677
5678 EVT PTy = getPointerTy(DAG.getDataLayout());
5679 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5680 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5681 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5682 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5683 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5684 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5685 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5686 // which does another jump to the destination. This also makes it easier
5687 // to translate it to TBB / TBH later (Thumb2 only).
5688 // FIXME: This might not work if the function is extremely large.
5689 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5690 Addr, Op.getOperand(2), JTI);
5691 }
5692 if (isPositionIndependent() || Subtarget->isROPI()) {
5693 Addr =
5694 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5695 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5696 Chain = Addr.getValue(1);
5697 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5698 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5699 } else {
5700 Addr =
5701 DAG.getLoad(PTy, dl, Chain, Addr,
5702 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5703 Chain = Addr.getValue(1);
5704 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5705 }
5706}
5707
5708static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5709 EVT VT = Op.getValueType();
5710 SDLoc dl(Op);
5711
5712 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5713 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5714 return Op;
5715 return DAG.UnrollVectorOp(Op.getNode());
5716 }
5717
5718 const bool HasFullFP16 =
5719 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5720
5721 EVT NewTy;
5722 const EVT OpTy = Op.getOperand(0).getValueType();
5723 if (OpTy == MVT::v4f32)
5724 NewTy = MVT::v4i32;
5725 else if (OpTy == MVT::v4f16 && HasFullFP16)
5726 NewTy = MVT::v4i16;
5727 else if (OpTy == MVT::v8f16 && HasFullFP16)
5728 NewTy = MVT::v8i16;
5729 else
5730 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5730)
;
5731
5732 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5733 return DAG.UnrollVectorOp(Op.getNode());
5734
5735 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5736 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5737}
5738
5739SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5740 EVT VT = Op.getValueType();
5741 if (VT.isVector())
5742 return LowerVectorFP_TO_INT(Op, DAG);
5743
5744 bool IsStrict = Op->isStrictFPOpcode();
5745 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5746
5747 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5748 RTLIB::Libcall LC;
5749 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5750 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5751 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5752 Op.getValueType());
5753 else
5754 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5755 Op.getValueType());
5756 SDLoc Loc(Op);
5757 MakeLibCallOptions CallOptions;
5758 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5759 SDValue Result;
5760 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5761 CallOptions, Loc, Chain);
5762 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5763 }
5764
5765 // FIXME: Remove this when we have strict fp instruction selection patterns
5766 if (IsStrict) {
5767 SDLoc Loc(Op);
5768 SDValue Result =
5769 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5770 : ISD::FP_TO_UINT,
5771 Loc, Op.getValueType(), SrcVal);
5772 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5773 }
5774
5775 return Op;
5776}
5777
5778static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5779 EVT VT = Op.getValueType();
5780 SDLoc dl(Op);
5781
5782 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5783 if (VT.getVectorElementType() == MVT::f32)
5784 return Op;
5785 return DAG.UnrollVectorOp(Op.getNode());
5786 }
5787
5788 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5790, __extension__ __PRETTY_FUNCTION__))
5789 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5790, __extension__ __PRETTY_FUNCTION__))
5790 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5790, __extension__ __PRETTY_FUNCTION__))
;
5791
5792 const bool HasFullFP16 =
5793 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5794
5795 EVT DestVecType;
5796 if (VT == MVT::v4f32)
5797 DestVecType = MVT::v4i32;
5798 else if (VT == MVT::v4f16 && HasFullFP16)
5799 DestVecType = MVT::v4i16;
5800 else if (VT == MVT::v8f16 && HasFullFP16)
5801 DestVecType = MVT::v8i16;
5802 else
5803 return DAG.UnrollVectorOp(Op.getNode());
5804
5805 unsigned CastOpc;
5806 unsigned Opc;
5807 switch (Op.getOpcode()) {
5808 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5808)
;
5809 case ISD::SINT_TO_FP:
5810 CastOpc = ISD::SIGN_EXTEND;
5811 Opc = ISD::SINT_TO_FP;
5812 break;
5813 case ISD::UINT_TO_FP:
5814 CastOpc = ISD::ZERO_EXTEND;
5815 Opc = ISD::UINT_TO_FP;
5816 break;
5817 }
5818
5819 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5820 return DAG.getNode(Opc, dl, VT, Op);
5821}
5822
5823SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5824 EVT VT = Op.getValueType();
5825 if (VT.isVector())
5826 return LowerVectorINT_TO_FP(Op, DAG);
5827 if (isUnsupportedFloatingType(VT)) {
5828 RTLIB::Libcall LC;
5829 if (Op.getOpcode() == ISD::SINT_TO_FP)
5830 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5831 Op.getValueType());
5832 else
5833 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5834 Op.getValueType());
5835 MakeLibCallOptions CallOptions;
5836 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5837 CallOptions, SDLoc(Op)).first;
5838 }
5839
5840 return Op;
5841}
5842
5843SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5844 // Implement fcopysign with a fabs and a conditional fneg.
5845 SDValue Tmp0 = Op.getOperand(0);
5846 SDValue Tmp1 = Op.getOperand(1);
5847 SDLoc dl(Op);
5848 EVT VT = Op.getValueType();
5849 EVT SrcVT = Tmp1.getValueType();
5850 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5851 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5852 bool UseNEON = !InGPR && Subtarget->hasNEON();
5853
5854 if (UseNEON) {
5855 // Use VBSL to copy the sign bit.
5856 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5857 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5858 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5859 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5860 if (VT == MVT::f64)
5861 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5862 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5863 DAG.getConstant(32, dl, MVT::i32));
5864 else /*if (VT == MVT::f32)*/
5865 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5866 if (SrcVT == MVT::f32) {
5867 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5868 if (VT == MVT::f64)
5869 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5870 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5871 DAG.getConstant(32, dl, MVT::i32));
5872 } else if (VT == MVT::f32)
5873 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5874 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5875 DAG.getConstant(32, dl, MVT::i32));
5876 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5877 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5878
5879 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5880 dl, MVT::i32);
5881 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5882 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5883 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5884
5885 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5886 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5887 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5888 if (VT == MVT::f32) {
5889 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5890 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5891 DAG.getConstant(0, dl, MVT::i32));
5892 } else {
5893 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5894 }
5895
5896 return Res;
5897 }
5898
5899 // Bitcast operand 1 to i32.
5900 if (SrcVT == MVT::f64)
5901 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5902 Tmp1).getValue(1);
5903 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5904
5905 // Or in the signbit with integer operations.
5906 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5907 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5908 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5909 if (VT == MVT::f32) {
5910 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5911 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5912 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5913 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5914 }
5915
5916 // f64: Or the high part with signbit and then combine two parts.
5917 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5918 Tmp0);
5919 SDValue Lo = Tmp0.getValue(0);
5920 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5921 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5922 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5923}
5924
5925SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5926 MachineFunction &MF = DAG.getMachineFunction();
5927 MachineFrameInfo &MFI = MF.getFrameInfo();
5928 MFI.setReturnAddressIsTaken(true);
5929
5930 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5931 return SDValue();
5932
5933 EVT VT = Op.getValueType();
5934 SDLoc dl(Op);
5935 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5936 if (Depth) {
5937 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5938 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5939 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5940 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5941 MachinePointerInfo());
5942 }
5943
5944 // Return LR, which contains the return address. Mark it an implicit live-in.
5945 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5946 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5947}
5948
5949SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5950 const ARMBaseRegisterInfo &ARI =
5951 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5952 MachineFunction &MF = DAG.getMachineFunction();
5953 MachineFrameInfo &MFI = MF.getFrameInfo();
5954 MFI.setFrameAddressIsTaken(true);
5955
5956 EVT VT = Op.getValueType();
5957 SDLoc dl(Op); // FIXME probably not meaningful
5958 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5959 Register FrameReg = ARI.getFrameRegister(MF);
5960 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5961 while (Depth--)
5962 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5963 MachinePointerInfo());
5964 return FrameAddr;
5965}
5966
5967// FIXME? Maybe this could be a TableGen attribute on some registers and
5968// this table could be generated automatically from RegInfo.
5969Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5970 const MachineFunction &MF) const {
5971 Register Reg = StringSwitch<unsigned>(RegName)
5972 .Case("sp", ARM::SP)
5973 .Default(0);
5974 if (Reg)
5975 return Reg;
5976 report_fatal_error(Twine("Invalid register name \""
5977 + StringRef(RegName) + "\"."));
5978}
5979
5980// Result is 64 bit value so split into two 32 bit values and return as a
5981// pair of values.
5982static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5983 SelectionDAG &DAG) {
5984 SDLoc DL(N);
5985
5986 // This function is only supposed to be called for i64 type destination.
5987 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5988, __extension__ __PRETTY_FUNCTION__))
5988 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-13~++20210613111130+5be314f79ba7/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5988, __extension__ __PRETTY_FUNCTION__))
;
5989
5990 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5991 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5992 N->getOperand(0),
5993 N->getOperand(1));
5994
5995 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5996 Read.getValue(1)));
5997 Results.push_back(Read.getOperand(0));
5998}
5999
6000/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
6001/// When \p DstVT, the destination type of \p BC, is on the vector
6002/// register bank and the source of bitcast, \p Op, operates on the same bank,
6003/// it might be possible to combine them, such that everything stays on the
6004/// vector register bank.
6005/// \p return The node that would replace \p BT, if the combine
6006/// is possible.
6007static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
6008 SelectionDAG &DAG) {
6009 SDValue Op = BC->getOperand(0);
6010 EVT DstVT = BC->getValueType(0);
6011
6012 // The only vector instruction that can produce a scalar (remember,
6013 // since the bitcast was about to be turned into VMOVDRR, the source
6014 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
6015 // Moreover, we can do this combine only if there is one use.
6016 // Finally, if the destination type is not a vector, there is not