Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2626, column 20
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/ARM -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-08-28-193554-24367-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MachineValueType.h"
103#include "llvm/Support/MathExtras.h"
104#include "llvm/Support/raw_ostream.h"
105#include "llvm/Target/TargetMachine.h"
106#include "llvm/Target/TargetOptions.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <string>
114#include <tuple>
115#include <utility>
116#include <vector>
117
118using namespace llvm;
119using namespace llvm::PatternMatch;
120
121#define DEBUG_TYPE"arm-isel" "arm-isel"
122
123STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
124STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
125STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
126STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
127 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
128
129static cl::opt<bool>
130ARMInterworking("arm-interworking", cl::Hidden,
131 cl::desc("Enable / disable ARM interworking (for debugging only)"),
132 cl::init(true));
133
134static cl::opt<bool> EnableConstpoolPromotion(
135 "arm-promote-constant", cl::Hidden,
136 cl::desc("Enable / disable promotion of unnamed_addr constants into "
137 "constant pools"),
138 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
139static cl::opt<unsigned> ConstpoolPromotionMaxSize(
140 "arm-promote-constant-max-size", cl::Hidden,
141 cl::desc("Maximum size of constant to promote into a constant pool"),
142 cl::init(64));
143static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
144 "arm-promote-constant-max-total", cl::Hidden,
145 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
146 cl::init(128));
147
148cl::opt<unsigned>
149MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
150 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
151 cl::init(2));
152
153// The APCS parameter registers.
154static const MCPhysReg GPRArgRegs[] = {
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156};
157
158void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Neon does not support vector divide/remainder operations.
198 setOperationAction(ISD::SDIV, VT, Expand);
199 setOperationAction(ISD::UDIV, VT, Expand);
200 setOperationAction(ISD::FDIV, VT, Expand);
201 setOperationAction(ISD::SREM, VT, Expand);
202 setOperationAction(ISD::UREM, VT, Expand);
203 setOperationAction(ISD::FREM, VT, Expand);
204 setOperationAction(ISD::SDIVREM, VT, Expand);
205 setOperationAction(ISD::UDIVREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211 if (!VT.isFloatingPoint())
212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
213 setOperationAction(Opcode, VT, Legal);
214}
215
216void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
217 addRegisterClass(VT, &ARM::DPRRegClass);
218 addTypeForNEON(VT, MVT::f64);
219}
220
221void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
222 addRegisterClass(VT, &ARM::DPairRegClass);
223 addTypeForNEON(VT, MVT::v2f64);
224}
225
226void ARMTargetLowering::setAllExpand(MVT VT) {
227 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
228 setOperationAction(Opc, VT, Expand);
229
230 // We support these really simple operations even on types where all
231 // the actual arithmetic has to be broken down into simpler
232 // operations or turned into library calls.
233 setOperationAction(ISD::BITCAST, VT, Legal);
234 setOperationAction(ISD::LOAD, VT, Legal);
235 setOperationAction(ISD::STORE, VT, Legal);
236 setOperationAction(ISD::UNDEF, VT, Legal);
237}
238
239void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
240 LegalizeAction Action) {
241 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
244}
245
246void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
247 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
248
249 for (auto VT : IntTypes) {
250 addRegisterClass(VT, &ARM::MQPRRegClass);
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
255 setOperationAction(ISD::SHL, VT, Custom);
256 setOperationAction(ISD::SRA, VT, Custom);
257 setOperationAction(ISD::SRL, VT, Custom);
258 setOperationAction(ISD::SMIN, VT, Legal);
259 setOperationAction(ISD::SMAX, VT, Legal);
260 setOperationAction(ISD::UMIN, VT, Legal);
261 setOperationAction(ISD::UMAX, VT, Legal);
262 setOperationAction(ISD::ABS, VT, Legal);
263 setOperationAction(ISD::SETCC, VT, Custom);
264 setOperationAction(ISD::MLOAD, VT, Custom);
265 setOperationAction(ISD::MSTORE, VT, Legal);
266 setOperationAction(ISD::CTLZ, VT, Legal);
267 setOperationAction(ISD::CTTZ, VT, Custom);
268 setOperationAction(ISD::BITREVERSE, VT, Legal);
269 setOperationAction(ISD::BSWAP, VT, Legal);
270 setOperationAction(ISD::SADDSAT, VT, Legal);
271 setOperationAction(ISD::UADDSAT, VT, Legal);
272 setOperationAction(ISD::SSUBSAT, VT, Legal);
273 setOperationAction(ISD::USUBSAT, VT, Legal);
274 setOperationAction(ISD::ABDS, VT, Legal);
275 setOperationAction(ISD::ABDU, VT, Legal);
276
277 // No native support for these.
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SDIV, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
281 setOperationAction(ISD::SREM, VT, Expand);
282 setOperationAction(ISD::UDIVREM, VT, Expand);
283 setOperationAction(ISD::SDIVREM, VT, Expand);
284 setOperationAction(ISD::CTPOP, VT, Expand);
285 setOperationAction(ISD::SELECT, VT, Expand);
286 setOperationAction(ISD::SELECT_CC, VT, Expand);
287
288 // Vector reductions
289 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
290 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
291 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
292 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
293 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
295 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
296 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
297 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
298
299 if (!HasMVEFP) {
300 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
301 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
302 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
303 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
304 }
305
306 // Pre and Post inc are supported on loads and stores
307 for (unsigned im = (unsigned)ISD::PRE_INC;
308 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
309 setIndexedLoadAction(im, VT, Legal);
310 setIndexedStoreAction(im, VT, Legal);
311 setIndexedMaskedLoadAction(im, VT, Legal);
312 setIndexedMaskedStoreAction(im, VT, Legal);
313 }
314 }
315
316 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
317 for (auto VT : FloatTypes) {
318 addRegisterClass(VT, &ARM::MQPRRegClass);
319 if (!HasMVEFP)
320 setAllExpand(VT);
321
322 // These are legal or custom whether we have MVE.fp or not
323 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
324 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
325 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
327 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
328 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
329 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
330 setOperationAction(ISD::SETCC, VT, Custom);
331 setOperationAction(ISD::MLOAD, VT, Custom);
332 setOperationAction(ISD::MSTORE, VT, Legal);
333 setOperationAction(ISD::SELECT, VT, Expand);
334 setOperationAction(ISD::SELECT_CC, VT, Expand);
335
336 // Pre and Post inc are supported on loads and stores
337 for (unsigned im = (unsigned)ISD::PRE_INC;
338 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
339 setIndexedLoadAction(im, VT, Legal);
340 setIndexedStoreAction(im, VT, Legal);
341 setIndexedMaskedLoadAction(im, VT, Legal);
342 setIndexedMaskedStoreAction(im, VT, Legal);
343 }
344
345 if (HasMVEFP) {
346 setOperationAction(ISD::FMINNUM, VT, Legal);
347 setOperationAction(ISD::FMAXNUM, VT, Legal);
348 setOperationAction(ISD::FROUND, VT, Legal);
349 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
350 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
351 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
352 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
353
354 // No native support for these.
355 setOperationAction(ISD::FDIV, VT, Expand);
356 setOperationAction(ISD::FREM, VT, Expand);
357 setOperationAction(ISD::FSQRT, VT, Expand);
358 setOperationAction(ISD::FSIN, VT, Expand);
359 setOperationAction(ISD::FCOS, VT, Expand);
360 setOperationAction(ISD::FPOW, VT, Expand);
361 setOperationAction(ISD::FLOG, VT, Expand);
362 setOperationAction(ISD::FLOG2, VT, Expand);
363 setOperationAction(ISD::FLOG10, VT, Expand);
364 setOperationAction(ISD::FEXP, VT, Expand);
365 setOperationAction(ISD::FEXP2, VT, Expand);
366 setOperationAction(ISD::FNEARBYINT, VT, Expand);
367 }
368 }
369
370 // Custom Expand smaller than legal vector reductions to prevent false zero
371 // items being added.
372 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
373 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
374 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
375 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
376 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
377 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
378 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
379 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
380
381 // We 'support' these types up to bitcast/load/store level, regardless of
382 // MVE integer-only / float support. Only doing FP data processing on the FP
383 // vector types is inhibited at integer-only level.
384 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
385 for (auto VT : LongTypes) {
386 addRegisterClass(VT, &ARM::MQPRRegClass);
387 setAllExpand(VT);
388 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
390 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
391 }
392 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
393
394 // We can do bitwise operations on v2i64 vectors
395 setOperationAction(ISD::AND, MVT::v2i64, Legal);
396 setOperationAction(ISD::OR, MVT::v2i64, Legal);
397 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
398
399 // It is legal to extload from v4i8 to v4i16 or v4i32.
400 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
401 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
402 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
403
404 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
410
411 // Some truncating stores are legal too.
412 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
413 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
414 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
415
416 // Pre and Post inc on these are legal, given the correct extends
417 for (unsigned im = (unsigned)ISD::PRE_INC;
418 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
419 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
420 setIndexedLoadAction(im, VT, Legal);
421 setIndexedStoreAction(im, VT, Legal);
422 setIndexedMaskedLoadAction(im, VT, Legal);
423 setIndexedMaskedStoreAction(im, VT, Legal);
424 }
425 }
426
427 // Predicate types
428 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
429 for (auto VT : pTypes) {
430 addRegisterClass(VT, &ARM::VCCRRegClass);
431 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
432 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
433 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
434 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
435 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
436 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
437 setOperationAction(ISD::SETCC, VT, Custom);
438 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
439 setOperationAction(ISD::LOAD, VT, Custom);
440 setOperationAction(ISD::STORE, VT, Custom);
441 setOperationAction(ISD::TRUNCATE, VT, Custom);
442 setOperationAction(ISD::VSELECT, VT, Expand);
443 setOperationAction(ISD::SELECT, VT, Expand);
444 }
445 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
446 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
447 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
449 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
450 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
451 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
452 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
453}
454
455ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
456 const ARMSubtarget &STI)
457 : TargetLowering(TM), Subtarget(&STI) {
458 RegInfo = Subtarget->getRegisterInfo();
459 Itins = Subtarget->getInstrItineraryData();
460
461 setBooleanContents(ZeroOrOneBooleanContent);
462 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
463
464 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
465 !Subtarget->isTargetWatchOS()) {
466 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
467 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
468 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
469 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
470 : CallingConv::ARM_AAPCS);
471 }
472
473 if (Subtarget->isTargetMachO()) {
474 // Uses VFP for Thumb libfuncs if available.
475 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
476 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
477 static const struct {
478 const RTLIB::Libcall Op;
479 const char * const Name;
480 const ISD::CondCode Cond;
481 } LibraryCalls[] = {
482 // Single-precision floating-point arithmetic.
483 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
484 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
485 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
486 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
487
488 // Double-precision floating-point arithmetic.
489 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
490 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
491 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
492 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
493
494 // Single-precision comparisons.
495 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
496 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
497 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
498 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
499 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
500 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
501 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
502
503 // Double-precision comparisons.
504 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
505 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
506 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
507 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
508 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
509 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
510 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
511
512 // Floating-point to integer conversions.
513 // i64 conversions are done via library routines even when generating VFP
514 // instructions, so use the same ones.
515 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
516 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
517 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
518 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
519
520 // Conversions between floating types.
521 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
522 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
523
524 // Integer to floating-point conversions.
525 // i64 conversions are done via library routines even when generating VFP
526 // instructions, so use the same ones.
527 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
528 // e.g., __floatunsidf vs. __floatunssidfvfp.
529 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
530 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
531 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
532 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
533 };
534
535 for (const auto &LC : LibraryCalls) {
536 setLibcallName(LC.Op, LC.Name);
537 if (LC.Cond != ISD::SETCC_INVALID)
538 setCmpLibcallCC(LC.Op, LC.Cond);
539 }
540 }
541 }
542
543 // These libcalls are not available in 32-bit.
544 setLibcallName(RTLIB::SHL_I128, nullptr);
545 setLibcallName(RTLIB::SRL_I128, nullptr);
546 setLibcallName(RTLIB::SRA_I128, nullptr);
547 setLibcallName(RTLIB::MUL_I128, nullptr);
548 setLibcallName(RTLIB::MULO_I64, nullptr);
549 setLibcallName(RTLIB::MULO_I128, nullptr);
550
551 // RTLIB
552 if (Subtarget->isAAPCS_ABI() &&
553 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
554 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
555 static const struct {
556 const RTLIB::Libcall Op;
557 const char * const Name;
558 const CallingConv::ID CC;
559 const ISD::CondCode Cond;
560 } LibraryCalls[] = {
561 // Double-precision floating-point arithmetic helper functions
562 // RTABI chapter 4.1.2, Table 2
563 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
565 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
566 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
567
568 // Double-precision floating-point comparison helper functions
569 // RTABI chapter 4.1.2, Table 3
570 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
571 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
572 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
573 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
574 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
575 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
576 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
577
578 // Single-precision floating-point arithmetic helper functions
579 // RTABI chapter 4.1.2, Table 4
580 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
582 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
583 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
584
585 // Single-precision floating-point comparison helper functions
586 // RTABI chapter 4.1.2, Table 5
587 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
588 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
589 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
590 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
591 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
592 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
593 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
594
595 // Floating-point to integer conversions.
596 // RTABI chapter 4.1.2, Table 6
597 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
600 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
601 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
605
606 // Conversions between floating types.
607 // RTABI chapter 4.1.2, Table 7
608 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611
612 // Integer to floating-point conversions.
613 // RTABI chapter 4.1.2, Table 8
614 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
617 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
618 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
619 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
620 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
621 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
622
623 // Long long helper functions
624 // RTABI chapter 4.2, Table 9
625 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629
630 // Integer division functions
631 // RTABI chapter 4.3.1
632 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
634 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
635 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
639 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
640 };
641
642 for (const auto &LC : LibraryCalls) {
643 setLibcallName(LC.Op, LC.Name);
644 setLibcallCallingConv(LC.Op, LC.CC);
645 if (LC.Cond != ISD::SETCC_INVALID)
646 setCmpLibcallCC(LC.Op, LC.Cond);
647 }
648
649 // EABI dependent RTLIB
650 if (TM.Options.EABIVersion == EABI::EABI4 ||
651 TM.Options.EABIVersion == EABI::EABI5) {
652 static const struct {
653 const RTLIB::Libcall Op;
654 const char *const Name;
655 const CallingConv::ID CC;
656 const ISD::CondCode Cond;
657 } MemOpsLibraryCalls[] = {
658 // Memory operations
659 // RTABI chapter 4.3.4
660 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
662 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
663 };
664
665 for (const auto &LC : MemOpsLibraryCalls) {
666 setLibcallName(LC.Op, LC.Name);
667 setLibcallCallingConv(LC.Op, LC.CC);
668 if (LC.Cond != ISD::SETCC_INVALID)
669 setCmpLibcallCC(LC.Op, LC.Cond);
670 }
671 }
672 }
673
674 if (Subtarget->isTargetWindows()) {
675 static const struct {
676 const RTLIB::Libcall Op;
677 const char * const Name;
678 const CallingConv::ID CC;
679 } LibraryCalls[] = {
680 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
681 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
682 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
683 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
684 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
685 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
686 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
687 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
688 };
689
690 for (const auto &LC : LibraryCalls) {
691 setLibcallName(LC.Op, LC.Name);
692 setLibcallCallingConv(LC.Op, LC.CC);
693 }
694 }
695
696 // Use divmod compiler-rt calls for iOS 5.0 and later.
697 if (Subtarget->isTargetMachO() &&
698 !(Subtarget->isTargetIOS() &&
699 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
700 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
701 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
702 }
703
704 // The half <-> float conversion functions are always soft-float on
705 // non-watchos platforms, but are needed for some targets which use a
706 // hard-float calling convention by default.
707 if (!Subtarget->isTargetWatchABI()) {
708 if (Subtarget->isAAPCS_ABI()) {
709 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
710 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
711 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
712 } else {
713 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
714 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
715 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
716 }
717 }
718
719 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
720 // a __gnu_ prefix (which is the default).
721 if (Subtarget->isTargetAEABI()) {
722 static const struct {
723 const RTLIB::Libcall Op;
724 const char * const Name;
725 const CallingConv::ID CC;
726 } LibraryCalls[] = {
727 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
728 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
729 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
730 };
731
732 for (const auto &LC : LibraryCalls) {
733 setLibcallName(LC.Op, LC.Name);
734 setLibcallCallingConv(LC.Op, LC.CC);
735 }
736 }
737
738 if (Subtarget->isThumb1Only())
739 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
740 else
741 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
742
743 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
744 Subtarget->hasFPRegs()) {
745 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
746 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
747 if (!Subtarget->hasVFP2Base())
748 setAllExpand(MVT::f32);
749 if (!Subtarget->hasFP64())
750 setAllExpand(MVT::f64);
751 }
752
753 if (Subtarget->hasFullFP16()) {
754 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
755 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
756 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
757
758 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
759 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
760 }
761
762 if (Subtarget->hasBF16()) {
763 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
764 setAllExpand(MVT::bf16);
765 if (!Subtarget->hasFullFP16())
766 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
767 }
768
769 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
770 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
771 setTruncStoreAction(VT, InnerVT, Expand);
772 addAllExtLoads(VT, InnerVT, Expand);
773 }
774
775 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
776 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
777
778 setOperationAction(ISD::BSWAP, VT, Expand);
779 }
780
781 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
782 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
783
784 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
785 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
786
787 if (Subtarget->hasMVEIntegerOps())
788 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
789
790 // Combine low-overhead loop intrinsics so that we can lower i1 types.
791 if (Subtarget->hasLOB()) {
792 setTargetDAGCombine(ISD::BRCOND);
793 setTargetDAGCombine(ISD::BR_CC);
794 }
795
796 if (Subtarget->hasNEON()) {
797 addDRTypeForNEON(MVT::v2f32);
798 addDRTypeForNEON(MVT::v8i8);
799 addDRTypeForNEON(MVT::v4i16);
800 addDRTypeForNEON(MVT::v2i32);
801 addDRTypeForNEON(MVT::v1i64);
802
803 addQRTypeForNEON(MVT::v4f32);
804 addQRTypeForNEON(MVT::v2f64);
805 addQRTypeForNEON(MVT::v16i8);
806 addQRTypeForNEON(MVT::v8i16);
807 addQRTypeForNEON(MVT::v4i32);
808 addQRTypeForNEON(MVT::v2i64);
809
810 if (Subtarget->hasFullFP16()) {
811 addQRTypeForNEON(MVT::v8f16);
812 addDRTypeForNEON(MVT::v4f16);
813 }
814
815 if (Subtarget->hasBF16()) {
816 addQRTypeForNEON(MVT::v8bf16);
817 addDRTypeForNEON(MVT::v4bf16);
818 }
819 }
820
821 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
822 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
823 // none of Neon, MVE or VFP supports any arithmetic operations on it.
824 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
825 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
826 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
827 // FIXME: Code duplication: FDIV and FREM are expanded always, see
828 // ARMTargetLowering::addTypeForNEON method for details.
829 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
830 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
831 // FIXME: Create unittest.
832 // In another words, find a way when "copysign" appears in DAG with vector
833 // operands.
834 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
835 // FIXME: Code duplication: SETCC has custom operation action, see
836 // ARMTargetLowering::addTypeForNEON method for details.
837 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
838 // FIXME: Create unittest for FNEG and for FABS.
839 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
840 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
841 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
842 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
843 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
844 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
845 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
846 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
847 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
848 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
849 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
850 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
851 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
852 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
853 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
854 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
855 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
856 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
857 }
858
859 if (Subtarget->hasNEON()) {
860 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
861 // supported for v4f32.
862 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
863 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
864 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
865 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
866 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
867 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
868 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
869 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
870 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
871 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
872 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
873 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
874 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
875 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
876
877 // Mark v2f32 intrinsics.
878 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
879 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
880 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
881 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
882 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
883 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
884 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
885 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
886 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
887 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
888 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
889 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
890 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
891 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
892
893 // Neon does not support some operations on v1i64 and v2i64 types.
894 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
895 // Custom handling for some quad-vector types to detect VMULL.
896 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
897 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
898 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
899 // Custom handling for some vector types to avoid expensive expansions
900 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
901 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
902 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
903 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
904 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
905 // a destination type that is wider than the source, and nor does
906 // it have a FP_TO_[SU]INT instruction with a narrower destination than
907 // source.
908 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
909 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
910 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
911 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
912 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
913 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
914 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
916
917 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
918 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
919
920 // NEON does not have single instruction CTPOP for vectors with element
921 // types wider than 8-bits. However, custom lowering can leverage the
922 // v8i8/v16i8 vcnt instruction.
923 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
924 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
925 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
926 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
927 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
928 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
929
930 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
931 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
932
933 // NEON does not have single instruction CTTZ for vectors.
934 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
935 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
936 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
937 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
938
939 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
940 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
941 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
942 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
943
944 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
945 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
946 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
947 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
948
949 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
950 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
951 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
952 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
953
954 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
955 setOperationAction(ISD::MULHS, VT, Expand);
956 setOperationAction(ISD::MULHU, VT, Expand);
957 }
958
959 // NEON only has FMA instructions as of VFP4.
960 if (!Subtarget->hasVFP4Base()) {
961 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
962 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
963 }
964
965 setTargetDAGCombine(ISD::SHL);
966 setTargetDAGCombine(ISD::SRL);
967 setTargetDAGCombine(ISD::SRA);
968 setTargetDAGCombine(ISD::FP_TO_SINT);
969 setTargetDAGCombine(ISD::FP_TO_UINT);
970 setTargetDAGCombine(ISD::FDIV);
971 setTargetDAGCombine(ISD::LOAD);
972
973 // It is legal to extload from v4i8 to v4i16 or v4i32.
974 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
975 MVT::v2i32}) {
976 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
977 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
980 }
981 }
982 }
983
984 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
985 setTargetDAGCombine(ISD::BUILD_VECTOR);
986 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
987 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
988 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
989 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
990 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
991 setTargetDAGCombine(ISD::STORE);
992 setTargetDAGCombine(ISD::SIGN_EXTEND);
993 setTargetDAGCombine(ISD::ZERO_EXTEND);
994 setTargetDAGCombine(ISD::ANY_EXTEND);
995 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
996 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
997 setTargetDAGCombine(ISD::INTRINSIC_VOID);
998 setTargetDAGCombine(ISD::VECREDUCE_ADD);
999 setTargetDAGCombine(ISD::ADD);
1000 setTargetDAGCombine(ISD::BITCAST);
1001 }
1002 if (Subtarget->hasMVEIntegerOps()) {
1003 setTargetDAGCombine(ISD::SMIN);
1004 setTargetDAGCombine(ISD::UMIN);
1005 setTargetDAGCombine(ISD::SMAX);
1006 setTargetDAGCombine(ISD::UMAX);
1007 setTargetDAGCombine(ISD::FP_EXTEND);
1008 setTargetDAGCombine(ISD::SELECT);
1009 setTargetDAGCombine(ISD::SELECT_CC);
1010 }
1011
1012 if (!Subtarget->hasFP64()) {
1013 // When targeting a floating-point unit with only single-precision
1014 // operations, f64 is legal for the few double-precision instructions which
1015 // are present However, no double-precision operations other than moves,
1016 // loads and stores are provided by the hardware.
1017 setOperationAction(ISD::FADD, MVT::f64, Expand);
1018 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1019 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1020 setOperationAction(ISD::FMA, MVT::f64, Expand);
1021 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1022 setOperationAction(ISD::FREM, MVT::f64, Expand);
1023 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1024 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1025 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1026 setOperationAction(ISD::FABS, MVT::f64, Expand);
1027 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1028 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1029 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1030 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1031 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1032 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1033 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1034 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1035 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1036 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1037 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1038 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1039 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1040 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1042 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1043 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1044 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1045 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1046 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1047 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1048 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1049 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1050 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1051 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1052 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1053 }
1054
1055 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1056 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1057 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1058 if (Subtarget->hasFullFP16()) {
1059 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1060 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1061 }
1062 }
1063
1064 if (!Subtarget->hasFP16()) {
1065 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1066 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1067 }
1068
1069 computeRegisterProperties(Subtarget->getRegisterInfo());
1070
1071 // ARM does not have floating-point extending loads.
1072 for (MVT VT : MVT::fp_valuetypes()) {
1073 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1074 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1075 }
1076
1077 // ... or truncating stores
1078 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1079 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1080 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1081
1082 // ARM does not have i1 sign extending load.
1083 for (MVT VT : MVT::integer_valuetypes())
1084 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1085
1086 // ARM supports all 4 flavors of integer indexed load / store.
1087 if (!Subtarget->isThumb1Only()) {
1088 for (unsigned im = (unsigned)ISD::PRE_INC;
1089 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1090 setIndexedLoadAction(im, MVT::i1, Legal);
1091 setIndexedLoadAction(im, MVT::i8, Legal);
1092 setIndexedLoadAction(im, MVT::i16, Legal);
1093 setIndexedLoadAction(im, MVT::i32, Legal);
1094 setIndexedStoreAction(im, MVT::i1, Legal);
1095 setIndexedStoreAction(im, MVT::i8, Legal);
1096 setIndexedStoreAction(im, MVT::i16, Legal);
1097 setIndexedStoreAction(im, MVT::i32, Legal);
1098 }
1099 } else {
1100 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1101 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1102 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1103 }
1104
1105 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1106 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1107 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1108 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1109
1110 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1111 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1112 if (Subtarget->hasDSP()) {
1113 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1114 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1115 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1116 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1117 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1118 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1119 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1120 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1121 }
1122 if (Subtarget->hasBaseDSP()) {
1123 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1124 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1125 }
1126
1127 // i64 operation support.
1128 setOperationAction(ISD::MUL, MVT::i64, Expand);
1129 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1130 if (Subtarget->isThumb1Only()) {
1131 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1132 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1133 }
1134 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1135 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1136 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1137
1138 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1139 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1140 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1141 setOperationAction(ISD::SRL, MVT::i64, Custom);
1142 setOperationAction(ISD::SRA, MVT::i64, Custom);
1143 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1144 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1145 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1146 setOperationAction(ISD::STORE, MVT::i64, Custom);
1147
1148 // MVE lowers 64 bit shifts to lsll and lsrl
1149 // assuming that ISD::SRL and SRA of i64 are already marked custom
1150 if (Subtarget->hasMVEIntegerOps())
1151 setOperationAction(ISD::SHL, MVT::i64, Custom);
1152
1153 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1154 if (Subtarget->isThumb1Only()) {
1155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1158 }
1159
1160 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1161 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1162
1163 // ARM does not have ROTL.
1164 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1165 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1166 setOperationAction(ISD::ROTL, VT, Expand);
1167 setOperationAction(ISD::ROTR, VT, Expand);
1168 }
1169 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1170 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1171 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1172 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1173 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1174 }
1175
1176 // @llvm.readcyclecounter requires the Performance Monitors extension.
1177 // Default to the 0 expansion on unsupported platforms.
1178 // FIXME: Technically there are older ARM CPUs that have
1179 // implementation-specific ways of obtaining this information.
1180 if (Subtarget->hasPerfMon())
1181 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1182
1183 // Only ARMv6 has BSWAP.
1184 if (!Subtarget->hasV6Ops())
1185 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1186
1187 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1188 : Subtarget->hasDivideInARMMode();
1189 if (!hasDivide) {
1190 // These are expanded into libcalls if the cpu doesn't have HW divider.
1191 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1192 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1193 }
1194
1195 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1196 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1197 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1198
1199 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1200 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1201 }
1202
1203 setOperationAction(ISD::SREM, MVT::i32, Expand);
1204 setOperationAction(ISD::UREM, MVT::i32, Expand);
1205
1206 // Register based DivRem for AEABI (RTABI 4.2)
1207 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1208 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1209 Subtarget->isTargetWindows()) {
1210 setOperationAction(ISD::SREM, MVT::i64, Custom);
1211 setOperationAction(ISD::UREM, MVT::i64, Custom);
1212 HasStandaloneRem = false;
1213
1214 if (Subtarget->isTargetWindows()) {
1215 const struct {
1216 const RTLIB::Libcall Op;
1217 const char * const Name;
1218 const CallingConv::ID CC;
1219 } LibraryCalls[] = {
1220 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1221 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1222 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1223 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1224
1225 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1226 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1227 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1228 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1229 };
1230
1231 for (const auto &LC : LibraryCalls) {
1232 setLibcallName(LC.Op, LC.Name);
1233 setLibcallCallingConv(LC.Op, LC.CC);
1234 }
1235 } else {
1236 const struct {
1237 const RTLIB::Libcall Op;
1238 const char * const Name;
1239 const CallingConv::ID CC;
1240 } LibraryCalls[] = {
1241 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1242 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1243 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1244 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1245
1246 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1247 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1248 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1249 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1250 };
1251
1252 for (const auto &LC : LibraryCalls) {
1253 setLibcallName(LC.Op, LC.Name);
1254 setLibcallCallingConv(LC.Op, LC.CC);
1255 }
1256 }
1257
1258 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1259 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1260 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1261 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1262 } else {
1263 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1264 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1265 }
1266
1267 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1268 // MSVCRT doesn't have powi; fall back to pow
1269 setLibcallName(RTLIB::POWI_F32, nullptr);
1270 setLibcallName(RTLIB::POWI_F64, nullptr);
1271 }
1272
1273 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1274 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1277
1278 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1279 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1280
1281 // Use the default implementation.
1282 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1283 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1284 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1285 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1286 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1287 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1288
1289 if (Subtarget->isTargetWindows())
1290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1291 else
1292 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1293
1294 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1295 // the default expansion.
1296 InsertFencesForAtomic = false;
1297 if (Subtarget->hasAnyDataBarrier() &&
1298 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1299 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1300 // to ldrex/strex loops already.
1301 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1302 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1303 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1304
1305 // On v8, we have particularly efficient implementations of atomic fences
1306 // if they can be combined with nearby atomic loads and stores.
1307 if (!Subtarget->hasAcquireRelease() ||
1308 getTargetMachine().getOptLevel() == 0) {
1309 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1310 InsertFencesForAtomic = true;
1311 }
1312 } else {
1313 // If there's anything we can use as a barrier, go through custom lowering
1314 // for ATOMIC_FENCE.
1315 // If target has DMB in thumb, Fences can be inserted.
1316 if (Subtarget->hasDataBarrier())
1317 InsertFencesForAtomic = true;
1318
1319 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1320 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1321
1322 // Set them all for expansion, which will force libcalls.
1323 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1324 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1325 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1326 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1327 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1328 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1329 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1330 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1331 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1332 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1333 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1334 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1335 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1336 // Unordered/Monotonic case.
1337 if (!InsertFencesForAtomic) {
1338 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1339 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1340 }
1341 }
1342
1343 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1344
1345 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1346 if (!Subtarget->hasV6Ops()) {
1347 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1348 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1349 }
1350 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1351
1352 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1353 !Subtarget->isThumb1Only()) {
1354 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1355 // iff target supports vfp2.
1356 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1357 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1358 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1359 }
1360
1361 // We want to custom lower some of our intrinsics.
1362 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1363 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1364 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1365 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1366 if (Subtarget->useSjLjEH())
1367 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1368
1369 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1370 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1371 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1372 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1373 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1374 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1375 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1376 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1377 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1378 if (Subtarget->hasFullFP16()) {
1379 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1380 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1381 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1382 }
1383
1384 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1385
1386 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1387 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1388 if (Subtarget->hasFullFP16())
1389 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1390 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1391 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1392 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1393
1394 // We don't support sin/cos/fmod/copysign/pow
1395 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1396 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1397 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1398 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1399 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1400 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1401 setOperationAction(ISD::FREM, MVT::f64, Expand);
1402 setOperationAction(ISD::FREM, MVT::f32, Expand);
1403 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1404 !Subtarget->isThumb1Only()) {
1405 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1406 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1407 }
1408 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1409 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1410
1411 if (!Subtarget->hasVFP4Base()) {
1412 setOperationAction(ISD::FMA, MVT::f64, Expand);
1413 setOperationAction(ISD::FMA, MVT::f32, Expand);
1414 }
1415
1416 // Various VFP goodness
1417 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1418 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1419 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1420 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1421 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1422 }
1423
1424 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1425 if (!Subtarget->hasFP16()) {
1426 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1427 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1428 }
1429
1430 // Strict floating-point comparisons need custom lowering.
1431 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1432 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1433 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1434 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1435 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1436 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1437 }
1438
1439 // Use __sincos_stret if available.
1440 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1441 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1442 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1443 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1444 }
1445
1446 // FP-ARMv8 implements a lot of rounding-like FP operations.
1447 if (Subtarget->hasFPARMv8Base()) {
1448 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1449 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1450 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1451 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1453 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1454 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1455 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1456 if (Subtarget->hasNEON()) {
1457 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1458 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1459 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1460 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1461 }
1462
1463 if (Subtarget->hasFP64()) {
1464 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1465 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1466 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1467 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1468 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1469 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1470 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1471 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1472 }
1473 }
1474
1475 // FP16 often need to be promoted to call lib functions
1476 if (Subtarget->hasFullFP16()) {
1477 setOperationAction(ISD::FREM, MVT::f16, Promote);
1478 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1479 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1480 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1481 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1482 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1483 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1484 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1485 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1486 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1487 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1488 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1489
1490 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1491 }
1492
1493 if (Subtarget->hasNEON()) {
1494 // vmin and vmax aren't available in a scalar form, so we can use
1495 // a NEON instruction with an undef lane instead. This has a performance
1496 // penalty on some cores, so we don't do this unless we have been
1497 // asked to by the core tuning model.
1498 if (Subtarget->useNEONForSinglePrecisionFP()) {
1499 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1500 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1501 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1502 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1503 }
1504 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1505 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1506 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1507 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1508
1509 if (Subtarget->hasFullFP16()) {
1510 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1511 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1512 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1513 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1514
1515 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1516 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1517 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1518 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1519 }
1520 }
1521
1522 // We have target-specific dag combine patterns for the following nodes:
1523 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::SUB);
1526 setTargetDAGCombine(ISD::MUL);
1527 setTargetDAGCombine(ISD::AND);
1528 setTargetDAGCombine(ISD::OR);
1529 setTargetDAGCombine(ISD::XOR);
1530
1531 if (Subtarget->hasMVEIntegerOps())
1532 setTargetDAGCombine(ISD::VSELECT);
1533
1534 if (Subtarget->hasV6Ops())
1535 setTargetDAGCombine(ISD::SRL);
1536 if (Subtarget->isThumb1Only())
1537 setTargetDAGCombine(ISD::SHL);
1538
1539 setStackPointerRegisterToSaveRestore(ARM::SP);
1540
1541 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1542 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1543 setSchedulingPreference(Sched::RegPressure);
1544 else
1545 setSchedulingPreference(Sched::Hybrid);
1546
1547 //// temporary - rewrite interface to use type
1548 MaxStoresPerMemset = 8;
1549 MaxStoresPerMemsetOptSize = 4;
1550 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1551 MaxStoresPerMemcpyOptSize = 2;
1552 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1553 MaxStoresPerMemmoveOptSize = 2;
1554
1555 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1556 // are at least 4 bytes aligned.
1557 setMinStackArgumentAlignment(Align(4));
1558
1559 // Prefer likely predicted branches to selects on out-of-order cores.
1560 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1561
1562 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1563
1564 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1565
1566 if (Subtarget->isThumb() || Subtarget->isThumb2())
1567 setTargetDAGCombine(ISD::ABS);
1568}
1569
1570bool ARMTargetLowering::useSoftFloat() const {
1571 return Subtarget->useSoftFloat();
1572}
1573
1574// FIXME: It might make sense to define the representative register class as the
1575// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1576// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1577// SPR's representative would be DPR_VFP2. This should work well if register
1578// pressure tracking were modified such that a register use would increment the
1579// pressure of the register class's representative and all of it's super
1580// classes' representatives transitively. We have not implemented this because
1581// of the difficulty prior to coalescing of modeling operand register classes
1582// due to the common occurrence of cross class copies and subregister insertions
1583// and extractions.
1584std::pair<const TargetRegisterClass *, uint8_t>
1585ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1586 MVT VT) const {
1587 const TargetRegisterClass *RRC = nullptr;
1588 uint8_t Cost = 1;
1589 switch (VT.SimpleTy) {
1590 default:
1591 return TargetLowering::findRepresentativeClass(TRI, VT);
1592 // Use DPR as representative register class for all floating point
1593 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1594 // the cost is 1 for both f32 and f64.
1595 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1596 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1597 RRC = &ARM::DPRRegClass;
1598 // When NEON is used for SP, only half of the register file is available
1599 // because operations that define both SP and DP results will be constrained
1600 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1601 // coalescing by double-counting the SP regs. See the FIXME above.
1602 if (Subtarget->useNEONForSinglePrecisionFP())
1603 Cost = 2;
1604 break;
1605 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1606 case MVT::v4f32: case MVT::v2f64:
1607 RRC = &ARM::DPRRegClass;
1608 Cost = 2;
1609 break;
1610 case MVT::v4i64:
1611 RRC = &ARM::DPRRegClass;
1612 Cost = 4;
1613 break;
1614 case MVT::v8i64:
1615 RRC = &ARM::DPRRegClass;
1616 Cost = 8;
1617 break;
1618 }
1619 return std::make_pair(RRC, Cost);
1620}
1621
1622const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1623#define MAKE_CASE(V) \
1624 case V: \
1625 return #V;
1626 switch ((ARMISD::NodeType)Opcode) {
1627 case ARMISD::FIRST_NUMBER:
1628 break;
1629 MAKE_CASE(ARMISD::Wrapper)
1630 MAKE_CASE(ARMISD::WrapperPIC)
1631 MAKE_CASE(ARMISD::WrapperJT)
1632 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1633 MAKE_CASE(ARMISD::CALL)
1634 MAKE_CASE(ARMISD::CALL_PRED)
1635 MAKE_CASE(ARMISD::CALL_NOLINK)
1636 MAKE_CASE(ARMISD::tSECALL)
1637 MAKE_CASE(ARMISD::BRCOND)
1638 MAKE_CASE(ARMISD::BR_JT)
1639 MAKE_CASE(ARMISD::BR2_JT)
1640 MAKE_CASE(ARMISD::RET_FLAG)
1641 MAKE_CASE(ARMISD::SERET_FLAG)
1642 MAKE_CASE(ARMISD::INTRET_FLAG)
1643 MAKE_CASE(ARMISD::PIC_ADD)
1644 MAKE_CASE(ARMISD::CMP)
1645 MAKE_CASE(ARMISD::CMN)
1646 MAKE_CASE(ARMISD::CMPZ)
1647 MAKE_CASE(ARMISD::CMPFP)
1648 MAKE_CASE(ARMISD::CMPFPE)
1649 MAKE_CASE(ARMISD::CMPFPw0)
1650 MAKE_CASE(ARMISD::CMPFPEw0)
1651 MAKE_CASE(ARMISD::BCC_i64)
1652 MAKE_CASE(ARMISD::FMSTAT)
1653 MAKE_CASE(ARMISD::CMOV)
1654 MAKE_CASE(ARMISD::SUBS)
1655 MAKE_CASE(ARMISD::SSAT)
1656 MAKE_CASE(ARMISD::USAT)
1657 MAKE_CASE(ARMISD::ASRL)
1658 MAKE_CASE(ARMISD::LSRL)
1659 MAKE_CASE(ARMISD::LSLL)
1660 MAKE_CASE(ARMISD::SRL_FLAG)
1661 MAKE_CASE(ARMISD::SRA_FLAG)
1662 MAKE_CASE(ARMISD::RRX)
1663 MAKE_CASE(ARMISD::ADDC)
1664 MAKE_CASE(ARMISD::ADDE)
1665 MAKE_CASE(ARMISD::SUBC)
1666 MAKE_CASE(ARMISD::SUBE)
1667 MAKE_CASE(ARMISD::LSLS)
1668 MAKE_CASE(ARMISD::VMOVRRD)
1669 MAKE_CASE(ARMISD::VMOVDRR)
1670 MAKE_CASE(ARMISD::VMOVhr)
1671 MAKE_CASE(ARMISD::VMOVrh)
1672 MAKE_CASE(ARMISD::VMOVSR)
1673 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1674 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1675 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1676 MAKE_CASE(ARMISD::TC_RETURN)
1677 MAKE_CASE(ARMISD::THREAD_POINTER)
1678 MAKE_CASE(ARMISD::DYN_ALLOC)
1679 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1680 MAKE_CASE(ARMISD::PRELOAD)
1681 MAKE_CASE(ARMISD::LDRD)
1682 MAKE_CASE(ARMISD::STRD)
1683 MAKE_CASE(ARMISD::WIN__CHKSTK)
1684 MAKE_CASE(ARMISD::WIN__DBZCHK)
1685 MAKE_CASE(ARMISD::PREDICATE_CAST)
1686 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1687 MAKE_CASE(ARMISD::MVESEXT)
1688 MAKE_CASE(ARMISD::MVEZEXT)
1689 MAKE_CASE(ARMISD::MVETRUNC)
1690 MAKE_CASE(ARMISD::VCMP)
1691 MAKE_CASE(ARMISD::VCMPZ)
1692 MAKE_CASE(ARMISD::VTST)
1693 MAKE_CASE(ARMISD::VSHLs)
1694 MAKE_CASE(ARMISD::VSHLu)
1695 MAKE_CASE(ARMISD::VSHLIMM)
1696 MAKE_CASE(ARMISD::VSHRsIMM)
1697 MAKE_CASE(ARMISD::VSHRuIMM)
1698 MAKE_CASE(ARMISD::VRSHRsIMM)
1699 MAKE_CASE(ARMISD::VRSHRuIMM)
1700 MAKE_CASE(ARMISD::VRSHRNIMM)
1701 MAKE_CASE(ARMISD::VQSHLsIMM)
1702 MAKE_CASE(ARMISD::VQSHLuIMM)
1703 MAKE_CASE(ARMISD::VQSHLsuIMM)
1704 MAKE_CASE(ARMISD::VQSHRNsIMM)
1705 MAKE_CASE(ARMISD::VQSHRNuIMM)
1706 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1707 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1708 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1709 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1710 MAKE_CASE(ARMISD::VSLIIMM)
1711 MAKE_CASE(ARMISD::VSRIIMM)
1712 MAKE_CASE(ARMISD::VGETLANEu)
1713 MAKE_CASE(ARMISD::VGETLANEs)
1714 MAKE_CASE(ARMISD::VMOVIMM)
1715 MAKE_CASE(ARMISD::VMVNIMM)
1716 MAKE_CASE(ARMISD::VMOVFPIMM)
1717 MAKE_CASE(ARMISD::VDUP)
1718 MAKE_CASE(ARMISD::VDUPLANE)
1719 MAKE_CASE(ARMISD::VEXT)
1720 MAKE_CASE(ARMISD::VREV64)
1721 MAKE_CASE(ARMISD::VREV32)
1722 MAKE_CASE(ARMISD::VREV16)
1723 MAKE_CASE(ARMISD::VZIP)
1724 MAKE_CASE(ARMISD::VUZP)
1725 MAKE_CASE(ARMISD::VTRN)
1726 MAKE_CASE(ARMISD::VTBL1)
1727 MAKE_CASE(ARMISD::VTBL2)
1728 MAKE_CASE(ARMISD::VMOVN)
1729 MAKE_CASE(ARMISD::VQMOVNs)
1730 MAKE_CASE(ARMISD::VQMOVNu)
1731 MAKE_CASE(ARMISD::VCVTN)
1732 MAKE_CASE(ARMISD::VCVTL)
1733 MAKE_CASE(ARMISD::VIDUP)
1734 MAKE_CASE(ARMISD::VMULLs)
1735 MAKE_CASE(ARMISD::VMULLu)
1736 MAKE_CASE(ARMISD::VQDMULH)
1737 MAKE_CASE(ARMISD::VADDVs)
1738 MAKE_CASE(ARMISD::VADDVu)
1739 MAKE_CASE(ARMISD::VADDVps)
1740 MAKE_CASE(ARMISD::VADDVpu)
1741 MAKE_CASE(ARMISD::VADDLVs)
1742 MAKE_CASE(ARMISD::VADDLVu)
1743 MAKE_CASE(ARMISD::VADDLVAs)
1744 MAKE_CASE(ARMISD::VADDLVAu)
1745 MAKE_CASE(ARMISD::VADDLVps)
1746 MAKE_CASE(ARMISD::VADDLVpu)
1747 MAKE_CASE(ARMISD::VADDLVAps)
1748 MAKE_CASE(ARMISD::VADDLVApu)
1749 MAKE_CASE(ARMISD::VMLAVs)
1750 MAKE_CASE(ARMISD::VMLAVu)
1751 MAKE_CASE(ARMISD::VMLAVps)
1752 MAKE_CASE(ARMISD::VMLAVpu)
1753 MAKE_CASE(ARMISD::VMLALVs)
1754 MAKE_CASE(ARMISD::VMLALVu)
1755 MAKE_CASE(ARMISD::VMLALVps)
1756 MAKE_CASE(ARMISD::VMLALVpu)
1757 MAKE_CASE(ARMISD::VMLALVAs)
1758 MAKE_CASE(ARMISD::VMLALVAu)
1759 MAKE_CASE(ARMISD::VMLALVAps)
1760 MAKE_CASE(ARMISD::VMLALVApu)
1761 MAKE_CASE(ARMISD::VMINVu)
1762 MAKE_CASE(ARMISD::VMINVs)
1763 MAKE_CASE(ARMISD::VMAXVu)
1764 MAKE_CASE(ARMISD::VMAXVs)
1765 MAKE_CASE(ARMISD::UMAAL)
1766 MAKE_CASE(ARMISD::UMLAL)
1767 MAKE_CASE(ARMISD::SMLAL)
1768 MAKE_CASE(ARMISD::SMLALBB)
1769 MAKE_CASE(ARMISD::SMLALBT)
1770 MAKE_CASE(ARMISD::SMLALTB)
1771 MAKE_CASE(ARMISD::SMLALTT)
1772 MAKE_CASE(ARMISD::SMULWB)
1773 MAKE_CASE(ARMISD::SMULWT)
1774 MAKE_CASE(ARMISD::SMLALD)
1775 MAKE_CASE(ARMISD::SMLALDX)
1776 MAKE_CASE(ARMISD::SMLSLD)
1777 MAKE_CASE(ARMISD::SMLSLDX)
1778 MAKE_CASE(ARMISD::SMMLAR)
1779 MAKE_CASE(ARMISD::SMMLSR)
1780 MAKE_CASE(ARMISD::QADD16b)
1781 MAKE_CASE(ARMISD::QSUB16b)
1782 MAKE_CASE(ARMISD::QADD8b)
1783 MAKE_CASE(ARMISD::QSUB8b)
1784 MAKE_CASE(ARMISD::UQADD16b)
1785 MAKE_CASE(ARMISD::UQSUB16b)
1786 MAKE_CASE(ARMISD::UQADD8b)
1787 MAKE_CASE(ARMISD::UQSUB8b)
1788 MAKE_CASE(ARMISD::BUILD_VECTOR)
1789 MAKE_CASE(ARMISD::BFI)
1790 MAKE_CASE(ARMISD::VORRIMM)
1791 MAKE_CASE(ARMISD::VBICIMM)
1792 MAKE_CASE(ARMISD::VBSP)
1793 MAKE_CASE(ARMISD::MEMCPY)
1794 MAKE_CASE(ARMISD::VLD1DUP)
1795 MAKE_CASE(ARMISD::VLD2DUP)
1796 MAKE_CASE(ARMISD::VLD3DUP)
1797 MAKE_CASE(ARMISD::VLD4DUP)
1798 MAKE_CASE(ARMISD::VLD1_UPD)
1799 MAKE_CASE(ARMISD::VLD2_UPD)
1800 MAKE_CASE(ARMISD::VLD3_UPD)
1801 MAKE_CASE(ARMISD::VLD4_UPD)
1802 MAKE_CASE(ARMISD::VLD1x2_UPD)
1803 MAKE_CASE(ARMISD::VLD1x3_UPD)
1804 MAKE_CASE(ARMISD::VLD1x4_UPD)
1805 MAKE_CASE(ARMISD::VLD2LN_UPD)
1806 MAKE_CASE(ARMISD::VLD3LN_UPD)
1807 MAKE_CASE(ARMISD::VLD4LN_UPD)
1808 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1809 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1810 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1811 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1812 MAKE_CASE(ARMISD::VST1_UPD)
1813 MAKE_CASE(ARMISD::VST2_UPD)
1814 MAKE_CASE(ARMISD::VST3_UPD)
1815 MAKE_CASE(ARMISD::VST4_UPD)
1816 MAKE_CASE(ARMISD::VST1x2_UPD)
1817 MAKE_CASE(ARMISD::VST1x3_UPD)
1818 MAKE_CASE(ARMISD::VST1x4_UPD)
1819 MAKE_CASE(ARMISD::VST2LN_UPD)
1820 MAKE_CASE(ARMISD::VST3LN_UPD)
1821 MAKE_CASE(ARMISD::VST4LN_UPD)
1822 MAKE_CASE(ARMISD::WLS)
1823 MAKE_CASE(ARMISD::WLSSETUP)
1824 MAKE_CASE(ARMISD::LE)
1825 MAKE_CASE(ARMISD::LOOP_DEC)
1826 MAKE_CASE(ARMISD::CSINV)
1827 MAKE_CASE(ARMISD::CSNEG)
1828 MAKE_CASE(ARMISD::CSINC)
1829 MAKE_CASE(ARMISD::MEMCPYLOOP)
1830 MAKE_CASE(ARMISD::MEMSETLOOP)
1831#undef MAKE_CASE
1832 }
1833 return nullptr;
1834}
1835
1836EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1837 EVT VT) const {
1838 if (!VT.isVector())
1839 return getPointerTy(DL);
1840
1841 // MVE has a predicate register.
1842 if ((Subtarget->hasMVEIntegerOps() &&
1843 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8)) ||
1844 (Subtarget->hasMVEFloatOps() && (VT == MVT::v4f32 || VT == MVT::v8f16)))
1845 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1846 return VT.changeVectorElementTypeToInteger();
1847}
1848
1849/// getRegClassFor - Return the register class that should be used for the
1850/// specified value type.
1851const TargetRegisterClass *
1852ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1853 (void)isDivergent;
1854 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1855 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1856 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1857 // MVE Q registers.
1858 if (Subtarget->hasNEON()) {
1859 if (VT == MVT::v4i64)
1860 return &ARM::QQPRRegClass;
1861 if (VT == MVT::v8i64)
1862 return &ARM::QQQQPRRegClass;
1863 }
1864 if (Subtarget->hasMVEIntegerOps()) {
1865 if (VT == MVT::v4i64)
1866 return &ARM::MQQPRRegClass;
1867 if (VT == MVT::v8i64)
1868 return &ARM::MQQQQPRRegClass;
1869 }
1870 return TargetLowering::getRegClassFor(VT);
1871}
1872
1873// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1874// source/dest is aligned and the copy size is large enough. We therefore want
1875// to align such objects passed to memory intrinsics.
1876bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1877 unsigned &PrefAlign) const {
1878 if (!isa<MemIntrinsic>(CI))
1879 return false;
1880 MinSize = 8;
1881 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1882 // cycle faster than 4-byte aligned LDM.
1883 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1884 return true;
1885}
1886
1887// Create a fast isel object.
1888FastISel *
1889ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1890 const TargetLibraryInfo *libInfo) const {
1891 return ARM::createFastISel(funcInfo, libInfo);
1892}
1893
1894Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1895 unsigned NumVals = N->getNumValues();
1896 if (!NumVals)
1897 return Sched::RegPressure;
1898
1899 for (unsigned i = 0; i != NumVals; ++i) {
1900 EVT VT = N->getValueType(i);
1901 if (VT == MVT::Glue || VT == MVT::Other)
1902 continue;
1903 if (VT.isFloatingPoint() || VT.isVector())
1904 return Sched::ILP;
1905 }
1906
1907 if (!N->isMachineOpcode())
1908 return Sched::RegPressure;
1909
1910 // Load are scheduled for latency even if there instruction itinerary
1911 // is not available.
1912 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1913 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1914
1915 if (MCID.getNumDefs() == 0)
1916 return Sched::RegPressure;
1917 if (!Itins->isEmpty() &&
1918 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1919 return Sched::ILP;
1920
1921 return Sched::RegPressure;
1922}
1923
1924//===----------------------------------------------------------------------===//
1925// Lowering Code
1926//===----------------------------------------------------------------------===//
1927
1928static bool isSRL16(const SDValue &Op) {
1929 if (Op.getOpcode() != ISD::SRL)
1930 return false;
1931 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1932 return Const->getZExtValue() == 16;
1933 return false;
1934}
1935
1936static bool isSRA16(const SDValue &Op) {
1937 if (Op.getOpcode() != ISD::SRA)
1938 return false;
1939 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1940 return Const->getZExtValue() == 16;
1941 return false;
1942}
1943
1944static bool isSHL16(const SDValue &Op) {
1945 if (Op.getOpcode() != ISD::SHL)
1946 return false;
1947 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1948 return Const->getZExtValue() == 16;
1949 return false;
1950}
1951
1952// Check for a signed 16-bit value. We special case SRA because it makes it
1953// more simple when also looking for SRAs that aren't sign extending a
1954// smaller value. Without the check, we'd need to take extra care with
1955// checking order for some operations.
1956static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1957 if (isSRA16(Op))
1958 return isSHL16(Op.getOperand(0));
1959 return DAG.ComputeNumSignBits(Op) == 17;
1960}
1961
1962/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1963static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1964 switch (CC) {
1965 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1965)
;
1966 case ISD::SETNE: return ARMCC::NE;
1967 case ISD::SETEQ: return ARMCC::EQ;
1968 case ISD::SETGT: return ARMCC::GT;
1969 case ISD::SETGE: return ARMCC::GE;
1970 case ISD::SETLT: return ARMCC::LT;
1971 case ISD::SETLE: return ARMCC::LE;
1972 case ISD::SETUGT: return ARMCC::HI;
1973 case ISD::SETUGE: return ARMCC::HS;
1974 case ISD::SETULT: return ARMCC::LO;
1975 case ISD::SETULE: return ARMCC::LS;
1976 }
1977}
1978
1979/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1980static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1981 ARMCC::CondCodes &CondCode2) {
1982 CondCode2 = ARMCC::AL;
1983 switch (CC) {
1984 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1984)
;
1985 case ISD::SETEQ:
1986 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1987 case ISD::SETGT:
1988 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1989 case ISD::SETGE:
1990 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1991 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1992 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1993 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1994 case ISD::SETO: CondCode = ARMCC::VC; break;
1995 case ISD::SETUO: CondCode = ARMCC::VS; break;
1996 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1997 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1998 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1999 case ISD::SETLT:
2000 case ISD::SETULT: CondCode = ARMCC::LT; break;
2001 case ISD::SETLE:
2002 case ISD::SETULE: CondCode = ARMCC::LE; break;
2003 case ISD::SETNE:
2004 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2005 }
2006}
2007
2008//===----------------------------------------------------------------------===//
2009// Calling Convention Implementation
2010//===----------------------------------------------------------------------===//
2011
2012/// getEffectiveCallingConv - Get the effective calling convention, taking into
2013/// account presence of floating point hardware and calling convention
2014/// limitations, such as support for variadic functions.
2015CallingConv::ID
2016ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2017 bool isVarArg) const {
2018 switch (CC) {
2019 default:
2020 report_fatal_error("Unsupported calling convention");
2021 case CallingConv::ARM_AAPCS:
2022 case CallingConv::ARM_APCS:
2023 case CallingConv::GHC:
2024 case CallingConv::CFGuard_Check:
2025 return CC;
2026 case CallingConv::PreserveMost:
2027 return CallingConv::PreserveMost;
2028 case CallingConv::ARM_AAPCS_VFP:
2029 case CallingConv::Swift:
2030 case CallingConv::SwiftTail:
2031 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2032 case CallingConv::C:
2033 case CallingConv::Tail:
2034 if (!Subtarget->isAAPCS_ABI())
2035 return CallingConv::ARM_APCS;
2036 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2037 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2038 !isVarArg)
2039 return CallingConv::ARM_AAPCS_VFP;
2040 else
2041 return CallingConv::ARM_AAPCS;
2042 case CallingConv::Fast:
2043 case CallingConv::CXX_FAST_TLS:
2044 if (!Subtarget->isAAPCS_ABI()) {
2045 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2046 return CallingConv::Fast;
2047 return CallingConv::ARM_APCS;
2048 } else if (Subtarget->hasVFP2Base() &&
2049 !Subtarget->isThumb1Only() && !isVarArg)
2050 return CallingConv::ARM_AAPCS_VFP;
2051 else
2052 return CallingConv::ARM_AAPCS;
2053 }
2054}
2055
2056CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2057 bool isVarArg) const {
2058 return CCAssignFnForNode(CC, false, isVarArg);
2059}
2060
2061CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2062 bool isVarArg) const {
2063 return CCAssignFnForNode(CC, true, isVarArg);
2064}
2065
2066/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2067/// CallingConvention.
2068CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2069 bool Return,
2070 bool isVarArg) const {
2071 switch (getEffectiveCallingConv(CC, isVarArg)) {
2072 default:
2073 report_fatal_error("Unsupported calling convention");
2074 case CallingConv::ARM_APCS:
2075 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2076 case CallingConv::ARM_AAPCS:
2077 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2078 case CallingConv::ARM_AAPCS_VFP:
2079 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2080 case CallingConv::Fast:
2081 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2082 case CallingConv::GHC:
2083 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2084 case CallingConv::PreserveMost:
2085 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2086 case CallingConv::CFGuard_Check:
2087 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2088 }
2089}
2090
2091SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2092 MVT LocVT, MVT ValVT, SDValue Val) const {
2093 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2094 Val);
2095 if (Subtarget->hasFullFP16()) {
2096 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2097 } else {
2098 Val = DAG.getNode(ISD::TRUNCATE, dl,
2099 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2100 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2101 }
2102 return Val;
2103}
2104
2105SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2106 MVT LocVT, MVT ValVT,
2107 SDValue Val) const {
2108 if (Subtarget->hasFullFP16()) {
2109 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2110 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2111 } else {
2112 Val = DAG.getNode(ISD::BITCAST, dl,
2113 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2114 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2115 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2116 }
2117 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2118}
2119
2120/// LowerCallResult - Lower the result values of a call into the
2121/// appropriate copies out of appropriate physical registers.
2122SDValue ARMTargetLowering::LowerCallResult(
2123 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2124 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2125 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2126 SDValue ThisVal) const {
2127 // Assign locations to each value returned by this call.
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2130 *DAG.getContext());
2131 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2132
2133 // Copy all of the result registers out of their specified physreg.
2134 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2135 CCValAssign VA = RVLocs[i];
2136
2137 // Pass 'this' value directly from the argument to return value, to avoid
2138 // reg unit interference
2139 if (i == 0 && isThisReturn) {
2140 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2141, __extension__ __PRETTY_FUNCTION__))
2141 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2141, __extension__ __PRETTY_FUNCTION__))
;
2142 InVals.push_back(ThisVal);
2143 continue;
2144 }
2145
2146 SDValue Val;
2147 if (VA.needsCustom() &&
2148 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2149 // Handle f64 or half of a v2f64.
2150 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2151 InFlag);
2152 Chain = Lo.getValue(1);
2153 InFlag = Lo.getValue(2);
2154 VA = RVLocs[++i]; // skip ahead to next loc
2155 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2156 InFlag);
2157 Chain = Hi.getValue(1);
2158 InFlag = Hi.getValue(2);
2159 if (!Subtarget->isLittle())
2160 std::swap (Lo, Hi);
2161 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2162
2163 if (VA.getLocVT() == MVT::v2f64) {
2164 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2165 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2166 DAG.getConstant(0, dl, MVT::i32));
2167
2168 VA = RVLocs[++i]; // skip ahead to next loc
2169 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2170 Chain = Lo.getValue(1);
2171 InFlag = Lo.getValue(2);
2172 VA = RVLocs[++i]; // skip ahead to next loc
2173 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2174 Chain = Hi.getValue(1);
2175 InFlag = Hi.getValue(2);
2176 if (!Subtarget->isLittle())
2177 std::swap (Lo, Hi);
2178 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2179 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2180 DAG.getConstant(1, dl, MVT::i32));
2181 }
2182 } else {
2183 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2184 InFlag);
2185 Chain = Val.getValue(1);
2186 InFlag = Val.getValue(2);
2187 }
2188
2189 switch (VA.getLocInfo()) {
2190 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2190)
;
2191 case CCValAssign::Full: break;
2192 case CCValAssign::BCvt:
2193 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2194 break;
2195 }
2196
2197 // f16 arguments have their size extended to 4 bytes and passed as if they
2198 // had been copied to the LSBs of a 32-bit register.
2199 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2200 if (VA.needsCustom() &&
2201 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2202 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2203
2204 InVals.push_back(Val);
2205 }
2206
2207 return Chain;
2208}
2209
2210std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2211 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2212 bool IsTailCall, int SPDiff) const {
2213 SDValue DstAddr;
2214 MachinePointerInfo DstInfo;
2215 int32_t Offset = VA.getLocMemOffset();
2216 MachineFunction &MF = DAG.getMachineFunction();
2217
2218 if (IsTailCall) {
2219 Offset += SPDiff;
2220 auto PtrVT = getPointerTy(DAG.getDataLayout());
2221 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2222 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2223 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2224 DstInfo =
2225 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2226 } else {
2227 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2228 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2229 StackPtr, PtrOff);
2230 DstInfo =
2231 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2232 }
2233
2234 return std::make_pair(DstAddr, DstInfo);
2235}
2236
2237void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2238 SDValue Chain, SDValue &Arg,
2239 RegsToPassVector &RegsToPass,
2240 CCValAssign &VA, CCValAssign &NextVA,
2241 SDValue &StackPtr,
2242 SmallVectorImpl<SDValue> &MemOpChains,
2243 bool IsTailCall,
2244 int SPDiff) const {
2245 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2246 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2247 unsigned id = Subtarget->isLittle() ? 0 : 1;
2248 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2249
2250 if (NextVA.isRegLoc())
2251 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2252 else {
2253 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2253, __extension__ __PRETTY_FUNCTION__))
;
2254 if (!StackPtr.getNode())
2255 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2256 getPointerTy(DAG.getDataLayout()));
2257
2258 SDValue DstAddr;
2259 MachinePointerInfo DstInfo;
2260 std::tie(DstAddr, DstInfo) =
2261 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2262 MemOpChains.push_back(
2263 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2264 }
2265}
2266
2267static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2268 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2269 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2270}
2271
2272/// LowerCall - Lowering a call into a callseq_start <-
2273/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2274/// nodes.
2275SDValue
2276ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2277 SmallVectorImpl<SDValue> &InVals) const {
2278 SelectionDAG &DAG = CLI.DAG;
2279 SDLoc &dl = CLI.DL;
2280 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2281 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2282 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2283 SDValue Chain = CLI.Chain;
2284 SDValue Callee = CLI.Callee;
2285 bool &isTailCall = CLI.IsTailCall;
2286 CallingConv::ID CallConv = CLI.CallConv;
2287 bool doesNotRet = CLI.DoesNotReturn;
2288 bool isVarArg = CLI.IsVarArg;
2289
2290 MachineFunction &MF = DAG.getMachineFunction();
2291 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2292 MachineFunction::CallSiteInfo CSInfo;
2293 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2294 bool isThisReturn = false;
2295 bool isCmseNSCall = false;
2296 bool isSibCall = false;
2297 bool PreferIndirect = false;
2298
2299 // Determine whether this is a non-secure function call.
2300 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
2
Assuming field 'CB' is null
3
Taking false branch
2301 isCmseNSCall = true;
2302
2303 // Disable tail calls if they're not supported.
2304 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
2305 isTailCall = false;
2306
2307 // For both the non-secure calls and the returns from a CMSE entry function,
2308 // the function needs to do some extra work afte r the call, or before the
2309 // return, respectively, thus it cannot end with atail call
2310 if (isCmseNSCall
4.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
5
Assuming the condition is false
6
Taking false branch
2311 isTailCall = false;
2312
2313 if (isa<GlobalAddressSDNode>(Callee)) {
7
Assuming 'Callee' is not a 'GlobalAddressSDNode'
8
Taking false branch
2314 // If we're optimizing for minimum size and the function is called three or
2315 // more times in this block, we can improve codesize by calling indirectly
2316 // as BLXr has a 16-bit encoding.
2317 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2318 if (CLI.CB) {
2319 auto *BB = CLI.CB->getParent();
2320 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2321 count_if(GV->users(), [&BB](const User *U) {
2322 return isa<Instruction>(U) &&
2323 cast<Instruction>(U)->getParent() == BB;
2324 }) > 2;
2325 }
2326 }
2327 if (isTailCall) {
9
Assuming 'isTailCall' is false
2328 // Check if it's really possible to do a tail call.
2329 isTailCall = IsEligibleForTailCallOptimization(
2330 Callee, CallConv, isVarArg, isStructRet,
2331 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2332 PreferIndirect);
2333
2334 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2335 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2336 isSibCall = true;
2337
2338 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2339 // detected sibcalls.
2340 if (isTailCall)
2341 ++NumTailCalls;
2342 }
2343
2344 if (!isTailCall
9.1
'isTailCall' is false
&& CLI.CB
9.2
Field 'CB' is null
&& CLI.CB->isMustTailCall())
2345 report_fatal_error("failed to perform tail call elimination on a call "
2346 "site marked musttail");
2347 // Analyze operands of the call, assigning locations to each operand.
2348 SmallVector<CCValAssign, 16> ArgLocs;
2349 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2350 *DAG.getContext());
2351 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2352
2353 // Get a count of how many bytes are to be pushed on the stack.
2354 unsigned NumBytes = CCInfo.getNextStackOffset();
2355
2356 // SPDiff is the byte offset of the call's argument area from the callee's.
2357 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2358 // by this amount for a tail call. In a sibling call it must be 0 because the
2359 // caller will deallocate the entire stack and the callee still expects its
2360 // arguments to begin at SP+0. Completely unused for non-tail calls.
2361 int SPDiff = 0;
2362
2363 if (isTailCall && !isSibCall) {
10
Assuming 'isTailCall' is false
2364 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2365 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2366
2367 // Since callee will pop argument stack as a tail call, we must keep the
2368 // popped size 16-byte aligned.
2369 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2370 NumBytes = alignTo(NumBytes, StackAlign);
2371
2372 // SPDiff will be negative if this tail call requires more space than we
2373 // would automatically have in our incoming argument space. Positive if we
2374 // can actually shrink the stack.
2375 SPDiff = NumReusableBytes - NumBytes;
2376
2377 // If this call requires more stack than we have available from
2378 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2379 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2380 AFI->setArgRegsSaveSize(-SPDiff);
2381 }
2382
2383 if (isSibCall
10.1
'isSibCall' is false
) {
11
Taking false branch
2384 // For sibling tail calls, memory operands are available in our caller's stack.
2385 NumBytes = 0;
2386 } else {
2387 // Adjust the stack pointer for the new arguments...
2388 // These operations are automatically eliminated by the prolog/epilog pass
2389 Chain = DAG.getCALLSEQ_START(Chain, isTailCall
11.1
'isTailCall' is false
? 0 : NumBytes, 0, dl);
12
'?' condition is false
2390 }
2391
2392 SDValue StackPtr =
2393 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2394
2395 RegsToPassVector RegsToPass;
2396 SmallVector<SDValue, 8> MemOpChains;
2397
2398 // During a tail call, stores to the argument area must happen after all of
2399 // the function's incoming arguments have been loaded because they may alias.
2400 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2401 // there's no point in doing so repeatedly so this tracks whether that's
2402 // happened yet.
2403 bool AfterFormalArgLoads = false;
2404
2405 // Walk the register/memloc assignments, inserting copies/loads. In the case
2406 // of tail call optimization, arguments are handled later.
2407 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
14
Loop condition is false. Execution continues on line 2561
2408 i != e;
13
Assuming 'i' is equal to 'e'
2409 ++i, ++realArgIdx) {
2410 CCValAssign &VA = ArgLocs[i];
2411 SDValue Arg = OutVals[realArgIdx];
2412 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2413 bool isByVal = Flags.isByVal();
2414
2415 // Promote the value if needed.
2416 switch (VA.getLocInfo()) {
2417 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2417)
;
2418 case CCValAssign::Full: break;
2419 case CCValAssign::SExt:
2420 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2421 break;
2422 case CCValAssign::ZExt:
2423 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2424 break;
2425 case CCValAssign::AExt:
2426 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2427 break;
2428 case CCValAssign::BCvt:
2429 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2430 break;
2431 }
2432
2433 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2434 Chain = DAG.getStackArgumentTokenFactor(Chain);
2435 AfterFormalArgLoads = true;
2436 }
2437
2438 // f16 arguments have their size extended to 4 bytes and passed as if they
2439 // had been copied to the LSBs of a 32-bit register.
2440 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2441 if (VA.needsCustom() &&
2442 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2443 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2444 } else {
2445 // f16 arguments could have been extended prior to argument lowering.
2446 // Mask them arguments if this is a CMSE nonsecure call.
2447 auto ArgVT = Outs[realArgIdx].ArgVT;
2448 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2449 auto LocBits = VA.getLocVT().getSizeInBits();
2450 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2451 SDValue Mask =
2452 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2453 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2454 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2455 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2456 }
2457 }
2458
2459 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2460 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2461 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2462 DAG.getConstant(0, dl, MVT::i32));
2463 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2464 DAG.getConstant(1, dl, MVT::i32));
2465
2466 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2467 StackPtr, MemOpChains, isTailCall, SPDiff);
2468
2469 VA = ArgLocs[++i]; // skip ahead to next loc
2470 if (VA.isRegLoc()) {
2471 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2472 StackPtr, MemOpChains, isTailCall, SPDiff);
2473 } else {
2474 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2474, __extension__ __PRETTY_FUNCTION__))
;
2475 SDValue DstAddr;
2476 MachinePointerInfo DstInfo;
2477 std::tie(DstAddr, DstInfo) =
2478 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2479 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2480 }
2481 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2482 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2483 StackPtr, MemOpChains, isTailCall, SPDiff);
2484 } else if (VA.isRegLoc()) {
2485 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2486 Outs[0].VT == MVT::i32) {
2487 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2488, __extension__ __PRETTY_FUNCTION__))
2488 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2488, __extension__ __PRETTY_FUNCTION__))
;
2489 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2490, __extension__ __PRETTY_FUNCTION__))
2490 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2490, __extension__ __PRETTY_FUNCTION__))
;
2491 isThisReturn = true;
2492 }
2493 const TargetOptions &Options = DAG.getTarget().Options;
2494 if (Options.EmitCallSiteInfo)
2495 CSInfo.emplace_back(VA.getLocReg(), i);
2496 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2497 } else if (isByVal) {
2498 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2498, __extension__ __PRETTY_FUNCTION__))
;
2499 unsigned offset = 0;
2500
2501 // True if this byval aggregate will be split between registers
2502 // and memory.
2503 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2504 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2505
2506 if (CurByValIdx < ByValArgsCount) {
2507
2508 unsigned RegBegin, RegEnd;
2509 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2510
2511 EVT PtrVT =
2512 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2513 unsigned int i, j;
2514 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2515 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2516 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2517 SDValue Load =
2518 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2519 DAG.InferPtrAlign(AddArg));
2520 MemOpChains.push_back(Load.getValue(1));
2521 RegsToPass.push_back(std::make_pair(j, Load));
2522 }
2523
2524 // If parameter size outsides register area, "offset" value
2525 // helps us to calculate stack slot for remained part properly.
2526 offset = RegEnd - RegBegin;
2527
2528 CCInfo.nextInRegsParam();
2529 }
2530
2531 if (Flags.getByValSize() > 4*offset) {
2532 auto PtrVT = getPointerTy(DAG.getDataLayout());
2533 SDValue Dst;
2534 MachinePointerInfo DstInfo;
2535 std::tie(Dst, DstInfo) =
2536 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2537 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2538 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2539 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2540 MVT::i32);
2541 SDValue AlignNode =
2542 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2543
2544 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2545 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2546 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2547 Ops));
2548 }
2549 } else {
2550 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2550, __extension__ __PRETTY_FUNCTION__))
;
2551 SDValue DstAddr;
2552 MachinePointerInfo DstInfo;
2553 std::tie(DstAddr, DstInfo) =
2554 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2555
2556 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2557 MemOpChains.push_back(Store);
2558 }
2559 }
2560
2561 if (!MemOpChains.empty())
15
Taking false branch
2562 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2563
2564 // Build a sequence of copy-to-reg nodes chained together with token chain
2565 // and flag operands which copy the outgoing args into the appropriate regs.
2566 SDValue InFlag;
2567 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
16
Assuming 'i' is equal to 'e'
17
Loop condition is false. Execution continues on line 2576
2568 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2569 RegsToPass[i].second, InFlag);
2570 InFlag = Chain.getValue(1);
2571 }
2572
2573 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2574 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2575 // node so that legalize doesn't hack it.
2576 bool isDirect = false;
2577
2578 const TargetMachine &TM = getTargetMachine();
2579 const Module *Mod = MF.getFunction().getParent();
2580 const GlobalValue *GV = nullptr;
18
'GV' initialized to a null pointer value
2581 if (GlobalAddressSDNode *G
18.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
2582 GV = G->getGlobal();
2583 bool isStub =
2584 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
19
Assuming the condition is false
2585
2586 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
20
Assuming the condition is true
2587 bool isLocalARMFunc = false;
2588 auto PtrVt = getPointerTy(DAG.getDataLayout());
2589
2590 if (Subtarget->genLongCalls()) {
21
Assuming the condition is false
22
Taking false branch
2591 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2592, __extension__ __PRETTY_FUNCTION__))
2592 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2592, __extension__ __PRETTY_FUNCTION__))
;
2593 // Handle a global address or an external symbol. If it's not one of
2594 // those, the target's already in a register, so we don't need to do
2595 // anything extra.
2596 if (isa<GlobalAddressSDNode>(Callee)) {
2597 // Create a constant pool entry for the callee address
2598 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2599 ARMConstantPoolValue *CPV =
2600 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2601
2602 // Get the address of the callee into a register
2603 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2604 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2605 Callee = DAG.getLoad(
2606 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2607 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2608 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2609 const char *Sym = S->getSymbol();
2610
2611 // Create a constant pool entry for the callee address
2612 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2613 ARMConstantPoolValue *CPV =
2614 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2615 ARMPCLabelIndex, 0);
2616 // Get the address of the callee into a register
2617 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2618 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2619 Callee = DAG.getLoad(
2620 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2621 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2622 }
2623 } else if (isa<GlobalAddressSDNode>(Callee)) {
23
Assuming 'Callee' is a 'GlobalAddressSDNode'
24
Taking true branch
2624 if (!PreferIndirect
24.1
'PreferIndirect' is false
) {
25
Taking true branch
2625 isDirect = true;
2626 bool isDef = GV->isStrongDefinitionForLinker();
26
Called C++ object pointer is null
2627
2628 // ARM call to a local ARM function is predicable.
2629 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2630 // tBX takes a register source operand.
2631 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2632 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2632, __extension__ __PRETTY_FUNCTION__))
;
2633 Callee = DAG.getNode(
2634 ARMISD::WrapperPIC, dl, PtrVt,
2635 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2636 Callee = DAG.getLoad(
2637 PtrVt, dl, DAG.getEntryNode(), Callee,
2638 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2639 MachineMemOperand::MODereferenceable |
2640 MachineMemOperand::MOInvariant);
2641 } else if (Subtarget->isTargetCOFF()) {
2642 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2643, __extension__ __PRETTY_FUNCTION__))
2643 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2643, __extension__ __PRETTY_FUNCTION__))
;
2644 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2645 if (GV->hasDLLImportStorageClass())
2646 TargetFlags = ARMII::MO_DLLIMPORT;
2647 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2648 TargetFlags = ARMII::MO_COFFSTUB;
2649 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2650 TargetFlags);
2651 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2652 Callee =
2653 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2654 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2655 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2656 } else {
2657 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2658 }
2659 }
2660 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2661 isDirect = true;
2662 // tBX takes a register source operand.
2663 const char *Sym = S->getSymbol();
2664 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2665 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2666 ARMConstantPoolValue *CPV =
2667 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2668 ARMPCLabelIndex, 4);
2669 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2670 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2671 Callee = DAG.getLoad(
2672 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2673 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2674 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2675 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2676 } else {
2677 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2678 }
2679 }
2680
2681 if (isCmseNSCall) {
2682 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2683, __extension__ __PRETTY_FUNCTION__))
2683 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2683, __extension__ __PRETTY_FUNCTION__))
;
2684 if (NumBytes > 0) {
2685 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2686 "call to non-secure function would "
2687 "require passing arguments on stack",
2688 dl.getDebugLoc());
2689 DAG.getContext()->diagnose(Diag);
2690 }
2691 if (isStructRet) {
2692 DiagnosticInfoUnsupported Diag(
2693 DAG.getMachineFunction().getFunction(),
2694 "call to non-secure function would return value through pointer",
2695 dl.getDebugLoc());
2696 DAG.getContext()->diagnose(Diag);
2697 }
2698 }
2699
2700 // FIXME: handle tail calls differently.
2701 unsigned CallOpc;
2702 if (Subtarget->isThumb()) {
2703 if (isCmseNSCall)
2704 CallOpc = ARMISD::tSECALL;
2705 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2706 CallOpc = ARMISD::CALL_NOLINK;
2707 else
2708 CallOpc = ARMISD::CALL;
2709 } else {
2710 if (!isDirect && !Subtarget->hasV5TOps())
2711 CallOpc = ARMISD::CALL_NOLINK;
2712 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2713 // Emit regular call when code size is the priority
2714 !Subtarget->hasMinSize())
2715 // "mov lr, pc; b _foo" to avoid confusing the RSP
2716 CallOpc = ARMISD::CALL_NOLINK;
2717 else
2718 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2719 }
2720
2721 // We don't usually want to end the call-sequence here because we would tidy
2722 // the frame up *after* the call, however in the ABI-changing tail-call case
2723 // we've carefully laid out the parameters so that when sp is reset they'll be
2724 // in the correct location.
2725 if (isTailCall && !isSibCall) {
2726 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
2727 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2728 InFlag = Chain.getValue(1);
2729 }
2730
2731 std::vector<SDValue> Ops;
2732 Ops.push_back(Chain);
2733 Ops.push_back(Callee);
2734
2735 if (isTailCall) {
2736 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2737 }
2738
2739 // Add argument registers to the end of the list so that they are known live
2740 // into the call.
2741 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2742 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2743 RegsToPass[i].second.getValueType()));
2744
2745 // Add a register mask operand representing the call-preserved registers.
2746 if (!isTailCall) {
2747 const uint32_t *Mask;
2748 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2749 if (isThisReturn) {
2750 // For 'this' returns, use the R0-preserving mask if applicable
2751 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2752 if (!Mask) {
2753 // Set isThisReturn to false if the calling convention is not one that
2754 // allows 'returned' to be modeled in this way, so LowerCallResult does
2755 // not try to pass 'this' straight through
2756 isThisReturn = false;
2757 Mask = ARI->getCallPreservedMask(MF, CallConv);
2758 }
2759 } else
2760 Mask = ARI->getCallPreservedMask(MF, CallConv);
2761
2762 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2762, __extension__ __PRETTY_FUNCTION__))
;
2763 Ops.push_back(DAG.getRegisterMask(Mask));
2764 }
2765
2766 if (InFlag.getNode())
2767 Ops.push_back(InFlag);
2768
2769 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2770 if (isTailCall) {
2771 MF.getFrameInfo().setHasTailCall();
2772 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2773 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2774 return Ret;
2775 }
2776
2777 // Returns a chain and a flag for retval copy to use.
2778 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2779 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2780 InFlag = Chain.getValue(1);
2781 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2782
2783 // If we're guaranteeing tail-calls will be honoured, the callee must
2784 // pop its own argument stack on return. But this call is *not* a tail call so
2785 // we need to undo that after it returns to restore the status-quo.
2786 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2787 uint64_t CalleePopBytes =
2788 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2789
2790 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2791 DAG.getIntPtrConstant(CalleePopBytes, dl, true),
2792 InFlag, dl);
2793 if (!Ins.empty())
2794 InFlag = Chain.getValue(1);
2795
2796 // Handle result values, copying them out of physregs into vregs that we
2797 // return.
2798 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2799 InVals, isThisReturn,
2800 isThisReturn ? OutVals[0] : SDValue());
2801}
2802
2803/// HandleByVal - Every parameter *after* a byval parameter is passed
2804/// on the stack. Remember the next parameter register to allocate,
2805/// and then confiscate the rest of the parameter registers to insure
2806/// this.
2807void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2808 Align Alignment) const {
2809 // Byval (as with any stack) slots are always at least 4 byte aligned.
2810 Alignment = std::max(Alignment, Align(4));
2811
2812 unsigned Reg = State->AllocateReg(GPRArgRegs);
2813 if (!Reg)
2814 return;
2815
2816 unsigned AlignInRegs = Alignment.value() / 4;
2817 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2818 for (unsigned i = 0; i < Waste; ++i)
2819 Reg = State->AllocateReg(GPRArgRegs);
2820
2821 if (!Reg)
2822 return;
2823
2824 unsigned Excess = 4 * (ARM::R4 - Reg);
2825
2826 // Special case when NSAA != SP and parameter size greater than size of
2827 // all remained GPR regs. In that case we can't split parameter, we must
2828 // send it to stack. We also must set NCRN to R4, so waste all
2829 // remained registers.
2830 const unsigned NSAAOffset = State->getNextStackOffset();
2831 if (NSAAOffset != 0 && Size > Excess) {
2832 while (State->AllocateReg(GPRArgRegs))
2833 ;
2834 return;
2835 }
2836
2837 // First register for byval parameter is the first register that wasn't
2838 // allocated before this method call, so it would be "reg".
2839 // If parameter is small enough to be saved in range [reg, r4), then
2840 // the end (first after last) register would be reg + param-size-in-regs,
2841 // else parameter would be splitted between registers and stack,
2842 // end register would be r4 in this case.
2843 unsigned ByValRegBegin = Reg;
2844 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2845 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2846 // Note, first register is allocated in the beginning of function already,
2847 // allocate remained amount of registers we need.
2848 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2849 State->AllocateReg(GPRArgRegs);
2850 // A byval parameter that is split between registers and memory needs its
2851 // size truncated here.
2852 // In the case where the entire structure fits in registers, we set the
2853 // size in memory to zero.
2854 Size = std::max<int>(Size - Excess, 0);
2855}
2856
2857/// MatchingStackOffset - Return true if the given stack call argument is
2858/// already available in the same position (relatively) of the caller's
2859/// incoming argument stack.
2860static
2861bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2862 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2863 const TargetInstrInfo *TII) {
2864 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2865 int FI = std::numeric_limits<int>::max();
2866 if (Arg.getOpcode() == ISD::CopyFromReg) {
2867 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2868 if (!Register::isVirtualRegister(VR))
2869 return false;
2870 MachineInstr *Def = MRI->getVRegDef(VR);
2871 if (!Def)
2872 return false;
2873 if (!Flags.isByVal()) {
2874 if (!TII->isLoadFromStackSlot(*Def, FI))
2875 return false;
2876 } else {
2877 return false;
2878 }
2879 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2880 if (Flags.isByVal())
2881 // ByVal argument is passed in as a pointer but it's now being
2882 // dereferenced. e.g.
2883 // define @foo(%struct.X* %A) {
2884 // tail call @bar(%struct.X* byval %A)
2885 // }
2886 return false;
2887 SDValue Ptr = Ld->getBasePtr();
2888 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2889 if (!FINode)
2890 return false;
2891 FI = FINode->getIndex();
2892 } else
2893 return false;
2894
2895 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2895, __extension__ __PRETTY_FUNCTION__))
;
2896 if (!MFI.isFixedObjectIndex(FI))
2897 return false;
2898 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2899}
2900
2901/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2902/// for tail call optimization. Targets which want to do tail call
2903/// optimization should implement this function.
2904bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2905 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2906 bool isCalleeStructRet, bool isCallerStructRet,
2907 const SmallVectorImpl<ISD::OutputArg> &Outs,
2908 const SmallVectorImpl<SDValue> &OutVals,
2909 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2910 const bool isIndirect) const {
2911 MachineFunction &MF = DAG.getMachineFunction();
2912 const Function &CallerF = MF.getFunction();
2913 CallingConv::ID CallerCC = CallerF.getCallingConv();
2914
2915 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2915, __extension__ __PRETTY_FUNCTION__))
;
2916
2917 // Indirect tail calls cannot be optimized for Thumb1 if the args
2918 // to the call take up r0-r3. The reason is that there are no legal registers
2919 // left to hold the pointer to the function to be called.
2920 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2921 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2922 return false;
2923
2924 // Look for obvious safe cases to perform tail call optimization that do not
2925 // require ABI changes. This is what gcc calls sibcall.
2926
2927 // Exception-handling functions need a special set of instructions to indicate
2928 // a return to the hardware. Tail-calling another function would probably
2929 // break this.
2930 if (CallerF.hasFnAttribute("interrupt"))
2931 return false;
2932
2933 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2934 return CalleeCC == CallerCC;
2935
2936 // Also avoid sibcall optimization if either caller or callee uses struct
2937 // return semantics.
2938 if (isCalleeStructRet || isCallerStructRet)
2939 return false;
2940
2941 // Externally-defined functions with weak linkage should not be
2942 // tail-called on ARM when the OS does not support dynamic
2943 // pre-emption of symbols, as the AAELF spec requires normal calls
2944 // to undefined weak functions to be replaced with a NOP or jump to the
2945 // next instruction. The behaviour of branch instructions in this
2946 // situation (as used for tail calls) is implementation-defined, so we
2947 // cannot rely on the linker replacing the tail call with a return.
2948 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2949 const GlobalValue *GV = G->getGlobal();
2950 const Triple &TT = getTargetMachine().getTargetTriple();
2951 if (GV->hasExternalWeakLinkage() &&
2952 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2953 return false;
2954 }
2955
2956 // Check that the call results are passed in the same way.
2957 LLVMContext &C = *DAG.getContext();
2958 if (!CCState::resultsCompatible(
2959 getEffectiveCallingConv(CalleeCC, isVarArg),
2960 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2961 CCAssignFnForReturn(CalleeCC, isVarArg),
2962 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2963 return false;
2964 // The callee has to preserve all registers the caller needs to preserve.
2965 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2966 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2967 if (CalleeCC != CallerCC) {
2968 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2969 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2970 return false;
2971 }
2972
2973 // If Caller's vararg or byval argument has been split between registers and
2974 // stack, do not perform tail call, since part of the argument is in caller's
2975 // local frame.
2976 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2977 if (AFI_Caller->getArgRegsSaveSize())
2978 return false;
2979
2980 // If the callee takes no arguments then go on to check the results of the
2981 // call.
2982 if (!Outs.empty()) {
2983 // Check if stack adjustment is needed. For now, do not do this if any
2984 // argument is passed on the stack.
2985 SmallVector<CCValAssign, 16> ArgLocs;
2986 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2987 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2988 if (CCInfo.getNextStackOffset()) {
2989 // Check if the arguments are already laid out in the right way as
2990 // the caller's fixed stack objects.
2991 MachineFrameInfo &MFI = MF.getFrameInfo();
2992 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2993 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2994 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2995 i != e;
2996 ++i, ++realArgIdx) {
2997 CCValAssign &VA = ArgLocs[i];
2998 EVT RegVT = VA.getLocVT();
2999 SDValue Arg = OutVals[realArgIdx];
3000 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3001 if (VA.getLocInfo() == CCValAssign::Indirect)
3002 return false;
3003 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3004 // f64 and vector types are split into multiple registers or
3005 // register/stack-slot combinations. The types will not match
3006 // the registers; give up on memory f64 refs until we figure
3007 // out what to do about this.
3008 if (!VA.isRegLoc())
3009 return false;
3010 if (!ArgLocs[++i].isRegLoc())
3011 return false;
3012 if (RegVT == MVT::v2f64) {
3013 if (!ArgLocs[++i].isRegLoc())
3014 return false;
3015 if (!ArgLocs[++i].isRegLoc())
3016 return false;
3017 }
3018 } else if (!VA.isRegLoc()) {
3019 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3020 MFI, MRI, TII))
3021 return false;
3022 }
3023 }
3024 }
3025
3026 const MachineRegisterInfo &MRI = MF.getRegInfo();
3027 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3028 return false;
3029 }
3030
3031 return true;
3032}
3033
3034bool
3035ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3036 MachineFunction &MF, bool isVarArg,
3037 const SmallVectorImpl<ISD::OutputArg> &Outs,
3038 LLVMContext &Context) const {
3039 SmallVector<CCValAssign, 16> RVLocs;
3040 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3041 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3042}
3043
3044static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3045 const SDLoc &DL, SelectionDAG &DAG) {
3046 const MachineFunction &MF = DAG.getMachineFunction();
3047 const Function &F = MF.getFunction();
3048
3049 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3050
3051 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3052 // version of the "preferred return address". These offsets affect the return
3053 // instruction if this is a return from PL1 without hypervisor extensions.
3054 // IRQ/FIQ: +4 "subs pc, lr, #4"
3055 // SWI: 0 "subs pc, lr, #0"
3056 // ABORT: +4 "subs pc, lr, #4"
3057 // UNDEF: +4/+2 "subs pc, lr, #0"
3058 // UNDEF varies depending on where the exception came from ARM or Thumb
3059 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3060
3061 int64_t LROffset;
3062 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3063 IntKind == "ABORT")
3064 LROffset = 4;
3065 else if (IntKind == "SWI" || IntKind == "UNDEF")
3066 LROffset = 0;
3067 else
3068 report_fatal_error("Unsupported interrupt attribute. If present, value "
3069 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3070
3071 RetOps.insert(RetOps.begin() + 1,
3072 DAG.getConstant(LROffset, DL, MVT::i32, false));
3073
3074 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3075}
3076
3077SDValue
3078ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3079 bool isVarArg,
3080 const SmallVectorImpl<ISD::OutputArg> &Outs,
3081 const SmallVectorImpl<SDValue> &OutVals,
3082 const SDLoc &dl, SelectionDAG &DAG) const {
3083 // CCValAssign - represent the assignment of the return value to a location.
3084 SmallVector<CCValAssign, 16> RVLocs;
3085
3086 // CCState - Info about the registers and stack slots.
3087 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3088 *DAG.getContext());
3089
3090 // Analyze outgoing return values.
3091 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3092
3093 SDValue Flag;
3094 SmallVector<SDValue, 4> RetOps;
3095 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3096 bool isLittleEndian = Subtarget->isLittle();
3097
3098 MachineFunction &MF = DAG.getMachineFunction();
3099 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3100 AFI->setReturnRegsCount(RVLocs.size());
3101
3102 // Report error if cmse entry function returns structure through first ptr arg.
3103 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3104 // Note: using an empty SDLoc(), as the first line of the function is a
3105 // better place to report than the last line.
3106 DiagnosticInfoUnsupported Diag(
3107 DAG.getMachineFunction().getFunction(),
3108 "secure entry function would return value through pointer",
3109 SDLoc().getDebugLoc());
3110 DAG.getContext()->diagnose(Diag);
3111 }
3112
3113 // Copy the result values into the output registers.
3114 for (unsigned i = 0, realRVLocIdx = 0;
3115 i != RVLocs.size();
3116 ++i, ++realRVLocIdx) {
3117 CCValAssign &VA = RVLocs[i];
3118 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3118, __extension__ __PRETTY_FUNCTION__))
;
3119
3120 SDValue Arg = OutVals[realRVLocIdx];
3121 bool ReturnF16 = false;
3122
3123 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3124 // Half-precision return values can be returned like this:
3125 //
3126 // t11 f16 = fadd ...
3127 // t12: i16 = bitcast t11
3128 // t13: i32 = zero_extend t12
3129 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3130 //
3131 // to avoid code generation for bitcasts, we simply set Arg to the node
3132 // that produces the f16 value, t11 in this case.
3133 //
3134 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3135 SDValue ZE = Arg.getOperand(0);
3136 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3137 SDValue BC = ZE.getOperand(0);
3138 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3139 Arg = BC.getOperand(0);
3140 ReturnF16 = true;
3141 }
3142 }
3143 }
3144 }
3145
3146 switch (VA.getLocInfo()) {
3147 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3147)
;
3148 case CCValAssign::Full: break;
3149 case CCValAssign::BCvt:
3150 if (!ReturnF16)
3151 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3152 break;
3153 }
3154
3155 // Mask f16 arguments if this is a CMSE nonsecure entry.
3156 auto RetVT = Outs[realRVLocIdx].ArgVT;
3157 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3158 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3159 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3160 } else {
3161 auto LocBits = VA.getLocVT().getSizeInBits();
3162 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3163 SDValue Mask =
3164 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3165 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3166 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3167 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3168 }
3169 }
3170
3171 if (VA.needsCustom() &&
3172 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3173 if (VA.getLocVT() == MVT::v2f64) {
3174 // Extract the first half and return it in two registers.
3175 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3176 DAG.getConstant(0, dl, MVT::i32));
3177 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3178 DAG.getVTList(MVT::i32, MVT::i32), Half);
3179
3180 Chain =
3181 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3182 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3183 Flag = Chain.getValue(1);
3184 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3185 VA = RVLocs[++i]; // skip ahead to next loc
3186 Chain =
3187 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3188 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3189 Flag = Chain.getValue(1);
3190 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3191 VA = RVLocs[++i]; // skip ahead to next loc
3192
3193 // Extract the 2nd half and fall through to handle it as an f64 value.
3194 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3195 DAG.getConstant(1, dl, MVT::i32));
3196 }
3197 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3198 // available.
3199 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3200 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3201 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3202 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3203 Flag = Chain.getValue(1);
3204 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3205 VA = RVLocs[++i]; // skip ahead to next loc
3206 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3207 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3208 } else
3209 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3210
3211 // Guarantee that all emitted copies are
3212 // stuck together, avoiding something bad.
3213 Flag = Chain.getValue(1);
3214 RetOps.push_back(DAG.getRegister(
3215 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3216 }
3217 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3218 const MCPhysReg *I =
3219 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3220 if (I) {
3221 for (; *I; ++I) {
3222 if (ARM::GPRRegClass.contains(*I))
3223 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3224 else if (ARM::DPRRegClass.contains(*I))
3225 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3226 else
3227 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3227)
;
3228 }
3229 }
3230
3231 // Update chain and glue.
3232 RetOps[0] = Chain;
3233 if (Flag.getNode())
3234 RetOps.push_back(Flag);
3235
3236 // CPUs which aren't M-class use a special sequence to return from
3237 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3238 // though we use "subs pc, lr, #N").
3239 //
3240 // M-class CPUs actually use a normal return sequence with a special
3241 // (hardware-provided) value in LR, so the normal code path works.
3242 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3243 !Subtarget->isMClass()) {
3244 if (Subtarget->isThumb1Only())
3245 report_fatal_error("interrupt attribute is not supported in Thumb1");
3246 return LowerInterruptReturn(RetOps, dl, DAG);
3247 }
3248
3249 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3250 ARMISD::RET_FLAG;
3251 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3252}
3253
3254bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3255 if (N->getNumValues() != 1)
3256 return false;
3257 if (!N->hasNUsesOfValue(1, 0))
3258 return false;
3259
3260 SDValue TCChain = Chain;
3261 SDNode *Copy = *N->use_begin();
3262 if (Copy->getOpcode() == ISD::CopyToReg) {
3263 // If the copy has a glue operand, we conservatively assume it isn't safe to
3264 // perform a tail call.
3265 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3266 return false;
3267 TCChain = Copy->getOperand(0);
3268 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3269 SDNode *VMov = Copy;
3270 // f64 returned in a pair of GPRs.
3271 SmallPtrSet<SDNode*, 2> Copies;
3272 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3273 UI != UE; ++UI) {
3274 if (UI->getOpcode() != ISD::CopyToReg)
3275 return false;
3276 Copies.insert(*UI);
3277 }
3278 if (Copies.size() > 2)
3279 return false;
3280
3281 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3282 UI != UE; ++UI) {
3283 SDValue UseChain = UI->getOperand(0);
3284 if (Copies.count(UseChain.getNode()))
3285 // Second CopyToReg
3286 Copy = *UI;
3287 else {
3288 // We are at the top of this chain.
3289 // If the copy has a glue operand, we conservatively assume it
3290 // isn't safe to perform a tail call.
3291 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3292 return false;
3293 // First CopyToReg
3294 TCChain = UseChain;
3295 }
3296 }
3297 } else if (Copy->getOpcode() == ISD::BITCAST) {
3298 // f32 returned in a single GPR.
3299 if (!Copy->hasOneUse())
3300 return false;
3301 Copy = *Copy->use_begin();
3302 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3303 return false;
3304 // If the copy has a glue operand, we conservatively assume it isn't safe to
3305 // perform a tail call.
3306 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3307 return false;
3308 TCChain = Copy->getOperand(0);
3309 } else {
3310 return false;
3311 }
3312
3313 bool HasRet = false;
3314 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3315 UI != UE; ++UI) {
3316 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3317 UI->getOpcode() != ARMISD::INTRET_FLAG)
3318 return false;
3319 HasRet = true;
3320 }
3321
3322 if (!HasRet)
3323 return false;
3324
3325 Chain = TCChain;
3326 return true;
3327}
3328
3329bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3330 if (!Subtarget->supportsTailCall())
3331 return false;
3332
3333 if (!CI->isTailCall())
3334 return false;
3335
3336 return true;
3337}
3338
3339// Trying to write a 64 bit value so need to split into two 32 bit values first,
3340// and pass the lower and high parts through.
3341static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3342 SDLoc DL(Op);
3343 SDValue WriteValue = Op->getOperand(2);
3344
3345 // This function is only supposed to be called for i64 type argument.
3346 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3347, __extension__ __PRETTY_FUNCTION__))
3347 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3347, __extension__ __PRETTY_FUNCTION__))
;
3348
3349 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3350 DAG.getConstant(0, DL, MVT::i32));
3351 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3352 DAG.getConstant(1, DL, MVT::i32));
3353 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3354 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3355}
3356
3357// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3358// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3359// one of the above mentioned nodes. It has to be wrapped because otherwise
3360// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3361// be used to form addressing mode. These wrapped nodes will be selected
3362// into MOVi.
3363SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3364 SelectionDAG &DAG) const {
3365 EVT PtrVT = Op.getValueType();
3366 // FIXME there is no actual debug info here
3367 SDLoc dl(Op);
3368 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3369 SDValue Res;
3370
3371 // When generating execute-only code Constant Pools must be promoted to the
3372 // global data section. It's a bit ugly that we can't share them across basic
3373 // blocks, but this way we guarantee that execute-only behaves correct with
3374 // position-independent addressing modes.
3375 if (Subtarget->genExecuteOnly()) {
3376 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3377 auto T = const_cast<Type*>(CP->getType());
3378 auto C = const_cast<Constant*>(CP->getConstVal());
3379 auto M = const_cast<Module*>(DAG.getMachineFunction().
3380 getFunction().getParent());
3381 auto GV = new GlobalVariable(
3382 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3383 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3384 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3385 Twine(AFI->createPICLabelUId())
3386 );
3387 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3388 dl, PtrVT);
3389 return LowerGlobalAddress(GA, DAG);
3390 }
3391
3392 if (CP->isMachineConstantPoolEntry())
3393 Res =
3394 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3395 else
3396 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3397 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3398}
3399
3400unsigned ARMTargetLowering::getJumpTableEncoding() const {
3401 return MachineJumpTableInfo::EK_Inline;
3402}
3403
3404SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3405 SelectionDAG &DAG) const {
3406 MachineFunction &MF = DAG.getMachineFunction();
3407 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3408 unsigned ARMPCLabelIndex = 0;
3409 SDLoc DL(Op);
3410 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3411 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3412 SDValue CPAddr;
3413 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3414 if (!IsPositionIndependent) {
3415 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3416 } else {
3417 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3418 ARMPCLabelIndex = AFI->createPICLabelUId();
3419 ARMConstantPoolValue *CPV =
3420 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3421 ARMCP::CPBlockAddress, PCAdj);
3422 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3423 }
3424 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3425 SDValue Result = DAG.getLoad(
3426 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3427 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3428 if (!IsPositionIndependent)
3429 return Result;
3430 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3431 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3432}
3433
3434/// Convert a TLS address reference into the correct sequence of loads
3435/// and calls to compute the variable's address for Darwin, and return an
3436/// SDValue containing the final node.
3437
3438/// Darwin only has one TLS scheme which must be capable of dealing with the
3439/// fully general situation, in the worst case. This means:
3440/// + "extern __thread" declaration.
3441/// + Defined in a possibly unknown dynamic library.
3442///
3443/// The general system is that each __thread variable has a [3 x i32] descriptor
3444/// which contains information used by the runtime to calculate the address. The
3445/// only part of this the compiler needs to know about is the first word, which
3446/// contains a function pointer that must be called with the address of the
3447/// entire descriptor in "r0".
3448///
3449/// Since this descriptor may be in a different unit, in general access must
3450/// proceed along the usual ARM rules. A common sequence to produce is:
3451///
3452/// movw rT1, :lower16:_var$non_lazy_ptr
3453/// movt rT1, :upper16:_var$non_lazy_ptr
3454/// ldr r0, [rT1]
3455/// ldr rT2, [r0]
3456/// blx rT2
3457/// [...address now in r0...]
3458SDValue
3459ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3460 SelectionDAG &DAG) const {
3461 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3462, __extension__ __PRETTY_FUNCTION__))
3462 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3462, __extension__ __PRETTY_FUNCTION__))
;
3463 SDLoc DL(Op);
3464
3465 // First step is to get the address of the actua global symbol. This is where
3466 // the TLS descriptor lives.
3467 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3468
3469 // The first entry in the descriptor is a function pointer that we must call
3470 // to obtain the address of the variable.
3471 SDValue Chain = DAG.getEntryNode();
3472 SDValue FuncTLVGet = DAG.getLoad(
3473 MVT::i32, DL, Chain, DescAddr,
3474 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3475 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3476 MachineMemOperand::MOInvariant);
3477 Chain = FuncTLVGet.getValue(1);
3478
3479 MachineFunction &F = DAG.getMachineFunction();
3480 MachineFrameInfo &MFI = F.getFrameInfo();
3481 MFI.setAdjustsStack(true);
3482
3483 // TLS calls preserve all registers except those that absolutely must be
3484 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3485 // silly).
3486 auto TRI =
3487 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3488 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3489 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3490
3491 // Finally, we can make the call. This is just a degenerate version of a
3492 // normal AArch64 call node: r0 takes the address of the descriptor, and
3493 // returns the address of the variable in this thread.
3494 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3495 Chain =
3496 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3497 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3498 DAG.getRegisterMask(Mask), Chain.getValue(1));
3499 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3500}
3501
3502SDValue
3503ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3504 SelectionDAG &DAG) const {
3505 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3505, __extension__ __PRETTY_FUNCTION__))
;
3506
3507 SDValue Chain = DAG.getEntryNode();
3508 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3509 SDLoc DL(Op);
3510
3511 // Load the current TEB (thread environment block)
3512 SDValue Ops[] = {Chain,
3513 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3514 DAG.getTargetConstant(15, DL, MVT::i32),
3515 DAG.getTargetConstant(0, DL, MVT::i32),
3516 DAG.getTargetConstant(13, DL, MVT::i32),
3517 DAG.getTargetConstant(0, DL, MVT::i32),
3518 DAG.getTargetConstant(2, DL, MVT::i32)};
3519 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3520 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3521
3522 SDValue TEB = CurrentTEB.getValue(0);
3523 Chain = CurrentTEB.getValue(1);
3524
3525 // Load the ThreadLocalStoragePointer from the TEB
3526 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3527 SDValue TLSArray =
3528 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3529 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3530
3531 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3532 // offset into the TLSArray.
3533
3534 // Load the TLS index from the C runtime
3535 SDValue TLSIndex =
3536 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3537 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3538 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3539
3540 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3541 DAG.getConstant(2, DL, MVT::i32));
3542 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3543 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3544 MachinePointerInfo());
3545
3546 // Get the offset of the start of the .tls section (section base)
3547 const auto *GA = cast<GlobalAddressSDNode>(Op);
3548 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3549 SDValue Offset = DAG.getLoad(
3550 PtrVT, DL, Chain,
3551 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3552 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3553 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3554
3555 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3556}
3557
3558// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3559SDValue
3560ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3561 SelectionDAG &DAG) const {
3562 SDLoc dl(GA);
3563 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3564 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3565 MachineFunction &MF = DAG.getMachineFunction();
3566 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3567 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3568 ARMConstantPoolValue *CPV =
3569 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3570 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3571 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3572 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3573 Argument = DAG.getLoad(
3574 PtrVT, dl, DAG.getEntryNode(), Argument,
3575 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3576 SDValue Chain = Argument.getValue(1);
3577
3578 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3579 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3580
3581 // call __tls_get_addr.
3582 ArgListTy Args;
3583 ArgListEntry Entry;
3584 Entry.Node = Argument;
3585 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3586 Args.push_back(Entry);
3587
3588 // FIXME: is there useful debug info available here?
3589 TargetLowering::CallLoweringInfo CLI(DAG);
3590 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3591 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3592 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3593
3594 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3595 return CallResult.first;
3596}
3597
3598// Lower ISD::GlobalTLSAddress using the "initial exec" or
3599// "local exec" model.
3600SDValue
3601ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3602 SelectionDAG &DAG,
3603 TLSModel::Model model) const {
3604 const GlobalValue *GV = GA->getGlobal();
3605 SDLoc dl(GA);
3606 SDValue Offset;
3607 SDValue Chain = DAG.getEntryNode();
3608 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3609 // Get the Thread Pointer
3610 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3611
3612 if (model == TLSModel::InitialExec) {
3613 MachineFunction &MF = DAG.getMachineFunction();
3614 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3615 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3616 // Initial exec model.
3617 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3618 ARMConstantPoolValue *CPV =
3619 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3620 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3621 true);
3622 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3623 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3624 Offset = DAG.getLoad(
3625 PtrVT, dl, Chain, Offset,
3626 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3627 Chain = Offset.getValue(1);
3628
3629 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3630 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3631
3632 Offset = DAG.getLoad(
3633 PtrVT, dl, Chain, Offset,
3634 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3635 } else {
3636 // local exec model
3637 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3637, __extension__ __PRETTY_FUNCTION__))
;
3638 ARMConstantPoolValue *CPV =
3639 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3640 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3641 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3642 Offset = DAG.getLoad(
3643 PtrVT, dl, Chain, Offset,
3644 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3645 }
3646
3647 // The address of the thread local variable is the add of the thread
3648 // pointer with the offset of the variable.
3649 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3650}
3651
3652SDValue
3653ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3654 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3655 if (DAG.getTarget().useEmulatedTLS())
3656 return LowerToTLSEmulatedModel(GA, DAG);
3657
3658 if (Subtarget->isTargetDarwin())
3659 return LowerGlobalTLSAddressDarwin(Op, DAG);
3660
3661 if (Subtarget->isTargetWindows())
3662 return LowerGlobalTLSAddressWindows(Op, DAG);
3663
3664 // TODO: implement the "local dynamic" model
3665 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3665, __extension__ __PRETTY_FUNCTION__))
;
3666 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3667
3668 switch (model) {
3669 case TLSModel::GeneralDynamic:
3670 case TLSModel::LocalDynamic:
3671 return LowerToTLSGeneralDynamicModel(GA, DAG);
3672 case TLSModel::InitialExec:
3673 case TLSModel::LocalExec:
3674 return LowerToTLSExecModels(GA, DAG, model);
3675 }
3676 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3676)
;
3677}
3678
3679/// Return true if all users of V are within function F, looking through
3680/// ConstantExprs.
3681static bool allUsersAreInFunction(const Value *V, const Function *F) {
3682 SmallVector<const User*,4> Worklist(V->users());
3683 while (!Worklist.empty()) {
3684 auto *U = Worklist.pop_back_val();
3685 if (isa<ConstantExpr>(U)) {
3686 append_range(Worklist, U->users());
3687 continue;
3688 }
3689
3690 auto *I = dyn_cast<Instruction>(U);
3691 if (!I || I->getParent()->getParent() != F)
3692 return false;
3693 }
3694 return true;
3695}
3696
3697static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3698 const GlobalValue *GV, SelectionDAG &DAG,
3699 EVT PtrVT, const SDLoc &dl) {
3700 // If we're creating a pool entry for a constant global with unnamed address,
3701 // and the global is small enough, we can emit it inline into the constant pool
3702 // to save ourselves an indirection.
3703 //
3704 // This is a win if the constant is only used in one function (so it doesn't
3705 // need to be duplicated) or duplicating the constant wouldn't increase code
3706 // size (implying the constant is no larger than 4 bytes).
3707 const Function &F = DAG.getMachineFunction().getFunction();
3708
3709 // We rely on this decision to inline being idemopotent and unrelated to the
3710 // use-site. We know that if we inline a variable at one use site, we'll
3711 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3712 // doesn't know about this optimization, so bail out if it's enabled else
3713 // we could decide to inline here (and thus never emit the GV) but require
3714 // the GV from fast-isel generated code.
3715 if (!EnableConstpoolPromotion ||
3716 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3717 return SDValue();
3718
3719 auto *GVar = dyn_cast<GlobalVariable>(GV);
3720 if (!GVar || !GVar->hasInitializer() ||
3721 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3722 !GVar->hasLocalLinkage())
3723 return SDValue();
3724
3725 // If we inline a value that contains relocations, we move the relocations
3726 // from .data to .text. This is not allowed in position-independent code.
3727 auto *Init = GVar->getInitializer();
3728 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3729 Init->needsDynamicRelocation())
3730 return SDValue();
3731
3732 // The constant islands pass can only really deal with alignment requests
3733 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3734 // any type wanting greater alignment requirements than 4 bytes. We also
3735 // can only promote constants that are multiples of 4 bytes in size or
3736 // are paddable to a multiple of 4. Currently we only try and pad constants
3737 // that are strings for simplicity.
3738 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3739 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3740 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3741 unsigned RequiredPadding = 4 - (Size % 4);
3742 bool PaddingPossible =
3743 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3744 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3745 Size == 0)
3746 return SDValue();
3747
3748 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3749 MachineFunction &MF = DAG.getMachineFunction();
3750 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3751
3752 // We can't bloat the constant pool too much, else the ConstantIslands pass
3753 // may fail to converge. If we haven't promoted this global yet (it may have
3754 // multiple uses), and promoting it would increase the constant pool size (Sz
3755 // > 4), ensure we have space to do so up to MaxTotal.
3756 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3757 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3758 ConstpoolPromotionMaxTotal)
3759 return SDValue();
3760
3761 // This is only valid if all users are in a single function; we can't clone
3762 // the constant in general. The LLVM IR unnamed_addr allows merging
3763 // constants, but not cloning them.
3764 //
3765 // We could potentially allow cloning if we could prove all uses of the
3766 // constant in the current function don't care about the address, like
3767 // printf format strings. But that isn't implemented for now.
3768 if (!allUsersAreInFunction(GVar, &F))
3769 return SDValue();
3770
3771 // We're going to inline this global. Pad it out if needed.
3772 if (RequiredPadding != 4) {
3773 StringRef S = CDAInit->getAsString();
3774
3775 SmallVector<uint8_t,16> V(S.size());
3776 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3777 while (RequiredPadding--)
3778 V.push_back(0);
3779 Init = ConstantDataArray::get(*DAG.getContext(), V);
3780 }
3781
3782 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3783 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3784 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3785 AFI->markGlobalAsPromotedToConstantPool(GVar);
3786 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3787 PaddedSize - 4);
3788 }
3789 ++NumConstpoolPromoted;
3790 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3791}
3792
3793bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3794 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3795 if (!(GV = GA->getBaseObject()))
3796 return false;
3797 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3798 return V->isConstant();
3799 return isa<Function>(GV);
3800}
3801
3802SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3803 SelectionDAG &DAG) const {
3804 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3805 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3805)
;
3806 case Triple::COFF:
3807 return LowerGlobalAddressWindows(Op, DAG);
3808 case Triple::ELF:
3809 return LowerGlobalAddressELF(Op, DAG);
3810 case Triple::MachO:
3811 return LowerGlobalAddressDarwin(Op, DAG);
3812 }
3813}
3814
3815SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3816 SelectionDAG &DAG) const {
3817 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3818 SDLoc dl(Op);
3819 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3820 const TargetMachine &TM = getTargetMachine();
3821 bool IsRO = isReadOnly(GV);
3822
3823 // promoteToConstantPool only if not generating XO text section
3824 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3825 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3826 return V;
3827
3828 if (isPositionIndependent()) {
3829 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3830 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3831 UseGOT_PREL ? ARMII::MO_GOT : 0);
3832 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3833 if (UseGOT_PREL)
3834 Result =
3835 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3836 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3837 return Result;
3838 } else if (Subtarget->isROPI() && IsRO) {
3839 // PC-relative.
3840 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3841 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3842 return Result;
3843 } else if (Subtarget->isRWPI() && !IsRO) {
3844 // SB-relative.
3845 SDValue RelAddr;
3846 if (Subtarget->useMovt()) {
3847 ++NumMovwMovt;
3848 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3849 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3850 } else { // use literal pool for address constant
3851 ARMConstantPoolValue *CPV =
3852 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3853 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3854 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3855 RelAddr = DAG.getLoad(
3856 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3857 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3858 }
3859 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3860 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3861 return Result;
3862 }
3863
3864 // If we have T2 ops, we can materialize the address directly via movt/movw
3865 // pair. This is always cheaper.
3866 if (Subtarget->useMovt()) {
3867 ++NumMovwMovt;
3868 // FIXME: Once remat is capable of dealing with instructions with register
3869 // operands, expand this into two nodes.
3870 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3871 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3872 } else {
3873 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3874 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3875 return DAG.getLoad(
3876 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3877 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3878 }
3879}
3880
3881SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3882 SelectionDAG &DAG) const {
3883 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3884, __extension__ __PRETTY_FUNCTION__))
3884 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3884, __extension__ __PRETTY_FUNCTION__))
;
3885 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3886 SDLoc dl(Op);
3887 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3888
3889 if (Subtarget->useMovt())
3890 ++NumMovwMovt;
3891
3892 // FIXME: Once remat is capable of dealing with instructions with register
3893 // operands, expand this into multiple nodes
3894 unsigned Wrapper =
3895 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3896
3897 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3898 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3899
3900 if (Subtarget->isGVIndirectSymbol(GV))
3901 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3902 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3903 return Result;
3904}
3905
3906SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3907 SelectionDAG &DAG) const {
3908 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3908, __extension__ __PRETTY_FUNCTION__))
;
3909 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3910, __extension__ __PRETTY_FUNCTION__))
3910 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3910, __extension__ __PRETTY_FUNCTION__))
;
3911 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3912, __extension__ __PRETTY_FUNCTION__))
3912 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3912, __extension__ __PRETTY_FUNCTION__))
;
3913
3914 const TargetMachine &TM = getTargetMachine();
3915 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3916 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3917 if (GV->hasDLLImportStorageClass())
3918 TargetFlags = ARMII::MO_DLLIMPORT;
3919 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3920 TargetFlags = ARMII::MO_COFFSTUB;
3921 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3922 SDValue Result;
3923 SDLoc DL(Op);
3924
3925 ++NumMovwMovt;
3926
3927 // FIXME: Once remat is capable of dealing with instructions with register
3928 // operands, expand this into two nodes.
3929 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3930 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3931 TargetFlags));
3932 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3933 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3934 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3935 return Result;
3936}
3937
3938SDValue
3939ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3940 SDLoc dl(Op);
3941 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3942 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3943 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3944 Op.getOperand(1), Val);
3945}
3946
3947SDValue
3948ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3949 SDLoc dl(Op);
3950 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3951 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3952}
3953
3954SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3955 SelectionDAG &DAG) const {
3956 SDLoc dl(Op);
3957 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3958 Op.getOperand(0));
3959}
3960
3961SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3962 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3963 unsigned IntNo =
3964 cast<ConstantSDNode>(
3965 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3966 ->getZExtValue();
3967 switch (IntNo) {
3968 default:
3969 return SDValue(); // Don't custom lower most intrinsics.
3970 case Intrinsic::arm_gnu_eabi_mcount: {
3971 MachineFunction &MF = DAG.getMachineFunction();
3972 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3973 SDLoc dl(Op);
3974 SDValue Chain = Op.getOperand(0);
3975 // call "\01__gnu_mcount_nc"
3976 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3977 const uint32_t *Mask =
3978 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3979 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3979, __extension__ __PRETTY_FUNCTION__))
;
3980 // Mark LR an implicit live-in.
3981 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3982 SDValue ReturnAddress =
3983 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3984 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3985 SDValue Callee =
3986 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3987 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3988 if (Subtarget->isThumb())
3989 return SDValue(
3990 DAG.getMachineNode(
3991 ARM::tBL_PUSHLR, dl, ResultTys,
3992 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3993 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3994 0);
3995 return SDValue(
3996 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3997 {ReturnAddress, Callee, RegisterMask, Chain}),
3998 0);
3999 }
4000 }
4001}
4002
4003SDValue
4004ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4005 const ARMSubtarget *Subtarget) const {
4006 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4007 SDLoc dl(Op);
4008 switch (IntNo) {
4009 default: return SDValue(); // Don't custom lower most intrinsics.
4010 case Intrinsic::thread_pointer: {
4011 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4012 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4013 }
4014 case Intrinsic::arm_cls: {
4015 const SDValue &Operand = Op.getOperand(1);
4016 const EVT VTy = Op.getValueType();
4017 SDValue SRA =
4018 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4019 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4020 SDValue SHL =
4021 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4022 SDValue OR =
4023 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4024 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4025 return Result;
4026 }
4027 case Intrinsic::arm_cls64: {
4028 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4029 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4030 const SDValue &Operand = Op.getOperand(1);
4031 const EVT VTy = Op.getValueType();
4032
4033 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4034 DAG.getConstant(1, dl, VTy));
4035 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4036 DAG.getConstant(0, dl, VTy));
4037 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4038 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4039 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4040 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4041 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4042 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4043 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4044 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4045 SDValue CheckLo =
4046 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4047 SDValue HiIsZero =
4048 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4049 SDValue AdjustedLo =
4050 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4051 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4052 SDValue Result =
4053 DAG.getSelect(dl, VTy, CheckLo,
4054 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4055 return Result;
4056 }
4057 case Intrinsic::eh_sjlj_lsda: {
4058 MachineFunction &MF = DAG.getMachineFunction();
4059 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4060 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4061 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4062 SDValue CPAddr;
4063 bool IsPositionIndependent = isPositionIndependent();
4064 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4065 ARMConstantPoolValue *CPV =
4066 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4067 ARMCP::CPLSDA, PCAdj);
4068 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4069 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4070 SDValue Result = DAG.getLoad(
4071 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4072 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4073
4074 if (IsPositionIndependent) {
4075 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4076 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4077 }
4078 return Result;
4079 }
4080 case Intrinsic::arm_neon_vabs:
4081 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4082 Op.getOperand(1));
4083 case Intrinsic::arm_neon_vmulls:
4084 case Intrinsic::arm_neon_vmullu: {
4085 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4086 ? ARMISD::VMULLs : ARMISD::VMULLu;
4087 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4088 Op.getOperand(1), Op.getOperand(2));
4089 }
4090 case Intrinsic::arm_neon_vminnm:
4091 case Intrinsic::arm_neon_vmaxnm: {
4092 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4093 ? ISD::FMINNUM : ISD::FMAXNUM;
4094 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4095 Op.getOperand(1), Op.getOperand(2));
4096 }
4097 case Intrinsic::arm_neon_vminu:
4098 case Intrinsic::arm_neon_vmaxu: {
4099 if (Op.getValueType().isFloatingPoint())
4100 return SDValue();
4101 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4102 ? ISD::UMIN : ISD::UMAX;
4103 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4104 Op.getOperand(1), Op.getOperand(2));
4105 }
4106 case Intrinsic::arm_neon_vmins:
4107 case Intrinsic::arm_neon_vmaxs: {
4108 // v{min,max}s is overloaded between signed integers and floats.
4109 if (!Op.getValueType().isFloatingPoint()) {
4110 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4111 ? ISD::SMIN : ISD::SMAX;
4112 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4113 Op.getOperand(1), Op.getOperand(2));
4114 }
4115 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4116 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4117 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4118 Op.getOperand(1), Op.getOperand(2));
4119 }
4120 case Intrinsic::arm_neon_vtbl1:
4121 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4122 Op.getOperand(1), Op.getOperand(2));
4123 case Intrinsic::arm_neon_vtbl2:
4124 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4125 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4126 case Intrinsic::arm_mve_pred_i2v:
4127 case Intrinsic::arm_mve_pred_v2i:
4128 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4129 Op.getOperand(1));
4130 case Intrinsic::arm_mve_vreinterpretq:
4131 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4132 Op.getOperand(1));
4133 case Intrinsic::arm_mve_lsll:
4134 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4135 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4136 case Intrinsic::arm_mve_asrl:
4137 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4138 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4139 }
4140}
4141
4142static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4143 const ARMSubtarget *Subtarget) {
4144 SDLoc dl(Op);
4145 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4146 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4147 if (SSID == SyncScope::SingleThread)
4148 return Op;
4149
4150 if (!Subtarget->hasDataBarrier()) {
4151 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4152 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4153 // here.
4154 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __extension__ __PRETTY_FUNCTION__))
4155 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __extension__ __PRETTY_FUNCTION__))
;
4156 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4157 DAG.getConstant(0, dl, MVT::i32));
4158 }
4159
4160 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4161 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4162 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4163 if (Subtarget->isMClass()) {
4164 // Only a full system barrier exists in the M-class architectures.
4165 Domain = ARM_MB::SY;
4166 } else if (Subtarget->preferISHSTBarriers() &&
4167 Ord == AtomicOrdering::Release) {
4168 // Swift happens to implement ISHST barriers in a way that's compatible with
4169 // Release semantics but weaker than ISH so we'd be fools not to use
4170 // it. Beware: other processors probably don't!
4171 Domain = ARM_MB::ISHST;
4172 }
4173
4174 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4175 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4176 DAG.getConstant(Domain, dl, MVT::i32));
4177}
4178
4179static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4180 const ARMSubtarget *Subtarget) {
4181 // ARM pre v5TE and Thumb1 does not have preload instructions.
4182 if (!(Subtarget->isThumb2() ||
4183 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4184 // Just preserve the chain.
4185 return Op.getOperand(0);
4186
4187 SDLoc dl(Op);
4188 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4189 if (!isRead &&
4190 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4191 // ARMv7 with MP extension has PLDW.
4192 return Op.getOperand(0);
4193
4194 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4195 if (Subtarget->isThumb()) {
4196 // Invert the bits.
4197 isRead = ~isRead & 1;
4198 isData = ~isData & 1;
4199 }
4200
4201 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4202 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4203 DAG.getConstant(isData, dl, MVT::i32));
4204}
4205
4206static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4207 MachineFunction &MF = DAG.getMachineFunction();
4208 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4209
4210 // vastart just stores the address of the VarArgsFrameIndex slot into the
4211 // memory location argument.
4212 SDLoc dl(Op);
4213 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4214 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4215 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4216 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4217 MachinePointerInfo(SV));
4218}
4219
4220SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4221 CCValAssign &NextVA,
4222 SDValue &Root,
4223 SelectionDAG &DAG,
4224 const SDLoc &dl) const {
4225 MachineFunction &MF = DAG.getMachineFunction();
4226 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4227
4228 const TargetRegisterClass *RC;
4229 if (AFI->isThumb1OnlyFunction())
4230 RC = &ARM::tGPRRegClass;
4231 else
4232 RC = &ARM::GPRRegClass;
4233
4234 // Transform the arguments stored in physical registers into virtual ones.
4235 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4236 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4237
4238 SDValue ArgValue2;
4239 if (NextVA.isMemLoc()) {
4240 MachineFrameInfo &MFI = MF.getFrameInfo();
4241 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4242
4243 // Create load node to retrieve arguments from the stack.
4244 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4245 ArgValue2 = DAG.getLoad(
4246 MVT::i32, dl, Root, FIN,
4247 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4248 } else {
4249 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4250 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4251 }
4252 if (!Subtarget->isLittle())
4253 std::swap (ArgValue, ArgValue2);
4254 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4255}
4256
4257// The remaining GPRs hold either the beginning of variable-argument
4258// data, or the beginning of an aggregate passed by value (usually
4259// byval). Either way, we allocate stack slots adjacent to the data
4260// provided by our caller, and store the unallocated registers there.
4261// If this is a variadic function, the va_list pointer will begin with
4262// these values; otherwise, this reassembles a (byval) structure that
4263// was split between registers and memory.
4264// Return: The frame index registers were stored into.
4265int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4266 const SDLoc &dl, SDValue &Chain,
4267 const Value *OrigArg,
4268 unsigned InRegsParamRecordIdx,
4269 int ArgOffset, unsigned ArgSize) const {
4270 // Currently, two use-cases possible:
4271 // Case #1. Non-var-args function, and we meet first byval parameter.
4272 // Setup first unallocated register as first byval register;
4273 // eat all remained registers
4274 // (these two actions are performed by HandleByVal method).
4275 // Then, here, we initialize stack frame with
4276 // "store-reg" instructions.
4277 // Case #2. Var-args function, that doesn't contain byval parameters.
4278 // The same: eat all remained unallocated registers,
4279 // initialize stack frame.
4280
4281 MachineFunction &MF = DAG.getMachineFunction();
4282 MachineFrameInfo &MFI = MF.getFrameInfo();
4283 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4284 unsigned RBegin, REnd;
4285 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4286 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4287 } else {
4288 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4289 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4290 REnd = ARM::R4;
4291 }
4292
4293 if (REnd != RBegin)
4294 ArgOffset = -4 * (ARM::R4 - RBegin);
4295
4296 auto PtrVT = getPointerTy(DAG.getDataLayout());
4297 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4298 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4299
4300 SmallVector<SDValue, 4> MemOps;
4301 const TargetRegisterClass *RC =
4302 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4303
4304 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4305 unsigned VReg = MF.addLiveIn(Reg, RC);
4306 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4307 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4308 MachinePointerInfo(OrigArg, 4 * i));
4309 MemOps.push_back(Store);
4310 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4311 }
4312
4313 if (!MemOps.empty())
4314 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4315 return FrameIndex;
4316}
4317
4318// Setup stack frame, the va_list pointer will start from.
4319void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4320 const SDLoc &dl, SDValue &Chain,
4321 unsigned ArgOffset,
4322 unsigned TotalArgRegsSaveSize,
4323 bool ForceMutable) const {
4324 MachineFunction &MF = DAG.getMachineFunction();
4325 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4326
4327 // Try to store any remaining integer argument regs
4328 // to their spots on the stack so that they may be loaded by dereferencing
4329 // the result of va_next.
4330 // If there is no regs to be stored, just point address after last
4331 // argument passed via stack.
4332 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4333 CCInfo.getInRegsParamsCount(),
4334 CCInfo.getNextStackOffset(),
4335 std::max(4U, TotalArgRegsSaveSize));
4336 AFI->setVarArgsFrameIndex(FrameIndex);
4337}
4338
4339bool ARMTargetLowering::splitValueIntoRegisterParts(
4340 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4341 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4342 bool IsABIRegCopy = CC.hasValue();
4343 EVT ValueVT = Val.getValueType();
4344 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4345 PartVT == MVT::f32) {
4346 unsigned ValueBits = ValueVT.getSizeInBits();
4347 unsigned PartBits = PartVT.getSizeInBits();
4348 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4349 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4350 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4351 Parts[0] = Val;
4352 return true;
4353 }
4354 return false;
4355}
4356
4357SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4358 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4359 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4360 bool IsABIRegCopy = CC.hasValue();
4361 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4362 PartVT == MVT::f32) {
4363 unsigned ValueBits = ValueVT.getSizeInBits();
4364 unsigned PartBits = PartVT.getSizeInBits();
4365 SDValue Val = Parts[0];
4366
4367 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4368 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4369 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4370 return Val;
4371 }
4372 return SDValue();
4373}
4374
4375SDValue ARMTargetLowering::LowerFormalArguments(
4376 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4377 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4378 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4379 MachineFunction &MF = DAG.getMachineFunction();
4380 MachineFrameInfo &MFI = MF.getFrameInfo();
4381
4382 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4383
4384 // Assign locations to all of the incoming arguments.
4385 SmallVector<CCValAssign, 16> ArgLocs;
4386 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4387 *DAG.getContext());
4388 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4389
4390 SmallVector<SDValue, 16> ArgValues;
4391 SDValue ArgValue;
4392 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4393 unsigned CurArgIdx = 0;
4394
4395 // Initially ArgRegsSaveSize is zero.
4396 // Then we increase this value each time we meet byval parameter.
4397 // We also increase this value in case of varargs function.
4398 AFI->setArgRegsSaveSize(0);
4399
4400 // Calculate the amount of stack space that we need to allocate to store
4401 // byval and variadic arguments that are passed in registers.
4402 // We need to know this before we allocate the first byval or variadic
4403 // argument, as they will be allocated a stack slot below the CFA (Canonical
4404 // Frame Address, the stack pointer at entry to the function).
4405 unsigned ArgRegBegin = ARM::R4;
4406 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4407 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4408 break;
4409
4410 CCValAssign &VA = ArgLocs[i];
4411 unsigned Index = VA.getValNo();
4412 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4413 if (!Flags.isByVal())
4414 continue;
4415
4416 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4416, __extension__ __PRETTY_FUNCTION__))
;
4417 unsigned RBegin, REnd;
4418 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4419 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4420
4421 CCInfo.nextInRegsParam();
4422 }
4423 CCInfo.rewindByValRegsInfo();
4424
4425 int lastInsIndex = -1;
4426 if (isVarArg && MFI.hasVAStart()) {
4427 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4428 if (RegIdx != array_lengthof(GPRArgRegs))
4429 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4430 }
4431
4432 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4433 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4434 auto PtrVT = getPointerTy(DAG.getDataLayout());
4435
4436 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4437 CCValAssign &VA = ArgLocs[i];
4438 if (Ins[VA.getValNo()].isOrigArg()) {
4439 std::advance(CurOrigArg,
4440 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4441 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4442 }
4443 // Arguments stored in registers.
4444 if (VA.isRegLoc()) {
4445 EVT RegVT = VA.getLocVT();
4446
4447 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4448 // f64 and vector types are split up into multiple registers or
4449 // combinations of registers and stack slots.
4450 SDValue ArgValue1 =
4451 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4452 VA = ArgLocs[++i]; // skip ahead to next loc
4453 SDValue ArgValue2;
4454 if (VA.isMemLoc()) {
4455 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4456 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4457 ArgValue2 = DAG.getLoad(
4458 MVT::f64, dl, Chain, FIN,
4459 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4460 } else {
4461 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4462 }
4463 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4464 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4465 ArgValue1, DAG.getIntPtrConstant(0, dl));
4466 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4467 ArgValue2, DAG.getIntPtrConstant(1, dl));
4468 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4469 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4470 } else {
4471 const TargetRegisterClass *RC;
4472
4473 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4474 RC = &ARM::HPRRegClass;
4475 else if (RegVT == MVT::f32)
4476 RC = &ARM::SPRRegClass;
4477 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4478 RegVT == MVT::v4bf16)
4479 RC = &ARM::DPRRegClass;
4480 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4481 RegVT == MVT::v8bf16)
4482 RC = &ARM::QPRRegClass;
4483 else if (RegVT == MVT::i32)
4484 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4485 : &ARM::GPRRegClass;
4486 else
4487 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4487)
;
4488
4489 // Transform the arguments in physical registers into virtual ones.
4490 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4491 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4492
4493 // If this value is passed in r0 and has the returned attribute (e.g.
4494 // C++ 'structors), record this fact for later use.
4495 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4496 AFI->setPreservesR0();
4497 }
4498 }
4499
4500 // If this is an 8 or 16-bit value, it is really passed promoted
4501 // to 32 bits. Insert an assert[sz]ext to capture this, then
4502 // truncate to the right size.
4503 switch (VA.getLocInfo()) {
4504 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4504)
;
4505 case CCValAssign::Full: break;
4506 case CCValAssign::BCvt:
4507 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4508 break;
4509 case CCValAssign::SExt:
4510 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4511 DAG.getValueType(VA.getValVT()));
4512 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4513 break;
4514 case CCValAssign::ZExt:
4515 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4516 DAG.getValueType(VA.getValVT()));
4517 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4518 break;
4519 }
4520
4521 // f16 arguments have their size extended to 4 bytes and passed as if they
4522 // had been copied to the LSBs of a 32-bit register.
4523 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4524 if (VA.needsCustom() &&
4525 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4526 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4527
4528 InVals.push_back(ArgValue);
4529 } else { // VA.isRegLoc()
4530 // sanity check
4531 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4531, __extension__ __PRETTY_FUNCTION__))
;
4532 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4532, __extension__ __PRETTY_FUNCTION__))
;
4533
4534 int index = VA.getValNo();
4535
4536 // Some Ins[] entries become multiple ArgLoc[] entries.
4537 // Process them only once.
4538 if (index != lastInsIndex)
4539 {
4540 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4541 // FIXME: For now, all byval parameter objects are marked mutable.
4542 // This can be changed with more analysis.
4543 // In case of tail call optimization mark all arguments mutable.
4544 // Since they could be overwritten by lowering of arguments in case of
4545 // a tail call.
4546 if (Flags.isByVal()) {
4547 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4548, __extension__ __PRETTY_FUNCTION__))
4548 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4548, __extension__ __PRETTY_FUNCTION__))
;
4549 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4550
4551 int FrameIndex = StoreByValRegs(
4552 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4553 VA.getLocMemOffset(), Flags.getByValSize());
4554 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4555 CCInfo.nextInRegsParam();
4556 } else {
4557 unsigned FIOffset = VA.getLocMemOffset();
4558 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4559 FIOffset, true);
4560
4561 // Create load nodes to retrieve arguments from the stack.
4562 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4563 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4564 MachinePointerInfo::getFixedStack(
4565 DAG.getMachineFunction(), FI)));
4566 }
4567 lastInsIndex = index;
4568 }
4569 }
4570 }
4571
4572 // varargs
4573 if (isVarArg && MFI.hasVAStart()) {
4574 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4575 TotalArgRegsSaveSize);
4576 if (AFI->isCmseNSEntryFunction()) {
4577 DiagnosticInfoUnsupported Diag(
4578 DAG.getMachineFunction().getFunction(),
4579 "secure entry function must not be variadic", dl.getDebugLoc());
4580 DAG.getContext()->diagnose(Diag);
4581 }
4582 }
4583
4584 unsigned StackArgSize = CCInfo.getNextStackOffset();
4585 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4586 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4587 // The only way to guarantee a tail call is if the callee restores its
4588 // argument area, but it must also keep the stack aligned when doing so.
4589 const DataLayout &DL = DAG.getDataLayout();
4590 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4591
4592 AFI->setArgumentStackToRestore(StackArgSize);
4593 }
4594 AFI->setArgumentStackSize(StackArgSize);
4595
4596 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4597 DiagnosticInfoUnsupported Diag(
4598 DAG.getMachineFunction().getFunction(),
4599 "secure entry function requires arguments on stack", dl.getDebugLoc());
4600 DAG.getContext()->diagnose(Diag);
4601 }
4602
4603 return Chain;
4604}
4605
4606/// isFloatingPointZero - Return true if this is +0.0.
4607static bool isFloatingPointZero(SDValue Op) {
4608 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4609 return CFP->getValueAPF().isPosZero();
4610 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4611 // Maybe this has already been legalized into the constant pool?
4612 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4613 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4614 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4615 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4616 return CFP->getValueAPF().isPosZero();
4617 }
4618 } else if (Op->getOpcode() == ISD::BITCAST &&
4619 Op->getValueType(0) == MVT::f64) {
4620 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4621 // created by LowerConstantFP().
4622 SDValue BitcastOp = Op->getOperand(0);
4623 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4624 isNullConstant(BitcastOp->getOperand(0)))
4625 return true;
4626 }
4627 return false;
4628}
4629
4630/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4631/// the given operands.
4632SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4633 SDValue &ARMcc, SelectionDAG &DAG,
4634 const SDLoc &dl) const {
4635 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4636 unsigned C = RHSC->getZExtValue();
4637 if (!isLegalICmpImmediate((int32_t)C)) {
4638 // Constant does not fit, try adjusting it by one.
4639 switch (CC) {
4640 default: break;
4641 case ISD::SETLT:
4642 case ISD::SETGE:
4643 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4644 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4645 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4646 }
4647 break;
4648 case ISD::SETULT:
4649 case ISD::SETUGE:
4650 if (C != 0 && isLegalICmpImmediate(C-1)) {
4651 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4652 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4653 }
4654 break;
4655 case ISD::SETLE:
4656 case ISD::SETGT:
4657 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4658 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4659 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4660 }
4661 break;
4662 case ISD::SETULE:
4663 case ISD::SETUGT:
4664 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4665 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4666 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4667 }
4668 break;
4669 }
4670 }
4671 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4672 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4673 // In ARM and Thumb-2, the compare instructions can shift their second
4674 // operand.
4675 CC = ISD::getSetCCSwappedOperands(CC);
4676 std::swap(LHS, RHS);
4677 }
4678
4679 // Thumb1 has very limited immediate modes, so turning an "and" into a
4680 // shift can save multiple instructions.
4681 //
4682 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4683 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4684 // own. If it's the operand to an unsigned comparison with an immediate,
4685 // we can eliminate one of the shifts: we transform
4686 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4687 //
4688 // We avoid transforming cases which aren't profitable due to encoding
4689 // details:
4690 //
4691 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4692 // would not; in that case, we're essentially trading one immediate load for
4693 // another.
4694 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4695 // 3. C2 is zero; we have other code for this special case.
4696 //
4697 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4698 // instruction, since the AND is always one instruction anyway, but we could
4699 // use narrow instructions in some cases.
4700 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4701 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4702 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4703 !isSignedIntSetCC(CC)) {
4704 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4705 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4706 uint64_t RHSV = RHSC->getZExtValue();
4707 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4708 unsigned ShiftBits = countLeadingZeros(Mask);
4709 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4710 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4711 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4712 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4713 }
4714 }
4715 }
4716
4717 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4718 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4719 // way a cmp would.
4720 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4721 // some tweaks to the heuristics for the previous and->shift transform.
4722 // FIXME: Optimize cases where the LHS isn't a shift.
4723 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4724 isa<ConstantSDNode>(RHS) &&
4725 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4726 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4727 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4728 unsigned ShiftAmt =
4729 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4730 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4731 DAG.getVTList(MVT::i32, MVT::i32),
4732 LHS.getOperand(0),
4733 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4734 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4735 Shift.getValue(1), SDValue());
4736 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4737 return Chain.getValue(1);
4738 }
4739
4740 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4741
4742 // If the RHS is a constant zero then the V (overflow) flag will never be
4743 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4744 // simpler for other passes (like the peephole optimiser) to deal with.
4745 if (isNullConstant(RHS)) {
4746 switch (CondCode) {
4747 default: break;
4748 case ARMCC::GE:
4749 CondCode = ARMCC::PL;
4750 break;
4751 case ARMCC::LT:
4752 CondCode = ARMCC::MI;
4753 break;
4754 }
4755 }
4756
4757 ARMISD::NodeType CompareType;
4758 switch (CondCode) {
4759 default:
4760 CompareType = ARMISD::CMP;
4761 break;
4762 case ARMCC::EQ:
4763 case ARMCC::NE:
4764 // Uses only Z Flag
4765 CompareType = ARMISD::CMPZ;
4766 break;
4767 }
4768 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4769 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4770}
4771
4772/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4773SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4774 SelectionDAG &DAG, const SDLoc &dl,
4775 bool Signaling) const {
4776 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4776, __extension__ __PRETTY_FUNCTION__))
;
4777 SDValue Cmp;
4778 if (!isFloatingPointZero(RHS))
4779 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4780 dl, MVT::Glue, LHS, RHS);
4781 else
4782 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4783 dl, MVT::Glue, LHS);
4784 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4785}
4786
4787/// duplicateCmp - Glue values can have only one use, so this function
4788/// duplicates a comparison node.
4789SDValue
4790ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4791 unsigned Opc = Cmp.getOpcode();
4792 SDLoc DL(Cmp);
4793 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4794 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4795
4796 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4796, __extension__ __PRETTY_FUNCTION__))
;
4797 Cmp = Cmp.getOperand(0);
4798 Opc = Cmp.getOpcode();
4799 if (Opc == ARMISD::CMPFP)
4800 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4801 else {
4802 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4802, __extension__ __PRETTY_FUNCTION__))
;
4803 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4804 }
4805 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4806}
4807
4808// This function returns three things: the arithmetic computation itself
4809// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4810// comparison and the condition code define the case in which the arithmetic
4811// computation *does not* overflow.
4812std::pair<SDValue, SDValue>
4813ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4814 SDValue &ARMcc) const {
4815 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4815, __extension__ __PRETTY_FUNCTION__))
;
4816
4817 SDValue Value, OverflowCmp;
4818 SDValue LHS = Op.getOperand(0);
4819 SDValue RHS = Op.getOperand(1);
4820 SDLoc dl(Op);
4821
4822 // FIXME: We are currently always generating CMPs because we don't support
4823 // generating CMN through the backend. This is not as good as the natural
4824 // CMP case because it causes a register dependency and cannot be folded
4825 // later.
4826
4827 switch (Op.getOpcode()) {
4828 default:
4829 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4829)
;
4830 case ISD::SADDO:
4831 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4832 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4833 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4834 break;
4835 case ISD::UADDO:
4836 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4837 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4838 // We do not use it in the USUBO case as Value may not be used.
4839 Value = DAG.getNode(ARMISD::ADDC, dl,
4840 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4841 .getValue(0);
4842 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4843 break;
4844 case ISD::SSUBO:
4845 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4846 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4847 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4848 break;
4849 case ISD::USUBO:
4850 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4851 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4852 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4853 break;
4854 case ISD::UMULO:
4855 // We generate a UMUL_LOHI and then check if the high word is 0.
4856 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4857 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4858 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4859 LHS, RHS);
4860 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4861 DAG.getConstant(0, dl, MVT::i32));
4862 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4863 break;
4864 case ISD::SMULO:
4865 // We generate a SMUL_LOHI and then check if all the bits of the high word
4866 // are the same as the sign bit of the low word.
4867 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4868 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4869 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4870 LHS, RHS);
4871 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4872 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4873 Value.getValue(0),
4874 DAG.getConstant(31, dl, MVT::i32)));
4875 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4876 break;
4877 } // switch (...)
4878
4879 return std::make_pair(Value, OverflowCmp);
4880}
4881
4882SDValue
4883ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4884 // Let legalize expand this if it isn't a legal type yet.
4885 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4886 return SDValue();
4887
4888 SDValue Value, OverflowCmp;
4889 SDValue ARMcc;
4890 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4891 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4892 SDLoc dl(Op);
4893 // We use 0 and 1 as false and true values.
4894 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4895 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4896 EVT VT = Op.getValueType();
4897
4898 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4899 ARMcc, CCR, OverflowCmp);
4900
4901 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4902 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4903}
4904
4905static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4906 SelectionDAG &DAG) {
4907 SDLoc DL(BoolCarry);
4908 EVT CarryVT = BoolCarry.getValueType();
4909
4910 // This converts the boolean value carry into the carry flag by doing
4911 // ARMISD::SUBC Carry, 1
4912 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4913 DAG.getVTList(CarryVT, MVT::i32),
4914 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4915 return Carry.getValue(1);
4916}
4917
4918static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4919 SelectionDAG &DAG) {
4920 SDLoc DL(Flags);
4921
4922 // Now convert the carry flag into a boolean carry. We do this
4923 // using ARMISD:ADDE 0, 0, Carry
4924 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4925 DAG.getConstant(0, DL, MVT::i32),
4926 DAG.getConstant(0, DL, MVT::i32), Flags);
4927}
4928
4929SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4930 SelectionDAG &DAG) const {
4931 // Let legalize expand this if it isn't a legal type yet.
4932 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4933 return SDValue();
4934
4935 SDValue LHS = Op.getOperand(0);
4936 SDValue RHS = Op.getOperand(1);
4937 SDLoc dl(Op);
4938
4939 EVT VT = Op.getValueType();
4940 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4941 SDValue Value;
4942 SDValue Overflow;
4943 switch (Op.getOpcode()) {
4944 default:
4945 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4945)
;
4946 case ISD::UADDO:
4947 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4948 // Convert the carry flag into a boolean value.
4949 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4950 break;
4951 case ISD::USUBO: {
4952 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4953 // Convert the carry flag into a boolean value.
4954 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4955 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4956 // value. So compute 1 - C.
4957 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4958 DAG.getConstant(1, dl, MVT::i32), Overflow);
4959 break;
4960 }
4961 }
4962
4963 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4964}
4965
4966static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4967 const ARMSubtarget *Subtarget) {
4968 EVT VT = Op.getValueType();
4969 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
4970 return SDValue();
4971 if (!VT.isSimple())
4972 return SDValue();
4973
4974 unsigned NewOpcode;
4975 switch (VT.getSimpleVT().SimpleTy) {
4976 default:
4977 return SDValue();
4978 case MVT::i8:
4979 switch (Op->getOpcode()) {
4980 case ISD::UADDSAT:
4981 NewOpcode = ARMISD::UQADD8b;
4982 break;
4983 case ISD::SADDSAT:
4984 NewOpcode = ARMISD::QADD8b;
4985 break;
4986 case ISD::USUBSAT:
4987 NewOpcode = ARMISD::UQSUB8b;
4988 break;
4989 case ISD::SSUBSAT:
4990 NewOpcode = ARMISD::QSUB8b;
4991 break;
4992 }
4993 break;
4994 case MVT::i16:
4995 switch (Op->getOpcode()) {
4996 case ISD::UADDSAT:
4997 NewOpcode = ARMISD::UQADD16b;
4998 break;
4999 case ISD::SADDSAT:
5000 NewOpcode = ARMISD::QADD16b;
5001 break;
5002 case ISD::USUBSAT:
5003 NewOpcode = ARMISD::UQSUB16b;
5004 break;
5005 case ISD::SSUBSAT:
5006 NewOpcode = ARMISD::QSUB16b;
5007 break;
5008 }
5009 break;
5010 }
5011
5012 SDLoc dl(Op);
5013 SDValue Add =
5014 DAG.getNode(NewOpcode, dl, MVT::i32,
5015 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5016 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5017 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5018}
5019
5020SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5021 SDValue Cond = Op.getOperand(0);
5022 SDValue SelectTrue = Op.getOperand(1);
5023 SDValue SelectFalse = Op.getOperand(2);
5024 SDLoc dl(Op);
5025 unsigned Opc = Cond.getOpcode();
5026
5027 if (Cond.getResNo() == 1 &&
5028 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5029 Opc == ISD::USUBO)) {
5030 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5031 return SDValue();
5032
5033 SDValue Value, OverflowCmp;
5034 SDValue ARMcc;
5035 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5036 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5037 EVT VT = Op.getValueType();
5038
5039 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5040 OverflowCmp, DAG);
5041 }
5042
5043 // Convert:
5044 //
5045 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5046 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5047 //
5048 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5049 const ConstantSDNode *CMOVTrue =
5050 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5051 const ConstantSDNode *CMOVFalse =
5052 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5053
5054 if (CMOVTrue && CMOVFalse) {
5055 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5056 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5057
5058 SDValue True;
5059 SDValue False;
5060 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5061 True = SelectTrue;
5062 False = SelectFalse;
5063 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5064 True = SelectFalse;
5065 False = SelectTrue;
5066 }
5067
5068 if (True.getNode() && False.getNode()) {
5069 EVT VT = Op.getValueType();
5070 SDValue ARMcc = Cond.getOperand(2);
5071 SDValue CCR = Cond.getOperand(3);
5072 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5073 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5073, __extension__ __PRETTY_FUNCTION__))
;
5074 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5075 }
5076 }
5077 }
5078
5079 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5080 // undefined bits before doing a full-word comparison with zero.
5081 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5082 DAG.getConstant(1, dl, Cond.getValueType()));
5083
5084 return DAG.getSelectCC(dl, Cond,
5085 DAG.getConstant(0, dl, Cond.getValueType()),
5086 SelectTrue, SelectFalse, ISD::SETNE);
5087}
5088
5089static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5090 bool &swpCmpOps, bool &swpVselOps) {
5091 // Start by selecting the GE condition code for opcodes that return true for
5092 // 'equality'
5093 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5094 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5095 CondCode = ARMCC::GE;
5096
5097 // and GT for opcodes that return false for 'equality'.
5098 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5099 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5100 CondCode = ARMCC::GT;
5101
5102 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5103 // to swap the compare operands.
5104 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5105 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5106 swpCmpOps = true;
5107
5108 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5109 // If we have an unordered opcode, we need to swap the operands to the VSEL
5110 // instruction (effectively negating the condition).
5111 //
5112 // This also has the effect of swapping which one of 'less' or 'greater'
5113 // returns true, so we also swap the compare operands. It also switches
5114 // whether we return true for 'equality', so we compensate by picking the
5115 // opposite condition code to our original choice.
5116 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5117 CC == ISD::SETUGT) {
5118 swpCmpOps = !swpCmpOps;
5119 swpVselOps = !swpVselOps;
5120 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5121 }
5122
5123 // 'ordered' is 'anything but unordered', so use the VS condition code and
5124 // swap the VSEL operands.
5125 if (CC == ISD::SETO) {
5126 CondCode = ARMCC::VS;
5127 swpVselOps = true;
5128 }
5129
5130 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5131 // code and swap the VSEL operands. Also do this if we don't care about the
5132 // unordered case.
5133 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5134 CondCode = ARMCC::EQ;
5135 swpVselOps = true;
5136 }
5137}
5138
5139SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5140 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5141 SDValue Cmp, SelectionDAG &DAG) const {
5142 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5143 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5144 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5145 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5146 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5147
5148 SDValue TrueLow = TrueVal.getValue(0);
5149 SDValue TrueHigh = TrueVal.getValue(1);
5150 SDValue FalseLow = FalseVal.getValue(0);
5151 SDValue FalseHigh = FalseVal.getValue(1);
5152
5153 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5154 ARMcc, CCR, Cmp);
5155 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5156 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5157
5158 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5159 } else {
5160 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5161 Cmp);
5162 }
5163}
5164
5165static bool isGTorGE(ISD::CondCode CC) {
5166 return CC == ISD::SETGT || CC == ISD::SETGE;
5167}
5168
5169static bool isLTorLE(ISD::CondCode CC) {
5170 return CC == ISD::SETLT || CC == ISD::SETLE;
5171}
5172
5173// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5174// All of these conditions (and their <= and >= counterparts) will do:
5175// x < k ? k : x
5176// x > k ? x : k
5177// k < x ? x : k
5178// k > x ? k : x
5179static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5180 const SDValue TrueVal, const SDValue FalseVal,
5181 const ISD::CondCode CC, const SDValue K) {
5182 return (isGTorGE(CC) &&
5183 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5184 (isLTorLE(CC) &&
5185 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5186}
5187
5188// Check if two chained conditionals could be converted into SSAT or USAT.
5189//
5190// SSAT can replace a set of two conditional selectors that bound a number to an
5191// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5192//
5193// x < -k ? -k : (x > k ? k : x)
5194// x < -k ? -k : (x < k ? x : k)
5195// x > -k ? (x > k ? k : x) : -k
5196// x < k ? (x < -k ? -k : x) : k
5197// etc.
5198//
5199// LLVM canonicalizes these to either a min(max()) or a max(min())
5200// pattern. This function tries to match one of these and will return a SSAT
5201// node if successful.
5202//
5203// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5204// is a power of 2.
5205static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5206 EVT VT = Op.getValueType();
5207 SDValue V1 = Op.getOperand(0);
5208 SDValue K1 = Op.getOperand(1);
5209 SDValue TrueVal1 = Op.getOperand(2);
5210 SDValue FalseVal1 = Op.getOperand(3);
5211 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5212
5213 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5214 if (Op2.getOpcode() != ISD::SELECT_CC)
5215 return SDValue();
5216
5217 SDValue V2 = Op2.getOperand(0);
5218 SDValue K2 = Op2.getOperand(1);
5219 SDValue TrueVal2 = Op2.getOperand(2);
5220 SDValue FalseVal2 = Op2.getOperand(3);
5221 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5222
5223 SDValue V1Tmp = V1;
5224 SDValue V2Tmp = V2;
5225
5226 // Check that the registers and the constants match a max(min()) or min(max())
5227 // pattern
5228 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5229 K2 != FalseVal2 ||
5230 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5231 return SDValue();
5232
5233 // Check that the constant in the lower-bound check is
5234 // the opposite of the constant in the upper-bound check
5235 // in 1's complement.
5236 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5237 return SDValue();
5238
5239 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5240 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5241 int64_t PosVal = std::max(Val1, Val2);
5242 int64_t NegVal = std::min(Val1, Val2);
5243
5244 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5245 !isPowerOf2_64(PosVal + 1))
5246 return SDValue();
5247
5248 // Handle the difference between USAT (unsigned) and SSAT (signed)
5249 // saturation
5250 // At this point, PosVal is guaranteed to be positive
5251 uint64_t K = PosVal;
5252 SDLoc dl(Op);
5253 if (Val1 == ~Val2)
5254 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5255 DAG.getConstant(countTrailingOnes(K), dl, VT));
5256 if (NegVal == 0)
5257 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5258 DAG.getConstant(countTrailingOnes(K), dl, VT));
5259
5260 return SDValue();
5261}
5262
5263// Check if a condition of the type x < k ? k : x can be converted into a
5264// bit operation instead of conditional moves.
5265// Currently this is allowed given:
5266// - The conditions and values match up
5267// - k is 0 or -1 (all ones)
5268// This function will not check the last condition, thats up to the caller
5269// It returns true if the transformation can be made, and in such case
5270// returns x in V, and k in SatK.
5271static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5272 SDValue &SatK)
5273{
5274 SDValue LHS = Op.getOperand(0);
5275 SDValue RHS = Op.getOperand(1);
5276 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5277 SDValue TrueVal = Op.getOperand(2);
5278 SDValue FalseVal = Op.getOperand(3);
5279
5280 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5281 ? &RHS
5282 : nullptr;
5283
5284 // No constant operation in comparison, early out
5285 if (!K)
5286 return false;
5287
5288 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5289 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5290 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5291
5292 // If the constant on left and right side, or variable on left and right,
5293 // does not match, early out
5294 if (*K != KTmp || V != VTmp)
5295 return false;
5296
5297 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5298 SatK = *K;
5299 return true;
5300 }
5301
5302 return false;
5303}
5304
5305bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5306 if (VT == MVT::f32)
5307 return !Subtarget->hasVFP2Base();
5308 if (VT == MVT::f64)
5309 return !Subtarget->hasFP64();
5310 if (VT == MVT::f16)
5311 return !Subtarget->hasFullFP16();
5312 return false;
5313}
5314
5315SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5316 EVT VT = Op.getValueType();
5317 SDLoc dl(Op);
5318
5319 // Try to convert two saturating conditional selects into a single SSAT
5320 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5321 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5322 return SatValue;
5323
5324 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5325 // into more efficient bit operations, which is possible when k is 0 or -1
5326 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5327 // single instructions. On Thumb the shift and the bit operation will be two
5328 // instructions.
5329 // Only allow this transformation on full-width (32-bit) operations
5330 SDValue LowerSatConstant;
5331 SDValue SatValue;
5332 if (VT == MVT::i32 &&
5333 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5334 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5335 DAG.getConstant(31, dl, VT));
5336 if (isNullConstant(LowerSatConstant)) {
5337 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5338 DAG.getAllOnesConstant(dl, VT));
5339 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5340 } else if (isAllOnesConstant(LowerSatConstant))
5341 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5342 }
5343
5344 SDValue LHS = Op.getOperand(0);
5345 SDValue RHS = Op.getOperand(1);
5346 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5347 SDValue TrueVal = Op.getOperand(2);
5348 SDValue FalseVal = Op.getOperand(3);
5349 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5350 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5351
5352 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5353 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5354 unsigned TVal = CTVal->getZExtValue();
5355 unsigned FVal = CFVal->getZExtValue();
5356 unsigned Opcode = 0;
5357
5358 if (TVal == ~FVal) {
5359 Opcode = ARMISD::CSINV;
5360 } else if (TVal == ~FVal + 1) {
5361 Opcode = ARMISD::CSNEG;
5362 } else if (TVal + 1 == FVal) {
5363 Opcode = ARMISD::CSINC;
5364 } else if (TVal == FVal + 1) {
5365 Opcode = ARMISD::CSINC;
5366 std::swap(TrueVal, FalseVal);
5367 std::swap(TVal, FVal);
5368 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5369 }
5370
5371 if (Opcode) {
5372 // If one of the constants is cheaper than another, materialise the
5373 // cheaper one and let the csel generate the other.
5374 if (Opcode != ARMISD::CSINC &&
5375 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5376 std::swap(TrueVal, FalseVal);
5377 std::swap(TVal, FVal);
5378 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5379 }
5380
5381 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5382 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5383 // -(-a) == a, but (a+1)+1 != a).
5384 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5385 std::swap(TrueVal, FalseVal);
5386 std::swap(TVal, FVal);
5387 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5388 }
5389
5390 // Drops F's value because we can get it by inverting/negating TVal.
5391 FalseVal = TrueVal;
5392
5393 SDValue ARMcc;
5394 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5395 EVT VT = TrueVal.getValueType();
5396 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5397 }
5398 }
5399
5400 if (isUnsupportedFloatingType(LHS.getValueType())) {
5401 DAG.getTargetLoweringInfo().softenSetCCOperands(
5402 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5403
5404 // If softenSetCCOperands only returned one value, we should compare it to
5405 // zero.
5406 if (!RHS.getNode()) {
5407 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5408 CC = ISD::SETNE;
5409 }
5410 }
5411
5412 if (LHS.getValueType() == MVT::i32) {
5413 // Try to generate VSEL on ARMv8.
5414 // The VSEL instruction can't use all the usual ARM condition
5415 // codes: it only has two bits to select the condition code, so it's
5416 // constrained to use only GE, GT, VS and EQ.
5417 //
5418 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5419 // swap the operands of the previous compare instruction (effectively
5420 // inverting the compare condition, swapping 'less' and 'greater') and
5421 // sometimes need to swap the operands to the VSEL (which inverts the
5422 // condition in the sense of firing whenever the previous condition didn't)
5423 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5424 TrueVal.getValueType() == MVT::f32 ||
5425 TrueVal.getValueType() == MVT::f64)) {
5426 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5427 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5428 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5429 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5430 std::swap(TrueVal, FalseVal);
5431 }
5432 }
5433
5434 SDValue ARMcc;
5435 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5436 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5437 // Choose GE over PL, which vsel does now support
5438 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5439 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5440 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5441 }
5442
5443 ARMCC::CondCodes CondCode, CondCode2;
5444 FPCCToARMCC(CC, CondCode, CondCode2);
5445
5446 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5447 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5448 // must use VSEL (limited condition codes), due to not having conditional f16
5449 // moves.
5450 if (Subtarget->hasFPARMv8Base() &&
5451 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5452 (TrueVal.getValueType() == MVT::f16 ||
5453 TrueVal.getValueType() == MVT::f32 ||
5454 TrueVal.getValueType() == MVT::f64)) {
5455 bool swpCmpOps = false;
5456 bool swpVselOps = false;
5457 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5458
5459 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5460 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5461 if (swpCmpOps)
5462 std::swap(LHS, RHS);
5463 if (swpVselOps)
5464 std::swap(TrueVal, FalseVal);
5465 }
5466 }
5467
5468 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5469 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5470 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5471 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5472 if (CondCode2 != ARMCC::AL) {
5473 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5474 // FIXME: Needs another CMP because flag can have but one use.
5475 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5476 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5477 }
5478 return Result;
5479}
5480
5481/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5482/// to morph to an integer compare sequence.
5483static bool canChangeToInt(SDValue Op, bool &SeenZero,
5484 const ARMSubtarget *Subtarget) {
5485 SDNode *N = Op.getNode();
5486 if (!N->hasOneUse())
5487 // Otherwise it requires moving the value from fp to integer registers.
5488 return false;
5489 if (!N->getNumValues())
5490 return false;
5491 EVT VT = Op.getValueType();
5492 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5493 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5494 // vmrs are very slow, e.g. cortex-a8.
5495 return false;
5496
5497 if (isFloatingPointZero(Op)) {
5498 SeenZero = true;
5499 return true;
5500 }
5501 return ISD::isNormalLoad(N);
5502}
5503
5504static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5505 if (isFloatingPointZero(Op))
5506 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5507
5508 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5509 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5510 Ld->getPointerInfo(), Ld->getAlignment(),
5511 Ld->getMemOperand()->getFlags());
5512
5513 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5513)
;
5514}
5515
5516static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5517 SDValue &RetVal1, SDValue &RetVal2) {
5518 SDLoc dl(Op);
5519
5520 if (isFloatingPointZero(Op)) {
5521 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5522 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5523 return;
5524 }
5525
5526 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5527 SDValue Ptr = Ld->getBasePtr();
5528 RetVal1 =
5529 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5530 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5531
5532 EVT PtrType = Ptr.getValueType();
5533 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5534 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5535 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5536 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5537 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5538 Ld->getMemOperand()->getFlags());
5539 return;
5540 }
5541
5542 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5542)
;
5543}
5544
5545/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5546/// f32 and even f64 comparisons to integer ones.
5547SDValue
5548ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5549 SDValue Chain = Op.getOperand(0);
5550 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5551 SDValue LHS = Op.getOperand(2);
5552 SDValue RHS = Op.getOperand(3);
5553 SDValue Dest = Op.getOperand(4);
5554 SDLoc dl(Op);
5555
5556 bool LHSSeenZero = false;
5557 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5558 bool RHSSeenZero = false;
5559 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5560 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5561 // If unsafe fp math optimization is enabled and there are no other uses of
5562 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5563 // to an integer comparison.
5564 if (CC == ISD::SETOEQ)
5565 CC = ISD::SETEQ;
5566 else if (CC == ISD::SETUNE)
5567 CC = ISD::SETNE;
5568
5569 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5570 SDValue ARMcc;
5571 if (LHS.getValueType() == MVT::f32) {
5572 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5573 bitcastf32Toi32(LHS, DAG), Mask);
5574 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5575 bitcastf32Toi32(RHS, DAG), Mask);
5576 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5577 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5578 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5579 Chain, Dest, ARMcc, CCR, Cmp);
5580 }
5581
5582 SDValue LHS1, LHS2;
5583 SDValue RHS1, RHS2;
5584 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5585 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5586 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5587 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5588 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5589 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5590 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5591 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5592 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5593 }
5594
5595 return SDValue();
5596}
5597
5598SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5599 SDValue Chain = Op.getOperand(0);
5600 SDValue Cond = Op.getOperand(1);
5601 SDValue Dest = Op.getOperand(2);
5602 SDLoc dl(Op);
5603
5604 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5605 // instruction.
5606 unsigned Opc = Cond.getOpcode();
5607 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5608 !Subtarget->isThumb1Only();
5609 if (Cond.getResNo() == 1 &&
5610 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5611 Opc == ISD::USUBO || OptimizeMul)) {
5612 // Only lower legal XALUO ops.
5613 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5614 return SDValue();
5615
5616 // The actual operation with overflow check.
5617 SDValue Value, OverflowCmp;
5618 SDValue ARMcc;
5619 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5620
5621 // Reverse the condition code.
5622 ARMCC::CondCodes CondCode =
5623 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5624 CondCode = ARMCC::getOppositeCondition(CondCode);
5625 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5626 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5627
5628 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5629 OverflowCmp);
5630 }
5631
5632 return SDValue();
5633}
5634
5635SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5636 SDValue Chain = Op.getOperand(0);
5637 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5638 SDValue LHS = Op.getOperand(2);
5639 SDValue RHS = Op.getOperand(3);
5640 SDValue Dest = Op.getOperand(4);
5641 SDLoc dl(Op);
5642
5643 if (isUnsupportedFloatingType(LHS.getValueType())) {
5644 DAG.getTargetLoweringInfo().softenSetCCOperands(
5645 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5646
5647 // If softenSetCCOperands only returned one value, we should compare it to
5648 // zero.
5649 if (!RHS.getNode()) {
5650 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5651 CC = ISD::SETNE;
5652 }
5653 }
5654
5655 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5656 // instruction.
5657 unsigned Opc = LHS.getOpcode();
5658 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5659 !Subtarget->isThumb1Only();
5660 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5661 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5662 Opc == ISD::USUBO || OptimizeMul) &&
5663 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5664 // Only lower legal XALUO ops.
5665 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5666 return SDValue();
5667
5668 // The actual operation with overflow check.
5669 SDValue Value, OverflowCmp;
5670 SDValue ARMcc;
5671 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5672
5673 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5674 // Reverse the condition code.
5675 ARMCC::CondCodes CondCode =
5676 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5677 CondCode = ARMCC::getOppositeCondition(CondCode);
5678 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5679 }
5680 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5681
5682 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5683 OverflowCmp);
5684 }
5685
5686 if (LHS.getValueType() == MVT::i32) {
5687 SDValue ARMcc;
5688 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5689 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5690 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5691 Chain, Dest, ARMcc, CCR, Cmp);
5692 }
5693
5694 if (getTargetMachine().Options.UnsafeFPMath &&
5695 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5696 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5697 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5698 return Result;
5699 }
5700
5701 ARMCC::CondCodes CondCode, CondCode2;
5702 FPCCToARMCC(CC, CondCode, CondCode2);
5703
5704 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5705 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5706 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5707 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5708 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5709 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5710 if (CondCode2 != ARMCC::AL) {
5711 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5712 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5713 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5714 }
5715 return Res;
5716}
5717
5718SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5719 SDValue Chain = Op.getOperand(0);
5720 SDValue Table = Op.getOperand(1);
5721 SDValue Index = Op.getOperand(2);
5722 SDLoc dl(Op);
5723
5724 EVT PTy = getPointerTy(DAG.getDataLayout());
5725 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5726 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5727 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5728 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5729 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5730 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5731 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5732 // which does another jump to the destination. This also makes it easier
5733 // to translate it to TBB / TBH later (Thumb2 only).
5734 // FIXME: This might not work if the function is extremely large.
5735 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5736 Addr, Op.getOperand(2), JTI);
5737 }
5738 if (isPositionIndependent() || Subtarget->isROPI()) {
5739 Addr =
5740 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5741 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5742 Chain = Addr.getValue(1);
5743 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5744 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5745 } else {
5746 Addr =
5747 DAG.getLoad(PTy, dl, Chain, Addr,
5748 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5749 Chain = Addr.getValue(1);
5750 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5751 }
5752}
5753
5754static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5755 EVT VT = Op.getValueType();
5756 SDLoc dl(Op);
5757
5758 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5759 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5760 return Op;
5761 return DAG.UnrollVectorOp(Op.getNode());
5762 }
5763
5764 const bool HasFullFP16 =
5765 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5766
5767 EVT NewTy;
5768 const EVT OpTy = Op.getOperand(0).getValueType();
5769 if (OpTy == MVT::v4f32)
5770 NewTy = MVT::v4i32;
5771 else if (OpTy == MVT::v4f16 && HasFullFP16)
5772 NewTy = MVT::v4i16;
5773 else if (OpTy == MVT::v8f16 && HasFullFP16)
5774 NewTy = MVT::v8i16;
5775 else
5776 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5776)
;
5777
5778 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5779 return DAG.UnrollVectorOp(Op.getNode());
5780
5781 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5782 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5783}
5784
5785SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5786 EVT VT = Op.getValueType();
5787 if (VT.isVector())
5788 return LowerVectorFP_TO_INT(Op, DAG);
5789
5790 bool IsStrict = Op->isStrictFPOpcode();
5791 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5792
5793 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5794 RTLIB::Libcall LC;
5795 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5796 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5797 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5798 Op.getValueType());
5799 else
5800 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5801 Op.getValueType());
5802 SDLoc Loc(Op);
5803 MakeLibCallOptions CallOptions;
5804 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5805 SDValue Result;
5806 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5807 CallOptions, Loc, Chain);
5808 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5809 }
5810
5811 // FIXME: Remove this when we have strict fp instruction selection patterns
5812 if (IsStrict) {
5813 SDLoc Loc(Op);
5814 SDValue Result =
5815 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5816 : ISD::FP_TO_UINT,
5817 Loc, Op.getValueType(), SrcVal);
5818 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5819 }
5820
5821 return Op;
5822}
5823
5824static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5825 EVT VT = Op.getValueType();
5826 SDLoc dl(Op);
5827
5828 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5829 if (VT.getVectorElementType() == MVT::f32)
5830 return Op;
5831 return DAG.UnrollVectorOp(Op.getNode());
5832 }
5833
5834 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5836, __extension__ __PRETTY_FUNCTION__))
5835 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5836, __extension__ __PRETTY_FUNCTION__))
5836 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5836, __extension__ __PRETTY_FUNCTION__))
;
5837
5838 const bool HasFullFP16 =
5839 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5840
5841 EVT DestVecType;
5842 if (VT == MVT::v4f32)
5843 DestVecType = MVT::v4i32;
5844 else if (VT == MVT::v4f16 && HasFullFP16)
5845 DestVecType = MVT::v4i16;
5846 else if (VT == MVT::v8f16 && HasFullFP16)
5847 DestVecType = MVT::v8i16;
5848 else
5849 return DAG.UnrollVectorOp(Op.getNode());
5850
5851 unsigned CastOpc;
5852 unsigned Opc;
5853 switch (Op.getOpcode()) {
5854 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5854)
;
5855 case ISD::SINT_TO_FP:
5856 CastOpc = ISD::SIGN_EXTEND;
5857 Opc = ISD::SINT_TO_FP;
5858 break;
5859 case ISD::UINT_TO_FP:
5860 CastOpc = ISD::ZERO_EXTEND;
5861 Opc = ISD::UINT_TO_FP;
5862 break;
5863 }
5864
5865 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5866 return DAG.getNode(Opc, dl, VT, Op);
5867}
5868
5869SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5870 EVT VT = Op.getValueType();
5871 if (VT.isVector())
5872 return LowerVectorINT_TO_FP(Op, DAG);
5873 if (isUnsupportedFloatingType(VT)) {
5874 RTLIB::Libcall LC;
5875 if (Op.getOpcode() == ISD::SINT_TO_FP)
5876 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5877 Op.getValueType());
5878 else
5879 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5880 Op.getValueType());
5881 MakeLibCallOptions CallOptions;
5882 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5883 CallOptions, SDLoc(Op)).first;
5884 }
5885
5886 return Op;
5887}
5888
5889SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5890 // Implement fcopysign with a fabs and a conditional fneg.
5891 SDValue Tmp0 = Op.getOperand(0);
5892 SDValue Tmp1 = Op.getOperand(1);
5893 SDLoc dl(Op);
5894 EVT VT = Op.getValueType();
5895 EVT SrcVT = Tmp1.getValueType();
5896 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5897 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5898 bool UseNEON = !InGPR && Subtarget->hasNEON();
5899
5900 if (UseNEON) {
5901 // Use VBSL to copy the sign bit.
5902 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5903 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5904 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5905 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5906 if (VT == MVT::f64)
5907 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5908 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5909 DAG.getConstant(32, dl, MVT::i32));
5910 else /*if (VT == MVT::f32)*/
5911 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5912 if (SrcVT == MVT::f32) {
5913 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5914 if (VT == MVT::f64)
5915 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5916 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5917 DAG.getConstant(32, dl, MVT::i32));
5918 } else if (VT == MVT::f32)
5919 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5920 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5921 DAG.getConstant(32, dl, MVT::i32));
5922 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5923 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5924
5925 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5926 dl, MVT::i32);
5927 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5928 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5929 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5930
5931 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5932 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5933 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5934 if (VT == MVT::f32) {
5935 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5936 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5937 DAG.getConstant(0, dl, MVT::i32));
5938 } else {
5939 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5940 }