Bug Summary

File:build/source/llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2701, column 20
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM -I /build/source/llvm/lib/Target/ARM -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1668078801 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-11-10-135928-647445-1 -x c++ /build/source/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MachineValueType.h"
103#include "llvm/Support/MathExtras.h"
104#include "llvm/Support/raw_ostream.h"
105#include "llvm/Target/TargetMachine.h"
106#include "llvm/Target/TargetOptions.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <string>
114#include <tuple>
115#include <utility>
116#include <vector>
117
118using namespace llvm;
119using namespace llvm::PatternMatch;
120
121#define DEBUG_TYPE"arm-isel" "arm-isel"
122
123STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
124STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
125STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
126STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
127 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
128
129static cl::opt<bool>
130ARMInterworking("arm-interworking", cl::Hidden,
131 cl::desc("Enable / disable ARM interworking (for debugging only)"),
132 cl::init(true));
133
134static cl::opt<bool> EnableConstpoolPromotion(
135 "arm-promote-constant", cl::Hidden,
136 cl::desc("Enable / disable promotion of unnamed_addr constants into "
137 "constant pools"),
138 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
139static cl::opt<unsigned> ConstpoolPromotionMaxSize(
140 "arm-promote-constant-max-size", cl::Hidden,
141 cl::desc("Maximum size of constant to promote into a constant pool"),
142 cl::init(64));
143static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
144 "arm-promote-constant-max-total", cl::Hidden,
145 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
146 cl::init(128));
147
148cl::opt<unsigned>
149MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
150 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
151 cl::init(2));
152
153// The APCS parameter registers.
154static const MCPhysReg GPRArgRegs[] = {
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156};
157
158void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Neon does not support vector divide/remainder operations.
198 setOperationAction(ISD::SDIV, VT, Expand);
199 setOperationAction(ISD::UDIV, VT, Expand);
200 setOperationAction(ISD::FDIV, VT, Expand);
201 setOperationAction(ISD::SREM, VT, Expand);
202 setOperationAction(ISD::UREM, VT, Expand);
203 setOperationAction(ISD::FREM, VT, Expand);
204 setOperationAction(ISD::SDIVREM, VT, Expand);
205 setOperationAction(ISD::UDIVREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211 if (!VT.isFloatingPoint())
212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
213 setOperationAction(Opcode, VT, Legal);
214}
215
216void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
217 addRegisterClass(VT, &ARM::DPRRegClass);
218 addTypeForNEON(VT, MVT::f64);
219}
220
221void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
222 addRegisterClass(VT, &ARM::DPairRegClass);
223 addTypeForNEON(VT, MVT::v2f64);
224}
225
226void ARMTargetLowering::setAllExpand(MVT VT) {
227 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
228 setOperationAction(Opc, VT, Expand);
229
230 // We support these really simple operations even on types where all
231 // the actual arithmetic has to be broken down into simpler
232 // operations or turned into library calls.
233 setOperationAction(ISD::BITCAST, VT, Legal);
234 setOperationAction(ISD::LOAD, VT, Legal);
235 setOperationAction(ISD::STORE, VT, Legal);
236 setOperationAction(ISD::UNDEF, VT, Legal);
237}
238
239void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
240 LegalizeAction Action) {
241 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
244}
245
246void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
247 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
248
249 for (auto VT : IntTypes) {
250 addRegisterClass(VT, &ARM::MQPRRegClass);
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
255 setOperationAction(ISD::SHL, VT, Custom);
256 setOperationAction(ISD::SRA, VT, Custom);
257 setOperationAction(ISD::SRL, VT, Custom);
258 setOperationAction(ISD::SMIN, VT, Legal);
259 setOperationAction(ISD::SMAX, VT, Legal);
260 setOperationAction(ISD::UMIN, VT, Legal);
261 setOperationAction(ISD::UMAX, VT, Legal);
262 setOperationAction(ISD::ABS, VT, Legal);
263 setOperationAction(ISD::SETCC, VT, Custom);
264 setOperationAction(ISD::MLOAD, VT, Custom);
265 setOperationAction(ISD::MSTORE, VT, Legal);
266 setOperationAction(ISD::CTLZ, VT, Legal);
267 setOperationAction(ISD::CTTZ, VT, Custom);
268 setOperationAction(ISD::BITREVERSE, VT, Legal);
269 setOperationAction(ISD::BSWAP, VT, Legal);
270 setOperationAction(ISD::SADDSAT, VT, Legal);
271 setOperationAction(ISD::UADDSAT, VT, Legal);
272 setOperationAction(ISD::SSUBSAT, VT, Legal);
273 setOperationAction(ISD::USUBSAT, VT, Legal);
274 setOperationAction(ISD::ABDS, VT, Legal);
275 setOperationAction(ISD::ABDU, VT, Legal);
276 setOperationAction(ISD::AVGFLOORS, VT, Legal);
277 setOperationAction(ISD::AVGFLOORU, VT, Legal);
278 setOperationAction(ISD::AVGCEILS, VT, Legal);
279 setOperationAction(ISD::AVGCEILU, VT, Legal);
280
281 // No native support for these.
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
285 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::UDIVREM, VT, Expand);
287 setOperationAction(ISD::SDIVREM, VT, Expand);
288 setOperationAction(ISD::CTPOP, VT, Expand);
289 setOperationAction(ISD::SELECT, VT, Expand);
290 setOperationAction(ISD::SELECT_CC, VT, Expand);
291
292 // Vector reductions
293 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
299 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
302
303 if (!HasMVEFP) {
304 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
305 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
307 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
308 } else {
309 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
310 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
311 }
312
313 // Pre and Post inc are supported on loads and stores
314 for (unsigned im = (unsigned)ISD::PRE_INC;
315 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
316 setIndexedLoadAction(im, VT, Legal);
317 setIndexedStoreAction(im, VT, Legal);
318 setIndexedMaskedLoadAction(im, VT, Legal);
319 setIndexedMaskedStoreAction(im, VT, Legal);
320 }
321 }
322
323 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
324 for (auto VT : FloatTypes) {
325 addRegisterClass(VT, &ARM::MQPRRegClass);
326 if (!HasMVEFP)
327 setAllExpand(VT);
328
329 // These are legal or custom whether we have MVE.fp or not
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
336 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
337 setOperationAction(ISD::SETCC, VT, Custom);
338 setOperationAction(ISD::MLOAD, VT, Custom);
339 setOperationAction(ISD::MSTORE, VT, Legal);
340 setOperationAction(ISD::SELECT, VT, Expand);
341 setOperationAction(ISD::SELECT_CC, VT, Expand);
342
343 // Pre and Post inc are supported on loads and stores
344 for (unsigned im = (unsigned)ISD::PRE_INC;
345 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
346 setIndexedLoadAction(im, VT, Legal);
347 setIndexedStoreAction(im, VT, Legal);
348 setIndexedMaskedLoadAction(im, VT, Legal);
349 setIndexedMaskedStoreAction(im, VT, Legal);
350 }
351
352 if (HasMVEFP) {
353 setOperationAction(ISD::FMINNUM, VT, Legal);
354 setOperationAction(ISD::FMAXNUM, VT, Legal);
355 setOperationAction(ISD::FROUND, VT, Legal);
356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
357 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
360
361 // No native support for these.
362 setOperationAction(ISD::FDIV, VT, Expand);
363 setOperationAction(ISD::FREM, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FSIN, VT, Expand);
366 setOperationAction(ISD::FCOS, VT, Expand);
367 setOperationAction(ISD::FPOW, VT, Expand);
368 setOperationAction(ISD::FLOG, VT, Expand);
369 setOperationAction(ISD::FLOG2, VT, Expand);
370 setOperationAction(ISD::FLOG10, VT, Expand);
371 setOperationAction(ISD::FEXP, VT, Expand);
372 setOperationAction(ISD::FEXP2, VT, Expand);
373 setOperationAction(ISD::FNEARBYINT, VT, Expand);
374 }
375 }
376
377 // Custom Expand smaller than legal vector reductions to prevent false zero
378 // items being added.
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
387
388 // We 'support' these types up to bitcast/load/store level, regardless of
389 // MVE integer-only / float support. Only doing FP data processing on the FP
390 // vector types is inhibited at integer-only level.
391 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
392 for (auto VT : LongTypes) {
393 addRegisterClass(VT, &ARM::MQPRRegClass);
394 setAllExpand(VT);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
398 setOperationAction(ISD::VSELECT, VT, Legal);
399 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
400 }
401 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
402
403 // We can do bitwise operations on v2i64 vectors
404 setOperationAction(ISD::AND, MVT::v2i64, Legal);
405 setOperationAction(ISD::OR, MVT::v2i64, Legal);
406 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
407
408 // It is legal to extload from v4i8 to v4i16 or v4i32.
409 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
410 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
411 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
412
413 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
418 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
419
420 // Some truncating stores are legal too.
421 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
422 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
423 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
424
425 // Pre and Post inc on these are legal, given the correct extends
426 for (unsigned im = (unsigned)ISD::PRE_INC;
427 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
428 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
429 setIndexedLoadAction(im, VT, Legal);
430 setIndexedStoreAction(im, VT, Legal);
431 setIndexedMaskedLoadAction(im, VT, Legal);
432 setIndexedMaskedStoreAction(im, VT, Legal);
433 }
434 }
435
436 // Predicate types
437 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
438 for (auto VT : pTypes) {
439 addRegisterClass(VT, &ARM::VCCRRegClass);
440 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
442 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
443 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
444 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
446 setOperationAction(ISD::SETCC, VT, Custom);
447 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
448 setOperationAction(ISD::LOAD, VT, Custom);
449 setOperationAction(ISD::STORE, VT, Custom);
450 setOperationAction(ISD::TRUNCATE, VT, Custom);
451 setOperationAction(ISD::VSELECT, VT, Expand);
452 setOperationAction(ISD::SELECT, VT, Expand);
453 setOperationAction(ISD::SELECT_CC, VT, Expand);
454
455 if (!HasMVEFP) {
456 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
457 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
458 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
459 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
460 }
461 }
462 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
463 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
464 setOperationAction(ISD::AND, MVT::v2i1, Expand);
465 setOperationAction(ISD::OR, MVT::v2i1, Expand);
466 setOperationAction(ISD::XOR, MVT::v2i1, Expand);
467 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand);
468 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand);
469 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand);
470 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand);
471
472 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
473 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
474 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
475 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
476 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
477 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
478 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
479 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
480}
481
482ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
483 const ARMSubtarget &STI)
484 : TargetLowering(TM), Subtarget(&STI) {
485 RegInfo = Subtarget->getRegisterInfo();
486 Itins = Subtarget->getInstrItineraryData();
487
488 setBooleanContents(ZeroOrOneBooleanContent);
489 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
490
491 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
492 !Subtarget->isTargetWatchOS() && !Subtarget->isTargetDriverKit()) {
493 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
494 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
495 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
496 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
497 : CallingConv::ARM_AAPCS);
498 }
499
500 if (Subtarget->isTargetMachO()) {
501 // Uses VFP for Thumb libfuncs if available.
502 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
503 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
504 static const struct {
505 const RTLIB::Libcall Op;
506 const char * const Name;
507 const ISD::CondCode Cond;
508 } LibraryCalls[] = {
509 // Single-precision floating-point arithmetic.
510 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
511 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
512 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
513 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
514
515 // Double-precision floating-point arithmetic.
516 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
517 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
518 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
519 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
520
521 // Single-precision comparisons.
522 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
523 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
524 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
525 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
526 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
527 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
528 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
529
530 // Double-precision comparisons.
531 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
532 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
533 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
534 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
535 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
536 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
537 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
538
539 // Floating-point to integer conversions.
540 // i64 conversions are done via library routines even when generating VFP
541 // instructions, so use the same ones.
542 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
543 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
544 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
545 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
546
547 // Conversions between floating types.
548 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
549 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
550
551 // Integer to floating-point conversions.
552 // i64 conversions are done via library routines even when generating VFP
553 // instructions, so use the same ones.
554 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
555 // e.g., __floatunsidf vs. __floatunssidfvfp.
556 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
557 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
558 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
559 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
560 };
561
562 for (const auto &LC : LibraryCalls) {
563 setLibcallName(LC.Op, LC.Name);
564 if (LC.Cond != ISD::SETCC_INVALID)
565 setCmpLibcallCC(LC.Op, LC.Cond);
566 }
567 }
568 }
569
570 // These libcalls are not available in 32-bit.
571 setLibcallName(RTLIB::SHL_I128, nullptr);
572 setLibcallName(RTLIB::SRL_I128, nullptr);
573 setLibcallName(RTLIB::SRA_I128, nullptr);
574 setLibcallName(RTLIB::MUL_I128, nullptr);
575 setLibcallName(RTLIB::MULO_I64, nullptr);
576 setLibcallName(RTLIB::MULO_I128, nullptr);
577
578 // RTLIB
579 if (Subtarget->isAAPCS_ABI() &&
580 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
581 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
582 static const struct {
583 const RTLIB::Libcall Op;
584 const char * const Name;
585 const CallingConv::ID CC;
586 const ISD::CondCode Cond;
587 } LibraryCalls[] = {
588 // Double-precision floating-point arithmetic helper functions
589 // RTABI chapter 4.1.2, Table 2
590 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
594
595 // Double-precision floating-point comparison helper functions
596 // RTABI chapter 4.1.2, Table 3
597 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
598 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
599 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
600 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
601 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
602 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
603 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
604
605 // Single-precision floating-point arithmetic helper functions
606 // RTABI chapter 4.1.2, Table 4
607 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611
612 // Single-precision floating-point comparison helper functions
613 // RTABI chapter 4.1.2, Table 5
614 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
615 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
616 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
617 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
618 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
619 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
620 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
621
622 // Floating-point to integer conversions.
623 // RTABI chapter 4.1.2, Table 6
624 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632
633 // Conversions between floating types.
634 // RTABI chapter 4.1.2, Table 7
635 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638
639 // Integer to floating-point conversions.
640 // RTABI chapter 4.1.2, Table 8
641 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
642 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
643 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
644 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
645 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
646 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
647 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649
650 // Long long helper functions
651 // RTABI chapter 4.2, Table 9
652 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
653 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
654 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
655 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
656
657 // Integer division functions
658 // RTABI chapter 4.3.1
659 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
660 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
662 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
663 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
664 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
665 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
666 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
667 };
668
669 for (const auto &LC : LibraryCalls) {
670 setLibcallName(LC.Op, LC.Name);
671 setLibcallCallingConv(LC.Op, LC.CC);
672 if (LC.Cond != ISD::SETCC_INVALID)
673 setCmpLibcallCC(LC.Op, LC.Cond);
674 }
675
676 // EABI dependent RTLIB
677 if (TM.Options.EABIVersion == EABI::EABI4 ||
678 TM.Options.EABIVersion == EABI::EABI5) {
679 static const struct {
680 const RTLIB::Libcall Op;
681 const char *const Name;
682 const CallingConv::ID CC;
683 const ISD::CondCode Cond;
684 } MemOpsLibraryCalls[] = {
685 // Memory operations
686 // RTABI chapter 4.3.4
687 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
688 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
689 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
690 };
691
692 for (const auto &LC : MemOpsLibraryCalls) {
693 setLibcallName(LC.Op, LC.Name);
694 setLibcallCallingConv(LC.Op, LC.CC);
695 if (LC.Cond != ISD::SETCC_INVALID)
696 setCmpLibcallCC(LC.Op, LC.Cond);
697 }
698 }
699 }
700
701 if (Subtarget->isTargetWindows()) {
702 static const struct {
703 const RTLIB::Libcall Op;
704 const char * const Name;
705 const CallingConv::ID CC;
706 } LibraryCalls[] = {
707 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
708 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
709 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
710 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
711 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
712 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
713 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
714 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
715 };
716
717 for (const auto &LC : LibraryCalls) {
718 setLibcallName(LC.Op, LC.Name);
719 setLibcallCallingConv(LC.Op, LC.CC);
720 }
721 }
722
723 // Use divmod compiler-rt calls for iOS 5.0 and later.
724 if (Subtarget->isTargetMachO() &&
725 !(Subtarget->isTargetIOS() &&
726 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
727 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
728 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
729 }
730
731 // The half <-> float conversion functions are always soft-float on
732 // non-watchos platforms, but are needed for some targets which use a
733 // hard-float calling convention by default.
734 if (!Subtarget->isTargetWatchABI()) {
735 if (Subtarget->isAAPCS_ABI()) {
736 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
737 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
738 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
739 } else {
740 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
741 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
742 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
743 }
744 }
745
746 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
747 // a __gnu_ prefix (which is the default).
748 if (Subtarget->isTargetAEABI()) {
749 static const struct {
750 const RTLIB::Libcall Op;
751 const char * const Name;
752 const CallingConv::ID CC;
753 } LibraryCalls[] = {
754 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
755 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
756 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
757 };
758
759 for (const auto &LC : LibraryCalls) {
760 setLibcallName(LC.Op, LC.Name);
761 setLibcallCallingConv(LC.Op, LC.CC);
762 }
763 }
764
765 if (Subtarget->isThumb1Only())
766 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
767 else
768 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
769
770 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
771 Subtarget->hasFPRegs()) {
772 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
773 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
774
775 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
776 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
777 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
778 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
779
780 if (!Subtarget->hasVFP2Base())
781 setAllExpand(MVT::f32);
782 if (!Subtarget->hasFP64())
783 setAllExpand(MVT::f64);
784 }
785
786 if (Subtarget->hasFullFP16()) {
787 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
788 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
789 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
790
791 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
792 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
793 }
794
795 if (Subtarget->hasBF16()) {
796 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
797 setAllExpand(MVT::bf16);
798 if (!Subtarget->hasFullFP16())
799 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
800 }
801
802 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
803 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
804 setTruncStoreAction(VT, InnerVT, Expand);
805 addAllExtLoads(VT, InnerVT, Expand);
806 }
807
808 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
809 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
810
811 setOperationAction(ISD::BSWAP, VT, Expand);
812 }
813
814 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
815 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
816
817 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
818 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
819
820 if (Subtarget->hasMVEIntegerOps())
821 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
822
823 // Combine low-overhead loop intrinsics so that we can lower i1 types.
824 if (Subtarget->hasLOB()) {
825 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC});
826 }
827
828 if (Subtarget->hasNEON()) {
829 addDRTypeForNEON(MVT::v2f32);
830 addDRTypeForNEON(MVT::v8i8);
831 addDRTypeForNEON(MVT::v4i16);
832 addDRTypeForNEON(MVT::v2i32);
833 addDRTypeForNEON(MVT::v1i64);
834
835 addQRTypeForNEON(MVT::v4f32);
836 addQRTypeForNEON(MVT::v2f64);
837 addQRTypeForNEON(MVT::v16i8);
838 addQRTypeForNEON(MVT::v8i16);
839 addQRTypeForNEON(MVT::v4i32);
840 addQRTypeForNEON(MVT::v2i64);
841
842 if (Subtarget->hasFullFP16()) {
843 addQRTypeForNEON(MVT::v8f16);
844 addDRTypeForNEON(MVT::v4f16);
845 }
846
847 if (Subtarget->hasBF16()) {
848 addQRTypeForNEON(MVT::v8bf16);
849 addDRTypeForNEON(MVT::v4bf16);
850 }
851 }
852
853 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
854 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
855 // none of Neon, MVE or VFP supports any arithmetic operations on it.
856 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
857 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
858 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
859 // FIXME: Code duplication: FDIV and FREM are expanded always, see
860 // ARMTargetLowering::addTypeForNEON method for details.
861 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
862 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
863 // FIXME: Create unittest.
864 // In another words, find a way when "copysign" appears in DAG with vector
865 // operands.
866 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
867 // FIXME: Code duplication: SETCC has custom operation action, see
868 // ARMTargetLowering::addTypeForNEON method for details.
869 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
870 // FIXME: Create unittest for FNEG and for FABS.
871 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
872 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
873 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
874 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
875 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
876 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
877 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
878 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
879 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
880 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
881 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
882 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
883 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
884 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
885 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
886 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
887 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
888 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
889 }
890
891 if (Subtarget->hasNEON()) {
892 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
893 // supported for v4f32.
894 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
895 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
896 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
897 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
898 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
899 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
900 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
901 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
902 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
903 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
904 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
905 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
906 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
907 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
908
909 // Mark v2f32 intrinsics.
910 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
911 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
912 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
913 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
914 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
915 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
916 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
917 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
918 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
919 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
920 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
921 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
922 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
923 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
924
925 // Neon does not support some operations on v1i64 and v2i64 types.
926 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
927 // Custom handling for some quad-vector types to detect VMULL.
928 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
929 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
930 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
931 // Custom handling for some vector types to avoid expensive expansions
932 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
933 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
934 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
935 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
936 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
937 // a destination type that is wider than the source, and nor does
938 // it have a FP_TO_[SU]INT instruction with a narrower destination than
939 // source.
940 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
941 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
942 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
945 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
946 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
947 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
948
949 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
950 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
951
952 // NEON does not have single instruction CTPOP for vectors with element
953 // types wider than 8-bits. However, custom lowering can leverage the
954 // v8i8/v16i8 vcnt instruction.
955 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
956 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
957 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
958 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
959 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
960 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
961
962 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
963 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
964
965 // NEON does not have single instruction CTTZ for vectors.
966 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
967 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
968 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
969 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
970
971 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
972 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
973 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
974 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
975
976 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
977 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
978 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
979 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
980
981 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
982 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
983 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
984 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
985
986 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
987 setOperationAction(ISD::MULHS, VT, Expand);
988 setOperationAction(ISD::MULHU, VT, Expand);
989 }
990
991 // NEON only has FMA instructions as of VFP4.
992 if (!Subtarget->hasVFP4Base()) {
993 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
994 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
995 }
996
997 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
998 ISD::FP_TO_UINT, ISD::FDIV, ISD::LOAD});
999
1000 // It is legal to extload from v4i8 to v4i16 or v4i32.
1001 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
1002 MVT::v2i32}) {
1003 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1004 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
1005 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
1006 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
1007 }
1008 }
1009 }
1010
1011 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1012 setTargetDAGCombine(
1013 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR,
1014 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
1015 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND,
1016 ISD::ANY_EXTEND, ISD::INTRINSIC_WO_CHAIN, ISD::INTRINSIC_W_CHAIN,
1017 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST});
1018 }
1019 if (Subtarget->hasMVEIntegerOps()) {
1020 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX,
1021 ISD::FP_EXTEND, ISD::SELECT, ISD::SELECT_CC,
1022 ISD::SETCC});
1023 }
1024 if (Subtarget->hasMVEFloatOps()) {
1025 setTargetDAGCombine(ISD::FADD);
1026 }
1027
1028 if (!Subtarget->hasFP64()) {
1029 // When targeting a floating-point unit with only single-precision
1030 // operations, f64 is legal for the few double-precision instructions which
1031 // are present However, no double-precision operations other than moves,
1032 // loads and stores are provided by the hardware.
1033 setOperationAction(ISD::FADD, MVT::f64, Expand);
1034 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1035 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1036 setOperationAction(ISD::FMA, MVT::f64, Expand);
1037 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1038 setOperationAction(ISD::FREM, MVT::f64, Expand);
1039 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1040 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1041 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1042 setOperationAction(ISD::FABS, MVT::f64, Expand);
1043 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1044 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1045 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1046 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1047 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1048 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1049 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1050 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1051 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1052 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1053 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1054 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1055 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1056 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1058 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1060 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1062 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1063 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1064 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1065 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1066 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1067 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1068 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1069 }
1070
1071 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1072 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1073 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1074 if (Subtarget->hasFullFP16()) {
1075 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1076 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1077 }
1078 }
1079
1080 if (!Subtarget->hasFP16()) {
1081 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1082 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1083 }
1084
1085 computeRegisterProperties(Subtarget->getRegisterInfo());
1086
1087 // ARM does not have floating-point extending loads.
1088 for (MVT VT : MVT::fp_valuetypes()) {
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1090 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1091 }
1092
1093 // ... or truncating stores
1094 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1095 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1096 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1097
1098 // ARM does not have i1 sign extending load.
1099 for (MVT VT : MVT::integer_valuetypes())
1100 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1101
1102 // ARM supports all 4 flavors of integer indexed load / store.
1103 if (!Subtarget->isThumb1Only()) {
1104 for (unsigned im = (unsigned)ISD::PRE_INC;
1105 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1106 setIndexedLoadAction(im, MVT::i1, Legal);
1107 setIndexedLoadAction(im, MVT::i8, Legal);
1108 setIndexedLoadAction(im, MVT::i16, Legal);
1109 setIndexedLoadAction(im, MVT::i32, Legal);
1110 setIndexedStoreAction(im, MVT::i1, Legal);
1111 setIndexedStoreAction(im, MVT::i8, Legal);
1112 setIndexedStoreAction(im, MVT::i16, Legal);
1113 setIndexedStoreAction(im, MVT::i32, Legal);
1114 }
1115 } else {
1116 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1117 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1118 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1119 }
1120
1121 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1122 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1123 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1124 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1125
1126 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1127 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1128 if (Subtarget->hasDSP()) {
1129 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1130 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1131 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1132 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1133 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1134 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1135 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1136 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1137 }
1138 if (Subtarget->hasBaseDSP()) {
1139 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1140 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1141 }
1142
1143 // i64 operation support.
1144 setOperationAction(ISD::MUL, MVT::i64, Expand);
1145 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1146 if (Subtarget->isThumb1Only()) {
1147 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1148 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1149 }
1150 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1151 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1152 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1153
1154 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1155 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1156 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1157 setOperationAction(ISD::SRL, MVT::i64, Custom);
1158 setOperationAction(ISD::SRA, MVT::i64, Custom);
1159 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1160 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1161 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1162 setOperationAction(ISD::STORE, MVT::i64, Custom);
1163
1164 // MVE lowers 64 bit shifts to lsll and lsrl
1165 // assuming that ISD::SRL and SRA of i64 are already marked custom
1166 if (Subtarget->hasMVEIntegerOps())
1167 setOperationAction(ISD::SHL, MVT::i64, Custom);
1168
1169 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1170 if (Subtarget->isThumb1Only()) {
1171 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1172 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1173 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1174 }
1175
1176 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1177 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1178
1179 // ARM does not have ROTL.
1180 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1181 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1182 setOperationAction(ISD::ROTL, VT, Expand);
1183 setOperationAction(ISD::ROTR, VT, Expand);
1184 }
1185 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1186 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1187 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1188 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1189 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1190 }
1191
1192 // @llvm.readcyclecounter requires the Performance Monitors extension.
1193 // Default to the 0 expansion on unsupported platforms.
1194 // FIXME: Technically there are older ARM CPUs that have
1195 // implementation-specific ways of obtaining this information.
1196 if (Subtarget->hasPerfMon())
1197 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1198
1199 // Only ARMv6 has BSWAP.
1200 if (!Subtarget->hasV6Ops())
1201 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1202
1203 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1204 : Subtarget->hasDivideInARMMode();
1205 if (!hasDivide) {
1206 // These are expanded into libcalls if the cpu doesn't have HW divider.
1207 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1208 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1209 }
1210
1211 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1212 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1213 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1214
1215 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1216 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1217 }
1218
1219 setOperationAction(ISD::SREM, MVT::i32, Expand);
1220 setOperationAction(ISD::UREM, MVT::i32, Expand);
1221
1222 // Register based DivRem for AEABI (RTABI 4.2)
1223 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1224 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1225 Subtarget->isTargetWindows()) {
1226 setOperationAction(ISD::SREM, MVT::i64, Custom);
1227 setOperationAction(ISD::UREM, MVT::i64, Custom);
1228 HasStandaloneRem = false;
1229
1230 if (Subtarget->isTargetWindows()) {
1231 const struct {
1232 const RTLIB::Libcall Op;
1233 const char * const Name;
1234 const CallingConv::ID CC;
1235 } LibraryCalls[] = {
1236 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1237 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1238 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1239 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1240
1241 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1242 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1243 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1244 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1245 };
1246
1247 for (const auto &LC : LibraryCalls) {
1248 setLibcallName(LC.Op, LC.Name);
1249 setLibcallCallingConv(LC.Op, LC.CC);
1250 }
1251 } else {
1252 const struct {
1253 const RTLIB::Libcall Op;
1254 const char * const Name;
1255 const CallingConv::ID CC;
1256 } LibraryCalls[] = {
1257 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1258 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1259 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1260 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1261
1262 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1263 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1264 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1265 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1266 };
1267
1268 for (const auto &LC : LibraryCalls) {
1269 setLibcallName(LC.Op, LC.Name);
1270 setLibcallCallingConv(LC.Op, LC.CC);
1271 }
1272 }
1273
1274 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1275 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1276 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1277 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1278 } else {
1279 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1280 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1281 }
1282
1283 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1284 // MSVCRT doesn't have powi; fall back to pow
1285 setLibcallName(RTLIB::POWI_F32, nullptr);
1286 setLibcallName(RTLIB::POWI_F64, nullptr);
1287 }
1288
1289 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1290 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1291 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1292 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1293
1294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1295 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1296
1297 // Use the default implementation.
1298 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1299 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1300 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1301 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1302 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1303 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1304
1305 if (Subtarget->isTargetWindows())
1306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1307 else
1308 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1309
1310 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1311 // the default expansion.
1312 InsertFencesForAtomic = false;
1313 if (Subtarget->hasAnyDataBarrier() &&
1314 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1315 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1316 // to ldrex/strex loops already.
1317 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1318 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1320
1321 // On v8, we have particularly efficient implementations of atomic fences
1322 // if they can be combined with nearby atomic loads and stores.
1323 if (!Subtarget->hasAcquireRelease() ||
1324 getTargetMachine().getOptLevel() == 0) {
1325 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1326 InsertFencesForAtomic = true;
1327 }
1328 } else {
1329 // If there's anything we can use as a barrier, go through custom lowering
1330 // for ATOMIC_FENCE.
1331 // If target has DMB in thumb, Fences can be inserted.
1332 if (Subtarget->hasDataBarrier())
1333 InsertFencesForAtomic = true;
1334
1335 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1336 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1337
1338 // Set them all for expansion, which will force libcalls.
1339 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1340 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1347 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1348 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1349 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1350 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1351 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1352 // Unordered/Monotonic case.
1353 if (!InsertFencesForAtomic) {
1354 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1355 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1356 }
1357 }
1358
1359 // Compute supported atomic widths.
1360 if (Subtarget->isTargetLinux() ||
1361 (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
1362 // For targets where __sync_* routines are reliably available, we use them
1363 // if necessary.
1364 //
1365 // ARM Linux always supports 64-bit atomics through kernel-assisted atomic
1366 // routines (kernel 3.1 or later). FIXME: Not with compiler-rt?
1367 //
1368 // ARMv6 targets have native instructions in ARM mode. For Thumb mode,
1369 // such targets should provide __sync_* routines, which use the ARM mode
1370 // instructions. (ARMv6 doesn't have dmb, but it has an equivalent
1371 // encoding; see ARMISD::MEMBARRIER_MCR.)
1372 setMaxAtomicSizeInBitsSupported(64);
1373 } else if ((Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) ||
1374 Subtarget->hasForced32BitAtomics()) {
1375 // Cortex-M (besides Cortex-M0) have 32-bit atomics.
1376 setMaxAtomicSizeInBitsSupported(32);
1377 } else {
1378 // We can't assume anything about other targets; just use libatomic
1379 // routines.
1380 setMaxAtomicSizeInBitsSupported(0);
1381 }
1382
1383 setMaxDivRemBitWidthSupported(64);
1384
1385 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1386
1387 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1388 if (!Subtarget->hasV6Ops()) {
1389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1391 }
1392 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1393
1394 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1395 !Subtarget->isThumb1Only()) {
1396 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1397 // iff target supports vfp2.
1398 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1399 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1400 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1401 }
1402
1403 // We want to custom lower some of our intrinsics.
1404 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1405 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1406 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1407 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1408 if (Subtarget->useSjLjEH())
1409 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1410
1411 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1412 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1413 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1414 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1415 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1416 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1417 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1418 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1419 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1420 if (Subtarget->hasFullFP16()) {
1421 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1422 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1423 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1424 }
1425
1426 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1427
1428 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1429 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1430 if (Subtarget->hasFullFP16())
1431 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1432 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1433 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1434 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1435
1436 // We don't support sin/cos/fmod/copysign/pow
1437 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1438 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1439 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1440 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1441 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1442 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1443 setOperationAction(ISD::FREM, MVT::f64, Expand);
1444 setOperationAction(ISD::FREM, MVT::f32, Expand);
1445 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1446 !Subtarget->isThumb1Only()) {
1447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1449 }
1450 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1451 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1452
1453 if (!Subtarget->hasVFP4Base()) {
1454 setOperationAction(ISD::FMA, MVT::f64, Expand);
1455 setOperationAction(ISD::FMA, MVT::f32, Expand);
1456 }
1457
1458 // Various VFP goodness
1459 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1460 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1461 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1462 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1463 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1464 }
1465
1466 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1467 if (!Subtarget->hasFP16()) {
1468 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1469 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1470 }
1471
1472 // Strict floating-point comparisons need custom lowering.
1473 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1474 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1475 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1476 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1477 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1478 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1479 }
1480
1481 // Use __sincos_stret if available.
1482 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1483 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1484 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1485 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1486 }
1487
1488 // FP-ARMv8 implements a lot of rounding-like FP operations.
1489 if (Subtarget->hasFPARMv8Base()) {
1490 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1491 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1492 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1493 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1494 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1495 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1496 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1497 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1498 if (Subtarget->hasNEON()) {
1499 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1500 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1501 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1502 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1503 }
1504
1505 if (Subtarget->hasFP64()) {
1506 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1507 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1508 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1509 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1510 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1511 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1512 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1513 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1514 }
1515 }
1516
1517 // FP16 often need to be promoted to call lib functions
1518 if (Subtarget->hasFullFP16()) {
1519 setOperationAction(ISD::FREM, MVT::f16, Promote);
1520 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1521 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1522 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1523 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1524 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1525 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1526 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1527 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1528 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1529 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1530 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1531
1532 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1533 }
1534
1535 if (Subtarget->hasNEON()) {
1536 // vmin and vmax aren't available in a scalar form, so we can use
1537 // a NEON instruction with an undef lane instead. This has a performance
1538 // penalty on some cores, so we don't do this unless we have been
1539 // asked to by the core tuning model.
1540 if (Subtarget->useNEONForSinglePrecisionFP()) {
1541 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1542 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1543 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1544 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1545 }
1546 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1547 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1548 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1549 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1550
1551 if (Subtarget->hasFullFP16()) {
1552 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1553 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1554 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1555 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1556
1557 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1558 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1559 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1560 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1561 }
1562 }
1563
1564 // We have target-specific dag combine patterns for the following nodes:
1565 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1566 setTargetDAGCombine(
1567 {ISD::ADD, ISD::SUB, ISD::MUL, ISD::AND, ISD::OR, ISD::XOR});
1568
1569 if (Subtarget->hasMVEIntegerOps())
1570 setTargetDAGCombine(ISD::VSELECT);
1571
1572 if (Subtarget->hasV6Ops())
1573 setTargetDAGCombine(ISD::SRL);
1574 if (Subtarget->isThumb1Only())
1575 setTargetDAGCombine(ISD::SHL);
1576 // Attempt to lower smin/smax to ssat/usat
1577 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
1578 Subtarget->isThumb2()) {
1579 setTargetDAGCombine({ISD::SMIN, ISD::SMAX});
1580 }
1581
1582 setStackPointerRegisterToSaveRestore(ARM::SP);
1583
1584 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1585 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1586 setSchedulingPreference(Sched::RegPressure);
1587 else
1588 setSchedulingPreference(Sched::Hybrid);
1589
1590 //// temporary - rewrite interface to use type
1591 MaxStoresPerMemset = 8;
1592 MaxStoresPerMemsetOptSize = 4;
1593 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1594 MaxStoresPerMemcpyOptSize = 2;
1595 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1596 MaxStoresPerMemmoveOptSize = 2;
1597
1598 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1599 // are at least 4 bytes aligned.
1600 setMinStackArgumentAlignment(Align(4));
1601
1602 // Prefer likely predicted branches to selects on out-of-order cores.
1603 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1604
1605 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1606
1607 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1608
1609 if (Subtarget->isThumb() || Subtarget->isThumb2())
1610 setTargetDAGCombine(ISD::ABS);
1611}
1612
1613bool ARMTargetLowering::useSoftFloat() const {
1614 return Subtarget->useSoftFloat();
1615}
1616
1617// FIXME: It might make sense to define the representative register class as the
1618// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1619// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1620// SPR's representative would be DPR_VFP2. This should work well if register
1621// pressure tracking were modified such that a register use would increment the
1622// pressure of the register class's representative and all of it's super
1623// classes' representatives transitively. We have not implemented this because
1624// of the difficulty prior to coalescing of modeling operand register classes
1625// due to the common occurrence of cross class copies and subregister insertions
1626// and extractions.
1627std::pair<const TargetRegisterClass *, uint8_t>
1628ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1629 MVT VT) const {
1630 const TargetRegisterClass *RRC = nullptr;
1631 uint8_t Cost = 1;
1632 switch (VT.SimpleTy) {
1633 default:
1634 return TargetLowering::findRepresentativeClass(TRI, VT);
1635 // Use DPR as representative register class for all floating point
1636 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1637 // the cost is 1 for both f32 and f64.
1638 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1639 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1640 RRC = &ARM::DPRRegClass;
1641 // When NEON is used for SP, only half of the register file is available
1642 // because operations that define both SP and DP results will be constrained
1643 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1644 // coalescing by double-counting the SP regs. See the FIXME above.
1645 if (Subtarget->useNEONForSinglePrecisionFP())
1646 Cost = 2;
1647 break;
1648 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1649 case MVT::v4f32: case MVT::v2f64:
1650 RRC = &ARM::DPRRegClass;
1651 Cost = 2;
1652 break;
1653 case MVT::v4i64:
1654 RRC = &ARM::DPRRegClass;
1655 Cost = 4;
1656 break;
1657 case MVT::v8i64:
1658 RRC = &ARM::DPRRegClass;
1659 Cost = 8;
1660 break;
1661 }
1662 return std::make_pair(RRC, Cost);
1663}
1664
1665const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1666#define MAKE_CASE(V) \
1667 case V: \
1668 return #V;
1669 switch ((ARMISD::NodeType)Opcode) {
1670 case ARMISD::FIRST_NUMBER:
1671 break;
1672 MAKE_CASE(ARMISD::Wrapper)
1673 MAKE_CASE(ARMISD::WrapperPIC)
1674 MAKE_CASE(ARMISD::WrapperJT)
1675 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1676 MAKE_CASE(ARMISD::CALL)
1677 MAKE_CASE(ARMISD::CALL_PRED)
1678 MAKE_CASE(ARMISD::CALL_NOLINK)
1679 MAKE_CASE(ARMISD::tSECALL)
1680 MAKE_CASE(ARMISD::t2CALL_BTI)
1681 MAKE_CASE(ARMISD::BRCOND)
1682 MAKE_CASE(ARMISD::BR_JT)
1683 MAKE_CASE(ARMISD::BR2_JT)
1684 MAKE_CASE(ARMISD::RET_FLAG)
1685 MAKE_CASE(ARMISD::SERET_FLAG)
1686 MAKE_CASE(ARMISD::INTRET_FLAG)
1687 MAKE_CASE(ARMISD::PIC_ADD)
1688 MAKE_CASE(ARMISD::CMP)
1689 MAKE_CASE(ARMISD::CMN)
1690 MAKE_CASE(ARMISD::CMPZ)
1691 MAKE_CASE(ARMISD::CMPFP)
1692 MAKE_CASE(ARMISD::CMPFPE)
1693 MAKE_CASE(ARMISD::CMPFPw0)
1694 MAKE_CASE(ARMISD::CMPFPEw0)
1695 MAKE_CASE(ARMISD::BCC_i64)
1696 MAKE_CASE(ARMISD::FMSTAT)
1697 MAKE_CASE(ARMISD::CMOV)
1698 MAKE_CASE(ARMISD::SUBS)
1699 MAKE_CASE(ARMISD::SSAT)
1700 MAKE_CASE(ARMISD::USAT)
1701 MAKE_CASE(ARMISD::ASRL)
1702 MAKE_CASE(ARMISD::LSRL)
1703 MAKE_CASE(ARMISD::LSLL)
1704 MAKE_CASE(ARMISD::SRL_FLAG)
1705 MAKE_CASE(ARMISD::SRA_FLAG)
1706 MAKE_CASE(ARMISD::RRX)
1707 MAKE_CASE(ARMISD::ADDC)
1708 MAKE_CASE(ARMISD::ADDE)
1709 MAKE_CASE(ARMISD::SUBC)
1710 MAKE_CASE(ARMISD::SUBE)
1711 MAKE_CASE(ARMISD::LSLS)
1712 MAKE_CASE(ARMISD::VMOVRRD)
1713 MAKE_CASE(ARMISD::VMOVDRR)
1714 MAKE_CASE(ARMISD::VMOVhr)
1715 MAKE_CASE(ARMISD::VMOVrh)
1716 MAKE_CASE(ARMISD::VMOVSR)
1717 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1718 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1719 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1720 MAKE_CASE(ARMISD::TC_RETURN)
1721 MAKE_CASE(ARMISD::THREAD_POINTER)
1722 MAKE_CASE(ARMISD::DYN_ALLOC)
1723 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1724 MAKE_CASE(ARMISD::PRELOAD)
1725 MAKE_CASE(ARMISD::LDRD)
1726 MAKE_CASE(ARMISD::STRD)
1727 MAKE_CASE(ARMISD::WIN__CHKSTK)
1728 MAKE_CASE(ARMISD::WIN__DBZCHK)
1729 MAKE_CASE(ARMISD::PREDICATE_CAST)
1730 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1731 MAKE_CASE(ARMISD::MVESEXT)
1732 MAKE_CASE(ARMISD::MVEZEXT)
1733 MAKE_CASE(ARMISD::MVETRUNC)
1734 MAKE_CASE(ARMISD::VCMP)
1735 MAKE_CASE(ARMISD::VCMPZ)
1736 MAKE_CASE(ARMISD::VTST)
1737 MAKE_CASE(ARMISD::VSHLs)
1738 MAKE_CASE(ARMISD::VSHLu)
1739 MAKE_CASE(ARMISD::VSHLIMM)
1740 MAKE_CASE(ARMISD::VSHRsIMM)
1741 MAKE_CASE(ARMISD::VSHRuIMM)
1742 MAKE_CASE(ARMISD::VRSHRsIMM)
1743 MAKE_CASE(ARMISD::VRSHRuIMM)
1744 MAKE_CASE(ARMISD::VRSHRNIMM)
1745 MAKE_CASE(ARMISD::VQSHLsIMM)
1746 MAKE_CASE(ARMISD::VQSHLuIMM)
1747 MAKE_CASE(ARMISD::VQSHLsuIMM)
1748 MAKE_CASE(ARMISD::VQSHRNsIMM)
1749 MAKE_CASE(ARMISD::VQSHRNuIMM)
1750 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1751 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1752 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1753 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1754 MAKE_CASE(ARMISD::VSLIIMM)
1755 MAKE_CASE(ARMISD::VSRIIMM)
1756 MAKE_CASE(ARMISD::VGETLANEu)
1757 MAKE_CASE(ARMISD::VGETLANEs)
1758 MAKE_CASE(ARMISD::VMOVIMM)
1759 MAKE_CASE(ARMISD::VMVNIMM)
1760 MAKE_CASE(ARMISD::VMOVFPIMM)
1761 MAKE_CASE(ARMISD::VDUP)
1762 MAKE_CASE(ARMISD::VDUPLANE)
1763 MAKE_CASE(ARMISD::VEXT)
1764 MAKE_CASE(ARMISD::VREV64)
1765 MAKE_CASE(ARMISD::VREV32)
1766 MAKE_CASE(ARMISD::VREV16)
1767 MAKE_CASE(ARMISD::VZIP)
1768 MAKE_CASE(ARMISD::VUZP)
1769 MAKE_CASE(ARMISD::VTRN)
1770 MAKE_CASE(ARMISD::VTBL1)
1771 MAKE_CASE(ARMISD::VTBL2)
1772 MAKE_CASE(ARMISD::VMOVN)
1773 MAKE_CASE(ARMISD::VQMOVNs)
1774 MAKE_CASE(ARMISD::VQMOVNu)
1775 MAKE_CASE(ARMISD::VCVTN)
1776 MAKE_CASE(ARMISD::VCVTL)
1777 MAKE_CASE(ARMISD::VIDUP)
1778 MAKE_CASE(ARMISD::VMULLs)
1779 MAKE_CASE(ARMISD::VMULLu)
1780 MAKE_CASE(ARMISD::VQDMULH)
1781 MAKE_CASE(ARMISD::VADDVs)
1782 MAKE_CASE(ARMISD::VADDVu)
1783 MAKE_CASE(ARMISD::VADDVps)
1784 MAKE_CASE(ARMISD::VADDVpu)
1785 MAKE_CASE(ARMISD::VADDLVs)
1786 MAKE_CASE(ARMISD::VADDLVu)
1787 MAKE_CASE(ARMISD::VADDLVAs)
1788 MAKE_CASE(ARMISD::VADDLVAu)
1789 MAKE_CASE(ARMISD::VADDLVps)
1790 MAKE_CASE(ARMISD::VADDLVpu)
1791 MAKE_CASE(ARMISD::VADDLVAps)
1792 MAKE_CASE(ARMISD::VADDLVApu)
1793 MAKE_CASE(ARMISD::VMLAVs)
1794 MAKE_CASE(ARMISD::VMLAVu)
1795 MAKE_CASE(ARMISD::VMLAVps)
1796 MAKE_CASE(ARMISD::VMLAVpu)
1797 MAKE_CASE(ARMISD::VMLALVs)
1798 MAKE_CASE(ARMISD::VMLALVu)
1799 MAKE_CASE(ARMISD::VMLALVps)
1800 MAKE_CASE(ARMISD::VMLALVpu)
1801 MAKE_CASE(ARMISD::VMLALVAs)
1802 MAKE_CASE(ARMISD::VMLALVAu)
1803 MAKE_CASE(ARMISD::VMLALVAps)
1804 MAKE_CASE(ARMISD::VMLALVApu)
1805 MAKE_CASE(ARMISD::VMINVu)
1806 MAKE_CASE(ARMISD::VMINVs)
1807 MAKE_CASE(ARMISD::VMAXVu)
1808 MAKE_CASE(ARMISD::VMAXVs)
1809 MAKE_CASE(ARMISD::UMAAL)
1810 MAKE_CASE(ARMISD::UMLAL)
1811 MAKE_CASE(ARMISD::SMLAL)
1812 MAKE_CASE(ARMISD::SMLALBB)
1813 MAKE_CASE(ARMISD::SMLALBT)
1814 MAKE_CASE(ARMISD::SMLALTB)
1815 MAKE_CASE(ARMISD::SMLALTT)
1816 MAKE_CASE(ARMISD::SMULWB)
1817 MAKE_CASE(ARMISD::SMULWT)
1818 MAKE_CASE(ARMISD::SMLALD)
1819 MAKE_CASE(ARMISD::SMLALDX)
1820 MAKE_CASE(ARMISD::SMLSLD)
1821 MAKE_CASE(ARMISD::SMLSLDX)
1822 MAKE_CASE(ARMISD::SMMLAR)
1823 MAKE_CASE(ARMISD::SMMLSR)
1824 MAKE_CASE(ARMISD::QADD16b)
1825 MAKE_CASE(ARMISD::QSUB16b)
1826 MAKE_CASE(ARMISD::QADD8b)
1827 MAKE_CASE(ARMISD::QSUB8b)
1828 MAKE_CASE(ARMISD::UQADD16b)
1829 MAKE_CASE(ARMISD::UQSUB16b)
1830 MAKE_CASE(ARMISD::UQADD8b)
1831 MAKE_CASE(ARMISD::UQSUB8b)
1832 MAKE_CASE(ARMISD::BUILD_VECTOR)
1833 MAKE_CASE(ARMISD::BFI)
1834 MAKE_CASE(ARMISD::VORRIMM)
1835 MAKE_CASE(ARMISD::VBICIMM)
1836 MAKE_CASE(ARMISD::VBSP)
1837 MAKE_CASE(ARMISD::MEMCPY)
1838 MAKE_CASE(ARMISD::VLD1DUP)
1839 MAKE_CASE(ARMISD::VLD2DUP)
1840 MAKE_CASE(ARMISD::VLD3DUP)
1841 MAKE_CASE(ARMISD::VLD4DUP)
1842 MAKE_CASE(ARMISD::VLD1_UPD)
1843 MAKE_CASE(ARMISD::VLD2_UPD)
1844 MAKE_CASE(ARMISD::VLD3_UPD)
1845 MAKE_CASE(ARMISD::VLD4_UPD)
1846 MAKE_CASE(ARMISD::VLD1x2_UPD)
1847 MAKE_CASE(ARMISD::VLD1x3_UPD)
1848 MAKE_CASE(ARMISD::VLD1x4_UPD)
1849 MAKE_CASE(ARMISD::VLD2LN_UPD)
1850 MAKE_CASE(ARMISD::VLD3LN_UPD)
1851 MAKE_CASE(ARMISD::VLD4LN_UPD)
1852 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1853 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1854 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1855 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1856 MAKE_CASE(ARMISD::VST1_UPD)
1857 MAKE_CASE(ARMISD::VST2_UPD)
1858 MAKE_CASE(ARMISD::VST3_UPD)
1859 MAKE_CASE(ARMISD::VST4_UPD)
1860 MAKE_CASE(ARMISD::VST1x2_UPD)
1861 MAKE_CASE(ARMISD::VST1x3_UPD)
1862 MAKE_CASE(ARMISD::VST1x4_UPD)
1863 MAKE_CASE(ARMISD::VST2LN_UPD)
1864 MAKE_CASE(ARMISD::VST3LN_UPD)
1865 MAKE_CASE(ARMISD::VST4LN_UPD)
1866 MAKE_CASE(ARMISD::WLS)
1867 MAKE_CASE(ARMISD::WLSSETUP)
1868 MAKE_CASE(ARMISD::LE)
1869 MAKE_CASE(ARMISD::LOOP_DEC)
1870 MAKE_CASE(ARMISD::CSINV)
1871 MAKE_CASE(ARMISD::CSNEG)
1872 MAKE_CASE(ARMISD::CSINC)
1873 MAKE_CASE(ARMISD::MEMCPYLOOP)
1874 MAKE_CASE(ARMISD::MEMSETLOOP)
1875#undef MAKE_CASE
1876 }
1877 return nullptr;
1878}
1879
1880EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1881 EVT VT) const {
1882 if (!VT.isVector())
1883 return getPointerTy(DL);
1884
1885 // MVE has a predicate register.
1886 if ((Subtarget->hasMVEIntegerOps() &&
1887 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
1888 VT == MVT::v16i8)) ||
1889 (Subtarget->hasMVEFloatOps() &&
1890 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
1891 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1892 return VT.changeVectorElementTypeToInteger();
1893}
1894
1895/// getRegClassFor - Return the register class that should be used for the
1896/// specified value type.
1897const TargetRegisterClass *
1898ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1899 (void)isDivergent;
1900 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1901 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1902 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1903 // MVE Q registers.
1904 if (Subtarget->hasNEON()) {
1905 if (VT == MVT::v4i64)
1906 return &ARM::QQPRRegClass;
1907 if (VT == MVT::v8i64)
1908 return &ARM::QQQQPRRegClass;
1909 }
1910 if (Subtarget->hasMVEIntegerOps()) {
1911 if (VT == MVT::v4i64)
1912 return &ARM::MQQPRRegClass;
1913 if (VT == MVT::v8i64)
1914 return &ARM::MQQQQPRRegClass;
1915 }
1916 return TargetLowering::getRegClassFor(VT);
1917}
1918
1919// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1920// source/dest is aligned and the copy size is large enough. We therefore want
1921// to align such objects passed to memory intrinsics.
1922bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1923 Align &PrefAlign) const {
1924 if (!isa<MemIntrinsic>(CI))
1925 return false;
1926 MinSize = 8;
1927 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1928 // cycle faster than 4-byte aligned LDM.
1929 PrefAlign =
1930 (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));
1931 return true;
1932}
1933
1934// Create a fast isel object.
1935FastISel *
1936ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1937 const TargetLibraryInfo *libInfo) const {
1938 return ARM::createFastISel(funcInfo, libInfo);
1939}
1940
1941Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1942 unsigned NumVals = N->getNumValues();
1943 if (!NumVals)
1944 return Sched::RegPressure;
1945
1946 for (unsigned i = 0; i != NumVals; ++i) {
1947 EVT VT = N->getValueType(i);
1948 if (VT == MVT::Glue || VT == MVT::Other)
1949 continue;
1950 if (VT.isFloatingPoint() || VT.isVector())
1951 return Sched::ILP;
1952 }
1953
1954 if (!N->isMachineOpcode())
1955 return Sched::RegPressure;
1956
1957 // Load are scheduled for latency even if there instruction itinerary
1958 // is not available.
1959 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1960 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1961
1962 if (MCID.getNumDefs() == 0)
1963 return Sched::RegPressure;
1964 if (!Itins->isEmpty() &&
1965 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1966 return Sched::ILP;
1967
1968 return Sched::RegPressure;
1969}
1970
1971//===----------------------------------------------------------------------===//
1972// Lowering Code
1973//===----------------------------------------------------------------------===//
1974
1975static bool isSRL16(const SDValue &Op) {
1976 if (Op.getOpcode() != ISD::SRL)
1977 return false;
1978 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1979 return Const->getZExtValue() == 16;
1980 return false;
1981}
1982
1983static bool isSRA16(const SDValue &Op) {
1984 if (Op.getOpcode() != ISD::SRA)
1985 return false;
1986 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1987 return Const->getZExtValue() == 16;
1988 return false;
1989}
1990
1991static bool isSHL16(const SDValue &Op) {
1992 if (Op.getOpcode() != ISD::SHL)
1993 return false;
1994 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1995 return Const->getZExtValue() == 16;
1996 return false;
1997}
1998
1999// Check for a signed 16-bit value. We special case SRA because it makes it
2000// more simple when also looking for SRAs that aren't sign extending a
2001// smaller value. Without the check, we'd need to take extra care with
2002// checking order for some operations.
2003static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
2004 if (isSRA16(Op))
2005 return isSHL16(Op.getOperand(0));
2006 return DAG.ComputeNumSignBits(Op) == 17;
2007}
2008
2009/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
2010static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2011 switch (CC) {
2012 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2012)
;
2013 case ISD::SETNE: return ARMCC::NE;
2014 case ISD::SETEQ: return ARMCC::EQ;
2015 case ISD::SETGT: return ARMCC::GT;
2016 case ISD::SETGE: return ARMCC::GE;
2017 case ISD::SETLT: return ARMCC::LT;
2018 case ISD::SETLE: return ARMCC::LE;
2019 case ISD::SETUGT: return ARMCC::HI;
2020 case ISD::SETUGE: return ARMCC::HS;
2021 case ISD::SETULT: return ARMCC::LO;
2022 case ISD::SETULE: return ARMCC::LS;
2023 }
2024}
2025
2026/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
2027static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2028 ARMCC::CondCodes &CondCode2) {
2029 CondCode2 = ARMCC::AL;
2030 switch (CC) {
2031 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2031)
;
2032 case ISD::SETEQ:
2033 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2034 case ISD::SETGT:
2035 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2036 case ISD::SETGE:
2037 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2038 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2039 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2040 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2041 case ISD::SETO: CondCode = ARMCC::VC; break;
2042 case ISD::SETUO: CondCode = ARMCC::VS; break;
2043 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2044 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2045 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2046 case ISD::SETLT:
2047 case ISD::SETULT: CondCode = ARMCC::LT; break;
2048 case ISD::SETLE:
2049 case ISD::SETULE: CondCode = ARMCC::LE; break;
2050 case ISD::SETNE:
2051 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2052 }
2053}
2054
2055//===----------------------------------------------------------------------===//
2056// Calling Convention Implementation
2057//===----------------------------------------------------------------------===//
2058
2059/// getEffectiveCallingConv - Get the effective calling convention, taking into
2060/// account presence of floating point hardware and calling convention
2061/// limitations, such as support for variadic functions.
2062CallingConv::ID
2063ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2064 bool isVarArg) const {
2065 switch (CC) {
2066 default:
2067 report_fatal_error("Unsupported calling convention");
2068 case CallingConv::ARM_AAPCS:
2069 case CallingConv::ARM_APCS:
2070 case CallingConv::GHC:
2071 case CallingConv::CFGuard_Check:
2072 return CC;
2073 case CallingConv::PreserveMost:
2074 return CallingConv::PreserveMost;
2075 case CallingConv::ARM_AAPCS_VFP:
2076 case CallingConv::Swift:
2077 case CallingConv::SwiftTail:
2078 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2079 case CallingConv::C:
2080 case CallingConv::Tail:
2081 if (!Subtarget->isAAPCS_ABI())
2082 return CallingConv::ARM_APCS;
2083 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2084 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2085 !isVarArg)
2086 return CallingConv::ARM_AAPCS_VFP;
2087 else
2088 return CallingConv::ARM_AAPCS;
2089 case CallingConv::Fast:
2090 case CallingConv::CXX_FAST_TLS:
2091 if (!Subtarget->isAAPCS_ABI()) {
2092 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2093 return CallingConv::Fast;
2094 return CallingConv::ARM_APCS;
2095 } else if (Subtarget->hasVFP2Base() &&
2096 !Subtarget->isThumb1Only() && !isVarArg)
2097 return CallingConv::ARM_AAPCS_VFP;
2098 else
2099 return CallingConv::ARM_AAPCS;
2100 }
2101}
2102
2103CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2104 bool isVarArg) const {
2105 return CCAssignFnForNode(CC, false, isVarArg);
2106}
2107
2108CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2109 bool isVarArg) const {
2110 return CCAssignFnForNode(CC, true, isVarArg);
2111}
2112
2113/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2114/// CallingConvention.
2115CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2116 bool Return,
2117 bool isVarArg) const {
2118 switch (getEffectiveCallingConv(CC, isVarArg)) {
2119 default:
2120 report_fatal_error("Unsupported calling convention");
2121 case CallingConv::ARM_APCS:
2122 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2123 case CallingConv::ARM_AAPCS:
2124 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2125 case CallingConv::ARM_AAPCS_VFP:
2126 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2127 case CallingConv::Fast:
2128 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2129 case CallingConv::GHC:
2130 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2131 case CallingConv::PreserveMost:
2132 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2133 case CallingConv::CFGuard_Check:
2134 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2135 }
2136}
2137
2138SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2139 MVT LocVT, MVT ValVT, SDValue Val) const {
2140 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2141 Val);
2142 if (Subtarget->hasFullFP16()) {
2143 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2144 } else {
2145 Val = DAG.getNode(ISD::TRUNCATE, dl,
2146 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2147 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2148 }
2149 return Val;
2150}
2151
2152SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2153 MVT LocVT, MVT ValVT,
2154 SDValue Val) const {
2155 if (Subtarget->hasFullFP16()) {
2156 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2157 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2158 } else {
2159 Val = DAG.getNode(ISD::BITCAST, dl,
2160 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2161 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2162 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2163 }
2164 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2165}
2166
2167/// LowerCallResult - Lower the result values of a call into the
2168/// appropriate copies out of appropriate physical registers.
2169SDValue ARMTargetLowering::LowerCallResult(
2170 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2171 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2172 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2173 SDValue ThisVal) const {
2174 // Assign locations to each value returned by this call.
2175 SmallVector<CCValAssign, 16> RVLocs;
2176 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2177 *DAG.getContext());
2178 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2179
2180 // Copy all of the result registers out of their specified physreg.
2181 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2182 CCValAssign VA = RVLocs[i];
2183
2184 // Pass 'this' value directly from the argument to return value, to avoid
2185 // reg unit interference
2186 if (i == 0 && isThisReturn) {
2187 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2188, __extension__
__PRETTY_FUNCTION__))
2188 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2188, __extension__
__PRETTY_FUNCTION__))
;
2189 InVals.push_back(ThisVal);
2190 continue;
2191 }
2192
2193 SDValue Val;
2194 if (VA.needsCustom() &&
2195 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2196 // Handle f64 or half of a v2f64.
2197 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2198 InFlag);
2199 Chain = Lo.getValue(1);
2200 InFlag = Lo.getValue(2);
2201 VA = RVLocs[++i]; // skip ahead to next loc
2202 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2203 InFlag);
2204 Chain = Hi.getValue(1);
2205 InFlag = Hi.getValue(2);
2206 if (!Subtarget->isLittle())
2207 std::swap (Lo, Hi);
2208 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2209
2210 if (VA.getLocVT() == MVT::v2f64) {
2211 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2212 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2213 DAG.getConstant(0, dl, MVT::i32));
2214
2215 VA = RVLocs[++i]; // skip ahead to next loc
2216 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2217 Chain = Lo.getValue(1);
2218 InFlag = Lo.getValue(2);
2219 VA = RVLocs[++i]; // skip ahead to next loc
2220 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2221 Chain = Hi.getValue(1);
2222 InFlag = Hi.getValue(2);
2223 if (!Subtarget->isLittle())
2224 std::swap (Lo, Hi);
2225 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2226 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2227 DAG.getConstant(1, dl, MVT::i32));
2228 }
2229 } else {
2230 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2231 InFlag);
2232 Chain = Val.getValue(1);
2233 InFlag = Val.getValue(2);
2234 }
2235
2236 switch (VA.getLocInfo()) {
2237 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2237)
;
2238 case CCValAssign::Full: break;
2239 case CCValAssign::BCvt:
2240 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2241 break;
2242 }
2243
2244 // f16 arguments have their size extended to 4 bytes and passed as if they
2245 // had been copied to the LSBs of a 32-bit register.
2246 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2247 if (VA.needsCustom() &&
2248 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2249 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2250
2251 InVals.push_back(Val);
2252 }
2253
2254 return Chain;
2255}
2256
2257std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2258 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2259 bool IsTailCall, int SPDiff) const {
2260 SDValue DstAddr;
2261 MachinePointerInfo DstInfo;
2262 int32_t Offset = VA.getLocMemOffset();
2263 MachineFunction &MF = DAG.getMachineFunction();
2264
2265 if (IsTailCall) {
2266 Offset += SPDiff;
2267 auto PtrVT = getPointerTy(DAG.getDataLayout());
2268 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2269 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2270 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2271 DstInfo =
2272 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2273 } else {
2274 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2275 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2276 StackPtr, PtrOff);
2277 DstInfo =
2278 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2279 }
2280
2281 return std::make_pair(DstAddr, DstInfo);
2282}
2283
2284void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2285 SDValue Chain, SDValue &Arg,
2286 RegsToPassVector &RegsToPass,
2287 CCValAssign &VA, CCValAssign &NextVA,
2288 SDValue &StackPtr,
2289 SmallVectorImpl<SDValue> &MemOpChains,
2290 bool IsTailCall,
2291 int SPDiff) const {
2292 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2293 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2294 unsigned id = Subtarget->isLittle() ? 0 : 1;
2295 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2296
2297 if (NextVA.isRegLoc())
2298 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2299 else {
2300 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2300, __extension__ __PRETTY_FUNCTION__))
;
2301 if (!StackPtr.getNode())
2302 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2303 getPointerTy(DAG.getDataLayout()));
2304
2305 SDValue DstAddr;
2306 MachinePointerInfo DstInfo;
2307 std::tie(DstAddr, DstInfo) =
2308 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2309 MemOpChains.push_back(
2310 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2311 }
2312}
2313
2314static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2315 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2316 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2317}
2318
2319/// LowerCall - Lowering a call into a callseq_start <-
2320/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2321/// nodes.
2322SDValue
2323ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2324 SmallVectorImpl<SDValue> &InVals) const {
2325 SelectionDAG &DAG = CLI.DAG;
2326 SDLoc &dl = CLI.DL;
2327 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2328 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2329 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2330 SDValue Chain = CLI.Chain;
2331 SDValue Callee = CLI.Callee;
2332 bool &isTailCall = CLI.IsTailCall;
2333 CallingConv::ID CallConv = CLI.CallConv;
2334 bool doesNotRet = CLI.DoesNotReturn;
2335 bool isVarArg = CLI.IsVarArg;
2336
2337 MachineFunction &MF = DAG.getMachineFunction();
2338 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2339 MachineFunction::CallSiteInfo CSInfo;
2340 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2341 bool isThisReturn = false;
2342 bool isCmseNSCall = false;
2343 bool isSibCall = false;
2344 bool PreferIndirect = false;
2345 bool GuardWithBTI = false;
2346
2347 // Lower 'returns_twice' calls to a pseudo-instruction.
2348 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
2
Assuming field 'CB' is null
2349 !Subtarget->noBTIAtReturnTwice())
2350 GuardWithBTI = AFI->branchTargetEnforcement();
2351
2352 // Determine whether this is a non-secure function call.
2353 if (CLI.CB
2.1
Field 'CB' is null
&& CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
3
Taking false branch
2354 isCmseNSCall = true;
2355
2356 // Disable tail calls if they're not supported.
2357 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
2358 isTailCall = false;
2359
2360 // For both the non-secure calls and the returns from a CMSE entry function,
2361 // the function needs to do some extra work afte r the call, or before the
2362 // return, respectively, thus it cannot end with atail call
2363 if (isCmseNSCall
4.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
5
Assuming the condition is false
6
Taking false branch
2364 isTailCall = false;
2365
2366 if (isa<GlobalAddressSDNode>(Callee)) {
7
Assuming 'Callee' is not a 'GlobalAddressSDNode'
8
Taking false branch
2367 // If we're optimizing for minimum size and the function is called three or
2368 // more times in this block, we can improve codesize by calling indirectly
2369 // as BLXr has a 16-bit encoding.
2370 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2371 if (CLI.CB) {
2372 auto *BB = CLI.CB->getParent();
2373 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2374 count_if(GV->users(), [&BB](const User *U) {
2375 return isa<Instruction>(U) &&
2376 cast<Instruction>(U)->getParent() == BB;
2377 }) > 2;
2378 }
2379 }
2380 if (isTailCall) {
9
Assuming 'isTailCall' is false
2381 // Check if it's really possible to do a tail call.
2382 isTailCall = IsEligibleForTailCallOptimization(
2383 Callee, CallConv, isVarArg, isStructRet,
2384 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2385 PreferIndirect);
2386
2387 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2388 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2389 isSibCall = true;
2390
2391 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2392 // detected sibcalls.
2393 if (isTailCall)
2394 ++NumTailCalls;
2395 }
2396
2397 if (!isTailCall
9.1
'isTailCall' is false
&& CLI.CB
9.2
Field 'CB' is null
&& CLI.CB->isMustTailCall())
2398 report_fatal_error("failed to perform tail call elimination on a call "
2399 "site marked musttail");
2400 // Analyze operands of the call, assigning locations to each operand.
2401 SmallVector<CCValAssign, 16> ArgLocs;
2402 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2403 *DAG.getContext());
2404 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2405
2406 // Get a count of how many bytes are to be pushed on the stack.
2407 unsigned NumBytes = CCInfo.getNextStackOffset();
2408
2409 // SPDiff is the byte offset of the call's argument area from the callee's.
2410 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2411 // by this amount for a tail call. In a sibling call it must be 0 because the
2412 // caller will deallocate the entire stack and the callee still expects its
2413 // arguments to begin at SP+0. Completely unused for non-tail calls.
2414 int SPDiff = 0;
2415
2416 if (isTailCall && !isSibCall) {
10
Assuming 'isTailCall' is false
2417 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2418 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2419
2420 // Since callee will pop argument stack as a tail call, we must keep the
2421 // popped size 16-byte aligned.
2422 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2423 NumBytes = alignTo(NumBytes, StackAlign);
2424
2425 // SPDiff will be negative if this tail call requires more space than we
2426 // would automatically have in our incoming argument space. Positive if we
2427 // can actually shrink the stack.
2428 SPDiff = NumReusableBytes - NumBytes;
2429
2430 // If this call requires more stack than we have available from
2431 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2432 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2433 AFI->setArgRegsSaveSize(-SPDiff);
2434 }
2435
2436 if (isSibCall
10.1
'isSibCall' is false
) {
11
Taking false branch
2437 // For sibling tail calls, memory operands are available in our caller's stack.
2438 NumBytes = 0;
2439 } else {
2440 // Adjust the stack pointer for the new arguments...
2441 // These operations are automatically eliminated by the prolog/epilog pass
2442 Chain = DAG.getCALLSEQ_START(Chain, isTailCall
11.1
'isTailCall' is false
? 0 : NumBytes, 0, dl);
12
'?' condition is false
2443 }
2444
2445 SDValue StackPtr =
2446 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2447
2448 RegsToPassVector RegsToPass;
2449 SmallVector<SDValue, 8> MemOpChains;
2450
2451 // During a tail call, stores to the argument area must happen after all of
2452 // the function's incoming arguments have been loaded because they may alias.
2453 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2454 // there's no point in doing so repeatedly so this tracks whether that's
2455 // happened yet.
2456 bool AfterFormalArgLoads = false;
2457
2458 // Walk the register/memloc assignments, inserting copies/loads. In the case
2459 // of tail call optimization, arguments are handled later.
2460 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
14
Loop condition is false. Execution continues on line 2614
2461 i != e;
13
Assuming 'i' is equal to 'e'
2462 ++i, ++realArgIdx) {
2463 CCValAssign &VA = ArgLocs[i];
2464 SDValue Arg = OutVals[realArgIdx];
2465 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2466 bool isByVal = Flags.isByVal();
2467
2468 // Promote the value if needed.
2469 switch (VA.getLocInfo()) {
2470 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2470)
;
2471 case CCValAssign::Full: break;
2472 case CCValAssign::SExt:
2473 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2474 break;
2475 case CCValAssign::ZExt:
2476 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2477 break;
2478 case CCValAssign::AExt:
2479 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2480 break;
2481 case CCValAssign::BCvt:
2482 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2483 break;
2484 }
2485
2486 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2487 Chain = DAG.getStackArgumentTokenFactor(Chain);
2488 AfterFormalArgLoads = true;
2489 }
2490
2491 // f16 arguments have their size extended to 4 bytes and passed as if they
2492 // had been copied to the LSBs of a 32-bit register.
2493 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2494 if (VA.needsCustom() &&
2495 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2496 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2497 } else {
2498 // f16 arguments could have been extended prior to argument lowering.
2499 // Mask them arguments if this is a CMSE nonsecure call.
2500 auto ArgVT = Outs[realArgIdx].ArgVT;
2501 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2502 auto LocBits = VA.getLocVT().getSizeInBits();
2503 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2504 SDValue Mask =
2505 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2506 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2507 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2508 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2509 }
2510 }
2511
2512 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2513 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2514 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2515 DAG.getConstant(0, dl, MVT::i32));
2516 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2517 DAG.getConstant(1, dl, MVT::i32));
2518
2519 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2520 StackPtr, MemOpChains, isTailCall, SPDiff);
2521
2522 VA = ArgLocs[++i]; // skip ahead to next loc
2523 if (VA.isRegLoc()) {
2524 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2525 StackPtr, MemOpChains, isTailCall, SPDiff);
2526 } else {
2527 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2527, __extension__ __PRETTY_FUNCTION__))
;
2528 SDValue DstAddr;
2529 MachinePointerInfo DstInfo;
2530 std::tie(DstAddr, DstInfo) =
2531 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2532 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2533 }
2534 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2535 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2536 StackPtr, MemOpChains, isTailCall, SPDiff);
2537 } else if (VA.isRegLoc()) {
2538 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2539 Outs[0].VT == MVT::i32) {
2540 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
2541 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
;
2542 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2543, __extension__
__PRETTY_FUNCTION__))
2543 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2543, __extension__
__PRETTY_FUNCTION__))
;
2544 isThisReturn = true;
2545 }
2546 const TargetOptions &Options = DAG.getTarget().Options;
2547 if (Options.EmitCallSiteInfo)
2548 CSInfo.emplace_back(VA.getLocReg(), i);
2549 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2550 } else if (isByVal) {
2551 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2551, __extension__ __PRETTY_FUNCTION__))
;
2552 unsigned offset = 0;
2553
2554 // True if this byval aggregate will be split between registers
2555 // and memory.
2556 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2557 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2558
2559 if (CurByValIdx < ByValArgsCount) {
2560
2561 unsigned RegBegin, RegEnd;
2562 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2563
2564 EVT PtrVT =
2565 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2566 unsigned int i, j;
2567 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2568 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2569 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2570 SDValue Load =
2571 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2572 DAG.InferPtrAlign(AddArg));
2573 MemOpChains.push_back(Load.getValue(1));
2574 RegsToPass.push_back(std::make_pair(j, Load));
2575 }
2576
2577 // If parameter size outsides register area, "offset" value
2578 // helps us to calculate stack slot for remained part properly.
2579 offset = RegEnd - RegBegin;
2580
2581 CCInfo.nextInRegsParam();
2582 }
2583
2584 if (Flags.getByValSize() > 4*offset) {
2585 auto PtrVT = getPointerTy(DAG.getDataLayout());
2586 SDValue Dst;
2587 MachinePointerInfo DstInfo;
2588 std::tie(Dst, DstInfo) =
2589 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2590 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2591 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2592 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2593 MVT::i32);
2594 SDValue AlignNode =
2595 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2596
2597 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2598 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2599 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2600 Ops));
2601 }
2602 } else {
2603 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2603, __extension__ __PRETTY_FUNCTION__))
;
2604 SDValue DstAddr;
2605 MachinePointerInfo DstInfo;
2606 std::tie(DstAddr, DstInfo) =
2607 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2608
2609 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2610 MemOpChains.push_back(Store);
2611 }
2612 }
2613
2614 if (!MemOpChains.empty())
15
Taking true branch
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2616
2617 // Build a sequence of copy-to-reg nodes chained together with token chain
2618 // and flag operands which copy the outgoing args into the appropriate regs.
2619 SDValue InFlag;
2620 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
16
Assuming 'i' is equal to 'e'
17
Loop condition is false. Execution continues on line 2629
2621 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2622 RegsToPass[i].second, InFlag);
2623 InFlag = Chain.getValue(1);
2624 }
2625
2626 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2627 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2628 // node so that legalize doesn't hack it.
2629 bool isDirect = false;
2630
2631 const TargetMachine &TM = getTargetMachine();
2632 const Module *Mod = MF.getFunction().getParent();
2633 const GlobalValue *GVal = nullptr;
18
'GVal' initialized to a null pointer value
2634 if (GlobalAddressSDNode *G
18.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
2635 GVal = G->getGlobal();
2636 bool isStub =
2637 !TM.shouldAssumeDSOLocal(*Mod, GVal) && Subtarget->isTargetMachO();
19
Assuming the condition is false
2638
2639 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
20
Assuming the condition is true
2640 bool isLocalARMFunc = false;
2641 auto PtrVt = getPointerTy(DAG.getDataLayout());
2642
2643 if (Subtarget->genLongCalls()) {
21
Assuming the condition is false
22
Taking false branch
2644 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2645, __extension__
__PRETTY_FUNCTION__))
2645 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2645, __extension__
__PRETTY_FUNCTION__))
;
2646 // Handle a global address or an external symbol. If it's not one of
2647 // those, the target's already in a register, so we don't need to do
2648 // anything extra.
2649 if (isa<GlobalAddressSDNode>(Callee)) {
2650 // When generating execute-only code we use movw movt pair.
2651 // Currently execute-only is only available for architectures that
2652 // support movw movt, so we are safe to assume that.
2653 if (Subtarget->genExecuteOnly()) {
2654 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2655, __extension__
__PRETTY_FUNCTION__))
2655 "long-calls with execute-only requires movt and movw!")(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2655, __extension__
__PRETTY_FUNCTION__))
;
2656 ++NumMovwMovt;
2657 Callee = DAG.getNode(ARMISD::Wrapper, dl, PtrVt,
2658 DAG.getTargetGlobalAddress(GVal, dl, PtrVt));
2659 } else {
2660 // Create a constant pool entry for the callee address
2661 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2662 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2663 GVal, ARMPCLabelIndex, ARMCP::CPValue, 0);
2664
2665 // Get the address of the callee into a register
2666 SDValue Addr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2667 Addr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Addr);
2668 Callee = DAG.getLoad(
2669 PtrVt, dl, DAG.getEntryNode(), Addr,
2670 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2671 }
2672 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2673 const char *Sym = S->getSymbol();
2674
2675 // When generating execute-only code we use movw movt pair.
2676 // Currently execute-only is only available for architectures that
2677 // support movw movt, so we are safe to assume that.
2678 if (Subtarget->genExecuteOnly()) {
2679 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2680, __extension__
__PRETTY_FUNCTION__))
2680 "long-calls with execute-only requires movt and movw!")(static_cast <bool> (Subtarget->useMovt() &&
"long-calls with execute-only requires movt and movw!") ? void
(0) : __assert_fail ("Subtarget->useMovt() && \"long-calls with execute-only requires movt and movw!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2680, __extension__
__PRETTY_FUNCTION__))
;
2681 ++NumMovwMovt;
2682 Callee = DAG.getNode(ARMISD::Wrapper, dl, PtrVt,
2683 DAG.getTargetGlobalAddress(GVal, dl, PtrVt));
2684 } else {
2685 // Create a constant pool entry for the callee address
2686 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2687 ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
2688 *DAG.getContext(), Sym, ARMPCLabelIndex, 0);
2689
2690 // Get the address of the callee into a register
2691 SDValue Addr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2692 Addr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Addr);
2693 Callee = DAG.getLoad(
2694 PtrVt, dl, DAG.getEntryNode(), Addr,
2695 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2696 }
2697 }
2698 } else if (isa<GlobalAddressSDNode>(Callee)) {
23
Assuming 'Callee' is a 'class llvm::GlobalAddressSDNode &'
24
Taking true branch
2699 if (!PreferIndirect
24.1
'PreferIndirect' is false
) {
25
Taking true branch
2700 isDirect = true;
2701 bool isDef = GVal->isStrongDefinitionForLinker();
26
Called C++ object pointer is null
2702
2703 // ARM call to a local ARM function is predicable.
2704 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2705 // tBX takes a register source operand.
2706 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2707 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2707, __extension__
__PRETTY_FUNCTION__))
;
2708 Callee = DAG.getNode(
2709 ARMISD::WrapperPIC, dl, PtrVt,
2710 DAG.getTargetGlobalAddress(GVal, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2711 Callee = DAG.getLoad(
2712 PtrVt, dl, DAG.getEntryNode(), Callee,
2713 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2714 MachineMemOperand::MODereferenceable |
2715 MachineMemOperand::MOInvariant);
2716 } else if (Subtarget->isTargetCOFF()) {
2717 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2718, __extension__
__PRETTY_FUNCTION__))
2718 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2718, __extension__
__PRETTY_FUNCTION__))
;
2719 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2720 if (GVal->hasDLLImportStorageClass())
2721 TargetFlags = ARMII::MO_DLLIMPORT;
2722 else if (!TM.shouldAssumeDSOLocal(*GVal->getParent(), GVal))
2723 TargetFlags = ARMII::MO_COFFSTUB;
2724 Callee = DAG.getTargetGlobalAddress(GVal, dl, PtrVt, /*offset=*/0,
2725 TargetFlags);
2726 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2727 Callee =
2728 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2729 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2730 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2731 } else {
2732 Callee = DAG.getTargetGlobalAddress(GVal, dl, PtrVt, 0, 0);
2733 }
2734 }
2735 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2736 isDirect = true;
2737 // tBX takes a register source operand.
2738 const char *Sym = S->getSymbol();
2739 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2740 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2741 ARMConstantPoolValue *CPV =
2742 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2743 ARMPCLabelIndex, 4);
2744 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2745 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2746 Callee = DAG.getLoad(
2747 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2748 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2749 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2750 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2751 } else {
2752 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2753 }
2754 }
2755
2756 if (isCmseNSCall) {
2757 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2758, __extension__
__PRETTY_FUNCTION__))
2758 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2758, __extension__
__PRETTY_FUNCTION__))
;
2759 if (NumBytes > 0) {
2760 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2761 "call to non-secure function would "
2762 "require passing arguments on stack",
2763 dl.getDebugLoc());
2764 DAG.getContext()->diagnose(Diag);
2765 }
2766 if (isStructRet) {
2767 DiagnosticInfoUnsupported Diag(
2768 DAG.getMachineFunction().getFunction(),
2769 "call to non-secure function would return value through pointer",
2770 dl.getDebugLoc());
2771 DAG.getContext()->diagnose(Diag);
2772 }
2773 }
2774
2775 // FIXME: handle tail calls differently.
2776 unsigned CallOpc;
2777 if (Subtarget->isThumb()) {
2778 if (GuardWithBTI)
2779 CallOpc = ARMISD::t2CALL_BTI;
2780 else if (isCmseNSCall)
2781 CallOpc = ARMISD::tSECALL;
2782 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2783 CallOpc = ARMISD::CALL_NOLINK;
2784 else
2785 CallOpc = ARMISD::CALL;
2786 } else {
2787 if (!isDirect && !Subtarget->hasV5TOps())
2788 CallOpc = ARMISD::CALL_NOLINK;
2789 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2790 // Emit regular call when code size is the priority
2791 !Subtarget->hasMinSize())
2792 // "mov lr, pc; b _foo" to avoid confusing the RSP
2793 CallOpc = ARMISD::CALL_NOLINK;
2794 else
2795 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2796 }
2797
2798 // We don't usually want to end the call-sequence here because we would tidy
2799 // the frame up *after* the call, however in the ABI-changing tail-call case
2800 // we've carefully laid out the parameters so that when sp is reset they'll be
2801 // in the correct location.
2802 if (isTailCall && !isSibCall) {
2803 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InFlag, dl);
2804 InFlag = Chain.getValue(1);
2805 }
2806
2807 std::vector<SDValue> Ops;
2808 Ops.push_back(Chain);
2809 Ops.push_back(Callee);
2810
2811 if (isTailCall) {
2812 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2813 }
2814
2815 // Add argument registers to the end of the list so that they are known live
2816 // into the call.
2817 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2818 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2819 RegsToPass[i].second.getValueType()));
2820
2821 // Add a register mask operand representing the call-preserved registers.
2822 const uint32_t *Mask;
2823 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2824 if (isThisReturn) {
2825 // For 'this' returns, use the R0-preserving mask if applicable
2826 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2827 if (!Mask) {
2828 // Set isThisReturn to false if the calling convention is not one that
2829 // allows 'returned' to be modeled in this way, so LowerCallResult does
2830 // not try to pass 'this' straight through
2831 isThisReturn = false;
2832 Mask = ARI->getCallPreservedMask(MF, CallConv);
2833 }
2834 } else
2835 Mask = ARI->getCallPreservedMask(MF, CallConv);
2836
2837 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2837, __extension__
__PRETTY_FUNCTION__))
;
2838 Ops.push_back(DAG.getRegisterMask(Mask));
2839
2840 if (InFlag.getNode())
2841 Ops.push_back(InFlag);
2842
2843 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2844 if (isTailCall) {
2845 MF.getFrameInfo().setHasTailCall();
2846 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2847 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2848 return Ret;
2849 }
2850
2851 // Returns a chain and a flag for retval copy to use.
2852 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2853 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2854 InFlag = Chain.getValue(1);
2855 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2856
2857 // If we're guaranteeing tail-calls will be honoured, the callee must
2858 // pop its own argument stack on return. But this call is *not* a tail call so
2859 // we need to undo that after it returns to restore the status-quo.
2860 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2861 uint64_t CalleePopBytes =
2862 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2863
2864 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, CalleePopBytes, InFlag, dl);
2865 if (!Ins.empty())
2866 InFlag = Chain.getValue(1);
2867
2868 // Handle result values, copying them out of physregs into vregs that we
2869 // return.
2870 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2871 InVals, isThisReturn,
2872 isThisReturn ? OutVals[0] : SDValue());
2873}
2874
2875/// HandleByVal - Every parameter *after* a byval parameter is passed
2876/// on the stack. Remember the next parameter register to allocate,
2877/// and then confiscate the rest of the parameter registers to insure
2878/// this.
2879void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2880 Align Alignment) const {
2881 // Byval (as with any stack) slots are always at least 4 byte aligned.
2882 Alignment = std::max(Alignment, Align(4));
2883
2884 unsigned Reg = State->AllocateReg(GPRArgRegs);
2885 if (!Reg)
2886 return;
2887
2888 unsigned AlignInRegs = Alignment.value() / 4;
2889 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2890 for (unsigned i = 0; i < Waste; ++i)
2891 Reg = State->AllocateReg(GPRArgRegs);
2892
2893 if (!Reg)
2894 return;
2895
2896 unsigned Excess = 4 * (ARM::R4 - Reg);
2897
2898 // Special case when NSAA != SP and parameter size greater than size of
2899 // all remained GPR regs. In that case we can't split parameter, we must
2900 // send it to stack. We also must set NCRN to R4, so waste all
2901 // remained registers.
2902 const unsigned NSAAOffset = State->getNextStackOffset();
2903 if (NSAAOffset != 0 && Size > Excess) {
2904 while (State->AllocateReg(GPRArgRegs))
2905 ;
2906 return;
2907 }
2908
2909 // First register for byval parameter is the first register that wasn't
2910 // allocated before this method call, so it would be "reg".
2911 // If parameter is small enough to be saved in range [reg, r4), then
2912 // the end (first after last) register would be reg + param-size-in-regs,
2913 // else parameter would be splitted between registers and stack,
2914 // end register would be r4 in this case.
2915 unsigned ByValRegBegin = Reg;
2916 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2917 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2918 // Note, first register is allocated in the beginning of function already,
2919 // allocate remained amount of registers we need.
2920 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2921 State->AllocateReg(GPRArgRegs);
2922 // A byval parameter that is split between registers and memory needs its
2923 // size truncated here.
2924 // In the case where the entire structure fits in registers, we set the
2925 // size in memory to zero.
2926 Size = std::max<int>(Size - Excess, 0);
2927}
2928
2929/// MatchingStackOffset - Return true if the given stack call argument is
2930/// already available in the same position (relatively) of the caller's
2931/// incoming argument stack.
2932static
2933bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2934 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2935 const TargetInstrInfo *TII) {
2936 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2937 int FI = std::numeric_limits<int>::max();
2938 if (Arg.getOpcode() == ISD::CopyFromReg) {
2939 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2940 if (!Register::isVirtualRegister(VR))
2941 return false;
2942 MachineInstr *Def = MRI->getVRegDef(VR);
2943 if (!Def)
2944 return false;
2945 if (!Flags.isByVal()) {
2946 if (!TII->isLoadFromStackSlot(*Def, FI))
2947 return false;
2948 } else {
2949 return false;
2950 }
2951 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2952 if (Flags.isByVal())
2953 // ByVal argument is passed in as a pointer but it's now being
2954 // dereferenced. e.g.
2955 // define @foo(%struct.X* %A) {
2956 // tail call @bar(%struct.X* byval %A)
2957 // }
2958 return false;
2959 SDValue Ptr = Ld->getBasePtr();
2960 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2961 if (!FINode)
2962 return false;
2963 FI = FINode->getIndex();
2964 } else
2965 return false;
2966
2967 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2967, __extension__
__PRETTY_FUNCTION__))
;
2968 if (!MFI.isFixedObjectIndex(FI))
2969 return false;
2970 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2971}
2972
2973/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2974/// for tail call optimization. Targets which want to do tail call
2975/// optimization should implement this function.
2976bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2977 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2978 bool isCalleeStructRet, bool isCallerStructRet,
2979 const SmallVectorImpl<ISD::OutputArg> &Outs,
2980 const SmallVectorImpl<SDValue> &OutVals,
2981 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2982 const bool isIndirect) const {
2983 MachineFunction &MF = DAG.getMachineFunction();
2984 const Function &CallerF = MF.getFunction();
2985 CallingConv::ID CallerCC = CallerF.getCallingConv();
2986
2987 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2987, __extension__
__PRETTY_FUNCTION__))
;
2988
2989 // Indirect tail calls cannot be optimized for Thumb1 if the args
2990 // to the call take up r0-r3. The reason is that there are no legal registers
2991 // left to hold the pointer to the function to be called.
2992 // Similarly, if the function uses return address sign and authentication,
2993 // r12 is needed to hold the PAC and is not available to hold the callee
2994 // address.
2995 if (Outs.size() >= 4 &&
2996 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect)) {
2997 if (Subtarget->isThumb1Only())
2998 return false;
2999 // Conservatively assume the function spills LR.
3000 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true))
3001 return false;
3002 }
3003
3004 // Look for obvious safe cases to perform tail call optimization that do not
3005 // require ABI changes. This is what gcc calls sibcall.
3006
3007 // Exception-handling functions need a special set of instructions to indicate
3008 // a return to the hardware. Tail-calling another function would probably
3009 // break this.
3010 if (CallerF.hasFnAttribute("interrupt"))
3011 return false;
3012
3013 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
3014 return CalleeCC == CallerCC;
3015
3016 // Also avoid sibcall optimization if either caller or callee uses struct
3017 // return semantics.
3018 if (isCalleeStructRet || isCallerStructRet)
3019 return false;
3020
3021 // Externally-defined functions with weak linkage should not be
3022 // tail-called on ARM when the OS does not support dynamic
3023 // pre-emption of symbols, as the AAELF spec requires normal calls
3024 // to undefined weak functions to be replaced with a NOP or jump to the
3025 // next instruction. The behaviour of branch instructions in this
3026 // situation (as used for tail calls) is implementation-defined, so we
3027 // cannot rely on the linker replacing the tail call with a return.
3028 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3029 const GlobalValue *GV = G->getGlobal();
3030 const Triple &TT = getTargetMachine().getTargetTriple();
3031 if (GV->hasExternalWeakLinkage() &&
3032 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
3033 return false;
3034 }
3035
3036 // Check that the call results are passed in the same way.
3037 LLVMContext &C = *DAG.getContext();
3038 if (!CCState::resultsCompatible(
3039 getEffectiveCallingConv(CalleeCC, isVarArg),
3040 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
3041 CCAssignFnForReturn(CalleeCC, isVarArg),
3042 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
3043 return false;
3044 // The callee has to preserve all registers the caller needs to preserve.
3045 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3046 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3047 if (CalleeCC != CallerCC) {
3048 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3049 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3050 return false;
3051 }
3052
3053 // If Caller's vararg or byval argument has been split between registers and
3054 // stack, do not perform tail call, since part of the argument is in caller's
3055 // local frame.
3056 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
3057 if (AFI_Caller->getArgRegsSaveSize())
3058 return false;
3059
3060 // If the callee takes no arguments then go on to check the results of the
3061 // call.
3062 if (!Outs.empty()) {
3063 // Check if stack adjustment is needed. For now, do not do this if any
3064 // argument is passed on the stack.
3065 SmallVector<CCValAssign, 16> ArgLocs;
3066 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3067 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3068 if (CCInfo.getNextStackOffset()) {
3069 // Check if the arguments are already laid out in the right way as
3070 // the caller's fixed stack objects.
3071 MachineFrameInfo &MFI = MF.getFrameInfo();
3072 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3073 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3074 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
3075 i != e;
3076 ++i, ++realArgIdx) {
3077 CCValAssign &VA = ArgLocs[i];
3078 EVT RegVT = VA.getLocVT();
3079 SDValue Arg = OutVals[realArgIdx];
3080 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3081 if (VA.getLocInfo() == CCValAssign::Indirect)
3082 return false;
3083 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3084 // f64 and vector types are split into multiple registers or
3085 // register/stack-slot combinations. The types will not match
3086 // the registers; give up on memory f64 refs until we figure
3087 // out what to do about this.
3088 if (!VA.isRegLoc())
3089 return false;
3090 if (!ArgLocs[++i].isRegLoc())
3091 return false;
3092 if (RegVT == MVT::v2f64) {
3093 if (!ArgLocs[++i].isRegLoc())
3094 return false;
3095 if (!ArgLocs[++i].isRegLoc())
3096 return false;
3097 }
3098 } else if (!VA.isRegLoc()) {
3099 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3100 MFI, MRI, TII))
3101 return false;
3102 }
3103 }
3104 }
3105
3106 const MachineRegisterInfo &MRI = MF.getRegInfo();
3107 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3108 return false;
3109 }
3110
3111 return true;
3112}
3113
3114bool
3115ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3116 MachineFunction &MF, bool isVarArg,
3117 const SmallVectorImpl<ISD::OutputArg> &Outs,
3118 LLVMContext &Context) const {
3119 SmallVector<CCValAssign, 16> RVLocs;
3120 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3121 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3122}
3123
3124static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3125 const SDLoc &DL, SelectionDAG &DAG) {
3126 const MachineFunction &MF = DAG.getMachineFunction();
3127 const Function &F = MF.getFunction();
3128
3129 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3130
3131 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3132 // version of the "preferred return address". These offsets affect the return
3133 // instruction if this is a return from PL1 without hypervisor extensions.
3134 // IRQ/FIQ: +4 "subs pc, lr, #4"
3135 // SWI: 0 "subs pc, lr, #0"
3136 // ABORT: +4 "subs pc, lr, #4"
3137 // UNDEF: +4/+2 "subs pc, lr, #0"
3138 // UNDEF varies depending on where the exception came from ARM or Thumb
3139 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3140
3141 int64_t LROffset;
3142 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3143 IntKind == "ABORT")
3144 LROffset = 4;
3145 else if (IntKind == "SWI" || IntKind == "UNDEF")
3146 LROffset = 0;
3147 else
3148 report_fatal_error("Unsupported interrupt attribute. If present, value "
3149 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3150
3151 RetOps.insert(RetOps.begin() + 1,
3152 DAG.getConstant(LROffset, DL, MVT::i32, false));
3153
3154 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3155}
3156
3157SDValue
3158ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3159 bool isVarArg,
3160 const SmallVectorImpl<ISD::OutputArg> &Outs,
3161 const SmallVectorImpl<SDValue> &OutVals,
3162 const SDLoc &dl, SelectionDAG &DAG) const {
3163 // CCValAssign - represent the assignment of the return value to a location.
3164 SmallVector<CCValAssign, 16> RVLocs;
3165
3166 // CCState - Info about the registers and stack slots.
3167 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3168 *DAG.getContext());
3169
3170 // Analyze outgoing return values.
3171 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3172
3173 SDValue Flag;
3174 SmallVector<SDValue, 4> RetOps;
3175 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3176 bool isLittleEndian = Subtarget->isLittle();
3177
3178 MachineFunction &MF = DAG.getMachineFunction();
3179 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3180 AFI->setReturnRegsCount(RVLocs.size());
3181
3182 // Report error if cmse entry function returns structure through first ptr arg.
3183 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3184 // Note: using an empty SDLoc(), as the first line of the function is a
3185 // better place to report than the last line.
3186 DiagnosticInfoUnsupported Diag(
3187 DAG.getMachineFunction().getFunction(),
3188 "secure entry function would return value through pointer",
3189 SDLoc().getDebugLoc());
3190 DAG.getContext()->diagnose(Diag);
3191 }
3192
3193 // Copy the result values into the output registers.
3194 for (unsigned i = 0, realRVLocIdx = 0;
3195 i != RVLocs.size();
3196 ++i, ++realRVLocIdx) {
3197 CCValAssign &VA = RVLocs[i];
3198 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3198, __extension__
__PRETTY_FUNCTION__))
;
3199
3200 SDValue Arg = OutVals[realRVLocIdx];
3201 bool ReturnF16 = false;
3202
3203 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3204 // Half-precision return values can be returned like this:
3205 //
3206 // t11 f16 = fadd ...
3207 // t12: i16 = bitcast t11
3208 // t13: i32 = zero_extend t12
3209 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3210 //
3211 // to avoid code generation for bitcasts, we simply set Arg to the node
3212 // that produces the f16 value, t11 in this case.
3213 //
3214 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3215 SDValue ZE = Arg.getOperand(0);
3216 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3217 SDValue BC = ZE.getOperand(0);
3218 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3219 Arg = BC.getOperand(0);
3220 ReturnF16 = true;
3221 }
3222 }
3223 }
3224 }
3225
3226 switch (VA.getLocInfo()) {
3227 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3227)
;
3228 case CCValAssign::Full: break;
3229 case CCValAssign::BCvt:
3230 if (!ReturnF16)
3231 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3232 break;
3233 }
3234
3235 // Mask f16 arguments if this is a CMSE nonsecure entry.
3236 auto RetVT = Outs[realRVLocIdx].ArgVT;
3237 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3238 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3239 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3240 } else {
3241 auto LocBits = VA.getLocVT().getSizeInBits();
3242 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3243 SDValue Mask =
3244 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3245 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3246 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3247 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3248 }
3249 }
3250
3251 if (VA.needsCustom() &&
3252 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3253 if (VA.getLocVT() == MVT::v2f64) {
3254 // Extract the first half and return it in two registers.
3255 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3256 DAG.getConstant(0, dl, MVT::i32));
3257 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3258 DAG.getVTList(MVT::i32, MVT::i32), Half);
3259
3260 Chain =
3261 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3262 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3263 Flag = Chain.getValue(1);
3264 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3265 VA = RVLocs[++i]; // skip ahead to next loc
3266 Chain =
3267 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3268 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3269 Flag = Chain.getValue(1);
3270 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3271 VA = RVLocs[++i]; // skip ahead to next loc
3272
3273 // Extract the 2nd half and fall through to handle it as an f64 value.
3274 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3275 DAG.getConstant(1, dl, MVT::i32));
3276 }
3277 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3278 // available.
3279 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3280 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3281 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3282 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3283 Flag = Chain.getValue(1);
3284 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3285 VA = RVLocs[++i]; // skip ahead to next loc
3286 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3287 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3288 } else
3289 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3290
3291 // Guarantee that all emitted copies are
3292 // stuck together, avoiding something bad.
3293 Flag = Chain.getValue(1);
3294 RetOps.push_back(DAG.getRegister(
3295 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3296 }
3297 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3298 const MCPhysReg *I =
3299 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3300 if (I) {
3301 for (; *I; ++I) {
3302 if (ARM::GPRRegClass.contains(*I))
3303 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3304 else if (ARM::DPRRegClass.contains(*I))
3305 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3306 else
3307 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3307)
;
3308 }
3309 }
3310
3311 // Update chain and glue.
3312 RetOps[0] = Chain;
3313 if (Flag.getNode())
3314 RetOps.push_back(Flag);
3315
3316 // CPUs which aren't M-class use a special sequence to return from
3317 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3318 // though we use "subs pc, lr, #N").
3319 //
3320 // M-class CPUs actually use a normal return sequence with a special
3321 // (hardware-provided) value in LR, so the normal code path works.
3322 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3323 !Subtarget->isMClass()) {
3324 if (Subtarget->isThumb1Only())
3325 report_fatal_error("interrupt attribute is not supported in Thumb1");
3326 return LowerInterruptReturn(RetOps, dl, DAG);
3327 }
3328
3329 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3330 ARMISD::RET_FLAG;
3331 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3332}
3333
3334bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3335 if (N->getNumValues() != 1)
3336 return false;
3337 if (!N->hasNUsesOfValue(1, 0))
3338 return false;
3339
3340 SDValue TCChain = Chain;
3341 SDNode *Copy = *N->use_begin();
3342 if (Copy->getOpcode() == ISD::CopyToReg) {
3343 // If the copy has a glue operand, we conservatively assume it isn't safe to
3344 // perform a tail call.
3345 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3346 return false;
3347 TCChain = Copy->getOperand(0);
3348 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3349 SDNode *VMov = Copy;
3350 // f64 returned in a pair of GPRs.
3351 SmallPtrSet<SDNode*, 2> Copies;
3352 for (SDNode *U : VMov->uses()) {
3353 if (U->getOpcode() != ISD::CopyToReg)
3354 return false;
3355 Copies.insert(U);
3356 }
3357 if (Copies.size() > 2)
3358 return false;
3359
3360 for (SDNode *U : VMov->uses()) {
3361 SDValue UseChain = U->getOperand(0);
3362 if (Copies.count(UseChain.getNode()))
3363 // Second CopyToReg
3364 Copy = U;
3365 else {
3366 // We are at the top of this chain.
3367 // If the copy has a glue operand, we conservatively assume it
3368 // isn't safe to perform a tail call.
3369 if (U->getOperand(U->getNumOperands() - 1).getValueType() == MVT::Glue)
3370 return false;
3371 // First CopyToReg
3372 TCChain = UseChain;
3373 }
3374 }
3375 } else if (Copy->getOpcode() == ISD::BITCAST) {
3376 // f32 returned in a single GPR.
3377 if (!Copy->hasOneUse())
3378 return false;
3379 Copy = *Copy->use_begin();
3380 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3381 return false;
3382 // If the copy has a glue operand, we conservatively assume it isn't safe to
3383 // perform a tail call.
3384 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3385 return false;
3386 TCChain = Copy->getOperand(0);
3387 } else {
3388 return false;
3389 }
3390
3391 bool HasRet = false;
3392 for (const SDNode *U : Copy->uses()) {
3393 if (U->getOpcode() != ARMISD::RET_FLAG &&
3394 U->getOpcode() != ARMISD::INTRET_FLAG)
3395 return false;
3396 HasRet = true;
3397 }
3398
3399 if (!HasRet)
3400 return false;
3401
3402 Chain = TCChain;
3403 return true;
3404}
3405
3406bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3407 if (!Subtarget->supportsTailCall())
3408 return false;
3409
3410 if (!CI->isTailCall())
3411 return false;
3412
3413 return true;
3414}
3415
3416// Trying to write a 64 bit value so need to split into two 32 bit values first,
3417// and pass the lower and high parts through.
3418static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3419 SDLoc DL(Op);
3420 SDValue WriteValue = Op->getOperand(2);
3421
3422 // This function is only supposed to be called for i64 type argument.
3423 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3424, __extension__
__PRETTY_FUNCTION__))
3424 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3424, __extension__
__PRETTY_FUNCTION__))
;
3425
3426 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3427 DAG.getConstant(0, DL, MVT::i32));
3428 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3429 DAG.getConstant(1, DL, MVT::i32));
3430 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3431 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3432}
3433
3434// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3435// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3436// one of the above mentioned nodes. It has to be wrapped because otherwise
3437// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3438// be used to form addressing mode. These wrapped nodes will be selected
3439// into MOVi.
3440SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3441 SelectionDAG &DAG) const {
3442 EVT PtrVT = Op.getValueType();
3443 // FIXME there is no actual debug info here
3444 SDLoc dl(Op);
3445 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3446 SDValue Res;
3447
3448 // When generating execute-only code Constant Pools must be promoted to the
3449 // global data section. It's a bit ugly that we can't share them across basic
3450 // blocks, but this way we guarantee that execute-only behaves correct with
3451 // position-independent addressing modes.
3452 if (Subtarget->genExecuteOnly()) {
3453 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3454 auto T = const_cast<Type*>(CP->getType());
3455 auto C = const_cast<Constant*>(CP->getConstVal());
3456 auto M = const_cast<Module*>(DAG.getMachineFunction().
3457 getFunction().getParent());
3458 auto GV = new GlobalVariable(
3459 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3460 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3461 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3462 Twine(AFI->createPICLabelUId())
3463 );
3464 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3465 dl, PtrVT);
3466 return LowerGlobalAddress(GA, DAG);
3467 }
3468
3469 // The 16-bit ADR instruction can only encode offsets that are multiples of 4,
3470 // so we need to align to at least 4 bytes when we don't have 32-bit ADR.
3471 Align CPAlign = CP->getAlign();
3472 if (Subtarget->isThumb1Only())
3473 CPAlign = std::max(CPAlign, Align(4));
3474 if (CP->isMachineConstantPoolEntry())
3475 Res =
3476 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CPAlign);
3477 else
3478 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CPAlign);
3479 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3480}
3481
3482unsigned ARMTargetLowering::getJumpTableEncoding() const {
3483 return MachineJumpTableInfo::EK_Inline;
3484}
3485
3486SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3487 SelectionDAG &DAG) const {
3488 MachineFunction &MF = DAG.getMachineFunction();
3489 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3490 unsigned ARMPCLabelIndex = 0;
3491 SDLoc DL(Op);
3492 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3493 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3494 SDValue CPAddr;
3495 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3496 if (!IsPositionIndependent) {
3497 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3498 } else {
3499 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3500 ARMPCLabelIndex = AFI->createPICLabelUId();
3501 ARMConstantPoolValue *CPV =
3502 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3503 ARMCP::CPBlockAddress, PCAdj);
3504 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3505 }
3506 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3507 SDValue Result = DAG.getLoad(
3508 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3509 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3510 if (!IsPositionIndependent)
3511 return Result;
3512 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3513 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3514}
3515
3516/// Convert a TLS address reference into the correct sequence of loads
3517/// and calls to compute the variable's address for Darwin, and return an
3518/// SDValue containing the final node.
3519
3520/// Darwin only has one TLS scheme which must be capable of dealing with the
3521/// fully general situation, in the worst case. This means:
3522/// + "extern __thread" declaration.
3523/// + Defined in a possibly unknown dynamic library.
3524///
3525/// The general system is that each __thread variable has a [3 x i32] descriptor
3526/// which contains information used by the runtime to calculate the address. The
3527/// only part of this the compiler needs to know about is the first word, which
3528/// contains a function pointer that must be called with the address of the
3529/// entire descriptor in "r0".
3530///
3531/// Since this descriptor may be in a different unit, in general access must
3532/// proceed along the usual ARM rules. A common sequence to produce is:
3533///
3534/// movw rT1, :lower16:_var$non_lazy_ptr
3535/// movt rT1, :upper16:_var$non_lazy_ptr
3536/// ldr r0, [rT1]
3537/// ldr rT2, [r0]
3538/// blx rT2
3539/// [...address now in r0...]
3540SDValue
3541ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3542 SelectionDAG &DAG) const {
3543 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3544, __extension__
__PRETTY_FUNCTION__))
3544 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3544, __extension__
__PRETTY_FUNCTION__))
;
3545 SDLoc DL(Op);
3546
3547 // First step is to get the address of the actua global symbol. This is where
3548 // the TLS descriptor lives.
3549 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3550
3551 // The first entry in the descriptor is a function pointer that we must call
3552 // to obtain the address of the variable.
3553 SDValue Chain = DAG.getEntryNode();
3554 SDValue FuncTLVGet = DAG.getLoad(
3555 MVT::i32, DL, Chain, DescAddr,
3556 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3557 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3558 MachineMemOperand::MOInvariant);
3559 Chain = FuncTLVGet.getValue(1);
3560
3561 MachineFunction &F = DAG.getMachineFunction();
3562 MachineFrameInfo &MFI = F.getFrameInfo();
3563 MFI.setAdjustsStack(true);
3564
3565 // TLS calls preserve all registers except those that absolutely must be
3566 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3567 // silly).
3568 auto TRI =
3569 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3570 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3571 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3572
3573 // Finally, we can make the call. This is just a degenerate version of a
3574 // normal AArch64 call node: r0 takes the address of the descriptor, and
3575 // returns the address of the variable in this thread.
3576 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3577 Chain =
3578 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3579 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3580 DAG.getRegisterMask(Mask), Chain.getValue(1));
3581 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3582}
3583
3584SDValue
3585ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3586 SelectionDAG &DAG) const {
3587 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3587, __extension__
__PRETTY_FUNCTION__))
;
3588
3589 SDValue Chain = DAG.getEntryNode();
3590 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3591 SDLoc DL(Op);
3592
3593 // Load the current TEB (thread environment block)
3594 SDValue Ops[] = {Chain,
3595 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3596 DAG.getTargetConstant(15, DL, MVT::i32),
3597 DAG.getTargetConstant(0, DL, MVT::i32),
3598 DAG.getTargetConstant(13, DL, MVT::i32),
3599 DAG.getTargetConstant(0, DL, MVT::i32),
3600 DAG.getTargetConstant(2, DL, MVT::i32)};
3601 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3602 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3603
3604 SDValue TEB = CurrentTEB.getValue(0);
3605 Chain = CurrentTEB.getValue(1);
3606
3607 // Load the ThreadLocalStoragePointer from the TEB
3608 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3609 SDValue TLSArray =
3610 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3611 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3612
3613 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3614 // offset into the TLSArray.
3615
3616 // Load the TLS index from the C runtime
3617 SDValue TLSIndex =
3618 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3619 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3620 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3621
3622 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3623 DAG.getConstant(2, DL, MVT::i32));
3624 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3625 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3626 MachinePointerInfo());
3627
3628 // Get the offset of the start of the .tls section (section base)
3629 const auto *GA = cast<GlobalAddressSDNode>(Op);
3630 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3631 SDValue Offset = DAG.getLoad(
3632 PtrVT, DL, Chain,
3633 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3634 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3635 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3636
3637 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3638}
3639
3640// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3641SDValue
3642ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3643 SelectionDAG &DAG) const {
3644 SDLoc dl(GA);
3645 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3646 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3647 MachineFunction &MF = DAG.getMachineFunction();
3648 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3649 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3650 ARMConstantPoolValue *CPV =
3651 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3652 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3653 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3654 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3655 Argument = DAG.getLoad(
3656 PtrVT, dl, DAG.getEntryNode(), Argument,
3657 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3658 SDValue Chain = Argument.getValue(1);
3659
3660 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3661 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3662
3663 // call __tls_get_addr.
3664 ArgListTy Args;
3665 ArgListEntry Entry;
3666 Entry.Node = Argument;
3667 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3668 Args.push_back(Entry);
3669
3670 // FIXME: is there useful debug info available here?
3671 TargetLowering::CallLoweringInfo CLI(DAG);
3672 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3673 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3674 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3675
3676 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3677 return CallResult.first;
3678}
3679
3680// Lower ISD::GlobalTLSAddress using the "initial exec" or
3681// "local exec" model.
3682SDValue
3683ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3684 SelectionDAG &DAG,
3685 TLSModel::Model model) const {
3686 const GlobalValue *GV = GA->getGlobal();
3687 SDLoc dl(GA);
3688 SDValue Offset;
3689 SDValue Chain = DAG.getEntryNode();
3690 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3691 // Get the Thread Pointer
3692 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3693
3694 if (model == TLSModel::InitialExec) {
3695 MachineFunction &MF = DAG.getMachineFunction();
3696 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3697 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3698 // Initial exec model.
3699 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3700 ARMConstantPoolValue *CPV =
3701 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3702 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3703 true);
3704 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3705 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3706 Offset = DAG.getLoad(
3707 PtrVT, dl, Chain, Offset,
3708 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3709 Chain = Offset.getValue(1);
3710
3711 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3712 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3713
3714 Offset = DAG.getLoad(
3715 PtrVT, dl, Chain, Offset,
3716 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3717 } else {
3718 // local exec model
3719 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3719, __extension__ __PRETTY_FUNCTION__))
;
3720 ARMConstantPoolValue *CPV =
3721 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3722 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3723 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3724 Offset = DAG.getLoad(
3725 PtrVT, dl, Chain, Offset,
3726 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3727 }
3728
3729 // The address of the thread local variable is the add of the thread
3730 // pointer with the offset of the variable.
3731 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3732}
3733
3734SDValue
3735ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3736 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3737 if (DAG.getTarget().useEmulatedTLS())
3738 return LowerToTLSEmulatedModel(GA, DAG);
3739
3740 if (Subtarget->isTargetDarwin())
3741 return LowerGlobalTLSAddressDarwin(Op, DAG);
3742
3743 if (Subtarget->isTargetWindows())
3744 return LowerGlobalTLSAddressWindows(Op, DAG);
3745
3746 // TODO: implement the "local dynamic" model
3747 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3747, __extension__
__PRETTY_FUNCTION__))
;
3748 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3749
3750 switch (model) {
3751 case TLSModel::GeneralDynamic:
3752 case TLSModel::LocalDynamic:
3753 return LowerToTLSGeneralDynamicModel(GA, DAG);
3754 case TLSModel::InitialExec:
3755 case TLSModel::LocalExec:
3756 return LowerToTLSExecModels(GA, DAG, model);
3757 }
3758 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3758)
;
3759}
3760
3761/// Return true if all users of V are within function F, looking through
3762/// ConstantExprs.
3763static bool allUsersAreInFunction(const Value *V, const Function *F) {
3764 SmallVector<const User*,4> Worklist(V->users());
3765 while (!Worklist.empty()) {
3766 auto *U = Worklist.pop_back_val();
3767 if (isa<ConstantExpr>(U)) {
3768 append_range(Worklist, U->users());
3769 continue;
3770 }
3771
3772 auto *I = dyn_cast<Instruction>(U);
3773 if (!I || I->getParent()->getParent() != F)
3774 return false;
3775 }
3776 return true;
3777}
3778
3779static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3780 const GlobalValue *GV, SelectionDAG &DAG,
3781 EVT PtrVT, const SDLoc &dl) {
3782 // If we're creating a pool entry for a constant global with unnamed address,
3783 // and the global is small enough, we can emit it inline into the constant pool
3784 // to save ourselves an indirection.
3785 //
3786 // This is a win if the constant is only used in one function (so it doesn't
3787 // need to be duplicated) or duplicating the constant wouldn't increase code
3788 // size (implying the constant is no larger than 4 bytes).
3789 const Function &F = DAG.getMachineFunction().getFunction();
3790
3791 // We rely on this decision to inline being idemopotent and unrelated to the
3792 // use-site. We know that if we inline a variable at one use site, we'll
3793 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3794 // doesn't know about this optimization, so bail out if it's enabled else
3795 // we could decide to inline here (and thus never emit the GV) but require
3796 // the GV from fast-isel generated code.
3797 if (!EnableConstpoolPromotion ||
3798 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3799 return SDValue();
3800
3801 auto *GVar = dyn_cast<GlobalVariable>(GV);
3802 if (!GVar || !GVar->hasInitializer() ||
3803 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3804 !GVar->hasLocalLinkage())
3805 return SDValue();
3806
3807 // If we inline a value that contains relocations, we move the relocations
3808 // from .data to .text. This is not allowed in position-independent code.
3809 auto *Init = GVar->getInitializer();
3810 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3811 Init->needsDynamicRelocation())
3812 return SDValue();
3813
3814 // The constant islands pass can only really deal with alignment requests
3815 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3816 // any type wanting greater alignment requirements than 4 bytes. We also
3817 // can only promote constants that are multiples of 4 bytes in size or
3818 // are paddable to a multiple of 4. Currently we only try and pad constants
3819 // that are strings for simplicity.
3820 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3821 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3822 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3823 unsigned RequiredPadding = 4 - (Size % 4);
3824 bool PaddingPossible =
3825 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3826 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3827 Size == 0)
3828 return SDValue();
3829
3830 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3831 MachineFunction &MF = DAG.getMachineFunction();
3832 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3833
3834 // We can't bloat the constant pool too much, else the ConstantIslands pass
3835 // may fail to converge. If we haven't promoted this global yet (it may have
3836 // multiple uses), and promoting it would increase the constant pool size (Sz
3837 // > 4), ensure we have space to do so up to MaxTotal.
3838 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3839 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3840 ConstpoolPromotionMaxTotal)
3841 return SDValue();
3842
3843 // This is only valid if all users are in a single function; we can't clone
3844 // the constant in general. The LLVM IR unnamed_addr allows merging
3845 // constants, but not cloning them.
3846 //
3847 // We could potentially allow cloning if we could prove all uses of the
3848 // constant in the current function don't care about the address, like
3849 // printf format strings. But that isn't implemented for now.
3850 if (!allUsersAreInFunction(GVar, &F))
3851 return SDValue();
3852
3853 // We're going to inline this global. Pad it out if needed.
3854 if (RequiredPadding != 4) {
3855 StringRef S = CDAInit->getAsString();
3856
3857 SmallVector<uint8_t,16> V(S.size());
3858 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3859 while (RequiredPadding--)
3860 V.push_back(0);
3861 Init = ConstantDataArray::get(*DAG.getContext(), V);
3862 }
3863
3864 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3865 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3866 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3867 AFI->markGlobalAsPromotedToConstantPool(GVar);
3868 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3869 PaddedSize - 4);
3870 }
3871 ++NumConstpoolPromoted;
3872 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3873}
3874
3875bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3876 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3877 if (!(GV = GA->getAliaseeObject()))
3878 return false;
3879 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3880 return V->isConstant();
3881 return isa<Function>(GV);
3882}
3883
3884SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3885 SelectionDAG &DAG) const {
3886 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3887 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3887)
;
3888 case Triple::COFF:
3889 return LowerGlobalAddressWindows(Op, DAG);
3890 case Triple::ELF:
3891 return LowerGlobalAddressELF(Op, DAG);
3892 case Triple::MachO:
3893 return LowerGlobalAddressDarwin(Op, DAG);
3894 }
3895}
3896
3897SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3898 SelectionDAG &DAG) const {
3899 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3900 SDLoc dl(Op);
3901 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3902 const TargetMachine &TM = getTargetMachine();
3903 bool IsRO = isReadOnly(GV);
3904
3905 // promoteToConstantPool only if not generating XO text section
3906 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3907 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3908 return V;
3909
3910 if (isPositionIndependent()) {
3911 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3912 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3913 UseGOT_PREL ? ARMII::MO_GOT : 0);
3914 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3915 if (UseGOT_PREL)
3916 Result =
3917 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3918 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3919 return Result;
3920 } else if (Subtarget->isROPI() && IsRO) {
3921 // PC-relative.
3922 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3923 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3924 return Result;
3925 } else if (Subtarget->isRWPI() && !IsRO) {
3926 // SB-relative.
3927 SDValue RelAddr;
3928 if (Subtarget->useMovt()) {
3929 ++NumMovwMovt;
3930 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3931 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3932 } else { // use literal pool for address constant
3933 ARMConstantPoolValue *CPV =
3934 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3935 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3936 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3937 RelAddr = DAG.getLoad(
3938 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3939 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3940 }
3941 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3942 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3943 return Result;
3944 }
3945
3946 // If we have T2 ops, we can materialize the address directly via movt/movw
3947 // pair. This is always cheaper.
3948 if (Subtarget->useMovt()) {
3949 ++NumMovwMovt;
3950 // FIXME: Once remat is capable of dealing with instructions with register
3951 // operands, expand this into two nodes.
3952 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3953 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3954 } else {
3955 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3956 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3957 return DAG.getLoad(
3958 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3959 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3960 }
3961}
3962
3963SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3964 SelectionDAG &DAG) const {
3965 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3966, __extension__
__PRETTY_FUNCTION__))
3966 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3966, __extension__
__PRETTY_FUNCTION__))
;
3967 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3968 SDLoc dl(Op);
3969 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3970
3971 if (Subtarget->useMovt())
3972 ++NumMovwMovt;
3973
3974 // FIXME: Once remat is capable of dealing with instructions with register
3975 // operands, expand this into multiple nodes
3976 unsigned Wrapper =
3977 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3978
3979 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3980 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3981
3982 if (Subtarget->isGVIndirectSymbol(GV))
3983 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3984 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3985 return Result;
3986}
3987
3988SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3989 SelectionDAG &DAG) const {
3990 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3990, __extension__
__PRETTY_FUNCTION__))
;
3991 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3992, __extension__
__PRETTY_FUNCTION__))
3992 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3992, __extension__
__PRETTY_FUNCTION__))
;
3993 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3994, __extension__
__PRETTY_FUNCTION__))
3994 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3994, __extension__
__PRETTY_FUNCTION__))
;
3995
3996 const TargetMachine &TM = getTargetMachine();
3997 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3998 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3999 if (GV->hasDLLImportStorageClass())
4000 TargetFlags = ARMII::MO_DLLIMPORT;
4001 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
4002 TargetFlags = ARMII::MO_COFFSTUB;
4003 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4004 SDValue Result;
4005 SDLoc DL(Op);
4006
4007 ++NumMovwMovt;
4008
4009 // FIXME: Once remat is capable of dealing with instructions with register
4010 // operands, expand this into two nodes.
4011 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
4012 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
4013 TargetFlags));
4014 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
4015 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
4016 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
4017 return Result;
4018}
4019
4020SDValue
4021ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
4022 SDLoc dl(Op);
4023 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
4024 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
4025 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
4026 Op.getOperand(1), Val);
4027}
4028
4029SDValue
4030ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
4031 SDLoc dl(Op);
4032 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
4033 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
4034}
4035
4036SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
4037 SelectionDAG &DAG) const {
4038 SDLoc dl(Op);
4039 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
4040 Op.getOperand(0));
4041}
4042
4043SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4044 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
4045 unsigned IntNo =
4046 cast<ConstantSDNode>(
4047 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4048 ->getZExtValue();
4049 switch (IntNo) {
4050 default:
4051 return SDValue(); // Don't custom lower most intrinsics.
4052 case Intrinsic::arm_gnu_eabi_mcount: {
4053 MachineFunction &MF = DAG.getMachineFunction();
4054 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4055 SDLoc dl(Op);
4056 SDValue Chain = Op.getOperand(0);
4057 // call "\01__gnu_mcount_nc"
4058 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
4059 const uint32_t *Mask =
4060 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
4061 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4061, __extension__
__PRETTY_FUNCTION__))
;
4062 // Mark LR an implicit live-in.
4063 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4064 SDValue ReturnAddress =
4065 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
4066 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
4067 SDValue Callee =
4068 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
4069 SDValue RegisterMask = DAG.getRegisterMask(Mask);
4070 if (Subtarget->isThumb())
4071 return SDValue(
4072 DAG.getMachineNode(
4073 ARM::tBL_PUSHLR, dl, ResultTys,
4074 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
4075 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4076 0);
4077 return SDValue(
4078 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
4079 {ReturnAddress, Callee, RegisterMask, Chain}),
4080 0);
4081 }
4082 }
4083}
4084
4085SDValue
4086ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4087 const ARMSubtarget *Subtarget) const {
4088 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4089 SDLoc dl(Op);
4090 switch (IntNo) {
4091 default: return SDValue(); // Don't custom lower most intrinsics.
4092 case Intrinsic::thread_pointer: {
4093 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4094 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4095 }
4096 case Intrinsic::arm_cls: {
4097 const SDValue &Operand = Op.getOperand(1);
4098 const EVT VTy = Op.getValueType();
4099 SDValue SRA =
4100 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4101 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4102 SDValue SHL =
4103 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4104 SDValue OR =
4105 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4106 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4107 return Result;
4108 }
4109 case Intrinsic::arm_cls64: {
4110 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4111 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4112 const SDValue &Operand = Op.getOperand(1);
4113 const EVT VTy = Op.getValueType();
4114
4115 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4116 DAG.getConstant(1, dl, VTy));
4117 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4118 DAG.getConstant(0, dl, VTy));
4119 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4120 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4121 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4122 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4123 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4124 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4125 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4126 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4127 SDValue CheckLo =
4128 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4129 SDValue HiIsZero =
4130 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4131 SDValue AdjustedLo =
4132 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4133 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4134 SDValue Result =
4135 DAG.getSelect(dl, VTy, CheckLo,
4136 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4137 return Result;
4138 }
4139 case Intrinsic::eh_sjlj_lsda: {
4140 MachineFunction &MF = DAG.getMachineFunction();
4141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4142 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4143 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4144 SDValue CPAddr;
4145 bool IsPositionIndependent = isPositionIndependent();
4146 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4147 ARMConstantPoolValue *CPV =
4148 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4149 ARMCP::CPLSDA, PCAdj);
4150 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4151 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4152 SDValue Result = DAG.getLoad(
4153 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4154 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4155
4156 if (IsPositionIndependent) {
4157 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4158 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4159 }
4160 return Result;
4161 }
4162 case Intrinsic::arm_neon_vabs:
4163 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4164 Op.getOperand(1));
4165 case Intrinsic::arm_neon_vmulls:
4166 case Intrinsic::arm_neon_vmullu: {
4167 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4168 ? ARMISD::VMULLs : ARMISD::VMULLu;
4169 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4170 Op.getOperand(1), Op.getOperand(2));
4171 }
4172 case Intrinsic::arm_neon_vminnm:
4173 case Intrinsic::arm_neon_vmaxnm: {
4174 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4175 ? ISD::FMINNUM : ISD::FMAXNUM;
4176 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4177 Op.getOperand(1), Op.getOperand(2));
4178 }
4179 case Intrinsic::arm_neon_vminu:
4180 case Intrinsic::arm_neon_vmaxu: {
4181 if (Op.getValueType().isFloatingPoint())
4182 return SDValue();
4183 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4184 ? ISD::UMIN : ISD::UMAX;
4185 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4186 Op.getOperand(1), Op.getOperand(2));
4187 }
4188 case Intrinsic::arm_neon_vmins:
4189 case Intrinsic::arm_neon_vmaxs: {
4190 // v{min,max}s is overloaded between signed integers and floats.
4191 if (!Op.getValueType().isFloatingPoint()) {
4192 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4193 ? ISD::SMIN : ISD::SMAX;
4194 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4195 Op.getOperand(1), Op.getOperand(2));
4196 }
4197 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4198 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4199 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4200 Op.getOperand(1), Op.getOperand(2));
4201 }
4202 case Intrinsic::arm_neon_vtbl1:
4203 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4204 Op.getOperand(1), Op.getOperand(2));
4205 case Intrinsic::arm_neon_vtbl2:
4206 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4207 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4208 case Intrinsic::arm_mve_pred_i2v:
4209 case Intrinsic::arm_mve_pred_v2i:
4210 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4211 Op.getOperand(1));
4212 case Intrinsic::arm_mve_vreinterpretq:
4213 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4214 Op.getOperand(1));
4215 case Intrinsic::arm_mve_lsll:
4216 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4217 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4218 case Intrinsic::arm_mve_asrl:
4219 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4220 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4221 }
4222}
4223
4224static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4225 const ARMSubtarget *Subtarget) {
4226 SDLoc dl(Op);
4227 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4228 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4229 if (SSID == SyncScope::SingleThread)
4230 return Op;
4231
4232 if (!Subtarget->hasDataBarrier()) {
4233 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4234 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4235 // here.
4236 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4237, __extension__
__PRETTY_FUNCTION__))
4237 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4237, __extension__
__PRETTY_FUNCTION__))
;
4238 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4239 DAG.getConstant(0, dl, MVT::i32));
4240 }
4241
4242 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4243 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4244 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4245 if (Subtarget->isMClass()) {
4246 // Only a full system barrier exists in the M-class architectures.
4247 Domain = ARM_MB::SY;
4248 } else if (Subtarget->preferISHSTBarriers() &&
4249 Ord == AtomicOrdering::Release) {
4250 // Swift happens to implement ISHST barriers in a way that's compatible with
4251 // Release semantics but weaker than ISH so we'd be fools not to use
4252 // it. Beware: other processors probably don't!
4253 Domain = ARM_MB::ISHST;
4254 }
4255
4256 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4257 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4258 DAG.getConstant(Domain, dl, MVT::i32));
4259}
4260
4261static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4262 const ARMSubtarget *Subtarget) {
4263 // ARM pre v5TE and Thumb1 does not have preload instructions.
4264 if (!(Subtarget->isThumb2() ||
4265 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4266 // Just preserve the chain.
4267 return Op.getOperand(0);
4268
4269 SDLoc dl(Op);
4270 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4271 if (!isRead &&
4272 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4273 // ARMv7 with MP extension has PLDW.
4274 return Op.getOperand(0);
4275
4276 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4277 if (Subtarget->isThumb()) {
4278 // Invert the bits.
4279 isRead = ~isRead & 1;
4280 isData = ~isData & 1;
4281 }
4282
4283 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4284 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4285 DAG.getConstant(isData, dl, MVT::i32));
4286}
4287
4288static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4289 MachineFunction &MF = DAG.getMachineFunction();
4290 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4291
4292 // vastart just stores the address of the VarArgsFrameIndex slot into the
4293 // memory location argument.
4294 SDLoc dl(Op);
4295 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4296 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4297 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4298 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4299 MachinePointerInfo(SV));
4300}
4301
4302SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4303 CCValAssign &NextVA,
4304 SDValue &Root,
4305 SelectionDAG &DAG,
4306 const SDLoc &dl) const {
4307 MachineFunction &MF = DAG.getMachineFunction();
4308 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4309
4310 const TargetRegisterClass *RC;
4311 if (AFI->isThumb1OnlyFunction())
4312 RC = &ARM::tGPRRegClass;
4313 else
4314 RC = &ARM::GPRRegClass;
4315
4316 // Transform the arguments stored in physical registers into virtual ones.
4317 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4318 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4319
4320 SDValue ArgValue2;
4321 if (NextVA.isMemLoc()) {
4322 MachineFrameInfo &MFI = MF.getFrameInfo();
4323 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4324
4325 // Create load node to retrieve arguments from the stack.
4326 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4327 ArgValue2 = DAG.getLoad(
4328 MVT::i32, dl, Root, FIN,
4329 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4330 } else {
4331 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4332 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4333 }
4334 if (!Subtarget->isLittle())
4335 std::swap (ArgValue, ArgValue2);
4336 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4337}
4338
4339// The remaining GPRs hold either the beginning of variable-argument
4340// data, or the beginning of an aggregate passed by value (usually
4341// byval). Either way, we allocate stack slots adjacent to the data
4342// provided by our caller, and store the unallocated registers there.
4343// If this is a variadic function, the va_list pointer will begin with
4344// these values; otherwise, this reassembles a (byval) structure that
4345// was split between registers and memory.
4346// Return: The frame index registers were stored into.
4347int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4348 const SDLoc &dl, SDValue &Chain,
4349 const Value *OrigArg,
4350 unsigned InRegsParamRecordIdx,
4351 int ArgOffset, unsigned ArgSize) const {
4352 // Currently, two use-cases possible:
4353 // Case #1. Non-var-args function, and we meet first byval parameter.
4354 // Setup first unallocated register as first byval register;
4355 // eat all remained registers
4356 // (these two actions are performed by HandleByVal method).
4357 // Then, here, we initialize stack frame with
4358 // "store-reg" instructions.
4359 // Case #2. Var-args function, that doesn't contain byval parameters.
4360 // The same: eat all remained unallocated registers,
4361 // initialize stack frame.
4362
4363 MachineFunction &MF = DAG.getMachineFunction();
4364 MachineFrameInfo &MFI = MF.getFrameInfo();
4365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4366 unsigned RBegin, REnd;
4367 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4368 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4369 } else {
4370 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4371 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4372 REnd = ARM::R4;
4373 }
4374
4375 if (REnd != RBegin)
4376 ArgOffset = -4 * (ARM::R4 - RBegin);
4377
4378 auto PtrVT = getPointerTy(DAG.getDataLayout());
4379 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4380 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4381
4382 SmallVector<SDValue, 4> MemOps;
4383 const TargetRegisterClass *RC =
4384 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4385
4386 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4387 Register VReg = MF.addLiveIn(Reg, RC);
4388 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4389 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4390 MachinePointerInfo(OrigArg, 4 * i));
4391 MemOps.push_back(Store);
4392 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4393 }
4394
4395 if (!MemOps.empty())
4396 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4397 return FrameIndex;
4398}
4399
4400// Setup stack frame, the va_list pointer will start from.
4401void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4402 const SDLoc &dl, SDValue &Chain,
4403 unsigned ArgOffset,
4404 unsigned TotalArgRegsSaveSize,
4405 bool ForceMutable) const {
4406 MachineFunction &MF = DAG.getMachineFunction();
4407 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4408
4409 // Try to store any remaining integer argument regs
4410 // to their spots on the stack so that they may be loaded by dereferencing
4411 // the result of va_next.
4412 // If there is no regs to be stored, just point address after last
4413 // argument passed via stack.
4414 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4415 CCInfo.getInRegsParamsCount(),
4416 CCInfo.getNextStackOffset(),
4417 std::max(4U, TotalArgRegsSaveSize));
4418 AFI->setVarArgsFrameIndex(FrameIndex);
4419}
4420
4421bool ARMTargetLowering::splitValueIntoRegisterParts(
4422 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4423 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4424 bool IsABIRegCopy = CC.has_value();
4425 EVT ValueVT = Val.getValueType();
4426 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4427 PartVT == MVT::f32) {
4428 unsigned ValueBits = ValueVT.getSizeInBits();
4429 unsigned PartBits = PartVT.getSizeInBits();
4430 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4431 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4432 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4433 Parts[0] = Val;
4434 return true;
4435 }
4436 return false;
4437}
4438
4439SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4440 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4441 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4442 bool IsABIRegCopy = CC.has_value();
4443 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4444 PartVT == MVT::f32) {
4445 unsigned ValueBits = ValueVT.getSizeInBits();
4446 unsigned PartBits = PartVT.getSizeInBits();
4447 SDValue Val = Parts[0];
4448
4449 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4450 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4451 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4452 return Val;
4453 }
4454 return SDValue();
4455}
4456
4457SDValue ARMTargetLowering::LowerFormalArguments(
4458 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4459 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4460 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4461 MachineFunction &MF = DAG.getMachineFunction();
4462 MachineFrameInfo &MFI = MF.getFrameInfo();
4463
4464 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4465
4466 // Assign locations to all of the incoming arguments.
4467 SmallVector<CCValAssign, 16> ArgLocs;
4468 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4469 *DAG.getContext());
4470 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4471
4472 SmallVector<SDValue, 16> ArgValues;
4473 SDValue ArgValue;
4474 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4475 unsigned CurArgIdx = 0;
4476
4477 // Initially ArgRegsSaveSize is zero.
4478 // Then we increase this value each time we meet byval parameter.
4479 // We also increase this value in case of varargs function.
4480 AFI->setArgRegsSaveSize(0);
4481
4482 // Calculate the amount of stack space that we need to allocate to store
4483 // byval and variadic arguments that are passed in registers.
4484 // We need to know this before we allocate the first byval or variadic
4485 // argument, as they will be allocated a stack slot below the CFA (Canonical
4486 // Frame Address, the stack pointer at entry to the function).
4487 unsigned ArgRegBegin = ARM::R4;
4488 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4489 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4490 break;
4491
4492 CCValAssign &VA = ArgLocs[i];
4493 unsigned Index = VA.getValNo();
4494 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4495 if (!Flags.isByVal())
4496 continue;
4497
4498 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4498, __extension__
__PRETTY_FUNCTION__))
;
4499 unsigned RBegin, REnd;
4500 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4501 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4502
4503 CCInfo.nextInRegsParam();
4504 }
4505 CCInfo.rewindByValRegsInfo();
4506
4507 int lastInsIndex = -1;
4508 if (isVarArg && MFI.hasVAStart()) {
4509 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4510 if (RegIdx != std::size(GPRArgRegs))
4511 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4512 }
4513
4514 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4515 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4516 auto PtrVT = getPointerTy(DAG.getDataLayout());
4517
4518 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4519 CCValAssign &VA = ArgLocs[i];
4520 if (Ins[VA.getValNo()].isOrigArg()) {
4521 std::advance(CurOrigArg,
4522 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4523 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4524 }
4525 // Arguments stored in registers.
4526 if (VA.isRegLoc()) {
4527 EVT RegVT = VA.getLocVT();
4528
4529 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4530 // f64 and vector types are split up into multiple registers or
4531 // combinations of registers and stack slots.
4532 SDValue ArgValue1 =
4533 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4534 VA = ArgLocs[++i]; // skip ahead to next loc
4535 SDValue ArgValue2;
4536 if (VA.isMemLoc()) {
4537 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4538 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4539 ArgValue2 = DAG.getLoad(
4540 MVT::f64, dl, Chain, FIN,
4541 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4542 } else {
4543 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4544 }
4545 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4546 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4547 ArgValue1, DAG.getIntPtrConstant(0, dl));
4548 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4549 ArgValue2, DAG.getIntPtrConstant(1, dl));
4550 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4551 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4552 } else {
4553 const TargetRegisterClass *RC;
4554
4555 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4556 RC = &ARM::HPRRegClass;
4557 else if (RegVT == MVT::f32)
4558 RC = &ARM::SPRRegClass;
4559 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4560 RegVT == MVT::v4bf16)
4561 RC = &ARM::DPRRegClass;
4562 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4563 RegVT == MVT::v8bf16)
4564 RC = &ARM::QPRRegClass;
4565 else if (RegVT == MVT::i32)
4566 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4567 : &ARM::GPRRegClass;
4568 else
4569 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4569)
;
4570
4571 // Transform the arguments in physical registers into virtual ones.
4572 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4573 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4574
4575 // If this value is passed in r0 and has the returned attribute (e.g.
4576 // C++ 'structors), record this fact for later use.
4577 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4578 AFI->setPreservesR0();
4579 }
4580 }
4581
4582 // If this is an 8 or 16-bit value, it is really passed promoted
4583 // to 32 bits. Insert an assert[sz]ext to capture this, then
4584 // truncate to the right size.
4585 switch (VA.getLocInfo()) {
4586 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4586)
;
4587 case CCValAssign::Full: break;
4588 case CCValAssign::BCvt:
4589 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4590 break;
4591 case CCValAssign::SExt:
4592 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4593 DAG.getValueType(VA.getValVT()));
4594 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4595 break;
4596 case CCValAssign::ZExt:
4597 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4598 DAG.getValueType(VA.getValVT()));
4599 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4600 break;
4601 }
4602
4603 // f16 arguments have their size extended to 4 bytes and passed as if they
4604 // had been copied to the LSBs of a 32-bit register.
4605 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4606 if (VA.needsCustom() &&
4607 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4608 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4609
4610 InVals.push_back(ArgValue);
4611 } else { // VA.isRegLoc()
4612 // Only arguments passed on the stack should make it here.
4613 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
4613, __extension__ __PRETTY_FUNCTION__))
;
4614 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4614, __extension__
__PRETTY_FUNCTION__))
;
4615
4616 int index = VA.getValNo();
4617
4618 // Some Ins[] entries become multiple ArgLoc[] entries.
4619 // Process them only once.
4620 if (index != lastInsIndex)
4621 {
4622 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4623 // FIXME: For now, all byval parameter objects are marked mutable.
4624 // This can be changed with more analysis.
4625 // In case of tail call optimization mark all arguments mutable.
4626 // Since they could be overwritten by lowering of arguments in case of
4627 // a tail call.
4628 if (Flags.isByVal()) {
4629 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4630, __extension__
__PRETTY_FUNCTION__))
4630 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4630, __extension__
__PRETTY_FUNCTION__))
;
4631 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4632
4633 int FrameIndex = StoreByValRegs(
4634 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4635 VA.getLocMemOffset(), Flags.getByValSize());
4636 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4637 CCInfo.nextInRegsParam();
4638 } else {
4639 unsigned FIOffset = VA.getLocMemOffset();
4640 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4641 FIOffset, true);
4642
4643 // Create load nodes to retrieve arguments from the stack.
4644 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4645 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4646 MachinePointerInfo::getFixedStack(
4647 DAG.getMachineFunction(), FI)));
4648 }
4649 lastInsIndex = index;
4650 }
4651 }
4652 }
4653
4654 // varargs
4655 if (isVarArg && MFI.hasVAStart()) {
4656 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4657 TotalArgRegsSaveSize);
4658 if (AFI->isCmseNSEntryFunction()) {
4659 DiagnosticInfoUnsupported Diag(
4660 DAG.getMachineFunction().getFunction(),
4661 "secure entry function must not be variadic", dl.getDebugLoc());
4662 DAG.getContext()->diagnose(Diag);
4663 }
4664 }
4665
4666 unsigned StackArgSize = CCInfo.getNextStackOffset();
4667 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4668 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4669 // The only way to guarantee a tail call is if the callee restores its
4670 // argument area, but it must also keep the stack aligned when doing so.
4671 const DataLayout &DL = DAG.getDataLayout();
4672 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4673
4674 AFI->setArgumentStackToRestore(StackArgSize);
4675 }
4676 AFI->setArgumentStackSize(StackArgSize);
4677
4678 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4679 DiagnosticInfoUnsupported Diag(
4680 DAG.getMachineFunction().getFunction(),
4681 "secure entry function requires arguments on stack", dl.getDebugLoc());
4682 DAG.getContext()->diagnose(Diag);
4683 }
4684
4685 return Chain;
4686}
4687
4688/// isFloatingPointZero - Return true if this is +0.0.
4689static bool isFloatingPointZero(SDValue Op) {
4690 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4691 return CFP->getValueAPF().isPosZero();
4692 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4693 // Maybe this has already been legalized into the constant pool?
4694 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4695 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4696 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4697 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4698 return CFP->getValueAPF().isPosZero();
4699 }
4700 } else if (Op->getOpcode() == ISD::BITCAST &&
4701 Op->getValueType(0) == MVT::f64) {
4702 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4703 // created by LowerConstantFP().
4704 SDValue BitcastOp = Op->getOperand(0);
4705 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4706 isNullConstant(BitcastOp->getOperand(0)))
4707 return true;
4708 }
4709 return false;
4710}
4711
4712/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4713/// the given operands.
4714SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4715 SDValue &ARMcc, SelectionDAG &DAG,
4716 const SDLoc &dl) const {
4717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4718 unsigned C = RHSC->getZExtValue();
4719 if (!isLegalICmpImmediate((int32_t)C)) {
4720 // Constant does not fit, try adjusting it by one.
4721 switch (CC) {
4722 default: break;
4723 case ISD::SETLT:
4724 case ISD::SETGE:
4725 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4726 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4727 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4728 }
4729 break;
4730 case ISD::SETULT:
4731 case ISD::SETUGE:
4732 if (C != 0 && isLegalICmpImmediate(C-1)) {
4733 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4734 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4735 }
4736 break;
4737 case ISD::SETLE:
4738 case ISD::SETGT:
4739 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4740 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4741 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4742 }
4743 break;
4744 case ISD::SETULE:
4745 case ISD::SETUGT:
4746 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4747 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4748 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4749 }
4750 break;
4751 }
4752 }
4753 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4754 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4755 // In ARM and Thumb-2, the compare instructions can shift their second
4756 // operand.
4757 CC = ISD::getSetCCSwappedOperands(CC);
4758 std::swap(LHS, RHS);
4759 }
4760
4761 // Thumb1 has very limited immediate modes, so turning an "and" into a
4762 // shift can save multiple instructions.
4763 //
4764 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4765 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4766 // own. If it's the operand to an unsigned comparison with an immediate,
4767 // we can eliminate one of the shifts: we transform
4768 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4769 //
4770 // We avoid transforming cases which aren't profitable due to encoding
4771 // details:
4772 //
4773 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4774 // would not; in that case, we're essentially trading one immediate load for
4775 // another.
4776 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4777 // 3. C2 is zero; we have other code for this special case.
4778 //
4779 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4780 // instruction, since the AND is always one instruction anyway, but we could
4781 // use narrow instructions in some cases.
4782 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4783 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4784 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4785 !isSignedIntSetCC(CC)) {
4786 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4787 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4788 uint64_t RHSV = RHSC->getZExtValue();
4789 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4790 unsigned ShiftBits = countLeadingZeros(Mask);
4791 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4792 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4793 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4794 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4795 }
4796 }
4797 }
4798
4799 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4800 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4801 // way a cmp would.
4802 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4803 // some tweaks to the heuristics for the previous and->shift transform.
4804 // FIXME: Optimize cases where the LHS isn't a shift.
4805 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4806 isa<ConstantSDNode>(RHS) &&
4807 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4808 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4809 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4810 unsigned ShiftAmt =
4811 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4812 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4813 DAG.getVTList(MVT::i32, MVT::i32),
4814 LHS.getOperand(0),
4815 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4816 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4817 Shift.getValue(1), SDValue());
4818 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4819 return Chain.getValue(1);
4820 }
4821
4822 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4823
4824 // If the RHS is a constant zero then the V (overflow) flag will never be
4825 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4826 // simpler for other passes (like the peephole optimiser) to deal with.
4827 if (isNullConstant(RHS)) {
4828 switch (CondCode) {
4829 default: break;
4830 case ARMCC::GE:
4831 CondCode = ARMCC::PL;
4832 break;
4833 case ARMCC::LT:
4834 CondCode = ARMCC::MI;
4835 break;
4836 }
4837 }
4838
4839 ARMISD::NodeType CompareType;
4840 switch (CondCode) {
4841 default:
4842 CompareType = ARMISD::CMP;
4843 break;
4844 case ARMCC::EQ:
4845 case ARMCC::NE:
4846 // Uses only Z Flag
4847 CompareType = ARMISD::CMPZ;
4848 break;
4849 }
4850 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4851 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4852}
4853
4854/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4855SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4856 SelectionDAG &DAG, const SDLoc &dl,
4857 bool Signaling) const {
4858 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4858, __extension__
__PRETTY_FUNCTION__))
;
4859 SDValue Cmp;
4860 if (!isFloatingPointZero(RHS))
4861 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4862 dl, MVT::Glue, LHS, RHS);
4863 else
4864 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4865 dl, MVT::Glue, LHS);
4866 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4867}
4868
4869/// duplicateCmp - Glue values can have only one use, so this function
4870/// duplicates a comparison node.
4871SDValue
4872ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4873 unsigned Opc = Cmp.getOpcode();
4874 SDLoc DL(Cmp);
4875 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4876 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4877
4878 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4878, __extension__
__PRETTY_FUNCTION__))
;
4879 Cmp = Cmp.getOperand(0);
4880 Opc = Cmp.getOpcode();
4881 if (Opc == ARMISD::CMPFP)
4882 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4883 else {
4884 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4884, __extension__
__PRETTY_FUNCTION__))
;
4885 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4886 }
4887 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4888}
4889
4890// This function returns three things: the arithmetic computation itself
4891// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4892// comparison and the condition code define the case in which the arithmetic
4893// computation *does not* overflow.
4894std::pair<SDValue, SDValue>
4895ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4896 SDValue &ARMcc) const {
4897 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4897, __extension__
__PRETTY_FUNCTION__))
;
4898
4899 SDValue Value, OverflowCmp;
4900 SDValue LHS = Op.getOperand(0);
4901 SDValue RHS = Op.getOperand(1);
4902 SDLoc dl(Op);
4903
4904 // FIXME: We are currently always generating CMPs because we don't support
4905 // generating CMN through the backend. This is not as good as the natural
4906 // CMP case because it causes a register dependency and cannot be folded
4907 // later.
4908
4909 switch (Op.getOpcode()) {
4910 default:
4911 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4911)
;
4912 case ISD::SADDO:
4913 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4914 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4915 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4916 break;
4917 case ISD::UADDO:
4918 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4919 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4920 // We do not use it in the USUBO case as Value may not be used.
4921 Value = DAG.getNode(ARMISD::ADDC, dl,
4922 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4923 .getValue(0);
4924 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4925 break;
4926 case ISD::SSUBO:
4927 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4928 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4929 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4930 break;
4931 case ISD::USUBO:
4932 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4933 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4934 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4935 break;
4936 case ISD::UMULO:
4937 // We generate a UMUL_LOHI and then check if the high word is 0.
4938 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4939 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4940 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4941 LHS, RHS);
4942 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4943 DAG.getConstant(0, dl, MVT::i32));
4944 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4945 break;
4946 case ISD::SMULO:
4947 // We generate a SMUL_LOHI and then check if all the bits of the high word
4948 // are the same as the sign bit of the low word.
4949 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4950 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4951 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4952 LHS, RHS);
4953 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4954 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4955 Value.getValue(0),
4956 DAG.getConstant(31, dl, MVT::i32)));
4957 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4958 break;
4959 } // switch (...)
4960
4961 return std::make_pair(Value, OverflowCmp);
4962}
4963
4964SDValue
4965ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4966 // Let legalize expand this if it isn't a legal type yet.
4967 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4968 return SDValue();
4969
4970 SDValue Value, OverflowCmp;
4971 SDValue ARMcc;
4972 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4973 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4974 SDLoc dl(Op);
4975 // We use 0 and 1 as false and true values.
4976 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4977 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4978 EVT VT = Op.getValueType();
4979
4980 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4981 ARMcc, CCR, OverflowCmp);
4982
4983 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4984 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4985}
4986
4987static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4988 SelectionDAG &DAG) {
4989 SDLoc DL(BoolCarry);
4990 EVT CarryVT = BoolCarry.getValueType();
4991
4992 // This converts the boolean value carry into the carry flag by doing
4993 // ARMISD::SUBC Carry, 1
4994 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4995 DAG.getVTList(CarryVT, MVT::i32),
4996 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4997 return Carry.getValue(1);
4998}
4999
5000static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
5001 SelectionDAG &DAG) {
5002 SDLoc DL(Flags);
5003
5004 // Now convert the carry flag into a boolean carry. We do this
5005 // using ARMISD:ADDE 0, 0, Carry
5006 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
5007 DAG.getConstant(0, DL, MVT::i32),
5008 DAG.getConstant(0, DL, MVT::i32), Flags);
5009}
5010
5011SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
5012 SelectionDAG &DAG) const {
5013 // Let legalize expand this if it isn't a legal type yet.
5014 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
5015 return SDValue();
5016
5017 SDValue LHS = Op.getOperand(0);
5018 SDValue RHS = Op.getOperand(1);
5019 SDLoc dl(Op);
5020
5021 EVT VT = Op.getValueType();
5022 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5023 SDValue Value;
5024 SDValue Overflow;
5025 switch (Op.getOpcode()) {
5026 default:
5027 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5027)
;
5028 case ISD::UADDO:
5029 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
5030 // Convert the carry flag into a boolean value.
5031 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5032 break;
5033 case ISD::USUBO: {
5034 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
5035 // Convert the carry flag into a boolean value.
5036 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5037 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
5038 // value. So compute 1 - C.
5039 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
5040 DAG.getConstant(1, dl, MVT::i32), Overflow);
5041 break;
5042 }
5043 }
5044
5045 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5046}
5047
5048static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
5049 const ARMSubtarget *Subtarget) {
5050 EVT VT = Op.getValueType();
5051 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
5052 return SDValue();
5053 if (!VT.isSimple())
5054 return SDValue();
5055
5056 unsigned NewOpcode;
5057 switch (VT.getSimpleVT().SimpleTy) {
5058 default:
5059 return SDValue();
5060 case MVT::i8:
5061 switch (Op->getOpcode()) {
5062 case ISD::UADDSAT:
5063 NewOpcode = ARMISD::UQADD8b;
5064 break;
5065 case ISD::SADDSAT:
5066 NewOpcode = ARMISD::QADD8b;
5067 break;
5068 case ISD::USUBSAT:
5069 NewOpcode = ARMISD::UQSUB8b;
5070 break;
5071 case ISD::SSUBSAT:
5072 NewOpcode = ARMISD::QSUB8b;
5073 break;
5074 }
5075 break;
5076 case MVT::i16:
5077 switch (Op->getOpcode()) {
5078 case ISD::UADDSAT:
5079 NewOpcode = ARMISD::UQADD16b;
5080 break;
5081 case ISD::SADDSAT:
5082 NewOpcode = ARMISD::QADD16b;
5083 break;
5084 case ISD::USUBSAT:
5085 NewOpcode = ARMISD::UQSUB16b;
5086 break;
5087 case ISD::SSUBSAT:
5088 NewOpcode = ARMISD::QSUB16b;
5089 break;
5090 }
5091 break;
5092 }
5093
5094 SDLoc dl(Op);
5095 SDValue Add =
5096 DAG.getNode(NewOpcode, dl, MVT::i32,
5097 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5098 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5099 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5100}
5101
5102SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5103 SDValue Cond = Op.getOperand(0);
5104 SDValue SelectTrue = Op.getOperand(1);
5105 SDValue SelectFalse = Op.getOperand(2);
5106 SDLoc dl(Op);
5107 unsigned Opc = Cond.getOpcode();
5108
5109 if (Cond.getResNo() == 1 &&
5110 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5111 Opc == ISD::USUBO)) {
5112 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5113 return SDValue();
5114
5115 SDValue Value, OverflowCmp;
5116 SDValue ARMcc;
5117 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5118 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5119 EVT VT = Op.getValueType();
5120
5121 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5122 OverflowCmp, DAG);
5123 }
5124
5125 // Convert:
5126 //
5127 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5128 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5129 //
5130 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5131 const ConstantSDNode *CMOVTrue =
5132 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5133 const ConstantSDNode *CMOVFalse =
5134 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5135
5136 if (CMOVTrue && CMOVFalse) {
5137 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5138 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5139
5140 SDValue True;
5141 SDValue False;
5142 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5143 True = SelectTrue;
5144 False = SelectFalse;
5145 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5146 True = SelectFalse;
5147 False = SelectTrue;
5148 }
5149
5150 if (True.getNode() && False.getNode()) {
5151 EVT VT = Op.getValueType();
5152 SDValue ARMcc = Cond.getOperand(2);
5153 SDValue CCR = Cond.getOperand(3);
5154 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5155 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5155, __extension__ __PRETTY_FUNCTION__))
;
5156 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5157 }
5158 }
5159 }
5160
5161 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5162 // undefined bits before doing a full-word comparison with zero.
5163 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5164 DAG.getConstant(1, dl, Cond.getValueType()));
5165
5166 return DAG.getSelectCC(dl, Cond,
5167 DAG.getConstant(0, dl, Cond.getValueType()),
5168 SelectTrue, SelectFalse, ISD::SETNE);
5169}
5170
5171static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5172 bool &swpCmpOps, bool &swpVselOps) {
5173 // Start by selecting the GE condition code for opcodes that return true for
5174 // 'equality'
5175 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5176 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5177 CondCode = ARMCC::GE;
5178
5179 // and GT for opcodes that return false for 'equality'.
5180 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5181 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5182 CondCode = ARMCC::GT;
5183
5184 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5185 // to swap the compare operands.
5186 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5187 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5188 swpCmpOps = true;
5189
5190 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5191 // If we have an unordered opcode, we need to swap the operands to the VSEL
5192 // instruction (effectively negating the condition).
5193 //
5194 // This also has the effect of swapping which one of 'less' or 'greater'
5195 // returns true, so we also swap the compare operands. It also switches
5196 // whether we return true for 'equality', so we compensate by picking the
5197 // opposite condition code to our original choice.
5198 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5199 CC == ISD::SETUGT) {
5200 swpCmpOps = !swpCmpOps;
5201 swpVselOps = !swpVselOps;
5202 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5203 }
5204
5205 // 'ordered' is 'anything but unordered', so use the VS condition code and
5206 // swap the VSEL operands.
5207 if (CC == ISD::SETO) {
5208 CondCode = ARMCC::VS;
5209 swpVselOps = true;
5210 }
5211
5212 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5213 // code and swap the VSEL operands. Also do this if we don't care about the
5214 // unordered case.
5215 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5216 CondCode = ARMCC::EQ;
5217 swpVselOps = true;
5218 }
5219}
5220
5221SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5222 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5223 SDValue Cmp, SelectionDAG &DAG) const {
5224 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5225 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5226 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5227 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5228 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5229
5230 SDValue TrueLow = TrueVal.getValue(0);
5231 SDValue TrueHigh = TrueVal.getValue(1);
5232 SDValue FalseLow = FalseVal.getValue(0);
5233 SDValue FalseHigh = FalseVal.getValue(1);
5234
5235 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5236 ARMcc, CCR, Cmp);
5237 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5238 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5239
5240 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5241 } else {
5242 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5243 Cmp);
5244 }
5245}
5246
5247static bool isGTorGE(ISD::CondCode CC) {
5248 return CC == ISD::SETGT || CC == ISD::SETGE;
5249}
5250
5251static bool isLTorLE(ISD::CondCode CC) {
5252 return CC == ISD::SETLT || CC == ISD::SETLE;
5253}
5254
5255// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5256// All of these conditions (and their <= and >= counterparts) will do:
5257// x < k ? k : x
5258// x > k ? x : k
5259// k < x ? x : k
5260// k > x ? k : x
5261static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5262 const SDValue TrueVal, const SDValue FalseVal,
5263 const ISD::CondCode CC, const SDValue K) {
5264 return (isGTorGE(CC) &&
5265 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5266 (isLTorLE(CC) &&
5267 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5268}
5269
5270// Check if two chained conditionals could be converted into SSAT or USAT.
5271//
5272// SSAT can replace a set of two conditional selectors that bound a number to an
5273// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5274//
5275// x < -k ? -k : (x > k ? k : x)
5276// x < -k ? -k : (x < k ? x : k)
5277// x > -k ? (x > k ? k : x) : -k
5278// x < k ? (x < -k ? -k : x) : k
5279// etc.
5280//
5281// LLVM canonicalizes these to either a min(max()) or a max(min())
5282// pattern. This function tries to match one of these and will return a SSAT
5283// node if successful.
5284//
5285// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5286// is a power of 2.
5287static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5288 EVT VT = Op.getValueType();
5289 SDValue V1 = Op.getOperand(0);
5290 SDValue K1 = Op.getOperand(1);
5291 SDValue TrueVal1 = Op.getOperand(2);
5292 SDValue FalseVal1 = Op.getOperand(3);
5293 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5294
5295 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5296 if (Op2.getOpcode() != ISD::SELECT_CC)
5297 return SDValue();
5298
5299 SDValue V2 = Op2.getOperand(0);
5300 SDValue K2 = Op2.getOperand(1);
5301 SDValue TrueVal2 = Op2.getOperand(2);
5302 SDValue FalseVal2 = Op2.getOperand(3);
5303 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5304
5305 SDValue V1Tmp = V1;
5306 SDValue V2Tmp = V2;
5307
5308 // Check that the registers and the constants match a max(min()) or min(max())
5309 // pattern
5310 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5311 K2 != FalseVal2 ||
5312 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5313 return SDValue();
5314
5315 // Check that the constant in the lower-bound check is
5316 // the opposite of the constant in the upper-bound check
5317 // in 1's complement.
5318 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5319 return SDValue();
5320
5321 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5322 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5323 int64_t PosVal = std::max(Val1, Val2);
5324 int64_t NegVal = std::min(Val1, Val2);
5325
5326 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5327 !isPowerOf2_64(PosVal + 1))
5328 return SDValue();
5329
5330 // Handle the difference between USAT (unsigned) and SSAT (signed)
5331 // saturation
5332 // At this point, PosVal is guaranteed to be positive
5333 uint64_t K = PosVal;
5334 SDLoc dl(Op);
5335 if (Val1 == ~Val2)
5336 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5337 DAG.getConstant(countTrailingOnes(K), dl, VT));
5338 if (NegVal == 0)
5339 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5340 DAG.getConstant(countTrailingOnes(K), dl, VT));
5341
5342 return SDValue();
5343}
5344
5345// Check if a condition of the type x < k ? k : x can be converted into a
5346// bit operation instead of conditional moves.
5347// Currently this is allowed given:
5348// - The conditions and values match up
5349// - k is 0 or -1 (all ones)
5350// This function will not check the last condition, thats up to the caller
5351// It returns true if the transformation can be made, and in such case
5352// returns x in V, and k in SatK.
5353static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5354 SDValue &SatK)
5355{
5356 SDValue LHS = Op.getOperand(0);
5357 SDValue RHS = Op.getOperand(1);
5358 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5359 SDValue TrueVal = Op.getOperand(2);
5360 SDValue FalseVal = Op.getOperand(3);
5361
5362 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5363 ? &RHS
5364 : nullptr;
5365
5366 // No constant operation in comparison, early out
5367 if (!K)
5368 return false;
5369
5370 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5371 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5372 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5373
5374 // If the constant on left and right side, or variable on left and right,
5375 // does not match, early out
5376 if (*K != KTmp || V != VTmp)
5377 return false;
5378
5379 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5380 SatK = *K;
5381 return true;
5382 }
5383
5384 return false;
5385}
5386
5387bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5388 if (VT == MVT::f32)
5389 return !Subtarget->hasVFP2Base();
5390 if (VT == MVT::f64)
5391 return !Subtarget->hasFP64();
5392 if (VT == MVT::f16)
5393 return !Subtarget->hasFullFP16();
5394 return false;
5395}
5396
5397SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5398 EVT VT = Op.getValueType();
5399 SDLoc dl(Op);
5400
5401 // Try to convert two saturating conditional selects into a single SSAT
5402 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5403 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5404 return SatValue;
5405
5406 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5407 // into more efficient bit operations, which is possible when k is 0 or -1
5408 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5409 // single instructions. On Thumb the shift and the bit operation will be two
5410 // instructions.
5411 // Only allow this transformation on full-width (32-bit) operations
5412 SDValue LowerSatConstant;
5413 SDValue SatValue;
5414 if (VT == MVT::i32 &&
5415 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5416 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5417 DAG.getConstant(31, dl, VT));
5418 if (isNullConstant(LowerSatConstant)) {
5419 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5420 DAG.getAllOnesConstant(dl, VT));
5421 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5422 } else if (isAllOnesConstant(LowerSatConstant))
5423 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5424 }
5425
5426 SDValue LHS = Op.getOperand(0);
5427 SDValue RHS = Op.getOperand(1);
5428 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5429 SDValue TrueVal = Op.getOperand(2);
5430 SDValue FalseVal = Op.getOperand(3);
5431 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5432 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5433
5434 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5435 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5436 unsigned TVal = CTVal->getZExtValue();
5437 unsigned FVal = CFVal->getZExtValue();
5438 unsigned Opcode = 0;
5439
5440 if (TVal == ~FVal) {
5441 Opcode = ARMISD::CSINV;
5442 } else if (TVal == ~FVal + 1) {
5443 Opcode = ARMISD::CSNEG;
5444 } else if (TVal + 1 == FVal) {
5445 Opcode = ARMISD::CSINC;
5446 } else if (TVal == FVal + 1) {
5447 Opcode = ARMISD::CSINC;
5448 std::swap(TrueVal, FalseVal);
5449 std::swap(TVal, FVal);
5450 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5451 }
5452
5453 if (Opcode) {
5454 // If one of the constants is cheaper than another, materialise the
5455 // cheaper one and let the csel generate the other.
5456 if (Opcode != ARMISD::CSINC &&
5457 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5458 std::swap(TrueVal, FalseVal);
5459 std::swap(TVal, FVal);
5460 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5461 }
5462
5463 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5464 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5465 // -(-a) == a, but (a+1)+1 != a).
5466 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5467 std::swap(TrueVal, FalseVal);
5468 std::swap(TVal, FVal);
5469 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5470 }
5471
5472 // Drops F's value because we can get it by inverting/negating TVal.
5473 FalseVal = TrueVal;
5474
5475 SDValue ARMcc;
5476 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5477 EVT VT = TrueVal.getValueType();
5478 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5479 }
5480 }
5481
5482 if (isUnsupportedFloatingType(LHS.getValueType())) {
5483 DAG.getTargetLoweringInfo().softenSetCCOperands(
5484 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5485
5486 // If softenSetCCOperands only returned one value, we should compare it to
5487 // zero.
5488 if (!RHS.getNode()) {
5489 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5490 CC = ISD::SETNE;
5491 }
5492 }
5493
5494 if (LHS.getValueType() == MVT::i32) {
5495 // Try to generate VSEL on ARMv8.
5496 // The VSEL instruction can't use all the usual ARM condition
5497 // codes: it only has two bits to select the condition code, so it's
5498 // constrained to use only GE, GT, VS and EQ.
5499 //
5500 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5501 // swap the operands of the previous compare instruction (effectively
5502 // inverting the compare condition, swapping 'less' and 'greater') and
5503 // sometimes need to swap the operands to the VSEL (which inverts the
5504 // condition in the sense of firing whenever the previous condition didn't)
5505 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5506 TrueVal.getValueType() == MVT::f32 ||
5507 TrueVal.getValueType() == MVT::f64)) {
5508 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5509 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5510 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5511 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5512 std::swap(TrueVal, FalseVal);
5513 }
5514 }
5515
5516 SDValue ARMcc;
5517 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5518 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5519 // Choose GE over PL, which vsel does now support
5520 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5521 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5522 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5523 }
5524
5525 ARMCC::CondCodes CondCode, CondCode2;
5526 FPCCToARMCC(CC, CondCode, CondCode2);
5527
5528 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5529 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5530 // must use VSEL (limited condition codes), due to not having conditional f16
5531 // moves.
5532 if (Subtarget->hasFPARMv8Base() &&
5533 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5534 (TrueVal.getValueType() == MVT::f16 ||
5535 TrueVal.getValueType() == MVT::f32 ||
5536 TrueVal.getValueType() == MVT::f64)) {
5537 bool swpCmpOps = false;
5538 bool swpVselOps = false;
5539 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5540
5541 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5542 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5543 if (swpCmpOps)
5544 std::swap(LHS, RHS);
5545 if (swpVselOps)
5546 std::swap(TrueVal, FalseVal);
5547 }
5548 }
5549
5550 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5551 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5552 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5553 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5554 if (CondCode2 != ARMCC::AL) {
5555 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5556 // FIXME: Needs another CMP because flag can have but one use.
5557 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5558 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5559 }
5560 return Result;
5561}
5562
5563/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5564/// to morph to an integer compare sequence.
5565static bool canChangeToInt(SDValue Op, bool &SeenZero,
5566 const ARMSubtarget *Subtarget) {
5567 SDNode *N = Op.getNode();
5568 if (!N->hasOneUse())
5569 // Otherwise it requires moving the value from fp to integer registers.
5570 return false;
5571 if (!N->getNumValues())
5572 return false;
5573 EVT VT = Op.getValueType();
5574 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5575 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5576 // vmrs are very slow, e.g. cortex-a8.
5577 return false;
5578
5579 if (isFloatingPointZero(Op)) {
5580 SeenZero = true;
5581 return true;
5582 }
5583 return ISD::isNormalLoad(N);
5584}
5585
5586static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5587 if (isFloatingPointZero(Op))
5588 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5589
5590 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5591 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5592 Ld->getPointerInfo(), Ld->getAlign(),
5593 Ld->getMemOperand()->getFlags());
5594
5595 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5595)
;
5596}
5597
5598static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5599 SDValue &RetVal1, SDValue &RetVal2) {
5600 SDLoc dl(Op);
5601
5602 if (isFloatingPointZero(Op)) {
5603 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5604 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5605 return;
5606 }
5607
5608 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5609 SDValue Ptr = Ld->getBasePtr();
5610 RetVal1 =
5611 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5612 Ld->getAlign(), Ld->getMemOperand()->getFlags());
5613
5614 EVT PtrType = Ptr.getValueType();
5615 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5616 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5617 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5618 Ld->getPointerInfo().getWithOffset(4),
5619 commonAlignment(Ld->getAlign(), 4),
5620 Ld->getMemOperand()->getFlags());
5621 return;
5622 }
5623
5624 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5624)
;
5625}
5626
5627/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5628/// f32 and even f64 comparisons to integer ones.
5629SDValue
5630ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5631 SDValue Chain = Op.getOperand(0);
5632 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5633 SDValue LHS = Op.getOperand(2);
5634 SDValue RHS = Op.getOperand(3);
5635 SDValue Dest = Op.getOperand(4);
5636 SDLoc dl(Op);
5637
5638 bool LHSSeenZero = false;
5639 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5640 bool RHSSeenZero = false;
5641 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5642 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5643 // If unsafe fp math optimization is enabled and there are no other uses of
5644 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5645 // to an integer comparison.
5646 if (CC == ISD::SETOEQ)
5647 CC = ISD::SETEQ;
5648 else if (CC == ISD::SETUNE)
5649 CC = ISD::SETNE;
5650
5651 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5652 SDValue ARMcc;
5653 if (LHS.getValueType() == MVT::f32) {
5654 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5655 bitcastf32Toi32(LHS, DAG), Mask);
5656 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5657 bitcastf32Toi32(RHS, DAG), Mask);
5658 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5659 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5660 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5661 Chain, Dest, ARMcc, CCR, Cmp);
5662 }
5663
5664 SDValue LHS1, LHS2;
5665 SDValue RHS1, RHS2;
5666 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5667 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5668 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5669 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5670 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5671 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5672 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5673 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5674 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5675 }
5676
5677 return SDValue();
5678}
5679
5680SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5681 SDValue Chain = Op.getOperand(0);
5682 SDValue Cond = Op.getOperand(1);
5683 SDValue Dest = Op.getOperand(2);
5684 SDLoc dl(Op);
5685
5686 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5687 // instruction.
5688 unsigned Opc = Cond.getOpcode();
5689 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5690 !Subtarget->isThumb1Only();
5691 if (Cond.getResNo() == 1 &&
5692 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5693 Opc == ISD::USUBO || OptimizeMul)) {
5694 // Only lower legal XALUO ops.
5695 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5696 return SDValue();
5697
5698 // The actual operation with overflow check.
5699 SDValue Value, OverflowCmp;
5700 SDValue ARMcc;
5701 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5702
5703 // Reverse the condition code.
5704 ARMCC::CondCodes CondCode =
5705 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5706 CondCode = ARMCC::getOppositeCondition(CondCode);
5707 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5708 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5709
5710 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5711 OverflowCmp);
5712 }
5713
5714 return SDValue();
5715}
5716
5717SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5718 SDValue Chain = Op.getOperand(0);
5719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5720 SDValue LHS = Op.getOperand(2);
5721 SDValue RHS = Op.getOperand(3);
5722 SDValue Dest = Op.getOperand(4);
5723 SDLoc dl(Op);
5724
5725 if (isUnsupportedFloatingType(LHS.getValueType())) {
5726 DAG.getTargetLoweringInfo().softenSetCCOperands(
5727 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5728
5729 // If softenSetCCOperands only returned one value, we should compare it to
5730 // zero.
5731 if (!RHS.getNode()) {
5732 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5733 CC = ISD::SETNE;
5734 }
5735 }
5736
5737 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5738 // instruction.
5739 unsigned Opc = LHS.getOpcode();
5740 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5741 !Subtarget->isThumb1Only();
5742 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5743 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5744 Opc == ISD::USUBO || OptimizeMul) &&
5745 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5746 // Only lower legal XALUO ops.
5747 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5748 return SDValue();
5749
5750 // The actual operation with overflow check.
5751 SDValue Value, OverflowCmp;
5752 SDValue ARMcc;
5753 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5754
5755 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5756 // Reverse the condition code.
5757 ARMCC::CondCodes CondCode =
5758 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5759 CondCode = ARMCC::getOppositeCondition(CondCode);
5760 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5761 }
5762 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5763
5764 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5765 OverflowCmp);
5766 }
5767
5768 if (LHS.getValueType() == MVT::i32) {
5769 SDValue ARMcc;
5770 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5771 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5772 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5773 Chain, Dest, ARMcc, CCR, Cmp);
5774 }
5775
5776 if (getTargetMachine().Options.UnsafeFPMath &&
5777 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5778 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5779 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5780 return Result;
5781 }
5782
5783 ARMCC::CondCodes CondCode, CondCode2;
5784 FPCCToARMCC(CC, CondCode, CondCode2);
5785
5786 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5787 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5788 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5789 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5790 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5791 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5792 if (CondCode2 != ARMCC::AL) {
5793 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5794 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5795 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5796 }
5797 return Res;
5798}
5799
5800SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5801 SDValue Chain = Op.getOperand(0);
5802 SDValue Table = Op.getOperand(1);
5803 SDValue Index = Op.getOperand(2);
5804 SDLoc dl(Op);
5805
5806 EVT PTy = getPointerTy(DAG.getDataLayout());
5807 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5808 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5809 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5810 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5811 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5812 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5813 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5814 // which does another jump to the destination. This also makes it easier
5815 // to translate it to TBB / TBH later (Thumb2 only).
5816 // FIXME: This might not work if the function is extremely large.
5817 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5818 Addr, Op.getOperand(2), JTI);
5819 }
5820 if (isPositionIndependent() || Subtarget->isROPI()) {
5821 Addr =
5822 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5823 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5824 Chain = Addr.getValue(1);
5825 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5826 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5827 } else {
5828 Addr =
5829 DAG.getLoad(PTy, dl, Chain, Addr,
5830 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5831 Chain = Addr.getValue(1);
5832 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5833 }
5834}
5835
5836static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5837 EVT VT = Op.getValueType();
5838 SDLoc dl(Op);
5839
5840 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5841 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5842 return Op;
5843 return DAG.UnrollVectorOp(Op.getNode());
5844 }
5845
5846 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5847
5848 EVT NewTy;
5849 const EVT OpTy = Op.getOperand(0).getValueType();
5850 if (OpTy == MVT::v4f32)
5851 NewTy = MVT::v4i32;
5852 else if (OpTy == MVT::v4f16 && HasFullFP16)
5853 NewTy = MVT::v4i16;
5854 else if (OpTy == MVT::v8f16 && HasFullFP16)
5855 NewTy = MVT::v8i16;
5856 else
5857 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5857)
;
5858
5859 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5860 return DAG.UnrollVectorOp(Op.getNode());
5861
5862 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5863 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5864}
5865
5866SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5867 EVT VT = Op.getValueType();
5868 if (VT.isVector())
5869 return LowerVectorFP_TO_INT(Op, DAG);
5870
5871 bool IsStrict = Op->isStrictFPOpcode();
5872 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5873
5874 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5875 RTLIB::Libcall LC;
5876 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5877 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5878 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5879 Op.getValueType());
5880 else
5881 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5882 Op.getValueType());
5883 SDLoc Loc(Op);
5884 MakeLibCallOptions CallOptions;
5885 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5886 SDValue Result;
5887 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5888 CallOptions, Loc, Chain);
5889 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5890 }
5891
5892 // FIXME: Remove this when we have strict fp instruction selection patterns
5893 if (IsStrict) {
5894 SDLoc Loc(Op);
5895 SDValue Result =
5896 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5897 : ISD::FP_TO_UINT,
5898 Loc, Op.getValueType(), SrcVal);
5899 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5900 }
5901
5902 return Op;
5903}
5904
5905static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
5906 const ARMSubtarget *Subtarget) {
5907 EVT VT = Op.getValueType();
5908 EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5909 EVT FromVT = Op.getOperand(0).getValueType();
5910
5911 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f32)
5912 return Op;
5913 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f64 &&
5914 Subtarget->hasFP64())
5915 return Op;
5916 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f16 &&
5917 Subtarget->hasFullFP16())
5918 return Op;
5919 if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32 &&
5920 Subtarget->hasMVEFloatOps())
5921 return Op;
5922 if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16 &&
5923 Subtarget->hasMVEFloatOps())
5924 return Op;
5925
5926 if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
5927 return SDValue();
5928
5929 SDLoc DL(Op);
5930 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
5931 unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
5932 SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
5933 DAG.getValueType(VT.getScalarType()));
5934 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
5935 DAG.getConstant((1 << BW) - 1, DL, VT));
5936 if (IsSigned)
5937 Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
5938 DAG.getConstant(-(1 << BW), DL, VT));
5939 return Max;
5940}
5941
5942static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5943 EVT VT = Op.getValueType();
5944 SDLoc dl(Op);
5945
5946 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5947 if (VT.getVectorElementType() == MVT::f32)
5948 return Op;
5949 return DAG.UnrollVectorOp(Op.getNode());
5950 }
5951
5952 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5954, __extension__
__PRETTY_FUNCTION__))