Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 7032, column 14
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/ARM -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp -faddrsig
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/Type.h"
84#include "llvm/IR/User.h"
85#include "llvm/IR/Value.h"
86#include "llvm/MC/MCInstrDesc.h"
87#include "llvm/MC/MCInstrItineraries.h"
88#include "llvm/MC/MCRegisterInfo.h"
89#include "llvm/MC/MCSchedule.h"
90#include "llvm/Support/AtomicOrdering.h"
91#include "llvm/Support/BranchProbability.h"
92#include "llvm/Support/Casting.h"
93#include "llvm/Support/CodeGen.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/ErrorHandling.h"
98#include "llvm/Support/KnownBits.h"
99#include "llvm/Support/MachineValueType.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311 }
312
313 // These libcalls are not available in 32-bit.
314 setLibcallName(RTLIB::SHL_I128, nullptr);
315 setLibcallName(RTLIB::SRL_I128, nullptr);
316 setLibcallName(RTLIB::SRA_I128, nullptr);
317
318 // RTLIB
319 if (Subtarget->isAAPCS_ABI() &&
320 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
321 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
322 static const struct {
323 const RTLIB::Libcall Op;
324 const char * const Name;
325 const CallingConv::ID CC;
326 const ISD::CondCode Cond;
327 } LibraryCalls[] = {
328 // Double-precision floating-point arithmetic helper functions
329 // RTABI chapter 4.1.2, Table 2
330 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334
335 // Double-precision floating-point comparison helper functions
336 // RTABI chapter 4.1.2, Table 3
337 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
338 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
339 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
340 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
341 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
342 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
343 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
344 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
345
346 // Single-precision floating-point arithmetic helper functions
347 // RTABI chapter 4.1.2, Table 4
348 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352
353 // Single-precision floating-point comparison helper functions
354 // RTABI chapter 4.1.2, Table 5
355 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
356 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
357 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
358 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
359 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
360 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
361 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
362 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
363
364 // Floating-point to integer conversions.
365 // RTABI chapter 4.1.2, Table 6
366 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
368 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
369 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
371 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
372 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
373 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374
375 // Conversions between floating types.
376 // RTABI chapter 4.1.2, Table 7
377 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380
381 // Integer to floating-point conversions.
382 // RTABI chapter 4.1.2, Table 8
383 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
384 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
388 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
389 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
390 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391
392 // Long long helper functions
393 // RTABI chapter 4.2, Table 9
394 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Integer division functions
400 // RTABI chapter 4.3.1
401 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
406 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
407 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
408 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 };
410
411 for (const auto &LC : LibraryCalls) {
412 setLibcallName(LC.Op, LC.Name);
413 setLibcallCallingConv(LC.Op, LC.CC);
414 if (LC.Cond != ISD::SETCC_INVALID)
415 setCmpLibcallCC(LC.Op, LC.Cond);
416 }
417
418 // EABI dependent RTLIB
419 if (TM.Options.EABIVersion == EABI::EABI4 ||
420 TM.Options.EABIVersion == EABI::EABI5) {
421 static const struct {
422 const RTLIB::Libcall Op;
423 const char *const Name;
424 const CallingConv::ID CC;
425 const ISD::CondCode Cond;
426 } MemOpsLibraryCalls[] = {
427 // Memory operations
428 // RTABI chapter 4.3.4
429 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
430 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
431 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
432 };
433
434 for (const auto &LC : MemOpsLibraryCalls) {
435 setLibcallName(LC.Op, LC.Name);
436 setLibcallCallingConv(LC.Op, LC.CC);
437 if (LC.Cond != ISD::SETCC_INVALID)
438 setCmpLibcallCC(LC.Op, LC.Cond);
439 }
440 }
441 }
442
443 if (Subtarget->isTargetWindows()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const CallingConv::ID CC;
448 } LibraryCalls[] = {
449 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
450 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
451 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
452 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
453 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
454 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
455 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
456 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
457 };
458
459 for (const auto &LC : LibraryCalls) {
460 setLibcallName(LC.Op, LC.Name);
461 setLibcallCallingConv(LC.Op, LC.CC);
462 }
463 }
464
465 // Use divmod compiler-rt calls for iOS 5.0 and later.
466 if (Subtarget->isTargetMachO() &&
467 !(Subtarget->isTargetIOS() &&
468 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
469 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
470 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
471 }
472
473 // The half <-> float conversion functions are always soft-float on
474 // non-watchos platforms, but are needed for some targets which use a
475 // hard-float calling convention by default.
476 if (!Subtarget->isTargetWatchABI()) {
477 if (Subtarget->isAAPCS_ABI()) {
478 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
479 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
480 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
481 } else {
482 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
483 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
484 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
485 }
486 }
487
488 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
489 // a __gnu_ prefix (which is the default).
490 if (Subtarget->isTargetAEABI()) {
491 static const struct {
492 const RTLIB::Libcall Op;
493 const char * const Name;
494 const CallingConv::ID CC;
495 } LibraryCalls[] = {
496 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
497 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
498 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
499 };
500
501 for (const auto &LC : LibraryCalls) {
502 setLibcallName(LC.Op, LC.Name);
503 setLibcallCallingConv(LC.Op, LC.CC);
504 }
505 }
506
507 if (Subtarget->isThumb1Only())
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
509 else
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
511
512 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
513 !Subtarget->isThumb1Only()) {
514 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
515 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
516 }
517
518 if (Subtarget->hasFullFP16()) {
519 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
520 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
522 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
523
524 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
526 }
527
528 for (MVT VT : MVT::vector_valuetypes()) {
529 for (MVT InnerVT : MVT::vector_valuetypes()) {
530 setTruncStoreAction(VT, InnerVT, Expand);
531 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
532 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
533 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
534 }
535
536 setOperationAction(ISD::MULHS, VT, Expand);
537 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
538 setOperationAction(ISD::MULHU, VT, Expand);
539 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
540
541 setOperationAction(ISD::BSWAP, VT, Expand);
542 }
543
544 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
546
547 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
548 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
549
550 if (Subtarget->hasNEON()) {
551 addDRTypeForNEON(MVT::v2f32);
552 addDRTypeForNEON(MVT::v8i8);
553 addDRTypeForNEON(MVT::v4i16);
554 addDRTypeForNEON(MVT::v2i32);
555 addDRTypeForNEON(MVT::v1i64);
556
557 addQRTypeForNEON(MVT::v4f32);
558 addQRTypeForNEON(MVT::v2f64);
559 addQRTypeForNEON(MVT::v16i8);
560 addQRTypeForNEON(MVT::v8i16);
561 addQRTypeForNEON(MVT::v4i32);
562 addQRTypeForNEON(MVT::v2i64);
563
564 if (Subtarget->hasFullFP16()) {
565 addQRTypeForNEON(MVT::v8f16);
566 addDRTypeForNEON(MVT::v4f16);
567 }
568
569 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
570 // neither Neon nor VFP support any arithmetic operations on it.
571 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
572 // supported for v4f32.
573 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
574 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
575 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
576 // FIXME: Code duplication: FDIV and FREM are expanded always, see
577 // ARMTargetLowering::addTypeForNEON method for details.
578 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
580 // FIXME: Create unittest.
581 // In another words, find a way when "copysign" appears in DAG with vector
582 // operands.
583 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
584 // FIXME: Code duplication: SETCC has custom operation action, see
585 // ARMTargetLowering::addTypeForNEON method for details.
586 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
587 // FIXME: Create unittest for FNEG and for FABS.
588 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
589 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
591 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
593 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
596 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
599 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
600 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
601 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
602 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
604 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
605 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
606
607 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
608 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
610 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
613 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
616 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
617 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
618 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
621
622 // Mark v2f32 intrinsics.
623 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
624 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
626 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
629 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
632 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
633 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
634 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
636 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
637
638 // Neon does not support some operations on v1i64 and v2i64 types.
639 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
640 // Custom handling for some quad-vector types to detect VMULL.
641 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
642 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
643 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
644 // Custom handling for some vector types to avoid expensive expansions
645 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
646 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
647 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
648 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
649 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
650 // a destination type that is wider than the source, and nor does
651 // it have a FP_TO_[SU]INT instruction with a narrower destination than
652 // source.
653 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
655 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
656 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
657 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
658 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
659 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
660 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
661
662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
663 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
664
665 // NEON does not have single instruction CTPOP for vectors with element
666 // types wider than 8-bits. However, custom lowering can leverage the
667 // v8i8/v16i8 vcnt instruction.
668 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
670 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
671 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
672 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
673 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
674
675 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
676 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
677
678 // NEON does not have single instruction CTTZ for vectors.
679 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
683
684 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
685 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
686 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
687 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
688
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
693
694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
696 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
697 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
698
699 // NEON only has FMA instructions as of VFP4.
700 if (!Subtarget->hasVFP4()) {
701 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
702 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
703 }
704
705 setTargetDAGCombine(ISD::INTRINSIC_VOID);
706 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
707 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
708 setTargetDAGCombine(ISD::SHL);
709 setTargetDAGCombine(ISD::SRL);
710 setTargetDAGCombine(ISD::SRA);
711 setTargetDAGCombine(ISD::SIGN_EXTEND);
712 setTargetDAGCombine(ISD::ZERO_EXTEND);
713 setTargetDAGCombine(ISD::ANY_EXTEND);
714 setTargetDAGCombine(ISD::BUILD_VECTOR);
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
717 setTargetDAGCombine(ISD::STORE);
718 setTargetDAGCombine(ISD::FP_TO_SINT);
719 setTargetDAGCombine(ISD::FP_TO_UINT);
720 setTargetDAGCombine(ISD::FDIV);
721 setTargetDAGCombine(ISD::LOAD);
722
723 // It is legal to extload from v4i8 to v4i16 or v4i32.
724 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
725 MVT::v2i32}) {
726 for (MVT VT : MVT::integer_vector_valuetypes()) {
727 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
728 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
729 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
730 }
731 }
732 }
733
734 if (Subtarget->isFPOnlySP()) {
735 // When targeting a floating-point unit with only single-precision
736 // operations, f64 is legal for the few double-precision instructions which
737 // are present However, no double-precision operations other than moves,
738 // loads and stores are provided by the hardware.
739 setOperationAction(ISD::FADD, MVT::f64, Expand);
740 setOperationAction(ISD::FSUB, MVT::f64, Expand);
741 setOperationAction(ISD::FMUL, MVT::f64, Expand);
742 setOperationAction(ISD::FMA, MVT::f64, Expand);
743 setOperationAction(ISD::FDIV, MVT::f64, Expand);
744 setOperationAction(ISD::FREM, MVT::f64, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
747 setOperationAction(ISD::FNEG, MVT::f64, Expand);
748 setOperationAction(ISD::FABS, MVT::f64, Expand);
749 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
750 setOperationAction(ISD::FSIN, MVT::f64, Expand);
751 setOperationAction(ISD::FCOS, MVT::f64, Expand);
752 setOperationAction(ISD::FPOW, MVT::f64, Expand);
753 setOperationAction(ISD::FLOG, MVT::f64, Expand);
754 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
755 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
756 setOperationAction(ISD::FEXP, MVT::f64, Expand);
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
760 setOperationAction(ISD::FRINT, MVT::f64, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
762 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
766 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
768 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
770 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
771 }
772
773 computeRegisterProperties(Subtarget->getRegisterInfo());
774
775 // ARM does not have floating-point extending loads.
776 for (MVT VT : MVT::fp_valuetypes()) {
777 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
778 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
779 }
780
781 // ... or truncating stores
782 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
783 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
784 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
785
786 // ARM does not have i1 sign extending load.
787 for (MVT VT : MVT::integer_valuetypes())
788 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
789
790 // ARM supports all 4 flavors of integer indexed load / store.
791 if (!Subtarget->isThumb1Only()) {
792 for (unsigned im = (unsigned)ISD::PRE_INC;
793 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
794 setIndexedLoadAction(im, MVT::i1, Legal);
795 setIndexedLoadAction(im, MVT::i8, Legal);
796 setIndexedLoadAction(im, MVT::i16, Legal);
797 setIndexedLoadAction(im, MVT::i32, Legal);
798 setIndexedStoreAction(im, MVT::i1, Legal);
799 setIndexedStoreAction(im, MVT::i8, Legal);
800 setIndexedStoreAction(im, MVT::i16, Legal);
801 setIndexedStoreAction(im, MVT::i32, Legal);
802 }
803 } else {
804 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
805 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
806 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
807 }
808
809 setOperationAction(ISD::SADDO, MVT::i32, Custom);
810 setOperationAction(ISD::UADDO, MVT::i32, Custom);
811 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
812 setOperationAction(ISD::USUBO, MVT::i32, Custom);
813
814 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
815 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
816
817 // i64 operation support.
818 setOperationAction(ISD::MUL, MVT::i64, Expand);
819 setOperationAction(ISD::MULHU, MVT::i32, Expand);
820 if (Subtarget->isThumb1Only()) {
821 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
822 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
823 }
824 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
825 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
826 setOperationAction(ISD::MULHS, MVT::i32, Expand);
827
828 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
829 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
830 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
831 setOperationAction(ISD::SRL, MVT::i64, Custom);
832 setOperationAction(ISD::SRA, MVT::i64, Custom);
833 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
834
835 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
836 if (Subtarget->isThumb1Only()) {
837 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
838 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
839 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
840 }
841
842 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
844
845 // ARM does not have ROTL.
846 setOperationAction(ISD::ROTL, MVT::i32, Expand);
847 for (MVT VT : MVT::vector_valuetypes()) {
848 setOperationAction(ISD::ROTL, VT, Expand);
849 setOperationAction(ISD::ROTR, VT, Expand);
850 }
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
853 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
856 }
857
858 // @llvm.readcyclecounter requires the Performance Monitors extension.
859 // Default to the 0 expansion on unsupported platforms.
860 // FIXME: Technically there are older ARM CPUs that have
861 // implementation-specific ways of obtaining this information.
862 if (Subtarget->hasPerfMon())
863 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
864
865 // Only ARMv6 has BSWAP.
866 if (!Subtarget->hasV6Ops())
867 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
868
869 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
870 : Subtarget->hasDivideInARMMode();
871 if (!hasDivide) {
872 // These are expanded into libcalls if the cpu doesn't have HW divider.
873 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
874 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
875 }
876
877 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
878 setOperationAction(ISD::SDIV, MVT::i32, Custom);
879 setOperationAction(ISD::UDIV, MVT::i32, Custom);
880
881 setOperationAction(ISD::SDIV, MVT::i64, Custom);
882 setOperationAction(ISD::UDIV, MVT::i64, Custom);
883 }
884
885 setOperationAction(ISD::SREM, MVT::i32, Expand);
886 setOperationAction(ISD::UREM, MVT::i32, Expand);
887
888 // Register based DivRem for AEABI (RTABI 4.2)
889 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
890 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
891 Subtarget->isTargetWindows()) {
892 setOperationAction(ISD::SREM, MVT::i64, Custom);
893 setOperationAction(ISD::UREM, MVT::i64, Custom);
894 HasStandaloneRem = false;
895
896 if (Subtarget->isTargetWindows()) {
897 const struct {
898 const RTLIB::Libcall Op;
899 const char * const Name;
900 const CallingConv::ID CC;
901 } LibraryCalls[] = {
902 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
903 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
904 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
905 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
906
907 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
908 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
909 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
910 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
911 };
912
913 for (const auto &LC : LibraryCalls) {
914 setLibcallName(LC.Op, LC.Name);
915 setLibcallCallingConv(LC.Op, LC.CC);
916 }
917 } else {
918 const struct {
919 const RTLIB::Libcall Op;
920 const char * const Name;
921 const CallingConv::ID CC;
922 } LibraryCalls[] = {
923 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
925 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
926 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
927
928 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
930 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
931 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
932 };
933
934 for (const auto &LC : LibraryCalls) {
935 setLibcallName(LC.Op, LC.Name);
936 setLibcallCallingConv(LC.Op, LC.CC);
937 }
938 }
939
940 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
941 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
942 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
943 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
944 } else {
945 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
946 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
947 }
948
949 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
950 for (auto &VT : {MVT::f32, MVT::f64})
951 setOperationAction(ISD::FPOWI, VT, Custom);
952
953 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
954 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
955 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
956 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
957
958 setOperationAction(ISD::TRAP, MVT::Other, Legal);
959 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
960
961 // Use the default implementation.
962 setOperationAction(ISD::VASTART, MVT::Other, Custom);
963 setOperationAction(ISD::VAARG, MVT::Other, Expand);
964 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
965 setOperationAction(ISD::VAEND, MVT::Other, Expand);
966 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
967 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
968
969 if (Subtarget->isTargetWindows())
970 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
971 else
972 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
973
974 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
975 // the default expansion.
976 InsertFencesForAtomic = false;
977 if (Subtarget->hasAnyDataBarrier() &&
978 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
979 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
980 // to ldrex/strex loops already.
981 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
982 if (!Subtarget->isThumb() || !Subtarget->isMClass())
983 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
984
985 // On v8, we have particularly efficient implementations of atomic fences
986 // if they can be combined with nearby atomic loads and stores.
987 if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
988 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
989 InsertFencesForAtomic = true;
990 }
991 } else {
992 // If there's anything we can use as a barrier, go through custom lowering
993 // for ATOMIC_FENCE.
994 // If target has DMB in thumb, Fences can be inserted.
995 if (Subtarget->hasDataBarrier())
996 InsertFencesForAtomic = true;
997
998 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
999 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1000
1001 // Set them all for expansion, which will force libcalls.
1002 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1003 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1011 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1012 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1013 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1014 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1015 // Unordered/Monotonic case.
1016 if (!InsertFencesForAtomic) {
1017 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1018 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1019 }
1020 }
1021
1022 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1023
1024 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1025 if (!Subtarget->hasV6Ops()) {
1026 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1027 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1028 }
1029 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1030
1031 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1032 !Subtarget->isThumb1Only()) {
1033 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1034 // iff target supports vfp2.
1035 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1036 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1037 }
1038
1039 // We want to custom lower some of our intrinsics.
1040 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1041 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1042 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1043 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1044 if (Subtarget->useSjLjEH())
1045 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1046
1047 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1048 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1049 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1050 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1051 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1052 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1053 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1054 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1055 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1056 if (Subtarget->hasFullFP16()) {
1057 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1058 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1059 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1060 }
1061
1062 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1063
1064 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1065 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1066 if (Subtarget->hasFullFP16())
1067 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1068 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1069 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1070 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1071
1072 // We don't support sin/cos/fmod/copysign/pow
1073 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1074 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1075 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1076 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1077 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1078 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1079 setOperationAction(ISD::FREM, MVT::f64, Expand);
1080 setOperationAction(ISD::FREM, MVT::f32, Expand);
1081 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1082 !Subtarget->isThumb1Only()) {
1083 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1084 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1085 }
1086 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1087 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1088
1089 if (!Subtarget->hasVFP4()) {
1090 setOperationAction(ISD::FMA, MVT::f64, Expand);
1091 setOperationAction(ISD::FMA, MVT::f32, Expand);
1092 }
1093
1094 // Various VFP goodness
1095 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1096 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1097 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1098 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1099 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1100 }
1101
1102 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1103 if (!Subtarget->hasFP16()) {
1104 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1105 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1106 }
1107 }
1108
1109 // Use __sincos_stret if available.
1110 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1111 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1112 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1113 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1114 }
1115
1116 // FP-ARMv8 implements a lot of rounding-like FP operations.
1117 if (Subtarget->hasFPARMv8()) {
1118 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1120 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1121 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1122 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1123 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1124 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1125 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1126 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1127 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1128 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1129 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1130
1131 if (!Subtarget->isFPOnlySP()) {
1132 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1134 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1137 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1138 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1139 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1140 }
1141 }
1142
1143 if (Subtarget->hasNEON()) {
1144 // vmin and vmax aren't available in a scalar form, so we use
1145 // a NEON instruction with an undef lane instead.
1146 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1147 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1148 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1149 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1150 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1151 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1152 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1153 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1154
1155 if (Subtarget->hasFullFP16()) {
1156 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1157 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1158 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1159 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1160
1161 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1162 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1163 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1164 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1165 }
1166 }
1167
1168 // We have target-specific dag combine patterns for the following nodes:
1169 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1170 setTargetDAGCombine(ISD::ADD);
1171 setTargetDAGCombine(ISD::SUB);
1172 setTargetDAGCombine(ISD::MUL);
1173 setTargetDAGCombine(ISD::AND);
1174 setTargetDAGCombine(ISD::OR);
1175 setTargetDAGCombine(ISD::XOR);
1176
1177 if (Subtarget->hasV6Ops())
1178 setTargetDAGCombine(ISD::SRL);
1179
1180 setStackPointerRegisterToSaveRestore(ARM::SP);
1181
1182 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1183 !Subtarget->hasVFP2())
1184 setSchedulingPreference(Sched::RegPressure);
1185 else
1186 setSchedulingPreference(Sched::Hybrid);
1187
1188 //// temporary - rewrite interface to use type
1189 MaxStoresPerMemset = 8;
1190 MaxStoresPerMemsetOptSize = 4;
1191 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1192 MaxStoresPerMemcpyOptSize = 2;
1193 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1194 MaxStoresPerMemmoveOptSize = 2;
1195
1196 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1197 // are at least 4 bytes aligned.
1198 setMinStackArgumentAlignment(4);
1199
1200 // Prefer likely predicted branches to selects on out-of-order cores.
1201 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1202
1203 setPrefLoopAlignment(Subtarget->getPrefLoopAlignment());
1204
1205 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1206}
1207
1208bool ARMTargetLowering::useSoftFloat() const {
1209 return Subtarget->useSoftFloat();
1210}
1211
1212// FIXME: It might make sense to define the representative register class as the
1213// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1214// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1215// SPR's representative would be DPR_VFP2. This should work well if register
1216// pressure tracking were modified such that a register use would increment the
1217// pressure of the register class's representative and all of it's super
1218// classes' representatives transitively. We have not implemented this because
1219// of the difficulty prior to coalescing of modeling operand register classes
1220// due to the common occurrence of cross class copies and subregister insertions
1221// and extractions.
1222std::pair<const TargetRegisterClass *, uint8_t>
1223ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1224 MVT VT) const {
1225 const TargetRegisterClass *RRC = nullptr;
1226 uint8_t Cost = 1;
1227 switch (VT.SimpleTy) {
1228 default:
1229 return TargetLowering::findRepresentativeClass(TRI, VT);
1230 // Use DPR as representative register class for all floating point
1231 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1232 // the cost is 1 for both f32 and f64.
1233 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1234 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1235 RRC = &ARM::DPRRegClass;
1236 // When NEON is used for SP, only half of the register file is available
1237 // because operations that define both SP and DP results will be constrained
1238 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1239 // coalescing by double-counting the SP regs. See the FIXME above.
1240 if (Subtarget->useNEONForSinglePrecisionFP())
1241 Cost = 2;
1242 break;
1243 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1244 case MVT::v4f32: case MVT::v2f64:
1245 RRC = &ARM::DPRRegClass;
1246 Cost = 2;
1247 break;
1248 case MVT::v4i64:
1249 RRC = &ARM::DPRRegClass;
1250 Cost = 4;
1251 break;
1252 case MVT::v8i64:
1253 RRC = &ARM::DPRRegClass;
1254 Cost = 8;
1255 break;
1256 }
1257 return std::make_pair(RRC, Cost);
1258}
1259
1260const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1261 switch ((ARMISD::NodeType)Opcode) {
1262 case ARMISD::FIRST_NUMBER: break;
1263 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1264 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1265 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1266 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1267 case ARMISD::CALL: return "ARMISD::CALL";
1268 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1269 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1270 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1271 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1272 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1273 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1274 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1275 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1276 case ARMISD::CMP: return "ARMISD::CMP";
1277 case ARMISD::CMN: return "ARMISD::CMN";
1278 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1279 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1280 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1281 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1282 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1283
1284 case ARMISD::CMOV: return "ARMISD::CMOV";
1285
1286 case ARMISD::SSAT: return "ARMISD::SSAT";
1287 case ARMISD::USAT: return "ARMISD::USAT";
1288
1289 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1290 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1291 case ARMISD::RRX: return "ARMISD::RRX";
1292
1293 case ARMISD::ADDC: return "ARMISD::ADDC";
1294 case ARMISD::ADDE: return "ARMISD::ADDE";
1295 case ARMISD::SUBC: return "ARMISD::SUBC";
1296 case ARMISD::SUBE: return "ARMISD::SUBE";
1297
1298 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1299 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1300 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1301 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1302 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1303
1304 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1305 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1306 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1307
1308 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1309
1310 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1311
1312 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1313
1314 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1315
1316 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1317
1318 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1319 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1320
1321 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1322 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1323 case ARMISD::VCGE: return "ARMISD::VCGE";
1324 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1325 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1326 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1327 case ARMISD::VCGT: return "ARMISD::VCGT";
1328 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1329 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1330 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1331 case ARMISD::VTST: return "ARMISD::VTST";
1332
1333 case ARMISD::VSHL: return "ARMISD::VSHL";
1334 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1335 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1336 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1337 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1338 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1339 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1340 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1341 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1342 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1343 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1344 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1345 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1346 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1347 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1348 case ARMISD::VSLI: return "ARMISD::VSLI";
1349 case ARMISD::VSRI: return "ARMISD::VSRI";
1350 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1351 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1352 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1353 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1354 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1355 case ARMISD::VDUP: return "ARMISD::VDUP";
1356 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1357 case ARMISD::VEXT: return "ARMISD::VEXT";
1358 case ARMISD::VREV64: return "ARMISD::VREV64";
1359 case ARMISD::VREV32: return "ARMISD::VREV32";
1360 case ARMISD::VREV16: return "ARMISD::VREV16";
1361 case ARMISD::VZIP: return "ARMISD::VZIP";
1362 case ARMISD::VUZP: return "ARMISD::VUZP";
1363 case ARMISD::VTRN: return "ARMISD::VTRN";
1364 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1365 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1366 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1367 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1368 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1369 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1370 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1371 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1372 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1373 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1374 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1375 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1376 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1377 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1378 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1379 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1380 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1381 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1382 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1383 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1384 case ARMISD::BFI: return "ARMISD::BFI";
1385 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1386 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1387 case ARMISD::VBSL: return "ARMISD::VBSL";
1388 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1389 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1390 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1391 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1392 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1393 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1394 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1395 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1396 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1397 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1398 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1399 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1400 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1401 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1402 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1403 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1404 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1405 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1406 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1407 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1408 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1409 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1410 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1411 }
1412 return nullptr;
1413}
1414
1415EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1416 EVT VT) const {
1417 if (!VT.isVector())
1418 return getPointerTy(DL);
1419 return VT.changeVectorElementTypeToInteger();
1420}
1421
1422/// getRegClassFor - Return the register class that should be used for the
1423/// specified value type.
1424const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1425 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1426 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1427 // load / store 4 to 8 consecutive D registers.
1428 if (Subtarget->hasNEON()) {
1429 if (VT == MVT::v4i64)
1430 return &ARM::QQPRRegClass;
1431 if (VT == MVT::v8i64)
1432 return &ARM::QQQQPRRegClass;
1433 }
1434 return TargetLowering::getRegClassFor(VT);
1435}
1436
1437// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1438// source/dest is aligned and the copy size is large enough. We therefore want
1439// to align such objects passed to memory intrinsics.
1440bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1441 unsigned &PrefAlign) const {
1442 if (!isa<MemIntrinsic>(CI))
1443 return false;
1444 MinSize = 8;
1445 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1446 // cycle faster than 4-byte aligned LDM.
1447 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1448 return true;
1449}
1450
1451// Create a fast isel object.
1452FastISel *
1453ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1454 const TargetLibraryInfo *libInfo) const {
1455 return ARM::createFastISel(funcInfo, libInfo);
1456}
1457
1458Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1459 unsigned NumVals = N->getNumValues();
1460 if (!NumVals)
1461 return Sched::RegPressure;
1462
1463 for (unsigned i = 0; i != NumVals; ++i) {
1464 EVT VT = N->getValueType(i);
1465 if (VT == MVT::Glue || VT == MVT::Other)
1466 continue;
1467 if (VT.isFloatingPoint() || VT.isVector())
1468 return Sched::ILP;
1469 }
1470
1471 if (!N->isMachineOpcode())
1472 return Sched::RegPressure;
1473
1474 // Load are scheduled for latency even if there instruction itinerary
1475 // is not available.
1476 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1477 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1478
1479 if (MCID.getNumDefs() == 0)
1480 return Sched::RegPressure;
1481 if (!Itins->isEmpty() &&
1482 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1483 return Sched::ILP;
1484
1485 return Sched::RegPressure;
1486}
1487
1488//===----------------------------------------------------------------------===//
1489// Lowering Code
1490//===----------------------------------------------------------------------===//
1491
1492static bool isSRL16(const SDValue &Op) {
1493 if (Op.getOpcode() != ISD::SRL)
1494 return false;
1495 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1496 return Const->getZExtValue() == 16;
1497 return false;
1498}
1499
1500static bool isSRA16(const SDValue &Op) {
1501 if (Op.getOpcode() != ISD::SRA)
1502 return false;
1503 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1504 return Const->getZExtValue() == 16;
1505 return false;
1506}
1507
1508static bool isSHL16(const SDValue &Op) {
1509 if (Op.getOpcode() != ISD::SHL)
1510 return false;
1511 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1512 return Const->getZExtValue() == 16;
1513 return false;
1514}
1515
1516// Check for a signed 16-bit value. We special case SRA because it makes it
1517// more simple when also looking for SRAs that aren't sign extending a
1518// smaller value. Without the check, we'd need to take extra care with
1519// checking order for some operations.
1520static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1521 if (isSRA16(Op))
1522 return isSHL16(Op.getOperand(0));
1523 return DAG.ComputeNumSignBits(Op) == 17;
1524}
1525
1526/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1527static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1528 switch (CC) {
1529 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1529)
;
1530 case ISD::SETNE: return ARMCC::NE;
1531 case ISD::SETEQ: return ARMCC::EQ;
1532 case ISD::SETGT: return ARMCC::GT;
1533 case ISD::SETGE: return ARMCC::GE;
1534 case ISD::SETLT: return ARMCC::LT;
1535 case ISD::SETLE: return ARMCC::LE;
1536 case ISD::SETUGT: return ARMCC::HI;
1537 case ISD::SETUGE: return ARMCC::HS;
1538 case ISD::SETULT: return ARMCC::LO;
1539 case ISD::SETULE: return ARMCC::LS;
1540 }
1541}
1542
1543/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1544static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1545 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1546 CondCode2 = ARMCC::AL;
1547 InvalidOnQNaN = true;
1548 switch (CC) {
1549 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1549)
;
1550 case ISD::SETEQ:
1551 case ISD::SETOEQ:
1552 CondCode = ARMCC::EQ;
1553 InvalidOnQNaN = false;
1554 break;
1555 case ISD::SETGT:
1556 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1557 case ISD::SETGE:
1558 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1559 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1560 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1561 case ISD::SETONE:
1562 CondCode = ARMCC::MI;
1563 CondCode2 = ARMCC::GT;
1564 InvalidOnQNaN = false;
1565 break;
1566 case ISD::SETO: CondCode = ARMCC::VC; break;
1567 case ISD::SETUO: CondCode = ARMCC::VS; break;
1568 case ISD::SETUEQ:
1569 CondCode = ARMCC::EQ;
1570 CondCode2 = ARMCC::VS;
1571 InvalidOnQNaN = false;
1572 break;
1573 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1574 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1575 case ISD::SETLT:
1576 case ISD::SETULT: CondCode = ARMCC::LT; break;
1577 case ISD::SETLE:
1578 case ISD::SETULE: CondCode = ARMCC::LE; break;
1579 case ISD::SETNE:
1580 case ISD::SETUNE:
1581 CondCode = ARMCC::NE;
1582 InvalidOnQNaN = false;
1583 break;
1584 }
1585}
1586
1587//===----------------------------------------------------------------------===//
1588// Calling Convention Implementation
1589//===----------------------------------------------------------------------===//
1590
1591#include "ARMGenCallingConv.inc"
1592
1593/// getEffectiveCallingConv - Get the effective calling convention, taking into
1594/// account presence of floating point hardware and calling convention
1595/// limitations, such as support for variadic functions.
1596CallingConv::ID
1597ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1598 bool isVarArg) const {
1599 switch (CC) {
1600 default:
1601 report_fatal_error("Unsupported calling convention");
1602 case CallingConv::ARM_AAPCS:
1603 case CallingConv::ARM_APCS:
1604 case CallingConv::GHC:
1605 return CC;
1606 case CallingConv::PreserveMost:
1607 return CallingConv::PreserveMost;
1608 case CallingConv::ARM_AAPCS_VFP:
1609 case CallingConv::Swift:
1610 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1611 case CallingConv::C:
1612 if (!Subtarget->isAAPCS_ABI())
1613 return CallingConv::ARM_APCS;
1614 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1615 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1616 !isVarArg)
1617 return CallingConv::ARM_AAPCS_VFP;
1618 else
1619 return CallingConv::ARM_AAPCS;
1620 case CallingConv::Fast:
1621 case CallingConv::CXX_FAST_TLS:
1622 if (!Subtarget->isAAPCS_ABI()) {
1623 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1624 return CallingConv::Fast;
1625 return CallingConv::ARM_APCS;
1626 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1627 return CallingConv::ARM_AAPCS_VFP;
1628 else
1629 return CallingConv::ARM_AAPCS;
1630 }
1631}
1632
1633CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1634 bool isVarArg) const {
1635 return CCAssignFnForNode(CC, false, isVarArg);
1636}
1637
1638CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1639 bool isVarArg) const {
1640 return CCAssignFnForNode(CC, true, isVarArg);
1641}
1642
1643/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1644/// CallingConvention.
1645CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1646 bool Return,
1647 bool isVarArg) const {
1648 switch (getEffectiveCallingConv(CC, isVarArg)) {
1649 default:
1650 report_fatal_error("Unsupported calling convention");
1651 case CallingConv::ARM_APCS:
1652 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1653 case CallingConv::ARM_AAPCS:
1654 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1655 case CallingConv::ARM_AAPCS_VFP:
1656 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1657 case CallingConv::Fast:
1658 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1659 case CallingConv::GHC:
1660 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1661 case CallingConv::PreserveMost:
1662 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1663 }
1664}
1665
1666/// LowerCallResult - Lower the result values of a call into the
1667/// appropriate copies out of appropriate physical registers.
1668SDValue ARMTargetLowering::LowerCallResult(
1669 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1670 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1671 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1672 SDValue ThisVal) const {
1673 // Assign locations to each value returned by this call.
1674 SmallVector<CCValAssign, 16> RVLocs;
1675 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1676 *DAG.getContext());
1677 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1678
1679 // Copy all of the result registers out of their specified physreg.
1680 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1681 CCValAssign VA = RVLocs[i];
1682
1683 // Pass 'this' value directly from the argument to return value, to avoid
1684 // reg unit interference
1685 if (i == 0 && isThisReturn) {
1686 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1687, __PRETTY_FUNCTION__))
1687 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1687, __PRETTY_FUNCTION__))
;
1688 InVals.push_back(ThisVal);
1689 continue;
1690 }
1691
1692 SDValue Val;
1693 if (VA.needsCustom()) {
1694 // Handle f64 or half of a v2f64.
1695 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1696 InFlag);
1697 Chain = Lo.getValue(1);
1698 InFlag = Lo.getValue(2);
1699 VA = RVLocs[++i]; // skip ahead to next loc
1700 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1701 InFlag);
1702 Chain = Hi.getValue(1);
1703 InFlag = Hi.getValue(2);
1704 if (!Subtarget->isLittle())
1705 std::swap (Lo, Hi);
1706 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1707
1708 if (VA.getLocVT() == MVT::v2f64) {
1709 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1710 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1711 DAG.getConstant(0, dl, MVT::i32));
1712
1713 VA = RVLocs[++i]; // skip ahead to next loc
1714 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1715 Chain = Lo.getValue(1);
1716 InFlag = Lo.getValue(2);
1717 VA = RVLocs[++i]; // skip ahead to next loc
1718 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1719 Chain = Hi.getValue(1);
1720 InFlag = Hi.getValue(2);
1721 if (!Subtarget->isLittle())
1722 std::swap (Lo, Hi);
1723 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1724 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1725 DAG.getConstant(1, dl, MVT::i32));
1726 }
1727 } else {
1728 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1729 InFlag);
1730 Chain = Val.getValue(1);
1731 InFlag = Val.getValue(2);
1732 }
1733
1734 switch (VA.getLocInfo()) {
1735 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1735)
;
1736 case CCValAssign::Full: break;
1737 case CCValAssign::BCvt:
1738 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1739 break;
1740 }
1741
1742 InVals.push_back(Val);
1743 }
1744
1745 return Chain;
1746}
1747
1748/// LowerMemOpCallTo - Store the argument to the stack.
1749SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1750 SDValue Arg, const SDLoc &dl,
1751 SelectionDAG &DAG,
1752 const CCValAssign &VA,
1753 ISD::ArgFlagsTy Flags) const {
1754 unsigned LocMemOffset = VA.getLocMemOffset();
1755 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1756 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1757 StackPtr, PtrOff);
1758 return DAG.getStore(
1759 Chain, dl, Arg, PtrOff,
1760 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1761}
1762
1763void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1764 SDValue Chain, SDValue &Arg,
1765 RegsToPassVector &RegsToPass,
1766 CCValAssign &VA, CCValAssign &NextVA,
1767 SDValue &StackPtr,
1768 SmallVectorImpl<SDValue> &MemOpChains,
1769 ISD::ArgFlagsTy Flags) const {
1770 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1771 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1772 unsigned id = Subtarget->isLittle() ? 0 : 1;
1773 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1774
1775 if (NextVA.isRegLoc())
1776 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1777 else {
1778 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1778, __PRETTY_FUNCTION__))
;
1779 if (!StackPtr.getNode())
1780 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1781 getPointerTy(DAG.getDataLayout()));
1782
1783 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1784 dl, DAG, NextVA,
1785 Flags));
1786 }
1787}
1788
1789/// LowerCall - Lowering a call into a callseq_start <-
1790/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1791/// nodes.
1792SDValue
1793ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1794 SmallVectorImpl<SDValue> &InVals) const {
1795 SelectionDAG &DAG = CLI.DAG;
1796 SDLoc &dl = CLI.DL;
1797 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1798 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1799 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1800 SDValue Chain = CLI.Chain;
1801 SDValue Callee = CLI.Callee;
1802 bool &isTailCall = CLI.IsTailCall;
1803 CallingConv::ID CallConv = CLI.CallConv;
1804 bool doesNotRet = CLI.DoesNotReturn;
1805 bool isVarArg = CLI.IsVarArg;
1806
1807 MachineFunction &MF = DAG.getMachineFunction();
1808 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1809 bool isThisReturn = false;
1810 bool isSibCall = false;
1811 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1812
1813 // Disable tail calls if they're not supported.
1814 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1815 isTailCall = false;
1816
1817 if (isTailCall) {
1818 // Check if it's really possible to do a tail call.
1819 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1820 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1821 Outs, OutVals, Ins, DAG);
1822 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1823 report_fatal_error("failed to perform tail call elimination on a call "
1824 "site marked musttail");
1825 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1826 // detected sibcalls.
1827 if (isTailCall) {
1828 ++NumTailCalls;
1829 isSibCall = true;
1830 }
1831 }
1832
1833 // Analyze operands of the call, assigning locations to each operand.
1834 SmallVector<CCValAssign, 16> ArgLocs;
1835 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1836 *DAG.getContext());
1837 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1838
1839 // Get a count of how many bytes are to be pushed on the stack.
1840 unsigned NumBytes = CCInfo.getNextStackOffset();
1841
1842 // For tail calls, memory operands are available in our caller's stack.
1843 if (isSibCall)
1844 NumBytes = 0;
1845
1846 // Adjust the stack pointer for the new arguments...
1847 // These operations are automatically eliminated by the prolog/epilog pass
1848 if (!isSibCall)
1849 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1850
1851 SDValue StackPtr =
1852 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1853
1854 RegsToPassVector RegsToPass;
1855 SmallVector<SDValue, 8> MemOpChains;
1856
1857 // Walk the register/memloc assignments, inserting copies/loads. In the case
1858 // of tail call optimization, arguments are handled later.
1859 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1860 i != e;
1861 ++i, ++realArgIdx) {
1862 CCValAssign &VA = ArgLocs[i];
1863 SDValue Arg = OutVals[realArgIdx];
1864 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1865 bool isByVal = Flags.isByVal();
1866
1867 // Promote the value if needed.
1868 switch (VA.getLocInfo()) {
1869 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1869)
;
1870 case CCValAssign::Full: break;
1871 case CCValAssign::SExt:
1872 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1873 break;
1874 case CCValAssign::ZExt:
1875 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1876 break;
1877 case CCValAssign::AExt:
1878 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1879 break;
1880 case CCValAssign::BCvt:
1881 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1882 break;
1883 }
1884
1885 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1886 if (VA.needsCustom()) {
1887 if (VA.getLocVT() == MVT::v2f64) {
1888 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1889 DAG.getConstant(0, dl, MVT::i32));
1890 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1891 DAG.getConstant(1, dl, MVT::i32));
1892
1893 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1894 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1895
1896 VA = ArgLocs[++i]; // skip ahead to next loc
1897 if (VA.isRegLoc()) {
1898 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1899 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1900 } else {
1901 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1901, __PRETTY_FUNCTION__))
;
1902
1903 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1904 dl, DAG, VA, Flags));
1905 }
1906 } else {
1907 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1908 StackPtr, MemOpChains, Flags);
1909 }
1910 } else if (VA.isRegLoc()) {
1911 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1912 Outs[0].VT == MVT::i32) {
1913 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1914, __PRETTY_FUNCTION__))
1914 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1914, __PRETTY_FUNCTION__))
;
1915 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1916, __PRETTY_FUNCTION__))
1916 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1916, __PRETTY_FUNCTION__))
;
1917 isThisReturn = true;
1918 }
1919 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1920 } else if (isByVal) {
1921 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1921, __PRETTY_FUNCTION__))
;
1922 unsigned offset = 0;
1923
1924 // True if this byval aggregate will be split between registers
1925 // and memory.
1926 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1927 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1928
1929 if (CurByValIdx < ByValArgsCount) {
1930
1931 unsigned RegBegin, RegEnd;
1932 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1933
1934 EVT PtrVT =
1935 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1936 unsigned int i, j;
1937 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1938 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1939 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1940 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1941 MachinePointerInfo(),
1942 DAG.InferPtrAlignment(AddArg));
1943 MemOpChains.push_back(Load.getValue(1));
1944 RegsToPass.push_back(std::make_pair(j, Load));
1945 }
1946
1947 // If parameter size outsides register area, "offset" value
1948 // helps us to calculate stack slot for remained part properly.
1949 offset = RegEnd - RegBegin;
1950
1951 CCInfo.nextInRegsParam();
1952 }
1953
1954 if (Flags.getByValSize() > 4*offset) {
1955 auto PtrVT = getPointerTy(DAG.getDataLayout());
1956 unsigned LocMemOffset = VA.getLocMemOffset();
1957 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1958 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1959 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1960 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1961 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1962 MVT::i32);
1963 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1964 MVT::i32);
1965
1966 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1967 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1968 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1969 Ops));
1970 }
1971 } else if (!isSibCall) {
1972 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 1972, __PRETTY_FUNCTION__))
;
1973
1974 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1975 dl, DAG, VA, Flags));
1976 }
1977 }
1978
1979 if (!MemOpChains.empty())
1980 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1981
1982 // Build a sequence of copy-to-reg nodes chained together with token chain
1983 // and flag operands which copy the outgoing args into the appropriate regs.
1984 SDValue InFlag;
1985 // Tail call byval lowering might overwrite argument registers so in case of
1986 // tail call optimization the copies to registers are lowered later.
1987 if (!isTailCall)
1988 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1989 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1990 RegsToPass[i].second, InFlag);
1991 InFlag = Chain.getValue(1);
1992 }
1993
1994 // For tail calls lower the arguments to the 'real' stack slot.
1995 if (isTailCall) {
1996 // Force all the incoming stack arguments to be loaded from the stack
1997 // before any new outgoing arguments are stored to the stack, because the
1998 // outgoing stack slots may alias the incoming argument stack slots, and
1999 // the alias isn't otherwise explicit. This is slightly more conservative
2000 // than necessary, because it means that each store effectively depends
2001 // on every argument instead of just those arguments it would clobber.
2002
2003 // Do not flag preceding copytoreg stuff together with the following stuff.
2004 InFlag = SDValue();
2005 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2006 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2007 RegsToPass[i].second, InFlag);
2008 InFlag = Chain.getValue(1);
2009 }
2010 InFlag = SDValue();
2011 }
2012
2013 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2014 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2015 // node so that legalize doesn't hack it.
2016 bool isDirect = false;
2017
2018 const TargetMachine &TM = getTargetMachine();
2019 const Module *Mod = MF.getFunction().getParent();
2020 const GlobalValue *GV = nullptr;
2021 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2022 GV = G->getGlobal();
2023 bool isStub =
2024 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2025
2026 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2027 bool isLocalARMFunc = false;
2028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2029 auto PtrVt = getPointerTy(DAG.getDataLayout());
2030
2031 if (Subtarget->genLongCalls()) {
2032 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2033, __PRETTY_FUNCTION__))
2033 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2033, __PRETTY_FUNCTION__))
;
2034 // Handle a global address or an external symbol. If it's not one of
2035 // those, the target's already in a register, so we don't need to do
2036 // anything extra.
2037 if (isa<GlobalAddressSDNode>(Callee)) {
2038 // Create a constant pool entry for the callee address
2039 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2040 ARMConstantPoolValue *CPV =
2041 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2042
2043 // Get the address of the callee into a register
2044 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2045 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2046 Callee = DAG.getLoad(
2047 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2048 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2049 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2050 const char *Sym = S->getSymbol();
2051
2052 // Create a constant pool entry for the callee address
2053 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2054 ARMConstantPoolValue *CPV =
2055 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2056 ARMPCLabelIndex, 0);
2057 // Get the address of the callee into a register
2058 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2059 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2060 Callee = DAG.getLoad(
2061 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2062 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2063 }
2064 } else if (isa<GlobalAddressSDNode>(Callee)) {
2065 // If we're optimizing for minimum size and the function is called three or
2066 // more times in this block, we can improve codesize by calling indirectly
2067 // as BLXr has a 16-bit encoding.
2068 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2069 auto *BB = CLI.CS.getParent();
2070 bool PreferIndirect =
2071 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2072 count_if(GV->users(), [&BB](const User *U) {
2073 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2074 }) > 2;
2075
2076 if (!PreferIndirect) {
2077 isDirect = true;
2078 bool isDef = GV->isStrongDefinitionForLinker();
2079
2080 // ARM call to a local ARM function is predicable.
2081 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2082 // tBX takes a register source operand.
2083 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2084 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2084, __PRETTY_FUNCTION__))
;
2085 Callee = DAG.getNode(
2086 ARMISD::WrapperPIC, dl, PtrVt,
2087 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2088 Callee = DAG.getLoad(
2089 PtrVt, dl, DAG.getEntryNode(), Callee,
2090 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2091 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2092 MachineMemOperand::MOInvariant);
2093 } else if (Subtarget->isTargetCOFF()) {
2094 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2095, __PRETTY_FUNCTION__))
2095 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2095, __PRETTY_FUNCTION__))
;
2096 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2097 ? ARMII::MO_DLLIMPORT
2098 : ARMII::MO_NO_FLAG;
2099 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2100 TargetFlags);
2101 if (GV->hasDLLImportStorageClass())
2102 Callee =
2103 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2104 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2105 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2106 } else {
2107 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2108 }
2109 }
2110 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2111 isDirect = true;
2112 // tBX takes a register source operand.
2113 const char *Sym = S->getSymbol();
2114 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2115 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2116 ARMConstantPoolValue *CPV =
2117 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2118 ARMPCLabelIndex, 4);
2119 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2120 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2121 Callee = DAG.getLoad(
2122 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2123 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2124 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2125 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2126 } else {
2127 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2128 }
2129 }
2130
2131 // FIXME: handle tail calls differently.
2132 unsigned CallOpc;
2133 if (Subtarget->isThumb()) {
2134 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2135 CallOpc = ARMISD::CALL_NOLINK;
2136 else
2137 CallOpc = ARMISD::CALL;
2138 } else {
2139 if (!isDirect && !Subtarget->hasV5TOps())
2140 CallOpc = ARMISD::CALL_NOLINK;
2141 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2142 // Emit regular call when code size is the priority
2143 !MF.getFunction().optForMinSize())
2144 // "mov lr, pc; b _foo" to avoid confusing the RSP
2145 CallOpc = ARMISD::CALL_NOLINK;
2146 else
2147 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2148 }
2149
2150 std::vector<SDValue> Ops;
2151 Ops.push_back(Chain);
2152 Ops.push_back(Callee);
2153
2154 // Add argument registers to the end of the list so that they are known live
2155 // into the call.
2156 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2157 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2158 RegsToPass[i].second.getValueType()));
2159
2160 // Add a register mask operand representing the call-preserved registers.
2161 if (!isTailCall) {
2162 const uint32_t *Mask;
2163 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2164 if (isThisReturn) {
2165 // For 'this' returns, use the R0-preserving mask if applicable
2166 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2167 if (!Mask) {
2168 // Set isThisReturn to false if the calling convention is not one that
2169 // allows 'returned' to be modeled in this way, so LowerCallResult does
2170 // not try to pass 'this' straight through
2171 isThisReturn = false;
2172 Mask = ARI->getCallPreservedMask(MF, CallConv);
2173 }
2174 } else
2175 Mask = ARI->getCallPreservedMask(MF, CallConv);
2176
2177 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2177, __PRETTY_FUNCTION__))
;
2178 Ops.push_back(DAG.getRegisterMask(Mask));
2179 }
2180
2181 if (InFlag.getNode())
2182 Ops.push_back(InFlag);
2183
2184 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2185 if (isTailCall) {
2186 MF.getFrameInfo().setHasTailCall();
2187 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2188 }
2189
2190 // Returns a chain and a flag for retval copy to use.
2191 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2192 InFlag = Chain.getValue(1);
2193
2194 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2195 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2196 if (!Ins.empty())
2197 InFlag = Chain.getValue(1);
2198
2199 // Handle result values, copying them out of physregs into vregs that we
2200 // return.
2201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2202 InVals, isThisReturn,
2203 isThisReturn ? OutVals[0] : SDValue());
2204}
2205
2206/// HandleByVal - Every parameter *after* a byval parameter is passed
2207/// on the stack. Remember the next parameter register to allocate,
2208/// and then confiscate the rest of the parameter registers to insure
2209/// this.
2210void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2211 unsigned Align) const {
2212 // Byval (as with any stack) slots are always at least 4 byte aligned.
2213 Align = std::max(Align, 4U);
2214
2215 unsigned Reg = State->AllocateReg(GPRArgRegs);
2216 if (!Reg)
2217 return;
2218
2219 unsigned AlignInRegs = Align / 4;
2220 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2221 for (unsigned i = 0; i < Waste; ++i)
2222 Reg = State->AllocateReg(GPRArgRegs);
2223
2224 if (!Reg)
2225 return;
2226
2227 unsigned Excess = 4 * (ARM::R4 - Reg);
2228
2229 // Special case when NSAA != SP and parameter size greater than size of
2230 // all remained GPR regs. In that case we can't split parameter, we must
2231 // send it to stack. We also must set NCRN to R4, so waste all
2232 // remained registers.
2233 const unsigned NSAAOffset = State->getNextStackOffset();
2234 if (NSAAOffset != 0 && Size > Excess) {
2235 while (State->AllocateReg(GPRArgRegs))
2236 ;
2237 return;
2238 }
2239
2240 // First register for byval parameter is the first register that wasn't
2241 // allocated before this method call, so it would be "reg".
2242 // If parameter is small enough to be saved in range [reg, r4), then
2243 // the end (first after last) register would be reg + param-size-in-regs,
2244 // else parameter would be splitted between registers and stack,
2245 // end register would be r4 in this case.
2246 unsigned ByValRegBegin = Reg;
2247 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2248 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2249 // Note, first register is allocated in the beginning of function already,
2250 // allocate remained amount of registers we need.
2251 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2252 State->AllocateReg(GPRArgRegs);
2253 // A byval parameter that is split between registers and memory needs its
2254 // size truncated here.
2255 // In the case where the entire structure fits in registers, we set the
2256 // size in memory to zero.
2257 Size = std::max<int>(Size - Excess, 0);
2258}
2259
2260/// MatchingStackOffset - Return true if the given stack call argument is
2261/// already available in the same position (relatively) of the caller's
2262/// incoming argument stack.
2263static
2264bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2265 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2266 const TargetInstrInfo *TII) {
2267 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2268 int FI = std::numeric_limits<int>::max();
2269 if (Arg.getOpcode() == ISD::CopyFromReg) {
2270 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2271 if (!TargetRegisterInfo::isVirtualRegister(VR))
2272 return false;
2273 MachineInstr *Def = MRI->getVRegDef(VR);
2274 if (!Def)
2275 return false;
2276 if (!Flags.isByVal()) {
2277 if (!TII->isLoadFromStackSlot(*Def, FI))
2278 return false;
2279 } else {
2280 return false;
2281 }
2282 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2283 if (Flags.isByVal())
2284 // ByVal argument is passed in as a pointer but it's now being
2285 // dereferenced. e.g.
2286 // define @foo(%struct.X* %A) {
2287 // tail call @bar(%struct.X* byval %A)
2288 // }
2289 return false;
2290 SDValue Ptr = Ld->getBasePtr();
2291 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2292 if (!FINode)
2293 return false;
2294 FI = FINode->getIndex();
2295 } else
2296 return false;
2297
2298 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2298, __PRETTY_FUNCTION__))
;
2299 if (!MFI.isFixedObjectIndex(FI))
2300 return false;
2301 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2302}
2303
2304/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2305/// for tail call optimization. Targets which want to do tail call
2306/// optimization should implement this function.
2307bool
2308ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2309 CallingConv::ID CalleeCC,
2310 bool isVarArg,
2311 bool isCalleeStructRet,
2312 bool isCallerStructRet,
2313 const SmallVectorImpl<ISD::OutputArg> &Outs,
2314 const SmallVectorImpl<SDValue> &OutVals,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SelectionDAG& DAG) const {
2317 MachineFunction &MF = DAG.getMachineFunction();
2318 const Function &CallerF = MF.getFunction();
2319 CallingConv::ID CallerCC = CallerF.getCallingConv();
2320
2321 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2321, __PRETTY_FUNCTION__))
;
2322
2323 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2324 // to the call take up r0-r3. The reason is that there are no legal registers
2325 // left to hold the pointer to the function to be called.
2326 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2327 !isa<GlobalAddressSDNode>(Callee.getNode()))
2328 return false;
2329
2330 // Look for obvious safe cases to perform tail call optimization that do not
2331 // require ABI changes. This is what gcc calls sibcall.
2332
2333 // Exception-handling functions need a special set of instructions to indicate
2334 // a return to the hardware. Tail-calling another function would probably
2335 // break this.
2336 if (CallerF.hasFnAttribute("interrupt"))
2337 return false;
2338
2339 // Also avoid sibcall optimization if either caller or callee uses struct
2340 // return semantics.
2341 if (isCalleeStructRet || isCallerStructRet)
2342 return false;
2343
2344 // Externally-defined functions with weak linkage should not be
2345 // tail-called on ARM when the OS does not support dynamic
2346 // pre-emption of symbols, as the AAELF spec requires normal calls
2347 // to undefined weak functions to be replaced with a NOP or jump to the
2348 // next instruction. The behaviour of branch instructions in this
2349 // situation (as used for tail calls) is implementation-defined, so we
2350 // cannot rely on the linker replacing the tail call with a return.
2351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2352 const GlobalValue *GV = G->getGlobal();
2353 const Triple &TT = getTargetMachine().getTargetTriple();
2354 if (GV->hasExternalWeakLinkage() &&
2355 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2356 return false;
2357 }
2358
2359 // Check that the call results are passed in the same way.
2360 LLVMContext &C = *DAG.getContext();
2361 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2362 CCAssignFnForReturn(CalleeCC, isVarArg),
2363 CCAssignFnForReturn(CallerCC, isVarArg)))
2364 return false;
2365 // The callee has to preserve all registers the caller needs to preserve.
2366 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2367 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2368 if (CalleeCC != CallerCC) {
2369 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2370 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2371 return false;
2372 }
2373
2374 // If Caller's vararg or byval argument has been split between registers and
2375 // stack, do not perform tail call, since part of the argument is in caller's
2376 // local frame.
2377 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2378 if (AFI_Caller->getArgRegsSaveSize())
2379 return false;
2380
2381 // If the callee takes no arguments then go on to check the results of the
2382 // call.
2383 if (!Outs.empty()) {
2384 // Check if stack adjustment is needed. For now, do not do this if any
2385 // argument is passed on the stack.
2386 SmallVector<CCValAssign, 16> ArgLocs;
2387 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2388 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2389 if (CCInfo.getNextStackOffset()) {
2390 // Check if the arguments are already laid out in the right way as
2391 // the caller's fixed stack objects.
2392 MachineFrameInfo &MFI = MF.getFrameInfo();
2393 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2394 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2395 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2396 i != e;
2397 ++i, ++realArgIdx) {
2398 CCValAssign &VA = ArgLocs[i];
2399 EVT RegVT = VA.getLocVT();
2400 SDValue Arg = OutVals[realArgIdx];
2401 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2402 if (VA.getLocInfo() == CCValAssign::Indirect)
2403 return false;
2404 if (VA.needsCustom()) {
2405 // f64 and vector types are split into multiple registers or
2406 // register/stack-slot combinations. The types will not match
2407 // the registers; give up on memory f64 refs until we figure
2408 // out what to do about this.
2409 if (!VA.isRegLoc())
2410 return false;
2411 if (!ArgLocs[++i].isRegLoc())
2412 return false;
2413 if (RegVT == MVT::v2f64) {
2414 if (!ArgLocs[++i].isRegLoc())
2415 return false;
2416 if (!ArgLocs[++i].isRegLoc())
2417 return false;
2418 }
2419 } else if (!VA.isRegLoc()) {
2420 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2421 MFI, MRI, TII))
2422 return false;
2423 }
2424 }
2425 }
2426
2427 const MachineRegisterInfo &MRI = MF.getRegInfo();
2428 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2429 return false;
2430 }
2431
2432 return true;
2433}
2434
2435bool
2436ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2437 MachineFunction &MF, bool isVarArg,
2438 const SmallVectorImpl<ISD::OutputArg> &Outs,
2439 LLVMContext &Context) const {
2440 SmallVector<CCValAssign, 16> RVLocs;
2441 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2442 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2443}
2444
2445static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2446 const SDLoc &DL, SelectionDAG &DAG) {
2447 const MachineFunction &MF = DAG.getMachineFunction();
2448 const Function &F = MF.getFunction();
2449
2450 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2451
2452 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2453 // version of the "preferred return address". These offsets affect the return
2454 // instruction if this is a return from PL1 without hypervisor extensions.
2455 // IRQ/FIQ: +4 "subs pc, lr, #4"
2456 // SWI: 0 "subs pc, lr, #0"
2457 // ABORT: +4 "subs pc, lr, #4"
2458 // UNDEF: +4/+2 "subs pc, lr, #0"
2459 // UNDEF varies depending on where the exception came from ARM or Thumb
2460 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2461
2462 int64_t LROffset;
2463 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2464 IntKind == "ABORT")
2465 LROffset = 4;
2466 else if (IntKind == "SWI" || IntKind == "UNDEF")
2467 LROffset = 0;
2468 else
2469 report_fatal_error("Unsupported interrupt attribute. If present, value "
2470 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2471
2472 RetOps.insert(RetOps.begin() + 1,
2473 DAG.getConstant(LROffset, DL, MVT::i32, false));
2474
2475 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2476}
2477
2478SDValue
2479ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2480 bool isVarArg,
2481 const SmallVectorImpl<ISD::OutputArg> &Outs,
2482 const SmallVectorImpl<SDValue> &OutVals,
2483 const SDLoc &dl, SelectionDAG &DAG) const {
2484 // CCValAssign - represent the assignment of the return value to a location.
2485 SmallVector<CCValAssign, 16> RVLocs;
2486
2487 // CCState - Info about the registers and stack slots.
2488 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2489 *DAG.getContext());
2490
2491 // Analyze outgoing return values.
2492 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2493
2494 SDValue Flag;
2495 SmallVector<SDValue, 4> RetOps;
2496 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2497 bool isLittleEndian = Subtarget->isLittle();
2498
2499 MachineFunction &MF = DAG.getMachineFunction();
2500 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2501 AFI->setReturnRegsCount(RVLocs.size());
2502
2503 // Copy the result values into the output registers.
2504 for (unsigned i = 0, realRVLocIdx = 0;
2505 i != RVLocs.size();
2506 ++i, ++realRVLocIdx) {
2507 CCValAssign &VA = RVLocs[i];
2508 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2508, __PRETTY_FUNCTION__))
;
2509
2510 SDValue Arg = OutVals[realRVLocIdx];
2511 bool ReturnF16 = false;
2512
2513 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2514 // Half-precision return values can be returned like this:
2515 //
2516 // t11 f16 = fadd ...
2517 // t12: i16 = bitcast t11
2518 // t13: i32 = zero_extend t12
2519 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2520 //
2521 // to avoid code generation for bitcasts, we simply set Arg to the node
2522 // that produces the f16 value, t11 in this case.
2523 //
2524 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2525 SDValue ZE = Arg.getOperand(0);
2526 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2527 SDValue BC = ZE.getOperand(0);
2528 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2529 Arg = BC.getOperand(0);
2530 ReturnF16 = true;
2531 }
2532 }
2533 }
2534 }
2535
2536 switch (VA.getLocInfo()) {
2537 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2537)
;
2538 case CCValAssign::Full: break;
2539 case CCValAssign::BCvt:
2540 if (!ReturnF16)
2541 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2542 break;
2543 }
2544
2545 if (VA.needsCustom()) {
2546 if (VA.getLocVT() == MVT::v2f64) {
2547 // Extract the first half and return it in two registers.
2548 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2549 DAG.getConstant(0, dl, MVT::i32));
2550 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2551 DAG.getVTList(MVT::i32, MVT::i32), Half);
2552
2553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2554 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2555 Flag);
2556 Flag = Chain.getValue(1);
2557 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2558 VA = RVLocs[++i]; // skip ahead to next loc
2559 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2560 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2561 Flag);
2562 Flag = Chain.getValue(1);
2563 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2564 VA = RVLocs[++i]; // skip ahead to next loc
2565
2566 // Extract the 2nd half and fall through to handle it as an f64 value.
2567 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2568 DAG.getConstant(1, dl, MVT::i32));
2569 }
2570 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2571 // available.
2572 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2573 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2574 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2575 fmrrd.getValue(isLittleEndian ? 0 : 1),
2576 Flag);
2577 Flag = Chain.getValue(1);
2578 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2579 VA = RVLocs[++i]; // skip ahead to next loc
2580 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2581 fmrrd.getValue(isLittleEndian ? 1 : 0),
2582 Flag);
2583 } else
2584 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2585
2586 // Guarantee that all emitted copies are
2587 // stuck together, avoiding something bad.
2588 Flag = Chain.getValue(1);
2589 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2590 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2591 }
2592 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2593 const MCPhysReg *I =
2594 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2595 if (I) {
2596 for (; *I; ++I) {
2597 if (ARM::GPRRegClass.contains(*I))
2598 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2599 else if (ARM::DPRRegClass.contains(*I))
2600 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2601 else
2602 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2602)
;
2603 }
2604 }
2605
2606 // Update chain and glue.
2607 RetOps[0] = Chain;
2608 if (Flag.getNode())
2609 RetOps.push_back(Flag);
2610
2611 // CPUs which aren't M-class use a special sequence to return from
2612 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2613 // though we use "subs pc, lr, #N").
2614 //
2615 // M-class CPUs actually use a normal return sequence with a special
2616 // (hardware-provided) value in LR, so the normal code path works.
2617 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2618 !Subtarget->isMClass()) {
2619 if (Subtarget->isThumb1Only())
2620 report_fatal_error("interrupt attribute is not supported in Thumb1");
2621 return LowerInterruptReturn(RetOps, dl, DAG);
2622 }
2623
2624 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2625}
2626
2627bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2628 if (N->getNumValues() != 1)
2629 return false;
2630 if (!N->hasNUsesOfValue(1, 0))
2631 return false;
2632
2633 SDValue TCChain = Chain;
2634 SDNode *Copy = *N->use_begin();
2635 if (Copy->getOpcode() == ISD::CopyToReg) {
2636 // If the copy has a glue operand, we conservatively assume it isn't safe to
2637 // perform a tail call.
2638 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2639 return false;
2640 TCChain = Copy->getOperand(0);
2641 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2642 SDNode *VMov = Copy;
2643 // f64 returned in a pair of GPRs.
2644 SmallPtrSet<SDNode*, 2> Copies;
2645 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2646 UI != UE; ++UI) {
2647 if (UI->getOpcode() != ISD::CopyToReg)
2648 return false;
2649 Copies.insert(*UI);
2650 }
2651 if (Copies.size() > 2)
2652 return false;
2653
2654 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2655 UI != UE; ++UI) {
2656 SDValue UseChain = UI->getOperand(0);
2657 if (Copies.count(UseChain.getNode()))
2658 // Second CopyToReg
2659 Copy = *UI;
2660 else {
2661 // We are at the top of this chain.
2662 // If the copy has a glue operand, we conservatively assume it
2663 // isn't safe to perform a tail call.
2664 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2665 return false;
2666 // First CopyToReg
2667 TCChain = UseChain;
2668 }
2669 }
2670 } else if (Copy->getOpcode() == ISD::BITCAST) {
2671 // f32 returned in a single GPR.
2672 if (!Copy->hasOneUse())
2673 return false;
2674 Copy = *Copy->use_begin();
2675 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2676 return false;
2677 // If the copy has a glue operand, we conservatively assume it isn't safe to
2678 // perform a tail call.
2679 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2680 return false;
2681 TCChain = Copy->getOperand(0);
2682 } else {
2683 return false;
2684 }
2685
2686 bool HasRet = false;
2687 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2688 UI != UE; ++UI) {
2689 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2690 UI->getOpcode() != ARMISD::INTRET_FLAG)
2691 return false;
2692 HasRet = true;
2693 }
2694
2695 if (!HasRet)
2696 return false;
2697
2698 Chain = TCChain;
2699 return true;
2700}
2701
2702bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2703 if (!Subtarget->supportsTailCall())
2704 return false;
2705
2706 auto Attr =
2707 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2708 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2709 return false;
2710
2711 return true;
2712}
2713
2714// Trying to write a 64 bit value so need to split into two 32 bit values first,
2715// and pass the lower and high parts through.
2716static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2717 SDLoc DL(Op);
2718 SDValue WriteValue = Op->getOperand(2);
2719
2720 // This function is only supposed to be called for i64 type argument.
2721 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2722, __PRETTY_FUNCTION__))
2722 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2722, __PRETTY_FUNCTION__))
;
2723
2724 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2725 DAG.getConstant(0, DL, MVT::i32));
2726 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2727 DAG.getConstant(1, DL, MVT::i32));
2728 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2729 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2730}
2731
2732// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2733// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2734// one of the above mentioned nodes. It has to be wrapped because otherwise
2735// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2736// be used to form addressing mode. These wrapped nodes will be selected
2737// into MOVi.
2738SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2739 SelectionDAG &DAG) const {
2740 EVT PtrVT = Op.getValueType();
2741 // FIXME there is no actual debug info here
2742 SDLoc dl(Op);
2743 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2744 SDValue Res;
2745
2746 // When generating execute-only code Constant Pools must be promoted to the
2747 // global data section. It's a bit ugly that we can't share them across basic
2748 // blocks, but this way we guarantee that execute-only behaves correct with
2749 // position-independent addressing modes.
2750 if (Subtarget->genExecuteOnly()) {
2751 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2752 auto T = const_cast<Type*>(CP->getType());
2753 auto C = const_cast<Constant*>(CP->getConstVal());
2754 auto M = const_cast<Module*>(DAG.getMachineFunction().
2755 getFunction().getParent());
2756 auto GV = new GlobalVariable(
2757 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2758 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2759 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2760 Twine(AFI->createPICLabelUId())
2761 );
2762 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2763 dl, PtrVT);
2764 return LowerGlobalAddress(GA, DAG);
2765 }
2766
2767 if (CP->isMachineConstantPoolEntry())
2768 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2769 CP->getAlignment());
2770 else
2771 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2772 CP->getAlignment());
2773 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2774}
2775
2776unsigned ARMTargetLowering::getJumpTableEncoding() const {
2777 return MachineJumpTableInfo::EK_Inline;
2778}
2779
2780SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2781 SelectionDAG &DAG) const {
2782 MachineFunction &MF = DAG.getMachineFunction();
2783 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2784 unsigned ARMPCLabelIndex = 0;
2785 SDLoc DL(Op);
2786 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2787 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2788 SDValue CPAddr;
2789 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2790 if (!IsPositionIndependent) {
2791 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2792 } else {
2793 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2794 ARMPCLabelIndex = AFI->createPICLabelUId();
2795 ARMConstantPoolValue *CPV =
2796 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2797 ARMCP::CPBlockAddress, PCAdj);
2798 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2799 }
2800 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2801 SDValue Result = DAG.getLoad(
2802 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2803 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2804 if (!IsPositionIndependent)
2805 return Result;
2806 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2807 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2808}
2809
2810/// Convert a TLS address reference into the correct sequence of loads
2811/// and calls to compute the variable's address for Darwin, and return an
2812/// SDValue containing the final node.
2813
2814/// Darwin only has one TLS scheme which must be capable of dealing with the
2815/// fully general situation, in the worst case. This means:
2816/// + "extern __thread" declaration.
2817/// + Defined in a possibly unknown dynamic library.
2818///
2819/// The general system is that each __thread variable has a [3 x i32] descriptor
2820/// which contains information used by the runtime to calculate the address. The
2821/// only part of this the compiler needs to know about is the first word, which
2822/// contains a function pointer that must be called with the address of the
2823/// entire descriptor in "r0".
2824///
2825/// Since this descriptor may be in a different unit, in general access must
2826/// proceed along the usual ARM rules. A common sequence to produce is:
2827///
2828/// movw rT1, :lower16:_var$non_lazy_ptr
2829/// movt rT1, :upper16:_var$non_lazy_ptr
2830/// ldr r0, [rT1]
2831/// ldr rT2, [r0]
2832/// blx rT2
2833/// [...address now in r0...]
2834SDValue
2835ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2836 SelectionDAG &DAG) const {
2837 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2838, __PRETTY_FUNCTION__))
2838 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2838, __PRETTY_FUNCTION__))
;
2839 SDLoc DL(Op);
2840
2841 // First step is to get the address of the actua global symbol. This is where
2842 // the TLS descriptor lives.
2843 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2844
2845 // The first entry in the descriptor is a function pointer that we must call
2846 // to obtain the address of the variable.
2847 SDValue Chain = DAG.getEntryNode();
2848 SDValue FuncTLVGet = DAG.getLoad(
2849 MVT::i32, DL, Chain, DescAddr,
2850 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2851 /* Alignment = */ 4,
2852 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2853 MachineMemOperand::MOInvariant);
2854 Chain = FuncTLVGet.getValue(1);
2855
2856 MachineFunction &F = DAG.getMachineFunction();
2857 MachineFrameInfo &MFI = F.getFrameInfo();
2858 MFI.setAdjustsStack(true);
2859
2860 // TLS calls preserve all registers except those that absolutely must be
2861 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2862 // silly).
2863 auto TRI =
2864 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2865 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2866 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2867
2868 // Finally, we can make the call. This is just a degenerate version of a
2869 // normal AArch64 call node: r0 takes the address of the descriptor, and
2870 // returns the address of the variable in this thread.
2871 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2872 Chain =
2873 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2874 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2875 DAG.getRegisterMask(Mask), Chain.getValue(1));
2876 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2877}
2878
2879SDValue
2880ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2881 SelectionDAG &DAG) const {
2882 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 2882, __PRETTY_FUNCTION__))
;
2883
2884 SDValue Chain = DAG.getEntryNode();
2885 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2886 SDLoc DL(Op);
2887
2888 // Load the current TEB (thread environment block)
2889 SDValue Ops[] = {Chain,
2890 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2891 DAG.getConstant(15, DL, MVT::i32),
2892 DAG.getConstant(0, DL, MVT::i32),
2893 DAG.getConstant(13, DL, MVT::i32),
2894 DAG.getConstant(0, DL, MVT::i32),
2895 DAG.getConstant(2, DL, MVT::i32)};
2896 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2897 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2898
2899 SDValue TEB = CurrentTEB.getValue(0);
2900 Chain = CurrentTEB.getValue(1);
2901
2902 // Load the ThreadLocalStoragePointer from the TEB
2903 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2904 SDValue TLSArray =
2905 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2906 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2907
2908 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2909 // offset into the TLSArray.
2910
2911 // Load the TLS index from the C runtime
2912 SDValue TLSIndex =
2913 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2914 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2915 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2916
2917 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2918 DAG.getConstant(2, DL, MVT::i32));
2919 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2920 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2921 MachinePointerInfo());
2922
2923 // Get the offset of the start of the .tls section (section base)
2924 const auto *GA = cast<GlobalAddressSDNode>(Op);
2925 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2926 SDValue Offset = DAG.getLoad(
2927 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2928 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2929 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2930
2931 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2932}
2933
2934// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2935SDValue
2936ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2937 SelectionDAG &DAG) const {
2938 SDLoc dl(GA);
2939 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2940 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2941 MachineFunction &MF = DAG.getMachineFunction();
2942 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2943 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2944 ARMConstantPoolValue *CPV =
2945 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2946 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2947 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2948 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2949 Argument = DAG.getLoad(
2950 PtrVT, dl, DAG.getEntryNode(), Argument,
2951 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2952 SDValue Chain = Argument.getValue(1);
2953
2954 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2955 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2956
2957 // call __tls_get_addr.
2958 ArgListTy Args;
2959 ArgListEntry Entry;
2960 Entry.Node = Argument;
2961 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2962 Args.push_back(Entry);
2963
2964 // FIXME: is there useful debug info available here?
2965 TargetLowering::CallLoweringInfo CLI(DAG);
2966 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2967 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2968 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2969
2970 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2971 return CallResult.first;
2972}
2973
2974// Lower ISD::GlobalTLSAddress using the "initial exec" or
2975// "local exec" model.
2976SDValue
2977ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2978 SelectionDAG &DAG,
2979 TLSModel::Model model) const {
2980 const GlobalValue *GV = GA->getGlobal();
2981 SDLoc dl(GA);
2982 SDValue Offset;
2983 SDValue Chain = DAG.getEntryNode();
2984 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2985 // Get the Thread Pointer
2986 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2987
2988 if (model == TLSModel::InitialExec) {
2989 MachineFunction &MF = DAG.getMachineFunction();
2990 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2991 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2992 // Initial exec model.
2993 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2994 ARMConstantPoolValue *CPV =
2995 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2996 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2997 true);
2998 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2999 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3000 Offset = DAG.getLoad(
3001 PtrVT, dl, Chain, Offset,
3002 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3003 Chain = Offset.getValue(1);
3004
3005 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3006 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3007
3008 Offset = DAG.getLoad(
3009 PtrVT, dl, Chain, Offset,
3010 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3011 } else {
3012 // local exec model
3013 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3013, __PRETTY_FUNCTION__))
;
3014 ARMConstantPoolValue *CPV =
3015 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3016 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3017 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3018 Offset = DAG.getLoad(
3019 PtrVT, dl, Chain, Offset,
3020 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3021 }
3022
3023 // The address of the thread local variable is the add of the thread
3024 // pointer with the offset of the variable.
3025 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3026}
3027
3028SDValue
3029ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3030 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3031 if (DAG.getTarget().useEmulatedTLS())
3032 return LowerToTLSEmulatedModel(GA, DAG);
3033
3034 if (Subtarget->isTargetDarwin())
3035 return LowerGlobalTLSAddressDarwin(Op, DAG);
3036
3037 if (Subtarget->isTargetWindows())
3038 return LowerGlobalTLSAddressWindows(Op, DAG);
3039
3040 // TODO: implement the "local dynamic" model
3041 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3041, __PRETTY_FUNCTION__))
;
3042 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3043
3044 switch (model) {
3045 case TLSModel::GeneralDynamic:
3046 case TLSModel::LocalDynamic:
3047 return LowerToTLSGeneralDynamicModel(GA, DAG);
3048 case TLSModel::InitialExec:
3049 case TLSModel::LocalExec:
3050 return LowerToTLSExecModels(GA, DAG, model);
3051 }
3052 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3052)
;
3053}
3054
3055/// Return true if all users of V are within function F, looking through
3056/// ConstantExprs.
3057static bool allUsersAreInFunction(const Value *V, const Function *F) {
3058 SmallVector<const User*,4> Worklist;
3059 for (auto *U : V->users())
3060 Worklist.push_back(U);
3061 while (!Worklist.empty()) {
3062 auto *U = Worklist.pop_back_val();
3063 if (isa<ConstantExpr>(U)) {
3064 for (auto *UU : U->users())
3065 Worklist.push_back(UU);
3066 continue;
3067 }
3068
3069 auto *I = dyn_cast<Instruction>(U);
3070 if (!I || I->getParent()->getParent() != F)
3071 return false;
3072 }
3073 return true;
3074}
3075
3076static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3077 const GlobalValue *GV, SelectionDAG &DAG,
3078 EVT PtrVT, const SDLoc &dl) {
3079 // If we're creating a pool entry for a constant global with unnamed address,
3080 // and the global is small enough, we can emit it inline into the constant pool
3081 // to save ourselves an indirection.
3082 //
3083 // This is a win if the constant is only used in one function (so it doesn't
3084 // need to be duplicated) or duplicating the constant wouldn't increase code
3085 // size (implying the constant is no larger than 4 bytes).
3086 const Function &F = DAG.getMachineFunction().getFunction();
3087
3088 // We rely on this decision to inline being idemopotent and unrelated to the
3089 // use-site. We know that if we inline a variable at one use site, we'll
3090 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3091 // doesn't know about this optimization, so bail out if it's enabled else
3092 // we could decide to inline here (and thus never emit the GV) but require
3093 // the GV from fast-isel generated code.
3094 if (!EnableConstpoolPromotion ||
3095 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3096 return SDValue();
3097
3098 auto *GVar = dyn_cast<GlobalVariable>(GV);
3099 if (!GVar || !GVar->hasInitializer() ||
3100 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3101 !GVar->hasLocalLinkage())
3102 return SDValue();
3103
3104 // If we inline a value that contains relocations, we move the relocations
3105 // from .data to .text. This is not allowed in position-independent code.
3106 auto *Init = GVar->getInitializer();
3107 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3108 Init->needsRelocation())
3109 return SDValue();
3110
3111 // The constant islands pass can only really deal with alignment requests
3112 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3113 // any type wanting greater alignment requirements than 4 bytes. We also
3114 // can only promote constants that are multiples of 4 bytes in size or
3115 // are paddable to a multiple of 4. Currently we only try and pad constants
3116 // that are strings for simplicity.
3117 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3118 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3119 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3120 unsigned RequiredPadding = 4 - (Size % 4);
3121 bool PaddingPossible =
3122 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3123 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3124 Size == 0)
3125 return SDValue();
3126
3127 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3128 MachineFunction &MF = DAG.getMachineFunction();
3129 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3130
3131 // We can't bloat the constant pool too much, else the ConstantIslands pass
3132 // may fail to converge. If we haven't promoted this global yet (it may have
3133 // multiple uses), and promoting it would increase the constant pool size (Sz
3134 // > 4), ensure we have space to do so up to MaxTotal.
3135 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3136 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3137 ConstpoolPromotionMaxTotal)
3138 return SDValue();
3139
3140 // This is only valid if all users are in a single function; we can't clone
3141 // the constant in general. The LLVM IR unnamed_addr allows merging
3142 // constants, but not cloning them.
3143 //
3144 // We could potentially allow cloning if we could prove all uses of the
3145 // constant in the current function don't care about the address, like
3146 // printf format strings. But that isn't implemented for now.
3147 if (!allUsersAreInFunction(GVar, &F))
3148 return SDValue();
3149
3150 // We're going to inline this global. Pad it out if needed.
3151 if (RequiredPadding != 4) {
3152 StringRef S = CDAInit->getAsString();
3153
3154 SmallVector<uint8_t,16> V(S.size());
3155 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3156 while (RequiredPadding--)
3157 V.push_back(0);
3158 Init = ConstantDataArray::get(*DAG.getContext(), V);
3159 }
3160
3161 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3162 SDValue CPAddr =
3163 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3164 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3165 AFI->markGlobalAsPromotedToConstantPool(GVar);
3166 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3167 PaddedSize - 4);
3168 }
3169 ++NumConstpoolPromoted;
3170 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3171}
3172
3173bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3174 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3175 if (!(GV = GA->getBaseObject()))
3176 return false;
3177 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3178 return V->isConstant();
3179 return isa<Function>(GV);
3180}
3181
3182SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3183 SelectionDAG &DAG) const {
3184 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3185 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3185)
;
3186 case Triple::COFF:
3187 return LowerGlobalAddressWindows(Op, DAG);
3188 case Triple::ELF:
3189 return LowerGlobalAddressELF(Op, DAG);
3190 case Triple::MachO:
3191 return LowerGlobalAddressDarwin(Op, DAG);
3192 }
3193}
3194
3195SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3196 SelectionDAG &DAG) const {
3197 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3198 SDLoc dl(Op);
3199 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3200 const TargetMachine &TM = getTargetMachine();
3201 bool IsRO = isReadOnly(GV);
3202
3203 // promoteToConstantPool only if not generating XO text section
3204 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3205 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3206 return V;
3207
3208 if (isPositionIndependent()) {
3209 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3210 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3211 UseGOT_PREL ? ARMII::MO_GOT : 0);
3212 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3213 if (UseGOT_PREL)
3214 Result =
3215 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3216 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3217 return Result;
3218 } else if (Subtarget->isROPI() && IsRO) {
3219 // PC-relative.
3220 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3221 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3222 return Result;
3223 } else if (Subtarget->isRWPI() && !IsRO) {
3224 // SB-relative.
3225 SDValue RelAddr;
3226 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3227 ++NumMovwMovt;
3228 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3229 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3230 } else { // use literal pool for address constant
3231 ARMConstantPoolValue *CPV =
3232 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3233 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3234 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3235 RelAddr = DAG.getLoad(
3236 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3237 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3238 }
3239 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3240 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3241 return Result;
3242 }
3243
3244 // If we have T2 ops, we can materialize the address directly via movt/movw
3245 // pair. This is always cheaper.
3246 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3247 ++NumMovwMovt;
3248 // FIXME: Once remat is capable of dealing with instructions with register
3249 // operands, expand this into two nodes.
3250 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3251 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3252 } else {
3253 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3254 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3255 return DAG.getLoad(
3256 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3257 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3258 }
3259}
3260
3261SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3262 SelectionDAG &DAG) const {
3263 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3264, __PRETTY_FUNCTION__))
3264 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3264, __PRETTY_FUNCTION__))
;
3265 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3266 SDLoc dl(Op);
3267 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3268
3269 if (Subtarget->useMovt(DAG.getMachineFunction()))
3270 ++NumMovwMovt;
3271
3272 // FIXME: Once remat is capable of dealing with instructions with register
3273 // operands, expand this into multiple nodes
3274 unsigned Wrapper =
3275 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3276
3277 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3278 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3279
3280 if (Subtarget->isGVIndirectSymbol(GV))
3281 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3282 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3283 return Result;
3284}
3285
3286SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3287 SelectionDAG &DAG) const {
3288 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3288, __PRETTY_FUNCTION__))
;
3289 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&((Subtarget->useMovt(DAG.getMachineFunction()) && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3290, __PRETTY_FUNCTION__))
3290 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt(DAG.getMachineFunction()) && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3290, __PRETTY_FUNCTION__))
;
3291 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3292, __PRETTY_FUNCTION__))
3292 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3292, __PRETTY_FUNCTION__))
;
3293
3294 const TargetMachine &TM = getTargetMachine();
3295 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3296 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3297 if (GV->hasDLLImportStorageClass())
3298 TargetFlags = ARMII::MO_DLLIMPORT;
3299 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3300 TargetFlags = ARMII::MO_COFFSTUB;
3301 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3302 SDValue Result;
3303 SDLoc DL(Op);
3304
3305 ++NumMovwMovt;
3306
3307 // FIXME: Once remat is capable of dealing with instructions with register
3308 // operands, expand this into two nodes.
3309 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3310 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3311 TargetFlags));
3312 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3313 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3314 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3315 return Result;
3316}
3317
3318SDValue
3319ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3320 SDLoc dl(Op);
3321 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3322 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3323 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3324 Op.getOperand(1), Val);
3325}
3326
3327SDValue
3328ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3329 SDLoc dl(Op);
3330 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3331 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3332}
3333
3334SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3335 SelectionDAG &DAG) const {
3336 SDLoc dl(Op);
3337 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3338 Op.getOperand(0));
3339}
3340
3341SDValue
3342ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3343 const ARMSubtarget *Subtarget) const {
3344 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3345 SDLoc dl(Op);
3346 switch (IntNo) {
3347 default: return SDValue(); // Don't custom lower most intrinsics.
3348 case Intrinsic::thread_pointer: {
3349 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3350 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3351 }
3352 case Intrinsic::eh_sjlj_lsda: {
3353 MachineFunction &MF = DAG.getMachineFunction();
3354 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3355 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3356 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3357 SDValue CPAddr;
3358 bool IsPositionIndependent = isPositionIndependent();
3359 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3360 ARMConstantPoolValue *CPV =
3361 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3362 ARMCP::CPLSDA, PCAdj);
3363 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3364 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3365 SDValue Result = DAG.getLoad(
3366 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3367 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3368
3369 if (IsPositionIndependent) {
3370 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3371 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3372 }
3373 return Result;
3374 }
3375 case Intrinsic::arm_neon_vabs:
3376 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3377 Op.getOperand(1));
3378 case Intrinsic::arm_neon_vmulls:
3379 case Intrinsic::arm_neon_vmullu: {
3380 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3381 ? ARMISD::VMULLs : ARMISD::VMULLu;
3382 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3383 Op.getOperand(1), Op.getOperand(2));
3384 }
3385 case Intrinsic::arm_neon_vminnm:
3386 case Intrinsic::arm_neon_vmaxnm: {
3387 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3388 ? ISD::FMINNUM : ISD::FMAXNUM;
3389 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3390 Op.getOperand(1), Op.getOperand(2));
3391 }
3392 case Intrinsic::arm_neon_vminu:
3393 case Intrinsic::arm_neon_vmaxu: {
3394 if (Op.getValueType().isFloatingPoint())
3395 return SDValue();
3396 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3397 ? ISD::UMIN : ISD::UMAX;
3398 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3399 Op.getOperand(1), Op.getOperand(2));
3400 }
3401 case Intrinsic::arm_neon_vmins:
3402 case Intrinsic::arm_neon_vmaxs: {
3403 // v{min,max}s is overloaded between signed integers and floats.
3404 if (!Op.getValueType().isFloatingPoint()) {
3405 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3406 ? ISD::SMIN : ISD::SMAX;
3407 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3408 Op.getOperand(1), Op.getOperand(2));
3409 }
3410 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3411 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3412 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3413 Op.getOperand(1), Op.getOperand(2));
3414 }
3415 case Intrinsic::arm_neon_vtbl1:
3416 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3417 Op.getOperand(1), Op.getOperand(2));
3418 case Intrinsic::arm_neon_vtbl2:
3419 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3420 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3421 }
3422}
3423
3424static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3425 const ARMSubtarget *Subtarget) {
3426 SDLoc dl(Op);
3427 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3428 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3429 if (SSID == SyncScope::SingleThread)
3430 return Op;
3431
3432 if (!Subtarget->hasDataBarrier()) {
3433 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3434 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3435 // here.
3436 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3437, __PRETTY_FUNCTION__))
3437 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3437, __PRETTY_FUNCTION__))
;
3438 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3439 DAG.getConstant(0, dl, MVT::i32));
3440 }
3441
3442 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3443 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3444 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3445 if (Subtarget->isMClass()) {
3446 // Only a full system barrier exists in the M-class architectures.
3447 Domain = ARM_MB::SY;
3448 } else if (Subtarget->preferISHSTBarriers() &&
3449 Ord == AtomicOrdering::Release) {
3450 // Swift happens to implement ISHST barriers in a way that's compatible with
3451 // Release semantics but weaker than ISH so we'd be fools not to use
3452 // it. Beware: other processors probably don't!
3453 Domain = ARM_MB::ISHST;
3454 }
3455
3456 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3457 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3458 DAG.getConstant(Domain, dl, MVT::i32));
3459}
3460
3461static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3462 const ARMSubtarget *Subtarget) {
3463 // ARM pre v5TE and Thumb1 does not have preload instructions.
3464 if (!(Subtarget->isThumb2() ||
3465 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3466 // Just preserve the chain.
3467 return Op.getOperand(0);
3468
3469 SDLoc dl(Op);
3470 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3471 if (!isRead &&
3472 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3473 // ARMv7 with MP extension has PLDW.
3474 return Op.getOperand(0);
3475
3476 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3477 if (Subtarget->isThumb()) {
3478 // Invert the bits.
3479 isRead = ~isRead & 1;
3480 isData = ~isData & 1;
3481 }
3482
3483 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3484 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3485 DAG.getConstant(isData, dl, MVT::i32));
3486}
3487
3488static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3489 MachineFunction &MF = DAG.getMachineFunction();
3490 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3491
3492 // vastart just stores the address of the VarArgsFrameIndex slot into the
3493 // memory location argument.
3494 SDLoc dl(Op);
3495 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3496 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3497 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3498 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3499 MachinePointerInfo(SV));
3500}
3501
3502SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3503 CCValAssign &NextVA,
3504 SDValue &Root,
3505 SelectionDAG &DAG,
3506 const SDLoc &dl) const {
3507 MachineFunction &MF = DAG.getMachineFunction();
3508 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3509
3510 const TargetRegisterClass *RC;
3511 if (AFI->isThumb1OnlyFunction())
3512 RC = &ARM::tGPRRegClass;
3513 else
3514 RC = &ARM::GPRRegClass;
3515
3516 // Transform the arguments stored in physical registers into virtual ones.
3517 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3518 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3519
3520 SDValue ArgValue2;
3521 if (NextVA.isMemLoc()) {
3522 MachineFrameInfo &MFI = MF.getFrameInfo();
3523 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3524
3525 // Create load node to retrieve arguments from the stack.
3526 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3527 ArgValue2 = DAG.getLoad(
3528 MVT::i32, dl, Root, FIN,
3529 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3530 } else {
3531 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3532 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3533 }
3534 if (!Subtarget->isLittle())
3535 std::swap (ArgValue, ArgValue2);
3536 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3537}
3538
3539// The remaining GPRs hold either the beginning of variable-argument
3540// data, or the beginning of an aggregate passed by value (usually
3541// byval). Either way, we allocate stack slots adjacent to the data
3542// provided by our caller, and store the unallocated registers there.
3543// If this is a variadic function, the va_list pointer will begin with
3544// these values; otherwise, this reassembles a (byval) structure that
3545// was split between registers and memory.
3546// Return: The frame index registers were stored into.
3547int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3548 const SDLoc &dl, SDValue &Chain,
3549 const Value *OrigArg,
3550 unsigned InRegsParamRecordIdx,
3551 int ArgOffset, unsigned ArgSize) const {
3552 // Currently, two use-cases possible:
3553 // Case #1. Non-var-args function, and we meet first byval parameter.
3554 // Setup first unallocated register as first byval register;
3555 // eat all remained registers
3556 // (these two actions are performed by HandleByVal method).
3557 // Then, here, we initialize stack frame with
3558 // "store-reg" instructions.
3559 // Case #2. Var-args function, that doesn't contain byval parameters.
3560 // The same: eat all remained unallocated registers,
3561 // initialize stack frame.
3562
3563 MachineFunction &MF = DAG.getMachineFunction();
3564 MachineFrameInfo &MFI = MF.getFrameInfo();
3565 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3566 unsigned RBegin, REnd;
3567 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3568 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3569 } else {
3570 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3571 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3572 REnd = ARM::R4;
3573 }
3574
3575 if (REnd != RBegin)
3576 ArgOffset = -4 * (ARM::R4 - RBegin);
3577
3578 auto PtrVT = getPointerTy(DAG.getDataLayout());
3579 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3580 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3581
3582 SmallVector<SDValue, 4> MemOps;
3583 const TargetRegisterClass *RC =
3584 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3585
3586 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3587 unsigned VReg = MF.addLiveIn(Reg, RC);
3588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3589 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3590 MachinePointerInfo(OrigArg, 4 * i));
3591 MemOps.push_back(Store);
3592 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3593 }
3594
3595 if (!MemOps.empty())
3596 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3597 return FrameIndex;
3598}
3599
3600// Setup stack frame, the va_list pointer will start from.
3601void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3602 const SDLoc &dl, SDValue &Chain,
3603 unsigned ArgOffset,
3604 unsigned TotalArgRegsSaveSize,
3605 bool ForceMutable) const {
3606 MachineFunction &MF = DAG.getMachineFunction();
3607 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3608
3609 // Try to store any remaining integer argument regs
3610 // to their spots on the stack so that they may be loaded by dereferencing
3611 // the result of va_next.
3612 // If there is no regs to be stored, just point address after last
3613 // argument passed via stack.
3614 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3615 CCInfo.getInRegsParamsCount(),
3616 CCInfo.getNextStackOffset(), 4);
3617 AFI->setVarArgsFrameIndex(FrameIndex);
3618}
3619
3620SDValue ARMTargetLowering::LowerFormalArguments(
3621 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3622 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3623 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 MachineFrameInfo &MFI = MF.getFrameInfo();
3626
3627 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3628
3629 // Assign locations to all of the incoming arguments.
3630 SmallVector<CCValAssign, 16> ArgLocs;
3631 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3632 *DAG.getContext());
3633 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3634
3635 SmallVector<SDValue, 16> ArgValues;
3636 SDValue ArgValue;
3637 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3638 unsigned CurArgIdx = 0;
3639
3640 // Initially ArgRegsSaveSize is zero.
3641 // Then we increase this value each time we meet byval parameter.
3642 // We also increase this value in case of varargs function.
3643 AFI->setArgRegsSaveSize(0);
3644
3645 // Calculate the amount of stack space that we need to allocate to store
3646 // byval and variadic arguments that are passed in registers.
3647 // We need to know this before we allocate the first byval or variadic
3648 // argument, as they will be allocated a stack slot below the CFA (Canonical
3649 // Frame Address, the stack pointer at entry to the function).
3650 unsigned ArgRegBegin = ARM::R4;
3651 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3652 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3653 break;
3654
3655 CCValAssign &VA = ArgLocs[i];
3656 unsigned Index = VA.getValNo();
3657 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3658 if (!Flags.isByVal())
3659 continue;
3660
3661 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3661, __PRETTY_FUNCTION__))
;
3662 unsigned RBegin, REnd;
3663 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3664 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3665
3666 CCInfo.nextInRegsParam();
3667 }
3668 CCInfo.rewindByValRegsInfo();
3669
3670 int lastInsIndex = -1;
3671 if (isVarArg && MFI.hasVAStart()) {
3672 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3673 if (RegIdx != array_lengthof(GPRArgRegs))
3674 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3675 }
3676
3677 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3678 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3679 auto PtrVT = getPointerTy(DAG.getDataLayout());
3680
3681 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3682 CCValAssign &VA = ArgLocs[i];
3683 if (Ins[VA.getValNo()].isOrigArg()) {
3684 std::advance(CurOrigArg,
3685 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3686 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3687 }
3688 // Arguments stored in registers.
3689 if (VA.isRegLoc()) {
3690 EVT RegVT = VA.getLocVT();
3691
3692 if (VA.needsCustom()) {
3693 // f64 and vector types are split up into multiple registers or
3694 // combinations of registers and stack slots.
3695 if (VA.getLocVT() == MVT::v2f64) {
3696 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3697 Chain, DAG, dl);
3698 VA = ArgLocs[++i]; // skip ahead to next loc
3699 SDValue ArgValue2;
3700 if (VA.isMemLoc()) {
3701 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3702 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3703 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3704 MachinePointerInfo::getFixedStack(
3705 DAG.getMachineFunction(), FI));
3706 } else {
3707 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3708 Chain, DAG, dl);
3709 }
3710 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3711 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3712 ArgValue, ArgValue1,
3713 DAG.getIntPtrConstant(0, dl));
3714 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3715 ArgValue, ArgValue2,
3716 DAG.getIntPtrConstant(1, dl));
3717 } else
3718 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3719 } else {
3720 const TargetRegisterClass *RC;
3721
3722
3723 if (RegVT == MVT::f16)
3724 RC = &ARM::HPRRegClass;
3725 else if (RegVT == MVT::f32)
3726 RC = &ARM::SPRRegClass;
3727 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3728 RC = &ARM::DPRRegClass;
3729 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3730 RC = &ARM::QPRRegClass;
3731 else if (RegVT == MVT::i32)
3732 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3733 : &ARM::GPRRegClass;
3734 else
3735 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3735)
;
3736
3737 // Transform the arguments in physical registers into virtual ones.
3738 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3739 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3740 }
3741
3742 // If this is an 8 or 16-bit value, it is really passed promoted
3743 // to 32 bits. Insert an assert[sz]ext to capture this, then
3744 // truncate to the right size.
3745 switch (VA.getLocInfo()) {
3746 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3746)
;
3747 case CCValAssign::Full: break;
3748 case CCValAssign::BCvt:
3749 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3750 break;
3751 case CCValAssign::SExt:
3752 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3753 DAG.getValueType(VA.getValVT()));
3754 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3755 break;
3756 case CCValAssign::ZExt:
3757 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3758 DAG.getValueType(VA.getValVT()));
3759 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3760 break;
3761 }
3762
3763 InVals.push_back(ArgValue);
3764 } else { // VA.isRegLoc()
3765 // sanity check
3766 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3766, __PRETTY_FUNCTION__))
;
3767 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3767, __PRETTY_FUNCTION__))
;
3768
3769 int index = VA.getValNo();
3770
3771 // Some Ins[] entries become multiple ArgLoc[] entries.
3772 // Process them only once.
3773 if (index != lastInsIndex)
3774 {
3775 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3776 // FIXME: For now, all byval parameter objects are marked mutable.
3777 // This can be changed with more analysis.
3778 // In case of tail call optimization mark all arguments mutable.
3779 // Since they could be overwritten by lowering of arguments in case of
3780 // a tail call.
3781 if (Flags.isByVal()) {
3782 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3783, __PRETTY_FUNCTION__))
3783 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3783, __PRETTY_FUNCTION__))
;
3784 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3785
3786 int FrameIndex = StoreByValRegs(
3787 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3788 VA.getLocMemOffset(), Flags.getByValSize());
3789 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3790 CCInfo.nextInRegsParam();
3791 } else {
3792 unsigned FIOffset = VA.getLocMemOffset();
3793 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3794 FIOffset, true);
3795
3796 // Create load nodes to retrieve arguments from the stack.
3797 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3798 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3799 MachinePointerInfo::getFixedStack(
3800 DAG.getMachineFunction(), FI)));
3801 }
3802 lastInsIndex = index;
3803 }
3804 }
3805 }
3806
3807 // varargs
3808 if (isVarArg && MFI.hasVAStart())
3809 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3810 CCInfo.getNextStackOffset(),
3811 TotalArgRegsSaveSize);
3812
3813 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3814
3815 return Chain;
3816}
3817
3818/// isFloatingPointZero - Return true if this is +0.0.
3819static bool isFloatingPointZero(SDValue Op) {
3820 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3821 return CFP->getValueAPF().isPosZero();
3822 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3823 // Maybe this has already been legalized into the constant pool?
3824 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3825 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3826 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3827 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3828 return CFP->getValueAPF().isPosZero();
3829 }
3830 } else if (Op->getOpcode() == ISD::BITCAST &&
3831 Op->getValueType(0) == MVT::f64) {
3832 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3833 // created by LowerConstantFP().
3834 SDValue BitcastOp = Op->getOperand(0);
3835 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3836 isNullConstant(BitcastOp->getOperand(0)))
3837 return true;
3838 }
3839 return false;
3840}
3841
3842/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3843/// the given operands.
3844SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3845 SDValue &ARMcc, SelectionDAG &DAG,
3846 const SDLoc &dl) const {
3847 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3848 unsigned C = RHSC->getZExtValue();
3849 if (!isLegalICmpImmediate((int32_t)C)) {
3850 // Constant does not fit, try adjusting it by one.
3851 switch (CC) {
3852 default: break;
3853 case ISD::SETLT:
3854 case ISD::SETGE:
3855 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3856 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3857 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3858 }
3859 break;
3860 case ISD::SETULT:
3861 case ISD::SETUGE:
3862 if (C != 0 && isLegalICmpImmediate(C-1)) {
3863 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3864 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3865 }
3866 break;
3867 case ISD::SETLE:
3868 case ISD::SETGT:
3869 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3870 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3871 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3872 }
3873 break;
3874 case ISD::SETULE:
3875 case ISD::SETUGT:
3876 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3877 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3878 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3879 }
3880 break;
3881 }
3882 }
3883 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3884 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3885 // In ARM and Thumb-2, the compare instructions can shift their second
3886 // operand.
3887 CC = ISD::getSetCCSwappedOperands(CC);
3888 std::swap(LHS, RHS);
3889 }
3890
3891 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3892 ARMISD::NodeType CompareType;
3893 switch (CondCode) {
3894 default:
3895 CompareType = ARMISD::CMP;
3896 break;
3897 case ARMCC::EQ:
3898 case ARMCC::NE:
3899 // Uses only Z Flag
3900 CompareType = ARMISD::CMPZ;
3901 break;
3902 }
3903 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3904 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3905}
3906
3907/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3908SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3909 SelectionDAG &DAG, const SDLoc &dl,
3910 bool InvalidOnQNaN) const {
3911 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)((!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3911, __PRETTY_FUNCTION__))
;
3912 SDValue Cmp;
3913 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3914 if (!isFloatingPointZero(RHS))
3915 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3916 else
3917 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3918 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3919}
3920
3921/// duplicateCmp - Glue values can have only one use, so this function
3922/// duplicates a comparison node.
3923SDValue
3924ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3925 unsigned Opc = Cmp.getOpcode();
3926 SDLoc DL(Cmp);
3927 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3928 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3929
3930 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3930, __PRETTY_FUNCTION__))
;
3931 Cmp = Cmp.getOperand(0);
3932 Opc = Cmp.getOpcode();
3933 if (Opc == ARMISD::CMPFP)
3934 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3935 Cmp.getOperand(1), Cmp.getOperand(2));
3936 else {
3937 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3937, __PRETTY_FUNCTION__))
;
3938 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3939 Cmp.getOperand(1));
3940 }
3941 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3942}
3943
3944// This function returns three things: the arithmetic computation itself
3945// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3946// comparison and the condition code define the case in which the arithmetic
3947// computation *does not* overflow.
3948std::pair<SDValue, SDValue>
3949ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3950 SDValue &ARMcc) const {
3951 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3951, __PRETTY_FUNCTION__))
;
3952
3953 SDValue Value, OverflowCmp;
3954 SDValue LHS = Op.getOperand(0);
3955 SDValue RHS = Op.getOperand(1);
3956 SDLoc dl(Op);
3957
3958 // FIXME: We are currently always generating CMPs because we don't support
3959 // generating CMN through the backend. This is not as good as the natural
3960 // CMP case because it causes a register dependency and cannot be folded
3961 // later.
3962
3963 switch (Op.getOpcode()) {
3964 default:
3965 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 3965)
;
3966 case ISD::SADDO:
3967 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3968 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3969 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3970 break;
3971 case ISD::UADDO:
3972 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3973 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3974 // We do not use it in the USUBO case as Value may not be used.
3975 Value = DAG.getNode(ARMISD::ADDC, dl,
3976 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3977 .getValue(0);
3978 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3979 break;
3980 case ISD::SSUBO:
3981 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3982 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3983 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3984 break;
3985 case ISD::USUBO:
3986 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3987 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3988 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3989 break;
3990 case ISD::UMULO:
3991 // We generate a UMUL_LOHI and then check if the high word is 0.
3992 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3993 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3994 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3995 LHS, RHS);
3996 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3997 DAG.getConstant(0, dl, MVT::i32));
3998 Value = Value.getValue(0); // We only want the low 32 bits for the result.
3999 break;
4000 case ISD::SMULO:
4001 // We generate a SMUL_LOHI and then check if all the bits of the high word
4002 // are the same as the sign bit of the low word.
4003 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4004 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4005 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4006 LHS, RHS);
4007 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4008 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4009 Value.getValue(0),
4010 DAG.getConstant(31, dl, MVT::i32)));
4011 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4012 break;
4013 } // switch (...)
4014
4015 return std::make_pair(Value, OverflowCmp);
4016}
4017
4018SDValue
4019ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4020 // Let legalize expand this if it isn't a legal type yet.
4021 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4022 return SDValue();
4023
4024 SDValue Value, OverflowCmp;
4025 SDValue ARMcc;
4026 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4027 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4028 SDLoc dl(Op);
4029 // We use 0 and 1 as false and true values.
4030 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4031 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4032 EVT VT = Op.getValueType();
4033
4034 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4035 ARMcc, CCR, OverflowCmp);
4036
4037 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4038 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4039}
4040
4041static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4042 SelectionDAG &DAG) {
4043 SDLoc DL(BoolCarry);
4044 EVT CarryVT = BoolCarry.getValueType();
4045
4046 // This converts the boolean value carry into the carry flag by doing
4047 // ARMISD::SUBC Carry, 1
4048 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4049 DAG.getVTList(CarryVT, MVT::i32),
4050 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4051 return Carry.getValue(1);
4052}
4053
4054static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4055 SelectionDAG &DAG) {
4056 SDLoc DL(Flags);
4057
4058 // Now convert the carry flag into a boolean carry. We do this
4059 // using ARMISD:ADDE 0, 0, Carry
4060 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4061 DAG.getConstant(0, DL, MVT::i32),
4062 DAG.getConstant(0, DL, MVT::i32), Flags);
4063}
4064
4065SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 // Let legalize expand this if it isn't a legal type yet.
4068 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4069 return SDValue();
4070
4071 SDValue LHS = Op.getOperand(0);
4072 SDValue RHS = Op.getOperand(1);
4073 SDLoc dl(Op);
4074
4075 EVT VT = Op.getValueType();
4076 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4077 SDValue Value;
4078 SDValue Overflow;
4079 switch (Op.getOpcode()) {
4080 default:
4081 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4081)
;
4082 case ISD::UADDO:
4083 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4084 // Convert the carry flag into a boolean value.
4085 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4086 break;
4087 case ISD::USUBO: {
4088 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4089 // Convert the carry flag into a boolean value.
4090 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4091 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4092 // value. So compute 1 - C.
4093 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4094 DAG.getConstant(1, dl, MVT::i32), Overflow);
4095 break;
4096 }
4097 }
4098
4099 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4100}
4101
4102SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4103 SDValue Cond = Op.getOperand(0);
4104 SDValue SelectTrue = Op.getOperand(1);
4105 SDValue SelectFalse = Op.getOperand(2);
4106 SDLoc dl(Op);
4107 unsigned Opc = Cond.getOpcode();
4108
4109 if (Cond.getResNo() == 1 &&
4110 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4111 Opc == ISD::USUBO)) {
4112 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4113 return SDValue();
4114
4115 SDValue Value, OverflowCmp;
4116 SDValue ARMcc;
4117 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4118 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4119 EVT VT = Op.getValueType();
4120
4121 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4122 OverflowCmp, DAG);
4123 }
4124
4125 // Convert:
4126 //
4127 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4128 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4129 //
4130 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4131 const ConstantSDNode *CMOVTrue =
4132 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4133 const ConstantSDNode *CMOVFalse =
4134 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4135
4136 if (CMOVTrue && CMOVFalse) {
4137 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4138 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4139
4140 SDValue True;
4141 SDValue False;
4142 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4143 True = SelectTrue;
4144 False = SelectFalse;
4145 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4146 True = SelectFalse;
4147 False = SelectTrue;
4148 }
4149
4150 if (True.getNode() && False.getNode()) {
4151 EVT VT = Op.getValueType();
4152 SDValue ARMcc = Cond.getOperand(2);
4153 SDValue CCR = Cond.getOperand(3);
4154 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4155 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __PRETTY_FUNCTION__))
;
4156 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4157 }
4158 }
4159 }
4160
4161 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4162 // undefined bits before doing a full-word comparison with zero.
4163 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4164 DAG.getConstant(1, dl, Cond.getValueType()));
4165
4166 return DAG.getSelectCC(dl, Cond,
4167 DAG.getConstant(0, dl, Cond.getValueType()),
4168 SelectTrue, SelectFalse, ISD::SETNE);
4169}
4170
4171static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4172 bool &swpCmpOps, bool &swpVselOps) {
4173 // Start by selecting the GE condition code for opcodes that return true for
4174 // 'equality'
4175 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4176 CC == ISD::SETULE)
4177 CondCode = ARMCC::GE;
4178
4179 // and GT for opcodes that return false for 'equality'.
4180 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4181 CC == ISD::SETULT)
4182 CondCode = ARMCC::GT;
4183
4184 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4185 // to swap the compare operands.
4186 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4187 CC == ISD::SETULT)
4188 swpCmpOps = true;
4189
4190 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4191 // If we have an unordered opcode, we need to swap the operands to the VSEL
4192 // instruction (effectively negating the condition).
4193 //
4194 // This also has the effect of swapping which one of 'less' or 'greater'
4195 // returns true, so we also swap the compare operands. It also switches
4196 // whether we return true for 'equality', so we compensate by picking the
4197 // opposite condition code to our original choice.
4198 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4199 CC == ISD::SETUGT) {
4200 swpCmpOps = !swpCmpOps;
4201 swpVselOps = !swpVselOps;
4202 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4203 }
4204
4205 // 'ordered' is 'anything but unordered', so use the VS condition code and
4206 // swap the VSEL operands.
4207 if (CC == ISD::SETO) {
4208 CondCode = ARMCC::VS;
4209 swpVselOps = true;
4210 }
4211
4212 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4213 // code and swap the VSEL operands.
4214 if (CC == ISD::SETUNE) {
4215 CondCode = ARMCC::EQ;
4216 swpVselOps = true;
4217 }
4218}
4219
4220SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4221 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4222 SDValue Cmp, SelectionDAG &DAG) const {
4223 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4224 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4225 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4226 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4227 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4228
4229 SDValue TrueLow = TrueVal.getValue(0);
4230 SDValue TrueHigh = TrueVal.getValue(1);
4231 SDValue FalseLow = FalseVal.getValue(0);
4232 SDValue FalseHigh = FalseVal.getValue(1);
4233
4234 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4235 ARMcc, CCR, Cmp);
4236 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4237 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4238
4239 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4240 } else {
4241 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4242 Cmp);
4243 }
4244}
4245
4246static bool isGTorGE(ISD::CondCode CC) {
4247 return CC == ISD::SETGT || CC == ISD::SETGE;
4248}
4249
4250static bool isLTorLE(ISD::CondCode CC) {
4251 return CC == ISD::SETLT || CC == ISD::SETLE;
4252}
4253
4254// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4255// All of these conditions (and their <= and >= counterparts) will do:
4256// x < k ? k : x
4257// x > k ? x : k
4258// k < x ? x : k
4259// k > x ? k : x
4260static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4261 const SDValue TrueVal, const SDValue FalseVal,
4262 const ISD::CondCode CC, const SDValue K) {
4263 return (isGTorGE(CC) &&
4264 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4265 (isLTorLE(CC) &&
4266 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4267}
4268
4269// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4270static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4271 const SDValue TrueVal, const SDValue FalseVal,
4272 const ISD::CondCode CC, const SDValue K) {
4273 return (isGTorGE(CC) &&
4274 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4275 (isLTorLE(CC) &&
4276 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4277}
4278
4279// Check if two chained conditionals could be converted into SSAT or USAT.
4280//
4281// SSAT can replace a set of two conditional selectors that bound a number to an
4282// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4283//
4284// x < -k ? -k : (x > k ? k : x)
4285// x < -k ? -k : (x < k ? x : k)
4286// x > -k ? (x > k ? k : x) : -k
4287// x < k ? (x < -k ? -k : x) : k
4288// etc.
4289//
4290// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4291// a power of 2.
4292//
4293// It returns true if the conversion can be done, false otherwise.
4294// Additionally, the variable is returned in parameter V, the constant in K and
4295// usat is set to true if the conditional represents an unsigned saturation
4296static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4297 uint64_t &K, bool &usat) {
4298 SDValue LHS1 = Op.getOperand(0);
4299 SDValue RHS1 = Op.getOperand(1);
4300 SDValue TrueVal1 = Op.getOperand(2);
4301 SDValue FalseVal1 = Op.getOperand(3);
4302 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4303
4304 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4305 if (Op2.getOpcode() != ISD::SELECT_CC)
4306 return false;
4307
4308 SDValue LHS2 = Op2.getOperand(0);
4309 SDValue RHS2 = Op2.getOperand(1);
4310 SDValue TrueVal2 = Op2.getOperand(2);
4311 SDValue FalseVal2 = Op2.getOperand(3);
4312 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4313
4314 // Find out which are the constants and which are the variables
4315 // in each conditional
4316 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4317 ? &RHS1
4318 : nullptr;
4319 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4320 ? &RHS2
4321 : nullptr;
4322 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4323 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4324 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4325 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4326
4327 // We must detect cases where the original operations worked with 16- or
4328 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4329 // must work with sign-extended values but the select operations return
4330 // the original non-extended value.
4331 SDValue V2TmpReg = V2Tmp;
4332 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4333 V2TmpReg = V2Tmp->getOperand(0);
4334
4335 // Check that the registers and the constants have the correct values
4336 // in both conditionals
4337 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4338 V2TmpReg != V2)
4339 return false;
4340
4341 // Figure out which conditional is saturating the lower/upper bound.
4342 const SDValue *LowerCheckOp =
4343 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4344 ? &Op
4345 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4346 ? &Op2
4347 : nullptr;
4348 const SDValue *UpperCheckOp =
4349 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4350 ? &Op
4351 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4352 ? &Op2
4353 : nullptr;
4354
4355 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4356 return false;
4357
4358 // Check that the constant in the lower-bound check is
4359 // the opposite of the constant in the upper-bound check
4360 // in 1's complement.
4361 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4362 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4363 int64_t PosVal = std::max(Val1, Val2);
4364 int64_t NegVal = std::min(Val1, Val2);
4365
4366 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4367 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4368 isPowerOf2_64(PosVal + 1)) {
4369
4370 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4371 if (Val1 == ~Val2)
4372 usat = false;
4373 else if (NegVal == 0)
4374 usat = true;
4375 else
4376 return false;
4377
4378 V = V2;
4379 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4380
4381 return true;
4382 }
4383
4384 return false;
4385}
4386
4387// Check if a condition of the type x < k ? k : x can be converted into a
4388// bit operation instead of conditional moves.
4389// Currently this is allowed given:
4390// - The conditions and values match up
4391// - k is 0 or -1 (all ones)
4392// This function will not check the last condition, thats up to the caller
4393// It returns true if the transformation can be made, and in such case
4394// returns x in V, and k in SatK.
4395static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4396 SDValue &SatK)
4397{
4398 SDValue LHS = Op.getOperand(0);
4399 SDValue RHS = Op.getOperand(1);
4400 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4401 SDValue TrueVal = Op.getOperand(2);
4402 SDValue FalseVal = Op.getOperand(3);
4403
4404 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4405 ? &RHS
4406 : nullptr;
4407
4408 // No constant operation in comparison, early out
4409 if (!K)
4410 return false;
4411
4412 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4413 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4414 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4415
4416 // If the constant on left and right side, or variable on left and right,
4417 // does not match, early out
4418 if (*K != KTmp || V != VTmp)
4419 return false;
4420
4421 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4422 SatK = *K;
4423 return true;
4424 }
4425
4426 return false;
4427}
4428
4429SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4430 EVT VT = Op.getValueType();
4431 SDLoc dl(Op);
4432
4433 // Try to convert two saturating conditional selects into a single SSAT
4434 SDValue SatValue;
4435 uint64_t SatConstant;
4436 bool SatUSat;
4437 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4438 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4439 if (SatUSat)
4440 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4441 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4442 else
4443 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4444 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4445 }
4446
4447 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4448 // into more efficient bit operations, which is possible when k is 0 or -1
4449 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4450 // single instructions. On Thumb the shift and the bit operation will be two
4451 // instructions.
4452 // Only allow this transformation on full-width (32-bit) operations
4453 SDValue LowerSatConstant;
4454 if (VT == MVT::i32 &&
4455 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4456 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4457 DAG.getConstant(31, dl, VT));
4458 if (isNullConstant(LowerSatConstant)) {
4459 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4460 DAG.getAllOnesConstant(dl, VT));
4461 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4462 } else if (isAllOnesConstant(LowerSatConstant))
4463 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4464 }
4465
4466 SDValue LHS = Op.getOperand(0);
4467 SDValue RHS = Op.getOperand(1);
4468 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4469 SDValue TrueVal = Op.getOperand(2);
4470 SDValue FalseVal = Op.getOperand(3);
4471
4472 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4473 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4474 dl);
4475
4476 // If softenSetCCOperands only returned one value, we should compare it to
4477 // zero.
4478 if (!RHS.getNode()) {
4479 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4480 CC = ISD::SETNE;
4481 }
4482 }
4483
4484 if (LHS.getValueType() == MVT::i32) {
4485 // Try to generate VSEL on ARMv8.
4486 // The VSEL instruction can't use all the usual ARM condition
4487 // codes: it only has two bits to select the condition code, so it's
4488 // constrained to use only GE, GT, VS and EQ.
4489 //
4490 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4491 // swap the operands of the previous compare instruction (effectively
4492 // inverting the compare condition, swapping 'less' and 'greater') and
4493 // sometimes need to swap the operands to the VSEL (which inverts the
4494 // condition in the sense of firing whenever the previous condition didn't)
4495 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4496 TrueVal.getValueType() == MVT::f64)) {
4497 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4498 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4499 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4500 CC = ISD::getSetCCInverse(CC, true);
4501 std::swap(TrueVal, FalseVal);
4502 }
4503 }
4504
4505 SDValue ARMcc;
4506 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4507 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4508 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4509 }
4510
4511 ARMCC::CondCodes CondCode, CondCode2;
4512 bool InvalidOnQNaN;
4513 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4514
4515 // Normalize the fp compare. If RHS is zero we keep it there so we match
4516 // CMPFPw0 instead of CMPFP.
4517 if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
4518 (TrueVal.getValueType() == MVT::f16 ||
4519 TrueVal.getValueType() == MVT::f32 ||
4520 TrueVal.getValueType() == MVT::f64)) {
4521 bool swpCmpOps = false;
4522 bool swpVselOps = false;
4523 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4524
4525 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4526 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4527 if (swpCmpOps)
4528 std::swap(LHS, RHS);
4529 if (swpVselOps)
4530 std::swap(TrueVal, FalseVal);
4531 }
4532 }
4533
4534 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4535 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4536 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4537 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4538 if (CondCode2 != ARMCC::AL) {
4539 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4540 // FIXME: Needs another CMP because flag can have but one use.
4541 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4542 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4543 }
4544 return Result;
4545}
4546
4547/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4548/// to morph to an integer compare sequence.
4549static bool canChangeToInt(SDValue Op, bool &SeenZero,
4550 const ARMSubtarget *Subtarget) {
4551 SDNode *N = Op.getNode();
4552 if (!N->hasOneUse())
4553 // Otherwise it requires moving the value from fp to integer registers.
4554 return false;
4555 if (!N->getNumValues())
4556 return false;
4557 EVT VT = Op.getValueType();
4558 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4559 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4560 // vmrs are very slow, e.g. cortex-a8.
4561 return false;
4562
4563 if (isFloatingPointZero(Op)) {
4564 SeenZero = true;
4565 return true;
4566 }
4567 return ISD::isNormalLoad(N);
4568}
4569
4570static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4571 if (isFloatingPointZero(Op))
4572 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4573
4574 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4575 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4576 Ld->getPointerInfo(), Ld->getAlignment(),
4577 Ld->getMemOperand()->getFlags());
4578
4579 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4579)
;
4580}
4581
4582static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4583 SDValue &RetVal1, SDValue &RetVal2) {
4584 SDLoc dl(Op);
4585
4586 if (isFloatingPointZero(Op)) {
4587 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4588 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4589 return;
4590 }
4591
4592 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4593 SDValue Ptr = Ld->getBasePtr();
4594 RetVal1 =
4595 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4596 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4597
4598 EVT PtrType = Ptr.getValueType();
4599 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4600 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4601 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4602 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4603 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4604 Ld->getMemOperand()->getFlags());
4605 return;
4606 }
4607
4608 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4608)
;
4609}
4610
4611/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4612/// f32 and even f64 comparisons to integer ones.
4613SDValue
4614ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4615 SDValue Chain = Op.getOperand(0);
4616 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4617 SDValue LHS = Op.getOperand(2);
4618 SDValue RHS = Op.getOperand(3);
4619 SDValue Dest = Op.getOperand(4);
4620 SDLoc dl(Op);
4621
4622 bool LHSSeenZero = false;
4623 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4624 bool RHSSeenZero = false;
4625 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4626 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4627 // If unsafe fp math optimization is enabled and there are no other uses of
4628 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4629 // to an integer comparison.
4630 if (CC == ISD::SETOEQ)
4631 CC = ISD::SETEQ;
4632 else if (CC == ISD::SETUNE)
4633 CC = ISD::SETNE;
4634
4635 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4636 SDValue ARMcc;
4637 if (LHS.getValueType() == MVT::f32) {
4638 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4639 bitcastf32Toi32(LHS, DAG), Mask);
4640 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4641 bitcastf32Toi32(RHS, DAG), Mask);
4642 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4643 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4644 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4645 Chain, Dest, ARMcc, CCR, Cmp);
4646 }
4647
4648 SDValue LHS1, LHS2;
4649 SDValue RHS1, RHS2;
4650 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4651 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4652 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4653 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4654 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4655 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4656 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4657 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4658 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4659 }
4660
4661 return SDValue();
4662}
4663
4664SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4665 SDValue Chain = Op.getOperand(0);
4666 SDValue Cond = Op.getOperand(1);
4667 SDValue Dest = Op.getOperand(2);
4668 SDLoc dl(Op);
4669
4670 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4671 // instruction.
4672 unsigned Opc = Cond.getOpcode();
4673 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4674 !Subtarget->isThumb1Only();
4675 if (Cond.getResNo() == 1 &&
4676 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4677 Opc == ISD::USUBO || OptimizeMul)) {
4678 // Only lower legal XALUO ops.
4679 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4680 return SDValue();
4681
4682 // The actual operation with overflow check.
4683 SDValue Value, OverflowCmp;
4684 SDValue ARMcc;
4685 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4686
4687 // Reverse the condition code.
4688 ARMCC::CondCodes CondCode =
4689 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4690 CondCode = ARMCC::getOppositeCondition(CondCode);
4691 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4692 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4693
4694 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4695 OverflowCmp);
4696 }
4697
4698 return SDValue();
4699}
4700
4701SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4702 SDValue Chain = Op.getOperand(0);
4703 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4704 SDValue LHS = Op.getOperand(2);
4705 SDValue RHS = Op.getOperand(3);
4706 SDValue Dest = Op.getOperand(4);
4707 SDLoc dl(Op);
4708
4709 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4710 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4711 dl);
4712
4713 // If softenSetCCOperands only returned one value, we should compare it to
4714 // zero.
4715 if (!RHS.getNode()) {
4716 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4717 CC = ISD::SETNE;
4718 }
4719 }
4720
4721 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4722 // instruction.
4723 unsigned Opc = LHS.getOpcode();
4724 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4725 !Subtarget->isThumb1Only();
4726 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4727 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4728 Opc == ISD::USUBO || OptimizeMul) &&
4729 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4730 // Only lower legal XALUO ops.
4731 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4732 return SDValue();
4733
4734 // The actual operation with overflow check.
4735 SDValue Value, OverflowCmp;
4736 SDValue ARMcc;
4737 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4738
4739 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4740 // Reverse the condition code.
4741 ARMCC::CondCodes CondCode =
4742 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4743 CondCode = ARMCC::getOppositeCondition(CondCode);
4744 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4745 }
4746 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4747
4748 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4749 OverflowCmp);
4750 }
4751
4752 if (LHS.getValueType() == MVT::i32) {
4753 SDValue ARMcc;
4754 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4755 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4756 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4757 Chain, Dest, ARMcc, CCR, Cmp);
4758 }
4759
4760 if (getTargetMachine().Options.UnsafeFPMath &&
4761 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4762 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4763 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4764 return Result;
4765 }
4766
4767 ARMCC::CondCodes CondCode, CondCode2;
4768 bool InvalidOnQNaN;
4769 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4770
4771 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4772 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4773 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4774 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4775 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4776 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4777 if (CondCode2 != ARMCC::AL) {
4778 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4779 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4780 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4781 }
4782 return Res;
4783}
4784
4785SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4786 SDValue Chain = Op.getOperand(0);
4787 SDValue Table = Op.getOperand(1);
4788 SDValue Index = Op.getOperand(2);
4789 SDLoc dl(Op);
4790
4791 EVT PTy = getPointerTy(DAG.getDataLayout());
4792 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4793 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4794 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4795 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4796 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4797 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4798 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4799 // which does another jump to the destination. This also makes it easier
4800 // to translate it to TBB / TBH later (Thumb2 only).
4801 // FIXME: This might not work if the function is extremely large.
4802 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4803 Addr, Op.getOperand(2), JTI);
4804 }
4805 if (isPositionIndependent() || Subtarget->isROPI()) {
4806 Addr =
4807 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4808 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4809 Chain = Addr.getValue(1);
4810 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4811 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4812 } else {
4813 Addr =
4814 DAG.getLoad(PTy, dl, Chain, Addr,
4815 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4816 Chain = Addr.getValue(1);
4817 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4818 }
4819}
4820
4821static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4822 EVT VT = Op.getValueType();
4823 SDLoc dl(Op);
4824
4825 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4826 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4827 return Op;
4828 return DAG.UnrollVectorOp(Op.getNode());
4829 }
4830
4831 const bool HasFullFP16 =
4832 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4833
4834 EVT NewTy;
4835 const EVT OpTy = Op.getOperand(0).getValueType();
4836 if (OpTy == MVT::v4f32)
4837 NewTy = MVT::v4i32;
4838 else if (OpTy == MVT::v4f16 && HasFullFP16)
4839 NewTy = MVT::v4i16;
4840 else if (OpTy == MVT::v8f16 && HasFullFP16)
4841 NewTy = MVT::v8i16;
4842 else
4843 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4843)
;
4844
4845 if (VT != MVT::v4i16 && VT != MVT::v8i16)
4846 return DAG.UnrollVectorOp(Op.getNode());
4847
4848 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
4849 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4850}
4851
4852SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4853 EVT VT = Op.getValueType();
4854 if (VT.isVector())
4855 return LowerVectorFP_TO_INT(Op, DAG);
4856 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4857 RTLIB::Libcall LC;
4858 if (Op.getOpcode() == ISD::FP_TO_SINT)
4859 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4860 Op.getValueType());
4861 else
4862 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4863 Op.getValueType());
4864 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4865 /*isSigned*/ false, SDLoc(Op)).first;
4866 }
4867
4868 return Op;
4869}
4870
4871static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4872 EVT VT = Op.getValueType();
4873 SDLoc dl(Op);
4874
4875 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4876 if (VT.getVectorElementType() == MVT::f32)
4877 return Op;
4878 return DAG.UnrollVectorOp(Op.getNode());
4879 }
4880
4881 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4883, __PRETTY_FUNCTION__))
4882 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4883, __PRETTY_FUNCTION__))
4883 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4883, __PRETTY_FUNCTION__))
;
4884
4885 const bool HasFullFP16 =
4886 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4887
4888 EVT DestVecType;
4889 if (VT == MVT::v4f32)
4890 DestVecType = MVT::v4i32;
4891 else if (VT == MVT::v4f16 && HasFullFP16)
4892 DestVecType = MVT::v4i16;
4893 else if (VT == MVT::v8f16 && HasFullFP16)
4894 DestVecType = MVT::v8i16;
4895 else
4896 return DAG.UnrollVectorOp(Op.getNode());
4897
4898 unsigned CastOpc;
4899 unsigned Opc;
4900 switch (Op.getOpcode()) {
4901 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 4901)
;
4902 case ISD::SINT_TO_FP:
4903 CastOpc = ISD::SIGN_EXTEND;
4904 Opc = ISD::SINT_TO_FP;
4905 break;
4906 case ISD::UINT_TO_FP:
4907 CastOpc = ISD::ZERO_EXTEND;
4908 Opc = ISD::UINT_TO_FP;
4909 break;
4910 }
4911
4912 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
4913 return DAG.getNode(Opc, dl, VT, Op);
4914}
4915
4916SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4917 EVT VT = Op.getValueType();
4918 if (VT.isVector())
4919 return LowerVectorINT_TO_FP(Op, DAG);
4920 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4921 RTLIB::Libcall LC;
4922 if (Op.getOpcode() == ISD::SINT_TO_FP)
4923 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4924 Op.getValueType());
4925 else
4926 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4927 Op.getValueType());
4928 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4929 /*isSigned*/ false, SDLoc(Op)).first;
4930 }
4931
4932 return Op;
4933}
4934
4935SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4936 // Implement fcopysign with a fabs and a conditional fneg.
4937 SDValue Tmp0 = Op.getOperand(0);
4938 SDValue Tmp1 = Op.getOperand(1);
4939 SDLoc dl(Op);
4940 EVT VT = Op.getValueType();
4941 EVT SrcVT = Tmp1.getValueType();
4942 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4943 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4944 bool UseNEON = !InGPR && Subtarget->hasNEON();
4945
4946 if (UseNEON) {
4947 // Use VBSL to copy the sign bit.
4948 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4949 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4950 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4951 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4952 if (VT == MVT::f64)
4953 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4954 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4955 DAG.getConstant(32, dl, MVT::i32));
4956 else /*if (VT == MVT::f32)*/
4957 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4958 if (SrcVT == MVT::f32) {
4959 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4960 if (VT == MVT::f64)
4961 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4962 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4963 DAG.getConstant(32, dl, MVT::i32));
4964 } else if (VT == MVT::f32)
4965 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4966 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4967 DAG.getConstant(32, dl, MVT::i32));
4968 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4969 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4970
4971 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4972 dl, MVT::i32);
4973 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4974 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4975 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4976
4977 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4978 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4979 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4980 if (VT == MVT::f32) {
4981 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4982 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4983 DAG.getConstant(0, dl, MVT::i32));
4984 } else {
4985 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4986 }
4987
4988 return Res;
4989 }
4990
4991 // Bitcast operand 1 to i32.
4992 if (SrcVT == MVT::f64)
4993 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4994 Tmp1).getValue(1);
4995 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4996
4997 // Or in the signbit with integer operations.
4998 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4999 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5000 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5001 if (VT == MVT::f32) {
5002 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5003 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5004 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5005 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5006 }
5007
5008 // f64: Or the high part with signbit and then combine two parts.
5009 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5010 Tmp0);
5011 SDValue Lo = Tmp0.getValue(0);
5012 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5013 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5014 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5015}
5016
5017SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5018 MachineFunction &MF = DAG.getMachineFunction();
5019 MachineFrameInfo &MFI = MF.getFrameInfo();
5020 MFI.setReturnAddressIsTaken(true);
5021
5022 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5023 return SDValue();
5024
5025 EVT VT = Op.getValueType();
5026 SDLoc dl(Op);
5027 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5028 if (Depth) {
5029 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5030 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5031 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5032 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5033 MachinePointerInfo());
5034 }
5035
5036 // Return LR, which contains the return address. Mark it an implicit live-in.
5037 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5038 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5039}
5040
5041SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5042 const ARMBaseRegisterInfo &ARI =
5043 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5044 MachineFunction &MF = DAG.getMachineFunction();
5045 MachineFrameInfo &MFI = MF.getFrameInfo();
5046 MFI.setFrameAddressIsTaken(true);
5047
5048 EVT VT = Op.getValueType();
5049 SDLoc dl(Op); // FIXME probably not meaningful
5050 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5051 unsigned FrameReg = ARI.getFrameRegister(MF);
5052 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5053 while (Depth--)
5054 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5055 MachinePointerInfo());
5056 return FrameAddr;
5057}
5058
5059// FIXME? Maybe this could be a TableGen attribute on some registers and
5060// this table could be generated automatically from RegInfo.
5061unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5062 SelectionDAG &DAG) const {
5063 unsigned Reg = StringSwitch<unsigned>(RegName)
5064 .Case("sp", ARM::SP)
5065 .Default(0);
5066 if (Reg)
5067 return Reg;
5068 report_fatal_error(Twine("Invalid register name \""
5069 + StringRef(RegName) + "\"."));
5070}
5071
5072// Result is 64 bit value so split into two 32 bit values and return as a
5073// pair of values.
5074static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5075 SelectionDAG &DAG) {
5076 SDLoc DL(N);
5077
5078 // This function is only supposed to be called for i64 type destination.
5079 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5080, __PRETTY_FUNCTION__))
5080 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5080, __PRETTY_FUNCTION__))
;
5081
5082 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5083 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5084 N->getOperand(0),
5085 N->getOperand(1));
5086
5087 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5088 Read.getValue(1)));
5089 Results.push_back(Read.getOperand(0));
5090}
5091
5092/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5093/// When \p DstVT, the destination type of \p BC, is on the vector
5094/// register bank and the source of bitcast, \p Op, operates on the same bank,
5095/// it might be possible to combine them, such that everything stays on the
5096/// vector register bank.
5097/// \p return The node that would replace \p BT, if the combine
5098/// is possible.
5099static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5100 SelectionDAG &DAG) {
5101 SDValue Op = BC->getOperand(0);
5102 EVT DstVT = BC->getValueType(0);
5103
5104 // The only vector instruction that can produce a scalar (remember,
5105 // since the bitcast was about to be turned into VMOVDRR, the source
5106 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5107 // Moreover, we can do this combine only if there is one use.
5108 // Finally, if the destination type is not a vector, there is not
5109 // much point on forcing everything on the vector bank.
5110 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5111 !Op.hasOneUse())
5112 return SDValue();
5113
5114 // If the index is not constant, we will introduce an additional
5115 // multiply that will stick.
5116 // Give up in that case.
5117 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5118 if (!Index)
5119 return SDValue();
5120 unsigned DstNumElt = DstVT.getVectorNumElements();
5121
5122 // Compute the new index.
5123 const APInt &APIntIndex = Index->getAPIntValue();
5124 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5125 NewIndex *= APIntIndex;
5126 // Check if the new constant index fits into i32.
5127 if (NewIndex.getBitWidth() > 32)
5128 return SDValue();
5129
5130 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5131 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5132 SDLoc dl(Op);
5133 SDValue ExtractSrc = Op.getOperand(0);
5134 EVT VecVT = EVT::getVectorVT(
5135 *DAG.getContext(), DstVT.getScalarType(),
5136 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5137 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5138 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5139 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5140}
5141
5142/// ExpandBITCAST - If the target supports VFP, this function is called to
5143/// expand a bit convert where either the source or destination type is i64 to
5144/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5145/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5146/// vectors), since the legalizer won't know what to do with that.
5147static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5148 const ARMSubtarget *Subtarget) {
5149 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5150 SDLoc dl(N);
5151 SDValue Op = N->getOperand(0);
5152
5153 // This function is only supposed to be called for i64 types, either as the
5154 // source or destination of the bit convert.
5155 EVT SrcVT = Op.getValueType();
5156 EVT DstVT = N->getValueType(0);
5157 const bool HasFullFP16 = Subtarget->hasFullFP16();
5158
5159 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5160 // FullFP16: half values are passed in S-registers, and we don't
5161 // need any of the bitcast and moves:
5162 //
5163 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5164 // t5: i32 = bitcast t2
5165 // t18: f16 = ARMISD::VMOVhr t5
5166 if (Op.getOpcode() != ISD::CopyFromReg ||
5167 Op.getValueType() != MVT::f32)
5168 return SDValue();
5169
5170 auto Move = N->use_begin();
5171 if (Move->getOpcode() != ARMISD::VMOVhr)
5172 return SDValue();
5173
5174 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5175 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5176 DAG.ReplaceAllUsesWith(*Move, &Copy);
5177 return Copy;
5178 }
5179
5180 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5181 if (!HasFullFP16)
5182 return SDValue();
5183 // SoftFP: read half-precision arguments:
5184 //
5185 // t2: i32,ch = ...
5186 // t7: i16 = truncate t2 <~~~~ Op
5187 // t8: f16 = bitcast t7 <~~~~ N
5188 //
5189 if (Op.getOperand(0).getValueType() == MVT::i32)
5190 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5191 MVT::f16, Op.getOperand(0));
5192
5193 return SDValue();
5194 }
5195
5196 // Half-precision return values
5197 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5198 if (!HasFullFP16)
5199 return SDValue();
5200 //
5201 // t11: f16 = fadd t8, t10
5202 // t12: i16 = bitcast t11 <~~~ SDNode N
5203 // t13: i32 = zero_extend t12
5204 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5205 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5206 //
5207 // transform this into:
5208 //
5209 // t20: i32 = ARMISD::VMOVrh t11
5210 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5211 //
5212 auto ZeroExtend = N->use_begin();
5213 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5214 ZeroExtend->getValueType(0) != MVT::i32)
5215 return SDValue();
5216
5217 auto Copy = ZeroExtend->use_begin();
5218 if (Copy->getOpcode() == ISD::CopyToReg &&
5219 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5220 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5221 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5222 return Cvt;
5223 }
5224 return SDValue();
5225 }
5226
5227 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5228 return SDValue();
5229
5230 // Turn i64->f64 into VMOVDRR.
5231 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5232 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5233 // if we can combine the bitcast with its source.
5234 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5235 return Val;
5236
5237 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5238 DAG.getConstant(0, dl, MVT::i32));
5239 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5240 DAG.getConstant(1, dl, MVT::i32));
5241 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5242 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5243 }
5244
5245 // Turn f64->i64 into VMOVRRD.
5246 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5247 SDValue Cvt;
5248 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5249 SrcVT.getVectorNumElements() > 1)
5250 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5251 DAG.getVTList(MVT::i32, MVT::i32),
5252 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5253 else
5254 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5255 DAG.getVTList(MVT::i32, MVT::i32), Op);
5256 // Merge the pieces into a single i64 value.
5257 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5258 }
5259
5260 return SDValue();
5261}
5262
5263/// getZeroVector - Returns a vector of specified type with all zero elements.
5264/// Zero vectors are used to represent vector negation and in those cases
5265/// will be implemented with the NEON VNEG instruction. However, VNEG does
5266/// not support i64 elements, so sometimes the zero vectors will need to be
5267/// explicitly constructed. Regardless, use a canonical VMOV to create the
5268/// zero vector.
5269static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5270 assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5270, __PRETTY_FUNCTION__))
;
5271 // The canonical modified immediate encoding of a zero vector is....0!
5272 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5273 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5274 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5275 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5276}
5277
5278/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5279/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5280SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5281 SelectionDAG &DAG) const {
5282 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5282, __PRETTY_FUNCTION__))
;
5283 EVT VT = Op.getValueType();
5284 unsigned VTBits = VT.getSizeInBits();
5285 SDLoc dl(Op);
5286 SDValue ShOpLo = Op.getOperand(0);
5287 SDValue ShOpHi = Op.getOperand(1);
5288 SDValue ShAmt = Op.getOperand(2);
5289 SDValue ARMcc;
5290 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5291 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5292
5293 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::
SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5293, __PRETTY_FUNCTION__))
;
5294
5295 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5296 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5297 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5298 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5299 DAG.getConstant(VTBits, dl, MVT::i32));
5300 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5301 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5302 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5303 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5304 ISD::SETGE, ARMcc, DAG, dl);
5305 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5306 ARMcc, CCR, CmpLo);
5307
5308 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5309 SDValue HiBigShift = Opc == ISD::SRA
5310 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5311 DAG.getConstant(VTBits - 1, dl, VT))
5312 : DAG.getConstant(0, dl, VT);
5313 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5314 ISD::SETGE, ARMcc, DAG, dl);
5315 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5316 ARMcc, CCR, CmpHi);
5317
5318 SDValue Ops[2] = { Lo, Hi };
5319 return DAG.getMergeValues(Ops, dl);
5320}
5321
5322/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5323/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5324SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5325 SelectionDAG &DAG) const {
5326 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5326, __PRETTY_FUNCTION__))
;
5327 EVT VT = Op.getValueType();
5328 unsigned VTBits = VT.getSizeInBits();
5329 SDLoc dl(Op);
5330 SDValue ShOpLo = Op.getOperand(0);
5331 SDValue ShOpHi = Op.getOperand(1);
5332 SDValue ShAmt = Op.getOperand(2);
5333 SDValue ARMcc;
5334 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5335
5336 assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void>
(0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5336, __PRETTY_FUNCTION__))
;
5337 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5338 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5339 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5340 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5341 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5342
5343 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5344 DAG.getConstant(VTBits, dl, MVT::i32));
5345 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5346 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5347 ISD::SETGE, ARMcc, DAG, dl);
5348 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5349 ARMcc, CCR, CmpHi);
5350
5351 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5352 ISD::SETGE, ARMcc, DAG, dl);
5353 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5354 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5355 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5356
5357 SDValue Ops[2] = { Lo, Hi };
5358 return DAG.getMergeValues(Ops, dl);
5359}
5360
5361SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5362 SelectionDAG &DAG) const {
5363 // The rounding mode is in bits 23:22 of the FPSCR.
5364 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5365 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5366 // so that the shift + and get folded into a bitfield extract.
5367 SDLoc dl(Op);
5368 SDValue Ops[] = { DAG.getEntryNode(),
5369 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5370
5371 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5372 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5373 DAG.getConstant(1U << 22, dl, MVT::i32));
5374 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5375 DAG.getConstant(22, dl, MVT::i32));
5376 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5377 DAG.getConstant(3, dl, MVT::i32));
5378}
5379
5380static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5381 const ARMSubtarget *ST) {
5382 SDLoc dl(N);
5383 EVT VT = N->getValueType(0);
5384 if (VT.isVector()) {
5385 assert(ST->hasNEON())((ST->hasNEON()) ? static_cast<void> (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5385, __PRETTY_FUNCTION__))
;
5386
5387 // Compute the least significant set bit: LSB = X & -X
5388 SDValue X = N->getOperand(0);
5389 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5390 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5391
5392 EVT ElemTy = VT.getVectorElementType();
5393
5394 if (ElemTy == MVT::i8) {
5395 // Compute with: cttz(x) = ctpop(lsb - 1)
5396 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5397 DAG.getTargetConstant(1, dl, ElemTy));
5398 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5399 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5400 }
5401
5402 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5403 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5404 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5405 unsigned NumBits = ElemTy.getSizeInBits();
5406 SDValue WidthMinus1 =
5407 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5408 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5409 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5410 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5411 }
5412
5413 // Compute with: cttz(x) = ctpop(lsb - 1)
5414
5415 // Compute LSB - 1.
5416 SDValue Bits;
5417 if (ElemTy == MVT::i64) {
5418 // Load constant 0xffff'ffff'ffff'ffff to register.
5419 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5420 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5421 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5422 } else {
5423 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5424 DAG.getTargetConstant(1, dl, ElemTy));
5425 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5426 }
5427 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5428 }
5429
5430 if (!ST->hasV6T2Ops())
5431 return SDValue();
5432
5433 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5434 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5435}
5436
5437static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5438 const ARMSubtarget *ST) {
5439 EVT VT = N->getValueType(0);
5440 SDLoc DL(N);
5441
5442 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")((ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? static_cast<void> (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5442, __PRETTY_FUNCTION__))
;
5443 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5445, __PRETTY_FUNCTION__))
5444 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5445, __PRETTY_FUNCTION__))
5445 "Unexpected type for custom ctpop lowering")(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5445, __PRETTY_FUNCTION__))
;
5446
5447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5448 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5449 SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0));
5450 Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res);
5451
5452 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
5453 unsigned EltSize = 8;
5454 unsigned NumElts = VT.is64BitVector() ? 8 : 16;
5455 while (EltSize != VT.getScalarSizeInBits()) {
5456 SmallVector<SDValue, 8> Ops;
5457 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddlu, DL,
5458 TLI.getPointerTy(DAG.getDataLayout())));
5459 Ops.push_back(Res);
5460
5461 EltSize *= 2;
5462 NumElts /= 2;
5463 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts);
5464 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops);
5465 }
5466
5467 return Res;
5468}
5469
5470static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5471 const ARMSubtarget *ST) {
5472 EVT VT = N->getValueType(0);
5473 SDLoc dl(N);
5474
5475 if (!VT.isVector())
5476 return SDValue();
5477
5478 // Lower vector shifts on NEON to use VSHL.
5479 assert(ST->hasNEON() && "unexpected vector shift")((ST->hasNEON() && "unexpected vector shift") ? static_cast
<void> (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5479, __PRETTY_FUNCTION__))
;
5480
5481 // Left shifts translate directly to the vshiftu intrinsic.
5482 if (N->getOpcode() == ISD::SHL)
5483 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5484 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5485 MVT::i32),
5486 N->getOperand(0), N->getOperand(1));
5487
5488 assert((N->getOpcode() == ISD::SRA ||(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "unexpected vector shift opcode") ? static_cast
<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5489, __PRETTY_FUNCTION__))
5489 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "unexpected vector shift opcode") ? static_cast
<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5489, __PRETTY_FUNCTION__))
;
5490
5491 // NEON uses the same intrinsics for both left and right shifts. For
5492 // right shifts, the shift amounts are negative, so negate the vector of
5493 // shift amounts.
5494 EVT ShiftVT = N->getOperand(1).getValueType();
5495 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5496 getZeroVector(ShiftVT, DAG, dl),
5497 N->getOperand(1));
5498 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5499 Intrinsic::arm_neon_vshifts :
5500 Intrinsic::arm_neon_vshiftu);
5501 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5502 DAG.getConstant(vshiftInt, dl, MVT::i32),
5503 N->getOperand(0), NegatedCount);
5504}
5505
5506static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5507 const ARMSubtarget *ST) {
5508 EVT VT = N->getValueType(0);
5509 SDLoc dl(N);
5510
5511 // We can get here for a node like i32 = ISD::SHL i32, i64
5512 if (VT != MVT::i64)
5513 return SDValue();
5514
5515 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::
SRA) && "Unknown shift to lower!") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5516, __PRETTY_FUNCTION__))
5516 "Unknown shift to lower!")(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::
SRA) && "Unknown shift to lower!") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5516, __PRETTY_FUNCTION__))
;
5517
5518 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5519 if (!isOneConstant(N->getOperand(1)))
5520 return SDValue();
5521
5522 // If we are in thumb mode, we don't have RRX.
5523 if (ST->isThumb1Only()) return SDValue();
5524
5525 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5526 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5527 DAG.getConstant(0, dl, MVT::i32));
5528 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5529 DAG.getConstant(1, dl, MVT::i32));
5530
5531 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5532 // captures the result into a carry flag.
5533 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5534 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5535
5536 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5537 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5538
5539 // Merge the pieces into a single i64 value.
5540 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5541}
5542
5543static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5544 SDValue TmpOp0, TmpOp1;
5545 bool Invert = false;
5546 bool Swap = false;
5547 unsigned Opc = 0;
5548
5549 SDValue Op0 = Op.getOperand(0);
5550 SDValue Op1 = Op.getOperand(1);
5551 SDValue CC = Op.getOperand(2);
5552 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5553 EVT VT = Op.getValueType();
5554 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5555 SDLoc dl(Op);
5556
5557 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5558 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5559 // Special-case integer 64-bit equality comparisons. They aren't legal,
5560 // but they can be lowered with a few vector instructions.
5561 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5562 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5563 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5564 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5565 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5566 DAG.getCondCode(ISD::SETEQ));
5567 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5568 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5569 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5570 if (SetCCOpcode == ISD::SETNE)
5571 Merged = DAG.getNOT(dl, Merged, CmpVT);
5572 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5573 return Merged;
5574 }
5575
5576 if (CmpVT.getVectorElementType() == MVT::i64)
5577 // 64-bit comparisons are not legal in general.
5578 return SDValue();
5579
5580 if (Op1.getValueType().isFloatingPoint()) {
5581 switch (SetCCOpcode) {
5582 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5582)
;
5583 case ISD::SETUNE:
5584 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5585 case ISD::SETOEQ:
5586 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5587 case ISD::SETOLT:
5588 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5589 case ISD::SETOGT:
5590 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5591 case ISD::SETOLE:
5592 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5593 case ISD::SETOGE:
5594 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5595 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5596 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5597 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5598 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5599 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5600 case ISD::SETONE:
5601 // Expand this to (OLT | OGT).
5602 TmpOp0 = Op0;
5603 TmpOp1 = Op1;
5604 Opc = ISD::OR;
5605 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5606 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5607 break;
5608 case ISD::SETUO:
5609 Invert = true;
5610 LLVM_FALLTHROUGH[[clang::fallthrough]];
5611 case ISD::SETO:
5612 // Expand this to (OLT | OGE).
5613 TmpOp0 = Op0;
5614 TmpOp1 = Op1;
5615 Opc = ISD::OR;
5616 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5617 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5618 break;
5619 }
5620 } else {
5621 // Integer comparisons.
5622 switch (SetCCOpcode) {
5623 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5623)
;
5624 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5625 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5626 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5627 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5628 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5629 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5630 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5631 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5632 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5633 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5634 }
5635
5636 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5637 if (Opc == ARMISD::VCEQ) {
5638 SDValue AndOp;
5639 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5640 AndOp = Op0;
5641 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5642 AndOp = Op1;
5643
5644 // Ignore bitconvert.
5645 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5646 AndOp = AndOp.getOperand(0);
5647
5648 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5649 Opc = ARMISD::VTST;
5650 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5651 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5652 Invert = !Invert;
5653 }
5654 }
5655 }
5656
5657 if (Swap)
5658 std::swap(Op0, Op1);
5659
5660 // If one of the operands is a constant vector zero, attempt to fold the
5661 // comparison to a specialized compare-against-zero form.
5662 SDValue SingleOp;
5663 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5664 SingleOp = Op0;
5665 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5666 if (Opc == ARMISD::VCGE)
5667 Opc = ARMISD::VCLEZ;
5668 else if (Opc == ARMISD::VCGT)
5669 Opc = ARMISD::VCLTZ;
5670 SingleOp = Op1;
5671 }
5672
5673 SDValue Result;
5674 if (SingleOp.getNode()) {
5675 switch (Opc) {
5676 case ARMISD::VCEQ:
5677 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5678 case ARMISD::VCGE:
5679 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5680 case ARMISD::VCLEZ:
5681 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5682 case ARMISD::VCGT:
5683 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5684 case ARMISD::VCLTZ:
5685 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5686 default:
5687 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5688 }
5689 } else {
5690 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5691 }
5692
5693 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5694
5695 if (Invert)
5696 Result = DAG.getNOT(dl, Result, VT);
5697
5698 return Result;
5699}
5700
5701static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
5702 SDValue LHS = Op.getOperand(0);
5703 SDValue RHS = Op.getOperand(1);
5704 SDValue Carry = Op.getOperand(2);
5705 SDValue Cond = Op.getOperand(3);
5706 SDLoc DL(Op);
5707
5708 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.")((LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only."
) ? static_cast<void> (0) : __assert_fail ("LHS.getSimpleValueType().isInteger() && \"SETCCCARRY is integer only.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5708, __PRETTY_FUNCTION__))
;
5709
5710 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
5711 // have to invert the carry first.
5712 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
5713 DAG.getConstant(1, DL, MVT::i32), Carry);
5714 // This converts the boolean value carry into the carry flag.
5715 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
5716
5717 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5718 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5719
5720 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5721 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5722 SDValue ARMcc = DAG.getConstant(
5723 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5724 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5725 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5726 Cmp.getValue(1), SDValue());
5727 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5728 CCR, Chain.getValue(1));
5729}
5730
5731/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5732/// valid vector constant for a NEON instruction with a "modified immediate"
5733/// operand (e.g., VMOV). If so, return the encoded value.
5734static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5735 unsigned SplatBitSize, SelectionDAG &DAG,
5736 const SDLoc &dl, EVT &VT, bool is128Bits,
5737 NEONModImmType type) {
5738 unsigned OpCmode, Imm;
5739
5740 // SplatBitSize is set to the smallest size that splats the vector, so a
5741 // zero vector will always have SplatBitSize == 8. However, NEON modified
5742 // immediate instructions others than VMOV do not support the 8-bit encoding
5743 // of a zero vector, and the default encoding of zero is supposed to be the
5744 // 32-bit version.
5745 if (SplatBits == 0)
5746 SplatBitSize = 32;
5747
5748 switch (SplatBitSize) {
5749 case 8:
5750 if (type != VMOVModImm)
5751 return SDValue();
5752 // Any 1-byte value is OK. Op=0, Cmode=1110.
5753 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(((SplatBits & ~0xff) == 0 && "one byte splat value is too big"
) ? static_cast<void> (0) : __assert_fail ("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5753, __PRETTY_FUNCTION__))
;
5754 OpCmode = 0xe;
5755 Imm = SplatBits;
5756 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5757 break;
5758
5759 case 16:
5760 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5761 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5762 if ((SplatBits & ~0xff) == 0) {
5763 // Value = 0x00nn: Op=x, Cmode=100x.
5764 OpCmode = 0x8;
5765 Imm = SplatBits;
5766 break;
5767 }
5768 if ((SplatBits & ~0xff00) == 0) {
5769 // Value = 0xnn00: Op=x, Cmode=101x.
5770 OpCmode = 0xa;
5771 Imm = SplatBits >> 8;
5772 break;
5773 }
5774 return SDValue();
5775
5776 case 32:
5777 // NEON's 32-bit VMOV supports splat values where:
5778 // * only one byte is nonzero, or
5779 // * the least significant byte is 0xff and the second byte is nonzero, or
5780 // * the least significant 2 bytes are 0xff and the third is nonzero.
5781 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5782 if ((SplatBits & ~0xff) == 0) {
5783 // Value = 0x000000nn: Op=x, Cmode=000x.
5784 OpCmode = 0;
5785 Imm = SplatBits;
5786 break;
5787 }
5788 if ((SplatBits & ~0xff00) == 0) {
5789 // Value = 0x0000nn00: Op=x, Cmode=001x.
5790 OpCmode = 0x2;
5791 Imm = SplatBits >> 8;
5792 break;
5793 }
5794 if ((SplatBits & ~0xff0000) == 0) {
5795 // Value = 0x00nn0000: Op=x, Cmode=010x.
5796 OpCmode = 0x4;
5797 Imm = SplatBits >> 16;
5798 break;
5799 }
5800 if ((SplatBits & ~0xff000000) == 0) {
5801 // Value = 0xnn000000: Op=x, Cmode=011x.
5802 OpCmode = 0x6;
5803 Imm = SplatBits >> 24;
5804 break;
5805 }
5806
5807 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5808 if (type == OtherModImm) return SDValue();
5809
5810 if ((SplatBits & ~0xffff) == 0 &&
5811 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5812 // Value = 0x0000nnff: Op=x, Cmode=1100.
5813 OpCmode = 0xc;
5814 Imm = SplatBits >> 8;
5815 break;
5816 }
5817
5818 if ((SplatBits & ~0xffffff) == 0 &&
5819 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5820 // Value = 0x00nnffff: Op=x, Cmode=1101.
5821 OpCmode = 0xd;
5822 Imm = SplatBits >> 16;
5823 break;
5824 }
5825
5826 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5827 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5828 // VMOV.I32. A (very) minor optimization would be to replicate the value
5829 // and fall through here to test for a valid 64-bit splat. But, then the
5830 // caller would also need to check and handle the change in size.
5831 return SDValue();
5832
5833 case 64: {
5834 if (type != VMOVModImm)
5835 return SDValue();
5836 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5837 uint64_t BitMask = 0xff;
5838 uint64_t Val = 0;
5839 unsigned ImmMask = 1;
5840 Imm = 0;
5841 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5842 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5843 Val |= BitMask;
5844 Imm |= ImmMask;
5845 } else if ((SplatBits & BitMask) != 0) {
5846 return SDValue();
5847 }
5848 BitMask <<= 8;
5849 ImmMask <<= 1;
5850 }
5851
5852 if (DAG.getDataLayout().isBigEndian())
5853 // swap higher and lower 32 bit word
5854 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5855
5856 // Op=1, Cmode=1110.
5857 OpCmode = 0x1e;
5858 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5859 break;
5860 }
5861
5862 default:
5863 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5863)
;
5864 }
5865
5866 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5867 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5868}
5869
5870SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5871 const ARMSubtarget *ST) const {
5872 EVT VT = Op.getValueType();
5873 bool IsDouble = (VT == MVT::f64);
5874 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5875 const APFloat &FPVal = CFP->getValueAPF();
5876
5877 // Prevent floating-point constants from using literal loads
5878 // when execute-only is enabled.
5879 if (ST->genExecuteOnly()) {
5880 // If we can represent the constant as an immediate, don't lower it
5881 if (isFPImmLegal(FPVal, VT))
5882 return Op;
5883 // Otherwise, construct as integer, and move to float register
5884 APInt INTVal = FPVal.bitcastToAPInt();
5885 SDLoc DL(CFP);
5886 switch (VT.getSimpleVT().SimpleTy) {
5887 default:
5888 llvm_unreachable("Unknown floating point type!")::llvm::llvm_unreachable_internal("Unknown floating point type!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/ARM/ARMISelLowering.cpp"
, 5888)
;
5889 break;
5890 case MVT::f64: {
5891 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
5892 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
5893 if (!ST->isLittle())
5894 std::swap(Lo, Hi);
5895 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
5896 }
5897 case MVT::f32:
5898 return DAG.getNode(ARMISD::VMOVSR, DL, VT,
5899 DAG.getConstant(INTVal, DL, MVT::i32));
5900 }
5901 }
5902
5903 if (!ST->hasVFP3())
5904 return SDValue();
5905
5906 // Use the default (constant pool) lowering for double constants when we have
5907 // an SP-only FPU
5908 if (IsDouble && Subtarget->isFPOnlySP())
5909 return SDValue();
5910
5911 // Try splatting with a VMOV.f32...
5912 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
5913
5914 if (ImmVal != -1) {
5915 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
5916 // We have code in place to select a valid ConstantFP already, no need to
5917 // do any mangling.
5918 return Op;
5919 }
5920
5921 // It's a float and we are trying to use NEON operations where
5922 // possible. Lower it to a splat followed by an extract.
5923 SDLoc DL(Op);
5924 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
5925 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5926 NewVal);
5927 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
5928 DAG.getConstant(0, DL, MVT::i32));
5929 }
5930
5931 // The rest of our options are NEON only, make sure that's allowed before
5932 // proceeding..
5933 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
5934 return SDValue();
5935
5936 EVT VMovVT;
5937 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
5938
5939 // It wouldn't really be worth bothering for doubles except for one very
5940 // important value, which does happen to match: 0.0. So make sure we don't do
5941 // anything stupid.
5942 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
5943 return SDValue();
5944
5945 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
5946 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5947 VMovVT, false, VMOVModImm);
5948 if (NewVal != SDValue()) {
5949 SDLoc DL(Op);
5950 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5951 NewVal);
5952 if (IsDouble)
5953 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5954
5955 // It's a float: cast and extract a vector element.
5956 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5957 VecConstant);
5958 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5959 DAG.getConstant(0, DL, MVT::i32));
5960 }
5961
5962 // Finally, try a VMVN.i32
5963 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5964 false, VMVNModImm);
5965 if (NewVal != SDValue()) {
5966 SDLoc DL(Op);
5967 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5968
5969 if (IsDouble)
5970 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5971
5972 // It's a float: cast and extract a vector element.
5973 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5974 VecConstant);
5975 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5976 DAG.getConstant(0, DL, MVT::i32));
5977 }
5978
5979 return SDValue();