File: | lib/Target/ARM/ARMISelLowering.cpp |
Warning: | line 7021, column 14 1st function call argument is an uninitialized value |
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1 | //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | // | |||
9 | // This file defines the interfaces that ARM uses to lower LLVM code into a | |||
10 | // selection DAG. | |||
11 | // | |||
12 | //===----------------------------------------------------------------------===// | |||
13 | ||||
14 | #include "ARMISelLowering.h" | |||
15 | #include "ARMBaseInstrInfo.h" | |||
16 | #include "ARMBaseRegisterInfo.h" | |||
17 | #include "ARMCallingConv.h" | |||
18 | #include "ARMConstantPoolValue.h" | |||
19 | #include "ARMMachineFunctionInfo.h" | |||
20 | #include "ARMPerfectShuffle.h" | |||
21 | #include "ARMRegisterInfo.h" | |||
22 | #include "ARMSelectionDAGInfo.h" | |||
23 | #include "ARMSubtarget.h" | |||
24 | #include "MCTargetDesc/ARMAddressingModes.h" | |||
25 | #include "MCTargetDesc/ARMBaseInfo.h" | |||
26 | #include "Utils/ARMBaseInfo.h" | |||
27 | #include "llvm/ADT/APFloat.h" | |||
28 | #include "llvm/ADT/APInt.h" | |||
29 | #include "llvm/ADT/ArrayRef.h" | |||
30 | #include "llvm/ADT/BitVector.h" | |||
31 | #include "llvm/ADT/DenseMap.h" | |||
32 | #include "llvm/ADT/STLExtras.h" | |||
33 | #include "llvm/ADT/SmallPtrSet.h" | |||
34 | #include "llvm/ADT/SmallVector.h" | |||
35 | #include "llvm/ADT/Statistic.h" | |||
36 | #include "llvm/ADT/StringExtras.h" | |||
37 | #include "llvm/ADT/StringRef.h" | |||
38 | #include "llvm/ADT/StringSwitch.h" | |||
39 | #include "llvm/ADT/Triple.h" | |||
40 | #include "llvm/ADT/Twine.h" | |||
41 | #include "llvm/Analysis/VectorUtils.h" | |||
42 | #include "llvm/CodeGen/CallingConvLower.h" | |||
43 | #include "llvm/CodeGen/ISDOpcodes.h" | |||
44 | #include "llvm/CodeGen/IntrinsicLowering.h" | |||
45 | #include "llvm/CodeGen/MachineBasicBlock.h" | |||
46 | #include "llvm/CodeGen/MachineConstantPool.h" | |||
47 | #include "llvm/CodeGen/MachineFrameInfo.h" | |||
48 | #include "llvm/CodeGen/MachineFunction.h" | |||
49 | #include "llvm/CodeGen/MachineInstr.h" | |||
50 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |||
51 | #include "llvm/CodeGen/MachineJumpTableInfo.h" | |||
52 | #include "llvm/CodeGen/MachineMemOperand.h" | |||
53 | #include "llvm/CodeGen/MachineOperand.h" | |||
54 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |||
55 | #include "llvm/CodeGen/RuntimeLibcalls.h" | |||
56 | #include "llvm/CodeGen/SelectionDAG.h" | |||
57 | #include "llvm/CodeGen/SelectionDAGNodes.h" | |||
58 | #include "llvm/CodeGen/TargetInstrInfo.h" | |||
59 | #include "llvm/CodeGen/TargetLowering.h" | |||
60 | #include "llvm/CodeGen/TargetOpcodes.h" | |||
61 | #include "llvm/CodeGen/TargetRegisterInfo.h" | |||
62 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | |||
63 | #include "llvm/CodeGen/ValueTypes.h" | |||
64 | #include "llvm/IR/Attributes.h" | |||
65 | #include "llvm/IR/CallingConv.h" | |||
66 | #include "llvm/IR/Constant.h" | |||
67 | #include "llvm/IR/Constants.h" | |||
68 | #include "llvm/IR/DataLayout.h" | |||
69 | #include "llvm/IR/DebugLoc.h" | |||
70 | #include "llvm/IR/DerivedTypes.h" | |||
71 | #include "llvm/IR/Function.h" | |||
72 | #include "llvm/IR/GlobalAlias.h" | |||
73 | #include "llvm/IR/GlobalValue.h" | |||
74 | #include "llvm/IR/GlobalVariable.h" | |||
75 | #include "llvm/IR/IRBuilder.h" | |||
76 | #include "llvm/IR/InlineAsm.h" | |||
77 | #include "llvm/IR/Instruction.h" | |||
78 | #include "llvm/IR/Instructions.h" | |||
79 | #include "llvm/IR/IntrinsicInst.h" | |||
80 | #include "llvm/IR/Intrinsics.h" | |||
81 | #include "llvm/IR/Module.h" | |||
82 | #include "llvm/IR/PatternMatch.h" | |||
83 | #include "llvm/IR/Type.h" | |||
84 | #include "llvm/IR/User.h" | |||
85 | #include "llvm/IR/Value.h" | |||
86 | #include "llvm/MC/MCInstrDesc.h" | |||
87 | #include "llvm/MC/MCInstrItineraries.h" | |||
88 | #include "llvm/MC/MCRegisterInfo.h" | |||
89 | #include "llvm/MC/MCSchedule.h" | |||
90 | #include "llvm/Support/AtomicOrdering.h" | |||
91 | #include "llvm/Support/BranchProbability.h" | |||
92 | #include "llvm/Support/Casting.h" | |||
93 | #include "llvm/Support/CodeGen.h" | |||
94 | #include "llvm/Support/CommandLine.h" | |||
95 | #include "llvm/Support/Compiler.h" | |||
96 | #include "llvm/Support/Debug.h" | |||
97 | #include "llvm/Support/ErrorHandling.h" | |||
98 | #include "llvm/Support/KnownBits.h" | |||
99 | #include "llvm/Support/MachineValueType.h" | |||
100 | #include "llvm/Support/MathExtras.h" | |||
101 | #include "llvm/Support/raw_ostream.h" | |||
102 | #include "llvm/Target/TargetMachine.h" | |||
103 | #include "llvm/Target/TargetOptions.h" | |||
104 | #include <algorithm> | |||
105 | #include <cassert> | |||
106 | #include <cstdint> | |||
107 | #include <cstdlib> | |||
108 | #include <iterator> | |||
109 | #include <limits> | |||
110 | #include <string> | |||
111 | #include <tuple> | |||
112 | #include <utility> | |||
113 | #include <vector> | |||
114 | ||||
115 | using namespace llvm; | |||
116 | using namespace llvm::PatternMatch; | |||
117 | ||||
118 | #define DEBUG_TYPE"arm-isel" "arm-isel" | |||
119 | ||||
120 | STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls" , "Number of tail calls", {0}, {false}}; | |||
121 | STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt" , "Number of GAs materialized with movw + movt", {0}, {false} }; | |||
122 | STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals" , "Number of loops generated for byval arguments", {0}, {false }}; | |||
123 | STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted" , "Number of constants with their storage promoted into constant pools" , {0}, {false}} | |||
124 | "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted" , "Number of constants with their storage promoted into constant pools" , {0}, {false}}; | |||
125 | ||||
126 | static cl::opt<bool> | |||
127 | ARMInterworking("arm-interworking", cl::Hidden, | |||
128 | cl::desc("Enable / disable ARM interworking (for debugging only)"), | |||
129 | cl::init(true)); | |||
130 | ||||
131 | static cl::opt<bool> EnableConstpoolPromotion( | |||
132 | "arm-promote-constant", cl::Hidden, | |||
133 | cl::desc("Enable / disable promotion of unnamed_addr constants into " | |||
134 | "constant pools"), | |||
135 | cl::init(false)); // FIXME: set to true by default once PR32780 is fixed | |||
136 | static cl::opt<unsigned> ConstpoolPromotionMaxSize( | |||
137 | "arm-promote-constant-max-size", cl::Hidden, | |||
138 | cl::desc("Maximum size of constant to promote into a constant pool"), | |||
139 | cl::init(64)); | |||
140 | static cl::opt<unsigned> ConstpoolPromotionMaxTotal( | |||
141 | "arm-promote-constant-max-total", cl::Hidden, | |||
142 | cl::desc("Maximum size of ALL constants to promote into a constant pool"), | |||
143 | cl::init(128)); | |||
144 | ||||
145 | // The APCS parameter registers. | |||
146 | static const MCPhysReg GPRArgRegs[] = { | |||
147 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 | |||
148 | }; | |||
149 | ||||
150 | void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, | |||
151 | MVT PromotedBitwiseVT) { | |||
152 | if (VT != PromotedLdStVT) { | |||
153 | setOperationAction(ISD::LOAD, VT, Promote); | |||
154 | AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); | |||
155 | ||||
156 | setOperationAction(ISD::STORE, VT, Promote); | |||
157 | AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); | |||
158 | } | |||
159 | ||||
160 | MVT ElemTy = VT.getVectorElementType(); | |||
161 | if (ElemTy != MVT::f64) | |||
162 | setOperationAction(ISD::SETCC, VT, Custom); | |||
163 | setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); | |||
164 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); | |||
165 | if (ElemTy == MVT::i32) { | |||
166 | setOperationAction(ISD::SINT_TO_FP, VT, Custom); | |||
167 | setOperationAction(ISD::UINT_TO_FP, VT, Custom); | |||
168 | setOperationAction(ISD::FP_TO_SINT, VT, Custom); | |||
169 | setOperationAction(ISD::FP_TO_UINT, VT, Custom); | |||
170 | } else { | |||
171 | setOperationAction(ISD::SINT_TO_FP, VT, Expand); | |||
172 | setOperationAction(ISD::UINT_TO_FP, VT, Expand); | |||
173 | setOperationAction(ISD::FP_TO_SINT, VT, Expand); | |||
174 | setOperationAction(ISD::FP_TO_UINT, VT, Expand); | |||
175 | } | |||
176 | setOperationAction(ISD::BUILD_VECTOR, VT, Custom); | |||
177 | setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); | |||
178 | setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); | |||
179 | setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); | |||
180 | setOperationAction(ISD::SELECT, VT, Expand); | |||
181 | setOperationAction(ISD::SELECT_CC, VT, Expand); | |||
182 | setOperationAction(ISD::VSELECT, VT, Expand); | |||
183 | setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | |||
184 | if (VT.isInteger()) { | |||
185 | setOperationAction(ISD::SHL, VT, Custom); | |||
186 | setOperationAction(ISD::SRA, VT, Custom); | |||
187 | setOperationAction(ISD::SRL, VT, Custom); | |||
188 | } | |||
189 | ||||
190 | // Promote all bit-wise operations. | |||
191 | if (VT.isInteger() && VT != PromotedBitwiseVT) { | |||
192 | setOperationAction(ISD::AND, VT, Promote); | |||
193 | AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT); | |||
194 | setOperationAction(ISD::OR, VT, Promote); | |||
195 | AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT); | |||
196 | setOperationAction(ISD::XOR, VT, Promote); | |||
197 | AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT); | |||
198 | } | |||
199 | ||||
200 | // Neon does not support vector divide/remainder operations. | |||
201 | setOperationAction(ISD::SDIV, VT, Expand); | |||
202 | setOperationAction(ISD::UDIV, VT, Expand); | |||
203 | setOperationAction(ISD::FDIV, VT, Expand); | |||
204 | setOperationAction(ISD::SREM, VT, Expand); | |||
205 | setOperationAction(ISD::UREM, VT, Expand); | |||
206 | setOperationAction(ISD::FREM, VT, Expand); | |||
207 | ||||
208 | if (!VT.isFloatingPoint() && | |||
209 | VT != MVT::v2i64 && VT != MVT::v1i64) | |||
210 | for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) | |||
211 | setOperationAction(Opcode, VT, Legal); | |||
212 | } | |||
213 | ||||
214 | void ARMTargetLowering::addDRTypeForNEON(MVT VT) { | |||
215 | addRegisterClass(VT, &ARM::DPRRegClass); | |||
216 | addTypeForNEON(VT, MVT::f64, MVT::v2i32); | |||
217 | } | |||
218 | ||||
219 | void ARMTargetLowering::addQRTypeForNEON(MVT VT) { | |||
220 | addRegisterClass(VT, &ARM::DPairRegClass); | |||
221 | addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); | |||
222 | } | |||
223 | ||||
224 | ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, | |||
225 | const ARMSubtarget &STI) | |||
226 | : TargetLowering(TM), Subtarget(&STI) { | |||
227 | RegInfo = Subtarget->getRegisterInfo(); | |||
228 | Itins = Subtarget->getInstrItineraryData(); | |||
229 | ||||
230 | setBooleanContents(ZeroOrOneBooleanContent); | |||
231 | setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); | |||
232 | ||||
233 | if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() && | |||
234 | !Subtarget->isTargetWatchOS()) { | |||
235 | bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard; | |||
236 | for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID) | |||
237 | setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID), | |||
238 | IsHFTarget ? CallingConv::ARM_AAPCS_VFP | |||
239 | : CallingConv::ARM_AAPCS); | |||
240 | } | |||
241 | ||||
242 | if (Subtarget->isTargetMachO()) { | |||
243 | // Uses VFP for Thumb libfuncs if available. | |||
244 | if (Subtarget->isThumb() && Subtarget->hasVFP2() && | |||
245 | Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { | |||
246 | static const struct { | |||
247 | const RTLIB::Libcall Op; | |||
248 | const char * const Name; | |||
249 | const ISD::CondCode Cond; | |||
250 | } LibraryCalls[] = { | |||
251 | // Single-precision floating-point arithmetic. | |||
252 | { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID }, | |||
253 | { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID }, | |||
254 | { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID }, | |||
255 | { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID }, | |||
256 | ||||
257 | // Double-precision floating-point arithmetic. | |||
258 | { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID }, | |||
259 | { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID }, | |||
260 | { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID }, | |||
261 | { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID }, | |||
262 | ||||
263 | // Single-precision comparisons. | |||
264 | { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE }, | |||
265 | { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE }, | |||
266 | { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE }, | |||
267 | { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE }, | |||
268 | { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE }, | |||
269 | { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE }, | |||
270 | { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE }, | |||
271 | { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ }, | |||
272 | ||||
273 | // Double-precision comparisons. | |||
274 | { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE }, | |||
275 | { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE }, | |||
276 | { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE }, | |||
277 | { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE }, | |||
278 | { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE }, | |||
279 | { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE }, | |||
280 | { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE }, | |||
281 | { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ }, | |||
282 | ||||
283 | // Floating-point to integer conversions. | |||
284 | // i64 conversions are done via library routines even when generating VFP | |||
285 | // instructions, so use the same ones. | |||
286 | { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID }, | |||
287 | { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID }, | |||
288 | { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID }, | |||
289 | { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID }, | |||
290 | ||||
291 | // Conversions between floating types. | |||
292 | { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID }, | |||
293 | { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID }, | |||
294 | ||||
295 | // Integer to floating-point conversions. | |||
296 | // i64 conversions are done via library routines even when generating VFP | |||
297 | // instructions, so use the same ones. | |||
298 | // FIXME: There appears to be some naming inconsistency in ARM libgcc: | |||
299 | // e.g., __floatunsidf vs. __floatunssidfvfp. | |||
300 | { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID }, | |||
301 | { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID }, | |||
302 | { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID }, | |||
303 | { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID }, | |||
304 | }; | |||
305 | ||||
306 | for (const auto &LC : LibraryCalls) { | |||
307 | setLibcallName(LC.Op, LC.Name); | |||
308 | if (LC.Cond != ISD::SETCC_INVALID) | |||
309 | setCmpLibcallCC(LC.Op, LC.Cond); | |||
310 | } | |||
311 | } | |||
312 | } | |||
313 | ||||
314 | // These libcalls are not available in 32-bit. | |||
315 | setLibcallName(RTLIB::SHL_I128, nullptr); | |||
316 | setLibcallName(RTLIB::SRL_I128, nullptr); | |||
317 | setLibcallName(RTLIB::SRA_I128, nullptr); | |||
318 | ||||
319 | // RTLIB | |||
320 | if (Subtarget->isAAPCS_ABI() && | |||
321 | (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || | |||
322 | Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) { | |||
323 | static const struct { | |||
324 | const RTLIB::Libcall Op; | |||
325 | const char * const Name; | |||
326 | const CallingConv::ID CC; | |||
327 | const ISD::CondCode Cond; | |||
328 | } LibraryCalls[] = { | |||
329 | // Double-precision floating-point arithmetic helper functions | |||
330 | // RTABI chapter 4.1.2, Table 2 | |||
331 | { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
332 | { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
333 | { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
334 | { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
335 | ||||
336 | // Double-precision floating-point comparison helper functions | |||
337 | // RTABI chapter 4.1.2, Table 3 | |||
338 | { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
339 | { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, | |||
340 | { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
341 | { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
342 | { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
343 | { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
344 | { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
345 | { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, | |||
346 | ||||
347 | // Single-precision floating-point arithmetic helper functions | |||
348 | // RTABI chapter 4.1.2, Table 4 | |||
349 | { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
350 | { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
351 | { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
352 | { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
353 | ||||
354 | // Single-precision floating-point comparison helper functions | |||
355 | // RTABI chapter 4.1.2, Table 5 | |||
356 | { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
357 | { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, | |||
358 | { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
359 | { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
360 | { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
361 | { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
362 | { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE }, | |||
363 | { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, | |||
364 | ||||
365 | // Floating-point to integer conversions. | |||
366 | // RTABI chapter 4.1.2, Table 6 | |||
367 | { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
368 | { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
369 | { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
370 | { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
371 | { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
372 | { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
373 | { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
374 | { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
375 | ||||
376 | // Conversions between floating types. | |||
377 | // RTABI chapter 4.1.2, Table 7 | |||
378 | { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
379 | { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
380 | { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
381 | ||||
382 | // Integer to floating-point conversions. | |||
383 | // RTABI chapter 4.1.2, Table 8 | |||
384 | { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
385 | { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
386 | { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
387 | { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
388 | { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
389 | { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
390 | { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
391 | { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
392 | ||||
393 | // Long long helper functions | |||
394 | // RTABI chapter 4.2, Table 9 | |||
395 | { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
396 | { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
397 | { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
398 | { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
399 | ||||
400 | // Integer division functions | |||
401 | // RTABI chapter 4.3.1 | |||
402 | { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
403 | { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
404 | { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
405 | { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
406 | { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
407 | { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
408 | { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
409 | { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
410 | }; | |||
411 | ||||
412 | for (const auto &LC : LibraryCalls) { | |||
413 | setLibcallName(LC.Op, LC.Name); | |||
414 | setLibcallCallingConv(LC.Op, LC.CC); | |||
415 | if (LC.Cond != ISD::SETCC_INVALID) | |||
416 | setCmpLibcallCC(LC.Op, LC.Cond); | |||
417 | } | |||
418 | ||||
419 | // EABI dependent RTLIB | |||
420 | if (TM.Options.EABIVersion == EABI::EABI4 || | |||
421 | TM.Options.EABIVersion == EABI::EABI5) { | |||
422 | static const struct { | |||
423 | const RTLIB::Libcall Op; | |||
424 | const char *const Name; | |||
425 | const CallingConv::ID CC; | |||
426 | const ISD::CondCode Cond; | |||
427 | } MemOpsLibraryCalls[] = { | |||
428 | // Memory operations | |||
429 | // RTABI chapter 4.3.4 | |||
430 | { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
431 | { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
432 | { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID }, | |||
433 | }; | |||
434 | ||||
435 | for (const auto &LC : MemOpsLibraryCalls) { | |||
436 | setLibcallName(LC.Op, LC.Name); | |||
437 | setLibcallCallingConv(LC.Op, LC.CC); | |||
438 | if (LC.Cond != ISD::SETCC_INVALID) | |||
439 | setCmpLibcallCC(LC.Op, LC.Cond); | |||
440 | } | |||
441 | } | |||
442 | } | |||
443 | ||||
444 | if (Subtarget->isTargetWindows()) { | |||
445 | static const struct { | |||
446 | const RTLIB::Libcall Op; | |||
447 | const char * const Name; | |||
448 | const CallingConv::ID CC; | |||
449 | } LibraryCalls[] = { | |||
450 | { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP }, | |||
451 | { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP }, | |||
452 | { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP }, | |||
453 | { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP }, | |||
454 | { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP }, | |||
455 | { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP }, | |||
456 | { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP }, | |||
457 | { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP }, | |||
458 | }; | |||
459 | ||||
460 | for (const auto &LC : LibraryCalls) { | |||
461 | setLibcallName(LC.Op, LC.Name); | |||
462 | setLibcallCallingConv(LC.Op, LC.CC); | |||
463 | } | |||
464 | } | |||
465 | ||||
466 | // Use divmod compiler-rt calls for iOS 5.0 and later. | |||
467 | if (Subtarget->isTargetMachO() && | |||
468 | !(Subtarget->isTargetIOS() && | |||
469 | Subtarget->getTargetTriple().isOSVersionLT(5, 0))) { | |||
470 | setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); | |||
471 | setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); | |||
472 | } | |||
473 | ||||
474 | // The half <-> float conversion functions are always soft-float on | |||
475 | // non-watchos platforms, but are needed for some targets which use a | |||
476 | // hard-float calling convention by default. | |||
477 | if (!Subtarget->isTargetWatchABI()) { | |||
478 | if (Subtarget->isAAPCS_ABI()) { | |||
479 | setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS); | |||
480 | setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS); | |||
481 | setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS); | |||
482 | } else { | |||
483 | setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS); | |||
484 | setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS); | |||
485 | setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS); | |||
486 | } | |||
487 | } | |||
488 | ||||
489 | // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have | |||
490 | // a __gnu_ prefix (which is the default). | |||
491 | if (Subtarget->isTargetAEABI()) { | |||
492 | static const struct { | |||
493 | const RTLIB::Libcall Op; | |||
494 | const char * const Name; | |||
495 | const CallingConv::ID CC; | |||
496 | } LibraryCalls[] = { | |||
497 | { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS }, | |||
498 | { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS }, | |||
499 | { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS }, | |||
500 | }; | |||
501 | ||||
502 | for (const auto &LC : LibraryCalls) { | |||
503 | setLibcallName(LC.Op, LC.Name); | |||
504 | setLibcallCallingConv(LC.Op, LC.CC); | |||
505 | } | |||
506 | } | |||
507 | ||||
508 | if (Subtarget->isThumb1Only()) | |||
509 | addRegisterClass(MVT::i32, &ARM::tGPRRegClass); | |||
510 | else | |||
511 | addRegisterClass(MVT::i32, &ARM::GPRRegClass); | |||
512 | ||||
513 | if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() && | |||
514 | !Subtarget->isThumb1Only()) { | |||
515 | addRegisterClass(MVT::f32, &ARM::SPRRegClass); | |||
516 | addRegisterClass(MVT::f64, &ARM::DPRRegClass); | |||
517 | } | |||
518 | ||||
519 | if (Subtarget->hasFullFP16()) { | |||
520 | addRegisterClass(MVT::f16, &ARM::HPRRegClass); | |||
521 | setOperationAction(ISD::BITCAST, MVT::i16, Custom); | |||
522 | setOperationAction(ISD::BITCAST, MVT::i32, Custom); | |||
523 | setOperationAction(ISD::BITCAST, MVT::f16, Custom); | |||
524 | ||||
525 | setOperationAction(ISD::FMINNUM, MVT::f16, Legal); | |||
526 | setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); | |||
527 | } | |||
528 | ||||
529 | for (MVT VT : MVT::vector_valuetypes()) { | |||
530 | for (MVT InnerVT : MVT::vector_valuetypes()) { | |||
531 | setTruncStoreAction(VT, InnerVT, Expand); | |||
532 | setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); | |||
533 | setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); | |||
534 | setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); | |||
535 | } | |||
536 | ||||
537 | setOperationAction(ISD::MULHS, VT, Expand); | |||
538 | setOperationAction(ISD::SMUL_LOHI, VT, Expand); | |||
539 | setOperationAction(ISD::MULHU, VT, Expand); | |||
540 | setOperationAction(ISD::UMUL_LOHI, VT, Expand); | |||
541 | ||||
542 | setOperationAction(ISD::BSWAP, VT, Expand); | |||
543 | } | |||
544 | ||||
545 | setOperationAction(ISD::ConstantFP, MVT::f32, Custom); | |||
546 | setOperationAction(ISD::ConstantFP, MVT::f64, Custom); | |||
547 | ||||
548 | setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); | |||
549 | setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); | |||
550 | ||||
551 | if (Subtarget->hasNEON()) { | |||
552 | addDRTypeForNEON(MVT::v2f32); | |||
553 | addDRTypeForNEON(MVT::v8i8); | |||
554 | addDRTypeForNEON(MVT::v4i16); | |||
555 | addDRTypeForNEON(MVT::v2i32); | |||
556 | addDRTypeForNEON(MVT::v1i64); | |||
557 | ||||
558 | addQRTypeForNEON(MVT::v4f32); | |||
559 | addQRTypeForNEON(MVT::v2f64); | |||
560 | addQRTypeForNEON(MVT::v16i8); | |||
561 | addQRTypeForNEON(MVT::v8i16); | |||
562 | addQRTypeForNEON(MVT::v4i32); | |||
563 | addQRTypeForNEON(MVT::v2i64); | |||
564 | ||||
565 | if (Subtarget->hasFullFP16()) { | |||
566 | addQRTypeForNEON(MVT::v8f16); | |||
567 | addDRTypeForNEON(MVT::v4f16); | |||
568 | } | |||
569 | ||||
570 | // v2f64 is legal so that QR subregs can be extracted as f64 elements, but | |||
571 | // neither Neon nor VFP support any arithmetic operations on it. | |||
572 | // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively | |||
573 | // supported for v4f32. | |||
574 | setOperationAction(ISD::FADD, MVT::v2f64, Expand); | |||
575 | setOperationAction(ISD::FSUB, MVT::v2f64, Expand); | |||
576 | setOperationAction(ISD::FMUL, MVT::v2f64, Expand); | |||
577 | // FIXME: Code duplication: FDIV and FREM are expanded always, see | |||
578 | // ARMTargetLowering::addTypeForNEON method for details. | |||
579 | setOperationAction(ISD::FDIV, MVT::v2f64, Expand); | |||
580 | setOperationAction(ISD::FREM, MVT::v2f64, Expand); | |||
581 | // FIXME: Create unittest. | |||
582 | // In another words, find a way when "copysign" appears in DAG with vector | |||
583 | // operands. | |||
584 | setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); | |||
585 | // FIXME: Code duplication: SETCC has custom operation action, see | |||
586 | // ARMTargetLowering::addTypeForNEON method for details. | |||
587 | setOperationAction(ISD::SETCC, MVT::v2f64, Expand); | |||
588 | // FIXME: Create unittest for FNEG and for FABS. | |||
589 | setOperationAction(ISD::FNEG, MVT::v2f64, Expand); | |||
590 | setOperationAction(ISD::FABS, MVT::v2f64, Expand); | |||
591 | setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); | |||
592 | setOperationAction(ISD::FSIN, MVT::v2f64, Expand); | |||
593 | setOperationAction(ISD::FCOS, MVT::v2f64, Expand); | |||
594 | setOperationAction(ISD::FPOW, MVT::v2f64, Expand); | |||
595 | setOperationAction(ISD::FLOG, MVT::v2f64, Expand); | |||
596 | setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); | |||
597 | setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); | |||
598 | setOperationAction(ISD::FEXP, MVT::v2f64, Expand); | |||
599 | setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); | |||
600 | // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR. | |||
601 | setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); | |||
602 | setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); | |||
603 | setOperationAction(ISD::FRINT, MVT::v2f64, Expand); | |||
604 | setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); | |||
605 | setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); | |||
606 | setOperationAction(ISD::FMA, MVT::v2f64, Expand); | |||
607 | ||||
608 | setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); | |||
609 | setOperationAction(ISD::FSIN, MVT::v4f32, Expand); | |||
610 | setOperationAction(ISD::FCOS, MVT::v4f32, Expand); | |||
611 | setOperationAction(ISD::FPOW, MVT::v4f32, Expand); | |||
612 | setOperationAction(ISD::FLOG, MVT::v4f32, Expand); | |||
613 | setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); | |||
614 | setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); | |||
615 | setOperationAction(ISD::FEXP, MVT::v4f32, Expand); | |||
616 | setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); | |||
617 | setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); | |||
618 | setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand); | |||
619 | setOperationAction(ISD::FRINT, MVT::v4f32, Expand); | |||
620 | setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); | |||
621 | setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand); | |||
622 | ||||
623 | // Mark v2f32 intrinsics. | |||
624 | setOperationAction(ISD::FSQRT, MVT::v2f32, Expand); | |||
625 | setOperationAction(ISD::FSIN, MVT::v2f32, Expand); | |||
626 | setOperationAction(ISD::FCOS, MVT::v2f32, Expand); | |||
627 | setOperationAction(ISD::FPOW, MVT::v2f32, Expand); | |||
628 | setOperationAction(ISD::FLOG, MVT::v2f32, Expand); | |||
629 | setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); | |||
630 | setOperationAction(ISD::FLOG10, MVT::v2f32, Expand); | |||
631 | setOperationAction(ISD::FEXP, MVT::v2f32, Expand); | |||
632 | setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); | |||
633 | setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); | |||
634 | setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand); | |||
635 | setOperationAction(ISD::FRINT, MVT::v2f32, Expand); | |||
636 | setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); | |||
637 | setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand); | |||
638 | ||||
639 | // Neon does not support some operations on v1i64 and v2i64 types. | |||
640 | setOperationAction(ISD::MUL, MVT::v1i64, Expand); | |||
641 | // Custom handling for some quad-vector types to detect VMULL. | |||
642 | setOperationAction(ISD::MUL, MVT::v8i16, Custom); | |||
643 | setOperationAction(ISD::MUL, MVT::v4i32, Custom); | |||
644 | setOperationAction(ISD::MUL, MVT::v2i64, Custom); | |||
645 | // Custom handling for some vector types to avoid expensive expansions | |||
646 | setOperationAction(ISD::SDIV, MVT::v4i16, Custom); | |||
647 | setOperationAction(ISD::SDIV, MVT::v8i8, Custom); | |||
648 | setOperationAction(ISD::UDIV, MVT::v4i16, Custom); | |||
649 | setOperationAction(ISD::UDIV, MVT::v8i8, Custom); | |||
650 | // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with | |||
651 | // a destination type that is wider than the source, and nor does | |||
652 | // it have a FP_TO_[SU]INT instruction with a narrower destination than | |||
653 | // source. | |||
654 | setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); | |||
655 | setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); | |||
656 | setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); | |||
657 | setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); | |||
658 | setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); | |||
659 | setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom); | |||
660 | setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); | |||
661 | setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); | |||
662 | ||||
663 | setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); | |||
664 | setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); | |||
665 | ||||
666 | // NEON does not have single instruction CTPOP for vectors with element | |||
667 | // types wider than 8-bits. However, custom lowering can leverage the | |||
668 | // v8i8/v16i8 vcnt instruction. | |||
669 | setOperationAction(ISD::CTPOP, MVT::v2i32, Custom); | |||
670 | setOperationAction(ISD::CTPOP, MVT::v4i32, Custom); | |||
671 | setOperationAction(ISD::CTPOP, MVT::v4i16, Custom); | |||
672 | setOperationAction(ISD::CTPOP, MVT::v8i16, Custom); | |||
673 | setOperationAction(ISD::CTPOP, MVT::v1i64, Custom); | |||
674 | setOperationAction(ISD::CTPOP, MVT::v2i64, Custom); | |||
675 | ||||
676 | setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); | |||
677 | setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); | |||
678 | ||||
679 | // NEON does not have single instruction CTTZ for vectors. | |||
680 | setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); | |||
681 | setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); | |||
682 | setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); | |||
683 | setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); | |||
684 | ||||
685 | setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); | |||
686 | setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); | |||
687 | setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); | |||
688 | setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); | |||
689 | ||||
690 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom); | |||
691 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom); | |||
692 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom); | |||
693 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); | |||
694 | ||||
695 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom); | |||
696 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom); | |||
697 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); | |||
698 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); | |||
699 | ||||
700 | // NEON only has FMA instructions as of VFP4. | |||
701 | if (!Subtarget->hasVFP4()) { | |||
702 | setOperationAction(ISD::FMA, MVT::v2f32, Expand); | |||
703 | setOperationAction(ISD::FMA, MVT::v4f32, Expand); | |||
704 | } | |||
705 | ||||
706 | setTargetDAGCombine(ISD::INTRINSIC_VOID); | |||
707 | setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); | |||
708 | setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); | |||
709 | setTargetDAGCombine(ISD::SHL); | |||
710 | setTargetDAGCombine(ISD::SRL); | |||
711 | setTargetDAGCombine(ISD::SRA); | |||
712 | setTargetDAGCombine(ISD::SIGN_EXTEND); | |||
713 | setTargetDAGCombine(ISD::ZERO_EXTEND); | |||
714 | setTargetDAGCombine(ISD::ANY_EXTEND); | |||
715 | setTargetDAGCombine(ISD::BUILD_VECTOR); | |||
716 | setTargetDAGCombine(ISD::VECTOR_SHUFFLE); | |||
717 | setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); | |||
718 | setTargetDAGCombine(ISD::STORE); | |||
719 | setTargetDAGCombine(ISD::FP_TO_SINT); | |||
720 | setTargetDAGCombine(ISD::FP_TO_UINT); | |||
721 | setTargetDAGCombine(ISD::FDIV); | |||
722 | setTargetDAGCombine(ISD::LOAD); | |||
723 | ||||
724 | // It is legal to extload from v4i8 to v4i16 or v4i32. | |||
725 | for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, | |||
726 | MVT::v2i32}) { | |||
727 | for (MVT VT : MVT::integer_vector_valuetypes()) { | |||
728 | setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal); | |||
729 | setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal); | |||
730 | setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal); | |||
731 | } | |||
732 | } | |||
733 | } | |||
734 | ||||
735 | if (Subtarget->isFPOnlySP()) { | |||
736 | // When targeting a floating-point unit with only single-precision | |||
737 | // operations, f64 is legal for the few double-precision instructions which | |||
738 | // are present However, no double-precision operations other than moves, | |||
739 | // loads and stores are provided by the hardware. | |||
740 | setOperationAction(ISD::FADD, MVT::f64, Expand); | |||
741 | setOperationAction(ISD::FSUB, MVT::f64, Expand); | |||
742 | setOperationAction(ISD::FMUL, MVT::f64, Expand); | |||
743 | setOperationAction(ISD::FMA, MVT::f64, Expand); | |||
744 | setOperationAction(ISD::FDIV, MVT::f64, Expand); | |||
745 | setOperationAction(ISD::FREM, MVT::f64, Expand); | |||
746 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); | |||
747 | setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); | |||
748 | setOperationAction(ISD::FNEG, MVT::f64, Expand); | |||
749 | setOperationAction(ISD::FABS, MVT::f64, Expand); | |||
750 | setOperationAction(ISD::FSQRT, MVT::f64, Expand); | |||
751 | setOperationAction(ISD::FSIN, MVT::f64, Expand); | |||
752 | setOperationAction(ISD::FCOS, MVT::f64, Expand); | |||
753 | setOperationAction(ISD::FPOW, MVT::f64, Expand); | |||
754 | setOperationAction(ISD::FLOG, MVT::f64, Expand); | |||
755 | setOperationAction(ISD::FLOG2, MVT::f64, Expand); | |||
756 | setOperationAction(ISD::FLOG10, MVT::f64, Expand); | |||
757 | setOperationAction(ISD::FEXP, MVT::f64, Expand); | |||
758 | setOperationAction(ISD::FEXP2, MVT::f64, Expand); | |||
759 | setOperationAction(ISD::FCEIL, MVT::f64, Expand); | |||
760 | setOperationAction(ISD::FTRUNC, MVT::f64, Expand); | |||
761 | setOperationAction(ISD::FRINT, MVT::f64, Expand); | |||
762 | setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); | |||
763 | setOperationAction(ISD::FFLOOR, MVT::f64, Expand); | |||
764 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); | |||
765 | setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); | |||
766 | setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); | |||
767 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); | |||
768 | setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); | |||
769 | setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom); | |||
770 | setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); | |||
771 | setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); | |||
772 | } | |||
773 | ||||
774 | computeRegisterProperties(Subtarget->getRegisterInfo()); | |||
775 | ||||
776 | // ARM does not have floating-point extending loads. | |||
777 | for (MVT VT : MVT::fp_valuetypes()) { | |||
778 | setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); | |||
779 | setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); | |||
780 | } | |||
781 | ||||
782 | // ... or truncating stores | |||
783 | setTruncStoreAction(MVT::f64, MVT::f32, Expand); | |||
784 | setTruncStoreAction(MVT::f32, MVT::f16, Expand); | |||
785 | setTruncStoreAction(MVT::f64, MVT::f16, Expand); | |||
786 | ||||
787 | // ARM does not have i1 sign extending load. | |||
788 | for (MVT VT : MVT::integer_valuetypes()) | |||
789 | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); | |||
790 | ||||
791 | // ARM supports all 4 flavors of integer indexed load / store. | |||
792 | if (!Subtarget->isThumb1Only()) { | |||
793 | for (unsigned im = (unsigned)ISD::PRE_INC; | |||
794 | im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { | |||
795 | setIndexedLoadAction(im, MVT::i1, Legal); | |||
796 | setIndexedLoadAction(im, MVT::i8, Legal); | |||
797 | setIndexedLoadAction(im, MVT::i16, Legal); | |||
798 | setIndexedLoadAction(im, MVT::i32, Legal); | |||
799 | setIndexedStoreAction(im, MVT::i1, Legal); | |||
800 | setIndexedStoreAction(im, MVT::i8, Legal); | |||
801 | setIndexedStoreAction(im, MVT::i16, Legal); | |||
802 | setIndexedStoreAction(im, MVT::i32, Legal); | |||
803 | } | |||
804 | } else { | |||
805 | // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}. | |||
806 | setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); | |||
807 | setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); | |||
808 | } | |||
809 | ||||
810 | setOperationAction(ISD::SADDO, MVT::i32, Custom); | |||
811 | setOperationAction(ISD::UADDO, MVT::i32, Custom); | |||
812 | setOperationAction(ISD::SSUBO, MVT::i32, Custom); | |||
813 | setOperationAction(ISD::USUBO, MVT::i32, Custom); | |||
814 | ||||
815 | setOperationAction(ISD::ADDCARRY, MVT::i32, Custom); | |||
816 | setOperationAction(ISD::SUBCARRY, MVT::i32, Custom); | |||
817 | ||||
818 | // i64 operation support. | |||
819 | setOperationAction(ISD::MUL, MVT::i64, Expand); | |||
820 | setOperationAction(ISD::MULHU, MVT::i32, Expand); | |||
821 | if (Subtarget->isThumb1Only()) { | |||
822 | setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); | |||
823 | setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); | |||
824 | } | |||
825 | if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() | |||
826 | || (Subtarget->isThumb2() && !Subtarget->hasDSP())) | |||
827 | setOperationAction(ISD::MULHS, MVT::i32, Expand); | |||
828 | ||||
829 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); | |||
830 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); | |||
831 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); | |||
832 | setOperationAction(ISD::SRL, MVT::i64, Custom); | |||
833 | setOperationAction(ISD::SRA, MVT::i64, Custom); | |||
834 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); | |||
835 | ||||
836 | // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1. | |||
837 | if (Subtarget->isThumb1Only()) { | |||
838 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); | |||
839 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); | |||
840 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); | |||
841 | } | |||
842 | ||||
843 | if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) | |||
844 | setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); | |||
845 | ||||
846 | // ARM does not have ROTL. | |||
847 | setOperationAction(ISD::ROTL, MVT::i32, Expand); | |||
848 | for (MVT VT : MVT::vector_valuetypes()) { | |||
849 | setOperationAction(ISD::ROTL, VT, Expand); | |||
850 | setOperationAction(ISD::ROTR, VT, Expand); | |||
851 | } | |||
852 | setOperationAction(ISD::CTTZ, MVT::i32, Custom); | |||
853 | setOperationAction(ISD::CTPOP, MVT::i32, Expand); | |||
854 | if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) { | |||
855 | setOperationAction(ISD::CTLZ, MVT::i32, Expand); | |||
856 | setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall); | |||
857 | } | |||
858 | ||||
859 | // @llvm.readcyclecounter requires the Performance Monitors extension. | |||
860 | // Default to the 0 expansion on unsupported platforms. | |||
861 | // FIXME: Technically there are older ARM CPUs that have | |||
862 | // implementation-specific ways of obtaining this information. | |||
863 | if (Subtarget->hasPerfMon()) | |||
864 | setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); | |||
865 | ||||
866 | // Only ARMv6 has BSWAP. | |||
867 | if (!Subtarget->hasV6Ops()) | |||
868 | setOperationAction(ISD::BSWAP, MVT::i32, Expand); | |||
869 | ||||
870 | bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode() | |||
871 | : Subtarget->hasDivideInARMMode(); | |||
872 | if (!hasDivide) { | |||
873 | // These are expanded into libcalls if the cpu doesn't have HW divider. | |||
874 | setOperationAction(ISD::SDIV, MVT::i32, LibCall); | |||
875 | setOperationAction(ISD::UDIV, MVT::i32, LibCall); | |||
876 | } | |||
877 | ||||
878 | if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) { | |||
879 | setOperationAction(ISD::SDIV, MVT::i32, Custom); | |||
880 | setOperationAction(ISD::UDIV, MVT::i32, Custom); | |||
881 | ||||
882 | setOperationAction(ISD::SDIV, MVT::i64, Custom); | |||
883 | setOperationAction(ISD::UDIV, MVT::i64, Custom); | |||
884 | } | |||
885 | ||||
886 | setOperationAction(ISD::SREM, MVT::i32, Expand); | |||
887 | setOperationAction(ISD::UREM, MVT::i32, Expand); | |||
888 | ||||
889 | // Register based DivRem for AEABI (RTABI 4.2) | |||
890 | if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || | |||
891 | Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || | |||
892 | Subtarget->isTargetWindows()) { | |||
893 | setOperationAction(ISD::SREM, MVT::i64, Custom); | |||
894 | setOperationAction(ISD::UREM, MVT::i64, Custom); | |||
895 | HasStandaloneRem = false; | |||
896 | ||||
897 | if (Subtarget->isTargetWindows()) { | |||
898 | const struct { | |||
899 | const RTLIB::Libcall Op; | |||
900 | const char * const Name; | |||
901 | const CallingConv::ID CC; | |||
902 | } LibraryCalls[] = { | |||
903 | { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS }, | |||
904 | { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS }, | |||
905 | { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS }, | |||
906 | { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS }, | |||
907 | ||||
908 | { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS }, | |||
909 | { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS }, | |||
910 | { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS }, | |||
911 | { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS }, | |||
912 | }; | |||
913 | ||||
914 | for (const auto &LC : LibraryCalls) { | |||
915 | setLibcallName(LC.Op, LC.Name); | |||
916 | setLibcallCallingConv(LC.Op, LC.CC); | |||
917 | } | |||
918 | } else { | |||
919 | const struct { | |||
920 | const RTLIB::Libcall Op; | |||
921 | const char * const Name; | |||
922 | const CallingConv::ID CC; | |||
923 | } LibraryCalls[] = { | |||
924 | { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS }, | |||
925 | { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS }, | |||
926 | { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS }, | |||
927 | { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS }, | |||
928 | ||||
929 | { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS }, | |||
930 | { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS }, | |||
931 | { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS }, | |||
932 | { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS }, | |||
933 | }; | |||
934 | ||||
935 | for (const auto &LC : LibraryCalls) { | |||
936 | setLibcallName(LC.Op, LC.Name); | |||
937 | setLibcallCallingConv(LC.Op, LC.CC); | |||
938 | } | |||
939 | } | |||
940 | ||||
941 | setOperationAction(ISD::SDIVREM, MVT::i32, Custom); | |||
942 | setOperationAction(ISD::UDIVREM, MVT::i32, Custom); | |||
943 | setOperationAction(ISD::SDIVREM, MVT::i64, Custom); | |||
944 | setOperationAction(ISD::UDIVREM, MVT::i64, Custom); | |||
945 | } else { | |||
946 | setOperationAction(ISD::SDIVREM, MVT::i32, Expand); | |||
947 | setOperationAction(ISD::UDIVREM, MVT::i32, Expand); | |||
948 | } | |||
949 | ||||
950 | if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT()) | |||
951 | for (auto &VT : {MVT::f32, MVT::f64}) | |||
952 | setOperationAction(ISD::FPOWI, VT, Custom); | |||
953 | ||||
954 | setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); | |||
955 | setOperationAction(ISD::ConstantPool, MVT::i32, Custom); | |||
956 | setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); | |||
957 | setOperationAction(ISD::BlockAddress, MVT::i32, Custom); | |||
958 | ||||
959 | setOperationAction(ISD::TRAP, MVT::Other, Legal); | |||
960 | setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); | |||
961 | ||||
962 | // Use the default implementation. | |||
963 | setOperationAction(ISD::VASTART, MVT::Other, Custom); | |||
964 | setOperationAction(ISD::VAARG, MVT::Other, Expand); | |||
965 | setOperationAction(ISD::VACOPY, MVT::Other, Expand); | |||
966 | setOperationAction(ISD::VAEND, MVT::Other, Expand); | |||
967 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); | |||
968 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); | |||
969 | ||||
970 | if (Subtarget->isTargetWindows()) | |||
971 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); | |||
972 | else | |||
973 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); | |||
974 | ||||
975 | // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use | |||
976 | // the default expansion. | |||
977 | InsertFencesForAtomic = false; | |||
978 | if (Subtarget->hasAnyDataBarrier() && | |||
979 | (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) { | |||
980 | // ATOMIC_FENCE needs custom lowering; the others should have been expanded | |||
981 | // to ldrex/strex loops already. | |||
982 | setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); | |||
983 | if (!Subtarget->isThumb() || !Subtarget->isMClass()) | |||
984 | setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); | |||
985 | ||||
986 | // On v8, we have particularly efficient implementations of atomic fences | |||
987 | // if they can be combined with nearby atomic loads and stores. | |||
988 | if (!Subtarget->hasAcquireRelease() || | |||
989 | getTargetMachine().getOptLevel() == 0) { | |||
990 | // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc. | |||
991 | InsertFencesForAtomic = true; | |||
992 | } | |||
993 | } else { | |||
994 | // If there's anything we can use as a barrier, go through custom lowering | |||
995 | // for ATOMIC_FENCE. | |||
996 | // If target has DMB in thumb, Fences can be inserted. | |||
997 | if (Subtarget->hasDataBarrier()) | |||
998 | InsertFencesForAtomic = true; | |||
999 | ||||
1000 | setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, | |||
1001 | Subtarget->hasAnyDataBarrier() ? Custom : Expand); | |||
1002 | ||||
1003 | // Set them all for expansion, which will force libcalls. | |||
1004 | setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); | |||
1005 | setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); | |||
1006 | setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); | |||
1007 | setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); | |||
1008 | setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); | |||
1009 | setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); | |||
1010 | setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); | |||
1011 | setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); | |||
1012 | setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); | |||
1013 | setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); | |||
1014 | setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); | |||
1015 | setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); | |||
1016 | // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the | |||
1017 | // Unordered/Monotonic case. | |||
1018 | if (!InsertFencesForAtomic) { | |||
1019 | setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); | |||
1020 | setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); | |||
1021 | } | |||
1022 | } | |||
1023 | ||||
1024 | setOperationAction(ISD::PREFETCH, MVT::Other, Custom); | |||
1025 | ||||
1026 | // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. | |||
1027 | if (!Subtarget->hasV6Ops()) { | |||
1028 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); | |||
1029 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); | |||
1030 | } | |||
1031 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); | |||
1032 | ||||
1033 | if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() && | |||
1034 | !Subtarget->isThumb1Only()) { | |||
1035 | // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR | |||
1036 | // iff target supports vfp2. | |||
1037 | setOperationAction(ISD::BITCAST, MVT::i64, Custom); | |||
1038 | setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); | |||
1039 | } | |||
1040 | ||||
1041 | // We want to custom lower some of our intrinsics. | |||
1042 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); | |||
1043 | setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); | |||
1044 | setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); | |||
1045 | setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom); | |||
1046 | if (Subtarget->useSjLjEH()) | |||
1047 | setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); | |||
1048 | ||||
1049 | setOperationAction(ISD::SETCC, MVT::i32, Expand); | |||
1050 | setOperationAction(ISD::SETCC, MVT::f32, Expand); | |||
1051 | setOperationAction(ISD::SETCC, MVT::f64, Expand); | |||
1052 | setOperationAction(ISD::SELECT, MVT::i32, Custom); | |||
1053 | setOperationAction(ISD::SELECT, MVT::f32, Custom); | |||
1054 | setOperationAction(ISD::SELECT, MVT::f64, Custom); | |||
1055 | setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); | |||
1056 | setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); | |||
1057 | setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); | |||
1058 | if (Subtarget->hasFullFP16()) { | |||
1059 | setOperationAction(ISD::SETCC, MVT::f16, Expand); | |||
1060 | setOperationAction(ISD::SELECT, MVT::f16, Custom); | |||
1061 | setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); | |||
1062 | } | |||
1063 | ||||
1064 | setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom); | |||
1065 | ||||
1066 | setOperationAction(ISD::BRCOND, MVT::Other, Custom); | |||
1067 | setOperationAction(ISD::BR_CC, MVT::i32, Custom); | |||
1068 | if (Subtarget->hasFullFP16()) | |||
1069 | setOperationAction(ISD::BR_CC, MVT::f16, Custom); | |||
1070 | setOperationAction(ISD::BR_CC, MVT::f32, Custom); | |||
1071 | setOperationAction(ISD::BR_CC, MVT::f64, Custom); | |||
1072 | setOperationAction(ISD::BR_JT, MVT::Other, Custom); | |||
1073 | ||||
1074 | // We don't support sin/cos/fmod/copysign/pow | |||
1075 | setOperationAction(ISD::FSIN, MVT::f64, Expand); | |||
1076 | setOperationAction(ISD::FSIN, MVT::f32, Expand); | |||
1077 | setOperationAction(ISD::FCOS, MVT::f32, Expand); | |||
1078 | setOperationAction(ISD::FCOS, MVT::f64, Expand); | |||
1079 | setOperationAction(ISD::FSINCOS, MVT::f64, Expand); | |||
1080 | setOperationAction(ISD::FSINCOS, MVT::f32, Expand); | |||
1081 | setOperationAction(ISD::FREM, MVT::f64, Expand); | |||
1082 | setOperationAction(ISD::FREM, MVT::f32, Expand); | |||
1083 | if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() && | |||
1084 | !Subtarget->isThumb1Only()) { | |||
1085 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); | |||
1086 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); | |||
1087 | } | |||
1088 | setOperationAction(ISD::FPOW, MVT::f64, Expand); | |||
1089 | setOperationAction(ISD::FPOW, MVT::f32, Expand); | |||
1090 | ||||
1091 | if (!Subtarget->hasVFP4()) { | |||
1092 | setOperationAction(ISD::FMA, MVT::f64, Expand); | |||
1093 | setOperationAction(ISD::FMA, MVT::f32, Expand); | |||
1094 | } | |||
1095 | ||||
1096 | // Various VFP goodness | |||
1097 | if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) { | |||
1098 | // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded. | |||
1099 | if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) { | |||
1100 | setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); | |||
1101 | setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); | |||
1102 | } | |||
1103 | ||||
1104 | // fp16 is a special v7 extension that adds f16 <-> f32 conversions. | |||
1105 | if (!Subtarget->hasFP16()) { | |||
1106 | setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); | |||
1107 | setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); | |||
1108 | } | |||
1109 | } | |||
1110 | ||||
1111 | // Use __sincos_stret if available. | |||
1112 | if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr && | |||
1113 | getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) { | |||
1114 | setOperationAction(ISD::FSINCOS, MVT::f64, Custom); | |||
1115 | setOperationAction(ISD::FSINCOS, MVT::f32, Custom); | |||
1116 | } | |||
1117 | ||||
1118 | // FP-ARMv8 implements a lot of rounding-like FP operations. | |||
1119 | if (Subtarget->hasFPARMv8()) { | |||
1120 | setOperationAction(ISD::FFLOOR, MVT::f32, Legal); | |||
1121 | setOperationAction(ISD::FCEIL, MVT::f32, Legal); | |||
1122 | setOperationAction(ISD::FROUND, MVT::f32, Legal); | |||
1123 | setOperationAction(ISD::FTRUNC, MVT::f32, Legal); | |||
1124 | setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); | |||
1125 | setOperationAction(ISD::FRINT, MVT::f32, Legal); | |||
1126 | setOperationAction(ISD::FMINNUM, MVT::f32, Legal); | |||
1127 | setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); | |||
1128 | setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); | |||
1129 | setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); | |||
1130 | setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); | |||
1131 | setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); | |||
1132 | ||||
1133 | if (!Subtarget->isFPOnlySP()) { | |||
1134 | setOperationAction(ISD::FFLOOR, MVT::f64, Legal); | |||
1135 | setOperationAction(ISD::FCEIL, MVT::f64, Legal); | |||
1136 | setOperationAction(ISD::FROUND, MVT::f64, Legal); | |||
1137 | setOperationAction(ISD::FTRUNC, MVT::f64, Legal); | |||
1138 | setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); | |||
1139 | setOperationAction(ISD::FRINT, MVT::f64, Legal); | |||
1140 | setOperationAction(ISD::FMINNUM, MVT::f64, Legal); | |||
1141 | setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); | |||
1142 | } | |||
1143 | } | |||
1144 | ||||
1145 | if (Subtarget->hasNEON()) { | |||
1146 | // vmin and vmax aren't available in a scalar form, so we use | |||
1147 | // a NEON instruction with an undef lane instead. | |||
1148 | setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); | |||
1149 | setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); | |||
1150 | setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); | |||
1151 | setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); | |||
1152 | setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal); | |||
1153 | setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal); | |||
1154 | setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); | |||
1155 | setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal); | |||
1156 | ||||
1157 | if (Subtarget->hasFullFP16()) { | |||
1158 | setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); | |||
1159 | setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); | |||
1160 | setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); | |||
1161 | setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); | |||
1162 | ||||
1163 | setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal); | |||
1164 | setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal); | |||
1165 | setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); | |||
1166 | setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal); | |||
1167 | } | |||
1168 | } | |||
1169 | ||||
1170 | // We have target-specific dag combine patterns for the following nodes: | |||
1171 | // ARMISD::VMOVRRD - No need to call setTargetDAGCombine | |||
1172 | setTargetDAGCombine(ISD::ADD); | |||
1173 | setTargetDAGCombine(ISD::SUB); | |||
1174 | setTargetDAGCombine(ISD::MUL); | |||
1175 | setTargetDAGCombine(ISD::AND); | |||
1176 | setTargetDAGCombine(ISD::OR); | |||
1177 | setTargetDAGCombine(ISD::XOR); | |||
1178 | ||||
1179 | if (Subtarget->hasV6Ops()) | |||
1180 | setTargetDAGCombine(ISD::SRL); | |||
1181 | if (Subtarget->isThumb1Only()) | |||
1182 | setTargetDAGCombine(ISD::SHL); | |||
1183 | ||||
1184 | setStackPointerRegisterToSaveRestore(ARM::SP); | |||
1185 | ||||
1186 | if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() || | |||
1187 | !Subtarget->hasVFP2() || Subtarget->hasMinSize()) | |||
1188 | setSchedulingPreference(Sched::RegPressure); | |||
1189 | else | |||
1190 | setSchedulingPreference(Sched::Hybrid); | |||
1191 | ||||
1192 | //// temporary - rewrite interface to use type | |||
1193 | MaxStoresPerMemset = 8; | |||
1194 | MaxStoresPerMemsetOptSize = 4; | |||
1195 | MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores | |||
1196 | MaxStoresPerMemcpyOptSize = 2; | |||
1197 | MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores | |||
1198 | MaxStoresPerMemmoveOptSize = 2; | |||
1199 | ||||
1200 | // On ARM arguments smaller than 4 bytes are extended, so all arguments | |||
1201 | // are at least 4 bytes aligned. | |||
1202 | setMinStackArgumentAlignment(4); | |||
1203 | ||||
1204 | // Prefer likely predicted branches to selects on out-of-order cores. | |||
1205 | PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder(); | |||
1206 | ||||
1207 | setPrefLoopAlignment(Subtarget->getPrefLoopAlignment()); | |||
1208 | ||||
1209 | setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); | |||
1210 | ||||
1211 | if (Subtarget->isThumb() || Subtarget->isThumb2()) | |||
1212 | setTargetDAGCombine(ISD::ABS); | |||
1213 | } | |||
1214 | ||||
1215 | bool ARMTargetLowering::useSoftFloat() const { | |||
1216 | return Subtarget->useSoftFloat(); | |||
1217 | } | |||
1218 | ||||
1219 | // FIXME: It might make sense to define the representative register class as the | |||
1220 | // nearest super-register that has a non-null superset. For example, DPR_VFP2 is | |||
1221 | // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, | |||
1222 | // SPR's representative would be DPR_VFP2. This should work well if register | |||
1223 | // pressure tracking were modified such that a register use would increment the | |||
1224 | // pressure of the register class's representative and all of it's super | |||
1225 | // classes' representatives transitively. We have not implemented this because | |||
1226 | // of the difficulty prior to coalescing of modeling operand register classes | |||
1227 | // due to the common occurrence of cross class copies and subregister insertions | |||
1228 | // and extractions. | |||
1229 | std::pair<const TargetRegisterClass *, uint8_t> | |||
1230 | ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI, | |||
1231 | MVT VT) const { | |||
1232 | const TargetRegisterClass *RRC = nullptr; | |||
1233 | uint8_t Cost = 1; | |||
1234 | switch (VT.SimpleTy) { | |||
1235 | default: | |||
1236 | return TargetLowering::findRepresentativeClass(TRI, VT); | |||
1237 | // Use DPR as representative register class for all floating point | |||
1238 | // and vector types. Since there are 32 SPR registers and 32 DPR registers so | |||
1239 | // the cost is 1 for both f32 and f64. | |||
1240 | case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: | |||
1241 | case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: | |||
1242 | RRC = &ARM::DPRRegClass; | |||
1243 | // When NEON is used for SP, only half of the register file is available | |||
1244 | // because operations that define both SP and DP results will be constrained | |||
1245 | // to the VFP2 class (D0-D15). We currently model this constraint prior to | |||
1246 | // coalescing by double-counting the SP regs. See the FIXME above. | |||
1247 | if (Subtarget->useNEONForSinglePrecisionFP()) | |||
1248 | Cost = 2; | |||
1249 | break; | |||
1250 | case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: | |||
1251 | case MVT::v4f32: case MVT::v2f64: | |||
1252 | RRC = &ARM::DPRRegClass; | |||
1253 | Cost = 2; | |||
1254 | break; | |||
1255 | case MVT::v4i64: | |||
1256 | RRC = &ARM::DPRRegClass; | |||
1257 | Cost = 4; | |||
1258 | break; | |||
1259 | case MVT::v8i64: | |||
1260 | RRC = &ARM::DPRRegClass; | |||
1261 | Cost = 8; | |||
1262 | break; | |||
1263 | } | |||
1264 | return std::make_pair(RRC, Cost); | |||
1265 | } | |||
1266 | ||||
1267 | const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { | |||
1268 | switch ((ARMISD::NodeType)Opcode) { | |||
1269 | case ARMISD::FIRST_NUMBER: break; | |||
1270 | case ARMISD::Wrapper: return "ARMISD::Wrapper"; | |||
1271 | case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; | |||
1272 | case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; | |||
1273 | case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL"; | |||
1274 | case ARMISD::CALL: return "ARMISD::CALL"; | |||
1275 | case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; | |||
1276 | case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; | |||
1277 | case ARMISD::BRCOND: return "ARMISD::BRCOND"; | |||
1278 | case ARMISD::BR_JT: return "ARMISD::BR_JT"; | |||
1279 | case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; | |||
1280 | case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; | |||
1281 | case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG"; | |||
1282 | case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; | |||
1283 | case ARMISD::CMP: return "ARMISD::CMP"; | |||
1284 | case ARMISD::CMN: return "ARMISD::CMN"; | |||
1285 | case ARMISD::CMPZ: return "ARMISD::CMPZ"; | |||
1286 | case ARMISD::CMPFP: return "ARMISD::CMPFP"; | |||
1287 | case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; | |||
1288 | case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; | |||
1289 | case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; | |||
1290 | ||||
1291 | case ARMISD::CMOV: return "ARMISD::CMOV"; | |||
1292 | case ARMISD::SUBS: return "ARMISD::SUBS"; | |||
1293 | ||||
1294 | case ARMISD::SSAT: return "ARMISD::SSAT"; | |||
1295 | case ARMISD::USAT: return "ARMISD::USAT"; | |||
1296 | ||||
1297 | case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; | |||
1298 | case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; | |||
1299 | case ARMISD::RRX: return "ARMISD::RRX"; | |||
1300 | ||||
1301 | case ARMISD::ADDC: return "ARMISD::ADDC"; | |||
1302 | case ARMISD::ADDE: return "ARMISD::ADDE"; | |||
1303 | case ARMISD::SUBC: return "ARMISD::SUBC"; | |||
1304 | case ARMISD::SUBE: return "ARMISD::SUBE"; | |||
1305 | ||||
1306 | case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; | |||
1307 | case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; | |||
1308 | case ARMISD::VMOVhr: return "ARMISD::VMOVhr"; | |||
1309 | case ARMISD::VMOVrh: return "ARMISD::VMOVrh"; | |||
1310 | case ARMISD::VMOVSR: return "ARMISD::VMOVSR"; | |||
1311 | ||||
1312 | case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; | |||
1313 | case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP"; | |||
1314 | case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH"; | |||
1315 | ||||
1316 | case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; | |||
1317 | ||||
1318 | case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; | |||
1319 | ||||
1320 | case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; | |||
1321 | ||||
1322 | case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; | |||
1323 | ||||
1324 | case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; | |||
1325 | ||||
1326 | case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK"; | |||
1327 | case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK"; | |||
1328 | ||||
1329 | case ARMISD::VCEQ: return "ARMISD::VCEQ"; | |||
1330 | case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; | |||
1331 | case ARMISD::VCGE: return "ARMISD::VCGE"; | |||
1332 | case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; | |||
1333 | case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; | |||
1334 | case ARMISD::VCGEU: return "ARMISD::VCGEU"; | |||
1335 | case ARMISD::VCGT: return "ARMISD::VCGT"; | |||
1336 | case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; | |||
1337 | case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; | |||
1338 | case ARMISD::VCGTU: return "ARMISD::VCGTU"; | |||
1339 | case ARMISD::VTST: return "ARMISD::VTST"; | |||
1340 | ||||
1341 | case ARMISD::VSHL: return "ARMISD::VSHL"; | |||
1342 | case ARMISD::VSHRs: return "ARMISD::VSHRs"; | |||
1343 | case ARMISD::VSHRu: return "ARMISD::VSHRu"; | |||
1344 | case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; | |||
1345 | case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; | |||
1346 | case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; | |||
1347 | case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; | |||
1348 | case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; | |||
1349 | case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; | |||
1350 | case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; | |||
1351 | case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; | |||
1352 | case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; | |||
1353 | case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; | |||
1354 | case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; | |||
1355 | case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; | |||
1356 | case ARMISD::VSLI: return "ARMISD::VSLI"; | |||
1357 | case ARMISD::VSRI: return "ARMISD::VSRI"; | |||
1358 | case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; | |||
1359 | case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; | |||
1360 | case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; | |||
1361 | case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; | |||
1362 | case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM"; | |||
1363 | case ARMISD::VDUP: return "ARMISD::VDUP"; | |||
1364 | case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; | |||
1365 | case ARMISD::VEXT: return "ARMISD::VEXT"; | |||
1366 | case ARMISD::VREV64: return "ARMISD::VREV64"; | |||
1367 | case ARMISD::VREV32: return "ARMISD::VREV32"; | |||
1368 | case ARMISD::VREV16: return "ARMISD::VREV16"; | |||
1369 | case ARMISD::VZIP: return "ARMISD::VZIP"; | |||
1370 | case ARMISD::VUZP: return "ARMISD::VUZP"; | |||
1371 | case ARMISD::VTRN: return "ARMISD::VTRN"; | |||
1372 | case ARMISD::VTBL1: return "ARMISD::VTBL1"; | |||
1373 | case ARMISD::VTBL2: return "ARMISD::VTBL2"; | |||
1374 | case ARMISD::VMULLs: return "ARMISD::VMULLs"; | |||
1375 | case ARMISD::VMULLu: return "ARMISD::VMULLu"; | |||
1376 | case ARMISD::UMAAL: return "ARMISD::UMAAL"; | |||
1377 | case ARMISD::UMLAL: return "ARMISD::UMLAL"; | |||
1378 | case ARMISD::SMLAL: return "ARMISD::SMLAL"; | |||
1379 | case ARMISD::SMLALBB: return "ARMISD::SMLALBB"; | |||
1380 | case ARMISD::SMLALBT: return "ARMISD::SMLALBT"; | |||
1381 | case ARMISD::SMLALTB: return "ARMISD::SMLALTB"; | |||
1382 | case ARMISD::SMLALTT: return "ARMISD::SMLALTT"; | |||
1383 | case ARMISD::SMULWB: return "ARMISD::SMULWB"; | |||
1384 | case ARMISD::SMULWT: return "ARMISD::SMULWT"; | |||
1385 | case ARMISD::SMLALD: return "ARMISD::SMLALD"; | |||
1386 | case ARMISD::SMLALDX: return "ARMISD::SMLALDX"; | |||
1387 | case ARMISD::SMLSLD: return "ARMISD::SMLSLD"; | |||
1388 | case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX"; | |||
1389 | case ARMISD::SMMLAR: return "ARMISD::SMMLAR"; | |||
1390 | case ARMISD::SMMLSR: return "ARMISD::SMMLSR"; | |||
1391 | case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; | |||
1392 | case ARMISD::BFI: return "ARMISD::BFI"; | |||
1393 | case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; | |||
1394 | case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; | |||
1395 | case ARMISD::VBSL: return "ARMISD::VBSL"; | |||
1396 | case ARMISD::MEMCPY: return "ARMISD::MEMCPY"; | |||
1397 | case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP"; | |||
1398 | case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; | |||
1399 | case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; | |||
1400 | case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; | |||
1401 | case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; | |||
1402 | case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; | |||
1403 | case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; | |||
1404 | case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; | |||
1405 | case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; | |||
1406 | case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; | |||
1407 | case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; | |||
1408 | case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD"; | |||
1409 | case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; | |||
1410 | case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; | |||
1411 | case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; | |||
1412 | case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; | |||
1413 | case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; | |||
1414 | case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; | |||
1415 | case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; | |||
1416 | case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; | |||
1417 | case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; | |||
1418 | case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; | |||
1419 | } | |||
1420 | return nullptr; | |||
1421 | } | |||
1422 | ||||
1423 | EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, | |||
1424 | EVT VT) const { | |||
1425 | if (!VT.isVector()) | |||
1426 | return getPointerTy(DL); | |||
1427 | return VT.changeVectorElementTypeToInteger(); | |||
1428 | } | |||
1429 | ||||
1430 | /// getRegClassFor - Return the register class that should be used for the | |||
1431 | /// specified value type. | |||
1432 | const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const { | |||
1433 | // Map v4i64 to QQ registers but do not make the type legal. Similarly map | |||
1434 | // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to | |||
1435 | // load / store 4 to 8 consecutive D registers. | |||
1436 | if (Subtarget->hasNEON()) { | |||
1437 | if (VT == MVT::v4i64) | |||
1438 | return &ARM::QQPRRegClass; | |||
1439 | if (VT == MVT::v8i64) | |||
1440 | return &ARM::QQQQPRRegClass; | |||
1441 | } | |||
1442 | return TargetLowering::getRegClassFor(VT); | |||
1443 | } | |||
1444 | ||||
1445 | // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the | |||
1446 | // source/dest is aligned and the copy size is large enough. We therefore want | |||
1447 | // to align such objects passed to memory intrinsics. | |||
1448 | bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, | |||
1449 | unsigned &PrefAlign) const { | |||
1450 | if (!isa<MemIntrinsic>(CI)) | |||
1451 | return false; | |||
1452 | MinSize = 8; | |||
1453 | // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1 | |||
1454 | // cycle faster than 4-byte aligned LDM. | |||
1455 | PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); | |||
1456 | return true; | |||
1457 | } | |||
1458 | ||||
1459 | // Create a fast isel object. | |||
1460 | FastISel * | |||
1461 | ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, | |||
1462 | const TargetLibraryInfo *libInfo) const { | |||
1463 | return ARM::createFastISel(funcInfo, libInfo); | |||
1464 | } | |||
1465 | ||||
1466 | Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { | |||
1467 | unsigned NumVals = N->getNumValues(); | |||
1468 | if (!NumVals) | |||
1469 | return Sched::RegPressure; | |||
1470 | ||||
1471 | for (unsigned i = 0; i != NumVals; ++i) { | |||
1472 | EVT VT = N->getValueType(i); | |||
1473 | if (VT == MVT::Glue || VT == MVT::Other) | |||
1474 | continue; | |||
1475 | if (VT.isFloatingPoint() || VT.isVector()) | |||
1476 | return Sched::ILP; | |||
1477 | } | |||
1478 | ||||
1479 | if (!N->isMachineOpcode()) | |||
1480 | return Sched::RegPressure; | |||
1481 | ||||
1482 | // Load are scheduled for latency even if there instruction itinerary | |||
1483 | // is not available. | |||
1484 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
1485 | const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); | |||
1486 | ||||
1487 | if (MCID.getNumDefs() == 0) | |||
1488 | return Sched::RegPressure; | |||
1489 | if (!Itins->isEmpty() && | |||
1490 | Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) | |||
1491 | return Sched::ILP; | |||
1492 | ||||
1493 | return Sched::RegPressure; | |||
1494 | } | |||
1495 | ||||
1496 | //===----------------------------------------------------------------------===// | |||
1497 | // Lowering Code | |||
1498 | //===----------------------------------------------------------------------===// | |||
1499 | ||||
1500 | static bool isSRL16(const SDValue &Op) { | |||
1501 | if (Op.getOpcode() != ISD::SRL) | |||
1502 | return false; | |||
1503 | if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1))) | |||
1504 | return Const->getZExtValue() == 16; | |||
1505 | return false; | |||
1506 | } | |||
1507 | ||||
1508 | static bool isSRA16(const SDValue &Op) { | |||
1509 | if (Op.getOpcode() != ISD::SRA) | |||
1510 | return false; | |||
1511 | if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1))) | |||
1512 | return Const->getZExtValue() == 16; | |||
1513 | return false; | |||
1514 | } | |||
1515 | ||||
1516 | static bool isSHL16(const SDValue &Op) { | |||
1517 | if (Op.getOpcode() != ISD::SHL) | |||
1518 | return false; | |||
1519 | if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1))) | |||
1520 | return Const->getZExtValue() == 16; | |||
1521 | return false; | |||
1522 | } | |||
1523 | ||||
1524 | // Check for a signed 16-bit value. We special case SRA because it makes it | |||
1525 | // more simple when also looking for SRAs that aren't sign extending a | |||
1526 | // smaller value. Without the check, we'd need to take extra care with | |||
1527 | // checking order for some operations. | |||
1528 | static bool isS16(const SDValue &Op, SelectionDAG &DAG) { | |||
1529 | if (isSRA16(Op)) | |||
1530 | return isSHL16(Op.getOperand(0)); | |||
1531 | return DAG.ComputeNumSignBits(Op) == 17; | |||
1532 | } | |||
1533 | ||||
1534 | /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC | |||
1535 | static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { | |||
1536 | switch (CC) { | |||
1537 | default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1537); | |||
1538 | case ISD::SETNE: return ARMCC::NE; | |||
1539 | case ISD::SETEQ: return ARMCC::EQ; | |||
1540 | case ISD::SETGT: return ARMCC::GT; | |||
1541 | case ISD::SETGE: return ARMCC::GE; | |||
1542 | case ISD::SETLT: return ARMCC::LT; | |||
1543 | case ISD::SETLE: return ARMCC::LE; | |||
1544 | case ISD::SETUGT: return ARMCC::HI; | |||
1545 | case ISD::SETUGE: return ARMCC::HS; | |||
1546 | case ISD::SETULT: return ARMCC::LO; | |||
1547 | case ISD::SETULE: return ARMCC::LS; | |||
1548 | } | |||
1549 | } | |||
1550 | ||||
1551 | /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. | |||
1552 | static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, | |||
1553 | ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) { | |||
1554 | CondCode2 = ARMCC::AL; | |||
1555 | InvalidOnQNaN = true; | |||
1556 | switch (CC) { | |||
1557 | default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1557); | |||
1558 | case ISD::SETEQ: | |||
1559 | case ISD::SETOEQ: | |||
1560 | CondCode = ARMCC::EQ; | |||
1561 | InvalidOnQNaN = false; | |||
1562 | break; | |||
1563 | case ISD::SETGT: | |||
1564 | case ISD::SETOGT: CondCode = ARMCC::GT; break; | |||
1565 | case ISD::SETGE: | |||
1566 | case ISD::SETOGE: CondCode = ARMCC::GE; break; | |||
1567 | case ISD::SETOLT: CondCode = ARMCC::MI; break; | |||
1568 | case ISD::SETOLE: CondCode = ARMCC::LS; break; | |||
1569 | case ISD::SETONE: | |||
1570 | CondCode = ARMCC::MI; | |||
1571 | CondCode2 = ARMCC::GT; | |||
1572 | InvalidOnQNaN = false; | |||
1573 | break; | |||
1574 | case ISD::SETO: CondCode = ARMCC::VC; break; | |||
1575 | case ISD::SETUO: CondCode = ARMCC::VS; break; | |||
1576 | case ISD::SETUEQ: | |||
1577 | CondCode = ARMCC::EQ; | |||
1578 | CondCode2 = ARMCC::VS; | |||
1579 | InvalidOnQNaN = false; | |||
1580 | break; | |||
1581 | case ISD::SETUGT: CondCode = ARMCC::HI; break; | |||
1582 | case ISD::SETUGE: CondCode = ARMCC::PL; break; | |||
1583 | case ISD::SETLT: | |||
1584 | case ISD::SETULT: CondCode = ARMCC::LT; break; | |||
1585 | case ISD::SETLE: | |||
1586 | case ISD::SETULE: CondCode = ARMCC::LE; break; | |||
1587 | case ISD::SETNE: | |||
1588 | case ISD::SETUNE: | |||
1589 | CondCode = ARMCC::NE; | |||
1590 | InvalidOnQNaN = false; | |||
1591 | break; | |||
1592 | } | |||
1593 | } | |||
1594 | ||||
1595 | //===----------------------------------------------------------------------===// | |||
1596 | // Calling Convention Implementation | |||
1597 | //===----------------------------------------------------------------------===// | |||
1598 | ||||
1599 | /// getEffectiveCallingConv - Get the effective calling convention, taking into | |||
1600 | /// account presence of floating point hardware and calling convention | |||
1601 | /// limitations, such as support for variadic functions. | |||
1602 | CallingConv::ID | |||
1603 | ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC, | |||
1604 | bool isVarArg) const { | |||
1605 | switch (CC) { | |||
1606 | default: | |||
1607 | report_fatal_error("Unsupported calling convention"); | |||
1608 | case CallingConv::ARM_AAPCS: | |||
1609 | case CallingConv::ARM_APCS: | |||
1610 | case CallingConv::GHC: | |||
1611 | return CC; | |||
1612 | case CallingConv::PreserveMost: | |||
1613 | return CallingConv::PreserveMost; | |||
1614 | case CallingConv::ARM_AAPCS_VFP: | |||
1615 | case CallingConv::Swift: | |||
1616 | return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP; | |||
1617 | case CallingConv::C: | |||
1618 | if (!Subtarget->isAAPCS_ABI()) | |||
1619 | return CallingConv::ARM_APCS; | |||
1620 | else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && | |||
1621 | getTargetMachine().Options.FloatABIType == FloatABI::Hard && | |||
1622 | !isVarArg) | |||
1623 | return CallingConv::ARM_AAPCS_VFP; | |||
1624 | else | |||
1625 | return CallingConv::ARM_AAPCS; | |||
1626 | case CallingConv::Fast: | |||
1627 | case CallingConv::CXX_FAST_TLS: | |||
1628 | if (!Subtarget->isAAPCS_ABI()) { | |||
1629 | if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg) | |||
1630 | return CallingConv::Fast; | |||
1631 | return CallingConv::ARM_APCS; | |||
1632 | } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg) | |||
1633 | return CallingConv::ARM_AAPCS_VFP; | |||
1634 | else | |||
1635 | return CallingConv::ARM_AAPCS; | |||
1636 | } | |||
1637 | } | |||
1638 | ||||
1639 | CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC, | |||
1640 | bool isVarArg) const { | |||
1641 | return CCAssignFnForNode(CC, false, isVarArg); | |||
1642 | } | |||
1643 | ||||
1644 | CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC, | |||
1645 | bool isVarArg) const { | |||
1646 | return CCAssignFnForNode(CC, true, isVarArg); | |||
1647 | } | |||
1648 | ||||
1649 | /// CCAssignFnForNode - Selects the correct CCAssignFn for the given | |||
1650 | /// CallingConvention. | |||
1651 | CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, | |||
1652 | bool Return, | |||
1653 | bool isVarArg) const { | |||
1654 | switch (getEffectiveCallingConv(CC, isVarArg)) { | |||
1655 | default: | |||
1656 | report_fatal_error("Unsupported calling convention"); | |||
1657 | case CallingConv::ARM_APCS: | |||
1658 | return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); | |||
1659 | case CallingConv::ARM_AAPCS: | |||
1660 | return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); | |||
1661 | case CallingConv::ARM_AAPCS_VFP: | |||
1662 | return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); | |||
1663 | case CallingConv::Fast: | |||
1664 | return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); | |||
1665 | case CallingConv::GHC: | |||
1666 | return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC); | |||
1667 | case CallingConv::PreserveMost: | |||
1668 | return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); | |||
1669 | } | |||
1670 | } | |||
1671 | ||||
1672 | /// LowerCallResult - Lower the result values of a call into the | |||
1673 | /// appropriate copies out of appropriate physical registers. | |||
1674 | SDValue ARMTargetLowering::LowerCallResult( | |||
1675 | SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, | |||
1676 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, | |||
1677 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, | |||
1678 | SDValue ThisVal) const { | |||
1679 | // Assign locations to each value returned by this call. | |||
1680 | SmallVector<CCValAssign, 16> RVLocs; | |||
1681 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, | |||
1682 | *DAG.getContext()); | |||
1683 | CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg)); | |||
1684 | ||||
1685 | // Copy all of the result registers out of their specified physreg. | |||
1686 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | |||
1687 | CCValAssign VA = RVLocs[i]; | |||
1688 | ||||
1689 | // Pass 'this' value directly from the argument to return value, to avoid | |||
1690 | // reg unit interference | |||
1691 | if (i == 0 && isThisReturn) { | |||
1692 | assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 && "unexpected return calling convention register assignment") ? static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1693, __PRETTY_FUNCTION__)) | |||
1693 | "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 && "unexpected return calling convention register assignment") ? static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1693, __PRETTY_FUNCTION__)); | |||
1694 | InVals.push_back(ThisVal); | |||
1695 | continue; | |||
1696 | } | |||
1697 | ||||
1698 | SDValue Val; | |||
1699 | if (VA.needsCustom()) { | |||
1700 | // Handle f64 or half of a v2f64. | |||
1701 | SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, | |||
1702 | InFlag); | |||
1703 | Chain = Lo.getValue(1); | |||
1704 | InFlag = Lo.getValue(2); | |||
1705 | VA = RVLocs[++i]; // skip ahead to next loc | |||
1706 | SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, | |||
1707 | InFlag); | |||
1708 | Chain = Hi.getValue(1); | |||
1709 | InFlag = Hi.getValue(2); | |||
1710 | if (!Subtarget->isLittle()) | |||
1711 | std::swap (Lo, Hi); | |||
1712 | Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); | |||
1713 | ||||
1714 | if (VA.getLocVT() == MVT::v2f64) { | |||
1715 | SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); | |||
1716 | Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, | |||
1717 | DAG.getConstant(0, dl, MVT::i32)); | |||
1718 | ||||
1719 | VA = RVLocs[++i]; // skip ahead to next loc | |||
1720 | Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); | |||
1721 | Chain = Lo.getValue(1); | |||
1722 | InFlag = Lo.getValue(2); | |||
1723 | VA = RVLocs[++i]; // skip ahead to next loc | |||
1724 | Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); | |||
1725 | Chain = Hi.getValue(1); | |||
1726 | InFlag = Hi.getValue(2); | |||
1727 | if (!Subtarget->isLittle()) | |||
1728 | std::swap (Lo, Hi); | |||
1729 | Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); | |||
1730 | Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, | |||
1731 | DAG.getConstant(1, dl, MVT::i32)); | |||
1732 | } | |||
1733 | } else { | |||
1734 | Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), | |||
1735 | InFlag); | |||
1736 | Chain = Val.getValue(1); | |||
1737 | InFlag = Val.getValue(2); | |||
1738 | } | |||
1739 | ||||
1740 | switch (VA.getLocInfo()) { | |||
1741 | default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1741); | |||
1742 | case CCValAssign::Full: break; | |||
1743 | case CCValAssign::BCvt: | |||
1744 | Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); | |||
1745 | break; | |||
1746 | } | |||
1747 | ||||
1748 | InVals.push_back(Val); | |||
1749 | } | |||
1750 | ||||
1751 | return Chain; | |||
1752 | } | |||
1753 | ||||
1754 | /// LowerMemOpCallTo - Store the argument to the stack. | |||
1755 | SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, | |||
1756 | SDValue Arg, const SDLoc &dl, | |||
1757 | SelectionDAG &DAG, | |||
1758 | const CCValAssign &VA, | |||
1759 | ISD::ArgFlagsTy Flags) const { | |||
1760 | unsigned LocMemOffset = VA.getLocMemOffset(); | |||
1761 | SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl); | |||
1762 | PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), | |||
1763 | StackPtr, PtrOff); | |||
1764 | return DAG.getStore( | |||
1765 | Chain, dl, Arg, PtrOff, | |||
1766 | MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset)); | |||
1767 | } | |||
1768 | ||||
1769 | void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, | |||
1770 | SDValue Chain, SDValue &Arg, | |||
1771 | RegsToPassVector &RegsToPass, | |||
1772 | CCValAssign &VA, CCValAssign &NextVA, | |||
1773 | SDValue &StackPtr, | |||
1774 | SmallVectorImpl<SDValue> &MemOpChains, | |||
1775 | ISD::ArgFlagsTy Flags) const { | |||
1776 | SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
1777 | DAG.getVTList(MVT::i32, MVT::i32), Arg); | |||
1778 | unsigned id = Subtarget->isLittle() ? 0 : 1; | |||
1779 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); | |||
1780 | ||||
1781 | if (NextVA.isRegLoc()) | |||
1782 | RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); | |||
1783 | else { | |||
1784 | assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1784, __PRETTY_FUNCTION__)); | |||
1785 | if (!StackPtr.getNode()) | |||
1786 | StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, | |||
1787 | getPointerTy(DAG.getDataLayout())); | |||
1788 | ||||
1789 | MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id), | |||
1790 | dl, DAG, NextVA, | |||
1791 | Flags)); | |||
1792 | } | |||
1793 | } | |||
1794 | ||||
1795 | /// LowerCall - Lowering a call into a callseq_start <- | |||
1796 | /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter | |||
1797 | /// nodes. | |||
1798 | SDValue | |||
1799 | ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, | |||
1800 | SmallVectorImpl<SDValue> &InVals) const { | |||
1801 | SelectionDAG &DAG = CLI.DAG; | |||
1802 | SDLoc &dl = CLI.DL; | |||
1803 | SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; | |||
1804 | SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; | |||
1805 | SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; | |||
1806 | SDValue Chain = CLI.Chain; | |||
1807 | SDValue Callee = CLI.Callee; | |||
1808 | bool &isTailCall = CLI.IsTailCall; | |||
1809 | CallingConv::ID CallConv = CLI.CallConv; | |||
1810 | bool doesNotRet = CLI.DoesNotReturn; | |||
1811 | bool isVarArg = CLI.IsVarArg; | |||
1812 | ||||
1813 | MachineFunction &MF = DAG.getMachineFunction(); | |||
1814 | bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); | |||
1815 | bool isThisReturn = false; | |||
1816 | bool isSibCall = false; | |||
1817 | auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls"); | |||
1818 | ||||
1819 | // Disable tail calls if they're not supported. | |||
1820 | if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true") | |||
1821 | isTailCall = false; | |||
1822 | ||||
1823 | if (isTailCall) { | |||
1824 | // Check if it's really possible to do a tail call. | |||
1825 | isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, | |||
1826 | isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(), | |||
1827 | Outs, OutVals, Ins, DAG); | |||
1828 | if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall()) | |||
1829 | report_fatal_error("failed to perform tail call elimination on a call " | |||
1830 | "site marked musttail"); | |||
1831 | // We don't support GuaranteedTailCallOpt for ARM, only automatically | |||
1832 | // detected sibcalls. | |||
1833 | if (isTailCall) { | |||
1834 | ++NumTailCalls; | |||
1835 | isSibCall = true; | |||
1836 | } | |||
1837 | } | |||
1838 | ||||
1839 | // Analyze operands of the call, assigning locations to each operand. | |||
1840 | SmallVector<CCValAssign, 16> ArgLocs; | |||
1841 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, | |||
1842 | *DAG.getContext()); | |||
1843 | CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg)); | |||
1844 | ||||
1845 | // Get a count of how many bytes are to be pushed on the stack. | |||
1846 | unsigned NumBytes = CCInfo.getNextStackOffset(); | |||
1847 | ||||
1848 | // For tail calls, memory operands are available in our caller's stack. | |||
1849 | if (isSibCall) | |||
1850 | NumBytes = 0; | |||
1851 | ||||
1852 | // Adjust the stack pointer for the new arguments... | |||
1853 | // These operations are automatically eliminated by the prolog/epilog pass | |||
1854 | if (!isSibCall) | |||
1855 | Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl); | |||
1856 | ||||
1857 | SDValue StackPtr = | |||
1858 | DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout())); | |||
1859 | ||||
1860 | RegsToPassVector RegsToPass; | |||
1861 | SmallVector<SDValue, 8> MemOpChains; | |||
1862 | ||||
1863 | // Walk the register/memloc assignments, inserting copies/loads. In the case | |||
1864 | // of tail call optimization, arguments are handled later. | |||
1865 | for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); | |||
1866 | i != e; | |||
1867 | ++i, ++realArgIdx) { | |||
1868 | CCValAssign &VA = ArgLocs[i]; | |||
1869 | SDValue Arg = OutVals[realArgIdx]; | |||
1870 | ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; | |||
1871 | bool isByVal = Flags.isByVal(); | |||
1872 | ||||
1873 | // Promote the value if needed. | |||
1874 | switch (VA.getLocInfo()) { | |||
1875 | default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1875); | |||
1876 | case CCValAssign::Full: break; | |||
1877 | case CCValAssign::SExt: | |||
1878 | Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); | |||
1879 | break; | |||
1880 | case CCValAssign::ZExt: | |||
1881 | Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); | |||
1882 | break; | |||
1883 | case CCValAssign::AExt: | |||
1884 | Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); | |||
1885 | break; | |||
1886 | case CCValAssign::BCvt: | |||
1887 | Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); | |||
1888 | break; | |||
1889 | } | |||
1890 | ||||
1891 | // f64 and v2f64 might be passed in i32 pairs and must be split into pieces | |||
1892 | if (VA.needsCustom()) { | |||
1893 | if (VA.getLocVT() == MVT::v2f64) { | |||
1894 | SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, | |||
1895 | DAG.getConstant(0, dl, MVT::i32)); | |||
1896 | SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, | |||
1897 | DAG.getConstant(1, dl, MVT::i32)); | |||
1898 | ||||
1899 | PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, | |||
1900 | VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); | |||
1901 | ||||
1902 | VA = ArgLocs[++i]; // skip ahead to next loc | |||
1903 | if (VA.isRegLoc()) { | |||
1904 | PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, | |||
1905 | VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); | |||
1906 | } else { | |||
1907 | assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1907, __PRETTY_FUNCTION__)); | |||
1908 | ||||
1909 | MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, | |||
1910 | dl, DAG, VA, Flags)); | |||
1911 | } | |||
1912 | } else { | |||
1913 | PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], | |||
1914 | StackPtr, MemOpChains, Flags); | |||
1915 | } | |||
1916 | } else if (VA.isRegLoc()) { | |||
1917 | if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() && | |||
1918 | Outs[0].VT == MVT::i32) { | |||
1919 | assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment" ) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1920, __PRETTY_FUNCTION__)) | |||
1920 | "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment" ) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1920, __PRETTY_FUNCTION__)); | |||
1921 | assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'" ) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1922, __PRETTY_FUNCTION__)) | |||
1922 | "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'" ) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1922, __PRETTY_FUNCTION__)); | |||
1923 | isThisReturn = true; | |||
1924 | } | |||
1925 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); | |||
1926 | } else if (isByVal) { | |||
1927 | assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1927, __PRETTY_FUNCTION__)); | |||
1928 | unsigned offset = 0; | |||
1929 | ||||
1930 | // True if this byval aggregate will be split between registers | |||
1931 | // and memory. | |||
1932 | unsigned ByValArgsCount = CCInfo.getInRegsParamsCount(); | |||
1933 | unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed(); | |||
1934 | ||||
1935 | if (CurByValIdx < ByValArgsCount) { | |||
1936 | ||||
1937 | unsigned RegBegin, RegEnd; | |||
1938 | CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd); | |||
1939 | ||||
1940 | EVT PtrVT = | |||
1941 | DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); | |||
1942 | unsigned int i, j; | |||
1943 | for (i = 0, j = RegBegin; j < RegEnd; i++, j++) { | |||
1944 | SDValue Const = DAG.getConstant(4*i, dl, MVT::i32); | |||
1945 | SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); | |||
1946 | SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, | |||
1947 | MachinePointerInfo(), | |||
1948 | DAG.InferPtrAlignment(AddArg)); | |||
1949 | MemOpChains.push_back(Load.getValue(1)); | |||
1950 | RegsToPass.push_back(std::make_pair(j, Load)); | |||
1951 | } | |||
1952 | ||||
1953 | // If parameter size outsides register area, "offset" value | |||
1954 | // helps us to calculate stack slot for remained part properly. | |||
1955 | offset = RegEnd - RegBegin; | |||
1956 | ||||
1957 | CCInfo.nextInRegsParam(); | |||
1958 | } | |||
1959 | ||||
1960 | if (Flags.getByValSize() > 4*offset) { | |||
1961 | auto PtrVT = getPointerTy(DAG.getDataLayout()); | |||
1962 | unsigned LocMemOffset = VA.getLocMemOffset(); | |||
1963 | SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl); | |||
1964 | SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff); | |||
1965 | SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl); | |||
1966 | SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset); | |||
1967 | SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl, | |||
1968 | MVT::i32); | |||
1969 | SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl, | |||
1970 | MVT::i32); | |||
1971 | ||||
1972 | SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); | |||
1973 | SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode}; | |||
1974 | MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs, | |||
1975 | Ops)); | |||
1976 | } | |||
1977 | } else if (!isSibCall) { | |||
1978 | assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 1978, __PRETTY_FUNCTION__)); | |||
1979 | ||||
1980 | MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, | |||
1981 | dl, DAG, VA, Flags)); | |||
1982 | } | |||
1983 | } | |||
1984 | ||||
1985 | if (!MemOpChains.empty()) | |||
1986 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); | |||
1987 | ||||
1988 | // Build a sequence of copy-to-reg nodes chained together with token chain | |||
1989 | // and flag operands which copy the outgoing args into the appropriate regs. | |||
1990 | SDValue InFlag; | |||
1991 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { | |||
1992 | Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, | |||
1993 | RegsToPass[i].second, InFlag); | |||
1994 | InFlag = Chain.getValue(1); | |||
1995 | } | |||
1996 | ||||
1997 | // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every | |||
1998 | // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol | |||
1999 | // node so that legalize doesn't hack it. | |||
2000 | bool isDirect = false; | |||
2001 | ||||
2002 | const TargetMachine &TM = getTargetMachine(); | |||
2003 | const Module *Mod = MF.getFunction().getParent(); | |||
2004 | const GlobalValue *GV = nullptr; | |||
2005 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) | |||
2006 | GV = G->getGlobal(); | |||
2007 | bool isStub = | |||
2008 | !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO(); | |||
2009 | ||||
2010 | bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); | |||
2011 | bool isLocalARMFunc = false; | |||
2012 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
2013 | auto PtrVt = getPointerTy(DAG.getDataLayout()); | |||
2014 | ||||
2015 | if (Subtarget->genLongCalls()) { | |||
2016 | assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows( )) && "long-calls codegen is not position independent!" ) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2017, __PRETTY_FUNCTION__)) | |||
2017 | "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows( )) && "long-calls codegen is not position independent!" ) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2017, __PRETTY_FUNCTION__)); | |||
2018 | // Handle a global address or an external symbol. If it's not one of | |||
2019 | // those, the target's already in a register, so we don't need to do | |||
2020 | // anything extra. | |||
2021 | if (isa<GlobalAddressSDNode>(Callee)) { | |||
2022 | // Create a constant pool entry for the callee address | |||
2023 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2024 | ARMConstantPoolValue *CPV = | |||
2025 | ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); | |||
2026 | ||||
2027 | // Get the address of the callee into a register | |||
2028 | SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); | |||
2029 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
2030 | Callee = DAG.getLoad( | |||
2031 | PtrVt, dl, DAG.getEntryNode(), CPAddr, | |||
2032 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2033 | } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { | |||
2034 | const char *Sym = S->getSymbol(); | |||
2035 | ||||
2036 | // Create a constant pool entry for the callee address | |||
2037 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2038 | ARMConstantPoolValue *CPV = | |||
2039 | ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, | |||
2040 | ARMPCLabelIndex, 0); | |||
2041 | // Get the address of the callee into a register | |||
2042 | SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); | |||
2043 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
2044 | Callee = DAG.getLoad( | |||
2045 | PtrVt, dl, DAG.getEntryNode(), CPAddr, | |||
2046 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2047 | } | |||
2048 | } else if (isa<GlobalAddressSDNode>(Callee)) { | |||
2049 | // If we're optimizing for minimum size and the function is called three or | |||
2050 | // more times in this block, we can improve codesize by calling indirectly | |||
2051 | // as BLXr has a 16-bit encoding. | |||
2052 | auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal(); | |||
2053 | auto *BB = CLI.CS.getParent(); | |||
2054 | bool PreferIndirect = | |||
2055 | Subtarget->isThumb() && Subtarget->hasMinSize() && | |||
2056 | count_if(GV->users(), [&BB](const User *U) { | |||
2057 | return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB; | |||
2058 | }) > 2; | |||
2059 | ||||
2060 | if (!PreferIndirect) { | |||
2061 | isDirect = true; | |||
2062 | bool isDef = GV->isStrongDefinitionForLinker(); | |||
2063 | ||||
2064 | // ARM call to a local ARM function is predicable. | |||
2065 | isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking); | |||
2066 | // tBX takes a register source operand. | |||
2067 | if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { | |||
2068 | assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2068, __PRETTY_FUNCTION__)); | |||
2069 | Callee = DAG.getNode( | |||
2070 | ARMISD::WrapperPIC, dl, PtrVt, | |||
2071 | DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY)); | |||
2072 | Callee = DAG.getLoad( | |||
2073 | PtrVt, dl, DAG.getEntryNode(), Callee, | |||
2074 | MachinePointerInfo::getGOT(DAG.getMachineFunction()), | |||
2075 | /* Alignment = */ 0, MachineMemOperand::MODereferenceable | | |||
2076 | MachineMemOperand::MOInvariant); | |||
2077 | } else if (Subtarget->isTargetCOFF()) { | |||
2078 | assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2079, __PRETTY_FUNCTION__)) | |||
2079 | "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2079, __PRETTY_FUNCTION__)); | |||
2080 | unsigned TargetFlags = GV->hasDLLImportStorageClass() | |||
2081 | ? ARMII::MO_DLLIMPORT | |||
2082 | : ARMII::MO_NO_FLAG; | |||
2083 | Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0, | |||
2084 | TargetFlags); | |||
2085 | if (GV->hasDLLImportStorageClass()) | |||
2086 | Callee = | |||
2087 | DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), | |||
2088 | DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee), | |||
2089 | MachinePointerInfo::getGOT(DAG.getMachineFunction())); | |||
2090 | } else { | |||
2091 | Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0); | |||
2092 | } | |||
2093 | } | |||
2094 | } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { | |||
2095 | isDirect = true; | |||
2096 | // tBX takes a register source operand. | |||
2097 | const char *Sym = S->getSymbol(); | |||
2098 | if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { | |||
2099 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2100 | ARMConstantPoolValue *CPV = | |||
2101 | ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, | |||
2102 | ARMPCLabelIndex, 4); | |||
2103 | SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); | |||
2104 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
2105 | Callee = DAG.getLoad( | |||
2106 | PtrVt, dl, DAG.getEntryNode(), CPAddr, | |||
2107 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2108 | SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); | |||
2109 | Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel); | |||
2110 | } else { | |||
2111 | Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0); | |||
2112 | } | |||
2113 | } | |||
2114 | ||||
2115 | // FIXME: handle tail calls differently. | |||
2116 | unsigned CallOpc; | |||
2117 | if (Subtarget->isThumb()) { | |||
2118 | if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) | |||
2119 | CallOpc = ARMISD::CALL_NOLINK; | |||
2120 | else | |||
2121 | CallOpc = ARMISD::CALL; | |||
2122 | } else { | |||
2123 | if (!isDirect && !Subtarget->hasV5TOps()) | |||
2124 | CallOpc = ARMISD::CALL_NOLINK; | |||
2125 | else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() && | |||
2126 | // Emit regular call when code size is the priority | |||
2127 | !Subtarget->hasMinSize()) | |||
2128 | // "mov lr, pc; b _foo" to avoid confusing the RSP | |||
2129 | CallOpc = ARMISD::CALL_NOLINK; | |||
2130 | else | |||
2131 | CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL; | |||
2132 | } | |||
2133 | ||||
2134 | std::vector<SDValue> Ops; | |||
2135 | Ops.push_back(Chain); | |||
2136 | Ops.push_back(Callee); | |||
2137 | ||||
2138 | // Add argument registers to the end of the list so that they are known live | |||
2139 | // into the call. | |||
2140 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) | |||
2141 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, | |||
2142 | RegsToPass[i].second.getValueType())); | |||
2143 | ||||
2144 | // Add a register mask operand representing the call-preserved registers. | |||
2145 | if (!isTailCall) { | |||
2146 | const uint32_t *Mask; | |||
2147 | const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo(); | |||
2148 | if (isThisReturn) { | |||
2149 | // For 'this' returns, use the R0-preserving mask if applicable | |||
2150 | Mask = ARI->getThisReturnPreservedMask(MF, CallConv); | |||
2151 | if (!Mask) { | |||
2152 | // Set isThisReturn to false if the calling convention is not one that | |||
2153 | // allows 'returned' to be modeled in this way, so LowerCallResult does | |||
2154 | // not try to pass 'this' straight through | |||
2155 | isThisReturn = false; | |||
2156 | Mask = ARI->getCallPreservedMask(MF, CallConv); | |||
2157 | } | |||
2158 | } else | |||
2159 | Mask = ARI->getCallPreservedMask(MF, CallConv); | |||
2160 | ||||
2161 | assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention" ) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2161, __PRETTY_FUNCTION__)); | |||
2162 | Ops.push_back(DAG.getRegisterMask(Mask)); | |||
2163 | } | |||
2164 | ||||
2165 | if (InFlag.getNode()) | |||
2166 | Ops.push_back(InFlag); | |||
2167 | ||||
2168 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
2169 | if (isTailCall) { | |||
2170 | MF.getFrameInfo().setHasTailCall(); | |||
2171 | return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops); | |||
2172 | } | |||
2173 | ||||
2174 | // Returns a chain and a flag for retval copy to use. | |||
2175 | Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops); | |||
2176 | InFlag = Chain.getValue(1); | |||
2177 | ||||
2178 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true), | |||
2179 | DAG.getIntPtrConstant(0, dl, true), InFlag, dl); | |||
2180 | if (!Ins.empty()) | |||
2181 | InFlag = Chain.getValue(1); | |||
2182 | ||||
2183 | // Handle result values, copying them out of physregs into vregs that we | |||
2184 | // return. | |||
2185 | return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, | |||
2186 | InVals, isThisReturn, | |||
2187 | isThisReturn ? OutVals[0] : SDValue()); | |||
2188 | } | |||
2189 | ||||
2190 | /// HandleByVal - Every parameter *after* a byval parameter is passed | |||
2191 | /// on the stack. Remember the next parameter register to allocate, | |||
2192 | /// and then confiscate the rest of the parameter registers to insure | |||
2193 | /// this. | |||
2194 | void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size, | |||
2195 | unsigned Align) const { | |||
2196 | // Byval (as with any stack) slots are always at least 4 byte aligned. | |||
2197 | Align = std::max(Align, 4U); | |||
2198 | ||||
2199 | unsigned Reg = State->AllocateReg(GPRArgRegs); | |||
2200 | if (!Reg) | |||
2201 | return; | |||
2202 | ||||
2203 | unsigned AlignInRegs = Align / 4; | |||
2204 | unsigned Waste = (ARM::R4 - Reg) % AlignInRegs; | |||
2205 | for (unsigned i = 0; i < Waste; ++i) | |||
2206 | Reg = State->AllocateReg(GPRArgRegs); | |||
2207 | ||||
2208 | if (!Reg) | |||
2209 | return; | |||
2210 | ||||
2211 | unsigned Excess = 4 * (ARM::R4 - Reg); | |||
2212 | ||||
2213 | // Special case when NSAA != SP and parameter size greater than size of | |||
2214 | // all remained GPR regs. In that case we can't split parameter, we must | |||
2215 | // send it to stack. We also must set NCRN to R4, so waste all | |||
2216 | // remained registers. | |||
2217 | const unsigned NSAAOffset = State->getNextStackOffset(); | |||
2218 | if (NSAAOffset != 0 && Size > Excess) { | |||
2219 | while (State->AllocateReg(GPRArgRegs)) | |||
2220 | ; | |||
2221 | return; | |||
2222 | } | |||
2223 | ||||
2224 | // First register for byval parameter is the first register that wasn't | |||
2225 | // allocated before this method call, so it would be "reg". | |||
2226 | // If parameter is small enough to be saved in range [reg, r4), then | |||
2227 | // the end (first after last) register would be reg + param-size-in-regs, | |||
2228 | // else parameter would be splitted between registers and stack, | |||
2229 | // end register would be r4 in this case. | |||
2230 | unsigned ByValRegBegin = Reg; | |||
2231 | unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4); | |||
2232 | State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd); | |||
2233 | // Note, first register is allocated in the beginning of function already, | |||
2234 | // allocate remained amount of registers we need. | |||
2235 | for (unsigned i = Reg + 1; i != ByValRegEnd; ++i) | |||
2236 | State->AllocateReg(GPRArgRegs); | |||
2237 | // A byval parameter that is split between registers and memory needs its | |||
2238 | // size truncated here. | |||
2239 | // In the case where the entire structure fits in registers, we set the | |||
2240 | // size in memory to zero. | |||
2241 | Size = std::max<int>(Size - Excess, 0); | |||
2242 | } | |||
2243 | ||||
2244 | /// MatchingStackOffset - Return true if the given stack call argument is | |||
2245 | /// already available in the same position (relatively) of the caller's | |||
2246 | /// incoming argument stack. | |||
2247 | static | |||
2248 | bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, | |||
2249 | MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, | |||
2250 | const TargetInstrInfo *TII) { | |||
2251 | unsigned Bytes = Arg.getValueSizeInBits() / 8; | |||
2252 | int FI = std::numeric_limits<int>::max(); | |||
2253 | if (Arg.getOpcode() == ISD::CopyFromReg) { | |||
2254 | unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); | |||
2255 | if (!TargetRegisterInfo::isVirtualRegister(VR)) | |||
2256 | return false; | |||
2257 | MachineInstr *Def = MRI->getVRegDef(VR); | |||
2258 | if (!Def) | |||
2259 | return false; | |||
2260 | if (!Flags.isByVal()) { | |||
2261 | if (!TII->isLoadFromStackSlot(*Def, FI)) | |||
2262 | return false; | |||
2263 | } else { | |||
2264 | return false; | |||
2265 | } | |||
2266 | } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { | |||
2267 | if (Flags.isByVal()) | |||
2268 | // ByVal argument is passed in as a pointer but it's now being | |||
2269 | // dereferenced. e.g. | |||
2270 | // define @foo(%struct.X* %A) { | |||
2271 | // tail call @bar(%struct.X* byval %A) | |||
2272 | // } | |||
2273 | return false; | |||
2274 | SDValue Ptr = Ld->getBasePtr(); | |||
2275 | FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); | |||
2276 | if (!FINode) | |||
2277 | return false; | |||
2278 | FI = FINode->getIndex(); | |||
2279 | } else | |||
2280 | return false; | |||
2281 | ||||
2282 | assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast< void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2282, __PRETTY_FUNCTION__)); | |||
2283 | if (!MFI.isFixedObjectIndex(FI)) | |||
2284 | return false; | |||
2285 | return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI); | |||
2286 | } | |||
2287 | ||||
2288 | /// IsEligibleForTailCallOptimization - Check whether the call is eligible | |||
2289 | /// for tail call optimization. Targets which want to do tail call | |||
2290 | /// optimization should implement this function. | |||
2291 | bool | |||
2292 | ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, | |||
2293 | CallingConv::ID CalleeCC, | |||
2294 | bool isVarArg, | |||
2295 | bool isCalleeStructRet, | |||
2296 | bool isCallerStructRet, | |||
2297 | const SmallVectorImpl<ISD::OutputArg> &Outs, | |||
2298 | const SmallVectorImpl<SDValue> &OutVals, | |||
2299 | const SmallVectorImpl<ISD::InputArg> &Ins, | |||
2300 | SelectionDAG& DAG) const { | |||
2301 | MachineFunction &MF = DAG.getMachineFunction(); | |||
2302 | const Function &CallerF = MF.getFunction(); | |||
2303 | CallingConv::ID CallerCC = CallerF.getCallingConv(); | |||
2304 | ||||
2305 | assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void> (0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2305, __PRETTY_FUNCTION__)); | |||
2306 | ||||
2307 | // Tail calls to function pointers cannot be optimized for Thumb1 if the args | |||
2308 | // to the call take up r0-r3. The reason is that there are no legal registers | |||
2309 | // left to hold the pointer to the function to be called. | |||
2310 | if (Subtarget->isThumb1Only() && Outs.size() >= 4 && | |||
2311 | !isa<GlobalAddressSDNode>(Callee.getNode())) | |||
2312 | return false; | |||
2313 | ||||
2314 | // Look for obvious safe cases to perform tail call optimization that do not | |||
2315 | // require ABI changes. This is what gcc calls sibcall. | |||
2316 | ||||
2317 | // Exception-handling functions need a special set of instructions to indicate | |||
2318 | // a return to the hardware. Tail-calling another function would probably | |||
2319 | // break this. | |||
2320 | if (CallerF.hasFnAttribute("interrupt")) | |||
2321 | return false; | |||
2322 | ||||
2323 | // Also avoid sibcall optimization if either caller or callee uses struct | |||
2324 | // return semantics. | |||
2325 | if (isCalleeStructRet || isCallerStructRet) | |||
2326 | return false; | |||
2327 | ||||
2328 | // Externally-defined functions with weak linkage should not be | |||
2329 | // tail-called on ARM when the OS does not support dynamic | |||
2330 | // pre-emption of symbols, as the AAELF spec requires normal calls | |||
2331 | // to undefined weak functions to be replaced with a NOP or jump to the | |||
2332 | // next instruction. The behaviour of branch instructions in this | |||
2333 | // situation (as used for tail calls) is implementation-defined, so we | |||
2334 | // cannot rely on the linker replacing the tail call with a return. | |||
2335 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { | |||
2336 | const GlobalValue *GV = G->getGlobal(); | |||
2337 | const Triple &TT = getTargetMachine().getTargetTriple(); | |||
2338 | if (GV->hasExternalWeakLinkage() && | |||
2339 | (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO())) | |||
2340 | return false; | |||
2341 | } | |||
2342 | ||||
2343 | // Check that the call results are passed in the same way. | |||
2344 | LLVMContext &C = *DAG.getContext(); | |||
2345 | if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, | |||
2346 | CCAssignFnForReturn(CalleeCC, isVarArg), | |||
2347 | CCAssignFnForReturn(CallerCC, isVarArg))) | |||
2348 | return false; | |||
2349 | // The callee has to preserve all registers the caller needs to preserve. | |||
2350 | const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); | |||
2351 | const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC); | |||
2352 | if (CalleeCC != CallerCC) { | |||
2353 | const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC); | |||
2354 | if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) | |||
2355 | return false; | |||
2356 | } | |||
2357 | ||||
2358 | // If Caller's vararg or byval argument has been split between registers and | |||
2359 | // stack, do not perform tail call, since part of the argument is in caller's | |||
2360 | // local frame. | |||
2361 | const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>(); | |||
2362 | if (AFI_Caller->getArgRegsSaveSize()) | |||
2363 | return false; | |||
2364 | ||||
2365 | // If the callee takes no arguments then go on to check the results of the | |||
2366 | // call. | |||
2367 | if (!Outs.empty()) { | |||
2368 | // Check if stack adjustment is needed. For now, do not do this if any | |||
2369 | // argument is passed on the stack. | |||
2370 | SmallVector<CCValAssign, 16> ArgLocs; | |||
2371 | CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C); | |||
2372 | CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg)); | |||
2373 | if (CCInfo.getNextStackOffset()) { | |||
2374 | // Check if the arguments are already laid out in the right way as | |||
2375 | // the caller's fixed stack objects. | |||
2376 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
2377 | const MachineRegisterInfo *MRI = &MF.getRegInfo(); | |||
2378 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
2379 | for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); | |||
2380 | i != e; | |||
2381 | ++i, ++realArgIdx) { | |||
2382 | CCValAssign &VA = ArgLocs[i]; | |||
2383 | EVT RegVT = VA.getLocVT(); | |||
2384 | SDValue Arg = OutVals[realArgIdx]; | |||
2385 | ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; | |||
2386 | if (VA.getLocInfo() == CCValAssign::Indirect) | |||
2387 | return false; | |||
2388 | if (VA.needsCustom()) { | |||
2389 | // f64 and vector types are split into multiple registers or | |||
2390 | // register/stack-slot combinations. The types will not match | |||
2391 | // the registers; give up on memory f64 refs until we figure | |||
2392 | // out what to do about this. | |||
2393 | if (!VA.isRegLoc()) | |||
2394 | return false; | |||
2395 | if (!ArgLocs[++i].isRegLoc()) | |||
2396 | return false; | |||
2397 | if (RegVT == MVT::v2f64) { | |||
2398 | if (!ArgLocs[++i].isRegLoc()) | |||
2399 | return false; | |||
2400 | if (!ArgLocs[++i].isRegLoc()) | |||
2401 | return false; | |||
2402 | } | |||
2403 | } else if (!VA.isRegLoc()) { | |||
2404 | if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, | |||
2405 | MFI, MRI, TII)) | |||
2406 | return false; | |||
2407 | } | |||
2408 | } | |||
2409 | } | |||
2410 | ||||
2411 | const MachineRegisterInfo &MRI = MF.getRegInfo(); | |||
2412 | if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) | |||
2413 | return false; | |||
2414 | } | |||
2415 | ||||
2416 | return true; | |||
2417 | } | |||
2418 | ||||
2419 | bool | |||
2420 | ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv, | |||
2421 | MachineFunction &MF, bool isVarArg, | |||
2422 | const SmallVectorImpl<ISD::OutputArg> &Outs, | |||
2423 | LLVMContext &Context) const { | |||
2424 | SmallVector<CCValAssign, 16> RVLocs; | |||
2425 | CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); | |||
2426 | return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg)); | |||
2427 | } | |||
2428 | ||||
2429 | static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, | |||
2430 | const SDLoc &DL, SelectionDAG &DAG) { | |||
2431 | const MachineFunction &MF = DAG.getMachineFunction(); | |||
2432 | const Function &F = MF.getFunction(); | |||
2433 | ||||
2434 | StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString(); | |||
2435 | ||||
2436 | // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset | |||
2437 | // version of the "preferred return address". These offsets affect the return | |||
2438 | // instruction if this is a return from PL1 without hypervisor extensions. | |||
2439 | // IRQ/FIQ: +4 "subs pc, lr, #4" | |||
2440 | // SWI: 0 "subs pc, lr, #0" | |||
2441 | // ABORT: +4 "subs pc, lr, #4" | |||
2442 | // UNDEF: +4/+2 "subs pc, lr, #0" | |||
2443 | // UNDEF varies depending on where the exception came from ARM or Thumb | |||
2444 | // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0. | |||
2445 | ||||
2446 | int64_t LROffset; | |||
2447 | if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" || | |||
2448 | IntKind == "ABORT") | |||
2449 | LROffset = 4; | |||
2450 | else if (IntKind == "SWI" || IntKind == "UNDEF") | |||
2451 | LROffset = 0; | |||
2452 | else | |||
2453 | report_fatal_error("Unsupported interrupt attribute. If present, value " | |||
2454 | "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF"); | |||
2455 | ||||
2456 | RetOps.insert(RetOps.begin() + 1, | |||
2457 | DAG.getConstant(LROffset, DL, MVT::i32, false)); | |||
2458 | ||||
2459 | return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps); | |||
2460 | } | |||
2461 | ||||
2462 | SDValue | |||
2463 | ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, | |||
2464 | bool isVarArg, | |||
2465 | const SmallVectorImpl<ISD::OutputArg> &Outs, | |||
2466 | const SmallVectorImpl<SDValue> &OutVals, | |||
2467 | const SDLoc &dl, SelectionDAG &DAG) const { | |||
2468 | // CCValAssign - represent the assignment of the return value to a location. | |||
2469 | SmallVector<CCValAssign, 16> RVLocs; | |||
2470 | ||||
2471 | // CCState - Info about the registers and stack slots. | |||
2472 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, | |||
2473 | *DAG.getContext()); | |||
2474 | ||||
2475 | // Analyze outgoing return values. | |||
2476 | CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg)); | |||
2477 | ||||
2478 | SDValue Flag; | |||
2479 | SmallVector<SDValue, 4> RetOps; | |||
2480 | RetOps.push_back(Chain); // Operand #0 = Chain (updated below) | |||
2481 | bool isLittleEndian = Subtarget->isLittle(); | |||
2482 | ||||
2483 | MachineFunction &MF = DAG.getMachineFunction(); | |||
2484 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
2485 | AFI->setReturnRegsCount(RVLocs.size()); | |||
2486 | ||||
2487 | // Copy the result values into the output registers. | |||
2488 | for (unsigned i = 0, realRVLocIdx = 0; | |||
2489 | i != RVLocs.size(); | |||
2490 | ++i, ++realRVLocIdx) { | |||
2491 | CCValAssign &VA = RVLocs[i]; | |||
2492 | assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2492, __PRETTY_FUNCTION__)); | |||
2493 | ||||
2494 | SDValue Arg = OutVals[realRVLocIdx]; | |||
2495 | bool ReturnF16 = false; | |||
2496 | ||||
2497 | if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) { | |||
2498 | // Half-precision return values can be returned like this: | |||
2499 | // | |||
2500 | // t11 f16 = fadd ... | |||
2501 | // t12: i16 = bitcast t11 | |||
2502 | // t13: i32 = zero_extend t12 | |||
2503 | // t14: f32 = bitcast t13 <~~~~~~~ Arg | |||
2504 | // | |||
2505 | // to avoid code generation for bitcasts, we simply set Arg to the node | |||
2506 | // that produces the f16 value, t11 in this case. | |||
2507 | // | |||
2508 | if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) { | |||
2509 | SDValue ZE = Arg.getOperand(0); | |||
2510 | if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) { | |||
2511 | SDValue BC = ZE.getOperand(0); | |||
2512 | if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) { | |||
2513 | Arg = BC.getOperand(0); | |||
2514 | ReturnF16 = true; | |||
2515 | } | |||
2516 | } | |||
2517 | } | |||
2518 | } | |||
2519 | ||||
2520 | switch (VA.getLocInfo()) { | |||
2521 | default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2521); | |||
2522 | case CCValAssign::Full: break; | |||
2523 | case CCValAssign::BCvt: | |||
2524 | if (!ReturnF16) | |||
2525 | Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); | |||
2526 | break; | |||
2527 | } | |||
2528 | ||||
2529 | if (VA.needsCustom()) { | |||
2530 | if (VA.getLocVT() == MVT::v2f64) { | |||
2531 | // Extract the first half and return it in two registers. | |||
2532 | SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, | |||
2533 | DAG.getConstant(0, dl, MVT::i32)); | |||
2534 | SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
2535 | DAG.getVTList(MVT::i32, MVT::i32), Half); | |||
2536 | ||||
2537 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), | |||
2538 | HalfGPRs.getValue(isLittleEndian ? 0 : 1), | |||
2539 | Flag); | |||
2540 | Flag = Chain.getValue(1); | |||
2541 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); | |||
2542 | VA = RVLocs[++i]; // skip ahead to next loc | |||
2543 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), | |||
2544 | HalfGPRs.getValue(isLittleEndian ? 1 : 0), | |||
2545 | Flag); | |||
2546 | Flag = Chain.getValue(1); | |||
2547 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); | |||
2548 | VA = RVLocs[++i]; // skip ahead to next loc | |||
2549 | ||||
2550 | // Extract the 2nd half and fall through to handle it as an f64 value. | |||
2551 | Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, | |||
2552 | DAG.getConstant(1, dl, MVT::i32)); | |||
2553 | } | |||
2554 | // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is | |||
2555 | // available. | |||
2556 | SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
2557 | DAG.getVTList(MVT::i32, MVT::i32), Arg); | |||
2558 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), | |||
2559 | fmrrd.getValue(isLittleEndian ? 0 : 1), | |||
2560 | Flag); | |||
2561 | Flag = Chain.getValue(1); | |||
2562 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); | |||
2563 | VA = RVLocs[++i]; // skip ahead to next loc | |||
2564 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), | |||
2565 | fmrrd.getValue(isLittleEndian ? 1 : 0), | |||
2566 | Flag); | |||
2567 | } else | |||
2568 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); | |||
2569 | ||||
2570 | // Guarantee that all emitted copies are | |||
2571 | // stuck together, avoiding something bad. | |||
2572 | Flag = Chain.getValue(1); | |||
2573 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), | |||
2574 | ReturnF16 ? MVT::f16 : VA.getLocVT())); | |||
2575 | } | |||
2576 | const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); | |||
2577 | const MCPhysReg *I = | |||
2578 | TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction()); | |||
2579 | if (I) { | |||
2580 | for (; *I; ++I) { | |||
2581 | if (ARM::GPRRegClass.contains(*I)) | |||
2582 | RetOps.push_back(DAG.getRegister(*I, MVT::i32)); | |||
2583 | else if (ARM::DPRRegClass.contains(*I)) | |||
2584 | RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64))); | |||
2585 | else | |||
2586 | llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2586); | |||
2587 | } | |||
2588 | } | |||
2589 | ||||
2590 | // Update chain and glue. | |||
2591 | RetOps[0] = Chain; | |||
2592 | if (Flag.getNode()) | |||
2593 | RetOps.push_back(Flag); | |||
2594 | ||||
2595 | // CPUs which aren't M-class use a special sequence to return from | |||
2596 | // exceptions (roughly, any instruction setting pc and cpsr simultaneously, | |||
2597 | // though we use "subs pc, lr, #N"). | |||
2598 | // | |||
2599 | // M-class CPUs actually use a normal return sequence with a special | |||
2600 | // (hardware-provided) value in LR, so the normal code path works. | |||
2601 | if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") && | |||
2602 | !Subtarget->isMClass()) { | |||
2603 | if (Subtarget->isThumb1Only()) | |||
2604 | report_fatal_error("interrupt attribute is not supported in Thumb1"); | |||
2605 | return LowerInterruptReturn(RetOps, dl, DAG); | |||
2606 | } | |||
2607 | ||||
2608 | return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps); | |||
2609 | } | |||
2610 | ||||
2611 | bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { | |||
2612 | if (N->getNumValues() != 1) | |||
2613 | return false; | |||
2614 | if (!N->hasNUsesOfValue(1, 0)) | |||
2615 | return false; | |||
2616 | ||||
2617 | SDValue TCChain = Chain; | |||
2618 | SDNode *Copy = *N->use_begin(); | |||
2619 | if (Copy->getOpcode() == ISD::CopyToReg) { | |||
2620 | // If the copy has a glue operand, we conservatively assume it isn't safe to | |||
2621 | // perform a tail call. | |||
2622 | if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) | |||
2623 | return false; | |||
2624 | TCChain = Copy->getOperand(0); | |||
2625 | } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { | |||
2626 | SDNode *VMov = Copy; | |||
2627 | // f64 returned in a pair of GPRs. | |||
2628 | SmallPtrSet<SDNode*, 2> Copies; | |||
2629 | for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end(); | |||
2630 | UI != UE; ++UI) { | |||
2631 | if (UI->getOpcode() != ISD::CopyToReg) | |||
2632 | return false; | |||
2633 | Copies.insert(*UI); | |||
2634 | } | |||
2635 | if (Copies.size() > 2) | |||
2636 | return false; | |||
2637 | ||||
2638 | for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end(); | |||
2639 | UI != UE; ++UI) { | |||
2640 | SDValue UseChain = UI->getOperand(0); | |||
2641 | if (Copies.count(UseChain.getNode())) | |||
2642 | // Second CopyToReg | |||
2643 | Copy = *UI; | |||
2644 | else { | |||
2645 | // We are at the top of this chain. | |||
2646 | // If the copy has a glue operand, we conservatively assume it | |||
2647 | // isn't safe to perform a tail call. | |||
2648 | if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue) | |||
2649 | return false; | |||
2650 | // First CopyToReg | |||
2651 | TCChain = UseChain; | |||
2652 | } | |||
2653 | } | |||
2654 | } else if (Copy->getOpcode() == ISD::BITCAST) { | |||
2655 | // f32 returned in a single GPR. | |||
2656 | if (!Copy->hasOneUse()) | |||
2657 | return false; | |||
2658 | Copy = *Copy->use_begin(); | |||
2659 | if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0)) | |||
2660 | return false; | |||
2661 | // If the copy has a glue operand, we conservatively assume it isn't safe to | |||
2662 | // perform a tail call. | |||
2663 | if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) | |||
2664 | return false; | |||
2665 | TCChain = Copy->getOperand(0); | |||
2666 | } else { | |||
2667 | return false; | |||
2668 | } | |||
2669 | ||||
2670 | bool HasRet = false; | |||
2671 | for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); | |||
2672 | UI != UE; ++UI) { | |||
2673 | if (UI->getOpcode() != ARMISD::RET_FLAG && | |||
2674 | UI->getOpcode() != ARMISD::INTRET_FLAG) | |||
2675 | return false; | |||
2676 | HasRet = true; | |||
2677 | } | |||
2678 | ||||
2679 | if (!HasRet) | |||
2680 | return false; | |||
2681 | ||||
2682 | Chain = TCChain; | |||
2683 | return true; | |||
2684 | } | |||
2685 | ||||
2686 | bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { | |||
2687 | if (!Subtarget->supportsTailCall()) | |||
2688 | return false; | |||
2689 | ||||
2690 | auto Attr = | |||
2691 | CI->getParent()->getParent()->getFnAttribute("disable-tail-calls"); | |||
2692 | if (!CI->isTailCall() || Attr.getValueAsString() == "true") | |||
2693 | return false; | |||
2694 | ||||
2695 | return true; | |||
2696 | } | |||
2697 | ||||
2698 | // Trying to write a 64 bit value so need to split into two 32 bit values first, | |||
2699 | // and pass the lower and high parts through. | |||
2700 | static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) { | |||
2701 | SDLoc DL(Op); | |||
2702 | SDValue WriteValue = Op->getOperand(2); | |||
2703 | ||||
2704 | // This function is only supposed to be called for i64 type argument. | |||
2705 | assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument." ) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2706, __PRETTY_FUNCTION__)) | |||
2706 | && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument." ) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2706, __PRETTY_FUNCTION__)); | |||
2707 | ||||
2708 | SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, | |||
2709 | DAG.getConstant(0, DL, MVT::i32)); | |||
2710 | SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, | |||
2711 | DAG.getConstant(1, DL, MVT::i32)); | |||
2712 | SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi }; | |||
2713 | return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops); | |||
2714 | } | |||
2715 | ||||
2716 | // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as | |||
2717 | // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is | |||
2718 | // one of the above mentioned nodes. It has to be wrapped because otherwise | |||
2719 | // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only | |||
2720 | // be used to form addressing mode. These wrapped nodes will be selected | |||
2721 | // into MOVi. | |||
2722 | SDValue ARMTargetLowering::LowerConstantPool(SDValue Op, | |||
2723 | SelectionDAG &DAG) const { | |||
2724 | EVT PtrVT = Op.getValueType(); | |||
2725 | // FIXME there is no actual debug info here | |||
2726 | SDLoc dl(Op); | |||
2727 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); | |||
2728 | SDValue Res; | |||
2729 | ||||
2730 | // When generating execute-only code Constant Pools must be promoted to the | |||
2731 | // global data section. It's a bit ugly that we can't share them across basic | |||
2732 | // blocks, but this way we guarantee that execute-only behaves correct with | |||
2733 | // position-independent addressing modes. | |||
2734 | if (Subtarget->genExecuteOnly()) { | |||
2735 | auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); | |||
2736 | auto T = const_cast<Type*>(CP->getType()); | |||
2737 | auto C = const_cast<Constant*>(CP->getConstVal()); | |||
2738 | auto M = const_cast<Module*>(DAG.getMachineFunction(). | |||
2739 | getFunction().getParent()); | |||
2740 | auto GV = new GlobalVariable( | |||
2741 | *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C, | |||
2742 | Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" + | |||
2743 | Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" + | |||
2744 | Twine(AFI->createPICLabelUId()) | |||
2745 | ); | |||
2746 | SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV), | |||
2747 | dl, PtrVT); | |||
2748 | return LowerGlobalAddress(GA, DAG); | |||
2749 | } | |||
2750 | ||||
2751 | if (CP->isMachineConstantPoolEntry()) | |||
2752 | Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, | |||
2753 | CP->getAlignment()); | |||
2754 | else | |||
2755 | Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, | |||
2756 | CP->getAlignment()); | |||
2757 | return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); | |||
2758 | } | |||
2759 | ||||
2760 | unsigned ARMTargetLowering::getJumpTableEncoding() const { | |||
2761 | return MachineJumpTableInfo::EK_Inline; | |||
2762 | } | |||
2763 | ||||
2764 | SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, | |||
2765 | SelectionDAG &DAG) const { | |||
2766 | MachineFunction &MF = DAG.getMachineFunction(); | |||
2767 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
2768 | unsigned ARMPCLabelIndex = 0; | |||
2769 | SDLoc DL(Op); | |||
2770 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
2771 | const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); | |||
2772 | SDValue CPAddr; | |||
2773 | bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI(); | |||
2774 | if (!IsPositionIndependent) { | |||
2775 | CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); | |||
2776 | } else { | |||
2777 | unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; | |||
2778 | ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2779 | ARMConstantPoolValue *CPV = | |||
2780 | ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, | |||
2781 | ARMCP::CPBlockAddress, PCAdj); | |||
2782 | CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
2783 | } | |||
2784 | CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); | |||
2785 | SDValue Result = DAG.getLoad( | |||
2786 | PtrVT, DL, DAG.getEntryNode(), CPAddr, | |||
2787 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2788 | if (!IsPositionIndependent) | |||
2789 | return Result; | |||
2790 | SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32); | |||
2791 | return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); | |||
2792 | } | |||
2793 | ||||
2794 | /// Convert a TLS address reference into the correct sequence of loads | |||
2795 | /// and calls to compute the variable's address for Darwin, and return an | |||
2796 | /// SDValue containing the final node. | |||
2797 | ||||
2798 | /// Darwin only has one TLS scheme which must be capable of dealing with the | |||
2799 | /// fully general situation, in the worst case. This means: | |||
2800 | /// + "extern __thread" declaration. | |||
2801 | /// + Defined in a possibly unknown dynamic library. | |||
2802 | /// | |||
2803 | /// The general system is that each __thread variable has a [3 x i32] descriptor | |||
2804 | /// which contains information used by the runtime to calculate the address. The | |||
2805 | /// only part of this the compiler needs to know about is the first word, which | |||
2806 | /// contains a function pointer that must be called with the address of the | |||
2807 | /// entire descriptor in "r0". | |||
2808 | /// | |||
2809 | /// Since this descriptor may be in a different unit, in general access must | |||
2810 | /// proceed along the usual ARM rules. A common sequence to produce is: | |||
2811 | /// | |||
2812 | /// movw rT1, :lower16:_var$non_lazy_ptr | |||
2813 | /// movt rT1, :upper16:_var$non_lazy_ptr | |||
2814 | /// ldr r0, [rT1] | |||
2815 | /// ldr rT2, [r0] | |||
2816 | /// blx rT2 | |||
2817 | /// [...address now in r0...] | |||
2818 | SDValue | |||
2819 | ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op, | |||
2820 | SelectionDAG &DAG) const { | |||
2821 | assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2822, __PRETTY_FUNCTION__)) | |||
2822 | "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2822, __PRETTY_FUNCTION__)); | |||
2823 | SDLoc DL(Op); | |||
2824 | ||||
2825 | // First step is to get the address of the actua global symbol. This is where | |||
2826 | // the TLS descriptor lives. | |||
2827 | SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG); | |||
2828 | ||||
2829 | // The first entry in the descriptor is a function pointer that we must call | |||
2830 | // to obtain the address of the variable. | |||
2831 | SDValue Chain = DAG.getEntryNode(); | |||
2832 | SDValue FuncTLVGet = DAG.getLoad( | |||
2833 | MVT::i32, DL, Chain, DescAddr, | |||
2834 | MachinePointerInfo::getGOT(DAG.getMachineFunction()), | |||
2835 | /* Alignment = */ 4, | |||
2836 | MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable | | |||
2837 | MachineMemOperand::MOInvariant); | |||
2838 | Chain = FuncTLVGet.getValue(1); | |||
2839 | ||||
2840 | MachineFunction &F = DAG.getMachineFunction(); | |||
2841 | MachineFrameInfo &MFI = F.getFrameInfo(); | |||
2842 | MFI.setAdjustsStack(true); | |||
2843 | ||||
2844 | // TLS calls preserve all registers except those that absolutely must be | |||
2845 | // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be | |||
2846 | // silly). | |||
2847 | auto TRI = | |||
2848 | getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo(); | |||
2849 | auto ARI = static_cast<const ARMRegisterInfo *>(TRI); | |||
2850 | const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction()); | |||
2851 | ||||
2852 | // Finally, we can make the call. This is just a degenerate version of a | |||
2853 | // normal AArch64 call node: r0 takes the address of the descriptor, and | |||
2854 | // returns the address of the variable in this thread. | |||
2855 | Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue()); | |||
2856 | Chain = | |||
2857 | DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), | |||
2858 | Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32), | |||
2859 | DAG.getRegisterMask(Mask), Chain.getValue(1)); | |||
2860 | return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1)); | |||
2861 | } | |||
2862 | ||||
2863 | SDValue | |||
2864 | ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op, | |||
2865 | SelectionDAG &DAG) const { | |||
2866 | assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2866, __PRETTY_FUNCTION__)); | |||
2867 | ||||
2868 | SDValue Chain = DAG.getEntryNode(); | |||
2869 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
2870 | SDLoc DL(Op); | |||
2871 | ||||
2872 | // Load the current TEB (thread environment block) | |||
2873 | SDValue Ops[] = {Chain, | |||
2874 | DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32), | |||
2875 | DAG.getConstant(15, DL, MVT::i32), | |||
2876 | DAG.getConstant(0, DL, MVT::i32), | |||
2877 | DAG.getConstant(13, DL, MVT::i32), | |||
2878 | DAG.getConstant(0, DL, MVT::i32), | |||
2879 | DAG.getConstant(2, DL, MVT::i32)}; | |||
2880 | SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, | |||
2881 | DAG.getVTList(MVT::i32, MVT::Other), Ops); | |||
2882 | ||||
2883 | SDValue TEB = CurrentTEB.getValue(0); | |||
2884 | Chain = CurrentTEB.getValue(1); | |||
2885 | ||||
2886 | // Load the ThreadLocalStoragePointer from the TEB | |||
2887 | // A pointer to the TLS array is located at offset 0x2c from the TEB. | |||
2888 | SDValue TLSArray = | |||
2889 | DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL)); | |||
2890 | TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo()); | |||
2891 | ||||
2892 | // The pointer to the thread's TLS data area is at the TLS Index scaled by 4 | |||
2893 | // offset into the TLSArray. | |||
2894 | ||||
2895 | // Load the TLS index from the C runtime | |||
2896 | SDValue TLSIndex = | |||
2897 | DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG); | |||
2898 | TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex); | |||
2899 | TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo()); | |||
2900 | ||||
2901 | SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex, | |||
2902 | DAG.getConstant(2, DL, MVT::i32)); | |||
2903 | SDValue TLS = DAG.getLoad(PtrVT, DL, Chain, | |||
2904 | DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot), | |||
2905 | MachinePointerInfo()); | |||
2906 | ||||
2907 | // Get the offset of the start of the .tls section (section base) | |||
2908 | const auto *GA = cast<GlobalAddressSDNode>(Op); | |||
2909 | auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL); | |||
2910 | SDValue Offset = DAG.getLoad( | |||
2911 | PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32, | |||
2912 | DAG.getTargetConstantPool(CPV, PtrVT, 4)), | |||
2913 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2914 | ||||
2915 | return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset); | |||
2916 | } | |||
2917 | ||||
2918 | // Lower ISD::GlobalTLSAddress using the "general dynamic" model | |||
2919 | SDValue | |||
2920 | ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, | |||
2921 | SelectionDAG &DAG) const { | |||
2922 | SDLoc dl(GA); | |||
2923 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
2924 | unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; | |||
2925 | MachineFunction &MF = DAG.getMachineFunction(); | |||
2926 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
2927 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2928 | ARMConstantPoolValue *CPV = | |||
2929 | ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, | |||
2930 | ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); | |||
2931 | SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
2932 | Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); | |||
2933 | Argument = DAG.getLoad( | |||
2934 | PtrVT, dl, DAG.getEntryNode(), Argument, | |||
2935 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2936 | SDValue Chain = Argument.getValue(1); | |||
2937 | ||||
2938 | SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); | |||
2939 | Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); | |||
2940 | ||||
2941 | // call __tls_get_addr. | |||
2942 | ArgListTy Args; | |||
2943 | ArgListEntry Entry; | |||
2944 | Entry.Node = Argument; | |||
2945 | Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); | |||
2946 | Args.push_back(Entry); | |||
2947 | ||||
2948 | // FIXME: is there useful debug info available here? | |||
2949 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
2950 | CLI.setDebugLoc(dl).setChain(Chain).setLibCallee( | |||
2951 | CallingConv::C, Type::getInt32Ty(*DAG.getContext()), | |||
2952 | DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args)); | |||
2953 | ||||
2954 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); | |||
2955 | return CallResult.first; | |||
2956 | } | |||
2957 | ||||
2958 | // Lower ISD::GlobalTLSAddress using the "initial exec" or | |||
2959 | // "local exec" model. | |||
2960 | SDValue | |||
2961 | ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, | |||
2962 | SelectionDAG &DAG, | |||
2963 | TLSModel::Model model) const { | |||
2964 | const GlobalValue *GV = GA->getGlobal(); | |||
2965 | SDLoc dl(GA); | |||
2966 | SDValue Offset; | |||
2967 | SDValue Chain = DAG.getEntryNode(); | |||
2968 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
2969 | // Get the Thread Pointer | |||
2970 | SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); | |||
2971 | ||||
2972 | if (model == TLSModel::InitialExec) { | |||
2973 | MachineFunction &MF = DAG.getMachineFunction(); | |||
2974 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
2975 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
2976 | // Initial exec model. | |||
2977 | unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; | |||
2978 | ARMConstantPoolValue *CPV = | |||
2979 | ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, | |||
2980 | ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, | |||
2981 | true); | |||
2982 | Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
2983 | Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); | |||
2984 | Offset = DAG.getLoad( | |||
2985 | PtrVT, dl, Chain, Offset, | |||
2986 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2987 | Chain = Offset.getValue(1); | |||
2988 | ||||
2989 | SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); | |||
2990 | Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); | |||
2991 | ||||
2992 | Offset = DAG.getLoad( | |||
2993 | PtrVT, dl, Chain, Offset, | |||
2994 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
2995 | } else { | |||
2996 | // local exec model | |||
2997 | assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 2997, __PRETTY_FUNCTION__)); | |||
2998 | ARMConstantPoolValue *CPV = | |||
2999 | ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); | |||
3000 | Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
3001 | Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); | |||
3002 | Offset = DAG.getLoad( | |||
3003 | PtrVT, dl, Chain, Offset, | |||
3004 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
3005 | } | |||
3006 | ||||
3007 | // The address of the thread local variable is the add of the thread | |||
3008 | // pointer with the offset of the variable. | |||
3009 | return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); | |||
3010 | } | |||
3011 | ||||
3012 | SDValue | |||
3013 | ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { | |||
3014 | GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); | |||
3015 | if (DAG.getTarget().useEmulatedTLS()) | |||
3016 | return LowerToTLSEmulatedModel(GA, DAG); | |||
3017 | ||||
3018 | if (Subtarget->isTargetDarwin()) | |||
3019 | return LowerGlobalTLSAddressDarwin(Op, DAG); | |||
3020 | ||||
3021 | if (Subtarget->isTargetWindows()) | |||
3022 | return LowerGlobalTLSAddressWindows(Op, DAG); | |||
3023 | ||||
3024 | // TODO: implement the "local dynamic" model | |||
3025 | assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3025, __PRETTY_FUNCTION__)); | |||
3026 | TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal()); | |||
3027 | ||||
3028 | switch (model) { | |||
3029 | case TLSModel::GeneralDynamic: | |||
3030 | case TLSModel::LocalDynamic: | |||
3031 | return LowerToTLSGeneralDynamicModel(GA, DAG); | |||
3032 | case TLSModel::InitialExec: | |||
3033 | case TLSModel::LocalExec: | |||
3034 | return LowerToTLSExecModels(GA, DAG, model); | |||
3035 | } | |||
3036 | llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3036); | |||
3037 | } | |||
3038 | ||||
3039 | /// Return true if all users of V are within function F, looking through | |||
3040 | /// ConstantExprs. | |||
3041 | static bool allUsersAreInFunction(const Value *V, const Function *F) { | |||
3042 | SmallVector<const User*,4> Worklist; | |||
3043 | for (auto *U : V->users()) | |||
3044 | Worklist.push_back(U); | |||
3045 | while (!Worklist.empty()) { | |||
3046 | auto *U = Worklist.pop_back_val(); | |||
3047 | if (isa<ConstantExpr>(U)) { | |||
3048 | for (auto *UU : U->users()) | |||
3049 | Worklist.push_back(UU); | |||
3050 | continue; | |||
3051 | } | |||
3052 | ||||
3053 | auto *I = dyn_cast<Instruction>(U); | |||
3054 | if (!I || I->getParent()->getParent() != F) | |||
3055 | return false; | |||
3056 | } | |||
3057 | return true; | |||
3058 | } | |||
3059 | ||||
3060 | static SDValue promoteToConstantPool(const ARMTargetLowering *TLI, | |||
3061 | const GlobalValue *GV, SelectionDAG &DAG, | |||
3062 | EVT PtrVT, const SDLoc &dl) { | |||
3063 | // If we're creating a pool entry for a constant global with unnamed address, | |||
3064 | // and the global is small enough, we can emit it inline into the constant pool | |||
3065 | // to save ourselves an indirection. | |||
3066 | // | |||
3067 | // This is a win if the constant is only used in one function (so it doesn't | |||
3068 | // need to be duplicated) or duplicating the constant wouldn't increase code | |||
3069 | // size (implying the constant is no larger than 4 bytes). | |||
3070 | const Function &F = DAG.getMachineFunction().getFunction(); | |||
3071 | ||||
3072 | // We rely on this decision to inline being idemopotent and unrelated to the | |||
3073 | // use-site. We know that if we inline a variable at one use site, we'll | |||
3074 | // inline it elsewhere too (and reuse the constant pool entry). Fast-isel | |||
3075 | // doesn't know about this optimization, so bail out if it's enabled else | |||
3076 | // we could decide to inline here (and thus never emit the GV) but require | |||
3077 | // the GV from fast-isel generated code. | |||
3078 | if (!EnableConstpoolPromotion || | |||
3079 | DAG.getMachineFunction().getTarget().Options.EnableFastISel) | |||
3080 | return SDValue(); | |||
3081 | ||||
3082 | auto *GVar = dyn_cast<GlobalVariable>(GV); | |||
3083 | if (!GVar || !GVar->hasInitializer() || | |||
3084 | !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() || | |||
3085 | !GVar->hasLocalLinkage()) | |||
3086 | return SDValue(); | |||
3087 | ||||
3088 | // If we inline a value that contains relocations, we move the relocations | |||
3089 | // from .data to .text. This is not allowed in position-independent code. | |||
3090 | auto *Init = GVar->getInitializer(); | |||
3091 | if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) && | |||
3092 | Init->needsRelocation()) | |||
3093 | return SDValue(); | |||
3094 | ||||
3095 | // The constant islands pass can only really deal with alignment requests | |||
3096 | // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote | |||
3097 | // any type wanting greater alignment requirements than 4 bytes. We also | |||
3098 | // can only promote constants that are multiples of 4 bytes in size or | |||
3099 | // are paddable to a multiple of 4. Currently we only try and pad constants | |||
3100 | // that are strings for simplicity. | |||
3101 | auto *CDAInit = dyn_cast<ConstantDataArray>(Init); | |||
3102 | unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType()); | |||
3103 | unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar); | |||
3104 | unsigned RequiredPadding = 4 - (Size % 4); | |||
3105 | bool PaddingPossible = | |||
3106 | RequiredPadding == 4 || (CDAInit && CDAInit->isString()); | |||
3107 | if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize || | |||
3108 | Size == 0) | |||
3109 | return SDValue(); | |||
3110 | ||||
3111 | unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding); | |||
3112 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3113 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3114 | ||||
3115 | // We can't bloat the constant pool too much, else the ConstantIslands pass | |||
3116 | // may fail to converge. If we haven't promoted this global yet (it may have | |||
3117 | // multiple uses), and promoting it would increase the constant pool size (Sz | |||
3118 | // > 4), ensure we have space to do so up to MaxTotal. | |||
3119 | if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4) | |||
3120 | if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >= | |||
3121 | ConstpoolPromotionMaxTotal) | |||
3122 | return SDValue(); | |||
3123 | ||||
3124 | // This is only valid if all users are in a single function; we can't clone | |||
3125 | // the constant in general. The LLVM IR unnamed_addr allows merging | |||
3126 | // constants, but not cloning them. | |||
3127 | // | |||
3128 | // We could potentially allow cloning if we could prove all uses of the | |||
3129 | // constant in the current function don't care about the address, like | |||
3130 | // printf format strings. But that isn't implemented for now. | |||
3131 | if (!allUsersAreInFunction(GVar, &F)) | |||
3132 | return SDValue(); | |||
3133 | ||||
3134 | // We're going to inline this global. Pad it out if needed. | |||
3135 | if (RequiredPadding != 4) { | |||
3136 | StringRef S = CDAInit->getAsString(); | |||
3137 | ||||
3138 | SmallVector<uint8_t,16> V(S.size()); | |||
3139 | std::copy(S.bytes_begin(), S.bytes_end(), V.begin()); | |||
3140 | while (RequiredPadding--) | |||
3141 | V.push_back(0); | |||
3142 | Init = ConstantDataArray::get(*DAG.getContext(), V); | |||
3143 | } | |||
3144 | ||||
3145 | auto CPVal = ARMConstantPoolConstant::Create(GVar, Init); | |||
3146 | SDValue CPAddr = | |||
3147 | DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4); | |||
3148 | if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) { | |||
3149 | AFI->markGlobalAsPromotedToConstantPool(GVar); | |||
3150 | AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() + | |||
3151 | PaddedSize - 4); | |||
3152 | } | |||
3153 | ++NumConstpoolPromoted; | |||
3154 | return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
3155 | } | |||
3156 | ||||
3157 | bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const { | |||
3158 | if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) | |||
3159 | if (!(GV = GA->getBaseObject())) | |||
3160 | return false; | |||
3161 | if (const auto *V = dyn_cast<GlobalVariable>(GV)) | |||
3162 | return V->isConstant(); | |||
3163 | return isa<Function>(GV); | |||
3164 | } | |||
3165 | ||||
3166 | SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op, | |||
3167 | SelectionDAG &DAG) const { | |||
3168 | switch (Subtarget->getTargetTriple().getObjectFormat()) { | |||
3169 | default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3169); | |||
3170 | case Triple::COFF: | |||
3171 | return LowerGlobalAddressWindows(Op, DAG); | |||
3172 | case Triple::ELF: | |||
3173 | return LowerGlobalAddressELF(Op, DAG); | |||
3174 | case Triple::MachO: | |||
3175 | return LowerGlobalAddressDarwin(Op, DAG); | |||
3176 | } | |||
3177 | } | |||
3178 | ||||
3179 | SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, | |||
3180 | SelectionDAG &DAG) const { | |||
3181 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3182 | SDLoc dl(Op); | |||
3183 | const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); | |||
3184 | const TargetMachine &TM = getTargetMachine(); | |||
3185 | bool IsRO = isReadOnly(GV); | |||
3186 | ||||
3187 | // promoteToConstantPool only if not generating XO text section | |||
3188 | if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly()) | |||
3189 | if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl)) | |||
3190 | return V; | |||
3191 | ||||
3192 | if (isPositionIndependent()) { | |||
3193 | bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV); | |||
3194 | SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, | |||
3195 | UseGOT_PREL ? ARMII::MO_GOT : 0); | |||
3196 | SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G); | |||
3197 | if (UseGOT_PREL) | |||
3198 | Result = | |||
3199 | DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, | |||
3200 | MachinePointerInfo::getGOT(DAG.getMachineFunction())); | |||
3201 | return Result; | |||
3202 | } else if (Subtarget->isROPI() && IsRO) { | |||
3203 | // PC-relative. | |||
3204 | SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT); | |||
3205 | SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G); | |||
3206 | return Result; | |||
3207 | } else if (Subtarget->isRWPI() && !IsRO) { | |||
3208 | // SB-relative. | |||
3209 | SDValue RelAddr; | |||
3210 | if (Subtarget->useMovt()) { | |||
3211 | ++NumMovwMovt; | |||
3212 | SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL); | |||
3213 | RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G); | |||
3214 | } else { // use literal pool for address constant | |||
3215 | ARMConstantPoolValue *CPV = | |||
3216 | ARMConstantPoolConstant::Create(GV, ARMCP::SBREL); | |||
3217 | SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
3218 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
3219 | RelAddr = DAG.getLoad( | |||
3220 | PtrVT, dl, DAG.getEntryNode(), CPAddr, | |||
3221 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
3222 | } | |||
3223 | SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT); | |||
3224 | SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr); | |||
3225 | return Result; | |||
3226 | } | |||
3227 | ||||
3228 | // If we have T2 ops, we can materialize the address directly via movt/movw | |||
3229 | // pair. This is always cheaper. | |||
3230 | if (Subtarget->useMovt()) { | |||
3231 | ++NumMovwMovt; | |||
3232 | // FIXME: Once remat is capable of dealing with instructions with register | |||
3233 | // operands, expand this into two nodes. | |||
3234 | return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, | |||
3235 | DAG.getTargetGlobalAddress(GV, dl, PtrVT)); | |||
3236 | } else { | |||
3237 | SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); | |||
3238 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
3239 | return DAG.getLoad( | |||
3240 | PtrVT, dl, DAG.getEntryNode(), CPAddr, | |||
3241 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
3242 | } | |||
3243 | } | |||
3244 | ||||
3245 | SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, | |||
3246 | SelectionDAG &DAG) const { | |||
3247 | assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3248, __PRETTY_FUNCTION__)) | |||
3248 | "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3248, __PRETTY_FUNCTION__)); | |||
3249 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3250 | SDLoc dl(Op); | |||
3251 | const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); | |||
3252 | ||||
3253 | if (Subtarget->useMovt()) | |||
3254 | ++NumMovwMovt; | |||
3255 | ||||
3256 | // FIXME: Once remat is capable of dealing with instructions with register | |||
3257 | // operands, expand this into multiple nodes | |||
3258 | unsigned Wrapper = | |||
3259 | isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper; | |||
3260 | ||||
3261 | SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY); | |||
3262 | SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G); | |||
3263 | ||||
3264 | if (Subtarget->isGVIndirectSymbol(GV)) | |||
3265 | Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, | |||
3266 | MachinePointerInfo::getGOT(DAG.getMachineFunction())); | |||
3267 | return Result; | |||
3268 | } | |||
3269 | ||||
3270 | SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op, | |||
3271 | SelectionDAG &DAG) const { | |||
3272 | assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3272, __PRETTY_FUNCTION__)); | |||
3273 | assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3274, __PRETTY_FUNCTION__)) | |||
3274 | "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3274, __PRETTY_FUNCTION__)); | |||
3275 | assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3276, __PRETTY_FUNCTION__)) | |||
3276 | "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3276, __PRETTY_FUNCTION__)); | |||
3277 | ||||
3278 | const TargetMachine &TM = getTargetMachine(); | |||
3279 | const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); | |||
3280 | ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG; | |||
3281 | if (GV->hasDLLImportStorageClass()) | |||
3282 | TargetFlags = ARMII::MO_DLLIMPORT; | |||
3283 | else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) | |||
3284 | TargetFlags = ARMII::MO_COFFSTUB; | |||
3285 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3286 | SDValue Result; | |||
3287 | SDLoc DL(Op); | |||
3288 | ||||
3289 | ++NumMovwMovt; | |||
3290 | ||||
3291 | // FIXME: Once remat is capable of dealing with instructions with register | |||
3292 | // operands, expand this into two nodes. | |||
3293 | Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, | |||
3294 | DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0, | |||
3295 | TargetFlags)); | |||
3296 | if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB)) | |||
3297 | Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, | |||
3298 | MachinePointerInfo::getGOT(DAG.getMachineFunction())); | |||
3299 | return Result; | |||
3300 | } | |||
3301 | ||||
3302 | SDValue | |||
3303 | ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { | |||
3304 | SDLoc dl(Op); | |||
3305 | SDValue Val = DAG.getConstant(0, dl, MVT::i32); | |||
3306 | return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, | |||
3307 | DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), | |||
3308 | Op.getOperand(1), Val); | |||
3309 | } | |||
3310 | ||||
3311 | SDValue | |||
3312 | ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { | |||
3313 | SDLoc dl(Op); | |||
3314 | return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), | |||
3315 | Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); | |||
3316 | } | |||
3317 | ||||
3318 | SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, | |||
3319 | SelectionDAG &DAG) const { | |||
3320 | SDLoc dl(Op); | |||
3321 | return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other, | |||
3322 | Op.getOperand(0)); | |||
3323 | } | |||
3324 | ||||
3325 | SDValue | |||
3326 | ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, | |||
3327 | const ARMSubtarget *Subtarget) const { | |||
3328 | unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); | |||
3329 | SDLoc dl(Op); | |||
3330 | switch (IntNo) { | |||
3331 | default: return SDValue(); // Don't custom lower most intrinsics. | |||
3332 | case Intrinsic::thread_pointer: { | |||
3333 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3334 | return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); | |||
3335 | } | |||
3336 | case Intrinsic::eh_sjlj_lsda: { | |||
3337 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3338 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3339 | unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); | |||
3340 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3341 | SDValue CPAddr; | |||
3342 | bool IsPositionIndependent = isPositionIndependent(); | |||
3343 | unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0; | |||
3344 | ARMConstantPoolValue *CPV = | |||
3345 | ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex, | |||
3346 | ARMCP::CPLSDA, PCAdj); | |||
3347 | CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); | |||
3348 | CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); | |||
3349 | SDValue Result = DAG.getLoad( | |||
3350 | PtrVT, dl, DAG.getEntryNode(), CPAddr, | |||
3351 | MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); | |||
3352 | ||||
3353 | if (IsPositionIndependent) { | |||
3354 | SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); | |||
3355 | Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); | |||
3356 | } | |||
3357 | return Result; | |||
3358 | } | |||
3359 | case Intrinsic::arm_neon_vabs: | |||
3360 | return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(), | |||
3361 | Op.getOperand(1)); | |||
3362 | case Intrinsic::arm_neon_vmulls: | |||
3363 | case Intrinsic::arm_neon_vmullu: { | |||
3364 | unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) | |||
3365 | ? ARMISD::VMULLs : ARMISD::VMULLu; | |||
3366 | return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), | |||
3367 | Op.getOperand(1), Op.getOperand(2)); | |||
3368 | } | |||
3369 | case Intrinsic::arm_neon_vminnm: | |||
3370 | case Intrinsic::arm_neon_vmaxnm: { | |||
3371 | unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm) | |||
3372 | ? ISD::FMINNUM : ISD::FMAXNUM; | |||
3373 | return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), | |||
3374 | Op.getOperand(1), Op.getOperand(2)); | |||
3375 | } | |||
3376 | case Intrinsic::arm_neon_vminu: | |||
3377 | case Intrinsic::arm_neon_vmaxu: { | |||
3378 | if (Op.getValueType().isFloatingPoint()) | |||
3379 | return SDValue(); | |||
3380 | unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu) | |||
3381 | ? ISD::UMIN : ISD::UMAX; | |||
3382 | return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), | |||
3383 | Op.getOperand(1), Op.getOperand(2)); | |||
3384 | } | |||
3385 | case Intrinsic::arm_neon_vmins: | |||
3386 | case Intrinsic::arm_neon_vmaxs: { | |||
3387 | // v{min,max}s is overloaded between signed integers and floats. | |||
3388 | if (!Op.getValueType().isFloatingPoint()) { | |||
3389 | unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) | |||
3390 | ? ISD::SMIN : ISD::SMAX; | |||
3391 | return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), | |||
3392 | Op.getOperand(1), Op.getOperand(2)); | |||
3393 | } | |||
3394 | unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) | |||
3395 | ? ISD::FMINIMUM : ISD::FMAXIMUM; | |||
3396 | return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), | |||
3397 | Op.getOperand(1), Op.getOperand(2)); | |||
3398 | } | |||
3399 | case Intrinsic::arm_neon_vtbl1: | |||
3400 | return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(), | |||
3401 | Op.getOperand(1), Op.getOperand(2)); | |||
3402 | case Intrinsic::arm_neon_vtbl2: | |||
3403 | return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(), | |||
3404 | Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); | |||
3405 | } | |||
3406 | } | |||
3407 | ||||
3408 | static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, | |||
3409 | const ARMSubtarget *Subtarget) { | |||
3410 | SDLoc dl(Op); | |||
3411 | ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2)); | |||
3412 | auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue()); | |||
3413 | if (SSID == SyncScope::SingleThread) | |||
3414 | return Op; | |||
3415 | ||||
3416 | if (!Subtarget->hasDataBarrier()) { | |||
3417 | // Some ARMv6 cpus can support data barriers with an mcr instruction. | |||
3418 | // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get | |||
3419 | // here. | |||
3420 | assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb( ) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3421, __PRETTY_FUNCTION__)) | |||
3421 | "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb( ) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3421, __PRETTY_FUNCTION__)); | |||
3422 | return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), | |||
3423 | DAG.getConstant(0, dl, MVT::i32)); | |||
3424 | } | |||
3425 | ||||
3426 | ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1)); | |||
3427 | AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); | |||
3428 | ARM_MB::MemBOpt Domain = ARM_MB::ISH; | |||
3429 | if (Subtarget->isMClass()) { | |||
3430 | // Only a full system barrier exists in the M-class architectures. | |||
3431 | Domain = ARM_MB::SY; | |||
3432 | } else if (Subtarget->preferISHSTBarriers() && | |||
3433 | Ord == AtomicOrdering::Release) { | |||
3434 | // Swift happens to implement ISHST barriers in a way that's compatible with | |||
3435 | // Release semantics but weaker than ISH so we'd be fools not to use | |||
3436 | // it. Beware: other processors probably don't! | |||
3437 | Domain = ARM_MB::ISHST; | |||
3438 | } | |||
3439 | ||||
3440 | return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0), | |||
3441 | DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32), | |||
3442 | DAG.getConstant(Domain, dl, MVT::i32)); | |||
3443 | } | |||
3444 | ||||
3445 | static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, | |||
3446 | const ARMSubtarget *Subtarget) { | |||
3447 | // ARM pre v5TE and Thumb1 does not have preload instructions. | |||
3448 | if (!(Subtarget->isThumb2() || | |||
3449 | (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) | |||
3450 | // Just preserve the chain. | |||
3451 | return Op.getOperand(0); | |||
3452 | ||||
3453 | SDLoc dl(Op); | |||
3454 | unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; | |||
3455 | if (!isRead && | |||
3456 | (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) | |||
3457 | // ARMv7 with MP extension has PLDW. | |||
3458 | return Op.getOperand(0); | |||
3459 | ||||
3460 | unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); | |||
3461 | if (Subtarget->isThumb()) { | |||
3462 | // Invert the bits. | |||
3463 | isRead = ~isRead & 1; | |||
3464 | isData = ~isData & 1; | |||
3465 | } | |||
3466 | ||||
3467 | return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), | |||
3468 | Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32), | |||
3469 | DAG.getConstant(isData, dl, MVT::i32)); | |||
3470 | } | |||
3471 | ||||
3472 | static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { | |||
3473 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3474 | ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); | |||
3475 | ||||
3476 | // vastart just stores the address of the VarArgsFrameIndex slot into the | |||
3477 | // memory location argument. | |||
3478 | SDLoc dl(Op); | |||
3479 | EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); | |||
3480 | SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); | |||
3481 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); | |||
3482 | return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), | |||
3483 | MachinePointerInfo(SV)); | |||
3484 | } | |||
3485 | ||||
3486 | SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, | |||
3487 | CCValAssign &NextVA, | |||
3488 | SDValue &Root, | |||
3489 | SelectionDAG &DAG, | |||
3490 | const SDLoc &dl) const { | |||
3491 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3492 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3493 | ||||
3494 | const TargetRegisterClass *RC; | |||
3495 | if (AFI->isThumb1OnlyFunction()) | |||
3496 | RC = &ARM::tGPRRegClass; | |||
3497 | else | |||
3498 | RC = &ARM::GPRRegClass; | |||
3499 | ||||
3500 | // Transform the arguments stored in physical registers into virtual ones. | |||
3501 | unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); | |||
3502 | SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); | |||
3503 | ||||
3504 | SDValue ArgValue2; | |||
3505 | if (NextVA.isMemLoc()) { | |||
3506 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
3507 | int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true); | |||
3508 | ||||
3509 | // Create load node to retrieve arguments from the stack. | |||
3510 | SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); | |||
3511 | ArgValue2 = DAG.getLoad( | |||
3512 | MVT::i32, dl, Root, FIN, | |||
3513 | MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); | |||
3514 | } else { | |||
3515 | Reg = MF.addLiveIn(NextVA.getLocReg(), RC); | |||
3516 | ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); | |||
3517 | } | |||
3518 | if (!Subtarget->isLittle()) | |||
3519 | std::swap (ArgValue, ArgValue2); | |||
3520 | return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); | |||
3521 | } | |||
3522 | ||||
3523 | // The remaining GPRs hold either the beginning of variable-argument | |||
3524 | // data, or the beginning of an aggregate passed by value (usually | |||
3525 | // byval). Either way, we allocate stack slots adjacent to the data | |||
3526 | // provided by our caller, and store the unallocated registers there. | |||
3527 | // If this is a variadic function, the va_list pointer will begin with | |||
3528 | // these values; otherwise, this reassembles a (byval) structure that | |||
3529 | // was split between registers and memory. | |||
3530 | // Return: The frame index registers were stored into. | |||
3531 | int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, | |||
3532 | const SDLoc &dl, SDValue &Chain, | |||
3533 | const Value *OrigArg, | |||
3534 | unsigned InRegsParamRecordIdx, | |||
3535 | int ArgOffset, unsigned ArgSize) const { | |||
3536 | // Currently, two use-cases possible: | |||
3537 | // Case #1. Non-var-args function, and we meet first byval parameter. | |||
3538 | // Setup first unallocated register as first byval register; | |||
3539 | // eat all remained registers | |||
3540 | // (these two actions are performed by HandleByVal method). | |||
3541 | // Then, here, we initialize stack frame with | |||
3542 | // "store-reg" instructions. | |||
3543 | // Case #2. Var-args function, that doesn't contain byval parameters. | |||
3544 | // The same: eat all remained unallocated registers, | |||
3545 | // initialize stack frame. | |||
3546 | ||||
3547 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3548 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
3549 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3550 | unsigned RBegin, REnd; | |||
3551 | if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) { | |||
3552 | CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd); | |||
3553 | } else { | |||
3554 | unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs); | |||
3555 | RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx]; | |||
3556 | REnd = ARM::R4; | |||
3557 | } | |||
3558 | ||||
3559 | if (REnd != RBegin) | |||
3560 | ArgOffset = -4 * (ARM::R4 - RBegin); | |||
3561 | ||||
3562 | auto PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3563 | int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false); | |||
3564 | SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT); | |||
3565 | ||||
3566 | SmallVector<SDValue, 4> MemOps; | |||
3567 | const TargetRegisterClass *RC = | |||
3568 | AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass; | |||
3569 | ||||
3570 | for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) { | |||
3571 | unsigned VReg = MF.addLiveIn(Reg, RC); | |||
3572 | SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); | |||
3573 | SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, | |||
3574 | MachinePointerInfo(OrigArg, 4 * i)); | |||
3575 | MemOps.push_back(Store); | |||
3576 | FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT)); | |||
3577 | } | |||
3578 | ||||
3579 | if (!MemOps.empty()) | |||
3580 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); | |||
3581 | return FrameIndex; | |||
3582 | } | |||
3583 | ||||
3584 | // Setup stack frame, the va_list pointer will start from. | |||
3585 | void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, | |||
3586 | const SDLoc &dl, SDValue &Chain, | |||
3587 | unsigned ArgOffset, | |||
3588 | unsigned TotalArgRegsSaveSize, | |||
3589 | bool ForceMutable) const { | |||
3590 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3591 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3592 | ||||
3593 | // Try to store any remaining integer argument regs | |||
3594 | // to their spots on the stack so that they may be loaded by dereferencing | |||
3595 | // the result of va_next. | |||
3596 | // If there is no regs to be stored, just point address after last | |||
3597 | // argument passed via stack. | |||
3598 | int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr, | |||
3599 | CCInfo.getInRegsParamsCount(), | |||
3600 | CCInfo.getNextStackOffset(), 4); | |||
3601 | AFI->setVarArgsFrameIndex(FrameIndex); | |||
3602 | } | |||
3603 | ||||
3604 | SDValue ARMTargetLowering::LowerFormalArguments( | |||
3605 | SDValue Chain, CallingConv::ID CallConv, bool isVarArg, | |||
3606 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, | |||
3607 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { | |||
3608 | MachineFunction &MF = DAG.getMachineFunction(); | |||
3609 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
3610 | ||||
3611 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |||
3612 | ||||
3613 | // Assign locations to all of the incoming arguments. | |||
3614 | SmallVector<CCValAssign, 16> ArgLocs; | |||
3615 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, | |||
3616 | *DAG.getContext()); | |||
3617 | CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg)); | |||
3618 | ||||
3619 | SmallVector<SDValue, 16> ArgValues; | |||
3620 | SDValue ArgValue; | |||
3621 | Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin(); | |||
3622 | unsigned CurArgIdx = 0; | |||
3623 | ||||
3624 | // Initially ArgRegsSaveSize is zero. | |||
3625 | // Then we increase this value each time we meet byval parameter. | |||
3626 | // We also increase this value in case of varargs function. | |||
3627 | AFI->setArgRegsSaveSize(0); | |||
3628 | ||||
3629 | // Calculate the amount of stack space that we need to allocate to store | |||
3630 | // byval and variadic arguments that are passed in registers. | |||
3631 | // We need to know this before we allocate the first byval or variadic | |||
3632 | // argument, as they will be allocated a stack slot below the CFA (Canonical | |||
3633 | // Frame Address, the stack pointer at entry to the function). | |||
3634 | unsigned ArgRegBegin = ARM::R4; | |||
3635 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |||
3636 | if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount()) | |||
3637 | break; | |||
3638 | ||||
3639 | CCValAssign &VA = ArgLocs[i]; | |||
3640 | unsigned Index = VA.getValNo(); | |||
3641 | ISD::ArgFlagsTy Flags = Ins[Index].Flags; | |||
3642 | if (!Flags.isByVal()) | |||
3643 | continue; | |||
3644 | ||||
3645 | assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg") ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3645, __PRETTY_FUNCTION__)); | |||
3646 | unsigned RBegin, REnd; | |||
3647 | CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd); | |||
3648 | ArgRegBegin = std::min(ArgRegBegin, RBegin); | |||
3649 | ||||
3650 | CCInfo.nextInRegsParam(); | |||
3651 | } | |||
3652 | CCInfo.rewindByValRegsInfo(); | |||
3653 | ||||
3654 | int lastInsIndex = -1; | |||
3655 | if (isVarArg && MFI.hasVAStart()) { | |||
3656 | unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); | |||
3657 | if (RegIdx != array_lengthof(GPRArgRegs)) | |||
3658 | ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); | |||
3659 | } | |||
3660 | ||||
3661 | unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin); | |||
3662 | AFI->setArgRegsSaveSize(TotalArgRegsSaveSize); | |||
3663 | auto PtrVT = getPointerTy(DAG.getDataLayout()); | |||
3664 | ||||
3665 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |||
3666 | CCValAssign &VA = ArgLocs[i]; | |||
3667 | if (Ins[VA.getValNo()].isOrigArg()) { | |||
3668 | std::advance(CurOrigArg, | |||
3669 | Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx); | |||
3670 | CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex(); | |||
3671 | } | |||
3672 | // Arguments stored in registers. | |||
3673 | if (VA.isRegLoc()) { | |||
3674 | EVT RegVT = VA.getLocVT(); | |||
3675 | ||||
3676 | if (VA.needsCustom()) { | |||
3677 | // f64 and vector types are split up into multiple registers or | |||
3678 | // combinations of registers and stack slots. | |||
3679 | if (VA.getLocVT() == MVT::v2f64) { | |||
3680 | SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], | |||
3681 | Chain, DAG, dl); | |||
3682 | VA = ArgLocs[++i]; // skip ahead to next loc | |||
3683 | SDValue ArgValue2; | |||
3684 | if (VA.isMemLoc()) { | |||
3685 | int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true); | |||
3686 | SDValue FIN = DAG.getFrameIndex(FI, PtrVT); | |||
3687 | ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, | |||
3688 | MachinePointerInfo::getFixedStack( | |||
3689 | DAG.getMachineFunction(), FI)); | |||
3690 | } else { | |||
3691 | ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], | |||
3692 | Chain, DAG, dl); | |||
3693 | } | |||
3694 | ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); | |||
3695 | ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, | |||
3696 | ArgValue, ArgValue1, | |||
3697 | DAG.getIntPtrConstant(0, dl)); | |||
3698 | ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, | |||
3699 | ArgValue, ArgValue2, | |||
3700 | DAG.getIntPtrConstant(1, dl)); | |||
3701 | } else | |||
3702 | ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); | |||
3703 | } else { | |||
3704 | const TargetRegisterClass *RC; | |||
3705 | ||||
3706 | ||||
3707 | if (RegVT == MVT::f16) | |||
3708 | RC = &ARM::HPRRegClass; | |||
3709 | else if (RegVT == MVT::f32) | |||
3710 | RC = &ARM::SPRRegClass; | |||
3711 | else if (RegVT == MVT::f64 || RegVT == MVT::v4f16) | |||
3712 | RC = &ARM::DPRRegClass; | |||
3713 | else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16) | |||
3714 | RC = &ARM::QPRRegClass; | |||
3715 | else if (RegVT == MVT::i32) | |||
3716 | RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass | |||
3717 | : &ARM::GPRRegClass; | |||
3718 | else | |||
3719 | llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3719); | |||
3720 | ||||
3721 | // Transform the arguments in physical registers into virtual ones. | |||
3722 | unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); | |||
3723 | ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); | |||
3724 | } | |||
3725 | ||||
3726 | // If this is an 8 or 16-bit value, it is really passed promoted | |||
3727 | // to 32 bits. Insert an assert[sz]ext to capture this, then | |||
3728 | // truncate to the right size. | |||
3729 | switch (VA.getLocInfo()) { | |||
3730 | default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3730); | |||
3731 | case CCValAssign::Full: break; | |||
3732 | case CCValAssign::BCvt: | |||
3733 | ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); | |||
3734 | break; | |||
3735 | case CCValAssign::SExt: | |||
3736 | ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, | |||
3737 | DAG.getValueType(VA.getValVT())); | |||
3738 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); | |||
3739 | break; | |||
3740 | case CCValAssign::ZExt: | |||
3741 | ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, | |||
3742 | DAG.getValueType(VA.getValVT())); | |||
3743 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); | |||
3744 | break; | |||
3745 | } | |||
3746 | ||||
3747 | InVals.push_back(ArgValue); | |||
3748 | } else { // VA.isRegLoc() | |||
3749 | // sanity check | |||
3750 | assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3750, __PRETTY_FUNCTION__)); | |||
3751 | assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered" ) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3751, __PRETTY_FUNCTION__)); | |||
3752 | ||||
3753 | int index = VA.getValNo(); | |||
3754 | ||||
3755 | // Some Ins[] entries become multiple ArgLoc[] entries. | |||
3756 | // Process them only once. | |||
3757 | if (index != lastInsIndex) | |||
3758 | { | |||
3759 | ISD::ArgFlagsTy Flags = Ins[index].Flags; | |||
3760 | // FIXME: For now, all byval parameter objects are marked mutable. | |||
3761 | // This can be changed with more analysis. | |||
3762 | // In case of tail call optimization mark all arguments mutable. | |||
3763 | // Since they could be overwritten by lowering of arguments in case of | |||
3764 | // a tail call. | |||
3765 | if (Flags.isByVal()) { | |||
3766 | assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit" ) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3767, __PRETTY_FUNCTION__)) | |||
3767 | "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit" ) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3767, __PRETTY_FUNCTION__)); | |||
3768 | unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed(); | |||
3769 | ||||
3770 | int FrameIndex = StoreByValRegs( | |||
3771 | CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex, | |||
3772 | VA.getLocMemOffset(), Flags.getByValSize()); | |||
3773 | InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT)); | |||
3774 | CCInfo.nextInRegsParam(); | |||
3775 | } else { | |||
3776 | unsigned FIOffset = VA.getLocMemOffset(); | |||
3777 | int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8, | |||
3778 | FIOffset, true); | |||
3779 | ||||
3780 | // Create load nodes to retrieve arguments from the stack. | |||
3781 | SDValue FIN = DAG.getFrameIndex(FI, PtrVT); | |||
3782 | InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, | |||
3783 | MachinePointerInfo::getFixedStack( | |||
3784 | DAG.getMachineFunction(), FI))); | |||
3785 | } | |||
3786 | lastInsIndex = index; | |||
3787 | } | |||
3788 | } | |||
3789 | } | |||
3790 | ||||
3791 | // varargs | |||
3792 | if (isVarArg && MFI.hasVAStart()) | |||
3793 | VarArgStyleRegisters(CCInfo, DAG, dl, Chain, | |||
3794 | CCInfo.getNextStackOffset(), | |||
3795 | TotalArgRegsSaveSize); | |||
3796 | ||||
3797 | AFI->setArgumentStackSize(CCInfo.getNextStackOffset()); | |||
3798 | ||||
3799 | return Chain; | |||
3800 | } | |||
3801 | ||||
3802 | /// isFloatingPointZero - Return true if this is +0.0. | |||
3803 | static bool isFloatingPointZero(SDValue Op) { | |||
3804 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) | |||
3805 | return CFP->getValueAPF().isPosZero(); | |||
3806 | else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { | |||
3807 | // Maybe this has already been legalized into the constant pool? | |||
3808 | if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { | |||
3809 | SDValue WrapperOp = Op.getOperand(1).getOperand(0); | |||
3810 | if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) | |||
3811 | if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) | |||
3812 | return CFP->getValueAPF().isPosZero(); | |||
3813 | } | |||
3814 | } else if (Op->getOpcode() == ISD::BITCAST && | |||
3815 | Op->getValueType(0) == MVT::f64) { | |||
3816 | // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64) | |||
3817 | // created by LowerConstantFP(). | |||
3818 | SDValue BitcastOp = Op->getOperand(0); | |||
3819 | if (BitcastOp->getOpcode() == ARMISD::VMOVIMM && | |||
3820 | isNullConstant(BitcastOp->getOperand(0))) | |||
3821 | return true; | |||
3822 | } | |||
3823 | return false; | |||
3824 | } | |||
3825 | ||||
3826 | /// Returns appropriate ARM CMP (cmp) and corresponding condition code for | |||
3827 | /// the given operands. | |||
3828 | SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, | |||
3829 | SDValue &ARMcc, SelectionDAG &DAG, | |||
3830 | const SDLoc &dl) const { | |||
3831 | if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { | |||
3832 | unsigned C = RHSC->getZExtValue(); | |||
3833 | if (!isLegalICmpImmediate((int32_t)C)) { | |||
3834 | // Constant does not fit, try adjusting it by one. | |||
3835 | switch (CC) { | |||
3836 | default: break; | |||
3837 | case ISD::SETLT: | |||
3838 | case ISD::SETGE: | |||
3839 | if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { | |||
3840 | CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; | |||
3841 | RHS = DAG.getConstant(C - 1, dl, MVT::i32); | |||
3842 | } | |||
3843 | break; | |||
3844 | case ISD::SETULT: | |||
3845 | case ISD::SETUGE: | |||
3846 | if (C != 0 && isLegalICmpImmediate(C-1)) { | |||
3847 | CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; | |||
3848 | RHS = DAG.getConstant(C - 1, dl, MVT::i32); | |||
3849 | } | |||
3850 | break; | |||
3851 | case ISD::SETLE: | |||
3852 | case ISD::SETGT: | |||
3853 | if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { | |||
3854 | CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; | |||
3855 | RHS = DAG.getConstant(C + 1, dl, MVT::i32); | |||
3856 | } | |||
3857 | break; | |||
3858 | case ISD::SETULE: | |||
3859 | case ISD::SETUGT: | |||
3860 | if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { | |||
3861 | CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; | |||
3862 | RHS = DAG.getConstant(C + 1, dl, MVT::i32); | |||
3863 | } | |||
3864 | break; | |||
3865 | } | |||
3866 | } | |||
3867 | } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) && | |||
3868 | (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) { | |||
3869 | // In ARM and Thumb-2, the compare instructions can shift their second | |||
3870 | // operand. | |||
3871 | CC = ISD::getSetCCSwappedOperands(CC); | |||
3872 | std::swap(LHS, RHS); | |||
3873 | } | |||
3874 | ||||
3875 | ARMCC::CondCodes CondCode = IntCCToARMCC(CC); | |||
3876 | ARMISD::NodeType CompareType; | |||
3877 | switch (CondCode) { | |||
3878 | default: | |||
3879 | CompareType = ARMISD::CMP; | |||
3880 | break; | |||
3881 | case ARMCC::EQ: | |||
3882 | case ARMCC::NE: | |||
3883 | // Uses only Z Flag | |||
3884 | CompareType = ARMISD::CMPZ; | |||
3885 | break; | |||
3886 | } | |||
3887 | ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); | |||
3888 | return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); | |||
3889 | } | |||
3890 | ||||
3891 | /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. | |||
3892 | SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, | |||
3893 | SelectionDAG &DAG, const SDLoc &dl, | |||
3894 | bool InvalidOnQNaN) const { | |||
3895 | assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)((!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64 ) ? static_cast<void> (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3895, __PRETTY_FUNCTION__)); | |||
3896 | SDValue Cmp; | |||
3897 | SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32); | |||
3898 | if (!isFloatingPointZero(RHS)) | |||
3899 | Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C); | |||
3900 | else | |||
3901 | Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C); | |||
3902 | return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); | |||
3903 | } | |||
3904 | ||||
3905 | /// duplicateCmp - Glue values can have only one use, so this function | |||
3906 | /// duplicates a comparison node. | |||
3907 | SDValue | |||
3908 | ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { | |||
3909 | unsigned Opc = Cmp.getOpcode(); | |||
3910 | SDLoc DL(Cmp); | |||
3911 | if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) | |||
3912 | return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); | |||
3913 | ||||
3914 | assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation" ) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3914, __PRETTY_FUNCTION__)); | |||
3915 | Cmp = Cmp.getOperand(0); | |||
3916 | Opc = Cmp.getOpcode(); | |||
3917 | if (Opc == ARMISD::CMPFP) | |||
3918 | Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0), | |||
3919 | Cmp.getOperand(1), Cmp.getOperand(2)); | |||
3920 | else { | |||
3921 | assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT" ) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3921, __PRETTY_FUNCTION__)); | |||
3922 | Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0), | |||
3923 | Cmp.getOperand(1)); | |||
3924 | } | |||
3925 | return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); | |||
3926 | } | |||
3927 | ||||
3928 | // This function returns three things: the arithmetic computation itself | |||
3929 | // (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The | |||
3930 | // comparison and the condition code define the case in which the arithmetic | |||
3931 | // computation *does not* overflow. | |||
3932 | std::pair<SDValue, SDValue> | |||
3933 | ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, | |||
3934 | SDValue &ARMcc) const { | |||
3935 | assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3935, __PRETTY_FUNCTION__)); | |||
3936 | ||||
3937 | SDValue Value, OverflowCmp; | |||
3938 | SDValue LHS = Op.getOperand(0); | |||
3939 | SDValue RHS = Op.getOperand(1); | |||
3940 | SDLoc dl(Op); | |||
3941 | ||||
3942 | // FIXME: We are currently always generating CMPs because we don't support | |||
3943 | // generating CMN through the backend. This is not as good as the natural | |||
3944 | // CMP case because it causes a register dependency and cannot be folded | |||
3945 | // later. | |||
3946 | ||||
3947 | switch (Op.getOpcode()) { | |||
3948 | default: | |||
3949 | llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 3949); | |||
3950 | case ISD::SADDO: | |||
3951 | ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); | |||
3952 | Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS); | |||
3953 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); | |||
3954 | break; | |||
3955 | case ISD::UADDO: | |||
3956 | ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); | |||
3957 | // We use ADDC here to correspond to its use in LowerUnsignedALUO. | |||
3958 | // We do not use it in the USUBO case as Value may not be used. | |||
3959 | Value = DAG.getNode(ARMISD::ADDC, dl, | |||
3960 | DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS) | |||
3961 | .getValue(0); | |||
3962 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); | |||
3963 | break; | |||
3964 | case ISD::SSUBO: | |||
3965 | ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); | |||
3966 | Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS); | |||
3967 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); | |||
3968 | break; | |||
3969 | case ISD::USUBO: | |||
3970 | ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); | |||
3971 | Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS); | |||
3972 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); | |||
3973 | break; | |||
3974 | case ISD::UMULO: | |||
3975 | // We generate a UMUL_LOHI and then check if the high word is 0. | |||
3976 | ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32); | |||
3977 | Value = DAG.getNode(ISD::UMUL_LOHI, dl, | |||
3978 | DAG.getVTList(Op.getValueType(), Op.getValueType()), | |||
3979 | LHS, RHS); | |||
3980 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1), | |||
3981 | DAG.getConstant(0, dl, MVT::i32)); | |||
3982 | Value = Value.getValue(0); // We only want the low 32 bits for the result. | |||
3983 | break; | |||
3984 | case ISD::SMULO: | |||
3985 | // We generate a SMUL_LOHI and then check if all the bits of the high word | |||
3986 | // are the same as the sign bit of the low word. | |||
3987 | ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32); | |||
3988 | Value = DAG.getNode(ISD::SMUL_LOHI, dl, | |||
3989 | DAG.getVTList(Op.getValueType(), Op.getValueType()), | |||
3990 | LHS, RHS); | |||
3991 | OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1), | |||
3992 | DAG.getNode(ISD::SRA, dl, Op.getValueType(), | |||
3993 | Value.getValue(0), | |||
3994 | DAG.getConstant(31, dl, MVT::i32))); | |||
3995 | Value = Value.getValue(0); // We only want the low 32 bits for the result. | |||
3996 | break; | |||
3997 | } // switch (...) | |||
3998 | ||||
3999 | return std::make_pair(Value, OverflowCmp); | |||
4000 | } | |||
4001 | ||||
4002 | SDValue | |||
4003 | ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const { | |||
4004 | // Let legalize expand this if it isn't a legal type yet. | |||
4005 | if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) | |||
4006 | return SDValue(); | |||
4007 | ||||
4008 | SDValue Value, OverflowCmp; | |||
4009 | SDValue ARMcc; | |||
4010 | std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc); | |||
4011 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4012 | SDLoc dl(Op); | |||
4013 | // We use 0 and 1 as false and true values. | |||
4014 | SDValue TVal = DAG.getConstant(1, dl, MVT::i32); | |||
4015 | SDValue FVal = DAG.getConstant(0, dl, MVT::i32); | |||
4016 | EVT VT = Op.getValueType(); | |||
4017 | ||||
4018 | SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal, | |||
4019 | ARMcc, CCR, OverflowCmp); | |||
4020 | ||||
4021 | SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); | |||
4022 | return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); | |||
4023 | } | |||
4024 | ||||
4025 | static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry, | |||
4026 | SelectionDAG &DAG) { | |||
4027 | SDLoc DL(BoolCarry); | |||
4028 | EVT CarryVT = BoolCarry.getValueType(); | |||
4029 | ||||
4030 | // This converts the boolean value carry into the carry flag by doing | |||
4031 | // ARMISD::SUBC Carry, 1 | |||
4032 | SDValue Carry = DAG.getNode(ARMISD::SUBC, DL, | |||
4033 | DAG.getVTList(CarryVT, MVT::i32), | |||
4034 | BoolCarry, DAG.getConstant(1, DL, CarryVT)); | |||
4035 | return Carry.getValue(1); | |||
4036 | } | |||
4037 | ||||
4038 | static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT, | |||
4039 | SelectionDAG &DAG) { | |||
4040 | SDLoc DL(Flags); | |||
4041 | ||||
4042 | // Now convert the carry flag into a boolean carry. We do this | |||
4043 | // using ARMISD:ADDE 0, 0, Carry | |||
4044 | return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), | |||
4045 | DAG.getConstant(0, DL, MVT::i32), | |||
4046 | DAG.getConstant(0, DL, MVT::i32), Flags); | |||
4047 | } | |||
4048 | ||||
4049 | SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, | |||
4050 | SelectionDAG &DAG) const { | |||
4051 | // Let legalize expand this if it isn't a legal type yet. | |||
4052 | if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) | |||
4053 | return SDValue(); | |||
4054 | ||||
4055 | SDValue LHS = Op.getOperand(0); | |||
4056 | SDValue RHS = Op.getOperand(1); | |||
4057 | SDLoc dl(Op); | |||
4058 | ||||
4059 | EVT VT = Op.getValueType(); | |||
4060 | SDVTList VTs = DAG.getVTList(VT, MVT::i32); | |||
4061 | SDValue Value; | |||
4062 | SDValue Overflow; | |||
4063 | switch (Op.getOpcode()) { | |||
4064 | default: | |||
4065 | llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4065); | |||
4066 | case ISD::UADDO: | |||
4067 | Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); | |||
4068 | // Convert the carry flag into a boolean value. | |||
4069 | Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); | |||
4070 | break; | |||
4071 | case ISD::USUBO: { | |||
4072 | Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); | |||
4073 | // Convert the carry flag into a boolean value. | |||
4074 | Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); | |||
4075 | // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow | |||
4076 | // value. So compute 1 - C. | |||
4077 | Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32, | |||
4078 | DAG.getConstant(1, dl, MVT::i32), Overflow); | |||
4079 | break; | |||
4080 | } | |||
4081 | } | |||
4082 | ||||
4083 | return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); | |||
4084 | } | |||
4085 | ||||
4086 | SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { | |||
4087 | SDValue Cond = Op.getOperand(0); | |||
4088 | SDValue SelectTrue = Op.getOperand(1); | |||
4089 | SDValue SelectFalse = Op.getOperand(2); | |||
4090 | SDLoc dl(Op); | |||
4091 | unsigned Opc = Cond.getOpcode(); | |||
4092 | ||||
4093 | if (Cond.getResNo() == 1 && | |||
4094 | (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || | |||
4095 | Opc == ISD::USUBO)) { | |||
4096 | if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0))) | |||
4097 | return SDValue(); | |||
4098 | ||||
4099 | SDValue Value, OverflowCmp; | |||
4100 | SDValue ARMcc; | |||
4101 | std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc); | |||
4102 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4103 | EVT VT = Op.getValueType(); | |||
4104 | ||||
4105 | return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR, | |||
4106 | OverflowCmp, DAG); | |||
4107 | } | |||
4108 | ||||
4109 | // Convert: | |||
4110 | // | |||
4111 | // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) | |||
4112 | // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) | |||
4113 | // | |||
4114 | if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { | |||
4115 | const ConstantSDNode *CMOVTrue = | |||
4116 | dyn_cast<ConstantSDNode>(Cond.getOperand(0)); | |||
4117 | const ConstantSDNode *CMOVFalse = | |||
4118 | dyn_cast<ConstantSDNode>(Cond.getOperand(1)); | |||
4119 | ||||
4120 | if (CMOVTrue && CMOVFalse) { | |||
4121 | unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); | |||
4122 | unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); | |||
4123 | ||||
4124 | SDValue True; | |||
4125 | SDValue False; | |||
4126 | if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { | |||
4127 | True = SelectTrue; | |||
4128 | False = SelectFalse; | |||
4129 | } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { | |||
4130 | True = SelectFalse; | |||
4131 | False = SelectTrue; | |||
4132 | } | |||
4133 | ||||
4134 | if (True.getNode() && False.getNode()) { | |||
4135 | EVT VT = Op.getValueType(); | |||
4136 | SDValue ARMcc = Cond.getOperand(2); | |||
4137 | SDValue CCR = Cond.getOperand(3); | |||
4138 | SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); | |||
4139 | assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4139, __PRETTY_FUNCTION__)); | |||
4140 | return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG); | |||
4141 | } | |||
4142 | } | |||
4143 | } | |||
4144 | ||||
4145 | // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the | |||
4146 | // undefined bits before doing a full-word comparison with zero. | |||
4147 | Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond, | |||
4148 | DAG.getConstant(1, dl, Cond.getValueType())); | |||
4149 | ||||
4150 | return DAG.getSelectCC(dl, Cond, | |||
4151 | DAG.getConstant(0, dl, Cond.getValueType()), | |||
4152 | SelectTrue, SelectFalse, ISD::SETNE); | |||
4153 | } | |||
4154 | ||||
4155 | static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, | |||
4156 | bool &swpCmpOps, bool &swpVselOps) { | |||
4157 | // Start by selecting the GE condition code for opcodes that return true for | |||
4158 | // 'equality' | |||
4159 | if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE || | |||
4160 | CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE) | |||
4161 | CondCode = ARMCC::GE; | |||
4162 | ||||
4163 | // and GT for opcodes that return false for 'equality'. | |||
4164 | else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || | |||
4165 | CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT) | |||
4166 | CondCode = ARMCC::GT; | |||
4167 | ||||
4168 | // Since we are constrained to GE/GT, if the opcode contains 'less', we need | |||
4169 | // to swap the compare operands. | |||
4170 | if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT || | |||
4171 | CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT) | |||
4172 | swpCmpOps = true; | |||
4173 | ||||
4174 | // Both GT and GE are ordered comparisons, and return false for 'unordered'. | |||
4175 | // If we have an unordered opcode, we need to swap the operands to the VSEL | |||
4176 | // instruction (effectively negating the condition). | |||
4177 | // | |||
4178 | // This also has the effect of swapping which one of 'less' or 'greater' | |||
4179 | // returns true, so we also swap the compare operands. It also switches | |||
4180 | // whether we return true for 'equality', so we compensate by picking the | |||
4181 | // opposite condition code to our original choice. | |||
4182 | if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || | |||
4183 | CC == ISD::SETUGT) { | |||
4184 | swpCmpOps = !swpCmpOps; | |||
4185 | swpVselOps = !swpVselOps; | |||
4186 | CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT; | |||
4187 | } | |||
4188 | ||||
4189 | // 'ordered' is 'anything but unordered', so use the VS condition code and | |||
4190 | // swap the VSEL operands. | |||
4191 | if (CC == ISD::SETO) { | |||
4192 | CondCode = ARMCC::VS; | |||
4193 | swpVselOps = true; | |||
4194 | } | |||
4195 | ||||
4196 | // 'unordered or not equal' is 'anything but equal', so use the EQ condition | |||
4197 | // code and swap the VSEL operands. Also do this if we don't care about the | |||
4198 | // unordered case. | |||
4199 | if (CC == ISD::SETUNE || CC == ISD::SETNE) { | |||
4200 | CondCode = ARMCC::EQ; | |||
4201 | swpVselOps = true; | |||
4202 | } | |||
4203 | } | |||
4204 | ||||
4205 | SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, | |||
4206 | SDValue TrueVal, SDValue ARMcc, SDValue CCR, | |||
4207 | SDValue Cmp, SelectionDAG &DAG) const { | |||
4208 | if (Subtarget->isFPOnlySP() && VT == MVT::f64) { | |||
4209 | FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
4210 | DAG.getVTList(MVT::i32, MVT::i32), FalseVal); | |||
4211 | TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
4212 | DAG.getVTList(MVT::i32, MVT::i32), TrueVal); | |||
4213 | ||||
4214 | SDValue TrueLow = TrueVal.getValue(0); | |||
4215 | SDValue TrueHigh = TrueVal.getValue(1); | |||
4216 | SDValue FalseLow = FalseVal.getValue(0); | |||
4217 | SDValue FalseHigh = FalseVal.getValue(1); | |||
4218 | ||||
4219 | SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow, | |||
4220 | ARMcc, CCR, Cmp); | |||
4221 | SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh, | |||
4222 | ARMcc, CCR, duplicateCmp(Cmp, DAG)); | |||
4223 | ||||
4224 | return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); | |||
4225 | } else { | |||
4226 | return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, | |||
4227 | Cmp); | |||
4228 | } | |||
4229 | } | |||
4230 | ||||
4231 | static bool isGTorGE(ISD::CondCode CC) { | |||
4232 | return CC == ISD::SETGT || CC == ISD::SETGE; | |||
4233 | } | |||
4234 | ||||
4235 | static bool isLTorLE(ISD::CondCode CC) { | |||
4236 | return CC == ISD::SETLT || CC == ISD::SETLE; | |||
4237 | } | |||
4238 | ||||
4239 | // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating. | |||
4240 | // All of these conditions (and their <= and >= counterparts) will do: | |||
4241 | // x < k ? k : x | |||
4242 | // x > k ? x : k | |||
4243 | // k < x ? x : k | |||
4244 | // k > x ? k : x | |||
4245 | static bool isLowerSaturate(const SDValue LHS, const SDValue RHS, | |||
4246 | const SDValue TrueVal, const SDValue FalseVal, | |||
4247 | const ISD::CondCode CC, const SDValue K) { | |||
4248 | return (isGTorGE(CC) && | |||
4249 | ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) || | |||
4250 | (isLTorLE(CC) && | |||
4251 | ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))); | |||
4252 | } | |||
4253 | ||||
4254 | // Similar to isLowerSaturate(), but checks for upper-saturating conditions. | |||
4255 | static bool isUpperSaturate(const SDValue LHS, const SDValue RHS, | |||
4256 | const SDValue TrueVal, const SDValue FalseVal, | |||
4257 | const ISD::CondCode CC, const SDValue K) { | |||
4258 | return (isGTorGE(CC) && | |||
4259 | ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) || | |||
4260 | (isLTorLE(CC) && | |||
4261 | ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))); | |||
4262 | } | |||
4263 | ||||
4264 | // Check if two chained conditionals could be converted into SSAT or USAT. | |||
4265 | // | |||
4266 | // SSAT can replace a set of two conditional selectors that bound a number to an | |||
4267 | // interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples: | |||
4268 | // | |||
4269 | // x < -k ? -k : (x > k ? k : x) | |||
4270 | // x < -k ? -k : (x < k ? x : k) | |||
4271 | // x > -k ? (x > k ? k : x) : -k | |||
4272 | // x < k ? (x < -k ? -k : x) : k | |||
4273 | // etc. | |||
4274 | // | |||
4275 | // USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is | |||
4276 | // a power of 2. | |||
4277 | // | |||
4278 | // It returns true if the conversion can be done, false otherwise. | |||
4279 | // Additionally, the variable is returned in parameter V, the constant in K and | |||
4280 | // usat is set to true if the conditional represents an unsigned saturation | |||
4281 | static bool isSaturatingConditional(const SDValue &Op, SDValue &V, | |||
4282 | uint64_t &K, bool &usat) { | |||
4283 | SDValue LHS1 = Op.getOperand(0); | |||
4284 | SDValue RHS1 = Op.getOperand(1); | |||
4285 | SDValue TrueVal1 = Op.getOperand(2); | |||
4286 | SDValue FalseVal1 = Op.getOperand(3); | |||
4287 | ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get(); | |||
4288 | ||||
4289 | const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1; | |||
4290 | if (Op2.getOpcode() != ISD::SELECT_CC) | |||
4291 | return false; | |||
4292 | ||||
4293 | SDValue LHS2 = Op2.getOperand(0); | |||
4294 | SDValue RHS2 = Op2.getOperand(1); | |||
4295 | SDValue TrueVal2 = Op2.getOperand(2); | |||
4296 | SDValue FalseVal2 = Op2.getOperand(3); | |||
4297 | ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get(); | |||
4298 | ||||
4299 | // Find out which are the constants and which are the variables | |||
4300 | // in each conditional | |||
4301 | SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1) | |||
4302 | ? &RHS1 | |||
4303 | : nullptr; | |||
4304 | SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2) | |||
4305 | ? &RHS2 | |||
4306 | : nullptr; | |||
4307 | SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2; | |||
4308 | SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1; | |||
4309 | SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2; | |||
4310 | SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2; | |||
4311 | ||||
4312 | // We must detect cases where the original operations worked with 16- or | |||
4313 | // 8-bit values. In such case, V2Tmp != V2 because the comparison operations | |||
4314 | // must work with sign-extended values but the select operations return | |||
4315 | // the original non-extended value. | |||
4316 | SDValue V2TmpReg = V2Tmp; | |||
4317 | if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG) | |||
4318 | V2TmpReg = V2Tmp->getOperand(0); | |||
4319 | ||||
4320 | // Check that the registers and the constants have the correct values | |||
4321 | // in both conditionals | |||
4322 | if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp || | |||
4323 | V2TmpReg != V2) | |||
4324 | return false; | |||
4325 | ||||
4326 | // Figure out which conditional is saturating the lower/upper bound. | |||
4327 | const SDValue *LowerCheckOp = | |||
4328 | isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1) | |||
4329 | ? &Op | |||
4330 | : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) | |||
4331 | ? &Op2 | |||
4332 | : nullptr; | |||
4333 | const SDValue *UpperCheckOp = | |||
4334 | isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1) | |||
4335 | ? &Op | |||
4336 | : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) | |||
4337 | ? &Op2 | |||
4338 | : nullptr; | |||
4339 | ||||
4340 | if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp) | |||
4341 | return false; | |||
4342 | ||||
4343 | // Check that the constant in the lower-bound check is | |||
4344 | // the opposite of the constant in the upper-bound check | |||
4345 | // in 1's complement. | |||
4346 | int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue(); | |||
4347 | int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue(); | |||
4348 | int64_t PosVal = std::max(Val1, Val2); | |||
4349 | int64_t NegVal = std::min(Val1, Val2); | |||
4350 | ||||
4351 | if (((Val1 > Val2 && UpperCheckOp == &Op) || | |||
4352 | (Val1 < Val2 && UpperCheckOp == &Op2)) && | |||
4353 | isPowerOf2_64(PosVal + 1)) { | |||
4354 | ||||
4355 | // Handle the difference between USAT (unsigned) and SSAT (signed) saturation | |||
4356 | if (Val1 == ~Val2) | |||
4357 | usat = false; | |||
4358 | else if (NegVal == 0) | |||
4359 | usat = true; | |||
4360 | else | |||
4361 | return false; | |||
4362 | ||||
4363 | V = V2; | |||
4364 | K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive | |||
4365 | ||||
4366 | return true; | |||
4367 | } | |||
4368 | ||||
4369 | return false; | |||
4370 | } | |||
4371 | ||||
4372 | // Check if a condition of the type x < k ? k : x can be converted into a | |||
4373 | // bit operation instead of conditional moves. | |||
4374 | // Currently this is allowed given: | |||
4375 | // - The conditions and values match up | |||
4376 | // - k is 0 or -1 (all ones) | |||
4377 | // This function will not check the last condition, thats up to the caller | |||
4378 | // It returns true if the transformation can be made, and in such case | |||
4379 | // returns x in V, and k in SatK. | |||
4380 | static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V, | |||
4381 | SDValue &SatK) | |||
4382 | { | |||
4383 | SDValue LHS = Op.getOperand(0); | |||
4384 | SDValue RHS = Op.getOperand(1); | |||
4385 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); | |||
4386 | SDValue TrueVal = Op.getOperand(2); | |||
4387 | SDValue FalseVal = Op.getOperand(3); | |||
4388 | ||||
4389 | SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS) | |||
4390 | ? &RHS | |||
4391 | : nullptr; | |||
4392 | ||||
4393 | // No constant operation in comparison, early out | |||
4394 | if (!K) | |||
4395 | return false; | |||
4396 | ||||
4397 | SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal; | |||
4398 | V = (KTmp == TrueVal) ? FalseVal : TrueVal; | |||
4399 | SDValue VTmp = (K && *K == LHS) ? RHS : LHS; | |||
4400 | ||||
4401 | // If the constant on left and right side, or variable on left and right, | |||
4402 | // does not match, early out | |||
4403 | if (*K != KTmp || V != VTmp) | |||
4404 | return false; | |||
4405 | ||||
4406 | if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) { | |||
4407 | SatK = *K; | |||
4408 | return true; | |||
4409 | } | |||
4410 | ||||
4411 | return false; | |||
4412 | } | |||
4413 | ||||
4414 | SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { | |||
4415 | EVT VT = Op.getValueType(); | |||
4416 | SDLoc dl(Op); | |||
4417 | ||||
4418 | // Try to convert two saturating conditional selects into a single SSAT | |||
4419 | SDValue SatValue; | |||
4420 | uint64_t SatConstant; | |||
4421 | bool SatUSat; | |||
4422 | if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) && | |||
4423 | isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) { | |||
4424 | if (SatUSat) | |||
4425 | return DAG.getNode(ARMISD::USAT, dl, VT, SatValue, | |||
4426 | DAG.getConstant(countTrailingOnes(SatConstant), dl, VT)); | |||
4427 | else | |||
4428 | return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue, | |||
4429 | DAG.getConstant(countTrailingOnes(SatConstant), dl, VT)); | |||
4430 | } | |||
4431 | ||||
4432 | // Try to convert expressions of the form x < k ? k : x (and similar forms) | |||
4433 | // into more efficient bit operations, which is possible when k is 0 or -1 | |||
4434 | // On ARM and Thumb-2 which have flexible operand 2 this will result in | |||
4435 | // single instructions. On Thumb the shift and the bit operation will be two | |||
4436 | // instructions. | |||
4437 | // Only allow this transformation on full-width (32-bit) operations | |||
4438 | SDValue LowerSatConstant; | |||
4439 | if (VT == MVT::i32 && | |||
4440 | isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) { | |||
4441 | SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue, | |||
4442 | DAG.getConstant(31, dl, VT)); | |||
4443 | if (isNullConstant(LowerSatConstant)) { | |||
4444 | SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV, | |||
4445 | DAG.getAllOnesConstant(dl, VT)); | |||
4446 | return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV); | |||
4447 | } else if (isAllOnesConstant(LowerSatConstant)) | |||
4448 | return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV); | |||
4449 | } | |||
4450 | ||||
4451 | SDValue LHS = Op.getOperand(0); | |||
4452 | SDValue RHS = Op.getOperand(1); | |||
4453 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); | |||
4454 | SDValue TrueVal = Op.getOperand(2); | |||
4455 | SDValue FalseVal = Op.getOperand(3); | |||
4456 | ||||
4457 | if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) { | |||
4458 | DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, | |||
4459 | dl); | |||
4460 | ||||
4461 | // If softenSetCCOperands only returned one value, we should compare it to | |||
4462 | // zero. | |||
4463 | if (!RHS.getNode()) { | |||
4464 | RHS = DAG.getConstant(0, dl, LHS.getValueType()); | |||
4465 | CC = ISD::SETNE; | |||
4466 | } | |||
4467 | } | |||
4468 | ||||
4469 | if (LHS.getValueType() == MVT::i32) { | |||
4470 | // Try to generate VSEL on ARMv8. | |||
4471 | // The VSEL instruction can't use all the usual ARM condition | |||
4472 | // codes: it only has two bits to select the condition code, so it's | |||
4473 | // constrained to use only GE, GT, VS and EQ. | |||
4474 | // | |||
4475 | // To implement all the various ISD::SETXXX opcodes, we sometimes need to | |||
4476 | // swap the operands of the previous compare instruction (effectively | |||
4477 | // inverting the compare condition, swapping 'less' and 'greater') and | |||
4478 | // sometimes need to swap the operands to the VSEL (which inverts the | |||
4479 | // condition in the sense of firing whenever the previous condition didn't) | |||
4480 | if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f16 || | |||
4481 | TrueVal.getValueType() == MVT::f32 || | |||
4482 | TrueVal.getValueType() == MVT::f64)) { | |||
4483 | ARMCC::CondCodes CondCode = IntCCToARMCC(CC); | |||
4484 | if (CondCode == ARMCC::LT || CondCode == ARMCC::LE || | |||
4485 | CondCode == ARMCC::VC || CondCode == ARMCC::NE) { | |||
4486 | CC = ISD::getSetCCInverse(CC, true); | |||
4487 | std::swap(TrueVal, FalseVal); | |||
4488 | } | |||
4489 | } | |||
4490 | ||||
4491 | SDValue ARMcc; | |||
4492 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4493 | SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); | |||
4494 | return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG); | |||
4495 | } | |||
4496 | ||||
4497 | ARMCC::CondCodes CondCode, CondCode2; | |||
4498 | bool InvalidOnQNaN; | |||
4499 | FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN); | |||
4500 | ||||
4501 | // Normalize the fp compare. If RHS is zero we prefer to keep it there so we | |||
4502 | // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we | |||
4503 | // must use VSEL (limited condition codes), due to not having conditional f16 | |||
4504 | // moves. | |||
4505 | if (Subtarget->hasFPARMv8() && | |||
4506 | !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) && | |||
4507 | (TrueVal.getValueType() == MVT::f16 || | |||
4508 | TrueVal.getValueType() == MVT::f32 || | |||
4509 | TrueVal.getValueType() == MVT::f64)) { | |||
4510 | bool swpCmpOps = false; | |||
4511 | bool swpVselOps = false; | |||
4512 | checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps); | |||
4513 | ||||
4514 | if (CondCode == ARMCC::GT || CondCode == ARMCC::GE || | |||
4515 | CondCode == ARMCC::VS || CondCode == ARMCC::EQ) { | |||
4516 | if (swpCmpOps) | |||
4517 | std::swap(LHS, RHS); | |||
4518 | if (swpVselOps) | |||
4519 | std::swap(TrueVal, FalseVal); | |||
4520 | } | |||
4521 | } | |||
4522 | ||||
4523 | SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); | |||
4524 | SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN); | |||
4525 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4526 | SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG); | |||
4527 | if (CondCode2 != ARMCC::AL) { | |||
4528 | SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32); | |||
4529 | // FIXME: Needs another CMP because flag can have but one use. | |||
4530 | SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN); | |||
4531 | Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG); | |||
4532 | } | |||
4533 | return Result; | |||
4534 | } | |||
4535 | ||||
4536 | /// canChangeToInt - Given the fp compare operand, return true if it is suitable | |||
4537 | /// to morph to an integer compare sequence. | |||
4538 | static bool canChangeToInt(SDValue Op, bool &SeenZero, | |||
4539 | const ARMSubtarget *Subtarget) { | |||
4540 | SDNode *N = Op.getNode(); | |||
4541 | if (!N->hasOneUse()) | |||
4542 | // Otherwise it requires moving the value from fp to integer registers. | |||
4543 | return false; | |||
4544 | if (!N->getNumValues()) | |||
4545 | return false; | |||
4546 | EVT VT = Op.getValueType(); | |||
4547 | if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) | |||
4548 | // f32 case is generally profitable. f64 case only makes sense when vcmpe + | |||
4549 | // vmrs are very slow, e.g. cortex-a8. | |||
4550 | return false; | |||
4551 | ||||
4552 | if (isFloatingPointZero(Op)) { | |||
4553 | SeenZero = true; | |||
4554 | return true; | |||
4555 | } | |||
4556 | return ISD::isNormalLoad(N); | |||
4557 | } | |||
4558 | ||||
4559 | static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { | |||
4560 | if (isFloatingPointZero(Op)) | |||
4561 | return DAG.getConstant(0, SDLoc(Op), MVT::i32); | |||
4562 | ||||
4563 | if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) | |||
4564 | return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(), | |||
4565 | Ld->getPointerInfo(), Ld->getAlignment(), | |||
4566 | Ld->getMemOperand()->getFlags()); | |||
4567 | ||||
4568 | llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4568); | |||
4569 | } | |||
4570 | ||||
4571 | static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, | |||
4572 | SDValue &RetVal1, SDValue &RetVal2) { | |||
4573 | SDLoc dl(Op); | |||
4574 | ||||
4575 | if (isFloatingPointZero(Op)) { | |||
4576 | RetVal1 = DAG.getConstant(0, dl, MVT::i32); | |||
4577 | RetVal2 = DAG.getConstant(0, dl, MVT::i32); | |||
4578 | return; | |||
4579 | } | |||
4580 | ||||
4581 | if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { | |||
4582 | SDValue Ptr = Ld->getBasePtr(); | |||
4583 | RetVal1 = | |||
4584 | DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(), | |||
4585 | Ld->getAlignment(), Ld->getMemOperand()->getFlags()); | |||
4586 | ||||
4587 | EVT PtrType = Ptr.getValueType(); | |||
4588 | unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); | |||
4589 | SDValue NewPtr = DAG.getNode(ISD::ADD, dl, | |||
4590 | PtrType, Ptr, DAG.getConstant(4, dl, PtrType)); | |||
4591 | RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr, | |||
4592 | Ld->getPointerInfo().getWithOffset(4), NewAlign, | |||
4593 | Ld->getMemOperand()->getFlags()); | |||
4594 | return; | |||
4595 | } | |||
4596 | ||||
4597 | llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4597); | |||
4598 | } | |||
4599 | ||||
4600 | /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some | |||
4601 | /// f32 and even f64 comparisons to integer ones. | |||
4602 | SDValue | |||
4603 | ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { | |||
4604 | SDValue Chain = Op.getOperand(0); | |||
4605 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); | |||
4606 | SDValue LHS = Op.getOperand(2); | |||
4607 | SDValue RHS = Op.getOperand(3); | |||
4608 | SDValue Dest = Op.getOperand(4); | |||
4609 | SDLoc dl(Op); | |||
4610 | ||||
4611 | bool LHSSeenZero = false; | |||
4612 | bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget); | |||
4613 | bool RHSSeenZero = false; | |||
4614 | bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget); | |||
4615 | if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) { | |||
4616 | // If unsafe fp math optimization is enabled and there are no other uses of | |||
4617 | // the CMP operands, and the condition code is EQ or NE, we can optimize it | |||
4618 | // to an integer comparison. | |||
4619 | if (CC == ISD::SETOEQ) | |||
4620 | CC = ISD::SETEQ; | |||
4621 | else if (CC == ISD::SETUNE) | |||
4622 | CC = ISD::SETNE; | |||
4623 | ||||
4624 | SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32); | |||
4625 | SDValue ARMcc; | |||
4626 | if (LHS.getValueType() == MVT::f32) { | |||
4627 | LHS = DAG.getNode(ISD::AND, dl, MVT::i32, | |||
4628 | bitcastf32Toi32(LHS, DAG), Mask); | |||
4629 | RHS = DAG.getNode(ISD::AND, dl, MVT::i32, | |||
4630 | bitcastf32Toi32(RHS, DAG), Mask); | |||
4631 | SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); | |||
4632 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4633 | return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, | |||
4634 | Chain, Dest, ARMcc, CCR, Cmp); | |||
4635 | } | |||
4636 | ||||
4637 | SDValue LHS1, LHS2; | |||
4638 | SDValue RHS1, RHS2; | |||
4639 | expandf64Toi32(LHS, DAG, LHS1, LHS2); | |||
4640 | expandf64Toi32(RHS, DAG, RHS1, RHS2); | |||
4641 | LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); | |||
4642 | RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); | |||
4643 | ARMCC::CondCodes CondCode = IntCCToARMCC(CC); | |||
4644 | ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); | |||
4645 | SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); | |||
4646 | SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; | |||
4647 | return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops); | |||
4648 | } | |||
4649 | ||||
4650 | return SDValue(); | |||
4651 | } | |||
4652 | ||||
4653 | SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { | |||
4654 | SDValue Chain = Op.getOperand(0); | |||
4655 | SDValue Cond = Op.getOperand(1); | |||
4656 | SDValue Dest = Op.getOperand(2); | |||
4657 | SDLoc dl(Op); | |||
4658 | ||||
4659 | // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch | |||
4660 | // instruction. | |||
4661 | unsigned Opc = Cond.getOpcode(); | |||
4662 | bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && | |||
4663 | !Subtarget->isThumb1Only(); | |||
4664 | if (Cond.getResNo() == 1 && | |||
4665 | (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || | |||
4666 | Opc == ISD::USUBO || OptimizeMul)) { | |||
4667 | // Only lower legal XALUO ops. | |||
4668 | if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0))) | |||
4669 | return SDValue(); | |||
4670 | ||||
4671 | // The actual operation with overflow check. | |||
4672 | SDValue Value, OverflowCmp; | |||
4673 | SDValue ARMcc; | |||
4674 | std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc); | |||
4675 | ||||
4676 | // Reverse the condition code. | |||
4677 | ARMCC::CondCodes CondCode = | |||
4678 | (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue(); | |||
4679 | CondCode = ARMCC::getOppositeCondition(CondCode); | |||
4680 | ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32); | |||
4681 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4682 | ||||
4683 | return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, | |||
4684 | OverflowCmp); | |||
4685 | } | |||
4686 | ||||
4687 | return SDValue(); | |||
4688 | } | |||
4689 | ||||
4690 | SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { | |||
4691 | SDValue Chain = Op.getOperand(0); | |||
4692 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); | |||
4693 | SDValue LHS = Op.getOperand(2); | |||
4694 | SDValue RHS = Op.getOperand(3); | |||
4695 | SDValue Dest = Op.getOperand(4); | |||
4696 | SDLoc dl(Op); | |||
4697 | ||||
4698 | if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) { | |||
4699 | DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, | |||
4700 | dl); | |||
4701 | ||||
4702 | // If softenSetCCOperands only returned one value, we should compare it to | |||
4703 | // zero. | |||
4704 | if (!RHS.getNode()) { | |||
4705 | RHS = DAG.getConstant(0, dl, LHS.getValueType()); | |||
4706 | CC = ISD::SETNE; | |||
4707 | } | |||
4708 | } | |||
4709 | ||||
4710 | // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch | |||
4711 | // instruction. | |||
4712 | unsigned Opc = LHS.getOpcode(); | |||
4713 | bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && | |||
4714 | !Subtarget->isThumb1Only(); | |||
4715 | if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && | |||
4716 | (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || | |||
4717 | Opc == ISD::USUBO || OptimizeMul) && | |||
4718 | (CC == ISD::SETEQ || CC == ISD::SETNE)) { | |||
4719 | // Only lower legal XALUO ops. | |||
4720 | if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0))) | |||
4721 | return SDValue(); | |||
4722 | ||||
4723 | // The actual operation with overflow check. | |||
4724 | SDValue Value, OverflowCmp; | |||
4725 | SDValue ARMcc; | |||
4726 | std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc); | |||
4727 | ||||
4728 | if ((CC == ISD::SETNE) != isOneConstant(RHS)) { | |||
4729 | // Reverse the condition code. | |||
4730 | ARMCC::CondCodes CondCode = | |||
4731 | (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue(); | |||
4732 | CondCode = ARMCC::getOppositeCondition(CondCode); | |||
4733 | ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32); | |||
4734 | } | |||
4735 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4736 | ||||
4737 | return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, | |||
4738 | OverflowCmp); | |||
4739 | } | |||
4740 | ||||
4741 | if (LHS.getValueType() == MVT::i32) { | |||
4742 | SDValue ARMcc; | |||
4743 | SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); | |||
4744 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4745 | return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, | |||
4746 | Chain, Dest, ARMcc, CCR, Cmp); | |||
4747 | } | |||
4748 | ||||
4749 | if (getTargetMachine().Options.UnsafeFPMath && | |||
4750 | (CC == ISD::SETEQ || CC == ISD::SETOEQ || | |||
4751 | CC == ISD::SETNE || CC == ISD::SETUNE)) { | |||
4752 | if (SDValue Result = OptimizeVFPBrcond(Op, DAG)) | |||
4753 | return Result; | |||
4754 | } | |||
4755 | ||||
4756 | ARMCC::CondCodes CondCode, CondCode2; | |||
4757 | bool InvalidOnQNaN; | |||
4758 | FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN); | |||
4759 | ||||
4760 | SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); | |||
4761 | SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN); | |||
4762 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
4763 | SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); | |||
4764 | SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; | |||
4765 | SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); | |||
4766 | if (CondCode2 != ARMCC::AL) { | |||
4767 | ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32); | |||
4768 | SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; | |||
4769 | Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); | |||
4770 | } | |||
4771 | return Res; | |||
4772 | } | |||
4773 | ||||
4774 | SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { | |||
4775 | SDValue Chain = Op.getOperand(0); | |||
4776 | SDValue Table = Op.getOperand(1); | |||
4777 | SDValue Index = Op.getOperand(2); | |||
4778 | SDLoc dl(Op); | |||
4779 | ||||
4780 | EVT PTy = getPointerTy(DAG.getDataLayout()); | |||
4781 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); | |||
4782 | SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); | |||
4783 | Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI); | |||
4784 | Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy)); | |||
4785 | SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index); | |||
4786 | if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) { | |||
4787 | // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table | |||
4788 | // which does another jump to the destination. This also makes it easier | |||
4789 | // to translate it to TBB / TBH later (Thumb2 only). | |||
4790 | // FIXME: This might not work if the function is extremely large. | |||
4791 | return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, | |||
4792 | Addr, Op.getOperand(2), JTI); | |||
4793 | } | |||
4794 | if (isPositionIndependent() || Subtarget->isROPI()) { | |||
4795 | Addr = | |||
4796 | DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, | |||
4797 | MachinePointerInfo::getJumpTable(DAG.getMachineFunction())); | |||
4798 | Chain = Addr.getValue(1); | |||
4799 | Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr); | |||
4800 | return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); | |||
4801 | } else { | |||
4802 | Addr = | |||
4803 | DAG.getLoad(PTy, dl, Chain, Addr, | |||
4804 | MachinePointerInfo::getJumpTable(DAG.getMachineFunction())); | |||
4805 | Chain = Addr.getValue(1); | |||
4806 | return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); | |||
4807 | } | |||
4808 | } | |||
4809 | ||||
4810 | static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { | |||
4811 | EVT VT = Op.getValueType(); | |||
4812 | SDLoc dl(Op); | |||
4813 | ||||
4814 | if (Op.getValueType().getVectorElementType() == MVT::i32) { | |||
4815 | if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32) | |||
4816 | return Op; | |||
4817 | return DAG.UnrollVectorOp(Op.getNode()); | |||
4818 | } | |||
4819 | ||||
4820 | const bool HasFullFP16 = | |||
4821 | static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16(); | |||
4822 | ||||
4823 | EVT NewTy; | |||
4824 | const EVT OpTy = Op.getOperand(0).getValueType(); | |||
4825 | if (OpTy == MVT::v4f32) | |||
4826 | NewTy = MVT::v4i32; | |||
4827 | else if (OpTy == MVT::v4f16 && HasFullFP16) | |||
4828 | NewTy = MVT::v4i16; | |||
4829 | else if (OpTy == MVT::v8f16 && HasFullFP16) | |||
4830 | NewTy = MVT::v8i16; | |||
4831 | else | |||
4832 | llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4832); | |||
4833 | ||||
4834 | if (VT != MVT::v4i16 && VT != MVT::v8i16) | |||
4835 | return DAG.UnrollVectorOp(Op.getNode()); | |||
4836 | ||||
4837 | Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0)); | |||
4838 | return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); | |||
4839 | } | |||
4840 | ||||
4841 | SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { | |||
4842 | EVT VT = Op.getValueType(); | |||
4843 | if (VT.isVector()) | |||
4844 | return LowerVectorFP_TO_INT(Op, DAG); | |||
4845 | if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) { | |||
4846 | RTLIB::Libcall LC; | |||
4847 | if (Op.getOpcode() == ISD::FP_TO_SINT) | |||
4848 | LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), | |||
4849 | Op.getValueType()); | |||
4850 | else | |||
4851 | LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), | |||
4852 | Op.getValueType()); | |||
4853 | return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0), | |||
4854 | /*isSigned*/ false, SDLoc(Op)).first; | |||
4855 | } | |||
4856 | ||||
4857 | return Op; | |||
4858 | } | |||
4859 | ||||
4860 | static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { | |||
4861 | EVT VT = Op.getValueType(); | |||
4862 | SDLoc dl(Op); | |||
4863 | ||||
4864 | if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { | |||
4865 | if (VT.getVectorElementType() == MVT::f32) | |||
4866 | return Op; | |||
4867 | return DAG.UnrollVectorOp(Op.getNode()); | |||
4868 | } | |||
4869 | ||||
4870 | assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand (0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!" ) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4872, __PRETTY_FUNCTION__)) | |||
4871 | Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand (0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!" ) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4872, __PRETTY_FUNCTION__)) | |||
4872 | "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand (0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!" ) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4872, __PRETTY_FUNCTION__)); | |||
4873 | ||||
4874 | const bool HasFullFP16 = | |||
4875 | static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16(); | |||
4876 | ||||
4877 | EVT DestVecType; | |||
4878 | if (VT == MVT::v4f32) | |||
4879 | DestVecType = MVT::v4i32; | |||
4880 | else if (VT == MVT::v4f16 && HasFullFP16) | |||
4881 | DestVecType = MVT::v4i16; | |||
4882 | else if (VT == MVT::v8f16 && HasFullFP16) | |||
4883 | DestVecType = MVT::v8i16; | |||
4884 | else | |||
4885 | return DAG.UnrollVectorOp(Op.getNode()); | |||
4886 | ||||
4887 | unsigned CastOpc; | |||
4888 | unsigned Opc; | |||
4889 | switch (Op.getOpcode()) { | |||
4890 | default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 4890); | |||
4891 | case ISD::SINT_TO_FP: | |||
4892 | CastOpc = ISD::SIGN_EXTEND; | |||
4893 | Opc = ISD::SINT_TO_FP; | |||
4894 | break; | |||
4895 | case ISD::UINT_TO_FP: | |||
4896 | CastOpc = ISD::ZERO_EXTEND; | |||
4897 | Opc = ISD::UINT_TO_FP; | |||
4898 | break; | |||
4899 | } | |||
4900 | ||||
4901 | Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0)); | |||
4902 | return DAG.getNode(Opc, dl, VT, Op); | |||
4903 | } | |||
4904 | ||||
4905 | SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const { | |||
4906 | EVT VT = Op.getValueType(); | |||
4907 | if (VT.isVector()) | |||
4908 | return LowerVectorINT_TO_FP(Op, DAG); | |||
4909 | if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) { | |||
4910 | RTLIB::Libcall LC; | |||
4911 | if (Op.getOpcode() == ISD::SINT_TO_FP) | |||
4912 | LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), | |||
4913 | Op.getValueType()); | |||
4914 | else | |||
4915 | LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), | |||
4916 | Op.getValueType()); | |||
4917 | return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0), | |||
4918 | /*isSigned*/ false, SDLoc(Op)).first; | |||
4919 | } | |||
4920 | ||||
4921 | return Op; | |||
4922 | } | |||
4923 | ||||
4924 | SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { | |||
4925 | // Implement fcopysign with a fabs and a conditional fneg. | |||
4926 | SDValue Tmp0 = Op.getOperand(0); | |||
4927 | SDValue Tmp1 = Op.getOperand(1); | |||
4928 | SDLoc dl(Op); | |||
4929 | EVT VT = Op.getValueType(); | |||
4930 | EVT SrcVT = Tmp1.getValueType(); | |||
4931 | bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || | |||
4932 | Tmp0.getOpcode() == ARMISD::VMOVDRR; | |||
4933 | bool UseNEON = !InGPR && Subtarget->hasNEON(); | |||
4934 | ||||
4935 | if (UseNEON) { | |||
4936 | // Use VBSL to copy the sign bit. | |||
4937 | unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); | |||
4938 | SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, | |||
4939 | DAG.getTargetConstant(EncodedVal, dl, MVT::i32)); | |||
4940 | EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; | |||
4941 | if (VT == MVT::f64) | |||
4942 | Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, | |||
4943 | DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), | |||
4944 | DAG.getConstant(32, dl, MVT::i32)); | |||
4945 | else /*if (VT == MVT::f32)*/ | |||
4946 | Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); | |||
4947 | if (SrcVT == MVT::f32) { | |||
4948 | Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); | |||
4949 | if (VT == MVT::f64) | |||
4950 | Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, | |||
4951 | DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), | |||
4952 | DAG.getConstant(32, dl, MVT::i32)); | |||
4953 | } else if (VT == MVT::f32) | |||
4954 | Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, | |||
4955 | DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), | |||
4956 | DAG.getConstant(32, dl, MVT::i32)); | |||
4957 | Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); | |||
4958 | Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); | |||
4959 | ||||
4960 | SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), | |||
4961 | dl, MVT::i32); | |||
4962 | AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); | |||
4963 | SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, | |||
4964 | DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); | |||
4965 | ||||
4966 | SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, | |||
4967 | DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), | |||
4968 | DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); | |||
4969 | if (VT == MVT::f32) { | |||
4970 | Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); | |||
4971 | Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, | |||
4972 | DAG.getConstant(0, dl, MVT::i32)); | |||
4973 | } else { | |||
4974 | Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); | |||
4975 | } | |||
4976 | ||||
4977 | return Res; | |||
4978 | } | |||
4979 | ||||
4980 | // Bitcast operand 1 to i32. | |||
4981 | if (SrcVT == MVT::f64) | |||
4982 | Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), | |||
4983 | Tmp1).getValue(1); | |||
4984 | Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); | |||
4985 | ||||
4986 | // Or in the signbit with integer operations. | |||
4987 | SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); | |||
4988 | SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); | |||
4989 | Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); | |||
4990 | if (VT == MVT::f32) { | |||
4991 | Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, | |||
4992 | DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); | |||
4993 | return DAG.getNode(ISD::BITCAST, dl, MVT::f32, | |||
4994 | DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); | |||
4995 | } | |||
4996 | ||||
4997 | // f64: Or the high part with signbit and then combine two parts. | |||
4998 | Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), | |||
4999 | Tmp0); | |||
5000 | SDValue Lo = Tmp0.getValue(0); | |||
5001 | SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); | |||
5002 | Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); | |||
5003 | return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); | |||
5004 | } | |||
5005 | ||||
5006 | SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ | |||
5007 | MachineFunction &MF = DAG.getMachineFunction(); | |||
5008 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
5009 | MFI.setReturnAddressIsTaken(true); | |||
5010 | ||||
5011 | if (verifyReturnAddressArgumentIsConstant(Op, DAG)) | |||
5012 | return SDValue(); | |||
5013 | ||||
5014 | EVT VT = Op.getValueType(); | |||
5015 | SDLoc dl(Op); | |||
5016 | unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); | |||
5017 | if (Depth) { | |||
5018 | SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); | |||
5019 | SDValue Offset = DAG.getConstant(4, dl, MVT::i32); | |||
5020 | return DAG.getLoad(VT, dl, DAG.getEntryNode(), | |||
5021 | DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), | |||
5022 | MachinePointerInfo()); | |||
5023 | } | |||
5024 | ||||
5025 | // Return LR, which contains the return address. Mark it an implicit live-in. | |||
5026 | unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); | |||
5027 | return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); | |||
5028 | } | |||
5029 | ||||
5030 | SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { | |||
5031 | const ARMBaseRegisterInfo &ARI = | |||
5032 | *static_cast<const ARMBaseRegisterInfo*>(RegInfo); | |||
5033 | MachineFunction &MF = DAG.getMachineFunction(); | |||
5034 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
5035 | MFI.setFrameAddressIsTaken(true); | |||
5036 | ||||
5037 | EVT VT = Op.getValueType(); | |||
5038 | SDLoc dl(Op); // FIXME probably not meaningful | |||
5039 | unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); | |||
5040 | unsigned FrameReg = ARI.getFrameRegister(MF); | |||
5041 | SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); | |||
5042 | while (Depth--) | |||
5043 | FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, | |||
5044 | MachinePointerInfo()); | |||
5045 | return FrameAddr; | |||
5046 | } | |||
5047 | ||||
5048 | // FIXME? Maybe this could be a TableGen attribute on some registers and | |||
5049 | // this table could be generated automatically from RegInfo. | |||
5050 | unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT, | |||
5051 | SelectionDAG &DAG) const { | |||
5052 | unsigned Reg = StringSwitch<unsigned>(RegName) | |||
5053 | .Case("sp", ARM::SP) | |||
5054 | .Default(0); | |||
5055 | if (Reg) | |||
5056 | return Reg; | |||
5057 | report_fatal_error(Twine("Invalid register name \"" | |||
5058 | + StringRef(RegName) + "\".")); | |||
5059 | } | |||
5060 | ||||
5061 | // Result is 64 bit value so split into two 32 bit values and return as a | |||
5062 | // pair of values. | |||
5063 | static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results, | |||
5064 | SelectionDAG &DAG) { | |||
5065 | SDLoc DL(N); | |||
5066 | ||||
5067 | // This function is only supposed to be called for i64 type destination. | |||
5068 | assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result." ) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5069, __PRETTY_FUNCTION__)) | |||
5069 | && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result." ) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5069, __PRETTY_FUNCTION__)); | |||
5070 | ||||
5071 | SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL, | |||
5072 | DAG.getVTList(MVT::i32, MVT::i32, MVT::Other), | |||
5073 | N->getOperand(0), | |||
5074 | N->getOperand(1)); | |||
5075 | ||||
5076 | Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), | |||
5077 | Read.getValue(1))); | |||
5078 | Results.push_back(Read.getOperand(0)); | |||
5079 | } | |||
5080 | ||||
5081 | /// \p BC is a bitcast that is about to be turned into a VMOVDRR. | |||
5082 | /// When \p DstVT, the destination type of \p BC, is on the vector | |||
5083 | /// register bank and the source of bitcast, \p Op, operates on the same bank, | |||
5084 | /// it might be possible to combine them, such that everything stays on the | |||
5085 | /// vector register bank. | |||
5086 | /// \p return The node that would replace \p BT, if the combine | |||
5087 | /// is possible. | |||
5088 | static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC, | |||
5089 | SelectionDAG &DAG) { | |||
5090 | SDValue Op = BC->getOperand(0); | |||
5091 | EVT DstVT = BC->getValueType(0); | |||
5092 | ||||
5093 | // The only vector instruction that can produce a scalar (remember, | |||
5094 | // since the bitcast was about to be turned into VMOVDRR, the source | |||
5095 | // type is i64) from a vector is EXTRACT_VECTOR_ELT. | |||
5096 | // Moreover, we can do this combine only if there is one use. | |||
5097 | // Finally, if the destination type is not a vector, there is not | |||
5098 | // much point on forcing everything on the vector bank. | |||
5099 | if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || | |||
5100 | !Op.hasOneUse()) | |||
5101 | return SDValue(); | |||
5102 | ||||
5103 | // If the index is not constant, we will introduce an additional | |||
5104 | // multiply that will stick. | |||
5105 | // Give up in that case. | |||
5106 | ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | |||
5107 | if (!Index) | |||
5108 | return SDValue(); | |||
5109 | unsigned DstNumElt = DstVT.getVectorNumElements(); | |||
5110 | ||||
5111 | // Compute the new index. | |||
5112 | const APInt &APIntIndex = Index->getAPIntValue(); | |||
5113 | APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt); | |||
5114 | NewIndex *= APIntIndex; | |||
5115 | // Check if the new constant index fits into i32. | |||
5116 | if (NewIndex.getBitWidth() > 32) | |||
5117 | return SDValue(); | |||
5118 | ||||
5119 | // vMTy bitcast(i64 extractelt vNi64 src, i32 index) -> | |||
5120 | // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M) | |||
5121 | SDLoc dl(Op); | |||
5122 | SDValue ExtractSrc = Op.getOperand(0); | |||
5123 | EVT VecVT = EVT::getVectorVT( | |||
5124 | *DAG.getContext(), DstVT.getScalarType(), | |||
5125 | ExtractSrc.getValueType().getVectorNumElements() * DstNumElt); | |||
5126 | SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); | |||
5127 | return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, | |||
5128 | DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32)); | |||
5129 | } | |||
5130 | ||||
5131 | /// ExpandBITCAST - If the target supports VFP, this function is called to | |||
5132 | /// expand a bit convert where either the source or destination type is i64 to | |||
5133 | /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 | |||
5134 | /// operand type is illegal (e.g., v2f32 for a target that doesn't support | |||
5135 | /// vectors), since the legalizer won't know what to do with that. | |||
5136 | static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, | |||
5137 | const ARMSubtarget *Subtarget) { | |||
5138 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
5139 | SDLoc dl(N); | |||
5140 | SDValue Op = N->getOperand(0); | |||
5141 | ||||
5142 | // This function is only supposed to be called for i64 types, either as the | |||
5143 | // source or destination of the bit convert. | |||
5144 | EVT SrcVT = Op.getValueType(); | |||
5145 | EVT DstVT = N->getValueType(0); | |||
5146 | const bool HasFullFP16 = Subtarget->hasFullFP16(); | |||
5147 | ||||
5148 | if (SrcVT == MVT::f32 && DstVT == MVT::i32) { | |||
5149 | // FullFP16: half values are passed in S-registers, and we don't | |||
5150 | // need any of the bitcast and moves: | |||
5151 | // | |||
5152 | // t2: f32,ch = CopyFromReg t0, Register:f32 %0 | |||
5153 | // t5: i32 = bitcast t2 | |||
5154 | // t18: f16 = ARMISD::VMOVhr t5 | |||
5155 | if (Op.getOpcode() != ISD::CopyFromReg || | |||
5156 | Op.getValueType() != MVT::f32) | |||
5157 | return SDValue(); | |||
5158 | ||||
5159 | auto Move = N->use_begin(); | |||
5160 | if (Move->getOpcode() != ARMISD::VMOVhr) | |||
5161 | return SDValue(); | |||
5162 | ||||
5163 | SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) }; | |||
5164 | SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops); | |||
5165 | DAG.ReplaceAllUsesWith(*Move, &Copy); | |||
5166 | return Copy; | |||
5167 | } | |||
5168 | ||||
5169 | if (SrcVT == MVT::i16 && DstVT == MVT::f16) { | |||
5170 | if (!HasFullFP16) | |||
5171 | return SDValue(); | |||
5172 | // SoftFP: read half-precision arguments: | |||
5173 | // | |||
5174 | // t2: i32,ch = ... | |||
5175 | // t7: i16 = truncate t2 <~~~~ Op | |||
5176 | // t8: f16 = bitcast t7 <~~~~ N | |||
5177 | // | |||
5178 | if (Op.getOperand(0).getValueType() == MVT::i32) | |||
5179 | return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op), | |||
5180 | MVT::f16, Op.getOperand(0)); | |||
5181 | ||||
5182 | return SDValue(); | |||
5183 | } | |||
5184 | ||||
5185 | // Half-precision return values | |||
5186 | if (SrcVT == MVT::f16 && DstVT == MVT::i16) { | |||
5187 | if (!HasFullFP16) | |||
5188 | return SDValue(); | |||
5189 | // | |||
5190 | // t11: f16 = fadd t8, t10 | |||
5191 | // t12: i16 = bitcast t11 <~~~ SDNode N | |||
5192 | // t13: i32 = zero_extend t12 | |||
5193 | // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13 | |||
5194 | // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1 | |||
5195 | // | |||
5196 | // transform this into: | |||
5197 | // | |||
5198 | // t20: i32 = ARMISD::VMOVrh t11 | |||
5199 | // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20 | |||
5200 | // | |||
5201 | auto ZeroExtend = N->use_begin(); | |||
5202 | if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND || | |||
5203 | ZeroExtend->getValueType(0) != MVT::i32) | |||
5204 | return SDValue(); | |||
5205 | ||||
5206 | auto Copy = ZeroExtend->use_begin(); | |||
5207 | if (Copy->getOpcode() == ISD::CopyToReg && | |||
5208 | Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) { | |||
5209 | SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op); | |||
5210 | DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt); | |||
5211 | return Cvt; | |||
5212 | } | |||
5213 | return SDValue(); | |||
5214 | } | |||
5215 | ||||
5216 | if (!(SrcVT == MVT::i64 || DstVT == MVT::i64)) | |||
5217 | return SDValue(); | |||
5218 | ||||
5219 | // Turn i64->f64 into VMOVDRR. | |||
5220 | if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { | |||
5221 | // Do not force values to GPRs (this is what VMOVDRR does for the inputs) | |||
5222 | // if we can combine the bitcast with its source. | |||
5223 | if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG)) | |||
5224 | return Val; | |||
5225 | ||||
5226 | SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, | |||
5227 | DAG.getConstant(0, dl, MVT::i32)); | |||
5228 | SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, | |||
5229 | DAG.getConstant(1, dl, MVT::i32)); | |||
5230 | return DAG.getNode(ISD::BITCAST, dl, DstVT, | |||
5231 | DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); | |||
5232 | } | |||
5233 | ||||
5234 | // Turn f64->i64 into VMOVRRD. | |||
5235 | if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { | |||
5236 | SDValue Cvt; | |||
5237 | if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() && | |||
5238 | SrcVT.getVectorNumElements() > 1) | |||
5239 | Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
5240 | DAG.getVTList(MVT::i32, MVT::i32), | |||
5241 | DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); | |||
5242 | else | |||
5243 | Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, | |||
5244 | DAG.getVTList(MVT::i32, MVT::i32), Op); | |||
5245 | // Merge the pieces into a single i64 value. | |||
5246 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); | |||
5247 | } | |||
5248 | ||||
5249 | return SDValue(); | |||
5250 | } | |||
5251 | ||||
5252 | /// getZeroVector - Returns a vector of specified type with all zero elements. | |||
5253 | /// Zero vectors are used to represent vector negation and in those cases | |||
5254 | /// will be implemented with the NEON VNEG instruction. However, VNEG does | |||
5255 | /// not support i64 elements, so sometimes the zero vectors will need to be | |||
5256 | /// explicitly constructed. Regardless, use a canonical VMOV to create the | |||
5257 | /// zero vector. | |||
5258 | static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) { | |||
5259 | assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast <void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5259, __PRETTY_FUNCTION__)); | |||
5260 | // The canonical modified immediate encoding of a zero vector is....0! | |||
5261 | SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32); | |||
5262 | EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; | |||
5263 | SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); | |||
5264 | return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); | |||
5265 | } | |||
5266 | ||||
5267 | /// LowerShiftRightParts - Lower SRA_PARTS, which returns two | |||
5268 | /// i32 values and take a 2 x i32 value to shift plus a shift amount. | |||
5269 | SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, | |||
5270 | SelectionDAG &DAG) const { | |||
5271 | assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5271, __PRETTY_FUNCTION__)); | |||
5272 | EVT VT = Op.getValueType(); | |||
5273 | unsigned VTBits = VT.getSizeInBits(); | |||
5274 | SDLoc dl(Op); | |||
5275 | SDValue ShOpLo = Op.getOperand(0); | |||
5276 | SDValue ShOpHi = Op.getOperand(1); | |||
5277 | SDValue ShAmt = Op.getOperand(2); | |||
5278 | SDValue ARMcc; | |||
5279 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
5280 | unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; | |||
5281 | ||||
5282 | assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD:: SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5282, __PRETTY_FUNCTION__)); | |||
5283 | ||||
5284 | SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, | |||
5285 | DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); | |||
5286 | SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); | |||
5287 | SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, | |||
5288 | DAG.getConstant(VTBits, dl, MVT::i32)); | |||
5289 | SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); | |||
5290 | SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); | |||
5291 | SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); | |||
5292 | SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), | |||
5293 | ISD::SETGE, ARMcc, DAG, dl); | |||
5294 | SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift, | |||
5295 | ARMcc, CCR, CmpLo); | |||
5296 | ||||
5297 | SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); | |||
5298 | SDValue HiBigShift = Opc == ISD::SRA | |||
5299 | ? DAG.getNode(Opc, dl, VT, ShOpHi, | |||
5300 | DAG.getConstant(VTBits - 1, dl, VT)) | |||
5301 | : DAG.getConstant(0, dl, VT); | |||
5302 | SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), | |||
5303 | ISD::SETGE, ARMcc, DAG, dl); | |||
5304 | SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift, | |||
5305 | ARMcc, CCR, CmpHi); | |||
5306 | ||||
5307 | SDValue Ops[2] = { Lo, Hi }; | |||
5308 | return DAG.getMergeValues(Ops, dl); | |||
5309 | } | |||
5310 | ||||
5311 | /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two | |||
5312 | /// i32 values and take a 2 x i32 value to shift plus a shift amount. | |||
5313 | SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, | |||
5314 | SelectionDAG &DAG) const { | |||
5315 | assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5315, __PRETTY_FUNCTION__)); | |||
5316 | EVT VT = Op.getValueType(); | |||
5317 | unsigned VTBits = VT.getSizeInBits(); | |||
5318 | SDLoc dl(Op); | |||
5319 | SDValue ShOpLo = Op.getOperand(0); | |||
5320 | SDValue ShOpHi = Op.getOperand(1); | |||
5321 | SDValue ShAmt = Op.getOperand(2); | |||
5322 | SDValue ARMcc; | |||
5323 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
5324 | ||||
5325 | assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5325, __PRETTY_FUNCTION__)); | |||
5326 | SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, | |||
5327 | DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); | |||
5328 | SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); | |||
5329 | SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); | |||
5330 | SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); | |||
5331 | ||||
5332 | SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, | |||
5333 | DAG.getConstant(VTBits, dl, MVT::i32)); | |||
5334 | SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); | |||
5335 | SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), | |||
5336 | ISD::SETGE, ARMcc, DAG, dl); | |||
5337 | SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift, | |||
5338 | ARMcc, CCR, CmpHi); | |||
5339 | ||||
5340 | SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), | |||
5341 | ISD::SETGE, ARMcc, DAG, dl); | |||
5342 | SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); | |||
5343 | SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, | |||
5344 | DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo); | |||
5345 | ||||
5346 | SDValue Ops[2] = { Lo, Hi }; | |||
5347 | return DAG.getMergeValues(Ops, dl); | |||
5348 | } | |||
5349 | ||||
5350 | SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, | |||
5351 | SelectionDAG &DAG) const { | |||
5352 | // The rounding mode is in bits 23:22 of the FPSCR. | |||
5353 | // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 | |||
5354 | // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) | |||
5355 | // so that the shift + and get folded into a bitfield extract. | |||
5356 | SDLoc dl(Op); | |||
5357 | SDValue Ops[] = { DAG.getEntryNode(), | |||
5358 | DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) }; | |||
5359 | ||||
5360 | SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops); | |||
5361 | SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, | |||
5362 | DAG.getConstant(1U << 22, dl, MVT::i32)); | |||
5363 | SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, | |||
5364 | DAG.getConstant(22, dl, MVT::i32)); | |||
5365 | return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, | |||
5366 | DAG.getConstant(3, dl, MVT::i32)); | |||
5367 | } | |||
5368 | ||||
5369 | static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, | |||
5370 | const ARMSubtarget *ST) { | |||
5371 | SDLoc dl(N); | |||
5372 | EVT VT = N->getValueType(0); | |||
5373 | if (VT.isVector()) { | |||
5374 | assert(ST->hasNEON())((ST->hasNEON()) ? static_cast<void> (0) : __assert_fail ("ST->hasNEON()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5374, __PRETTY_FUNCTION__)); | |||
5375 | ||||
5376 | // Compute the least significant set bit: LSB = X & -X | |||
5377 | SDValue X = N->getOperand(0); | |||
5378 | SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X); | |||
5379 | SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX); | |||
5380 | ||||
5381 | EVT ElemTy = VT.getVectorElementType(); | |||
5382 | ||||
5383 | if (ElemTy == MVT::i8) { | |||
5384 | // Compute with: cttz(x) = ctpop(lsb - 1) | |||
5385 | SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT, | |||
5386 | DAG.getTargetConstant(1, dl, ElemTy)); | |||
5387 | SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One); | |||
5388 | return DAG.getNode(ISD::CTPOP, dl, VT, Bits); | |||
5389 | } | |||
5390 | ||||
5391 | if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) && | |||
5392 | (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) { | |||
5393 | // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0 | |||
5394 | unsigned NumBits = ElemTy.getSizeInBits(); | |||
5395 | SDValue WidthMinus1 = | |||
5396 | DAG.getNode(ARMISD::VMOVIMM, dl, VT, | |||
5397 | DAG.getTargetConstant(NumBits - 1, dl, ElemTy)); | |||
5398 | SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); | |||
5399 | return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ); | |||
5400 | } | |||
5401 | ||||
5402 | // Compute with: cttz(x) = ctpop(lsb - 1) | |||
5403 | ||||
5404 | // Compute LSB - 1. | |||
5405 | SDValue Bits; | |||
5406 | if (ElemTy == MVT::i64) { | |||
5407 | // Load constant 0xffff'ffff'ffff'ffff to register. | |||
5408 | SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT, | |||
5409 | DAG.getTargetConstant(0x1eff, dl, MVT::i32)); | |||
5410 | Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF); | |||
5411 | } else { | |||
5412 | SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT, | |||
5413 | DAG.getTargetConstant(1, dl, ElemTy)); | |||
5414 | Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One); | |||
5415 | } | |||
5416 | return DAG.getNode(ISD::CTPOP, dl, VT, Bits); | |||
5417 | } | |||
5418 | ||||
5419 | if (!ST->hasV6T2Ops()) | |||
5420 | return SDValue(); | |||
5421 | ||||
5422 | SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0)); | |||
5423 | return DAG.getNode(ISD::CTLZ, dl, VT, rbit); | |||
5424 | } | |||
5425 | ||||
5426 | static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG, | |||
5427 | const ARMSubtarget *ST) { | |||
5428 | EVT VT = N->getValueType(0); | |||
5429 | SDLoc DL(N); | |||
5430 | ||||
5431 | assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")((ST->hasNEON() && "Custom ctpop lowering requires NEON." ) ? static_cast<void> (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5431, __PRETTY_FUNCTION__)); | |||
5432 | assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering") ? static_cast< void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5434, __PRETTY_FUNCTION__)) | |||
5433 | VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering") ? static_cast< void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5434, __PRETTY_FUNCTION__)) | |||
5434 | "Unexpected type for custom ctpop lowering")(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering") ? static_cast< void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5434, __PRETTY_FUNCTION__)); | |||
5435 | ||||
5436 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
5437 | EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; | |||
5438 | SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0)); | |||
5439 | Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res); | |||
5440 | ||||
5441 | // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds. | |||
5442 | unsigned EltSize = 8; | |||
5443 | unsigned NumElts = VT.is64BitVector() ? 8 : 16; | |||
5444 | while (EltSize != VT.getScalarSizeInBits()) { | |||
5445 | SmallVector<SDValue, 8> Ops; | |||
5446 | Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddlu, DL, | |||
5447 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
5448 | Ops.push_back(Res); | |||
5449 | ||||
5450 | EltSize *= 2; | |||
5451 | NumElts /= 2; | |||
5452 | MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); | |||
5453 | Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops); | |||
5454 | } | |||
5455 | ||||
5456 | return Res; | |||
5457 | } | |||
5458 | ||||
5459 | static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, | |||
5460 | const ARMSubtarget *ST) { | |||
5461 | EVT VT = N->getValueType(0); | |||
5462 | SDLoc dl(N); | |||
5463 | ||||
5464 | if (!VT.isVector()) | |||
5465 | return SDValue(); | |||
5466 | ||||
5467 | // Lower vector shifts on NEON to use VSHL. | |||
5468 | assert(ST->hasNEON() && "unexpected vector shift")((ST->hasNEON() && "unexpected vector shift") ? static_cast <void> (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5468, __PRETTY_FUNCTION__)); | |||
5469 | ||||
5470 | // Left shifts translate directly to the vshiftu intrinsic. | |||
5471 | if (N->getOpcode() == ISD::SHL) | |||
5472 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, | |||
5473 | DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl, | |||
5474 | MVT::i32), | |||
5475 | N->getOperand(0), N->getOperand(1)); | |||
5476 | ||||
5477 | assert((N->getOpcode() == ISD::SRA ||(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD:: SRL) && "unexpected vector shift opcode") ? static_cast <void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5478, __PRETTY_FUNCTION__)) | |||
5478 | N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD:: SRL) && "unexpected vector shift opcode") ? static_cast <void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5478, __PRETTY_FUNCTION__)); | |||
5479 | ||||
5480 | // NEON uses the same intrinsics for both left and right shifts. For | |||
5481 | // right shifts, the shift amounts are negative, so negate the vector of | |||
5482 | // shift amounts. | |||
5483 | EVT ShiftVT = N->getOperand(1).getValueType(); | |||
5484 | SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, | |||
5485 | getZeroVector(ShiftVT, DAG, dl), | |||
5486 | N->getOperand(1)); | |||
5487 | Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? | |||
5488 | Intrinsic::arm_neon_vshifts : | |||
5489 | Intrinsic::arm_neon_vshiftu); | |||
5490 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, | |||
5491 | DAG.getConstant(vshiftInt, dl, MVT::i32), | |||
5492 | N->getOperand(0), NegatedCount); | |||
5493 | } | |||
5494 | ||||
5495 | static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, | |||
5496 | const ARMSubtarget *ST) { | |||
5497 | EVT VT = N->getValueType(0); | |||
5498 | SDLoc dl(N); | |||
5499 | ||||
5500 | // We can get here for a node like i32 = ISD::SHL i32, i64 | |||
5501 | if (VT != MVT::i64) | |||
5502 | return SDValue(); | |||
5503 | ||||
5504 | assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD:: SRA) && "Unknown shift to lower!") ? static_cast<void > (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5505, __PRETTY_FUNCTION__)) | |||
5505 | "Unknown shift to lower!")(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD:: SRA) && "Unknown shift to lower!") ? static_cast<void > (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5505, __PRETTY_FUNCTION__)); | |||
5506 | ||||
5507 | // We only lower SRA, SRL of 1 here, all others use generic lowering. | |||
5508 | if (!isOneConstant(N->getOperand(1))) | |||
5509 | return SDValue(); | |||
5510 | ||||
5511 | // If we are in thumb mode, we don't have RRX. | |||
5512 | if (ST->isThumb1Only()) return SDValue(); | |||
5513 | ||||
5514 | // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. | |||
5515 | SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), | |||
5516 | DAG.getConstant(0, dl, MVT::i32)); | |||
5517 | SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), | |||
5518 | DAG.getConstant(1, dl, MVT::i32)); | |||
5519 | ||||
5520 | // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and | |||
5521 | // captures the result into a carry flag. | |||
5522 | unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; | |||
5523 | Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi); | |||
5524 | ||||
5525 | // The low part is an ARMISD::RRX operand, which shifts the carry in. | |||
5526 | Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); | |||
5527 | ||||
5528 | // Merge the pieces into a single i64 value. | |||
5529 | return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); | |||
5530 | } | |||
5531 | ||||
5532 | static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { | |||
5533 | SDValue TmpOp0, TmpOp1; | |||
5534 | bool Invert = false; | |||
5535 | bool Swap = false; | |||
5536 | unsigned Opc = 0; | |||
5537 | ||||
5538 | SDValue Op0 = Op.getOperand(0); | |||
5539 | SDValue Op1 = Op.getOperand(1); | |||
5540 | SDValue CC = Op.getOperand(2); | |||
5541 | EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger(); | |||
5542 | EVT VT = Op.getValueType(); | |||
5543 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); | |||
5544 | SDLoc dl(Op); | |||
5545 | ||||
5546 | if (Op0.getValueType().getVectorElementType() == MVT::i64 && | |||
5547 | (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) { | |||
5548 | // Special-case integer 64-bit equality comparisons. They aren't legal, | |||
5549 | // but they can be lowered with a few vector instructions. | |||
5550 | unsigned CmpElements = CmpVT.getVectorNumElements() * 2; | |||
5551 | EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements); | |||
5552 | SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0); | |||
5553 | SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1); | |||
5554 | SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1, | |||
5555 | DAG.getCondCode(ISD::SETEQ)); | |||
5556 | SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); | |||
5557 | SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed); | |||
5558 | Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged); | |||
5559 | if (SetCCOpcode == ISD::SETNE) | |||
5560 | Merged = DAG.getNOT(dl, Merged, CmpVT); | |||
5561 | Merged = DAG.getSExtOrTrunc(Merged, dl, VT); | |||
5562 | return Merged; | |||
5563 | } | |||
5564 | ||||
5565 | if (CmpVT.getVectorElementType() == MVT::i64) | |||
5566 | // 64-bit comparisons are not legal in general. | |||
5567 | return SDValue(); | |||
5568 | ||||
5569 | if (Op1.getValueType().isFloatingPoint()) { | |||
5570 | switch (SetCCOpcode) { | |||
5571 | default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5571); | |||
5572 | case ISD::SETUNE: | |||
5573 | case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5574 | case ISD::SETOEQ: | |||
5575 | case ISD::SETEQ: Opc = ARMISD::VCEQ; break; | |||
5576 | case ISD::SETOLT: | |||
5577 | case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5578 | case ISD::SETOGT: | |||
5579 | case ISD::SETGT: Opc = ARMISD::VCGT; break; | |||
5580 | case ISD::SETOLE: | |||
5581 | case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5582 | case ISD::SETOGE: | |||
5583 | case ISD::SETGE: Opc = ARMISD::VCGE; break; | |||
5584 | case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5585 | case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; | |||
5586 | case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5587 | case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; | |||
5588 | case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5589 | case ISD::SETONE: | |||
5590 | // Expand this to (OLT | OGT). | |||
5591 | TmpOp0 = Op0; | |||
5592 | TmpOp1 = Op1; | |||
5593 | Opc = ISD::OR; | |||
5594 | Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); | |||
5595 | Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); | |||
5596 | break; | |||
5597 | case ISD::SETUO: | |||
5598 | Invert = true; | |||
5599 | LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5600 | case ISD::SETO: | |||
5601 | // Expand this to (OLT | OGE). | |||
5602 | TmpOp0 = Op0; | |||
5603 | TmpOp1 = Op1; | |||
5604 | Opc = ISD::OR; | |||
5605 | Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); | |||
5606 | Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); | |||
5607 | break; | |||
5608 | } | |||
5609 | } else { | |||
5610 | // Integer comparisons. | |||
5611 | switch (SetCCOpcode) { | |||
5612 | default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5612); | |||
5613 | case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5614 | case ISD::SETEQ: Opc = ARMISD::VCEQ; break; | |||
5615 | case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5616 | case ISD::SETGT: Opc = ARMISD::VCGT; break; | |||
5617 | case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5618 | case ISD::SETGE: Opc = ARMISD::VCGE; break; | |||
5619 | case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5620 | case ISD::SETUGT: Opc = ARMISD::VCGTU; break; | |||
5621 | case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
5622 | case ISD::SETUGE: Opc = ARMISD::VCGEU; break; | |||
5623 | } | |||
5624 | ||||
5625 | // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). | |||
5626 | if (Opc == ARMISD::VCEQ) { | |||
5627 | SDValue AndOp; | |||
5628 | if (ISD::isBuildVectorAllZeros(Op1.getNode())) | |||
5629 | AndOp = Op0; | |||
5630 | else if (ISD::isBuildVectorAllZeros(Op0.getNode())) | |||
5631 | AndOp = Op1; | |||
5632 | ||||
5633 | // Ignore bitconvert. | |||
5634 | if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) | |||
5635 | AndOp = AndOp.getOperand(0); | |||
5636 | ||||
5637 | if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { | |||
5638 | Opc = ARMISD::VTST; | |||
5639 | Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); | |||
5640 | Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); | |||
5641 | Invert = !Invert; | |||
5642 | } | |||
5643 | } | |||
5644 | } | |||
5645 | ||||
5646 | if (Swap) | |||
5647 | std::swap(Op0, Op1); | |||
5648 | ||||
5649 | // If one of the operands is a constant vector zero, attempt to fold the | |||
5650 | // comparison to a specialized compare-against-zero form. | |||
5651 | SDValue SingleOp; | |||
5652 | if (ISD::isBuildVectorAllZeros(Op1.getNode())) | |||
5653 | SingleOp = Op0; | |||
5654 | else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { | |||
5655 | if (Opc == ARMISD::VCGE) | |||
5656 | Opc = ARMISD::VCLEZ; | |||
5657 | else if (Opc == ARMISD::VCGT) | |||
5658 | Opc = ARMISD::VCLTZ; | |||
5659 | SingleOp = Op1; | |||
5660 | } | |||
5661 | ||||
5662 | SDValue Result; | |||
5663 | if (SingleOp.getNode()) { | |||
5664 | switch (Opc) { | |||
5665 | case ARMISD::VCEQ: | |||
5666 | Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break; | |||
5667 | case ARMISD::VCGE: | |||
5668 | Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break; | |||
5669 | case ARMISD::VCLEZ: | |||
5670 | Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break; | |||
5671 | case ARMISD::VCGT: | |||
5672 | Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break; | |||
5673 | case ARMISD::VCLTZ: | |||
5674 | Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break; | |||
5675 | default: | |||
5676 | Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1); | |||
5677 | } | |||
5678 | } else { | |||
5679 | Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1); | |||
5680 | } | |||
5681 | ||||
5682 | Result = DAG.getSExtOrTrunc(Result, dl, VT); | |||
5683 | ||||
5684 | if (Invert) | |||
5685 | Result = DAG.getNOT(dl, Result, VT); | |||
5686 | ||||
5687 | return Result; | |||
5688 | } | |||
5689 | ||||
5690 | static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) { | |||
5691 | SDValue LHS = Op.getOperand(0); | |||
5692 | SDValue RHS = Op.getOperand(1); | |||
5693 | SDValue Carry = Op.getOperand(2); | |||
5694 | SDValue Cond = Op.getOperand(3); | |||
5695 | SDLoc DL(Op); | |||
5696 | ||||
5697 | assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.")((LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only." ) ? static_cast<void> (0) : __assert_fail ("LHS.getSimpleValueType().isInteger() && \"SETCCCARRY is integer only.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5697, __PRETTY_FUNCTION__)); | |||
5698 | ||||
5699 | // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we | |||
5700 | // have to invert the carry first. | |||
5701 | Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, | |||
5702 | DAG.getConstant(1, DL, MVT::i32), Carry); | |||
5703 | // This converts the boolean value carry into the carry flag. | |||
5704 | Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG); | |||
5705 | ||||
5706 | SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); | |||
5707 | SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry); | |||
5708 | ||||
5709 | SDValue FVal = DAG.getConstant(0, DL, MVT::i32); | |||
5710 | SDValue TVal = DAG.getConstant(1, DL, MVT::i32); | |||
5711 | SDValue ARMcc = DAG.getConstant( | |||
5712 | IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32); | |||
5713 | SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); | |||
5714 | SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR, | |||
5715 | Cmp.getValue(1), SDValue()); | |||
5716 | return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc, | |||
5717 | CCR, Chain.getValue(1)); | |||
5718 | } | |||
5719 | ||||
5720 | /// isNEONModifiedImm - Check if the specified splat value corresponds to a | |||
5721 | /// valid vector constant for a NEON instruction with a "modified immediate" | |||
5722 | /// operand (e.g., VMOV). If so, return the encoded value. | |||
5723 | static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, | |||
5724 | unsigned SplatBitSize, SelectionDAG &DAG, | |||
5725 | const SDLoc &dl, EVT &VT, bool is128Bits, | |||
5726 | NEONModImmType type) { | |||
5727 | unsigned OpCmode, Imm; | |||
5728 | ||||
5729 | // SplatBitSize is set to the smallest size that splats the vector, so a | |||
5730 | // zero vector will always have SplatBitSize == 8. However, NEON modified | |||
5731 | // immediate instructions others than VMOV do not support the 8-bit encoding | |||
5732 | // of a zero vector, and the default encoding of zero is supposed to be the | |||
5733 | // 32-bit version. | |||
5734 | if (SplatBits == 0) | |||
5735 | SplatBitSize = 32; | |||
5736 | ||||
5737 | switch (SplatBitSize) { | |||
5738 | case 8: | |||
5739 | if (type != VMOVModImm) | |||
5740 | return SDValue(); | |||
5741 | // Any 1-byte value is OK. Op=0, Cmode=1110. | |||
5742 | assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(((SplatBits & ~0xff) == 0 && "one byte splat value is too big" ) ? static_cast<void> (0) : __assert_fail ("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5742, __PRETTY_FUNCTION__)); | |||
5743 | OpCmode = 0xe; | |||
5744 | Imm = SplatBits; | |||
5745 | VT = is128Bits ? MVT::v16i8 : MVT::v8i8; | |||
5746 | break; | |||
5747 | ||||
5748 | case 16: | |||
5749 | // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. | |||
5750 | VT = is128Bits ? MVT::v8i16 : MVT::v4i16; | |||
5751 | if ((SplatBits & ~0xff) == 0) { | |||
5752 | // Value = 0x00nn: Op=x, Cmode=100x. | |||
5753 | OpCmode = 0x8; | |||
5754 | Imm = SplatBits; | |||
5755 | break; | |||
5756 | } | |||
5757 | if ((SplatBits & ~0xff00) == 0) { | |||
5758 | // Value = 0xnn00: Op=x, Cmode=101x. | |||
5759 | OpCmode = 0xa; | |||
5760 | Imm = SplatBits >> 8; | |||
5761 | break; | |||
5762 | } | |||
5763 | return SDValue(); | |||
5764 | ||||
5765 | case 32: | |||
5766 | // NEON's 32-bit VMOV supports splat values where: | |||
5767 | // * only one byte is nonzero, or | |||
5768 | // * the least significant byte is 0xff and the second byte is nonzero, or | |||
5769 | // * the least significant 2 bytes are 0xff and the third is nonzero. | |||
5770 | VT = is128Bits ? MVT::v4i32 : MVT::v2i32; | |||
5771 | if ((SplatBits & ~0xff) == 0) { | |||
5772 | // Value = 0x000000nn: Op=x, Cmode=000x. | |||
5773 | OpCmode = 0; | |||
5774 | Imm = SplatBits; | |||
5775 | break; | |||
5776 | } | |||
5777 | if ((SplatBits & ~0xff00) == 0) { | |||
5778 | // Value = 0x0000nn00: Op=x, Cmode=001x. | |||
5779 | OpCmode = 0x2; | |||
5780 | Imm = SplatBits >> 8; | |||
5781 | break; | |||
5782 | } | |||
5783 | if ((SplatBits & ~0xff0000) == 0) { | |||
5784 | // Value = 0x00nn0000: Op=x, Cmode=010x. | |||
5785 | OpCmode = 0x4; | |||
5786 | Imm = SplatBits >> 16; | |||
5787 | break; | |||
5788 | } | |||
5789 | if ((SplatBits & ~0xff000000) == 0) { | |||
5790 | // Value = 0xnn000000: Op=x, Cmode=011x. | |||
5791 | OpCmode = 0x6; | |||
5792 | Imm = SplatBits >> 24; | |||
5793 | break; | |||
5794 | } | |||
5795 | ||||
5796 | // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC | |||
5797 | if (type == OtherModImm) return SDValue(); | |||
5798 | ||||
5799 | if ((SplatBits & ~0xffff) == 0 && | |||
5800 | ((SplatBits | SplatUndef) & 0xff) == 0xff) { | |||
5801 | // Value = 0x0000nnff: Op=x, Cmode=1100. | |||
5802 | OpCmode = 0xc; | |||
5803 | Imm = SplatBits >> 8; | |||
5804 | break; | |||
5805 | } | |||
5806 | ||||
5807 | if ((SplatBits & ~0xffffff) == 0 && | |||
5808 | ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { | |||
5809 | // Value = 0x00nnffff: Op=x, Cmode=1101. | |||
5810 | OpCmode = 0xd; | |||
5811 | Imm = SplatBits >> 16; | |||
5812 | break; | |||
5813 | } | |||
5814 | ||||
5815 | // Note: there are a few 32-bit splat values (specifically: 00ffff00, | |||
5816 | // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not | |||
5817 | // VMOV.I32. A (very) minor optimization would be to replicate the value | |||
5818 | // and fall through here to test for a valid 64-bit splat. But, then the | |||
5819 | // caller would also need to check and handle the change in size. | |||
5820 | return SDValue(); | |||
5821 | ||||
5822 | case 64: { | |||
5823 | if (type != VMOVModImm) | |||
5824 | return SDValue(); | |||
5825 | // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. | |||
5826 | uint64_t BitMask = 0xff; | |||
5827 | uint64_t Val = 0; | |||
5828 | unsigned ImmMask = 1; | |||
5829 | Imm = 0; | |||
5830 | for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { | |||
5831 | if (((SplatBits | SplatUndef) & BitMask) == BitMask) { | |||
5832 | Val |= BitMask; | |||
5833 | Imm |= ImmMask; | |||
5834 | } else if ((SplatBits & BitMask) != 0) { | |||
5835 | return SDValue(); | |||
5836 | } | |||
5837 | BitMask <<= 8; | |||
5838 | ImmMask <<= 1; | |||
5839 | } | |||
5840 | ||||
5841 | if (DAG.getDataLayout().isBigEndian()) | |||
5842 | // swap higher and lower 32 bit word | |||
5843 | Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4); | |||
5844 | ||||
5845 | // Op=1, Cmode=1110. | |||
5846 | OpCmode = 0x1e; | |||
5847 | VT = is128Bits ? MVT::v2i64 : MVT::v1i64; | |||
5848 | break; | |||
5849 | } | |||
5850 | ||||
5851 | default: | |||
5852 | llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5852); | |||
5853 | } | |||
5854 | ||||
5855 | unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); | |||
5856 | return DAG.getTargetConstant(EncodedVal, dl, MVT::i32); | |||
5857 | } | |||
5858 | ||||
5859 | SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG, | |||
5860 | const ARMSubtarget *ST) const { | |||
5861 | EVT VT = Op.getValueType(); | |||
5862 | bool IsDouble = (VT == MVT::f64); | |||
5863 | ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op); | |||
5864 | const APFloat &FPVal = CFP->getValueAPF(); | |||
5865 | ||||
5866 | // Prevent floating-point constants from using literal loads | |||
5867 | // when execute-only is enabled. | |||
5868 | if (ST->genExecuteOnly()) { | |||
5869 | // If we can represent the constant as an immediate, don't lower it | |||
5870 | if (isFPImmLegal(FPVal, VT)) | |||
5871 | return Op; | |||
5872 | // Otherwise, construct as integer, and move to float register | |||
5873 | APInt INTVal = FPVal.bitcastToAPInt(); | |||
5874 | SDLoc DL(CFP); | |||
5875 | switch (VT.getSimpleVT().SimpleTy) { | |||
5876 | default: | |||
5877 | llvm_unreachable("Unknown floating point type!")::llvm::llvm_unreachable_internal("Unknown floating point type!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 5877); | |||
5878 | break; | |||
5879 | case MVT::f64: { | |||
5880 | SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32); | |||
5881 | SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32); | |||
5882 | if (!ST->isLittle()) | |||
5883 | std::swap(Lo, Hi); | |||
5884 | return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); | |||
5885 | } | |||
5886 | case MVT::f32: | |||
5887 | return DAG.getNode(ARMISD::VMOVSR, DL, VT, | |||
5888 | DAG.getConstant(INTVal, DL, MVT::i32)); | |||
5889 | } | |||
5890 | } | |||
5891 | ||||
5892 | if (!ST->hasVFP3()) | |||
5893 | return SDValue(); | |||
5894 | ||||
5895 | // Use the default (constant pool) lowering for double constants when we have | |||
5896 | // an SP-only FPU | |||
5897 | if (IsDouble && Subtarget->isFPOnlySP()) | |||
5898 | return SDValue(); | |||
5899 | ||||
5900 | // Try splatting with a VMOV.f32... | |||
5901 | int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal); | |||
5902 | ||||
5903 | if (ImmVal != -1) { | |||
5904 | if (IsDouble || !ST->useNEONForSinglePrecisionFP()) { | |||
5905 | // We have code in place to select a valid ConstantFP already, no need to | |||
5906 | // do any mangling. | |||
5907 | return Op; | |||
5908 | } | |||
5909 | ||||
5910 | // It's a float and we are trying to use NEON operations where | |||
5911 | // possible. Lower it to a splat followed by an extract. | |||
5912 | SDLoc DL(Op); | |||
5913 | SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32); | |||
5914 | SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32, | |||
5915 | NewVal); | |||
5916 | return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant, | |||
5917 | DAG.getConstant(0, DL, MVT::i32)); | |||
5918 | } | |||
5919 | ||||
5920 | // The rest of our options are NEON only, make sure that's allowed before | |||
5921 | // proceeding.. | |||
5922 | if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP())) | |||
5923 | return SDValue(); | |||
5924 | ||||
5925 | EVT VMovVT; | |||
5926 | uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue(); | |||
5927 | ||||
5928 | // It wouldn't really be worth bothering for doubles except for one very | |||
5929 | // important value, which does happen to match: 0.0. So make sure we don't do | |||
5930 | // anything stupid. | |||
5931 | if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32)) | |||
5932 | return SDValue(); | |||
5933 | ||||
5934 | // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too). | |||
5935 | SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), | |||
5936 | VMovVT, false, VMOVModImm); | |||
5937 | if (NewVal != SDValue()) { | |||
5938 | SDLoc DL(Op); | |||
5939 | SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT, | |||
5940 | NewVal); | |||
5941 | if (IsDouble) | |||
5942 | return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); | |||
5943 | ||||
5944 | // It's a float: cast and extract a vector element. | |||
5945 | SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, | |||
5946 | VecConstant); | |||
5947 | return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, | |||
5948 | DAG.getConstant(0, DL, MVT::i32)); | |||
5949 | } | |||
5950 | ||||
5951 | // Finally, try a VMVN.i32 | |||
5952 | NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT, | |||
5953 | false, VMVNModImm); | |||
5954 | if (NewVal != SDValue()) { | |||
5955 | SDLoc DL(Op); | |||
5956 | SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal); | |||
5957 | ||||
5958 | if (IsDouble) | |||
5959 | return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); | |||
5960 | ||||
5961 | // It's a float: cast and extract a vector element. | |||
5962 | SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, | |||
5963 | VecConstant); | |||
5964 | return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, | |||
5965 | DAG.getConstant(0, DL, MVT::i32)); | |||
5966 | } | |||
5967 | ||||
5968 | return SDValue(); | |||
5969 | } | |||
5970 | ||||
5971 | // check if an VEXT instruction can handle the shuffle mask when the | |||
5972 | // vector sources of the shuffle are the same. | |||
5973 | static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) { | |||
5974 | unsigned NumElts = VT.getVectorNumElements(); | |||
5975 | ||||
5976 | // Assume that the first shuffle index is not UNDEF. Fail if it is. | |||
5977 | if (M[0] < 0) | |||
5978 | return false; | |||
5979 | ||||
5980 | Imm = M[0]; | |||
5981 | ||||
5982 | // If this is a VEXT shuffle, the immediate value is the index of the first | |||
5983 | // element. The other shuffle indices must be the successive elements after | |||
5984 | // the first one. | |||
5985 | unsigned ExpectedElt = Imm; | |||
5986 | for (unsigned i = 1; i < NumElts; ++i) { | |||
5987 | // Increment the expected index. If it wraps around, just follow it | |||
5988 | // back to index zero and keep going. | |||
5989 | ++ExpectedElt; | |||
5990 | if (ExpectedElt == NumElts) | |||
5991 | ExpectedElt = 0; | |||
5992 | ||||
5993 | if (M[i] < 0) continue; // ignore UNDEF indices | |||
5994 | if (ExpectedElt != static_cast<unsigned>(M[i])) | |||
5995 | return false; | |||
5996 | } | |||
5997 | ||||
5998 | return true; | |||
5999 | } | |||
6000 | ||||
6001 | static bool isVEXTMask(ArrayRef<int> M, EVT VT, | |||
6002 | bool &ReverseVEXT, unsigned &Imm) { | |||
6003 | unsigned NumElts = VT.getVectorNumElements(); | |||
6004 | ReverseVEXT = false; | |||
6005 | ||||
6006 | // Assume that the first shuffle index is not UNDEF. Fail if it is. | |||
6007 | if (M[0] < 0) | |||
6008 | return false; | |||
6009 | ||||
6010 | Imm = M[0]; | |||
6011 | ||||
6012 | // If this is a VEXT shuffle, the immediate value is the index of the first | |||
6013 | // element. The other shuffle indices must be the successive elements after | |||
6014 | // the first one. | |||
6015 | unsigned ExpectedElt = Imm; | |||
6016 | for (unsigned i = 1; i < NumElts; ++i) { | |||
6017 | // Increment the expected index. If it wraps around, it may still be | |||
6018 | // a VEXT but the source vectors must be swapped. | |||
6019 | ExpectedElt += 1; | |||
6020 | if (ExpectedElt == NumElts * 2) { | |||
6021 | ExpectedElt = 0; | |||
6022 | ReverseVEXT = true; | |||
6023 | } | |||
6024 | ||||
6025 | if (M[i] < 0) continue; // ignore UNDEF indices | |||
6026 | if (ExpectedElt != static_cast<unsigned>(M[i])) | |||
6027 | return false; | |||
6028 | } | |||
6029 | ||||
6030 | // Adjust the index value if the source operands will be swapped. | |||
6031 | if (ReverseVEXT) | |||
6032 | Imm -= NumElts; | |||
6033 | ||||
6034 | return true; | |||
6035 | } | |||
6036 | ||||
6037 | /// isVREVMask - Check if a vector shuffle corresponds to a VREV | |||
6038 | /// instruction with the specified blocksize. (The order of the elements | |||
6039 | /// within each block of the vector is reversed.) | |||
6040 | static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { | |||
6041 | assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&(((BlockSize==16 || BlockSize==32 || BlockSize==64) && "Only possible block sizes for VREV are: 16, 32, 64") ? static_cast <void> (0) : __assert_fail ("(BlockSize==16 || BlockSize==32 || BlockSize==64) && \"Only possible block sizes for VREV are: 16, 32, 64\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6042, __PRETTY_FUNCTION__)) | |||
6042 | "Only possible block sizes for VREV are: 16, 32, 64")(((BlockSize==16 || BlockSize==32 || BlockSize==64) && "Only possible block sizes for VREV are: 16, 32, 64") ? static_cast <void> (0) : __assert_fail ("(BlockSize==16 || BlockSize==32 || BlockSize==64) && \"Only possible block sizes for VREV are: 16, 32, 64\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6042, __PRETTY_FUNCTION__)); | |||
6043 | ||||
6044 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6045 | if (EltSz == 64) | |||
6046 | return false; | |||
6047 | ||||
6048 | unsigned NumElts = VT.getVectorNumElements(); | |||
6049 | unsigned BlockElts = M[0] + 1; | |||
6050 | // If the first shuffle index is UNDEF, be optimistic. | |||
6051 | if (M[0] < 0) | |||
6052 | BlockElts = BlockSize / EltSz; | |||
6053 | ||||
6054 | if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) | |||
6055 | return false; | |||
6056 | ||||
6057 | for (unsigned i = 0; i < NumElts; ++i) { | |||
6058 | if (M[i] < 0) continue; // ignore UNDEF indices | |||
6059 | if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) | |||
6060 | return false; | |||
6061 | } | |||
6062 | ||||
6063 | return true; | |||
6064 | } | |||
6065 | ||||
6066 | static bool isVTBLMask(ArrayRef<int> M, EVT VT) { | |||
6067 | // We can handle <8 x i8> vector shuffles. If the index in the mask is out of | |||
6068 | // range, then 0 is placed into the resulting vector. So pretty much any mask | |||
6069 | // of 8 elements can work here. | |||
6070 | return VT == MVT::v8i8 && M.size() == 8; | |||
6071 | } | |||
6072 | ||||
6073 | static unsigned SelectPairHalf(unsigned Elements, ArrayRef<int> Mask, | |||
6074 | unsigned Index) { | |||
6075 | if (Mask.size() == Elements * 2) | |||
6076 | return Index / Elements; | |||
6077 | return Mask[Index] == 0 ? 0 : 1; | |||
6078 | } | |||
6079 | ||||
6080 | // Checks whether the shuffle mask represents a vector transpose (VTRN) by | |||
6081 | // checking that pairs of elements in the shuffle mask represent the same index | |||
6082 | // in each vector, incrementing the expected index by 2 at each step. | |||
6083 | // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6] | |||
6084 | // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g} | |||
6085 | // v2={e,f,g,h} | |||
6086 | // WhichResult gives the offset for each element in the mask based on which | |||
6087 | // of the two results it belongs to. | |||
6088 | // | |||
6089 | // The transpose can be represented either as: | |||
6090 | // result1 = shufflevector v1, v2, result1_shuffle_mask | |||
6091 | // result2 = shufflevector v1, v2, result2_shuffle_mask | |||
6092 | // where v1/v2 and the shuffle masks have the same number of elements | |||
6093 | // (here WhichResult (see below) indicates which result is being checked) | |||
6094 | // | |||
6095 | // or as: | |||
6096 | // results = shufflevector v1, v2, shuffle_mask | |||
6097 | // where both results are returned in one vector and the shuffle mask has twice | |||
6098 | // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we | |||
6099 | // want to check the low half and high half of the shuffle mask as if it were | |||
6100 | // the other case | |||
6101 | static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { | |||
6102 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6103 | if (EltSz == 64) | |||
6104 | return false; | |||
6105 | ||||
6106 | unsigned NumElts = VT.getVectorNumElements(); | |||
6107 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6108 | return false; | |||
6109 | ||||
6110 | // If the mask is twice as long as the input vector then we need to check the | |||
6111 | // upper and lower parts of the mask with a matching value for WhichResult | |||
6112 | // FIXME: A mask with only even values will be rejected in case the first | |||
6113 | // element is undefined, e.g. [-1, 4, 2, 6] will be rejected, because only | |||
6114 | // M[0] is used to determine WhichResult | |||
6115 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6116 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6117 | for (unsigned j = 0; j < NumElts; j += 2) { | |||
6118 | if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) || | |||
6119 | (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult)) | |||
6120 | return false; | |||
6121 | } | |||
6122 | } | |||
6123 | ||||
6124 | if (M.size() == NumElts*2) | |||
6125 | WhichResult = 0; | |||
6126 | ||||
6127 | return true; | |||
6128 | } | |||
6129 | ||||
6130 | /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of | |||
6131 | /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". | |||
6132 | /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. | |||
6133 | static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ | |||
6134 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6135 | if (EltSz == 64) | |||
6136 | return false; | |||
6137 | ||||
6138 | unsigned NumElts = VT.getVectorNumElements(); | |||
6139 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6140 | return false; | |||
6141 | ||||
6142 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6143 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6144 | for (unsigned j = 0; j < NumElts; j += 2) { | |||
6145 | if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) || | |||
6146 | (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult)) | |||
6147 | return false; | |||
6148 | } | |||
6149 | } | |||
6150 | ||||
6151 | if (M.size() == NumElts*2) | |||
6152 | WhichResult = 0; | |||
6153 | ||||
6154 | return true; | |||
6155 | } | |||
6156 | ||||
6157 | // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking | |||
6158 | // that the mask elements are either all even and in steps of size 2 or all odd | |||
6159 | // and in steps of size 2. | |||
6160 | // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6] | |||
6161 | // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g} | |||
6162 | // v2={e,f,g,h} | |||
6163 | // Requires similar checks to that of isVTRNMask with | |||
6164 | // respect the how results are returned. | |||
6165 | static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { | |||
6166 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6167 | if (EltSz == 64) | |||
6168 | return false; | |||
6169 | ||||
6170 | unsigned NumElts = VT.getVectorNumElements(); | |||
6171 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6172 | return false; | |||
6173 | ||||
6174 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6175 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6176 | for (unsigned j = 0; j < NumElts; ++j) { | |||
6177 | if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult) | |||
6178 | return false; | |||
6179 | } | |||
6180 | } | |||
6181 | ||||
6182 | if (M.size() == NumElts*2) | |||
6183 | WhichResult = 0; | |||
6184 | ||||
6185 | // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. | |||
6186 | if (VT.is64BitVector() && EltSz == 32) | |||
6187 | return false; | |||
6188 | ||||
6189 | return true; | |||
6190 | } | |||
6191 | ||||
6192 | /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of | |||
6193 | /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". | |||
6194 | /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, | |||
6195 | static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ | |||
6196 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6197 | if (EltSz == 64) | |||
6198 | return false; | |||
6199 | ||||
6200 | unsigned NumElts = VT.getVectorNumElements(); | |||
6201 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6202 | return false; | |||
6203 | ||||
6204 | unsigned Half = NumElts / 2; | |||
6205 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6206 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6207 | for (unsigned j = 0; j < NumElts; j += Half) { | |||
6208 | unsigned Idx = WhichResult; | |||
6209 | for (unsigned k = 0; k < Half; ++k) { | |||
6210 | int MIdx = M[i + j + k]; | |||
6211 | if (MIdx >= 0 && (unsigned) MIdx != Idx) | |||
6212 | return false; | |||
6213 | Idx += 2; | |||
6214 | } | |||
6215 | } | |||
6216 | } | |||
6217 | ||||
6218 | if (M.size() == NumElts*2) | |||
6219 | WhichResult = 0; | |||
6220 | ||||
6221 | // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. | |||
6222 | if (VT.is64BitVector() && EltSz == 32) | |||
6223 | return false; | |||
6224 | ||||
6225 | return true; | |||
6226 | } | |||
6227 | ||||
6228 | // Checks whether the shuffle mask represents a vector zip (VZIP) by checking | |||
6229 | // that pairs of elements of the shufflemask represent the same index in each | |||
6230 | // vector incrementing sequentially through the vectors. | |||
6231 | // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5] | |||
6232 | // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f} | |||
6233 | // v2={e,f,g,h} | |||
6234 | // Requires similar checks to that of isVTRNMask with respect the how results | |||
6235 | // are returned. | |||
6236 | static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { | |||
6237 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6238 | if (EltSz == 64) | |||
6239 | return false; | |||
6240 | ||||
6241 | unsigned NumElts = VT.getVectorNumElements(); | |||
6242 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6243 | return false; | |||
6244 | ||||
6245 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6246 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6247 | unsigned Idx = WhichResult * NumElts / 2; | |||
6248 | for (unsigned j = 0; j < NumElts; j += 2) { | |||
6249 | if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || | |||
6250 | (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts)) | |||
6251 | return false; | |||
6252 | Idx += 1; | |||
6253 | } | |||
6254 | } | |||
6255 | ||||
6256 | if (M.size() == NumElts*2) | |||
6257 | WhichResult = 0; | |||
6258 | ||||
6259 | // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. | |||
6260 | if (VT.is64BitVector() && EltSz == 32) | |||
6261 | return false; | |||
6262 | ||||
6263 | return true; | |||
6264 | } | |||
6265 | ||||
6266 | /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of | |||
6267 | /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". | |||
6268 | /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. | |||
6269 | static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ | |||
6270 | unsigned EltSz = VT.getScalarSizeInBits(); | |||
6271 | if (EltSz == 64) | |||
6272 | return false; | |||
6273 | ||||
6274 | unsigned NumElts = VT.getVectorNumElements(); | |||
6275 | if (M.size() != NumElts && M.size() != NumElts*2) | |||
6276 | return false; | |||
6277 | ||||
6278 | for (unsigned i = 0; i < M.size(); i += NumElts) { | |||
6279 | WhichResult = SelectPairHalf(NumElts, M, i); | |||
6280 | unsigned Idx = WhichResult * NumElts / 2; | |||
6281 | for (unsigned j = 0; j < NumElts; j += 2) { | |||
6282 | if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || | |||
6283 | (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx)) | |||
6284 | return false; | |||
6285 | Idx += 1; | |||
6286 | } | |||
6287 | } | |||
6288 | ||||
6289 | if (M.size() == NumElts*2) | |||
6290 | WhichResult = 0; | |||
6291 | ||||
6292 | // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. | |||
6293 | if (VT.is64BitVector() && EltSz == 32) | |||
6294 | return false; | |||
6295 | ||||
6296 | return true; | |||
6297 | } | |||
6298 | ||||
6299 | /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), | |||
6300 | /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't. | |||
6301 | static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT, | |||
6302 | unsigned &WhichResult, | |||
6303 | bool &isV_UNDEF) { | |||
6304 | isV_UNDEF = false; | |||
6305 | if (isVTRNMask(ShuffleMask, VT, WhichResult)) | |||
6306 | return ARMISD::VTRN; | |||
6307 | if (isVUZPMask(ShuffleMask, VT, WhichResult)) | |||
6308 | return ARMISD::VUZP; | |||
6309 | if (isVZIPMask(ShuffleMask, VT, WhichResult)) | |||
6310 | return ARMISD::VZIP; | |||
6311 | ||||
6312 | isV_UNDEF = true; | |||
6313 | if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) | |||
6314 | return ARMISD::VTRN; | |||
6315 | if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) | |||
6316 | return ARMISD::VUZP; | |||
6317 | if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) | |||
6318 | return ARMISD::VZIP; | |||
6319 | ||||
6320 | return 0; | |||
6321 | } | |||
6322 | ||||
6323 | /// \return true if this is a reverse operation on an vector. | |||
6324 | static bool isReverseMask(ArrayRef<int> M, EVT VT) { | |||
6325 | unsigned NumElts = VT.getVectorNumElements(); | |||
6326 | // Make sure the mask has the right size. | |||
6327 | if (NumElts != M.size()) | |||
6328 | return false; | |||
6329 | ||||
6330 | // Look for <15, ..., 3, -1, 1, 0>. | |||
6331 | for (unsigned i = 0; i != NumElts; ++i) | |||
6332 | if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i)) | |||
6333 | return false; | |||
6334 | ||||
6335 | return true; | |||
6336 | } | |||
6337 | ||||
6338 | // If N is an integer constant that can be moved into a register in one | |||
6339 | // instruction, return an SDValue of such a constant (will become a MOV | |||
6340 | // instruction). Otherwise return null. | |||
6341 | static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, | |||
6342 | const ARMSubtarget *ST, const SDLoc &dl) { | |||
6343 | uint64_t Val; | |||
6344 | if (!isa<ConstantSDNode>(N)) | |||
6345 | return SDValue(); | |||
6346 | Val = cast<ConstantSDNode>(N)->getZExtValue(); | |||
6347 | ||||
6348 | if (ST->isThumb1Only()) { | |||
6349 | if (Val <= 255 || ~Val <= 255) | |||
6350 | return DAG.getConstant(Val, dl, MVT::i32); | |||
6351 | } else { | |||
6352 | if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) | |||
6353 | return DAG.getConstant(Val, dl, MVT::i32); | |||
6354 | } | |||
6355 | return SDValue(); | |||
6356 | } | |||
6357 | ||||
6358 | // If this is a case we can't handle, return null and let the default | |||
6359 | // expansion code take care of it. | |||
6360 | SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, | |||
6361 | const ARMSubtarget *ST) const { | |||
6362 | BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); | |||
6363 | SDLoc dl(Op); | |||
6364 | EVT VT = Op.getValueType(); | |||
6365 | ||||
6366 | APInt SplatBits, SplatUndef; | |||
6367 | unsigned SplatBitSize; | |||
6368 | bool HasAnyUndefs; | |||
6369 | if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { | |||
6370 | if (SplatUndef.isAllOnesValue()) | |||
6371 | return DAG.getUNDEF(VT); | |||
6372 | ||||
6373 | if (SplatBitSize <= 64) { | |||
6374 | // Check if an immediate VMOV works. | |||
6375 | EVT VmovVT; | |||
6376 | SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), | |||
6377 | SplatUndef.getZExtValue(), SplatBitSize, | |||
6378 | DAG, dl, VmovVT, VT.is128BitVector(), | |||
6379 | VMOVModImm); | |||
6380 | if (Val.getNode()) { | |||
6381 | SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); | |||
6382 | return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); | |||
6383 | } | |||
6384 | ||||
6385 | // Try an immediate VMVN. | |||
6386 | uint64_t NegatedImm = (~SplatBits).getZExtValue(); | |||
6387 | Val = isNEONModifiedImm(NegatedImm, | |||
6388 | SplatUndef.getZExtValue(), SplatBitSize, | |||
6389 | DAG, dl, VmovVT, VT.is128BitVector(), | |||
6390 | VMVNModImm); | |||
6391 | if (Val.getNode()) { | |||
6392 | SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); | |||
6393 | return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); | |||
6394 | } | |||
6395 | ||||
6396 | // Use vmov.f32 to materialize other v2f32 and v4f32 splats. | |||
6397 | if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) { | |||
6398 | int ImmVal = ARM_AM::getFP32Imm(SplatBits); | |||
6399 | if (ImmVal != -1) { | |||
6400 | SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32); | |||
6401 | return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val); | |||
6402 | } | |||
6403 | } | |||
6404 | } | |||
6405 | } | |||
6406 | ||||
6407 | // Scan through the operands to see if only one value is used. | |||
6408 | // | |||
6409 | // As an optimisation, even if more than one value is used it may be more | |||
6410 | // profitable to splat with one value then change some lanes. | |||
6411 | // | |||
6412 | // Heuristically we decide to do this if the vector has a "dominant" value, | |||
6413 | // defined as splatted to more than half of the lanes. | |||
6414 | unsigned NumElts = VT.getVectorNumElements(); | |||
6415 | bool isOnlyLowElement = true; | |||
6416 | bool usesOnlyOneValue = true; | |||
6417 | bool hasDominantValue = false; | |||
6418 | bool isConstant = true; | |||
6419 | ||||
6420 | // Map of the number of times a particular SDValue appears in the | |||
6421 | // element list. | |||
6422 | DenseMap<SDValue, unsigned> ValueCounts; | |||
6423 | SDValue Value; | |||
6424 | for (unsigned i = 0; i < NumElts; ++i) { | |||
6425 | SDValue V = Op.getOperand(i); | |||
6426 | if (V.isUndef()) | |||
6427 | continue; | |||
6428 | if (i > 0) | |||
6429 | isOnlyLowElement = false; | |||
6430 | if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) | |||
6431 | isConstant = false; | |||
6432 | ||||
6433 | ValueCounts.insert(std::make_pair(V, 0)); | |||
6434 | unsigned &Count = ValueCounts[V]; | |||
6435 | ||||
6436 | // Is this value dominant? (takes up more than half of the lanes) | |||
6437 | if (++Count > (NumElts / 2)) { | |||
6438 | hasDominantValue = true; | |||
6439 | Value = V; | |||
6440 | } | |||
6441 | } | |||
6442 | if (ValueCounts.size() != 1) | |||
6443 | usesOnlyOneValue = false; | |||
6444 | if (!Value.getNode() && !ValueCounts.empty()) | |||
6445 | Value = ValueCounts.begin()->first; | |||
6446 | ||||
6447 | if (ValueCounts.empty()) | |||
6448 | return DAG.getUNDEF(VT); | |||
6449 | ||||
6450 | // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR. | |||
6451 | // Keep going if we are hitting this case. | |||
6452 | if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode())) | |||
6453 | return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); | |||
6454 | ||||
6455 | unsigned EltSize = VT.getScalarSizeInBits(); | |||
6456 | ||||
6457 | // Use VDUP for non-constant splats. For f32 constant splats, reduce to | |||
6458 | // i32 and try again. | |||
6459 | if (hasDominantValue && EltSize <= 32) { | |||
6460 | if (!isConstant) { | |||
6461 | SDValue N; | |||
6462 | ||||
6463 | // If we are VDUPing a value that comes directly from a vector, that will | |||
6464 | // cause an unnecessary move to and from a GPR, where instead we could | |||
6465 | // just use VDUPLANE. We can only do this if the lane being extracted | |||
6466 | // is at a constant index, as the VDUP from lane instructions only have | |||
6467 | // constant-index forms. | |||
6468 | ConstantSDNode *constIndex; | |||
6469 | if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT && | |||
6470 | (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) { | |||
6471 | // We need to create a new undef vector to use for the VDUPLANE if the | |||
6472 | // size of the vector from which we get the value is different than the | |||
6473 | // size of the vector that we need to create. We will insert the element | |||
6474 | // such that the register coalescer will remove unnecessary copies. | |||
6475 | if (VT != Value->getOperand(0).getValueType()) { | |||
6476 | unsigned index = constIndex->getAPIntValue().getLimitedValue() % | |||
6477 | VT.getVectorNumElements(); | |||
6478 | N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, | |||
6479 | DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), | |||
6480 | Value, DAG.getConstant(index, dl, MVT::i32)), | |||
6481 | DAG.getConstant(index, dl, MVT::i32)); | |||
6482 | } else | |||
6483 | N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, | |||
6484 | Value->getOperand(0), Value->getOperand(1)); | |||
6485 | } else | |||
6486 | N = DAG.getNode(ARMISD::VDUP, dl, VT, Value); | |||
6487 | ||||
6488 | if (!usesOnlyOneValue) { | |||
6489 | // The dominant value was splatted as 'N', but we now have to insert | |||
6490 | // all differing elements. | |||
6491 | for (unsigned I = 0; I < NumElts; ++I) { | |||
6492 | if (Op.getOperand(I) == Value) | |||
6493 | continue; | |||
6494 | SmallVector<SDValue, 3> Ops; | |||
6495 | Ops.push_back(N); | |||
6496 | Ops.push_back(Op.getOperand(I)); | |||
6497 | Ops.push_back(DAG.getConstant(I, dl, MVT::i32)); | |||
6498 | N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); | |||
6499 | } | |||
6500 | } | |||
6501 | return N; | |||
6502 | } | |||
6503 | if (VT.getVectorElementType().isFloatingPoint()) { | |||
6504 | SmallVector<SDValue, 8> Ops; | |||
6505 | for (unsigned i = 0; i < NumElts; ++i) | |||
6506 | Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, | |||
6507 | Op.getOperand(i))); | |||
6508 | EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); | |||
6509 | SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); | |||
6510 | Val = LowerBUILD_VECTOR(Val, DAG, ST); | |||
6511 | if (Val.getNode()) | |||
6512 | return DAG.getNode(ISD::BITCAST, dl, VT, Val); | |||
6513 | } | |||
6514 | if (usesOnlyOneValue) { | |||
6515 | SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); | |||
6516 | if (isConstant && Val.getNode()) | |||
6517 | return DAG.getNode(ARMISD::VDUP, dl, VT, Val); | |||
6518 | } | |||
6519 | } | |||
6520 | ||||
6521 | // If all elements are constants and the case above didn't get hit, fall back | |||
6522 | // to the default expansion, which will generate a load from the constant | |||
6523 | // pool. | |||
6524 | if (isConstant) | |||
6525 | return SDValue(); | |||
6526 | ||||
6527 | // Empirical tests suggest this is rarely worth it for vectors of length <= 2. | |||
6528 | if (NumElts >= 4) { | |||
6529 | SDValue shuffle = ReconstructShuffle(Op, DAG); | |||
6530 | if (shuffle != SDValue()) | |||
6531 | return shuffle; | |||
6532 | } | |||
6533 | ||||
6534 | if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { | |||
6535 | // If we haven't found an efficient lowering, try splitting a 128-bit vector | |||
6536 | // into two 64-bit vectors; we might discover a better way to lower it. | |||
6537 | SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts); | |||
6538 | EVT ExtVT = VT.getVectorElementType(); | |||
6539 | EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElts / 2); | |||
6540 | SDValue Lower = | |||
6541 | DAG.getBuildVector(HVT, dl, makeArrayRef(&Ops[0], NumElts / 2)); | |||
6542 | if (Lower.getOpcode() == ISD::BUILD_VECTOR) | |||
6543 | Lower = LowerBUILD_VECTOR(Lower, DAG, ST); | |||
6544 | SDValue Upper = DAG.getBuildVector( | |||
6545 | HVT, dl, makeArrayRef(&Ops[NumElts / 2], NumElts / 2)); | |||
6546 | if (Upper.getOpcode() == ISD::BUILD_VECTOR) | |||
6547 | Upper = LowerBUILD_VECTOR(Upper, DAG, ST); | |||
6548 | if (Lower && Upper) | |||
6549 | return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); | |||
6550 | } | |||
6551 | ||||
6552 | // Vectors with 32- or 64-bit elements can be built by directly assigning | |||
6553 | // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands | |||
6554 | // will be legalized. | |||
6555 | if (EltSize >= 32) { | |||
6556 | // Do the expansion with floating-point types, since that is what the VFP | |||
6557 | // registers are defined to use, and since i64 is not legal. | |||
6558 | EVT EltVT = EVT::getFloatingPointVT(EltSize); | |||
6559 | EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); | |||
6560 | SmallVector<SDValue, 8> Ops; | |||
6561 | for (unsigned i = 0; i < NumElts; ++i) | |||
6562 | Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); | |||
6563 | SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); | |||
6564 | return DAG.getNode(ISD::BITCAST, dl, VT, Val); | |||
6565 | } | |||
6566 | ||||
6567 | // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we | |||
6568 | // know the default expansion would otherwise fall back on something even | |||
6569 | // worse. For a vector with one or two non-undef values, that's | |||
6570 | // scalar_to_vector for the elements followed by a shuffle (provided the | |||
6571 | // shuffle is valid for the target) and materialization element by element | |||
6572 | // on the stack followed by a load for everything else. | |||
6573 | if (!isConstant && !usesOnlyOneValue) { | |||
6574 | SDValue Vec = DAG.getUNDEF(VT); | |||
6575 | for (unsigned i = 0 ; i < NumElts; ++i) { | |||
6576 | SDValue V = Op.getOperand(i); | |||
6577 | if (V.isUndef()) | |||
6578 | continue; | |||
6579 | SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); | |||
6580 | Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); | |||
6581 | } | |||
6582 | return Vec; | |||
6583 | } | |||
6584 | ||||
6585 | return SDValue(); | |||
6586 | } | |||
6587 | ||||
6588 | // Gather data to see if the operation can be modelled as a | |||
6589 | // shuffle in combination with VEXTs. | |||
6590 | SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, | |||
6591 | SelectionDAG &DAG) const { | |||
6592 | assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!")((Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!" ) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::BUILD_VECTOR && \"Unknown opcode!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6592, __PRETTY_FUNCTION__)); | |||
6593 | SDLoc dl(Op); | |||
6594 | EVT VT = Op.getValueType(); | |||
6595 | unsigned NumElts = VT.getVectorNumElements(); | |||
6596 | ||||
6597 | struct ShuffleSourceInfo { | |||
6598 | SDValue Vec; | |||
6599 | unsigned MinElt = std::numeric_limits<unsigned>::max(); | |||
6600 | unsigned MaxElt = 0; | |||
6601 | ||||
6602 | // We may insert some combination of BITCASTs and VEXT nodes to force Vec to | |||
6603 | // be compatible with the shuffle we intend to construct. As a result | |||
6604 | // ShuffleVec will be some sliding window into the original Vec. | |||
6605 | SDValue ShuffleVec; | |||
6606 | ||||
6607 | // Code should guarantee that element i in Vec starts at element "WindowBase | |||
6608 | // + i * WindowScale in ShuffleVec". | |||
6609 | int WindowBase = 0; | |||
6610 | int WindowScale = 1; | |||
6611 | ||||
6612 | ShuffleSourceInfo(SDValue Vec) : Vec(Vec), ShuffleVec(Vec) {} | |||
6613 | ||||
6614 | bool operator ==(SDValue OtherVec) { return Vec == OtherVec; } | |||
6615 | }; | |||
6616 | ||||
6617 | // First gather all vectors used as an immediate source for this BUILD_VECTOR | |||
6618 | // node. | |||
6619 | SmallVector<ShuffleSourceInfo, 2> Sources; | |||
6620 | for (unsigned i = 0; i < NumElts; ++i) { | |||
6621 | SDValue V = Op.getOperand(i); | |||
6622 | if (V.isUndef()) | |||
6623 | continue; | |||
6624 | else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { | |||
6625 | // A shuffle can only come from building a vector from various | |||
6626 | // elements of other vectors. | |||
6627 | return SDValue(); | |||
6628 | } else if (!isa<ConstantSDNode>(V.getOperand(1))) { | |||
6629 | // Furthermore, shuffles require a constant mask, whereas extractelts | |||
6630 | // accept variable indices. | |||
6631 | return SDValue(); | |||
6632 | } | |||
6633 | ||||
6634 | // Add this element source to the list if it's not already there. | |||
6635 | SDValue SourceVec = V.getOperand(0); | |||
6636 | auto Source = llvm::find(Sources, SourceVec); | |||
6637 | if (Source == Sources.end()) | |||
6638 | Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec)); | |||
6639 | ||||
6640 | // Update the minimum and maximum lane number seen. | |||
6641 | unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); | |||
6642 | Source->MinElt = std::min(Source->MinElt, EltNo); | |||
6643 | Source->MaxElt = std::max(Source->MaxElt, EltNo); | |||
6644 | } | |||
6645 | ||||
6646 | // Currently only do something sane when at most two source vectors | |||
6647 | // are involved. | |||
6648 | if (Sources.size() > 2) | |||
6649 | return SDValue(); | |||
6650 | ||||
6651 | // Find out the smallest element size among result and two sources, and use | |||
6652 | // it as element size to build the shuffle_vector. | |||
6653 | EVT SmallestEltTy = VT.getVectorElementType(); | |||
6654 | for (auto &Source : Sources) { | |||
6655 | EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType(); | |||
6656 | if (SrcEltTy.bitsLT(SmallestEltTy)) | |||
6657 | SmallestEltTy = SrcEltTy; | |||
6658 | } | |||
6659 | unsigned ResMultiplier = | |||
6660 | VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits(); | |||
6661 | NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits(); | |||
6662 | EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts); | |||
6663 | ||||
6664 | // If the source vector is too wide or too narrow, we may nevertheless be able | |||
6665 | // to construct a compatible shuffle either by concatenating it with UNDEF or | |||
6666 | // extracting a suitable range of elements. | |||
6667 | for (auto &Src : Sources) { | |||
6668 | EVT SrcVT = Src.ShuffleVec.getValueType(); | |||
6669 | ||||
6670 | if (SrcVT.getSizeInBits() == VT.getSizeInBits()) | |||
6671 | continue; | |||
6672 | ||||
6673 | // This stage of the search produces a source with the same element type as | |||
6674 | // the original, but with a total width matching the BUILD_VECTOR output. | |||
6675 | EVT EltVT = SrcVT.getVectorElementType(); | |||
6676 | unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits(); | |||
6677 | EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); | |||
6678 | ||||
6679 | if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { | |||
6680 | if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits()) | |||
6681 | return SDValue(); | |||
6682 | // We can pad out the smaller vector for free, so if it's part of a | |||
6683 | // shuffle... | |||
6684 | Src.ShuffleVec = | |||
6685 | DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, | |||
6686 | DAG.getUNDEF(Src.ShuffleVec.getValueType())); | |||
6687 | continue; | |||
6688 | } | |||
6689 | ||||
6690 | if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits()) | |||
6691 | return SDValue(); | |||
6692 | ||||
6693 | if (Src.MaxElt - Src.MinElt >= NumSrcElts) { | |||
6694 | // Span too large for a VEXT to cope | |||
6695 | return SDValue(); | |||
6696 | } | |||
6697 | ||||
6698 | if (Src.MinElt >= NumSrcElts) { | |||
6699 | // The extraction can just take the second half | |||
6700 | Src.ShuffleVec = | |||
6701 | DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, | |||
6702 | DAG.getConstant(NumSrcElts, dl, MVT::i32)); | |||
6703 | Src.WindowBase = -NumSrcElts; | |||
6704 | } else if (Src.MaxElt < NumSrcElts) { | |||
6705 | // The extraction can just take the first half | |||
6706 | Src.ShuffleVec = | |||
6707 | DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, | |||
6708 | DAG.getConstant(0, dl, MVT::i32)); | |||
6709 | } else { | |||
6710 | // An actual VEXT is needed | |||
6711 | SDValue VEXTSrc1 = | |||
6712 | DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, | |||
6713 | DAG.getConstant(0, dl, MVT::i32)); | |||
6714 | SDValue VEXTSrc2 = | |||
6715 | DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, | |||
6716 | DAG.getConstant(NumSrcElts, dl, MVT::i32)); | |||
6717 | ||||
6718 | Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, | |||
6719 | VEXTSrc2, | |||
6720 | DAG.getConstant(Src.MinElt, dl, MVT::i32)); | |||
6721 | Src.WindowBase = -Src.MinElt; | |||
6722 | } | |||
6723 | } | |||
6724 | ||||
6725 | // Another possible incompatibility occurs from the vector element types. We | |||
6726 | // can fix this by bitcasting the source vectors to the same type we intend | |||
6727 | // for the shuffle. | |||
6728 | for (auto &Src : Sources) { | |||
6729 | EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType(); | |||
6730 | if (SrcEltTy == SmallestEltTy) | |||
6731 | continue; | |||
6732 | assert(ShuffleVT.getVectorElementType() == SmallestEltTy)((ShuffleVT.getVectorElementType() == SmallestEltTy) ? static_cast <void> (0) : __assert_fail ("ShuffleVT.getVectorElementType() == SmallestEltTy" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6732, __PRETTY_FUNCTION__)); | |||
6733 | Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec); | |||
6734 | Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits(); | |||
6735 | Src.WindowBase *= Src.WindowScale; | |||
6736 | } | |||
6737 | ||||
6738 | // Final sanity check before we try to actually produce a shuffle. | |||
6739 | LLVM_DEBUG(for (auto Srcdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { for (auto Src : Sources) ((Src.ShuffleVec.getValueType () == ShuffleVT) ? static_cast<void> (0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6741, __PRETTY_FUNCTION__));; } } while (false) | |||
6740 | : Sources)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { for (auto Src : Sources) ((Src.ShuffleVec.getValueType () == ShuffleVT) ? static_cast<void> (0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6741, __PRETTY_FUNCTION__));; } } while (false) | |||
6741 | assert(Src.ShuffleVec.getValueType() == ShuffleVT);)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { for (auto Src : Sources) ((Src.ShuffleVec.getValueType () == ShuffleVT) ? static_cast<void> (0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6741, __PRETTY_FUNCTION__));; } } while (false); | |||
6742 | ||||
6743 | // The stars all align, our next step is to produce the mask for the shuffle. | |||
6744 | SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1); | |||
6745 | int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits(); | |||
6746 | for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { | |||
6747 | SDValue Entry = Op.getOperand(i); | |||
6748 | if (Entry.isUndef()) | |||
6749 | continue; | |||
6750 | ||||
6751 | auto Src = llvm::find(Sources, Entry.getOperand(0)); | |||
6752 | int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue(); | |||
6753 | ||||
6754 | // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit | |||
6755 | // trunc. So only std::min(SrcBits, DestBits) actually get defined in this | |||
6756 | // segment. | |||
6757 | EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType(); | |||
6758 | int BitsDefined = std::min(OrigEltTy.getSizeInBits(), | |||
6759 | VT.getScalarSizeInBits()); | |||
6760 | int LanesDefined = BitsDefined / BitsPerShuffleLane; | |||
6761 | ||||
6762 | // This source is expected to fill ResMultiplier lanes of the final shuffle, | |||
6763 | // starting at the appropriate offset. | |||
6764 | int *LaneMask = &Mask[i * ResMultiplier]; | |||
6765 | ||||
6766 | int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase; | |||
6767 | ExtractBase += NumElts * (Src - Sources.begin()); | |||
6768 | for (int j = 0; j < LanesDefined; ++j) | |||
6769 | LaneMask[j] = ExtractBase + j; | |||
6770 | } | |||
6771 | ||||
6772 | // Final check before we try to produce nonsense... | |||
6773 | if (!isShuffleMaskLegal(Mask, ShuffleVT)) | |||
6774 | return SDValue(); | |||
6775 | ||||
6776 | // We can't handle more than two sources. This should have already | |||
6777 | // been checked before this point. | |||
6778 | assert(Sources.size() <= 2 && "Too many sources!")((Sources.size() <= 2 && "Too many sources!") ? static_cast <void> (0) : __assert_fail ("Sources.size() <= 2 && \"Too many sources!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6778, __PRETTY_FUNCTION__)); | |||
6779 | ||||
6780 | SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) }; | |||
6781 | for (unsigned i = 0; i < Sources.size(); ++i) | |||
6782 | ShuffleOps[i] = Sources[i].ShuffleVec; | |||
6783 | ||||
6784 | SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0], | |||
6785 | ShuffleOps[1], Mask); | |||
6786 | return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); | |||
6787 | } | |||
6788 | ||||
6789 | /// isShuffleMaskLegal - Targets can use this to indicate that they only | |||
6790 | /// support *some* VECTOR_SHUFFLE operations, those with specific masks. | |||
6791 | /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values | |||
6792 | /// are assumed to be legal. | |||
6793 | bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const { | |||
6794 | if (VT.getVectorNumElements() == 4 && | |||
6795 | (VT.is128BitVector() || VT.is64BitVector())) { | |||
6796 | unsigned PFIndexes[4]; | |||
6797 | for (unsigned i = 0; i != 4; ++i) { | |||
6798 | if (M[i] < 0) | |||
6799 | PFIndexes[i] = 8; | |||
6800 | else | |||
6801 | PFIndexes[i] = M[i]; | |||
6802 | } | |||
6803 | ||||
6804 | // Compute the index in the perfect shuffle table. | |||
6805 | unsigned PFTableIndex = | |||
6806 | PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; | |||
6807 | unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; | |||
6808 | unsigned Cost = (PFEntry >> 30); | |||
6809 | ||||
6810 | if (Cost <= 4) | |||
6811 | return true; | |||
6812 | } | |||
6813 | ||||
6814 | bool ReverseVEXT, isV_UNDEF; | |||
6815 | unsigned Imm, WhichResult; | |||
6816 | ||||
6817 | unsigned EltSize = VT.getScalarSizeInBits(); | |||
6818 | return (EltSize >= 32 || | |||
6819 | ShuffleVectorSDNode::isSplatMask(&M[0], VT) || | |||
6820 | isVREVMask(M, VT, 64) || | |||
6821 | isVREVMask(M, VT, 32) || | |||
6822 | isVREVMask(M, VT, 16) || | |||
6823 | isVEXTMask(M, VT, ReverseVEXT, Imm) || | |||
6824 | isVTBLMask(M, VT) || | |||
6825 | isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) || | |||
6826 | ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT))); | |||
6827 | } | |||
6828 | ||||
6829 | /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit | |||
6830 | /// the specified operations to build the shuffle. | |||
6831 | static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, | |||
6832 | SDValue RHS, SelectionDAG &DAG, | |||
6833 | const SDLoc &dl) { | |||
6834 | unsigned OpNum = (PFEntry >> 26) & 0x0F; | |||
6835 | unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); | |||
6836 | unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); | |||
6837 | ||||
6838 | enum { | |||
6839 | OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> | |||
6840 | OP_VREV, | |||
6841 | OP_VDUP0, | |||
6842 | OP_VDUP1, | |||
6843 | OP_VDUP2, | |||
6844 | OP_VDUP3, | |||
6845 | OP_VEXT1, | |||
6846 | OP_VEXT2, | |||
6847 | OP_VEXT3, | |||
6848 | OP_VUZPL, // VUZP, left result | |||
6849 | OP_VUZPR, // VUZP, right result | |||
6850 | OP_VZIPL, // VZIP, left result | |||
6851 | OP_VZIPR, // VZIP, right result | |||
6852 | OP_VTRNL, // VTRN, left result | |||
6853 | OP_VTRNR // VTRN, right result | |||
6854 | }; | |||
6855 | ||||
6856 | if (OpNum == OP_COPY) { | |||
6857 | if (LHSID == (1*9+2)*9+3) return LHS; | |||
6858 | assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!")((LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!") ? static_cast<void> (0) : __assert_fail ("LHSID == ((4*9+5)*9+6)*9+7 && \"Illegal OP_COPY!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6858, __PRETTY_FUNCTION__)); | |||
6859 | return RHS; | |||
6860 | } | |||
6861 | ||||
6862 | SDValue OpLHS, OpRHS; | |||
6863 | OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); | |||
6864 | OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); | |||
6865 | EVT VT = OpLHS.getValueType(); | |||
6866 | ||||
6867 | switch (OpNum) { | |||
6868 | default: llvm_unreachable("Unknown shuffle opcode!")::llvm::llvm_unreachable_internal("Unknown shuffle opcode!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6868); | |||
6869 | case OP_VREV: | |||
6870 | // VREV divides the vector in half and swaps within the half. | |||
6871 | if (VT.getVectorElementType() == MVT::i32 || | |||
6872 | VT.getVectorElementType() == MVT::f32) | |||
6873 | return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); | |||
6874 | // vrev <4 x i16> -> VREV32 | |||
6875 | if (VT.getVectorElementType() == MVT::i16) | |||
6876 | return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); | |||
6877 | // vrev <4 x i8> -> VREV16 | |||
6878 | assert(VT.getVectorElementType() == MVT::i8)((VT.getVectorElementType() == MVT::i8) ? static_cast<void > (0) : __assert_fail ("VT.getVectorElementType() == MVT::i8" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6878, __PRETTY_FUNCTION__)); | |||
6879 | return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); | |||
6880 | case OP_VDUP0: | |||
6881 | case OP_VDUP1: | |||
6882 | case OP_VDUP2: | |||
6883 | case OP_VDUP3: | |||
6884 | return DAG.getNode(ARMISD::VDUPLANE, dl, VT, | |||
6885 | OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32)); | |||
6886 | case OP_VEXT1: | |||
6887 | case OP_VEXT2: | |||
6888 | case OP_VEXT3: | |||
6889 | return DAG.getNode(ARMISD::VEXT, dl, VT, | |||
6890 | OpLHS, OpRHS, | |||
6891 | DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32)); | |||
6892 | case OP_VUZPL: | |||
6893 | case OP_VUZPR: | |||
6894 | return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), | |||
6895 | OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); | |||
6896 | case OP_VZIPL: | |||
6897 | case OP_VZIPR: | |||
6898 | return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), | |||
6899 | OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); | |||
6900 | case OP_VTRNL: | |||
6901 | case OP_VTRNR: | |||
6902 | return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), | |||
6903 | OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); | |||
6904 | } | |||
6905 | } | |||
6906 | ||||
6907 | static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, | |||
6908 | ArrayRef<int> ShuffleMask, | |||
6909 | SelectionDAG &DAG) { | |||
6910 | // Check to see if we can use the VTBL instruction. | |||
6911 | SDValue V1 = Op.getOperand(0); | |||
6912 | SDValue V2 = Op.getOperand(1); | |||
6913 | SDLoc DL(Op); | |||
6914 | ||||
6915 | SmallVector<SDValue, 8> VTBLMask; | |||
6916 | for (ArrayRef<int>::iterator | |||
6917 | I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) | |||
6918 | VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32)); | |||
6919 | ||||
6920 | if (V2.getNode()->isUndef()) | |||
6921 | return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, | |||
6922 | DAG.getBuildVector(MVT::v8i8, DL, VTBLMask)); | |||
6923 | ||||
6924 | return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, | |||
6925 | DAG.getBuildVector(MVT::v8i8, DL, VTBLMask)); | |||
6926 | } | |||
6927 | ||||
6928 | static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op, | |||
6929 | SelectionDAG &DAG) { | |||
6930 | SDLoc DL(Op); | |||
6931 | SDValue OpLHS = Op.getOperand(0); | |||
6932 | EVT VT = OpLHS.getValueType(); | |||
6933 | ||||
6934 | assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&(((VT == MVT::v8i16 || VT == MVT::v16i8) && "Expect an v8i16/v16i8 type" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v8i16 || VT == MVT::v16i8) && \"Expect an v8i16/v16i8 type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6935, __PRETTY_FUNCTION__)) | |||
6935 | "Expect an v8i16/v16i8 type")(((VT == MVT::v8i16 || VT == MVT::v16i8) && "Expect an v8i16/v16i8 type" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v8i16 || VT == MVT::v16i8) && \"Expect an v8i16/v16i8 type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 6935, __PRETTY_FUNCTION__)); | |||
6936 | OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); | |||
6937 | // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now, | |||
6938 | // extract the first 8 bytes into the top double word and the last 8 bytes | |||
6939 | // into the bottom double word. The v8i16 case is similar. | |||
6940 | unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4; | |||
6941 | return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS, | |||
6942 | DAG.getConstant(ExtractNum, DL, MVT::i32)); | |||
6943 | } | |||
6944 | ||||
6945 | static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { | |||
6946 | SDValue V1 = Op.getOperand(0); | |||
6947 | SDValue V2 = Op.getOperand(1); | |||
6948 | SDLoc dl(Op); | |||
6949 | EVT VT = Op.getValueType(); | |||
6950 | ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); | |||
6951 | ||||
6952 | // Convert shuffles that are directly supported on NEON to target-specific | |||
6953 | // DAG nodes, instead of keeping them as shuffles and matching them again | |||
6954 | // during code selection. This is more efficient and avoids the possibility | |||
6955 | // of inconsistencies between legalization and selection. | |||
6956 | // FIXME: floating-point vectors should be canonicalized to integer vectors | |||
6957 | // of the same time so that they get CSEd properly. | |||
6958 | ArrayRef<int> ShuffleMask = SVN->getMask(); | |||
6959 | ||||
6960 | unsigned EltSize = VT.getScalarSizeInBits(); | |||
6961 | if (EltSize <= 32) { | |||
6962 | if (SVN->isSplat()) { | |||
6963 | int Lane = SVN->getSplatIndex(); | |||
6964 | // If this is undef splat, generate it via "just" vdup, if possible. | |||
6965 | if (Lane == -1) Lane = 0; | |||
6966 | ||||
6967 | // Test if V1 is a SCALAR_TO_VECTOR. | |||
6968 | if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { | |||
6969 | return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); | |||
6970 | } | |||
6971 | // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR | |||
6972 | // (and probably will turn into a SCALAR_TO_VECTOR once legalization | |||
6973 | // reaches it). | |||
6974 | if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR && | |||
6975 | !isa<ConstantSDNode>(V1.getOperand(0))) { | |||
6976 | bool IsScalarToVector = true; | |||
6977 | for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) | |||
6978 | if (!V1.getOperand(i).isUndef()) { | |||
6979 | IsScalarToVector = false; | |||
6980 | break; | |||
6981 | } | |||
6982 | if (IsScalarToVector) | |||
6983 | return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); | |||
6984 | } | |||
6985 | return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, | |||
6986 | DAG.getConstant(Lane, dl, MVT::i32)); | |||
6987 | } | |||
6988 | ||||
6989 | bool ReverseVEXT; | |||
6990 | unsigned Imm; | |||
6991 | if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { | |||
6992 | if (ReverseVEXT) | |||
6993 | std::swap(V1, V2); | |||
6994 | return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, | |||
6995 | DAG.getConstant(Imm, dl, MVT::i32)); | |||
6996 | } | |||
6997 | ||||
6998 | if (isVREVMask(ShuffleMask, VT, 64)) | |||
6999 | return DAG.getNode(ARMISD::VREV64, dl, VT, V1); | |||
7000 | if (isVREVMask(ShuffleMask, VT, 32)) | |||
7001 | return DAG.getNode(ARMISD::VREV32, dl, VT, V1); | |||
7002 | if (isVREVMask(ShuffleMask, VT, 16)) | |||
7003 | return DAG.getNode(ARMISD::VREV16, dl, VT, V1); | |||
7004 | ||||
7005 | if (V2->isUndef() && isSingletonVEXTMask(ShuffleMask, VT, Imm)) { | |||
7006 | return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1, | |||
7007 | DAG.getConstant(Imm, dl, MVT::i32)); | |||
7008 | } | |||
7009 | ||||
7010 | // Check for Neon shuffles that modify both input vectors in place. | |||
7011 | // If both results are used, i.e., if there are two shuffles with the same | |||
7012 | // source operands and with masks corresponding to both results of one of | |||
7013 | // these operations, DAG memoization will ensure that a single node is | |||
7014 | // used for both shuffles. | |||
7015 | unsigned WhichResult; | |||
7016 | bool isV_UNDEF; | |||
7017 | if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask( | |||
7018 | ShuffleMask, VT, WhichResult, isV_UNDEF)) { | |||
7019 | if (isV_UNDEF) | |||
7020 | V2 = V1; | |||
7021 | return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2) | |||
| ||||
7022 | .getValue(WhichResult); | |||
7023 | } | |||
7024 | ||||
7025 | // Also check for these shuffles through CONCAT_VECTORS: we canonicalize | |||
7026 | // shuffles that produce a result larger than their operands with: | |||
7027 | // shuffle(concat(v1, undef), concat(v2, undef)) | |||
7028 | // -> | |||
7029 | // shuffle(concat(v1, v2), undef) | |||
7030 | // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine). | |||
7031 | // | |||
7032 | // This is useful in the general case, but there are special cases where | |||
7033 | // native shuffles produce larger results: the two-result ops. | |||
7034 | // | |||
7035 | // Look through the concat when lowering them: | |||
7036 | // shuffle(concat(v1, v2), undef) | |||
7037 | // -> | |||
7038 | // concat(VZIP(v1, v2):0, :1) | |||
7039 | // | |||
7040 | if (V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { | |||
7041 | SDValue SubV1 = V1->getOperand(0); | |||
7042 | SDValue SubV2 = V1->getOperand(1); | |||
7043 | EVT SubVT = SubV1.getValueType(); | |||
7044 | ||||
7045 | // We expect these to have been canonicalized to -1. | |||
7046 | assert(llvm::all_of(ShuffleMask, [&](int i) {((llvm::all_of(ShuffleMask, [&](int i) { return i < (int )VT.getVectorNumElements(); }) && "Unexpected shuffle index into UNDEF operand!" ) ? static_cast<void> (0) : __assert_fail ("llvm::all_of(ShuffleMask, [&](int i) { return i < (int)VT.getVectorNumElements(); }) && \"Unexpected shuffle index into UNDEF operand!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7048, __PRETTY_FUNCTION__)) | |||
7047 | return i < (int)VT.getVectorNumElements();((llvm::all_of(ShuffleMask, [&](int i) { return i < (int )VT.getVectorNumElements(); }) && "Unexpected shuffle index into UNDEF operand!" ) ? static_cast<void> (0) : __assert_fail ("llvm::all_of(ShuffleMask, [&](int i) { return i < (int)VT.getVectorNumElements(); }) && \"Unexpected shuffle index into UNDEF operand!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7048, __PRETTY_FUNCTION__)) | |||
7048 | }) && "Unexpected shuffle index into UNDEF operand!")((llvm::all_of(ShuffleMask, [&](int i) { return i < (int )VT.getVectorNumElements(); }) && "Unexpected shuffle index into UNDEF operand!" ) ? static_cast<void> (0) : __assert_fail ("llvm::all_of(ShuffleMask, [&](int i) { return i < (int)VT.getVectorNumElements(); }) && \"Unexpected shuffle index into UNDEF operand!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7048, __PRETTY_FUNCTION__)); | |||
7049 | ||||
7050 | if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask( | |||
7051 | ShuffleMask, SubVT, WhichResult, isV_UNDEF)) { | |||
7052 | if (isV_UNDEF) | |||
7053 | SubV2 = SubV1; | |||
7054 | assert((WhichResult == 0) &&(((WhichResult == 0) && "In-place shuffle of concat can only have one result!" ) ? static_cast<void> (0) : __assert_fail ("(WhichResult == 0) && \"In-place shuffle of concat can only have one result!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7055, __PRETTY_FUNCTION__)) | |||
7055 | "In-place shuffle of concat can only have one result!")(((WhichResult == 0) && "In-place shuffle of concat can only have one result!" ) ? static_cast<void> (0) : __assert_fail ("(WhichResult == 0) && \"In-place shuffle of concat can only have one result!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7055, __PRETTY_FUNCTION__)); | |||
7056 | SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT), | |||
7057 | SubV1, SubV2); | |||
7058 | return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), | |||
7059 | Res.getValue(1)); | |||
7060 | } | |||
7061 | } | |||
7062 | } | |||
7063 | ||||
7064 | // If the shuffle is not directly supported and it has 4 elements, use | |||
7065 | // the PerfectShuffle-generated table to synthesize it from other shuffles. | |||
7066 | unsigned NumElts = VT.getVectorNumElements(); | |||
7067 | if (NumElts == 4) { | |||
7068 | unsigned PFIndexes[4]; | |||
7069 | for (unsigned i = 0; i != 4; ++i) { | |||
7070 | if (ShuffleMask[i] < 0) | |||
7071 | PFIndexes[i] = 8; | |||
7072 | else | |||
7073 | PFIndexes[i] = ShuffleMask[i]; | |||
7074 | } | |||
7075 | ||||
7076 | // Compute the index in the perfect shuffle table. | |||
7077 | unsigned PFTableIndex = | |||
7078 | PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; | |||
7079 | unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; | |||
7080 | unsigned Cost = (PFEntry >> 30); | |||
7081 | ||||
7082 | if (Cost <= 4) | |||
7083 | return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); | |||
7084 | } | |||
7085 | ||||
7086 | // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. | |||
7087 | if (EltSize >= 32) { | |||
7088 | // Do the expansion with floating-point types, since that is what the VFP | |||
7089 | // registers are defined to use, and since i64 is not legal. | |||
7090 | EVT EltVT = EVT::getFloatingPointVT(EltSize); | |||
7091 | EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); | |||
7092 | V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); | |||
7093 | V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); | |||
7094 | SmallVector<SDValue, 8> Ops; | |||
7095 | for (unsigned i = 0; i < NumElts; ++i) { | |||
7096 | if (ShuffleMask[i] < 0) | |||
7097 | Ops.push_back(DAG.getUNDEF(EltVT)); | |||
7098 | else | |||
7099 | Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, | |||
7100 | ShuffleMask[i] < (int)NumElts ? V1 : V2, | |||
7101 | DAG.getConstant(ShuffleMask[i] & (NumElts-1), | |||
7102 | dl, MVT::i32))); | |||
7103 | } | |||
7104 | SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); | |||
7105 | return DAG.getNode(ISD::BITCAST, dl, VT, Val); | |||
7106 | } | |||
7107 | ||||
7108 | if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT)) | |||
7109 | return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG); | |||
7110 | ||||
7111 | if (VT == MVT::v8i8) | |||
7112 | if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG)) | |||
7113 | return NewOp; | |||
7114 | ||||
7115 | return SDValue(); | |||
7116 | } | |||
7117 | ||||
7118 | static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { | |||
7119 | // INSERT_VECTOR_ELT is legal only for immediate indexes. | |||
7120 | SDValue Lane = Op.getOperand(2); | |||
7121 | if (!isa<ConstantSDNode>(Lane)) | |||
7122 | return SDValue(); | |||
7123 | ||||
7124 | return Op; | |||
7125 | } | |||
7126 | ||||
7127 | static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { | |||
7128 | // EXTRACT_VECTOR_ELT is legal only for immediate indexes. | |||
7129 | SDValue Lane = Op.getOperand(1); | |||
7130 | if (!isa<ConstantSDNode>(Lane)) | |||
7131 | return SDValue(); | |||
7132 | ||||
7133 | SDValue Vec = Op.getOperand(0); | |||
7134 | if (Op.getValueType() == MVT::i32 && Vec.getScalarValueSizeInBits() < 32) { | |||
7135 | SDLoc dl(Op); | |||
7136 | return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); | |||
7137 | } | |||
7138 | ||||
7139 | return Op; | |||
7140 | } | |||
7141 | ||||
7142 | static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { | |||
7143 | // The only time a CONCAT_VECTORS operation can have legal types is when | |||
7144 | // two 64-bit vectors are concatenated to a 128-bit vector. | |||
7145 | assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&((Op.getValueType().is128BitVector() && Op.getNumOperands () == 2 && "unexpected CONCAT_VECTORS") ? static_cast <void> (0) : __assert_fail ("Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && \"unexpected CONCAT_VECTORS\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7146, __PRETTY_FUNCTION__)) | |||
7146 | "unexpected CONCAT_VECTORS")((Op.getValueType().is128BitVector() && Op.getNumOperands () == 2 && "unexpected CONCAT_VECTORS") ? static_cast <void> (0) : __assert_fail ("Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && \"unexpected CONCAT_VECTORS\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7146, __PRETTY_FUNCTION__)); | |||
7147 | SDLoc dl(Op); | |||
7148 | SDValue Val = DAG.getUNDEF(MVT::v2f64); | |||
7149 | SDValue Op0 = Op.getOperand(0); | |||
7150 | SDValue Op1 = Op.getOperand(1); | |||
7151 | if (!Op0.isUndef()) | |||
7152 | Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, | |||
7153 | DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), | |||
7154 | DAG.getIntPtrConstant(0, dl)); | |||
7155 | if (!Op1.isUndef()) | |||
7156 | Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, | |||
7157 | DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), | |||
7158 | DAG.getIntPtrConstant(1, dl)); | |||
7159 | return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); | |||
7160 | } | |||
7161 | ||||
7162 | /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each | |||
7163 | /// element has been zero/sign-extended, depending on the isSigned parameter, | |||
7164 | /// from an integer type half its size. | |||
7165 | static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, | |||
7166 | bool isSigned) { | |||
7167 | // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. | |||
7168 | EVT VT = N->getValueType(0); | |||
7169 | if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { | |||
7170 | SDNode *BVN = N->getOperand(0).getNode(); | |||
7171 | if (BVN->getValueType(0) != MVT::v4i32 || | |||
7172 | BVN->getOpcode() != ISD::BUILD_VECTOR) | |||
7173 | return false; | |||
7174 | unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0; | |||
7175 | unsigned HiElt = 1 - LoElt; | |||
7176 | ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); | |||
7177 | ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); | |||
7178 | ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); | |||
7179 | ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); | |||
7180 | if (!Lo0 || !Hi0 || !Lo1 || !Hi1) | |||
7181 | return false; | |||
7182 | if (isSigned) { | |||
7183 | if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && | |||
7184 | Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) | |||
7185 | return true; | |||
7186 | } else { | |||
7187 | if (Hi0->isNullValue() && Hi1->isNullValue()) | |||
7188 | return true; | |||
7189 | } | |||
7190 | return false; | |||
7191 | } | |||
7192 | ||||
7193 | if (N->getOpcode() != ISD::BUILD_VECTOR) | |||
7194 | return false; | |||
7195 | ||||
7196 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { | |||
7197 | SDNode *Elt = N->getOperand(i).getNode(); | |||
7198 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { | |||
7199 | unsigned EltSize = VT.getScalarSizeInBits(); | |||
7200 | unsigned HalfSize = EltSize / 2; | |||
7201 | if (isSigned) { | |||
7202 | if (!isIntN(HalfSize, C->getSExtValue())) | |||
7203 | return false; | |||
7204 | } else { | |||
7205 | if (!isUIntN(HalfSize, C->getZExtValue())) | |||
7206 | return false; | |||
7207 | } | |||
7208 | continue; | |||
7209 | } | |||
7210 | return false; | |||
7211 | } | |||
7212 | ||||
7213 | return true; | |||
7214 | } | |||
7215 | ||||
7216 | /// isSignExtended - Check if a node is a vector value that is sign-extended | |||
7217 | /// or a constant BUILD_VECTOR with sign-extended elements. | |||
7218 | static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { | |||
7219 | if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) | |||
7220 | return true; | |||
7221 | if (isExtendedBUILD_VECTOR(N, DAG, true)) | |||
7222 | return true; | |||
7223 | return false; | |||
7224 | } | |||
7225 | ||||
7226 | /// isZeroExtended - Check if a node is a vector value that is zero-extended | |||
7227 | /// or a constant BUILD_VECTOR with zero-extended elements. | |||
7228 | static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { | |||
7229 | if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) | |||
7230 | return true; | |||
7231 | if (isExtendedBUILD_VECTOR(N, DAG, false)) | |||
7232 | return true; | |||
7233 | return false; | |||
7234 | } | |||
7235 | ||||
7236 | static EVT getExtensionTo64Bits(const EVT &OrigVT) { | |||
7237 | if (OrigVT.getSizeInBits() >= 64) | |||
7238 | return OrigVT; | |||
7239 | ||||
7240 | assert(OrigVT.isSimple() && "Expecting a simple value type")((OrigVT.isSimple() && "Expecting a simple value type" ) ? static_cast<void> (0) : __assert_fail ("OrigVT.isSimple() && \"Expecting a simple value type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7240, __PRETTY_FUNCTION__)); | |||
7241 | ||||
7242 | MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; | |||
7243 | switch (OrigSimpleTy) { | |||
7244 | default: llvm_unreachable("Unexpected Vector Type")::llvm::llvm_unreachable_internal("Unexpected Vector Type", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7244); | |||
7245 | case MVT::v2i8: | |||
7246 | case MVT::v2i16: | |||
7247 | return MVT::v2i32; | |||
7248 | case MVT::v4i8: | |||
7249 | return MVT::v4i16; | |||
7250 | } | |||
7251 | } | |||
7252 | ||||
7253 | /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total | |||
7254 | /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL. | |||
7255 | /// We insert the required extension here to get the vector to fill a D register. | |||
7256 | static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, | |||
7257 | const EVT &OrigTy, | |||
7258 | const EVT &ExtTy, | |||
7259 | unsigned ExtOpcode) { | |||
7260 | // The vector originally had a size of OrigTy. It was then extended to ExtTy. | |||
7261 | // We expect the ExtTy to be 128-bits total. If the OrigTy is less than | |||
7262 | // 64-bits we need to insert a new extension so that it will be 64-bits. | |||
7263 | assert(ExtTy.is128BitVector() && "Unexpected extension size")((ExtTy.is128BitVector() && "Unexpected extension size" ) ? static_cast<void> (0) : __assert_fail ("ExtTy.is128BitVector() && \"Unexpected extension size\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7263, __PRETTY_FUNCTION__)); | |||
7264 | if (OrigTy.getSizeInBits() >= 64) | |||
7265 | return N; | |||
7266 | ||||
7267 | // Must extend size to at least 64 bits to be used as an operand for VMULL. | |||
7268 | EVT NewVT = getExtensionTo64Bits(OrigTy); | |||
7269 | ||||
7270 | return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); | |||
7271 | } | |||
7272 | ||||
7273 | /// SkipLoadExtensionForVMULL - return a load of the original vector size that | |||
7274 | /// does not do any sign/zero extension. If the original vector is less | |||
7275 | /// than 64 bits, an appropriate extension will be added after the load to | |||
7276 | /// reach a total size of 64 bits. We have to add the extension separately | |||
7277 | /// because ARM does not have a sign/zero extending load for vectors. | |||
7278 | static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) { | |||
7279 | EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT()); | |||
7280 | ||||
7281 | // The load already has the right type. | |||
7282 | if (ExtendedTy == LD->getMemoryVT()) | |||
7283 | return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(), | |||
7284 | LD->getBasePtr(), LD->getPointerInfo(), | |||
7285 | LD->getAlignment(), LD->getMemOperand()->getFlags()); | |||
7286 | ||||
7287 | // We need to create a zextload/sextload. We cannot just create a load | |||
7288 | // followed by a zext/zext node because LowerMUL is also run during normal | |||
7289 | // operation legalization where we can't create illegal types. | |||
7290 | return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy, | |||
7291 | LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), | |||
7292 | LD->getMemoryVT(), LD->getAlignment(), | |||
7293 | LD->getMemOperand()->getFlags()); | |||
7294 | } | |||
7295 | ||||
7296 | /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, | |||
7297 | /// extending load, or BUILD_VECTOR with extended elements, return the | |||
7298 | /// unextended value. The unextended vector should be 64 bits so that it can | |||
7299 | /// be used as an operand to a VMULL instruction. If the original vector size | |||
7300 | /// before extension is less than 64 bits we add a an extension to resize | |||
7301 | /// the vector to 64 bits. | |||
7302 | static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) { | |||
7303 | if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) | |||
7304 | return AddRequiredExtensionForVMULL(N->getOperand(0), DAG, | |||
7305 | N->getOperand(0)->getValueType(0), | |||
7306 | N->getValueType(0), | |||
7307 | N->getOpcode()); | |||
7308 | ||||
7309 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { | |||
7310 | assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) &&(((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && "Expected extending load" ) ? static_cast<void> (0) : __assert_fail ("(ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && \"Expected extending load\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7311, __PRETTY_FUNCTION__)) | |||
7311 | "Expected extending load")(((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && "Expected extending load" ) ? static_cast<void> (0) : __assert_fail ("(ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && \"Expected extending load\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7311, __PRETTY_FUNCTION__)); | |||
7312 | ||||
7313 | SDValue newLoad = SkipLoadExtensionForVMULL(LD, DAG); | |||
7314 | DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), newLoad.getValue(1)); | |||
7315 | unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; | |||
7316 | SDValue extLoad = | |||
7317 | DAG.getNode(Opcode, SDLoc(newLoad), LD->getValueType(0), newLoad); | |||
7318 | DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 0), extLoad); | |||
7319 | ||||
7320 | return newLoad; | |||
7321 | } | |||
7322 | ||||
7323 | // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will | |||
7324 | // have been legalized as a BITCAST from v4i32. | |||
7325 | if (N->getOpcode() == ISD::BITCAST) { | |||
7326 | SDNode *BVN = N->getOperand(0).getNode(); | |||
7327 | assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&((BVN->getOpcode() == ISD::BUILD_VECTOR && BVN-> getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR" ) ? static_cast<void> (0) : __assert_fail ("BVN->getOpcode() == ISD::BUILD_VECTOR && BVN->getValueType(0) == MVT::v4i32 && \"expected v4i32 BUILD_VECTOR\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7328, __PRETTY_FUNCTION__)) | |||
7328 | BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR")((BVN->getOpcode() == ISD::BUILD_VECTOR && BVN-> getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR" ) ? static_cast<void> (0) : __assert_fail ("BVN->getOpcode() == ISD::BUILD_VECTOR && BVN->getValueType(0) == MVT::v4i32 && \"expected v4i32 BUILD_VECTOR\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7328, __PRETTY_FUNCTION__)); | |||
7329 | unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0; | |||
7330 | return DAG.getBuildVector( | |||
7331 | MVT::v2i32, SDLoc(N), | |||
7332 | {BVN->getOperand(LowElt), BVN->getOperand(LowElt + 2)}); | |||
7333 | } | |||
7334 | // Construct a new BUILD_VECTOR with elements truncated to half the size. | |||
7335 | assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR")((N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR" ) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::BUILD_VECTOR && \"expected BUILD_VECTOR\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7335, __PRETTY_FUNCTION__)); | |||
7336 | EVT VT = N->getValueType(0); | |||
7337 | unsigned EltSize = VT.getScalarSizeInBits() / 2; | |||
7338 | unsigned NumElts = VT.getVectorNumElements(); | |||
7339 | MVT TruncVT = MVT::getIntegerVT(EltSize); | |||
7340 | SmallVector<SDValue, 8> Ops; | |||
7341 | SDLoc dl(N); | |||
7342 | for (unsigned i = 0; i != NumElts; ++i) { | |||
7343 | ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); | |||
7344 | const APInt &CInt = C->getAPIntValue(); | |||
7345 | // Element types smaller than 32 bits are not legal, so use i32 elements. | |||
7346 | // The values are implicitly truncated so sext vs. zext doesn't matter. | |||
7347 | Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); | |||
7348 | } | |||
7349 | return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops); | |||
7350 | } | |||
7351 | ||||
7352 | static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { | |||
7353 | unsigned Opcode = N->getOpcode(); | |||
7354 | if (Opcode == ISD::ADD || Opcode == ISD::SUB) { | |||
7355 | SDNode *N0 = N->getOperand(0).getNode(); | |||
7356 | SDNode *N1 = N->getOperand(1).getNode(); | |||
7357 | return N0->hasOneUse() && N1->hasOneUse() && | |||
7358 | isSignExtended(N0, DAG) && isSignExtended(N1, DAG); | |||
7359 | } | |||
7360 | return false; | |||
7361 | } | |||
7362 | ||||
7363 | static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { | |||
7364 | unsigned Opcode = N->getOpcode(); | |||
7365 | if (Opcode == ISD::ADD || Opcode == ISD::SUB) { | |||
7366 | SDNode *N0 = N->getOperand(0).getNode(); | |||
7367 | SDNode *N1 = N->getOperand(1).getNode(); | |||
7368 | return N0->hasOneUse() && N1->hasOneUse() && | |||
7369 | isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); | |||
7370 | } | |||
7371 | return false; | |||
7372 | } | |||
7373 | ||||
7374 | static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { | |||
7375 | // Multiplications are only custom-lowered for 128-bit vectors so that | |||
7376 | // VMULL can be detected. Otherwise v2i64 multiplications are not legal. | |||
7377 | EVT VT = Op.getValueType(); | |||
7378 | assert(VT.is128BitVector() && VT.isInteger() &&((VT.is128BitVector() && VT.isInteger() && "unexpected type for custom-lowering ISD::MUL" ) ? static_cast<void> (0) : __assert_fail ("VT.is128BitVector() && VT.isInteger() && \"unexpected type for custom-lowering ISD::MUL\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7379, __PRETTY_FUNCTION__)) | |||
7379 | "unexpected type for custom-lowering ISD::MUL")((VT.is128BitVector() && VT.isInteger() && "unexpected type for custom-lowering ISD::MUL" ) ? static_cast<void> (0) : __assert_fail ("VT.is128BitVector() && VT.isInteger() && \"unexpected type for custom-lowering ISD::MUL\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7379, __PRETTY_FUNCTION__)); | |||
7380 | SDNode *N0 = Op.getOperand(0).getNode(); | |||
7381 | SDNode *N1 = Op.getOperand(1).getNode(); | |||
7382 | unsigned NewOpc = 0; | |||
7383 | bool isMLA = false; | |||
7384 | bool isN0SExt = isSignExtended(N0, DAG); | |||
7385 | bool isN1SExt = isSignExtended(N1, DAG); | |||
7386 | if (isN0SExt && isN1SExt) | |||
7387 | NewOpc = ARMISD::VMULLs; | |||
7388 | else { | |||
7389 | bool isN0ZExt = isZeroExtended(N0, DAG); | |||
7390 | bool isN1ZExt = isZeroExtended(N1, DAG); | |||
7391 | if (isN0ZExt && isN1ZExt) | |||
7392 | NewOpc = ARMISD::VMULLu; | |||
7393 | else if (isN1SExt || isN1ZExt) { | |||
7394 | // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these | |||
7395 | // into (s/zext A * s/zext C) + (s/zext B * s/zext C) | |||
7396 | if (isN1SExt && isAddSubSExt(N0, DAG)) { | |||
7397 | NewOpc = ARMISD::VMULLs; | |||
7398 | isMLA = true; | |||
7399 | } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { | |||
7400 | NewOpc = ARMISD::VMULLu; | |||
7401 | isMLA = true; | |||
7402 | } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { | |||
7403 | std::swap(N0, N1); | |||
7404 | NewOpc = ARMISD::VMULLu; | |||
7405 | isMLA = true; | |||
7406 | } | |||
7407 | } | |||
7408 | ||||
7409 | if (!NewOpc) { | |||
7410 | if (VT == MVT::v2i64) | |||
7411 | // Fall through to expand this. It is not legal. | |||
7412 | return SDValue(); | |||
7413 | else | |||
7414 | // Other vector multiplications are legal. | |||
7415 | return Op; | |||
7416 | } | |||
7417 | } | |||
7418 | ||||
7419 | // Legalize to a VMULL instruction. | |||
7420 | SDLoc DL(Op); | |||
7421 | SDValue Op0; | |||
7422 | SDValue Op1 = SkipExtensionForVMULL(N1, DAG); | |||
7423 | if (!isMLA) { | |||
7424 | Op0 = SkipExtensionForVMULL(N0, DAG); | |||
7425 | assert(Op0.getValueType().is64BitVector() &&((Op0.getValueType().is64BitVector() && Op1.getValueType ().is64BitVector() && "unexpected types for extended operands to VMULL" ) ? static_cast<void> (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7427, __PRETTY_FUNCTION__)) | |||
7426 | Op1.getValueType().is64BitVector() &&((Op0.getValueType().is64BitVector() && Op1.getValueType ().is64BitVector() && "unexpected types for extended operands to VMULL" ) ? static_cast<void> (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7427, __PRETTY_FUNCTION__)) | |||
7427 | "unexpected types for extended operands to VMULL")((Op0.getValueType().is64BitVector() && Op1.getValueType ().is64BitVector() && "unexpected types for extended operands to VMULL" ) ? static_cast<void> (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7427, __PRETTY_FUNCTION__)); | |||
7428 | return DAG.getNode(NewOpc, DL, VT, Op0, Op1); | |||
7429 | } | |||
7430 | ||||
7431 | // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during | |||
7432 | // isel lowering to take advantage of no-stall back to back vmul + vmla. | |||
7433 | // vmull q0, d4, d6 | |||
7434 | // vmlal q0, d5, d6 | |||
7435 | // is faster than | |||
7436 | // vaddl q0, d4, d5 | |||
7437 | // vmovl q1, d6 | |||
7438 | // vmul q0, q0, q1 | |||
7439 | SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); | |||
7440 | SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); | |||
7441 | EVT Op1VT = Op1.getValueType(); | |||
7442 | return DAG.getNode(N0->getOpcode(), DL, VT, | |||
7443 | DAG.getNode(NewOpc, DL, VT, | |||
7444 | DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), | |||
7445 | DAG.getNode(NewOpc, DL, VT, | |||
7446 | DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); | |||
7447 | } | |||
7448 | ||||
7449 | static SDValue LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl, | |||
7450 | SelectionDAG &DAG) { | |||
7451 | // TODO: Should this propagate fast-math-flags? | |||
7452 | ||||
7453 | // Convert to float | |||
7454 | // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); | |||
7455 | // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); | |||
7456 | X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); | |||
7457 | Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); | |||
7458 | X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); | |||
7459 | Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); | |||
7460 | // Get reciprocal estimate. | |||
7461 | // float4 recip = vrecpeq_f32(yf); | |||
7462 | Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7463 | DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), | |||
7464 | Y); | |||
7465 | // Because char has a smaller range than uchar, we can actually get away | |||
7466 | // without any newton steps. This requires that we use a weird bias | |||
7467 | // of 0xb000, however (again, this has been exhaustively tested). | |||
7468 | // float4 result = as_float4(as_int4(xf*recip) + 0xb000); | |||
7469 | X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); | |||
7470 | X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); | |||
7471 | Y = DAG.getConstant(0xb000, dl, MVT::v4i32); | |||
7472 | X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); | |||
7473 | X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); | |||
7474 | // Convert back to short. | |||
7475 | X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); | |||
7476 | X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); | |||
7477 | return X; | |||
7478 | } | |||
7479 | ||||
7480 | static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, | |||
7481 | SelectionDAG &DAG) { | |||
7482 | // TODO: Should this propagate fast-math-flags? | |||
7483 | ||||
7484 | SDValue N2; | |||
7485 | // Convert to float. | |||
7486 | // float4 yf = vcvt_f32_s32(vmovl_s16(y)); | |||
7487 | // float4 xf = vcvt_f32_s32(vmovl_s16(x)); | |||
7488 | N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); | |||
7489 | N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); | |||
7490 | N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); | |||
7491 | N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); | |||
7492 | ||||
7493 | // Use reciprocal estimate and one refinement step. | |||
7494 | // float4 recip = vrecpeq_f32(yf); | |||
7495 | // recip *= vrecpsq_f32(yf, recip); | |||
7496 | N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7497 | DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), | |||
7498 | N1); | |||
7499 | N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7500 | DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), | |||
7501 | N1, N2); | |||
7502 | N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); | |||
7503 | // Because short has a smaller range than ushort, we can actually get away | |||
7504 | // with only a single newton step. This requires that we use a weird bias | |||
7505 | // of 89, however (again, this has been exhaustively tested). | |||
7506 | // float4 result = as_float4(as_int4(xf*recip) + 0x89); | |||
7507 | N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); | |||
7508 | N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); | |||
7509 | N1 = DAG.getConstant(0x89, dl, MVT::v4i32); | |||
7510 | N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); | |||
7511 | N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); | |||
7512 | // Convert back to integer and return. | |||
7513 | // return vmovn_s32(vcvt_s32_f32(result)); | |||
7514 | N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); | |||
7515 | N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); | |||
7516 | return N0; | |||
7517 | } | |||
7518 | ||||
7519 | static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { | |||
7520 | EVT VT = Op.getValueType(); | |||
7521 | assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&(((VT == MVT::v4i16 || VT == MVT::v8i8) && "unexpected type for custom-lowering ISD::SDIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v4i16 || VT == MVT::v8i8) && \"unexpected type for custom-lowering ISD::SDIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7522, __PRETTY_FUNCTION__)) | |||
7522 | "unexpected type for custom-lowering ISD::SDIV")(((VT == MVT::v4i16 || VT == MVT::v8i8) && "unexpected type for custom-lowering ISD::SDIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v4i16 || VT == MVT::v8i8) && \"unexpected type for custom-lowering ISD::SDIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7522, __PRETTY_FUNCTION__)); | |||
7523 | ||||
7524 | SDLoc dl(Op); | |||
7525 | SDValue N0 = Op.getOperand(0); | |||
7526 | SDValue N1 = Op.getOperand(1); | |||
7527 | SDValue N2, N3; | |||
7528 | ||||
7529 | if (VT == MVT::v8i8) { | |||
7530 | N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); | |||
7531 | N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); | |||
7532 | ||||
7533 | N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, | |||
7534 | DAG.getIntPtrConstant(4, dl)); | |||
7535 | N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, | |||
7536 | DAG.getIntPtrConstant(4, dl)); | |||
7537 | N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, | |||
7538 | DAG.getIntPtrConstant(0, dl)); | |||
7539 | N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, | |||
7540 | DAG.getIntPtrConstant(0, dl)); | |||
7541 | ||||
7542 | N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 | |||
7543 | N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 | |||
7544 | ||||
7545 | N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); | |||
7546 | N0 = LowerCONCAT_VECTORS(N0, DAG); | |||
7547 | ||||
7548 | N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); | |||
7549 | return N0; | |||
7550 | } | |||
7551 | return LowerSDIV_v4i16(N0, N1, dl, DAG); | |||
7552 | } | |||
7553 | ||||
7554 | static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { | |||
7555 | // TODO: Should this propagate fast-math-flags? | |||
7556 | EVT VT = Op.getValueType(); | |||
7557 | assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&(((VT == MVT::v4i16 || VT == MVT::v8i8) && "unexpected type for custom-lowering ISD::UDIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v4i16 || VT == MVT::v8i8) && \"unexpected type for custom-lowering ISD::UDIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7558, __PRETTY_FUNCTION__)) | |||
7558 | "unexpected type for custom-lowering ISD::UDIV")(((VT == MVT::v4i16 || VT == MVT::v8i8) && "unexpected type for custom-lowering ISD::UDIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::v4i16 || VT == MVT::v8i8) && \"unexpected type for custom-lowering ISD::UDIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7558, __PRETTY_FUNCTION__)); | |||
7559 | ||||
7560 | SDLoc dl(Op); | |||
7561 | SDValue N0 = Op.getOperand(0); | |||
7562 | SDValue N1 = Op.getOperand(1); | |||
7563 | SDValue N2, N3; | |||
7564 | ||||
7565 | if (VT == MVT::v8i8) { | |||
7566 | N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); | |||
7567 | N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); | |||
7568 | ||||
7569 | N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, | |||
7570 | DAG.getIntPtrConstant(4, dl)); | |||
7571 | N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, | |||
7572 | DAG.getIntPtrConstant(4, dl)); | |||
7573 | N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, | |||
7574 | DAG.getIntPtrConstant(0, dl)); | |||
7575 | N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, | |||
7576 | DAG.getIntPtrConstant(0, dl)); | |||
7577 | ||||
7578 | N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 | |||
7579 | N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 | |||
7580 | ||||
7581 | N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); | |||
7582 | N0 = LowerCONCAT_VECTORS(N0, DAG); | |||
7583 | ||||
7584 | N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, | |||
7585 | DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl, | |||
7586 | MVT::i32), | |||
7587 | N0); | |||
7588 | return N0; | |||
7589 | } | |||
7590 | ||||
7591 | // v4i16 sdiv ... Convert to float. | |||
7592 | // float4 yf = vcvt_f32_s32(vmovl_u16(y)); | |||
7593 | // float4 xf = vcvt_f32_s32(vmovl_u16(x)); | |||
7594 | N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); | |||
7595 | N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); | |||
7596 | N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); | |||
7597 | SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); | |||
7598 | ||||
7599 | // Use reciprocal estimate and two refinement steps. | |||
7600 | // float4 recip = vrecpeq_f32(yf); | |||
7601 | // recip *= vrecpsq_f32(yf, recip); | |||
7602 | // recip *= vrecpsq_f32(yf, recip); | |||
7603 | N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7604 | DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), | |||
7605 | BN1); | |||
7606 | N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7607 | DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), | |||
7608 | BN1, N2); | |||
7609 | N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); | |||
7610 | N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, | |||
7611 | DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), | |||
7612 | BN1, N2); | |||
7613 | N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); | |||
7614 | // Simply multiplying by the reciprocal estimate can leave us a few ulps | |||
7615 | // too low, so we add 2 ulps (exhaustive testing shows that this is enough, | |||
7616 | // and that it will never cause us to return an answer too large). | |||
7617 | // float4 result = as_float4(as_int4(xf*recip) + 2); | |||
7618 | N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); | |||
7619 | N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); | |||
7620 | N1 = DAG.getConstant(2, dl, MVT::v4i32); | |||
7621 | N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); | |||
7622 | N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); | |||
7623 | // Convert back to integer and return. | |||
7624 | // return vmovn_u32(vcvt_s32_f32(result)); | |||
7625 | N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); | |||
7626 | N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); | |||
7627 | return N0; | |||
7628 | } | |||
7629 | ||||
7630 | static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) { | |||
7631 | SDNode *N = Op.getNode(); | |||
7632 | EVT VT = N->getValueType(0); | |||
7633 | SDVTList VTs = DAG.getVTList(VT, MVT::i32); | |||
7634 | ||||
7635 | SDValue Carry = Op.getOperand(2); | |||
7636 | ||||
7637 | SDLoc DL(Op); | |||
7638 | ||||
7639 | SDValue Result; | |||
7640 | if (Op.getOpcode() == ISD::ADDCARRY) { | |||
7641 | // This converts the boolean value carry into the carry flag. | |||
7642 | Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG); | |||
7643 | ||||
7644 | // Do the addition proper using the carry flag we wanted. | |||
7645 | Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), | |||
7646 | Op.getOperand(1), Carry); | |||
7647 | ||||
7648 | // Now convert the carry flag into a boolean value. | |||
7649 | Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG); | |||
7650 | } else { | |||
7651 | // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we | |||
7652 | // have to invert the carry first. | |||
7653 | Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, | |||
7654 | DAG.getConstant(1, DL, MVT::i32), Carry); | |||
7655 | // This converts the boolean value carry into the carry flag. | |||
7656 | Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG); | |||
7657 | ||||
7658 | // Do the subtraction proper using the carry flag we wanted. | |||
7659 | Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0), | |||
7660 | Op.getOperand(1), Carry); | |||
7661 | ||||
7662 | // Now convert the carry flag into a boolean value. | |||
7663 | Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG); | |||
7664 | // But the carry returned by ARMISD::SUBE is not a borrow as expected | |||
7665 | // by ISD::SUBCARRY, so compute 1 - C. | |||
7666 | Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, | |||
7667 | DAG.getConstant(1, DL, MVT::i32), Carry); | |||
7668 | } | |||
7669 | ||||
7670 | // Return both values. | |||
7671 | return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); | |||
7672 | } | |||
7673 | ||||
7674 | SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const { | |||
7675 | assert(Subtarget->isTargetDarwin())((Subtarget->isTargetDarwin()) ? static_cast<void> ( 0) : __assert_fail ("Subtarget->isTargetDarwin()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7675, __PRETTY_FUNCTION__)); | |||
7676 | ||||
7677 | // For iOS, we want to call an alternative entry point: __sincos_stret, | |||
7678 | // return values are passed via sret. | |||
7679 | SDLoc dl(Op); | |||
7680 | SDValue Arg = Op.getOperand(0); | |||
7681 | EVT ArgVT = Arg.getValueType(); | |||
7682 | Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); | |||
7683 | auto PtrVT = getPointerTy(DAG.getDataLayout()); | |||
7684 | ||||
7685 | MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); | |||
7686 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
7687 | ||||
7688 | // Pair of floats / doubles used to pass the result. | |||
7689 | Type *RetTy = StructType::get(ArgTy, ArgTy); | |||
7690 | auto &DL = DAG.getDataLayout(); | |||
7691 | ||||
7692 | ArgListTy Args; | |||
7693 | bool ShouldUseSRet = Subtarget->isAPCS_ABI(); | |||
7694 | SDValue SRet; | |||
7695 | if (ShouldUseSRet) { | |||
7696 | // Create stack object for sret. | |||
7697 | const uint64_t ByteSize = DL.getTypeAllocSize(RetTy); | |||
7698 | const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy); | |||
7699 | int FrameIdx = MFI.CreateStackObject(ByteSize, StackAlign, false); | |||
7700 | SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy(DL)); | |||
7701 | ||||
7702 | ArgListEntry Entry; | |||
7703 | Entry.Node = SRet; | |||
7704 | Entry.Ty = RetTy->getPointerTo(); | |||
7705 | Entry.IsSExt = false; | |||
7706 | Entry.IsZExt = false; | |||
7707 | Entry.IsSRet = true; | |||
7708 | Args.push_back(Entry); | |||
7709 | RetTy = Type::getVoidTy(*DAG.getContext()); | |||
7710 | } | |||
7711 | ||||
7712 | ArgListEntry Entry; | |||
7713 | Entry.Node = Arg; | |||
7714 | Entry.Ty = ArgTy; | |||
7715 | Entry.IsSExt = false; | |||
7716 | Entry.IsZExt = false; | |||
7717 | Args.push_back(Entry); | |||
7718 | ||||
7719 | RTLIB::Libcall LC = | |||
7720 | (ArgVT == MVT::f64) ? RTLIB::SINCOS_STRET_F64 : RTLIB::SINCOS_STRET_F32; | |||
7721 | const char *LibcallName = getLibcallName(LC); | |||
7722 | CallingConv::ID CC = getLibcallCallingConv(LC); | |||
7723 | SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL)); | |||
7724 | ||||
7725 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
7726 | CLI.setDebugLoc(dl) | |||
7727 | .setChain(DAG.getEntryNode()) | |||
7728 | .setCallee(CC, RetTy, Callee, std::move(Args)) | |||
7729 | .setDiscardResult(ShouldUseSRet); | |||
7730 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); | |||
7731 | ||||
7732 | if (!ShouldUseSRet) | |||
7733 | return CallResult.first; | |||
7734 | ||||
7735 | SDValue LoadSin = | |||
7736 | DAG.getLoad(ArgVT, dl, CallResult.second, SRet, MachinePointerInfo()); | |||
7737 | ||||
7738 | // Address of cos field. | |||
7739 | SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet, | |||
7740 | DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl)); | |||
7741 | SDValue LoadCos = | |||
7742 | DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add, MachinePointerInfo()); | |||
7743 | ||||
7744 | SDVTList Tys = DAG.getVTList(ArgVT, ArgVT); | |||
7745 | return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, | |||
7746 | LoadSin.getValue(0), LoadCos.getValue(0)); | |||
7747 | } | |||
7748 | ||||
7749 | SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, | |||
7750 | bool Signed, | |||
7751 | SDValue &Chain) const { | |||
7752 | EVT VT = Op.getValueType(); | |||
7753 | assert((VT == MVT::i32 || VT == MVT::i64) &&(((VT == MVT::i32 || VT == MVT::i64) && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7754, __PRETTY_FUNCTION__)) | |||
7754 | "unexpected type for custom lowering DIV")(((VT == MVT::i32 || VT == MVT::i64) && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("(VT == MVT::i32 || VT == MVT::i64) && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7754, __PRETTY_FUNCTION__)); | |||
7755 | SDLoc dl(Op); | |||
7756 | ||||
7757 | const auto &DL = DAG.getDataLayout(); | |||
7758 | const auto &TLI = DAG.getTargetLoweringInfo(); | |||
7759 | ||||
7760 | const char *Name = nullptr; | |||
7761 | if (Signed) | |||
7762 | Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64"; | |||
7763 | else | |||
7764 | Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64"; | |||
7765 | ||||
7766 | SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL)); | |||
7767 | ||||
7768 | ARMTargetLowering::ArgListTy Args; | |||
7769 | ||||
7770 | for (auto AI : {1, 0}) { | |||
7771 | ArgListEntry Arg; | |||
7772 | Arg.Node = Op.getOperand(AI); | |||
7773 | Arg.Ty = Arg.Node.getValueType().getTypeForEVT(*DAG.getContext()); | |||
7774 | Args.push_back(Arg); | |||
7775 | } | |||
7776 | ||||
7777 | CallLoweringInfo CLI(DAG); | |||
7778 | CLI.setDebugLoc(dl) | |||
7779 | .setChain(Chain) | |||
7780 | .setCallee(CallingConv::ARM_AAPCS_VFP, VT.getTypeForEVT(*DAG.getContext()), | |||
7781 | ES, std::move(Args)); | |||
7782 | ||||
7783 | return LowerCallTo(CLI).first; | |||
7784 | } | |||
7785 | ||||
7786 | // This is a code size optimisation: return the original SDIV node to | |||
7787 | // DAGCombiner when we don't want to expand SDIV into a sequence of | |||
7788 | // instructions, and an empty node otherwise which will cause the | |||
7789 | // SDIV to be expanded in DAGCombine. | |||
7790 | SDValue | |||
7791 | ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, | |||
7792 | SelectionDAG &DAG, | |||
7793 | SmallVectorImpl<SDNode *> &Created) const { | |||
7794 | // TODO: Support SREM | |||
7795 | if (N->getOpcode() != ISD::SDIV) | |||
7796 | return SDValue(); | |||
7797 | ||||
7798 | const auto &ST = static_cast<const ARMSubtarget&>(DAG.getSubtarget()); | |||
7799 | const bool MinSize = ST.hasMinSize(); | |||
7800 | const bool HasDivide = ST.isThumb() ? ST.hasDivideInThumbMode() | |||
7801 | : ST.hasDivideInARMMode(); | |||
7802 | ||||
7803 | // Don't touch vector types; rewriting this may lead to scalarizing | |||
7804 | // the int divs. | |||
7805 | if (N->getOperand(0).getValueType().isVector()) | |||
7806 | return SDValue(); | |||
7807 | ||||
7808 | // Bail if MinSize is not set, and also for both ARM and Thumb mode we need | |||
7809 | // hwdiv support for this to be really profitable. | |||
7810 | if (!(MinSize && HasDivide)) | |||
7811 | return SDValue(); | |||
7812 | ||||
7813 | // ARM mode is a bit simpler than Thumb: we can handle large power | |||
7814 | // of 2 immediates with 1 mov instruction; no further checks required, | |||
7815 | // just return the sdiv node. | |||
7816 | if (!ST.isThumb()) | |||
7817 | return SDValue(N, 0); | |||
7818 | ||||
7819 | // In Thumb mode, immediates larger than 128 need a wide 4-byte MOV, | |||
7820 | // and thus lose the code size benefits of a MOVS that requires only 2. | |||
7821 | // TargetTransformInfo and 'getIntImmCodeSizeCost' could be helpful here, | |||
7822 | // but as it's doing exactly this, it's not worth the trouble to get TTI. | |||
7823 | if (Divisor.sgt(128)) | |||
7824 | return SDValue(); | |||
7825 | ||||
7826 | return SDValue(N, 0); | |||
7827 | } | |||
7828 | ||||
7829 | SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, | |||
7830 | bool Signed) const { | |||
7831 | assert(Op.getValueType() == MVT::i32 &&((Op.getValueType() == MVT::i32 && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7832, __PRETTY_FUNCTION__)) | |||
7832 | "unexpected type for custom lowering DIV")((Op.getValueType() == MVT::i32 && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7832, __PRETTY_FUNCTION__)); | |||
7833 | SDLoc dl(Op); | |||
7834 | ||||
7835 | SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, | |||
7836 | DAG.getEntryNode(), Op.getOperand(1)); | |||
7837 | ||||
7838 | return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK); | |||
7839 | } | |||
7840 | ||||
7841 | static SDValue WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) { | |||
7842 | SDLoc DL(N); | |||
7843 | SDValue Op = N->getOperand(1); | |||
7844 | if (N->getValueType(0) == MVT::i32) | |||
7845 | return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, Op); | |||
7846 | SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op, | |||
7847 | DAG.getConstant(0, DL, MVT::i32)); | |||
7848 | SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op, | |||
7849 | DAG.getConstant(1, DL, MVT::i32)); | |||
7850 | return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, | |||
7851 | DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi)); | |||
7852 | } | |||
7853 | ||||
7854 | void ARMTargetLowering::ExpandDIV_Windows( | |||
7855 | SDValue Op, SelectionDAG &DAG, bool Signed, | |||
7856 | SmallVectorImpl<SDValue> &Results) const { | |||
7857 | const auto &DL = DAG.getDataLayout(); | |||
7858 | const auto &TLI = DAG.getTargetLoweringInfo(); | |||
7859 | ||||
7860 | assert(Op.getValueType() == MVT::i64 &&((Op.getValueType() == MVT::i64 && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i64 && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7861, __PRETTY_FUNCTION__)) | |||
7861 | "unexpected type for custom lowering DIV")((Op.getValueType() == MVT::i64 && "unexpected type for custom lowering DIV" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i64 && \"unexpected type for custom lowering DIV\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7861, __PRETTY_FUNCTION__)); | |||
7862 | SDLoc dl(Op); | |||
7863 | ||||
7864 | SDValue DBZCHK = WinDBZCheckDenominator(DAG, Op.getNode(), DAG.getEntryNode()); | |||
7865 | ||||
7866 | SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK); | |||
7867 | ||||
7868 | SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result); | |||
7869 | SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result, | |||
7870 | DAG.getConstant(32, dl, TLI.getPointerTy(DL))); | |||
7871 | Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper); | |||
7872 | ||||
7873 | Results.push_back(Lower); | |||
7874 | Results.push_back(Upper); | |||
7875 | } | |||
7876 | ||||
7877 | static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { | |||
7878 | if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering())) | |||
7879 | // Acquire/Release load/store is not legal for targets without a dmb or | |||
7880 | // equivalent available. | |||
7881 | return SDValue(); | |||
7882 | ||||
7883 | // Monotonic load/store is legal for all targets. | |||
7884 | return Op; | |||
7885 | } | |||
7886 | ||||
7887 | static void ReplaceREADCYCLECOUNTER(SDNode *N, | |||
7888 | SmallVectorImpl<SDValue> &Results, | |||
7889 | SelectionDAG &DAG, | |||
7890 | const ARMSubtarget *Subtarget) { | |||
7891 | SDLoc DL(N); | |||
7892 | // Under Power Management extensions, the cycle-count is: | |||
7893 | // mrc p15, #0, <Rt>, c9, c13, #0 | |||
7894 | SDValue Ops[] = { N->getOperand(0), // Chain | |||
7895 | DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32), | |||
7896 | DAG.getConstant(15, DL, MVT::i32), | |||
7897 | DAG.getConstant(0, DL, MVT::i32), | |||
7898 | DAG.getConstant(9, DL, MVT::i32), | |||
7899 | DAG.getConstant(13, DL, MVT::i32), | |||
7900 | DAG.getConstant(0, DL, MVT::i32) | |||
7901 | }; | |||
7902 | ||||
7903 | SDValue Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, | |||
7904 | DAG.getVTList(MVT::i32, MVT::Other), Ops); | |||
7905 | Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32, | |||
7906 | DAG.getConstant(0, DL, MVT::i32))); | |||
7907 | Results.push_back(Cycles32.getValue(1)); | |||
7908 | } | |||
7909 | ||||
7910 | static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) { | |||
7911 | SDLoc dl(V.getNode()); | |||
7912 | SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i32); | |||
7913 | SDValue VHi = DAG.getAnyExtOrTrunc( | |||
7914 | DAG.getNode(ISD::SRL, dl, MVT::i64, V, DAG.getConstant(32, dl, MVT::i32)), | |||
7915 | dl, MVT::i32); | |||
7916 | bool isBigEndian = DAG.getDataLayout().isBigEndian(); | |||
7917 | if (isBigEndian) | |||
7918 | std::swap (VLo, VHi); | |||
7919 | SDValue RegClass = | |||
7920 | DAG.getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); | |||
7921 | SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); | |||
7922 | SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); | |||
7923 | const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; | |||
7924 | return SDValue( | |||
7925 | DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); | |||
7926 | } | |||
7927 | ||||
7928 | static void ReplaceCMP_SWAP_64Results(SDNode *N, | |||
7929 | SmallVectorImpl<SDValue> & Results, | |||
7930 | SelectionDAG &DAG) { | |||
7931 | assert(N->getValueType(0) == MVT::i64 &&((N->getValueType(0) == MVT::i64 && "AtomicCmpSwap on types less than 64 should be legal" ) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"AtomicCmpSwap on types less than 64 should be legal\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7932, __PRETTY_FUNCTION__)) | |||
7932 | "AtomicCmpSwap on types less than 64 should be legal")((N->getValueType(0) == MVT::i64 && "AtomicCmpSwap on types less than 64 should be legal" ) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"AtomicCmpSwap on types less than 64 should be legal\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7932, __PRETTY_FUNCTION__)); | |||
7933 | SDValue Ops[] = {N->getOperand(1), | |||
7934 | createGPRPairNode(DAG, N->getOperand(2)), | |||
7935 | createGPRPairNode(DAG, N->getOperand(3)), | |||
7936 | N->getOperand(0)}; | |||
7937 | SDNode *CmpSwap = DAG.getMachineNode( | |||
7938 | ARM::CMP_SWAP_64, SDLoc(N), | |||
7939 | DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops); | |||
7940 | ||||
7941 | MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand(); | |||
7942 | DAG.setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp}); | |||
7943 | ||||
7944 | bool isBigEndian = DAG.getDataLayout().isBigEndian(); | |||
7945 | ||||
7946 | Results.push_back( | |||
7947 | DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_1 : ARM::gsub_0, | |||
7948 | SDLoc(N), MVT::i32, SDValue(CmpSwap, 0))); | |||
7949 | Results.push_back( | |||
7950 | DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_0 : ARM::gsub_1, | |||
7951 | SDLoc(N), MVT::i32, SDValue(CmpSwap, 0))); | |||
7952 | Results.push_back(SDValue(CmpSwap, 2)); | |||
7953 | } | |||
7954 | ||||
7955 | static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget, | |||
7956 | SelectionDAG &DAG) { | |||
7957 | const auto &TLI = DAG.getTargetLoweringInfo(); | |||
7958 | ||||
7959 | assert(Subtarget.getTargetTriple().isOSMSVCRT() &&((Subtarget.getTargetTriple().isOSMSVCRT() && "Custom lowering is MSVCRT specific!" ) ? static_cast<void> (0) : __assert_fail ("Subtarget.getTargetTriple().isOSMSVCRT() && \"Custom lowering is MSVCRT specific!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7960, __PRETTY_FUNCTION__)) | |||
7960 | "Custom lowering is MSVCRT specific!")((Subtarget.getTargetTriple().isOSMSVCRT() && "Custom lowering is MSVCRT specific!" ) ? static_cast<void> (0) : __assert_fail ("Subtarget.getTargetTriple().isOSMSVCRT() && \"Custom lowering is MSVCRT specific!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 7960, __PRETTY_FUNCTION__)); | |||
7961 | ||||
7962 | SDLoc dl(Op); | |||
7963 | SDValue Val = Op.getOperand(0); | |||
7964 | MVT Ty = Val->getSimpleValueType(0); | |||
7965 | SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, dl, Ty, Op.getOperand(1)); | |||
7966 | SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow", | |||
7967 | TLI.getPointerTy(DAG.getDataLayout())); | |||
7968 | ||||
7969 | TargetLowering::ArgListTy Args; | |||
7970 | TargetLowering::ArgListEntry Entry; | |||
7971 | ||||
7972 | Entry.Node = Val; | |||
7973 | Entry.Ty = Val.getValueType().getTypeForEVT(*DAG.getContext()); | |||
7974 | Entry.IsZExt = true; | |||
7975 | Args.push_back(Entry); | |||
7976 | ||||
7977 | Entry.Node = Exponent; | |||
7978 | Entry.Ty = Exponent.getValueType().getTypeForEVT(*DAG.getContext()); | |||
7979 | Entry.IsZExt = true; | |||
7980 | Args.push_back(Entry); | |||
7981 | ||||
7982 | Type *LCRTy = Val.getValueType().getTypeForEVT(*DAG.getContext()); | |||
7983 | ||||
7984 | // In the in-chain to the call is the entry node If we are emitting a | |||
7985 | // tailcall, the chain will be mutated if the node has a non-entry input | |||
7986 | // chain. | |||
7987 | SDValue InChain = DAG.getEntryNode(); | |||
7988 | SDValue TCChain = InChain; | |||
7989 | ||||
7990 | const Function &F = DAG.getMachineFunction().getFunction(); | |||
7991 | bool IsTC = TLI.isInTailCallPosition(DAG, Op.getNode(), TCChain) && | |||
7992 | F.getReturnType() == LCRTy; | |||
7993 | if (IsTC) | |||
7994 | InChain = TCChain; | |||
7995 | ||||
7996 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
7997 | CLI.setDebugLoc(dl) | |||
7998 | .setChain(InChain) | |||
7999 | .setCallee(CallingConv::ARM_AAPCS_VFP, LCRTy, Callee, std::move(Args)) | |||
8000 | .setTailCall(IsTC); | |||
8001 | std::pair<SDValue, SDValue> CI = TLI.LowerCallTo(CLI); | |||
8002 | ||||
8003 | // Return the chain (the DAG root) if it is a tail call | |||
8004 | return !CI.second.getNode() ? DAG.getRoot() : CI.first; | |||
8005 | } | |||
8006 | ||||
8007 | SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { | |||
8008 | LLVM_DEBUG(dbgs() << "Lowering node: "; Op.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { dbgs() << "Lowering node: "; Op.dump(); } } while (false); | |||
| ||||
8009 | switch (Op.getOpcode()) { | |||
8010 | default: llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8010); | |||
8011 | case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG); | |||
8012 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); | |||
8013 | case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); | |||
8014 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); | |||
8015 | case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); | |||
8016 | case ISD::SELECT: return LowerSELECT(Op, DAG); | |||
8017 | case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); | |||
8018 | case ISD::BRCOND: return LowerBRCOND(Op, DAG); | |||
8019 | case ISD::BR_CC: return LowerBR_CC(Op, DAG); | |||
8020 | case ISD::BR_JT: return LowerBR_JT(Op, DAG); | |||
8021 | case ISD::VASTART: return LowerVASTART(Op, DAG); | |||
8022 | case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); | |||
8023 | case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); | |||
8024 | case ISD::SINT_TO_FP: | |||
8025 | case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); | |||
8026 | case ISD::FP_TO_SINT: | |||
8027 | case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); | |||
8028 | case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); | |||
8029 | case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); | |||
8030 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); | |||
8031 | case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); | |||
8032 | case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); | |||
8033 | case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG); | |||
8034 | case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, | |||
8035 | Subtarget); | |||
8036 | case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG, Subtarget); | |||
8037 | case ISD::SHL: | |||
8038 | case ISD::SRL: | |||
8039 | case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); | |||
8040 | case ISD::SREM: return LowerREM(Op.getNode(), DAG); | |||
8041 | case ISD::UREM: return LowerREM(Op.getNode(), DAG); | |||
8042 | case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); | |||
8043 | case ISD::SRL_PARTS: | |||
8044 | case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); | |||
8045 | case ISD::CTTZ: | |||
8046 | case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget); | |||
8047 | case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget); | |||
8048 | case ISD::SETCC: return LowerVSETCC(Op, DAG); | |||
8049 | case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG); | |||
8050 | case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget); | |||
8051 | case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); | |||
8052 | case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); | |||
8053 | case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); | |||
8054 | case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); | |||
8055 | case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); | |||
8056 | case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); | |||
8057 | case ISD::MUL: return LowerMUL(Op, DAG); | |||
8058 | case ISD::SDIV: | |||
8059 | if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) | |||
8060 | return LowerDIV_Windows(Op, DAG, /* Signed */ true); | |||
8061 | return LowerSDIV(Op, DAG); | |||
8062 | case ISD::UDIV: | |||
8063 | if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) | |||
8064 | return LowerDIV_Windows(Op, DAG, /* Signed */ false); | |||
8065 | return LowerUDIV(Op, DAG); | |||
8066 | case ISD::ADDCARRY: | |||
8067 | case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG); | |||
8068 | case ISD::SADDO: | |||
8069 | case ISD::SSUBO: | |||
8070 | return LowerSignedALUO(Op, DAG); | |||
8071 | case ISD::UADDO: | |||
8072 | case ISD::USUBO: | |||
8073 | return LowerUnsignedALUO(Op, DAG); | |||
8074 | case ISD::ATOMIC_LOAD: | |||
8075 | case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); | |||
8076 | case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); | |||
8077 | case ISD::SDIVREM: | |||
8078 | case ISD::UDIVREM: return LowerDivRem(Op, DAG); | |||
8079 | case ISD::DYNAMIC_STACKALLOC: | |||
8080 | if (Subtarget->isTargetWindows()) | |||
8081 | return LowerDYNAMIC_STACKALLOC(Op, DAG); | |||
8082 | llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8082); | |||
8083 | case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); | |||
8084 | case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); | |||
8085 | case ISD::FPOWI: return LowerFPOWI(Op, *Subtarget, DAG); | |||
8086 | case ARMISD::WIN__DBZCHK: return SDValue(); | |||
8087 | } | |||
8088 | } | |||
8089 | ||||
8090 | static void ReplaceLongIntrinsic(SDNode *N, SmallVectorImpl<SDValue> &Results, | |||
8091 | SelectionDAG &DAG) { | |||
8092 | unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); | |||
8093 | unsigned Opc = 0; | |||
8094 | if (IntNo == Intrinsic::arm_smlald) | |||
8095 | Opc = ARMISD::SMLALD; | |||
8096 | else if (IntNo == Intrinsic::arm_smlaldx) | |||
8097 | Opc = ARMISD::SMLALDX; | |||
8098 | else if (IntNo == Intrinsic::arm_smlsld) | |||
8099 | Opc = ARMISD::SMLSLD; | |||
8100 | else if (IntNo == Intrinsic::arm_smlsldx) | |||
8101 | Opc = ARMISD::SMLSLDX; | |||
8102 | else | |||
8103 | return; | |||
8104 | ||||
8105 | SDLoc dl(N); | |||
8106 | SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, | |||
8107 | N->getOperand(3), | |||
8108 | DAG.getConstant(0, dl, MVT::i32)); | |||
8109 | SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, | |||
8110 | N->getOperand(3), | |||
8111 | DAG.getConstant(1, dl, MVT::i32)); | |||
8112 | ||||
8113 | SDValue LongMul = DAG.getNode(Opc, dl, | |||
8114 | DAG.getVTList(MVT::i32, MVT::i32), | |||
8115 | N->getOperand(1), N->getOperand(2), | |||
8116 | Lo, Hi); | |||
8117 | Results.push_back(LongMul.getValue(0)); | |||
8118 | Results.push_back(LongMul.getValue(1)); | |||
8119 | } | |||
8120 | ||||
8121 | /// ReplaceNodeResults - Replace the results of node with an illegal result | |||
8122 | /// type with new values built out of custom code. | |||
8123 | void ARMTargetLowering::ReplaceNodeResults(SDNode *N, | |||
8124 | SmallVectorImpl<SDValue> &Results, | |||
8125 | SelectionDAG &DAG) const { | |||
8126 | SDValue Res; | |||
8127 | switch (N->getOpcode()) { | |||
8128 | default: | |||
8129 | llvm_unreachable("Don't know how to custom expand this!")::llvm::llvm_unreachable_internal("Don't know how to custom expand this!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8129); | |||
8130 | case ISD::READ_REGISTER: | |||
8131 | ExpandREAD_REGISTER(N, Results, DAG); | |||
8132 | break; | |||
8133 | case ISD::BITCAST: | |||
8134 | Res = ExpandBITCAST(N, DAG, Subtarget); | |||
8135 | break; | |||
8136 | case ISD::SRL: | |||
8137 | case ISD::SRA: | |||
8138 | Res = Expand64BitShift(N, DAG, Subtarget); | |||
8139 | break; | |||
8140 | case ISD::SREM: | |||
8141 | case ISD::UREM: | |||
8142 | Res = LowerREM(N, DAG); | |||
8143 | break; | |||
8144 | case ISD::SDIVREM: | |||
8145 | case ISD::UDIVREM: | |||
8146 | Res = LowerDivRem(SDValue(N, 0), DAG); | |||
8147 | assert(Res.getNumOperands() == 2 && "DivRem needs two values")((Res.getNumOperands() == 2 && "DivRem needs two values" ) ? static_cast<void> (0) : __assert_fail ("Res.getNumOperands() == 2 && \"DivRem needs two values\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8147, __PRETTY_FUNCTION__)); | |||
8148 | Results.push_back(Res.getValue(0)); | |||
8149 | Results.push_back(Res.getValue(1)); | |||
8150 | return; | |||
8151 | case ISD::READCYCLECOUNTER: | |||
8152 | ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget); | |||
8153 | return; | |||
8154 | case ISD::UDIV: | |||
8155 | case ISD::SDIV: | |||
8156 | assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows")((Subtarget->isTargetWindows() && "can only expand DIV on Windows" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"can only expand DIV on Windows\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8156, __PRETTY_FUNCTION__)); | |||
8157 | return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, | |||
8158 | Results); | |||
8159 | case ISD::ATOMIC_CMP_SWAP: | |||
8160 | ReplaceCMP_SWAP_64Results(N, Results, DAG); | |||
8161 | return; | |||
8162 | case ISD::INTRINSIC_WO_CHAIN: | |||
8163 | return ReplaceLongIntrinsic(N, Results, DAG); | |||
8164 | case ISD::ABS: | |||
8165 | lowerABS(N, Results, DAG); | |||
8166 | return ; | |||
8167 | ||||
8168 | } | |||
8169 | if (Res.getNode()) | |||
8170 | Results.push_back(Res); | |||
8171 | } | |||
8172 | ||||
8173 | //===----------------------------------------------------------------------===// | |||
8174 | // ARM Scheduler Hooks | |||
8175 | //===----------------------------------------------------------------------===// | |||
8176 | ||||
8177 | /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and | |||
8178 | /// registers the function context. | |||
8179 | void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI, | |||
8180 | MachineBasicBlock *MBB, | |||
8181 | MachineBasicBlock *DispatchBB, | |||
8182 | int FI) const { | |||
8183 | assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported with SjLj") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported with SjLj\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8184, __PRETTY_FUNCTION__)) | |||
8184 | "ROPI/RWPI not currently supported with SjLj")((!Subtarget->isROPI() && !Subtarget->isRWPI() && "ROPI/RWPI not currently supported with SjLj") ? static_cast <void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported with SjLj\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8184, __PRETTY_FUNCTION__)); | |||
8185 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
8186 | DebugLoc dl = MI.getDebugLoc(); | |||
8187 | MachineFunction *MF = MBB->getParent(); | |||
8188 | MachineRegisterInfo *MRI = &MF->getRegInfo(); | |||
8189 | MachineConstantPool *MCP = MF->getConstantPool(); | |||
8190 | ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); | |||
8191 | const Function &F = MF->getFunction(); | |||
8192 | ||||
8193 | bool isThumb = Subtarget->isThumb(); | |||
8194 | bool isThumb2 = Subtarget->isThumb2(); | |||
8195 | ||||
8196 | unsigned PCLabelId = AFI->createPICLabelUId(); | |||
8197 | unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; | |||
8198 | ARMConstantPoolValue *CPV = | |||
8199 | ARMConstantPoolMBB::Create(F.getContext(), DispatchBB, PCLabelId, PCAdj); | |||
8200 | unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); | |||
8201 | ||||
8202 | const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass | |||
8203 | : &ARM::GPRRegClass; | |||
8204 | ||||
8205 | // Grab constant pool and fixed stack memory operands. | |||
8206 | MachineMemOperand *CPMMO = | |||
8207 | MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF), | |||
8208 | MachineMemOperand::MOLoad, 4, 4); | |||
8209 | ||||
8210 | MachineMemOperand *FIMMOSt = | |||
8211 | MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), | |||
8212 | MachineMemOperand::MOStore, 4, 4); | |||
8213 | ||||
8214 | // Load the address of the dispatch MBB into the jump buffer. | |||
8215 | if (isThumb2) { | |||
8216 | // Incoming value: jbuf | |||
8217 | // ldr.n r5, LCPI1_1 | |||
8218 | // orr r5, r5, #1 | |||
8219 | // add r5, pc | |||
8220 | // str r5, [$jbuf, #+4] ; &jbuf[1] | |||
8221 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8222 | BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) | |||
8223 | .addConstantPoolIndex(CPI) | |||
8224 | .addMemOperand(CPMMO) | |||
8225 | .add(predOps(ARMCC::AL)); | |||
8226 | // Set the low bit because of thumb mode. | |||
8227 | unsigned NewVReg2 = MRI->createVirtualRegister(TRC); | |||
8228 | BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) | |||
8229 | .addReg(NewVReg1, RegState::Kill) | |||
8230 | .addImm(0x01) | |||
8231 | .add(predOps(ARMCC::AL)) | |||
8232 | .add(condCodeOp()); | |||
8233 | unsigned NewVReg3 = MRI->createVirtualRegister(TRC); | |||
8234 | BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) | |||
8235 | .addReg(NewVReg2, RegState::Kill) | |||
8236 | .addImm(PCLabelId); | |||
8237 | BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) | |||
8238 | .addReg(NewVReg3, RegState::Kill) | |||
8239 | .addFrameIndex(FI) | |||
8240 | .addImm(36) // &jbuf[1] :: pc | |||
8241 | .addMemOperand(FIMMOSt) | |||
8242 | .add(predOps(ARMCC::AL)); | |||
8243 | } else if (isThumb) { | |||
8244 | // Incoming value: jbuf | |||
8245 | // ldr.n r1, LCPI1_4 | |||
8246 | // add r1, pc | |||
8247 | // mov r2, #1 | |||
8248 | // orrs r1, r2 | |||
8249 | // add r2, $jbuf, #+4 ; &jbuf[1] | |||
8250 | // str r1, [r2] | |||
8251 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8252 | BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) | |||
8253 | .addConstantPoolIndex(CPI) | |||
8254 | .addMemOperand(CPMMO) | |||
8255 | .add(predOps(ARMCC::AL)); | |||
8256 | unsigned NewVReg2 = MRI->createVirtualRegister(TRC); | |||
8257 | BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) | |||
8258 | .addReg(NewVReg1, RegState::Kill) | |||
8259 | .addImm(PCLabelId); | |||
8260 | // Set the low bit because of thumb mode. | |||
8261 | unsigned NewVReg3 = MRI->createVirtualRegister(TRC); | |||
8262 | BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) | |||
8263 | .addReg(ARM::CPSR, RegState::Define) | |||
8264 | .addImm(1) | |||
8265 | .add(predOps(ARMCC::AL)); | |||
8266 | unsigned NewVReg4 = MRI->createVirtualRegister(TRC); | |||
8267 | BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) | |||
8268 | .addReg(ARM::CPSR, RegState::Define) | |||
8269 | .addReg(NewVReg2, RegState::Kill) | |||
8270 | .addReg(NewVReg3, RegState::Kill) | |||
8271 | .add(predOps(ARMCC::AL)); | |||
8272 | unsigned NewVReg5 = MRI->createVirtualRegister(TRC); | |||
8273 | BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5) | |||
8274 | .addFrameIndex(FI) | |||
8275 | .addImm(36); // &jbuf[1] :: pc | |||
8276 | BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) | |||
8277 | .addReg(NewVReg4, RegState::Kill) | |||
8278 | .addReg(NewVReg5, RegState::Kill) | |||
8279 | .addImm(0) | |||
8280 | .addMemOperand(FIMMOSt) | |||
8281 | .add(predOps(ARMCC::AL)); | |||
8282 | } else { | |||
8283 | // Incoming value: jbuf | |||
8284 | // ldr r1, LCPI1_1 | |||
8285 | // add r1, pc, r1 | |||
8286 | // str r1, [$jbuf, #+4] ; &jbuf[1] | |||
8287 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8288 | BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) | |||
8289 | .addConstantPoolIndex(CPI) | |||
8290 | .addImm(0) | |||
8291 | .addMemOperand(CPMMO) | |||
8292 | .add(predOps(ARMCC::AL)); | |||
8293 | unsigned NewVReg2 = MRI->createVirtualRegister(TRC); | |||
8294 | BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) | |||
8295 | .addReg(NewVReg1, RegState::Kill) | |||
8296 | .addImm(PCLabelId) | |||
8297 | .add(predOps(ARMCC::AL)); | |||
8298 | BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) | |||
8299 | .addReg(NewVReg2, RegState::Kill) | |||
8300 | .addFrameIndex(FI) | |||
8301 | .addImm(36) // &jbuf[1] :: pc | |||
8302 | .addMemOperand(FIMMOSt) | |||
8303 | .add(predOps(ARMCC::AL)); | |||
8304 | } | |||
8305 | } | |||
8306 | ||||
8307 | void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, | |||
8308 | MachineBasicBlock *MBB) const { | |||
8309 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
8310 | DebugLoc dl = MI.getDebugLoc(); | |||
8311 | MachineFunction *MF = MBB->getParent(); | |||
8312 | MachineRegisterInfo *MRI = &MF->getRegInfo(); | |||
8313 | MachineFrameInfo &MFI = MF->getFrameInfo(); | |||
8314 | int FI = MFI.getFunctionContextIndex(); | |||
8315 | ||||
8316 | const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass | |||
8317 | : &ARM::GPRnopcRegClass; | |||
8318 | ||||
8319 | // Get a mapping of the call site numbers to all of the landing pads they're | |||
8320 | // associated with. | |||
8321 | DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2>> CallSiteNumToLPad; | |||
8322 | unsigned MaxCSNum = 0; | |||
8323 | for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; | |||
8324 | ++BB) { | |||
8325 | if (!BB->isEHPad()) continue; | |||
8326 | ||||
8327 | // FIXME: We should assert that the EH_LABEL is the first MI in the landing | |||
8328 | // pad. | |||
8329 | for (MachineBasicBlock::iterator | |||
8330 | II = BB->begin(), IE = BB->end(); II != IE; ++II) { | |||
8331 | if (!II->isEHLabel()) continue; | |||
8332 | ||||
8333 | MCSymbol *Sym = II->getOperand(0).getMCSymbol(); | |||
8334 | if (!MF->hasCallSiteLandingPad(Sym)) continue; | |||
8335 | ||||
8336 | SmallVectorImpl<unsigned> &CallSiteIdxs = MF->getCallSiteLandingPad(Sym); | |||
8337 | for (SmallVectorImpl<unsigned>::iterator | |||
8338 | CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); | |||
8339 | CSI != CSE; ++CSI) { | |||
8340 | CallSiteNumToLPad[*CSI].push_back(&*BB); | |||
8341 | MaxCSNum = std::max(MaxCSNum, *CSI); | |||
8342 | } | |||
8343 | break; | |||
8344 | } | |||
8345 | } | |||
8346 | ||||
8347 | // Get an ordered list of the machine basic blocks for the jump table. | |||
8348 | std::vector<MachineBasicBlock*> LPadList; | |||
8349 | SmallPtrSet<MachineBasicBlock*, 32> InvokeBBs; | |||
8350 | LPadList.reserve(CallSiteNumToLPad.size()); | |||
8351 | for (unsigned I = 1; I <= MaxCSNum; ++I) { | |||
8352 | SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; | |||
8353 | for (SmallVectorImpl<MachineBasicBlock*>::iterator | |||
8354 | II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) { | |||
8355 | LPadList.push_back(*II); | |||
8356 | InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end()); | |||
8357 | } | |||
8358 | } | |||
8359 | ||||
8360 | assert(!LPadList.empty() &&((!LPadList.empty() && "No landing pad destinations for the dispatch jump table!" ) ? static_cast<void> (0) : __assert_fail ("!LPadList.empty() && \"No landing pad destinations for the dispatch jump table!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8361, __PRETTY_FUNCTION__)) | |||
8361 | "No landing pad destinations for the dispatch jump table!")((!LPadList.empty() && "No landing pad destinations for the dispatch jump table!" ) ? static_cast<void> (0) : __assert_fail ("!LPadList.empty() && \"No landing pad destinations for the dispatch jump table!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8361, __PRETTY_FUNCTION__)); | |||
8362 | ||||
8363 | // Create the jump table and associated information. | |||
8364 | MachineJumpTableInfo *JTI = | |||
8365 | MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); | |||
8366 | unsigned MJTI = JTI->createJumpTableIndex(LPadList); | |||
8367 | ||||
8368 | // Create the MBBs for the dispatch code. | |||
8369 | ||||
8370 | // Shove the dispatch's address into the return slot in the function context. | |||
8371 | MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); | |||
8372 | DispatchBB->setIsEHPad(); | |||
8373 | ||||
8374 | MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); | |||
8375 | unsigned trap_opcode; | |||
8376 | if (Subtarget->isThumb()) | |||
8377 | trap_opcode = ARM::tTRAP; | |||
8378 | else | |||
8379 | trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP; | |||
8380 | ||||
8381 | BuildMI(TrapBB, dl, TII->get(trap_opcode)); | |||
8382 | DispatchBB->addSuccessor(TrapBB); | |||
8383 | ||||
8384 | MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); | |||
8385 | DispatchBB->addSuccessor(DispContBB); | |||
8386 | ||||
8387 | // Insert and MBBs. | |||
8388 | MF->insert(MF->end(), DispatchBB); | |||
8389 | MF->insert(MF->end(), DispContBB); | |||
8390 | MF->insert(MF->end(), TrapBB); | |||
8391 | ||||
8392 | // Insert code into the entry block that creates and registers the function | |||
8393 | // context. | |||
8394 | SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); | |||
8395 | ||||
8396 | MachineMemOperand *FIMMOLd = MF->getMachineMemOperand( | |||
8397 | MachinePointerInfo::getFixedStack(*MF, FI), | |||
8398 | MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 4, 4); | |||
8399 | ||||
8400 | MachineInstrBuilder MIB; | |||
8401 | MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup)); | |||
8402 | ||||
8403 | const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); | |||
8404 | const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); | |||
8405 | ||||
8406 | // Add a register mask with no preserved registers. This results in all | |||
8407 | // registers being marked as clobbered. This can't work if the dispatch block | |||
8408 | // is in a Thumb1 function and is linked with ARM code which uses the FP | |||
8409 | // registers, as there is no way to preserve the FP registers in Thumb1 mode. | |||
8410 | MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF)); | |||
8411 | ||||
8412 | bool IsPositionIndependent = isPositionIndependent(); | |||
8413 | unsigned NumLPads = LPadList.size(); | |||
8414 | if (Subtarget->isThumb2()) { | |||
8415 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8416 | BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) | |||
8417 | .addFrameIndex(FI) | |||
8418 | .addImm(4) | |||
8419 | .addMemOperand(FIMMOLd) | |||
8420 | .add(predOps(ARMCC::AL)); | |||
8421 | ||||
8422 | if (NumLPads < 256) { | |||
8423 | BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) | |||
8424 | .addReg(NewVReg1) | |||
8425 | .addImm(LPadList.size()) | |||
8426 | .add(predOps(ARMCC::AL)); | |||
8427 | } else { | |||
8428 | unsigned VReg1 = MRI->createVirtualRegister(TRC); | |||
8429 | BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) | |||
8430 | .addImm(NumLPads & 0xFFFF) | |||
8431 | .add(predOps(ARMCC::AL)); | |||
8432 | ||||
8433 | unsigned VReg2 = VReg1; | |||
8434 | if ((NumLPads & 0xFFFF0000) != 0) { | |||
8435 | VReg2 = MRI->createVirtualRegister(TRC); | |||
8436 | BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2) | |||
8437 | .addReg(VReg1) | |||
8438 | .addImm(NumLPads >> 16) | |||
8439 | .add(predOps(ARMCC::AL)); | |||
8440 | } | |||
8441 | ||||
8442 | BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr)) | |||
8443 | .addReg(NewVReg1) | |||
8444 | .addReg(VReg2) | |||
8445 | .add(predOps(ARMCC::AL)); | |||
8446 | } | |||
8447 | ||||
8448 | BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) | |||
8449 | .addMBB(TrapBB) | |||
8450 | .addImm(ARMCC::HI) | |||
8451 | .addReg(ARM::CPSR); | |||
8452 | ||||
8453 | unsigned NewVReg3 = MRI->createVirtualRegister(TRC); | |||
8454 | BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3) | |||
8455 | .addJumpTableIndex(MJTI) | |||
8456 | .add(predOps(ARMCC::AL)); | |||
8457 | ||||
8458 | unsigned NewVReg4 = MRI->createVirtualRegister(TRC); | |||
8459 | BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4) | |||
8460 | .addReg(NewVReg3, RegState::Kill) | |||
8461 | .addReg(NewVReg1) | |||
8462 | .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)) | |||
8463 | .add(predOps(ARMCC::AL)) | |||
8464 | .add(condCodeOp()); | |||
8465 | ||||
8466 | BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) | |||
8467 | .addReg(NewVReg4, RegState::Kill) | |||
8468 | .addReg(NewVReg1) | |||
8469 | .addJumpTableIndex(MJTI); | |||
8470 | } else if (Subtarget->isThumb()) { | |||
8471 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8472 | BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) | |||
8473 | .addFrameIndex(FI) | |||
8474 | .addImm(1) | |||
8475 | .addMemOperand(FIMMOLd) | |||
8476 | .add(predOps(ARMCC::AL)); | |||
8477 | ||||
8478 | if (NumLPads < 256) { | |||
8479 | BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) | |||
8480 | .addReg(NewVReg1) | |||
8481 | .addImm(NumLPads) | |||
8482 | .add(predOps(ARMCC::AL)); | |||
8483 | } else { | |||
8484 | MachineConstantPool *ConstantPool = MF->getConstantPool(); | |||
8485 | Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext()); | |||
8486 | const Constant *C = ConstantInt::get(Int32Ty, NumLPads); | |||
8487 | ||||
8488 | // MachineConstantPool wants an explicit alignment. | |||
8489 | unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty); | |||
8490 | if (Align == 0) | |||
8491 | Align = MF->getDataLayout().getTypeAllocSize(C->getType()); | |||
8492 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); | |||
8493 | ||||
8494 | unsigned VReg1 = MRI->createVirtualRegister(TRC); | |||
8495 | BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci)) | |||
8496 | .addReg(VReg1, RegState::Define) | |||
8497 | .addConstantPoolIndex(Idx) | |||
8498 | .add(predOps(ARMCC::AL)); | |||
8499 | BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr)) | |||
8500 | .addReg(NewVReg1) | |||
8501 | .addReg(VReg1) | |||
8502 | .add(predOps(ARMCC::AL)); | |||
8503 | } | |||
8504 | ||||
8505 | BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) | |||
8506 | .addMBB(TrapBB) | |||
8507 | .addImm(ARMCC::HI) | |||
8508 | .addReg(ARM::CPSR); | |||
8509 | ||||
8510 | unsigned NewVReg2 = MRI->createVirtualRegister(TRC); | |||
8511 | BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) | |||
8512 | .addReg(ARM::CPSR, RegState::Define) | |||
8513 | .addReg(NewVReg1) | |||
8514 | .addImm(2) | |||
8515 | .add(predOps(ARMCC::AL)); | |||
8516 | ||||
8517 | unsigned NewVReg3 = MRI->createVirtualRegister(TRC); | |||
8518 | BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) | |||
8519 | .addJumpTableIndex(MJTI) | |||
8520 | .add(predOps(ARMCC::AL)); | |||
8521 | ||||
8522 | unsigned NewVReg4 = MRI->createVirtualRegister(TRC); | |||
8523 | BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) | |||
8524 | .addReg(ARM::CPSR, RegState::Define) | |||
8525 | .addReg(NewVReg2, RegState::Kill) | |||
8526 | .addReg(NewVReg3) | |||
8527 | .add(predOps(ARMCC::AL)); | |||
8528 | ||||
8529 | MachineMemOperand *JTMMOLd = MF->getMachineMemOperand( | |||
8530 | MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4); | |||
8531 | ||||
8532 | unsigned NewVReg5 = MRI->createVirtualRegister(TRC); | |||
8533 | BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) | |||
8534 | .addReg(NewVReg4, RegState::Kill) | |||
8535 | .addImm(0) | |||
8536 | .addMemOperand(JTMMOLd) | |||
8537 | .add(predOps(ARMCC::AL)); | |||
8538 | ||||
8539 | unsigned NewVReg6 = NewVReg5; | |||
8540 | if (IsPositionIndependent) { | |||
8541 | NewVReg6 = MRI->createVirtualRegister(TRC); | |||
8542 | BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) | |||
8543 | .addReg(ARM::CPSR, RegState::Define) | |||
8544 | .addReg(NewVReg5, RegState::Kill) | |||
8545 | .addReg(NewVReg3) | |||
8546 | .add(predOps(ARMCC::AL)); | |||
8547 | } | |||
8548 | ||||
8549 | BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) | |||
8550 | .addReg(NewVReg6, RegState::Kill) | |||
8551 | .addJumpTableIndex(MJTI); | |||
8552 | } else { | |||
8553 | unsigned NewVReg1 = MRI->createVirtualRegister(TRC); | |||
8554 | BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) | |||
8555 | .addFrameIndex(FI) | |||
8556 | .addImm(4) | |||
8557 | .addMemOperand(FIMMOLd) | |||
8558 | .add(predOps(ARMCC::AL)); | |||
8559 | ||||
8560 | if (NumLPads < 256) { | |||
8561 | BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) | |||
8562 | .addReg(NewVReg1) | |||
8563 | .addImm(NumLPads) | |||
8564 | .add(predOps(ARMCC::AL)); | |||
8565 | } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) { | |||
8566 | unsigned VReg1 = MRI->createVirtualRegister(TRC); | |||
8567 | BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) | |||
8568 | .addImm(NumLPads & 0xFFFF) | |||
8569 | .add(predOps(ARMCC::AL)); | |||
8570 | ||||
8571 | unsigned VReg2 = VReg1; | |||
8572 | if ((NumLPads & 0xFFFF0000) != 0) { | |||
8573 | VReg2 = MRI->createVirtualRegister(TRC); | |||
8574 | BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2) | |||
8575 | .addReg(VReg1) | |||
8576 | .addImm(NumLPads >> 16) | |||
8577 | .add(predOps(ARMCC::AL)); | |||
8578 | } | |||
8579 | ||||
8580 | BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) | |||
8581 | .addReg(NewVReg1) | |||
8582 | .addReg(VReg2) | |||
8583 | .add(predOps(ARMCC::AL)); | |||
8584 | } else { | |||
8585 | MachineConstantPool *ConstantPool = MF->getConstantPool(); | |||
8586 | Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext()); | |||
8587 | const Constant *C = ConstantInt::get(Int32Ty, NumLPads); | |||
8588 | ||||
8589 | // MachineConstantPool wants an explicit alignment. | |||
8590 | unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty); | |||
8591 | if (Align == 0) | |||
8592 | Align = MF->getDataLayout().getTypeAllocSize(C->getType()); | |||
8593 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); | |||
8594 | ||||
8595 | unsigned VReg1 = MRI->createVirtualRegister(TRC); | |||
8596 | BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp)) | |||
8597 | .addReg(VReg1, RegState::Define) | |||
8598 | .addConstantPoolIndex(Idx) | |||
8599 | .addImm(0) | |||
8600 | .add(predOps(ARMCC::AL)); | |||
8601 | BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) | |||
8602 | .addReg(NewVReg1) | |||
8603 | .addReg(VReg1, RegState::Kill) | |||
8604 | .add(predOps(ARMCC::AL)); | |||
8605 | } | |||
8606 | ||||
8607 | BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) | |||
8608 | .addMBB(TrapBB) | |||
8609 | .addImm(ARMCC::HI) | |||
8610 | .addReg(ARM::CPSR); | |||
8611 | ||||
8612 | unsigned NewVReg3 = MRI->createVirtualRegister(TRC); | |||
8613 | BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3) | |||
8614 | .addReg(NewVReg1) | |||
8615 | .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)) | |||
8616 | .add(predOps(ARMCC::AL)) | |||
8617 | .add(condCodeOp()); | |||
8618 | unsigned NewVReg4 = MRI->createVirtualRegister(TRC); | |||
8619 | BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4) | |||
8620 | .addJumpTableIndex(MJTI) | |||
8621 | .add(predOps(ARMCC::AL)); | |||
8622 | ||||
8623 | MachineMemOperand *JTMMOLd = MF->getMachineMemOperand( | |||
8624 | MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4); | |||
8625 | unsigned NewVReg5 = MRI->createVirtualRegister(TRC); | |||
8626 | BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5) | |||
8627 | .addReg(NewVReg3, RegState::Kill) | |||
8628 | .addReg(NewVReg4) | |||
8629 | .addImm(0) | |||
8630 | .addMemOperand(JTMMOLd) | |||
8631 | .add(predOps(ARMCC::AL)); | |||
8632 | ||||
8633 | if (IsPositionIndependent) { | |||
8634 | BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) | |||
8635 | .addReg(NewVReg5, RegState::Kill) | |||
8636 | .addReg(NewVReg4) | |||
8637 | .addJumpTableIndex(MJTI); | |||
8638 | } else { | |||
8639 | BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr)) | |||
8640 | .addReg(NewVReg5, RegState::Kill) | |||
8641 | .addJumpTableIndex(MJTI); | |||
8642 | } | |||
8643 | } | |||
8644 | ||||
8645 | // Add the jump table entries as successors to the MBB. | |||
8646 | SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs; | |||
8647 | for (std::vector<MachineBasicBlock*>::iterator | |||
8648 | I = LPadList.begin(), E = LPadList.end(); I != E; ++I) { | |||
8649 | MachineBasicBlock *CurMBB = *I; | |||
8650 | if (SeenMBBs.insert(CurMBB).second) | |||
8651 | DispContBB->addSuccessor(CurMBB); | |||
8652 | } | |||
8653 | ||||
8654 | // N.B. the order the invoke BBs are processed in doesn't matter here. | |||
8655 | const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF); | |||
8656 | SmallVector<MachineBasicBlock*, 64> MBBLPads; | |||
8657 | for (MachineBasicBlock *BB : InvokeBBs) { | |||
8658 | ||||
8659 | // Remove the landing pad successor from the invoke block and replace it | |||
8660 | // with the new dispatch block. | |||
8661 | SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(), | |||
8662 | BB->succ_end()); | |||
8663 | while (!Successors.empty()) { | |||
8664 | MachineBasicBlock *SMBB = Successors.pop_back_val(); | |||
8665 | if (SMBB->isEHPad()) { | |||
8666 | BB->removeSuccessor(SMBB); | |||
8667 | MBBLPads.push_back(SMBB); | |||
8668 | } | |||
8669 | } | |||
8670 | ||||
8671 | BB->addSuccessor(DispatchBB, BranchProbability::getZero()); | |||
8672 | BB->normalizeSuccProbs(); | |||
8673 | ||||
8674 | // Find the invoke call and mark all of the callee-saved registers as | |||
8675 | // 'implicit defined' so that they're spilled. This prevents code from | |||
8676 | // moving instructions to before the EH block, where they will never be | |||
8677 | // executed. | |||
8678 | for (MachineBasicBlock::reverse_iterator | |||
8679 | II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) { | |||
8680 | if (!II->isCall()) continue; | |||
8681 | ||||
8682 | DenseMap<unsigned, bool> DefRegs; | |||
8683 | for (MachineInstr::mop_iterator | |||
8684 | OI = II->operands_begin(), OE = II->operands_end(); | |||
8685 | OI != OE; ++OI) { | |||
8686 | if (!OI->isReg()) continue; | |||
8687 | DefRegs[OI->getReg()] = true; | |||
8688 | } | |||
8689 | ||||
8690 | MachineInstrBuilder MIB(*MF, &*II); | |||
8691 | ||||
8692 | for (unsigned i = 0; SavedRegs[i] != 0; ++i) { | |||
8693 | unsigned Reg = SavedRegs[i]; | |||
8694 | if (Subtarget->isThumb2() && | |||
8695 | !ARM::tGPRRegClass.contains(Reg) && | |||
8696 | !ARM::hGPRRegClass.contains(Reg)) | |||
8697 | continue; | |||
8698 | if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg)) | |||
8699 | continue; | |||
8700 | if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg)) | |||
8701 | continue; | |||
8702 | if (!DefRegs[Reg]) | |||
8703 | MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); | |||
8704 | } | |||
8705 | ||||
8706 | break; | |||
8707 | } | |||
8708 | } | |||
8709 | ||||
8710 | // Mark all former landing pads as non-landing pads. The dispatch is the only | |||
8711 | // landing pad now. | |||
8712 | for (SmallVectorImpl<MachineBasicBlock*>::iterator | |||
8713 | I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I) | |||
8714 | (*I)->setIsEHPad(false); | |||
8715 | ||||
8716 | // The instruction is gone now. | |||
8717 | MI.eraseFromParent(); | |||
8718 | } | |||
8719 | ||||
8720 | static | |||
8721 | MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { | |||
8722 | for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), | |||
8723 | E = MBB->succ_end(); I != E; ++I) | |||
8724 | if (*I != Succ) | |||
8725 | return *I; | |||
8726 | llvm_unreachable("Expecting a BB with two successors!")::llvm::llvm_unreachable_internal("Expecting a BB with two successors!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8726); | |||
8727 | } | |||
8728 | ||||
8729 | /// Return the load opcode for a given load size. If load size >= 8, | |||
8730 | /// neon opcode will be returned. | |||
8731 | static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) { | |||
8732 | if (LdSize >= 8) | |||
8733 | return LdSize == 16 ? ARM::VLD1q32wb_fixed | |||
8734 | : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0; | |||
8735 | if (IsThumb1) | |||
8736 | return LdSize == 4 ? ARM::tLDRi | |||
8737 | : LdSize == 2 ? ARM::tLDRHi | |||
8738 | : LdSize == 1 ? ARM::tLDRBi : 0; | |||
8739 | if (IsThumb2) | |||
8740 | return LdSize == 4 ? ARM::t2LDR_POST | |||
8741 | : LdSize == 2 ? ARM::t2LDRH_POST | |||
8742 | : LdSize == 1 ? ARM::t2LDRB_POST : 0; | |||
8743 | return LdSize == 4 ? ARM::LDR_POST_IMM | |||
8744 | : LdSize == 2 ? ARM::LDRH_POST | |||
8745 | : LdSize == 1 ? ARM::LDRB_POST_IMM : 0; | |||
8746 | } | |||
8747 | ||||
8748 | /// Return the store opcode for a given store size. If store size >= 8, | |||
8749 | /// neon opcode will be returned. | |||
8750 | static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) { | |||
8751 | if (StSize >= 8) | |||
8752 | return StSize == 16 ? ARM::VST1q32wb_fixed | |||
8753 | : StSize == 8 ? ARM::VST1d32wb_fixed : 0; | |||
8754 | if (IsThumb1) | |||
8755 | return StSize == 4 ? ARM::tSTRi | |||
8756 | : StSize == 2 ? ARM::tSTRHi | |||
8757 | : StSize == 1 ? ARM::tSTRBi : 0; | |||
8758 | if (IsThumb2) | |||
8759 | return StSize == 4 ? ARM::t2STR_POST | |||
8760 | : StSize == 2 ? ARM::t2STRH_POST | |||
8761 | : StSize == 1 ? ARM::t2STRB_POST : 0; | |||
8762 | return StSize == 4 ? ARM::STR_POST_IMM | |||
8763 | : StSize == 2 ? ARM::STRH_POST | |||
8764 | : StSize == 1 ? ARM::STRB_POST_IMM : 0; | |||
8765 | } | |||
8766 | ||||
8767 | /// Emit a post-increment load operation with given size. The instructions | |||
8768 | /// will be added to BB at Pos. | |||
8769 | static void emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, | |||
8770 | const TargetInstrInfo *TII, const DebugLoc &dl, | |||
8771 | unsigned LdSize, unsigned Data, unsigned AddrIn, | |||
8772 | unsigned AddrOut, bool IsThumb1, bool IsThumb2) { | |||
8773 | unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2); | |||
8774 | assert(LdOpc != 0 && "Should have a load opcode")((LdOpc != 0 && "Should have a load opcode") ? static_cast <void> (0) : __assert_fail ("LdOpc != 0 && \"Should have a load opcode\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8774, __PRETTY_FUNCTION__)); | |||
8775 | if (LdSize >= 8) { | |||
8776 | BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data) | |||
8777 | .addReg(AddrOut, RegState::Define) | |||
8778 | .addReg(AddrIn) | |||
8779 | .addImm(0) | |||
8780 | .add(predOps(ARMCC::AL)); | |||
8781 | } else if (IsThumb1) { | |||
8782 | // load + update AddrIn | |||
8783 | BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data) | |||
8784 | .addReg(AddrIn) | |||
8785 | .addImm(0) | |||
8786 | .add(predOps(ARMCC::AL)); | |||
8787 | BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut) | |||
8788 | .add(t1CondCodeOp()) | |||
8789 | .addReg(AddrIn) | |||
8790 | .addImm(LdSize) | |||
8791 | .add(predOps(ARMCC::AL)); | |||
8792 | } else if (IsThumb2) { | |||
8793 | BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data) | |||
8794 | .addReg(AddrOut, RegState::Define) | |||
8795 | .addReg(AddrIn) | |||
8796 | .addImm(LdSize) | |||
8797 | .add(predOps(ARMCC::AL)); | |||
8798 | } else { // arm | |||
8799 | BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data) | |||
8800 | .addReg(AddrOut, RegState::Define) | |||
8801 | .addReg(AddrIn) | |||
8802 | .addReg(0) | |||
8803 | .addImm(LdSize) | |||
8804 | .add(predOps(ARMCC::AL)); | |||
8805 | } | |||
8806 | } | |||
8807 | ||||
8808 | /// Emit a post-increment store operation with given size. The instructions | |||
8809 | /// will be added to BB at Pos. | |||
8810 | static void emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, | |||
8811 | const TargetInstrInfo *TII, const DebugLoc &dl, | |||
8812 | unsigned StSize, unsigned Data, unsigned AddrIn, | |||
8813 | unsigned AddrOut, bool IsThumb1, bool IsThumb2) { | |||
8814 | unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2); | |||
8815 | assert(StOpc != 0 && "Should have a store opcode")((StOpc != 0 && "Should have a store opcode") ? static_cast <void> (0) : __assert_fail ("StOpc != 0 && \"Should have a store opcode\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 8815, __PRETTY_FUNCTION__)); | |||
8816 | if (StSize >= 8) { | |||
8817 | BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut) | |||
8818 | .addReg(AddrIn) | |||
8819 | .addImm(0) | |||
8820 | .addReg(Data) | |||
8821 | .add(predOps(ARMCC::AL)); | |||
8822 | } else if (IsThumb1) { | |||
8823 | // store + update AddrIn | |||
8824 | BuildMI(*BB, Pos, dl, TII->get(StOpc)) | |||
8825 | .addReg(Data) | |||
8826 | .addReg(AddrIn) | |||
8827 | .addImm(0) | |||
8828 | .add(predOps(ARMCC::AL)); | |||
8829 | BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut) | |||
8830 | .add(t1CondCodeOp()) | |||
8831 | .addReg(AddrIn) | |||
8832 | .addImm(StSize) | |||
8833 | .add(predOps(ARMCC::AL)); | |||
8834 | } else if (IsThumb2) { | |||
8835 | BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut) | |||
8836 | .addReg(Data) | |||
8837 | .addReg(AddrIn) | |||
8838 | .addImm(StSize) | |||
8839 | .add(predOps(ARMCC::AL)); | |||
8840 | } else { // arm | |||
8841 | BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut) | |||
8842 | .addReg(Data) | |||
8843 | .addReg(AddrIn) | |||
8844 | .addReg(0) | |||
8845 | .addImm(StSize) | |||
8846 | .add(predOps(ARMCC::AL)); | |||
8847 | } | |||
8848 | } | |||
8849 | ||||
8850 | MachineBasicBlock * | |||
8851 | ARMTargetLowering::EmitStructByval(MachineInstr &MI, | |||
8852 | MachineBasicBlock *BB) const { | |||
8853 | // This pseudo instruction has 3 operands: dst, src, size | |||
8854 | // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold(). | |||
8855 | // Otherwise, we will generate unrolled scalar copies. | |||
8856 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
8857 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); | |||
8858 | MachineFunction::iterator It = ++BB->getIterator(); | |||
8859 | ||||
8860 | unsigned dest = MI.getOperand(0).getReg(); | |||
8861 | unsigned src = MI.getOperand(1).getReg(); | |||
8862 | unsigned SizeVal = MI.getOperand(2).getImm(); | |||
8863 | unsigned Align = MI.getOperand(3).getImm(); | |||
8864 | DebugLoc dl = MI.getDebugLoc(); | |||
8865 | ||||
8866 | MachineFunction *MF = BB->getParent(); | |||
8867 | MachineRegisterInfo &MRI = MF->getRegInfo(); | |||
8868 | unsigned UnitSize = 0; | |||
8869 | const TargetRegisterClass *TRC = nullptr; | |||
8870 | const TargetRegisterClass *VecTRC = nullptr; | |||
8871 | ||||
8872 | bool IsThumb1 = Subtarget->isThumb1Only(); | |||
8873 | bool IsThumb2 = Subtarget->isThumb2(); | |||
8874 | bool IsThumb = Subtarget->isThumb(); | |||
8875 | ||||
8876 | if (Align & 1) { | |||
8877 | UnitSize = 1; | |||
8878 | } else if (Align & 2) { | |||
8879 | UnitSize = 2; | |||
8880 | } else { | |||
8881 | // Check whether we can use NEON instructions. | |||
8882 | if (!MF->getFunction().hasFnAttribute(Attribute::NoImplicitFloat) && | |||
8883 | Subtarget->hasNEON()) { | |||
8884 | if ((Align % 16 == 0) && SizeVal >= 16) | |||
8885 | UnitSize = 16; | |||
8886 | else if ((Align % 8 == 0) && SizeVal >= 8) | |||
8887 | UnitSize = 8; | |||
8888 | } | |||
8889 | // Can't use NEON instructions. | |||
8890 | if (UnitSize == 0) | |||
8891 | UnitSize = 4; | |||
8892 | } | |||
8893 | ||||
8894 | // Select the correct opcode and register class for unit size load/store | |||
8895 | bool IsNeon = UnitSize >= 8; | |||
8896 | TRC = IsThumb ? &ARM::tGPRRegClass : &ARM::GPRRegClass; | |||
8897 | if (IsNeon) | |||
8898 | VecTRC = UnitSize == 16 ? &ARM::DPairRegClass | |||
8899 | : UnitSize == 8 ? &ARM::DPRRegClass | |||
8900 | : nullptr; | |||
8901 | ||||
8902 | unsigned BytesLeft = SizeVal % UnitSize; | |||
8903 | unsigned LoopSize = SizeVal - BytesLeft; | |||
8904 | ||||
8905 | if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) { | |||
8906 | // Use LDR and STR to copy. | |||
8907 | // [scratch, srcOut] = LDR_POST(srcIn, UnitSize) | |||
8908 | // [destOut] = STR_POST(scratch, destIn, UnitSize) | |||
8909 | unsigned srcIn = src; | |||
8910 | unsigned destIn = dest; | |||
8911 | for (unsigned i = 0; i < LoopSize; i+=UnitSize) { | |||
8912 | unsigned srcOut = MRI.createVirtualRegister(TRC); | |||
8913 | unsigned destOut = MRI.createVirtualRegister(TRC); | |||
8914 | unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC); | |||
8915 | emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut, | |||
8916 | IsThumb1, IsThumb2); | |||
8917 | emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut, | |||
8918 | IsThumb1, IsThumb2); | |||
8919 | srcIn = srcOut; | |||
8920 | destIn = destOut; | |||
8921 | } | |||
8922 | ||||
8923 | // Handle the leftover bytes with LDRB and STRB. | |||
8924 | // [scratch, srcOut] = LDRB_POST(srcIn, 1) | |||
8925 | // [destOut] = STRB_POST(scratch, destIn, 1) | |||
8926 | for (unsigned i = 0; i < BytesLeft; i++) { | |||
8927 | unsigned srcOut = MRI.createVirtualRegister(TRC); | |||
8928 | unsigned destOut = MRI.createVirtualRegister(TRC); | |||
8929 | unsigned scratch = MRI.createVirtualRegister(TRC); | |||
8930 | emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut, | |||
8931 | IsThumb1, IsThumb2); | |||
8932 | emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut, | |||
8933 | IsThumb1, IsThumb2); | |||
8934 | srcIn = srcOut; | |||
8935 | destIn = destOut; | |||
8936 | } | |||
8937 | MI.eraseFromParent(); // The instruction is gone now. | |||
8938 | return BB; | |||
8939 | } | |||
8940 | ||||
8941 | // Expand the pseudo op to a loop. | |||
8942 | // thisMBB: | |||
8943 | // ... | |||
8944 | // movw varEnd, # --> with thumb2 | |||
8945 | // movt varEnd, # | |||
8946 | // ldrcp varEnd, idx --> without thumb2 | |||
8947 | // fallthrough --> loopMBB | |||
8948 | // loopMBB: | |||
8949 | // PHI varPhi, varEnd, varLoop | |||
8950 | // PHI srcPhi, src, srcLoop | |||
8951 | // PHI destPhi, dst, destLoop | |||
8952 | // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize) | |||
8953 | // [destLoop] = STR_POST(scratch, destPhi, UnitSize) | |||
8954 | // subs varLoop, varPhi, #UnitSize | |||
8955 | // bne loopMBB | |||
8956 | // fallthrough --> exitMBB | |||
8957 | // exitMBB: | |||
8958 | // epilogue to handle left-over bytes | |||
8959 | // [scratch, srcOut] = LDRB_POST(srcLoop, 1) | |||
8960 | // [destOut] = STRB_POST(scratch, destLoop, 1) | |||
8961 | MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); | |||
8962 | MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); | |||
8963 | MF->insert(It, loopMBB); | |||
8964 | MF->insert(It, exitMBB); | |||
8965 | ||||
8966 | // Transfer the remainder of BB and its successor edges to exitMBB. | |||
8967 | exitMBB->splice(exitMBB->begin(), BB, | |||
8968 | std::next(MachineBasicBlock::iterator(MI)), BB->end()); | |||
8969 | exitMBB->transferSuccessorsAndUpdatePHIs(BB); | |||
8970 | ||||
8971 | // Load an immediate to varEnd. | |||
8972 | unsigned varEnd = MRI.createVirtualRegister(TRC); | |||
8973 | if (Subtarget->useMovt()) { | |||
8974 | unsigned Vtmp = varEnd; | |||
8975 | if ((LoopSize & 0xFFFF0000) != 0) | |||
8976 | Vtmp = MRI.createVirtualRegister(TRC); | |||
8977 | BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp) | |||
8978 | .addImm(LoopSize & 0xFFFF) | |||
8979 | .add(predOps(ARMCC::AL)); | |||
8980 | ||||
8981 | if ((LoopSize & 0xFFFF0000) != 0) | |||
8982 | BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd) | |||
8983 | .addReg(Vtmp) | |||
8984 | .addImm(LoopSize >> 16) | |||
8985 | .add(predOps(ARMCC::AL)); | |||
8986 | } else { | |||
8987 | MachineConstantPool *ConstantPool = MF->getConstantPool(); | |||
8988 | Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext()); | |||
8989 | const Constant *C = ConstantInt::get(Int32Ty, LoopSize); | |||
8990 | ||||
8991 | // MachineConstantPool wants an explicit alignment. | |||
8992 | unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty); | |||
8993 | if (Align == 0) | |||
8994 | Align = MF->getDataLayout().getTypeAllocSize(C->getType()); | |||
8995 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); | |||
8996 | MachineMemOperand *CPMMO = | |||
8997 | MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF), | |||
8998 | MachineMemOperand::MOLoad, 4, 4); | |||
8999 | ||||
9000 | if (IsThumb) | |||
9001 | BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)) | |||
9002 | .addReg(varEnd, RegState::Define) | |||
9003 | .addConstantPoolIndex(Idx) | |||
9004 | .add(predOps(ARMCC::AL)) | |||
9005 | .addMemOperand(CPMMO); | |||
9006 | else | |||
9007 | BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)) | |||
9008 | .addReg(varEnd, RegState::Define) | |||
9009 | .addConstantPoolIndex(Idx) | |||
9010 | .addImm(0) | |||
9011 | .add(predOps(ARMCC::AL)) | |||
9012 | .addMemOperand(CPMMO); | |||
9013 | } | |||
9014 | BB->addSuccessor(loopMBB); | |||
9015 | ||||
9016 | // Generate the loop body: | |||
9017 | // varPhi = PHI(varLoop, varEnd) | |||
9018 | // srcPhi = PHI(srcLoop, src) | |||
9019 | // destPhi = PHI(destLoop, dst) | |||
9020 | MachineBasicBlock *entryBB = BB; | |||
9021 | BB = loopMBB; | |||
9022 | unsigned varLoop = MRI.createVirtualRegister(TRC); | |||
9023 | unsigned varPhi = MRI.createVirtualRegister(TRC); | |||
9024 | unsigned srcLoop = MRI.createVirtualRegister(TRC); | |||
9025 | unsigned srcPhi = MRI.createVirtualRegister(TRC); | |||
9026 | unsigned destLoop = MRI.createVirtualRegister(TRC); | |||
9027 | unsigned destPhi = MRI.createVirtualRegister(TRC); | |||
9028 | ||||
9029 | BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi) | |||
9030 | .addReg(varLoop).addMBB(loopMBB) | |||
9031 | .addReg(varEnd).addMBB(entryBB); | |||
9032 | BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi) | |||
9033 | .addReg(srcLoop).addMBB(loopMBB) | |||
9034 | .addReg(src).addMBB(entryBB); | |||
9035 | BuildMI(BB, dl, TII->get(ARM::PHI), destPhi) | |||
9036 | .addReg(destLoop).addMBB(loopMBB) | |||
9037 | .addReg(dest).addMBB(entryBB); | |||
9038 | ||||
9039 | // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize) | |||
9040 | // [destLoop] = STR_POST(scratch, destPhi, UnitSiz) | |||
9041 | unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC); | |||
9042 | emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop, | |||
9043 | IsThumb1, IsThumb2); | |||
9044 | emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop, | |||
9045 | IsThumb1, IsThumb2); | |||
9046 | ||||
9047 | // Decrement loop variable by UnitSize. | |||
9048 | if (IsThumb1) { | |||
9049 | BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop) | |||
9050 | .add(t1CondCodeOp()) | |||
9051 | .addReg(varPhi) | |||
9052 | .addImm(UnitSize) | |||
9053 | .add(predOps(ARMCC::AL)); | |||
9054 | } else { | |||
9055 | MachineInstrBuilder MIB = | |||
9056 | BuildMI(*BB, BB->end(), dl, | |||
9057 | TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop); | |||
9058 | MIB.addReg(varPhi) | |||
9059 | .addImm(UnitSize) | |||
9060 | .add(predOps(ARMCC::AL)) | |||
9061 | .add(condCodeOp()); | |||
9062 | MIB->getOperand(5).setReg(ARM::CPSR); | |||
9063 | MIB->getOperand(5).setIsDef(true); | |||
9064 | } | |||
9065 | BuildMI(*BB, BB->end(), dl, | |||
9066 | TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc)) | |||
9067 | .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); | |||
9068 | ||||
9069 | // loopMBB can loop back to loopMBB or fall through to exitMBB. | |||
9070 | BB->addSuccessor(loopMBB); | |||
9071 | BB->addSuccessor(exitMBB); | |||
9072 | ||||
9073 | // Add epilogue to handle BytesLeft. | |||
9074 | BB = exitMBB; | |||
9075 | auto StartOfExit = exitMBB->begin(); | |||
9076 | ||||
9077 | // [scratch, srcOut] = LDRB_POST(srcLoop, 1) | |||
9078 | // [destOut] = STRB_POST(scratch, destLoop, 1) | |||
9079 | unsigned srcIn = srcLoop; | |||
9080 | unsigned destIn = destLoop; | |||
9081 | for (unsigned i = 0; i < BytesLeft; i++) { | |||
9082 | unsigned srcOut = MRI.createVirtualRegister(TRC); | |||
9083 | unsigned destOut = MRI.createVirtualRegister(TRC); | |||
9084 | unsigned scratch = MRI.createVirtualRegister(TRC); | |||
9085 | emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut, | |||
9086 | IsThumb1, IsThumb2); | |||
9087 | emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut, | |||
9088 | IsThumb1, IsThumb2); | |||
9089 | srcIn = srcOut; | |||
9090 | destIn = destOut; | |||
9091 | } | |||
9092 | ||||
9093 | MI.eraseFromParent(); // The instruction is gone now. | |||
9094 | return BB; | |||
9095 | } | |||
9096 | ||||
9097 | MachineBasicBlock * | |||
9098 | ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, | |||
9099 | MachineBasicBlock *MBB) const { | |||
9100 | const TargetMachine &TM = getTargetMachine(); | |||
9101 | const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); | |||
9102 | DebugLoc DL = MI.getDebugLoc(); | |||
9103 | ||||
9104 | assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "__chkstk is only supported on Windows" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"__chkstk is only supported on Windows\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9105, __PRETTY_FUNCTION__)) | |||
9105 | "__chkstk is only supported on Windows")((Subtarget->isTargetWindows() && "__chkstk is only supported on Windows" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"__chkstk is only supported on Windows\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9105, __PRETTY_FUNCTION__)); | |||
9106 | assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode")((Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isThumb2() && \"Windows on ARM requires Thumb-2 mode\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9106, __PRETTY_FUNCTION__)); | |||
9107 | ||||
9108 | // __chkstk takes the number of words to allocate on the stack in R4, and | |||
9109 | // returns the stack adjustment in number of bytes in R4. This will not | |||
9110 | // clober any other registers (other than the obvious lr). | |||
9111 | // | |||
9112 | // Although, technically, IP should be considered a register which may be | |||
9113 | // clobbered, the call itself will not touch it. Windows on ARM is a pure | |||
9114 | // thumb-2 environment, so there is no interworking required. As a result, we | |||
9115 | // do not expect a veneer to be emitted by the linker, clobbering IP. | |||
9116 | // | |||
9117 | // Each module receives its own copy of __chkstk, so no import thunk is | |||
9118 | // required, again, ensuring that IP is not clobbered. | |||
9119 | // | |||
9120 | // Finally, although some linkers may theoretically provide a trampoline for | |||
9121 | // out of range calls (which is quite common due to a 32M range limitation of | |||
9122 | // branches for Thumb), we can generate the long-call version via | |||
9123 | // -mcmodel=large, alleviating the need for the trampoline which may clobber | |||
9124 | // IP. | |||
9125 | ||||
9126 | switch (TM.getCodeModel()) { | |||
9127 | case CodeModel::Tiny: | |||
9128 | llvm_unreachable("Tiny code model not available on ARM.")::llvm::llvm_unreachable_internal("Tiny code model not available on ARM." , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9128); | |||
9129 | case CodeModel::Small: | |||
9130 | case CodeModel::Medium: | |||
9131 | case CodeModel::Kernel: | |||
9132 | BuildMI(*MBB, MI, DL, TII.get(ARM::tBL)) | |||
9133 | .add(predOps(ARMCC::AL)) | |||
9134 | .addExternalSymbol("__chkstk") | |||
9135 | .addReg(ARM::R4, RegState::Implicit | RegState::Kill) | |||
9136 | .addReg(ARM::R4, RegState::Implicit | RegState::Define) | |||
9137 | .addReg(ARM::R12, | |||
9138 | RegState::Implicit | RegState::Define | RegState::Dead) | |||
9139 | .addReg(ARM::CPSR, | |||
9140 | RegState::Implicit | RegState::Define | RegState::Dead); | |||
9141 | break; | |||
9142 | case CodeModel::Large: { | |||
9143 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); | |||
9144 | unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass); | |||
9145 | ||||
9146 | BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg) | |||
9147 | .addExternalSymbol("__chkstk"); | |||
9148 | BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr)) | |||
9149 | .add(predOps(ARMCC::AL)) | |||
9150 | .addReg(Reg, RegState::Kill) | |||
9151 | .addReg(ARM::R4, RegState::Implicit | RegState::Kill) | |||
9152 | .addReg(ARM::R4, RegState::Implicit | RegState::Define) | |||
9153 | .addReg(ARM::R12, | |||
9154 | RegState::Implicit | RegState::Define | RegState::Dead) | |||
9155 | .addReg(ARM::CPSR, | |||
9156 | RegState::Implicit | RegState::Define | RegState::Dead); | |||
9157 | break; | |||
9158 | } | |||
9159 | } | |||
9160 | ||||
9161 | BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP) | |||
9162 | .addReg(ARM::SP, RegState::Kill) | |||
9163 | .addReg(ARM::R4, RegState::Kill) | |||
9164 | .setMIFlags(MachineInstr::FrameSetup) | |||
9165 | .add(predOps(ARMCC::AL)) | |||
9166 | .add(condCodeOp()); | |||
9167 | ||||
9168 | MI.eraseFromParent(); | |||
9169 | return MBB; | |||
9170 | } | |||
9171 | ||||
9172 | MachineBasicBlock * | |||
9173 | ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI, | |||
9174 | MachineBasicBlock *MBB) const { | |||
9175 | DebugLoc DL = MI.getDebugLoc(); | |||
9176 | MachineFunction *MF = MBB->getParent(); | |||
9177 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
9178 | ||||
9179 | MachineBasicBlock *ContBB = MF->CreateMachineBasicBlock(); | |||
9180 | MF->insert(++MBB->getIterator(), ContBB); | |||
9181 | ContBB->splice(ContBB->begin(), MBB, | |||
9182 | std::next(MachineBasicBlock::iterator(MI)), MBB->end()); | |||
9183 | ContBB->transferSuccessorsAndUpdatePHIs(MBB); | |||
9184 | MBB->addSuccessor(ContBB); | |||
9185 | ||||
9186 | MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); | |||
9187 | BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0)); | |||
9188 | MF->push_back(TrapBB); | |||
9189 | MBB->addSuccessor(TrapBB); | |||
9190 | ||||
9191 | BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8)) | |||
9192 | .addReg(MI.getOperand(0).getReg()) | |||
9193 | .addImm(0) | |||
9194 | .add(predOps(ARMCC::AL)); | |||
9195 | BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc)) | |||
9196 | .addMBB(TrapBB) | |||
9197 | .addImm(ARMCC::EQ) | |||
9198 | .addReg(ARM::CPSR); | |||
9199 | ||||
9200 | MI.eraseFromParent(); | |||
9201 | return ContBB; | |||
9202 | } | |||
9203 | ||||
9204 | // The CPSR operand of SelectItr might be missing a kill marker | |||
9205 | // because there were multiple uses of CPSR, and ISel didn't know | |||
9206 | // which to mark. Figure out whether SelectItr should have had a | |||
9207 | // kill marker, and set it if it should. Returns the correct kill | |||
9208 | // marker value. | |||
9209 | static bool checkAndUpdateCPSRKill(MachineBasicBlock::iterator SelectItr, | |||
9210 | MachineBasicBlock* BB, | |||
9211 | const TargetRegisterInfo* TRI) { | |||
9212 | // Scan forward through BB for a use/def of CPSR. | |||
9213 | MachineBasicBlock::iterator miI(std::next(SelectItr)); | |||
9214 | for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { | |||
9215 | const MachineInstr& mi = *miI; | |||
9216 | if (mi.readsRegister(ARM::CPSR)) | |||
9217 | return false; | |||
9218 | if (mi.definesRegister(ARM::CPSR)) | |||
9219 | break; // Should have kill-flag - update below. | |||
9220 | } | |||
9221 | ||||
9222 | // If we hit the end of the block, check whether CPSR is live into a | |||
9223 | // successor. | |||
9224 | if (miI == BB->end()) { | |||
9225 | for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), | |||
9226 | sEnd = BB->succ_end(); | |||
9227 | sItr != sEnd; ++sItr) { | |||
9228 | MachineBasicBlock* succ = *sItr; | |||
9229 | if (succ->isLiveIn(ARM::CPSR)) | |||
9230 | return false; | |||
9231 | } | |||
9232 | } | |||
9233 | ||||
9234 | // We found a def, or hit the end of the basic block and CPSR wasn't live | |||
9235 | // out. SelectMI should have a kill flag on CPSR. | |||
9236 | SelectItr->addRegisterKilled(ARM::CPSR, TRI); | |||
9237 | return true; | |||
9238 | } | |||
9239 | ||||
9240 | MachineBasicBlock * | |||
9241 | ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, | |||
9242 | MachineBasicBlock *BB) const { | |||
9243 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
9244 | DebugLoc dl = MI.getDebugLoc(); | |||
9245 | bool isThumb2 = Subtarget->isThumb2(); | |||
9246 | switch (MI.getOpcode()) { | |||
9247 | default: { | |||
9248 | MI.print(errs()); | |||
9249 | llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9249); | |||
9250 | } | |||
9251 | ||||
9252 | // Thumb1 post-indexed loads are really just single-register LDMs. | |||
9253 | case ARM::tLDR_postidx: { | |||
9254 | MachineOperand Def(MI.getOperand(1)); | |||
9255 | BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD)) | |||
9256 | .add(Def) // Rn_wb | |||
9257 | .add(MI.getOperand(2)) // Rn | |||
9258 | .add(MI.getOperand(3)) // PredImm | |||
9259 | .add(MI.getOperand(4)) // PredReg | |||
9260 | .add(MI.getOperand(0)) // Rt | |||
9261 | .cloneMemRefs(MI); | |||
9262 | MI.eraseFromParent(); | |||
9263 | return BB; | |||
9264 | } | |||
9265 | ||||
9266 | // The Thumb2 pre-indexed stores have the same MI operands, they just | |||
9267 | // define them differently in the .td files from the isel patterns, so | |||
9268 | // they need pseudos. | |||
9269 | case ARM::t2STR_preidx: | |||
9270 | MI.setDesc(TII->get(ARM::t2STR_PRE)); | |||
9271 | return BB; | |||
9272 | case ARM::t2STRB_preidx: | |||
9273 | MI.setDesc(TII->get(ARM::t2STRB_PRE)); | |||
9274 | return BB; | |||
9275 | case ARM::t2STRH_preidx: | |||
9276 | MI.setDesc(TII->get(ARM::t2STRH_PRE)); | |||
9277 | return BB; | |||
9278 | ||||
9279 | case ARM::STRi_preidx: | |||
9280 | case ARM::STRBi_preidx: { | |||
9281 | unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM | |||
9282 | : ARM::STRB_PRE_IMM; | |||
9283 | // Decode the offset. | |||
9284 | unsigned Offset = MI.getOperand(4).getImm(); | |||
9285 | bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; | |||
9286 | Offset = ARM_AM::getAM2Offset(Offset); | |||
9287 | if (isSub) | |||
9288 | Offset = -Offset; | |||
9289 | ||||
9290 | MachineMemOperand *MMO = *MI.memoperands_begin(); | |||
9291 | BuildMI(*BB, MI, dl, TII->get(NewOpc)) | |||
9292 | .add(MI.getOperand(0)) // Rn_wb | |||
9293 | .add(MI.getOperand(1)) // Rt | |||
9294 | .add(MI.getOperand(2)) // Rn | |||
9295 | .addImm(Offset) // offset (skip GPR==zero_reg) | |||
9296 | .add(MI.getOperand(5)) // pred | |||
9297 | .add(MI.getOperand(6)) | |||
9298 | .addMemOperand(MMO); | |||
9299 | MI.eraseFromParent(); | |||
9300 | return BB; | |||
9301 | } | |||
9302 | case ARM::STRr_preidx: | |||
9303 | case ARM::STRBr_preidx: | |||
9304 | case ARM::STRH_preidx: { | |||
9305 | unsigned NewOpc; | |||
9306 | switch (MI.getOpcode()) { | |||
9307 | default: llvm_unreachable("unexpected opcode!")::llvm::llvm_unreachable_internal("unexpected opcode!", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9307); | |||
9308 | case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; | |||
9309 | case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; | |||
9310 | case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; | |||
9311 | } | |||
9312 | MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); | |||
9313 | for (unsigned i = 0; i < MI.getNumOperands(); ++i) | |||
9314 | MIB.add(MI.getOperand(i)); | |||
9315 | MI.eraseFromParent(); | |||
9316 | return BB; | |||
9317 | } | |||
9318 | ||||
9319 | case ARM::tMOVCCr_pseudo: { | |||
9320 | // To "insert" a SELECT_CC instruction, we actually have to insert the | |||
9321 | // diamond control-flow pattern. The incoming instruction knows the | |||
9322 | // destination vreg to set, the condition code register to branch on, the | |||
9323 | // true/false values to select between, and a branch opcode to use. | |||
9324 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); | |||
9325 | MachineFunction::iterator It = ++BB->getIterator(); | |||
9326 | ||||
9327 | // thisMBB: | |||
9328 | // ... | |||
9329 | // TrueVal = ... | |||
9330 | // cmpTY ccX, r1, r2 | |||
9331 | // bCC copy1MBB | |||
9332 | // fallthrough --> copy0MBB | |||
9333 | MachineBasicBlock *thisMBB = BB; | |||
9334 | MachineFunction *F = BB->getParent(); | |||
9335 | MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); | |||
9336 | MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); | |||
9337 | F->insert(It, copy0MBB); | |||
9338 | F->insert(It, sinkMBB); | |||
9339 | ||||
9340 | // Check whether CPSR is live past the tMOVCCr_pseudo. | |||
9341 | const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); | |||
9342 | if (!MI.killsRegister(ARM::CPSR) && | |||
9343 | !checkAndUpdateCPSRKill(MI, thisMBB, TRI)) { | |||
9344 | copy0MBB->addLiveIn(ARM::CPSR); | |||
9345 | sinkMBB->addLiveIn(ARM::CPSR); | |||
9346 | } | |||
9347 | ||||
9348 | // Transfer the remainder of BB and its successor edges to sinkMBB. | |||
9349 | sinkMBB->splice(sinkMBB->begin(), BB, | |||
9350 | std::next(MachineBasicBlock::iterator(MI)), BB->end()); | |||
9351 | sinkMBB->transferSuccessorsAndUpdatePHIs(BB); | |||
9352 | ||||
9353 | BB->addSuccessor(copy0MBB); | |||
9354 | BB->addSuccessor(sinkMBB); | |||
9355 | ||||
9356 | BuildMI(BB, dl, TII->get(ARM::tBcc)) | |||
9357 | .addMBB(sinkMBB) | |||
9358 | .addImm(MI.getOperand(3).getImm()) | |||
9359 | .addReg(MI.getOperand(4).getReg()); | |||
9360 | ||||
9361 | // copy0MBB: | |||
9362 | // %FalseValue = ... | |||
9363 | // # fallthrough to sinkMBB | |||
9364 | BB = copy0MBB; | |||
9365 | ||||
9366 | // Update machine-CFG edges | |||
9367 | BB->addSuccessor(sinkMBB); | |||
9368 | ||||
9369 | // sinkMBB: | |||
9370 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] | |||
9371 | // ... | |||
9372 | BB = sinkMBB; | |||
9373 | BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg()) | |||
9374 | .addReg(MI.getOperand(1).getReg()) | |||
9375 | .addMBB(copy0MBB) | |||
9376 | .addReg(MI.getOperand(2).getReg()) | |||
9377 | .addMBB(thisMBB); | |||
9378 | ||||
9379 | MI.eraseFromParent(); // The pseudo instruction is gone now. | |||
9380 | return BB; | |||
9381 | } | |||
9382 | ||||
9383 | case ARM::BCCi64: | |||
9384 | case ARM::BCCZi64: { | |||
9385 | // If there is an unconditional branch to the other successor, remove it. | |||
9386 | BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end()); | |||
9387 | ||||
9388 | // Compare both parts that make up the double comparison separately for | |||
9389 | // equality. | |||
9390 | bool RHSisZero = MI.getOpcode() == ARM::BCCZi64; | |||
9391 | ||||
9392 | unsigned LHS1 = MI.getOperand(1).getReg(); | |||
9393 | unsigned LHS2 = MI.getOperand(2).getReg(); | |||
9394 | if (RHSisZero) { | |||
9395 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) | |||
9396 | .addReg(LHS1) | |||
9397 | .addImm(0) | |||
9398 | .add(predOps(ARMCC::AL)); | |||
9399 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) | |||
9400 | .addReg(LHS2).addImm(0) | |||
9401 | .addImm(ARMCC::EQ).addReg(ARM::CPSR); | |||
9402 | } else { | |||
9403 | unsigned RHS1 = MI.getOperand(3).getReg(); | |||
9404 | unsigned RHS2 = MI.getOperand(4).getReg(); | |||
9405 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) | |||
9406 | .addReg(LHS1) | |||
9407 | .addReg(RHS1) | |||
9408 | .add(predOps(ARMCC::AL)); | |||
9409 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) | |||
9410 | .addReg(LHS2).addReg(RHS2) | |||
9411 | .addImm(ARMCC::EQ).addReg(ARM::CPSR); | |||
9412 | } | |||
9413 | ||||
9414 | MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB(); | |||
9415 | MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); | |||
9416 | if (MI.getOperand(0).getImm() == ARMCC::NE) | |||
9417 | std::swap(destMBB, exitMBB); | |||
9418 | ||||
9419 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) | |||
9420 | .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); | |||
9421 | if (isThumb2) | |||
9422 | BuildMI(BB, dl, TII->get(ARM::t2B)) | |||
9423 | .addMBB(exitMBB) | |||
9424 | .add(predOps(ARMCC::AL)); | |||
9425 | else | |||
9426 | BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); | |||
9427 | ||||
9428 | MI.eraseFromParent(); // The pseudo instruction is gone now. | |||
9429 | return BB; | |||
9430 | } | |||
9431 | ||||
9432 | case ARM::Int_eh_sjlj_setjmp: | |||
9433 | case ARM::Int_eh_sjlj_setjmp_nofp: | |||
9434 | case ARM::tInt_eh_sjlj_setjmp: | |||
9435 | case ARM::t2Int_eh_sjlj_setjmp: | |||
9436 | case ARM::t2Int_eh_sjlj_setjmp_nofp: | |||
9437 | return BB; | |||
9438 | ||||
9439 | case ARM::Int_eh_sjlj_setup_dispatch: | |||
9440 | EmitSjLjDispatchBlock(MI, BB); | |||
9441 | return BB; | |||
9442 | ||||
9443 | case ARM::ABS: | |||
9444 | case ARM::t2ABS: { | |||
9445 | // To insert an ABS instruction, we have to insert the | |||
9446 | // diamond control-flow pattern. The incoming instruction knows the | |||
9447 | // source vreg to test against 0, the destination vreg to set, | |||
9448 | // the condition code register to branch on, the | |||
9449 | // true/false values to select between, and a branch opcode to use. | |||
9450 | // It transforms | |||
9451 | // V1 = ABS V0 | |||
9452 | // into | |||
9453 | // V2 = MOVS V0 | |||
9454 | // BCC (branch to SinkBB if V0 >= 0) | |||
9455 | // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) | |||
9456 | // SinkBB: V1 = PHI(V2, V3) | |||
9457 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); | |||
9458 | MachineFunction::iterator BBI = ++BB->getIterator(); | |||
9459 | MachineFunction *Fn = BB->getParent(); | |||
9460 | MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); | |||
9461 | MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); | |||
9462 | Fn->insert(BBI, RSBBB); | |||
9463 | Fn->insert(BBI, SinkBB); | |||
9464 | ||||
9465 | unsigned int ABSSrcReg = MI.getOperand(1).getReg(); | |||
9466 | unsigned int ABSDstReg = MI.getOperand(0).getReg(); | |||
9467 | bool ABSSrcKIll = MI.getOperand(1).isKill(); | |||
9468 | bool isThumb2 = Subtarget->isThumb2(); | |||
9469 | MachineRegisterInfo &MRI = Fn->getRegInfo(); | |||
9470 | // In Thumb mode S must not be specified if source register is the SP or | |||
9471 | // PC and if destination register is the SP, so restrict register class | |||
9472 | unsigned NewRsbDstReg = | |||
9473 | MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass); | |||
9474 | ||||
9475 | // Transfer the remainder of BB and its successor edges to sinkMBB. | |||
9476 | SinkBB->splice(SinkBB->begin(), BB, | |||
9477 | std::next(MachineBasicBlock::iterator(MI)), BB->end()); | |||
9478 | SinkBB->transferSuccessorsAndUpdatePHIs(BB); | |||
9479 | ||||
9480 | BB->addSuccessor(RSBBB); | |||
9481 | BB->addSuccessor(SinkBB); | |||
9482 | ||||
9483 | // fall through to SinkMBB | |||
9484 | RSBBB->addSuccessor(SinkBB); | |||
9485 | ||||
9486 | // insert a cmp at the end of BB | |||
9487 | BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) | |||
9488 | .addReg(ABSSrcReg) | |||
9489 | .addImm(0) | |||
9490 | .add(predOps(ARMCC::AL)); | |||
9491 | ||||
9492 | // insert a bcc with opposite CC to ARMCC::MI at the end of BB | |||
9493 | BuildMI(BB, dl, | |||
9494 | TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) | |||
9495 | .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); | |||
9496 | ||||
9497 | // insert rsbri in RSBBB | |||
9498 | // Note: BCC and rsbri will be converted into predicated rsbmi | |||
9499 | // by if-conversion pass | |||
9500 | BuildMI(*RSBBB, RSBBB->begin(), dl, | |||
9501 | TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) | |||
9502 | .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0) | |||
9503 | .addImm(0) | |||
9504 | .add(predOps(ARMCC::AL)) | |||
9505 | .add(condCodeOp()); | |||
9506 | ||||
9507 | // insert PHI in SinkBB, | |||
9508 | // reuse ABSDstReg to not change uses of ABS instruction | |||
9509 | BuildMI(*SinkBB, SinkBB->begin(), dl, | |||
9510 | TII->get(ARM::PHI), ABSDstReg) | |||
9511 | .addReg(NewRsbDstReg).addMBB(RSBBB) | |||
9512 | .addReg(ABSSrcReg).addMBB(BB); | |||
9513 | ||||
9514 | // remove ABS instruction | |||
9515 | MI.eraseFromParent(); | |||
9516 | ||||
9517 | // return last added BB | |||
9518 | return SinkBB; | |||
9519 | } | |||
9520 | case ARM::COPY_STRUCT_BYVAL_I32: | |||
9521 | ++NumLoopByVals; | |||
9522 | return EmitStructByval(MI, BB); | |||
9523 | case ARM::WIN__CHKSTK: | |||
9524 | return EmitLowered__chkstk(MI, BB); | |||
9525 | case ARM::WIN__DBZCHK: | |||
9526 | return EmitLowered__dbzchk(MI, BB); | |||
9527 | } | |||
9528 | } | |||
9529 | ||||
9530 | /// Attaches vregs to MEMCPY that it will use as scratch registers | |||
9531 | /// when it is expanded into LDM/STM. This is done as a post-isel lowering | |||
9532 | /// instead of as a custom inserter because we need the use list from the SDNode. | |||
9533 | static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, | |||
9534 | MachineInstr &MI, const SDNode *Node) { | |||
9535 | bool isThumb1 = Subtarget->isThumb1Only(); | |||
9536 | ||||
9537 | DebugLoc DL = MI.getDebugLoc(); | |||
9538 | MachineFunction *MF = MI.getParent()->getParent(); | |||
9539 | MachineRegisterInfo &MRI = MF->getRegInfo(); | |||
9540 | MachineInstrBuilder MIB(*MF, MI); | |||
9541 | ||||
9542 | // If the new dst/src is unused mark it as dead. | |||
9543 | if (!Node->hasAnyUseOfValue(0)) { | |||
9544 | MI.getOperand(0).setIsDead(true); | |||
9545 | } | |||
9546 | if (!Node->hasAnyUseOfValue(1)) { | |||
9547 | MI.getOperand(1).setIsDead(true); | |||
9548 | } | |||
9549 | ||||
9550 | // The MEMCPY both defines and kills the scratch registers. | |||
9551 | for (unsigned I = 0; I != MI.getOperand(4).getImm(); ++I) { | |||
9552 | unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass | |||
9553 | : &ARM::GPRRegClass); | |||
9554 | MIB.addReg(TmpReg, RegState::Define|RegState::Dead); | |||
9555 | } | |||
9556 | } | |||
9557 | ||||
9558 | void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, | |||
9559 | SDNode *Node) const { | |||
9560 | if (MI.getOpcode() == ARM::MEMCPY) { | |||
9561 | attachMEMCPYScratchRegs(Subtarget, MI, Node); | |||
9562 | return; | |||
9563 | } | |||
9564 | ||||
9565 | const MCInstrDesc *MCID = &MI.getDesc(); | |||
9566 | // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, | |||
9567 | // RSC. Coming out of isel, they have an implicit CPSR def, but the optional | |||
9568 | // operand is still set to noreg. If needed, set the optional operand's | |||
9569 | // register to CPSR, and remove the redundant implicit def. | |||
9570 | // | |||
9571 | // e.g. ADCS (..., implicit-def CPSR) -> ADC (... opt:def CPSR). | |||
9572 | ||||
9573 | // Rename pseudo opcodes. | |||
9574 | unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode()); | |||
9575 | unsigned ccOutIdx; | |||
9576 | if (NewOpc) { | |||
9577 | const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo(); | |||
9578 | MCID = &TII->get(NewOpc); | |||
9579 | ||||
9580 | assert(MCID->getNumOperands() ==((MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && "converted opcode should be the same except for cc_out" " (and, on Thumb1, pred)") ? static_cast<void> (0) : __assert_fail ("MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && \"converted opcode should be the same except for cc_out\" \" (and, on Thumb1, pred)\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9583, __PRETTY_FUNCTION__)) | |||
9581 | MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()((MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && "converted opcode should be the same except for cc_out" " (and, on Thumb1, pred)") ? static_cast<void> (0) : __assert_fail ("MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && \"converted opcode should be the same except for cc_out\" \" (and, on Thumb1, pred)\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9583, __PRETTY_FUNCTION__)) | |||
9582 | && "converted opcode should be the same except for cc_out"((MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && "converted opcode should be the same except for cc_out" " (and, on Thumb1, pred)") ? static_cast<void> (0) : __assert_fail ("MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && \"converted opcode should be the same except for cc_out\" \" (and, on Thumb1, pred)\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9583, __PRETTY_FUNCTION__)) | |||
9583 | " (and, on Thumb1, pred)")((MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && "converted opcode should be the same except for cc_out" " (and, on Thumb1, pred)") ? static_cast<void> (0) : __assert_fail ("MCID->getNumOperands() == MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize() && \"converted opcode should be the same except for cc_out\" \" (and, on Thumb1, pred)\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9583, __PRETTY_FUNCTION__)); | |||
9584 | ||||
9585 | MI.setDesc(*MCID); | |||
9586 | ||||
9587 | // Add the optional cc_out operand | |||
9588 | MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); | |||
9589 | ||||
9590 | // On Thumb1, move all input operands to the end, then add the predicate | |||
9591 | if (Subtarget->isThumb1Only()) { | |||
9592 | for (unsigned c = MCID->getNumOperands() - 4; c--;) { | |||
9593 | MI.addOperand(MI.getOperand(1)); | |||
9594 | MI.RemoveOperand(1); | |||
9595 | } | |||
9596 | ||||
9597 | // Restore the ties | |||
9598 | for (unsigned i = MI.getNumOperands(); i--;) { | |||
9599 | const MachineOperand& op = MI.getOperand(i); | |||
9600 | if (op.isReg() && op.isUse()) { | |||
9601 | int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO); | |||
9602 | if (DefIdx != -1) | |||
9603 | MI.tieOperands(DefIdx, i); | |||
9604 | } | |||
9605 | } | |||
9606 | ||||
9607 | MI.addOperand(MachineOperand::CreateImm(ARMCC::AL)); | |||
9608 | MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false)); | |||
9609 | ccOutIdx = 1; | |||
9610 | } else | |||
9611 | ccOutIdx = MCID->getNumOperands() - 1; | |||
9612 | } else | |||
9613 | ccOutIdx = MCID->getNumOperands() - 1; | |||
9614 | ||||
9615 | // Any ARM instruction that sets the 's' bit should specify an optional | |||
9616 | // "cc_out" operand in the last operand position. | |||
9617 | if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { | |||
9618 | assert(!NewOpc && "Optional cc_out operand required")((!NewOpc && "Optional cc_out operand required") ? static_cast <void> (0) : __assert_fail ("!NewOpc && \"Optional cc_out operand required\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9618, __PRETTY_FUNCTION__)); | |||
9619 | return; | |||
9620 | } | |||
9621 | // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it | |||
9622 | // since we already have an optional CPSR def. | |||
9623 | bool definesCPSR = false; | |||
9624 | bool deadCPSR = false; | |||
9625 | for (unsigned i = MCID->getNumOperands(), e = MI.getNumOperands(); i != e; | |||
9626 | ++i) { | |||
9627 | const MachineOperand &MO = MI.getOperand(i); | |||
9628 | if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { | |||
9629 | definesCPSR = true; | |||
9630 | if (MO.isDead()) | |||
9631 | deadCPSR = true; | |||
9632 | MI.RemoveOperand(i); | |||
9633 | break; | |||
9634 | } | |||
9635 | } | |||
9636 | if (!definesCPSR) { | |||
9637 | assert(!NewOpc && "Optional cc_out operand required")((!NewOpc && "Optional cc_out operand required") ? static_cast <void> (0) : __assert_fail ("!NewOpc && \"Optional cc_out operand required\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9637, __PRETTY_FUNCTION__)); | |||
9638 | return; | |||
9639 | } | |||
9640 | assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag")((deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag" ) ? static_cast<void> (0) : __assert_fail ("deadCPSR == !Node->hasAnyUseOfValue(1) && \"inconsistent dead flag\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9640, __PRETTY_FUNCTION__)); | |||
9641 | if (deadCPSR) { | |||
9642 | assert(!MI.getOperand(ccOutIdx).getReg() &&((!MI.getOperand(ccOutIdx).getReg() && "expect uninitialized optional cc_out operand" ) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(ccOutIdx).getReg() && \"expect uninitialized optional cc_out operand\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9643, __PRETTY_FUNCTION__)) | |||
9643 | "expect uninitialized optional cc_out operand")((!MI.getOperand(ccOutIdx).getReg() && "expect uninitialized optional cc_out operand" ) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(ccOutIdx).getReg() && \"expect uninitialized optional cc_out operand\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9643, __PRETTY_FUNCTION__)); | |||
9644 | // Thumb1 instructions must have the S bit even if the CPSR is dead. | |||
9645 | if (!Subtarget->isThumb1Only()) | |||
9646 | return; | |||
9647 | } | |||
9648 | ||||
9649 | // If this instruction was defined with an optional CPSR def and its dag node | |||
9650 | // had a live implicit CPSR def, then activate the optional CPSR def. | |||
9651 | MachineOperand &MO = MI.getOperand(ccOutIdx); | |||
9652 | MO.setReg(ARM::CPSR); | |||
9653 | MO.setIsDef(true); | |||
9654 | } | |||
9655 | ||||
9656 | //===----------------------------------------------------------------------===// | |||
9657 | // ARM Optimization Hooks | |||
9658 | //===----------------------------------------------------------------------===// | |||
9659 | ||||
9660 | // Helper function that checks if N is a null or all ones constant. | |||
9661 | static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { | |||
9662 | return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); | |||
9663 | } | |||
9664 | ||||
9665 | // Return true if N is conditionally 0 or all ones. | |||
9666 | // Detects these expressions where cc is an i1 value: | |||
9667 | // | |||
9668 | // (select cc 0, y) [AllOnes=0] | |||
9669 | // (select cc y, 0) [AllOnes=0] | |||
9670 | // (zext cc) [AllOnes=0] | |||
9671 | // (sext cc) [AllOnes=0/1] | |||
9672 | // (select cc -1, y) [AllOnes=1] | |||
9673 | // (select cc y, -1) [AllOnes=1] | |||
9674 | // | |||
9675 | // Invert is set when N is the null/all ones constant when CC is false. | |||
9676 | // OtherOp is set to the alternative value of N. | |||
9677 | static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, | |||
9678 | SDValue &CC, bool &Invert, | |||
9679 | SDValue &OtherOp, | |||
9680 | SelectionDAG &DAG) { | |||
9681 | switch (N->getOpcode()) { | |||
9682 | default: return false; | |||
9683 | case ISD::SELECT: { | |||
9684 | CC = N->getOperand(0); | |||
9685 | SDValue N1 = N->getOperand(1); | |||
9686 | SDValue N2 = N->getOperand(2); | |||
9687 | if (isZeroOrAllOnes(N1, AllOnes)) { | |||
9688 | Invert = false; | |||
9689 | OtherOp = N2; | |||
9690 | return true; | |||
9691 | } | |||
9692 | if (isZeroOrAllOnes(N2, AllOnes)) { | |||
9693 | Invert = true; | |||
9694 | OtherOp = N1; | |||
9695 | return true; | |||
9696 | } | |||
9697 | return false; | |||
9698 | } | |||
9699 | case ISD::ZERO_EXTEND: | |||
9700 | // (zext cc) can never be the all ones value. | |||
9701 | if (AllOnes) | |||
9702 | return false; | |||
9703 | LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
9704 | case ISD::SIGN_EXTEND: { | |||
9705 | SDLoc dl(N); | |||
9706 | EVT VT = N->getValueType(0); | |||
9707 | CC = N->getOperand(0); | |||
9708 | if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC) | |||
9709 | return false; | |||
9710 | Invert = !AllOnes; | |||
9711 | if (AllOnes) | |||
9712 | // When looking for an AllOnes constant, N is an sext, and the 'other' | |||
9713 | // value is 0. | |||
9714 | OtherOp = DAG.getConstant(0, dl, VT); | |||
9715 | else if (N->getOpcode() == ISD::ZERO_EXTEND) | |||
9716 | // When looking for a 0 constant, N can be zext or sext. | |||
9717 | OtherOp = DAG.getConstant(1, dl, VT); | |||
9718 | else | |||
9719 | OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, | |||
9720 | VT); | |||
9721 | return true; | |||
9722 | } | |||
9723 | } | |||
9724 | } | |||
9725 | ||||
9726 | // Combine a constant select operand into its use: | |||
9727 | // | |||
9728 | // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) | |||
9729 | // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) | |||
9730 | // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1] | |||
9731 | // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) | |||
9732 | // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) | |||
9733 | // | |||
9734 | // The transform is rejected if the select doesn't have a constant operand that | |||
9735 | // is null, or all ones when AllOnes is set. | |||
9736 | // | |||
9737 | // Also recognize sext/zext from i1: | |||
9738 | // | |||
9739 | // (add (zext cc), x) -> (select cc (add x, 1), x) | |||
9740 | // (add (sext cc), x) -> (select cc (add x, -1), x) | |||
9741 | // | |||
9742 | // These transformations eventually create predicated instructions. | |||
9743 | // | |||
9744 | // @param N The node to transform. | |||
9745 | // @param Slct The N operand that is a select. | |||
9746 | // @param OtherOp The other N operand (x above). | |||
9747 | // @param DCI Context. | |||
9748 | // @param AllOnes Require the select constant to be all ones instead of null. | |||
9749 | // @returns The new node, or SDValue() on failure. | |||
9750 | static | |||
9751 | SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, | |||
9752 | TargetLowering::DAGCombinerInfo &DCI, | |||
9753 | bool AllOnes = false) { | |||
9754 | SelectionDAG &DAG = DCI.DAG; | |||
9755 | EVT VT = N->getValueType(0); | |||
9756 | SDValue NonConstantVal; | |||
9757 | SDValue CCOp; | |||
9758 | bool SwapSelectOps; | |||
9759 | if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, | |||
9760 | NonConstantVal, DAG)) | |||
9761 | return SDValue(); | |||
9762 | ||||
9763 | // Slct is now know to be the desired identity constant when CC is true. | |||
9764 | SDValue TrueVal = OtherOp; | |||
9765 | SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT, | |||
9766 | OtherOp, NonConstantVal); | |||
9767 | // Unless SwapSelectOps says CC should be false. | |||
9768 | if (SwapSelectOps) | |||
9769 | std::swap(TrueVal, FalseVal); | |||
9770 | ||||
9771 | return DAG.getNode(ISD::SELECT, SDLoc(N), VT, | |||
9772 | CCOp, TrueVal, FalseVal); | |||
9773 | } | |||
9774 | ||||
9775 | // Attempt combineSelectAndUse on each operand of a commutative operator N. | |||
9776 | static | |||
9777 | SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes, | |||
9778 | TargetLowering::DAGCombinerInfo &DCI) { | |||
9779 | SDValue N0 = N->getOperand(0); | |||
9780 | SDValue N1 = N->getOperand(1); | |||
9781 | if (N0.getNode()->hasOneUse()) | |||
9782 | if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) | |||
9783 | return Result; | |||
9784 | if (N1.getNode()->hasOneUse()) | |||
9785 | if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) | |||
9786 | return Result; | |||
9787 | return SDValue(); | |||
9788 | } | |||
9789 | ||||
9790 | static bool IsVUZPShuffleNode(SDNode *N) { | |||
9791 | // VUZP shuffle node. | |||
9792 | if (N->getOpcode() == ARMISD::VUZP) | |||
9793 | return true; | |||
9794 | ||||
9795 | // "VUZP" on i32 is an alias for VTRN. | |||
9796 | if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32) | |||
9797 | return true; | |||
9798 | ||||
9799 | return false; | |||
9800 | } | |||
9801 | ||||
9802 | static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1, | |||
9803 | TargetLowering::DAGCombinerInfo &DCI, | |||
9804 | const ARMSubtarget *Subtarget) { | |||
9805 | // Look for ADD(VUZP.0, VUZP.1). | |||
9806 | if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || | |||
9807 | N0 == N1) | |||
9808 | return SDValue(); | |||
9809 | ||||
9810 | // Make sure the ADD is a 64-bit add; there is no 128-bit VPADD. | |||
9811 | if (!N->getValueType(0).is64BitVector()) | |||
9812 | return SDValue(); | |||
9813 | ||||
9814 | // Generate vpadd. | |||
9815 | SelectionDAG &DAG = DCI.DAG; | |||
9816 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
9817 | SDLoc dl(N); | |||
9818 | SDNode *Unzip = N0.getNode(); | |||
9819 | EVT VT = N->getValueType(0); | |||
9820 | ||||
9821 | SmallVector<SDValue, 8> Ops; | |||
9822 | Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpadd, dl, | |||
9823 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
9824 | Ops.push_back(Unzip->getOperand(0)); | |||
9825 | Ops.push_back(Unzip->getOperand(1)); | |||
9826 | ||||
9827 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops); | |||
9828 | } | |||
9829 | ||||
9830 | static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1, | |||
9831 | TargetLowering::DAGCombinerInfo &DCI, | |||
9832 | const ARMSubtarget *Subtarget) { | |||
9833 | // Check for two extended operands. | |||
9834 | if (!(N0.getOpcode() == ISD::SIGN_EXTEND && | |||
9835 | N1.getOpcode() == ISD::SIGN_EXTEND) && | |||
9836 | !(N0.getOpcode() == ISD::ZERO_EXTEND && | |||
9837 | N1.getOpcode() == ISD::ZERO_EXTEND)) | |||
9838 | return SDValue(); | |||
9839 | ||||
9840 | SDValue N00 = N0.getOperand(0); | |||
9841 | SDValue N10 = N1.getOperand(0); | |||
9842 | ||||
9843 | // Look for ADD(SEXT(VUZP.0), SEXT(VUZP.1)) | |||
9844 | if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || | |||
9845 | N00 == N10) | |||
9846 | return SDValue(); | |||
9847 | ||||
9848 | // We only recognize Q register paddl here; this can't be reached until | |||
9849 | // after type legalization. | |||
9850 | if (!N00.getValueType().is64BitVector() || | |||
9851 | !N0.getValueType().is128BitVector()) | |||
9852 | return SDValue(); | |||
9853 | ||||
9854 | // Generate vpaddl. | |||
9855 | SelectionDAG &DAG = DCI.DAG; | |||
9856 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
9857 | SDLoc dl(N); | |||
9858 | EVT VT = N->getValueType(0); | |||
9859 | ||||
9860 | SmallVector<SDValue, 8> Ops; | |||
9861 | // Form vpaddl.sN or vpaddl.uN depending on the kind of extension. | |||
9862 | unsigned Opcode; | |||
9863 | if (N0.getOpcode() == ISD::SIGN_EXTEND) | |||
9864 | Opcode = Intrinsic::arm_neon_vpaddls; | |||
9865 | else | |||
9866 | Opcode = Intrinsic::arm_neon_vpaddlu; | |||
9867 | Ops.push_back(DAG.getConstant(Opcode, dl, | |||
9868 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
9869 | EVT ElemTy = N00.getValueType().getVectorElementType(); | |||
9870 | unsigned NumElts = VT.getVectorNumElements(); | |||
9871 | EVT ConcatVT = EVT::getVectorVT(*DAG.getContext(), ElemTy, NumElts * 2); | |||
9872 | SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, | |||
9873 | N00.getOperand(0), N00.getOperand(1)); | |||
9874 | Ops.push_back(Concat); | |||
9875 | ||||
9876 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops); | |||
9877 | } | |||
9878 | ||||
9879 | // FIXME: This function shouldn't be necessary; if we lower BUILD_VECTOR in | |||
9880 | // an appropriate manner, we end up with ADD(VUZP(ZEXT(N))), which is | |||
9881 | // much easier to match. | |||
9882 | static SDValue | |||
9883 | AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1, | |||
9884 | TargetLowering::DAGCombinerInfo &DCI, | |||
9885 | const ARMSubtarget *Subtarget) { | |||
9886 | // Only perform optimization if after legalize, and if NEON is available. We | |||
9887 | // also expected both operands to be BUILD_VECTORs. | |||
9888 | if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() | |||
9889 | || N0.getOpcode() != ISD::BUILD_VECTOR | |||
9890 | || N1.getOpcode() != ISD::BUILD_VECTOR) | |||
9891 | return SDValue(); | |||
9892 | ||||
9893 | // Check output type since VPADDL operand elements can only be 8, 16, or 32. | |||
9894 | EVT VT = N->getValueType(0); | |||
9895 | if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) | |||
9896 | return SDValue(); | |||
9897 | ||||
9898 | // Check that the vector operands are of the right form. | |||
9899 | // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR | |||
9900 | // operands, where N is the size of the formed vector. | |||
9901 | // Each EXTRACT_VECTOR should have the same input vector and odd or even | |||
9902 | // index such that we have a pair wise add pattern. | |||
9903 | ||||
9904 | // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. | |||
9905 | if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) | |||
9906 | return SDValue(); | |||
9907 | SDValue Vec = N0->getOperand(0)->getOperand(0); | |||
9908 | SDNode *V = Vec.getNode(); | |||
9909 | unsigned nextIndex = 0; | |||
9910 | ||||
9911 | // For each operands to the ADD which are BUILD_VECTORs, | |||
9912 | // check to see if each of their operands are an EXTRACT_VECTOR with | |||
9913 | // the same vector and appropriate index. | |||
9914 | for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { | |||
9915 | if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT | |||
9916 | && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { | |||
9917 | ||||
9918 | SDValue ExtVec0 = N0->getOperand(i); | |||
9919 | SDValue ExtVec1 = N1->getOperand(i); | |||
9920 | ||||
9921 | // First operand is the vector, verify its the same. | |||
9922 | if (V != ExtVec0->getOperand(0).getNode() || | |||
9923 | V != ExtVec1->getOperand(0).getNode()) | |||
9924 | return SDValue(); | |||
9925 | ||||
9926 | // Second is the constant, verify its correct. | |||
9927 | ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); | |||
9928 | ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); | |||
9929 | ||||
9930 | // For the constant, we want to see all the even or all the odd. | |||
9931 | if (!C0 || !C1 || C0->getZExtValue() != nextIndex | |||
9932 | || C1->getZExtValue() != nextIndex+1) | |||
9933 | return SDValue(); | |||
9934 | ||||
9935 | // Increment index. | |||
9936 | nextIndex+=2; | |||
9937 | } else | |||
9938 | return SDValue(); | |||
9939 | } | |||
9940 | ||||
9941 | // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also make sure | |||
9942 | // we're using the entire input vector, otherwise there's a size/legality | |||
9943 | // mismatch somewhere. | |||
9944 | if (nextIndex != Vec.getValueType().getVectorNumElements() || | |||
9945 | Vec.getValueType().getVectorElementType() == VT.getVectorElementType()) | |||
9946 | return SDValue(); | |||
9947 | ||||
9948 | // Create VPADDL node. | |||
9949 | SelectionDAG &DAG = DCI.DAG; | |||
9950 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
9951 | ||||
9952 | SDLoc dl(N); | |||
9953 | ||||
9954 | // Build operand list. | |||
9955 | SmallVector<SDValue, 8> Ops; | |||
9956 | Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl, | |||
9957 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
9958 | ||||
9959 | // Input is the vector. | |||
9960 | Ops.push_back(Vec); | |||
9961 | ||||
9962 | // Get widened type and narrowed type. | |||
9963 | MVT widenType; | |||
9964 | unsigned numElem = VT.getVectorNumElements(); | |||
9965 | ||||
9966 | EVT inputLaneType = Vec.getValueType().getVectorElementType(); | |||
9967 | switch (inputLaneType.getSimpleVT().SimpleTy) { | |||
9968 | case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; | |||
9969 | case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; | |||
9970 | case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; | |||
9971 | default: | |||
9972 | llvm_unreachable("Invalid vector element type for padd optimization.")::llvm::llvm_unreachable_internal("Invalid vector element type for padd optimization." , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 9972); | |||
9973 | } | |||
9974 | ||||
9975 | SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops); | |||
9976 | unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; | |||
9977 | return DAG.getNode(ExtOp, dl, VT, tmp); | |||
9978 | } | |||
9979 | ||||
9980 | static SDValue findMUL_LOHI(SDValue V) { | |||
9981 | if (V->getOpcode() == ISD::UMUL_LOHI || | |||
9982 | V->getOpcode() == ISD::SMUL_LOHI) | |||
9983 | return V; | |||
9984 | return SDValue(); | |||
9985 | } | |||
9986 | ||||
9987 | static SDValue AddCombineTo64BitSMLAL16(SDNode *AddcNode, SDNode *AddeNode, | |||
9988 | TargetLowering::DAGCombinerInfo &DCI, | |||
9989 | const ARMSubtarget *Subtarget) { | |||
9990 | if (Subtarget->isThumb()) { | |||
9991 | if (!Subtarget->hasDSP()) | |||
9992 | return SDValue(); | |||
9993 | } else if (!Subtarget->hasV5TEOps()) | |||
9994 | return SDValue(); | |||
9995 | ||||
9996 | // SMLALBB, SMLALBT, SMLALTB, SMLALTT multiply two 16-bit values and | |||
9997 | // accumulates the product into a 64-bit value. The 16-bit values will | |||
9998 | // be sign extended somehow or SRA'd into 32-bit values | |||
9999 | // (addc (adde (mul 16bit, 16bit), lo), hi) | |||
10000 | SDValue Mul = AddcNode->getOperand(0); | |||
10001 | SDValue Lo = AddcNode->getOperand(1); | |||
10002 | if (Mul.getOpcode() != ISD::MUL) { | |||
10003 | Lo = AddcNode->getOperand(0); | |||
10004 | Mul = AddcNode->getOperand(1); | |||
10005 | if (Mul.getOpcode() != ISD::MUL) | |||
10006 | return SDValue(); | |||
10007 | } | |||
10008 | ||||
10009 | SDValue SRA = AddeNode->getOperand(0); | |||
10010 | SDValue Hi = AddeNode->getOperand(1); | |||
10011 | if (SRA.getOpcode() != ISD::SRA) { | |||
10012 | SRA = AddeNode->getOperand(1); | |||
10013 | Hi = AddeNode->getOperand(0); | |||
10014 | if (SRA.getOpcode() != ISD::SRA) | |||
10015 | return SDValue(); | |||
10016 | } | |||
10017 | if (auto Const = dyn_cast<ConstantSDNode>(SRA.getOperand(1))) { | |||
10018 | if (Const->getZExtValue() != 31) | |||
10019 | return SDValue(); | |||
10020 | } else | |||
10021 | return SDValue(); | |||
10022 | ||||
10023 | if (SRA.getOperand(0) != Mul) | |||
10024 | return SDValue(); | |||
10025 | ||||
10026 | SelectionDAG &DAG = DCI.DAG; | |||
10027 | SDLoc dl(AddcNode); | |||
10028 | unsigned Opcode = 0; | |||
10029 | SDValue Op0; | |||
10030 | SDValue Op1; | |||
10031 | ||||
10032 | if (isS16(Mul.getOperand(0), DAG) && isS16(Mul.getOperand(1), DAG)) { | |||
10033 | Opcode = ARMISD::SMLALBB; | |||
10034 | Op0 = Mul.getOperand(0); | |||
10035 | Op1 = Mul.getOperand(1); | |||
10036 | } else if (isS16(Mul.getOperand(0), DAG) && isSRA16(Mul.getOperand(1))) { | |||
10037 | Opcode = ARMISD::SMLALBT; | |||
10038 | Op0 = Mul.getOperand(0); | |||
10039 | Op1 = Mul.getOperand(1).getOperand(0); | |||
10040 | } else if (isSRA16(Mul.getOperand(0)) && isS16(Mul.getOperand(1), DAG)) { | |||
10041 | Opcode = ARMISD::SMLALTB; | |||
10042 | Op0 = Mul.getOperand(0).getOperand(0); | |||
10043 | Op1 = Mul.getOperand(1); | |||
10044 | } else if (isSRA16(Mul.getOperand(0)) && isSRA16(Mul.getOperand(1))) { | |||
10045 | Opcode = ARMISD::SMLALTT; | |||
10046 | Op0 = Mul->getOperand(0).getOperand(0); | |||
10047 | Op1 = Mul->getOperand(1).getOperand(0); | |||
10048 | } | |||
10049 | ||||
10050 | if (!Op0 || !Op1) | |||
10051 | return SDValue(); | |||
10052 | ||||
10053 | SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), | |||
10054 | Op0, Op1, Lo, Hi); | |||
10055 | // Replace the ADDs' nodes uses by the MLA node's values. | |||
10056 | SDValue HiMLALResult(SMLAL.getNode(), 1); | |||
10057 | SDValue LoMLALResult(SMLAL.getNode(), 0); | |||
10058 | ||||
10059 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult); | |||
10060 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult); | |||
10061 | ||||
10062 | // Return original node to notify the driver to stop replacing. | |||
10063 | SDValue resNode(AddcNode, 0); | |||
10064 | return resNode; | |||
10065 | } | |||
10066 | ||||
10067 | static SDValue AddCombineTo64bitMLAL(SDNode *AddeSubeNode, | |||
10068 | TargetLowering::DAGCombinerInfo &DCI, | |||
10069 | const ARMSubtarget *Subtarget) { | |||
10070 | // Look for multiply add opportunities. | |||
10071 | // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where | |||
10072 | // each add nodes consumes a value from ISD::UMUL_LOHI and there is | |||
10073 | // a glue link from the first add to the second add. | |||
10074 | // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by | |||
10075 | // a S/UMLAL instruction. | |||
10076 | // UMUL_LOHI | |||
10077 | // / :lo \ :hi | |||
10078 | // V \ [no multiline comment] | |||
10079 | // loAdd -> ADDC | | |||
10080 | // \ :carry / | |||
10081 | // V V | |||
10082 | // ADDE <- hiAdd | |||
10083 | // | |||
10084 | // In the special case where only the higher part of a signed result is used | |||
10085 | // and the add to the low part of the result of ISD::UMUL_LOHI adds or subtracts | |||
10086 | // a constant with the exact value of 0x80000000, we recognize we are dealing | |||
10087 | // with a "rounded multiply and add" (or subtract) and transform it into | |||
10088 | // either a ARMISD::SMMLAR or ARMISD::SMMLSR respectively. | |||
10089 | ||||
10090 | assert((AddeSubeNode->getOpcode() == ARMISD::ADDE ||(((AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode ->getOpcode() == ARMISD::SUBE) && "Expect an ADDE or SUBE" ) ? static_cast<void> (0) : __assert_fail ("(AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode->getOpcode() == ARMISD::SUBE) && \"Expect an ADDE or SUBE\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10092, __PRETTY_FUNCTION__)) | |||
10091 | AddeSubeNode->getOpcode() == ARMISD::SUBE) &&(((AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode ->getOpcode() == ARMISD::SUBE) && "Expect an ADDE or SUBE" ) ? static_cast<void> (0) : __assert_fail ("(AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode->getOpcode() == ARMISD::SUBE) && \"Expect an ADDE or SUBE\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10092, __PRETTY_FUNCTION__)) | |||
10092 | "Expect an ADDE or SUBE")(((AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode ->getOpcode() == ARMISD::SUBE) && "Expect an ADDE or SUBE" ) ? static_cast<void> (0) : __assert_fail ("(AddeSubeNode->getOpcode() == ARMISD::ADDE || AddeSubeNode->getOpcode() == ARMISD::SUBE) && \"Expect an ADDE or SUBE\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10092, __PRETTY_FUNCTION__)); | |||
10093 | ||||
10094 | assert(AddeSubeNode->getNumOperands() == 3 &&((AddeSubeNode->getNumOperands() == 3 && AddeSubeNode ->getOperand(2).getValueType() == MVT::i32 && "ADDE node has the wrong inputs" ) ? static_cast<void> (0) : __assert_fail ("AddeSubeNode->getNumOperands() == 3 && AddeSubeNode->getOperand(2).getValueType() == MVT::i32 && \"ADDE node has the wrong inputs\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10096, __PRETTY_FUNCTION__)) | |||
10095 | AddeSubeNode->getOperand(2).getValueType() == MVT::i32 &&((AddeSubeNode->getNumOperands() == 3 && AddeSubeNode ->getOperand(2).getValueType() == MVT::i32 && "ADDE node has the wrong inputs" ) ? static_cast<void> (0) : __assert_fail ("AddeSubeNode->getNumOperands() == 3 && AddeSubeNode->getOperand(2).getValueType() == MVT::i32 && \"ADDE node has the wrong inputs\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10096, __PRETTY_FUNCTION__)) | |||
10096 | "ADDE node has the wrong inputs")((AddeSubeNode->getNumOperands() == 3 && AddeSubeNode ->getOperand(2).getValueType() == MVT::i32 && "ADDE node has the wrong inputs" ) ? static_cast<void> (0) : __assert_fail ("AddeSubeNode->getNumOperands() == 3 && AddeSubeNode->getOperand(2).getValueType() == MVT::i32 && \"ADDE node has the wrong inputs\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10096, __PRETTY_FUNCTION__)); | |||
10097 | ||||
10098 | // Check that we are chained to the right ADDC or SUBC node. | |||
10099 | SDNode *AddcSubcNode = AddeSubeNode->getOperand(2).getNode(); | |||
10100 | if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && | |||
10101 | AddcSubcNode->getOpcode() != ARMISD::ADDC) || | |||
10102 | (AddeSubeNode->getOpcode() == ARMISD::SUBE && | |||
10103 | AddcSubcNode->getOpcode() != ARMISD::SUBC)) | |||
10104 | return SDValue(); | |||
10105 | ||||
10106 | SDValue AddcSubcOp0 = AddcSubcNode->getOperand(0); | |||
10107 | SDValue AddcSubcOp1 = AddcSubcNode->getOperand(1); | |||
10108 | ||||
10109 | // Check if the two operands are from the same mul_lohi node. | |||
10110 | if (AddcSubcOp0.getNode() == AddcSubcOp1.getNode()) | |||
10111 | return SDValue(); | |||
10112 | ||||
10113 | assert(AddcSubcNode->getNumValues() == 2 &&((AddcSubcNode->getNumValues() == 2 && AddcSubcNode ->getValueType(0) == MVT::i32 && "Expect ADDC with two result values. First: i32" ) ? static_cast<void> (0) : __assert_fail ("AddcSubcNode->getNumValues() == 2 && AddcSubcNode->getValueType(0) == MVT::i32 && \"Expect ADDC with two result values. First: i32\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10115, __PRETTY_FUNCTION__)) | |||
10114 | AddcSubcNode->getValueType(0) == MVT::i32 &&((AddcSubcNode->getNumValues() == 2 && AddcSubcNode ->getValueType(0) == MVT::i32 && "Expect ADDC with two result values. First: i32" ) ? static_cast<void> (0) : __assert_fail ("AddcSubcNode->getNumValues() == 2 && AddcSubcNode->getValueType(0) == MVT::i32 && \"Expect ADDC with two result values. First: i32\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10115, __PRETTY_FUNCTION__)) | |||
10115 | "Expect ADDC with two result values. First: i32")((AddcSubcNode->getNumValues() == 2 && AddcSubcNode ->getValueType(0) == MVT::i32 && "Expect ADDC with two result values. First: i32" ) ? static_cast<void> (0) : __assert_fail ("AddcSubcNode->getNumValues() == 2 && AddcSubcNode->getValueType(0) == MVT::i32 && \"Expect ADDC with two result values. First: i32\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 10115, __PRETTY_FUNCTION__)); | |||
10116 | ||||
10117 | // Check that the ADDC adds the low result of the S/UMUL_LOHI. If not, it | |||
10118 | // maybe a SMLAL which multiplies two 16-bit values. | |||
10119 | if (AddeSubeNode->getOpcode() == ARMISD::ADDE && | |||
10120 | AddcSubcOp0->getOpcode() != ISD::UMUL_LOHI && | |||
10121 | AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI && | |||
10122 | AddcSubcOp1->getOpcode() != ISD::UMUL_LOHI && | |||
10123 | AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI) | |||
10124 | return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget); | |||
10125 | ||||
10126 | // Check for the triangle shape. | |||
10127 | SDValue AddeSubeOp0 = AddeSubeNode->getOperand(0); | |||
10128 | SDValue AddeSubeOp1 = AddeSubeNode->getOperand(1); | |||
10129 | ||||
10130 | // Make sure that the ADDE/SUBE operands are not coming from the same node. | |||
10131 | if (AddeSubeOp0.getNode() == AddeSubeOp1.getNode()) | |||
10132 | return SDValue(); | |||
10133 | ||||
10134 | // Find the MUL_LOHI node walking up ADDE/SUBE's operands. | |||
10135 | bool IsLeftOperandMUL = false; | |||
10136 | SDValue MULOp = findMUL_LOHI(AddeSubeOp0); | |||
10137 | if (MULOp == SDValue()) | |||
10138 | MULOp = findMUL_LOHI(AddeSubeOp1); | |||
10139 | else | |||
10140 | IsLeftOperandMUL = true; | |||
10141 | if (MULOp == SDValue()) | |||
10142 | return SDValue(); | |||
10143 | ||||
10144 | // Figure out the right opcode. | |||
10145 | unsigned Opc = MULOp->getOpcode(); | |||
10146 | unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; | |||
10147 | ||||
10148 | // Figure out the high and low input values to the MLAL node. | |||
10149 | SDValue *HiAddSub = nullptr; | |||
10150 | SDValue *LoMul = nullptr; | |||
10151 | SDValue *LowAddSub = nullptr; | |||
10152 | ||||
10153 | // Ensure that ADDE/SUBE is from high result of ISD::xMUL_LOHI. | |||
10154 | if ((AddeSubeOp0 != MULOp.getValue(1)) && (AddeSubeOp1 != MULOp.getValue(1))) | |||
10155 | return SDValue(); | |||
10156 | ||||
10157 | if (IsLeftOperandMUL) | |||
10158 | HiAddSub = &AddeSubeOp1; | |||
10159 | else | |||
10160 | HiAddSub = &AddeSubeOp0; | |||
10161 | ||||
10162 | // Ensure that LoMul and LowAddSub are taken from correct ISD::SMUL_LOHI node | |||
10163 | // whose low result is fed to the ADDC/SUBC we are checking. | |||
10164 | ||||
10165 | if (AddcSubcOp0 == MULOp.getValue(0)) { | |||
10166 | LoMul = &AddcSubcOp0; | |||
10167 | LowAddSub = &AddcSubcOp1; | |||
10168 | } | |||
10169 | if (AddcSubcOp1 == MULOp.getValue(0)) { | |||
10170 | LoMul = &AddcSubcOp1; | |||
10171 | LowAddSub = &AddcSubcOp0; | |||
10172 | } | |||
10173 | ||||
10174 | if (!LoMul) | |||
10175 | return SDValue(); | |||
10176 | ||||
10177 | // If HiAddSub is the same node as ADDC/SUBC or is a predecessor of ADDC/SUBC | |||
10178 | // the replacement below will create a cycle. | |||
10179 | if (AddcSubcNode == HiAddSub->getNode() || | |||
10180 | AddcSubcNode->isPredecessorOf(HiAddSub->getNode())) | |||
10181 | return SDValue(); | |||
10182 | ||||
10183 | // Create the merged node. | |||
10184 | SelectionDAG &DAG = DCI.DAG; | |||
10185 | ||||
10186 | // Start building operand list. | |||
10187 | SmallVector<SDValue, 8> Ops; | |||
10188 | Ops.push_back(LoMul->getOperand(0)); | |||
10189 | Ops.push_back(LoMul->getOperand(1)); | |||
10190 | ||||
10191 | // Check whether we can use SMMLAR, SMMLSR or SMMULR instead. For this to be | |||
10192 | // the case, we must be doing signed multiplication and only use the higher | |||
10193 | // part of the result of the MLAL, furthermore the LowAddSub must be a constant | |||
10194 | // addition or subtraction with the value of 0x800000. | |||
10195 | if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() && | |||
10196 | FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) && | |||
10197 | LowAddSub->getNode()->getOpcode() == ISD::Constant && | |||
10198 | static_cast<ConstantSDNode *>(LowAddSub->getNode())->getZExtValue() == | |||
10199 | 0x80000000) { | |||
10200 | Ops.push_back(*HiAddSub); | |||
10201 | if (AddcSubcNode->getOpcode() == ARMISD::SUBC) { | |||
10202 | FinalOpc = ARMISD::SMMLSR; | |||
10203 | } else { | |||
10204 | FinalOpc = ARMISD::SMMLAR; | |||
10205 | } | |||
10206 | SDValue NewNode = DAG.getNode(FinalOpc, SDLoc(AddcSubcNode), MVT::i32, Ops); | |||
10207 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddeSubeNode, 0), NewNode); | |||
10208 | ||||
10209 | return SDValue(AddeSubeNode, 0); | |||
10210 | } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC) | |||
10211 | // SMMLS is generated during instruction selection and the rest of this | |||
10212 | // function can not handle the case where AddcSubcNode is a SUBC. | |||
10213 | return SDValue(); | |||
10214 | ||||
10215 | // Finish building the operand list for {U/S}MLAL | |||
10216 | Ops.push_back(*LowAddSub); | |||
10217 | Ops.push_back(*HiAddSub); | |||
10218 | ||||
10219 | SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcSubcNode), | |||
10220 | DAG.getVTList(MVT::i32, MVT::i32), Ops); | |||
10221 | ||||
10222 | // Replace the ADDs' nodes uses by the MLA node's values. | |||
10223 | SDValue HiMLALResult(MLALNode.getNode(), 1); | |||
10224 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddeSubeNode, 0), HiMLALResult); | |||
10225 | ||||
10226 | SDValue LoMLALResult(MLALNode.getNode(), 0); | |||
10227 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddcSubcNode, 0), LoMLALResult); | |||
10228 | ||||
10229 | // Return original node to notify the driver to stop replacing. | |||
10230 | return SDValue(AddeSubeNode, 0); | |||
10231 | } | |||
10232 | ||||
10233 | static SDValue AddCombineTo64bitUMAAL(SDNode *AddeNode, | |||
10234 | TargetLowering::DAGCombinerInfo &DCI, | |||
10235 | const ARMSubtarget *Subtarget) { | |||
10236 | // UMAAL is similar to UMLAL except that it adds two unsigned values. | |||
10237 | // While trying to combine for the other MLAL nodes, first search for the | |||
10238 | // chance to use UMAAL. Check if Addc uses a node which has already | |||
10239 | // been combined into a UMLAL. The other pattern is UMLAL using Addc/Adde | |||
10240 | // as the addend, and it's handled in PerformUMLALCombine. | |||
10241 | ||||
10242 | if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) | |||
10243 | return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); | |||
10244 | ||||
10245 | // Check that we have a glued ADDC node. | |||
10246 | SDNode* AddcNode = AddeNode->getOperand(2).getNode(); | |||
10247 | if (AddcNode->getOpcode() != ARMISD::ADDC) | |||
10248 | return SDValue(); | |||
10249 | ||||
10250 | // Find the converted UMAAL or quit if it doesn't exist. | |||
10251 | SDNode *UmlalNode = nullptr; | |||
10252 | SDValue AddHi; | |||
10253 | if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { | |||
10254 | UmlalNode = AddcNode->getOperand(0).getNode(); | |||
10255 | AddHi = AddcNode->getOperand(1); | |||
10256 | } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { | |||
10257 | UmlalNode = AddcNode->getOperand(1).getNode(); | |||
10258 | AddHi = AddcNode->getOperand(0); | |||
10259 | } else { | |||
10260 | return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); | |||
10261 | } | |||
10262 | ||||
10263 | // The ADDC should be glued to an ADDE node, which uses the same UMLAL as | |||
10264 | // the ADDC as well as Zero. | |||
10265 | if (!isNullConstant(UmlalNode->getOperand(3))) | |||
10266 | return SDValue(); | |||
10267 | ||||
10268 | if ((isNullConstant(AddeNode->getOperand(0)) && | |||
10269 | AddeNode->getOperand(1).getNode() == UmlalNode) || | |||
10270 | (AddeNode->getOperand(0).getNode() == UmlalNode && | |||
10271 | isNullConstant(AddeNode->getOperand(1)))) { | |||
10272 | SelectionDAG &DAG = DCI.DAG; | |||
10273 | SDValue Ops[] = { UmlalNode->getOperand(0), UmlalNode->getOperand(1), | |||
10274 | UmlalNode->getOperand(2), AddHi }; | |||
10275 | SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode), | |||
10276 | DAG.getVTList(MVT::i32, MVT::i32), Ops); | |||
10277 | ||||
10278 | // Replace the ADDs' nodes uses by the UMAAL node's values. | |||
10279 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1)); | |||
10280 | DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0)); | |||
10281 | ||||
10282 | // Return original node to notify the driver to stop replacing. | |||
10283 | return SDValue(AddeNode, 0); | |||
10284 | } | |||
10285 | return SDValue(); | |||
10286 | } | |||
10287 | ||||
10288 | static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG, | |||
10289 | const ARMSubtarget *Subtarget) { | |||
10290 | if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) | |||
10291 | return SDValue(); | |||
10292 | ||||
10293 | // Check that we have a pair of ADDC and ADDE as operands. | |||
10294 | // Both addends of the ADDE must be zero. | |||
10295 | SDNode* AddcNode = N->getOperand(2).getNode(); | |||
10296 | SDNode* AddeNode = N->getOperand(3).getNode(); | |||
10297 | if ((AddcNode->getOpcode() == ARMISD::ADDC) && | |||
10298 | (AddeNode->getOpcode() == ARMISD::ADDE) && | |||
10299 | isNullConstant(AddeNode->getOperand(0)) && | |||
10300 | isNullConstant(AddeNode->getOperand(1)) && | |||
10301 | (AddeNode->getOperand(2).getNode() == AddcNode)) | |||
10302 | return DAG.getNode(ARMISD::UMAAL, SDLoc(N), | |||
10303 | DAG.getVTList(MVT::i32, MVT::i32), | |||
10304 | {N->getOperand(0), N->getOperand(1), | |||
10305 | AddcNode->getOperand(0), AddcNode->getOperand(1)}); | |||
10306 | else | |||
10307 | return SDValue(); | |||
10308 | } | |||
10309 | ||||
10310 | static SDValue PerformAddcSubcCombine(SDNode *N, | |||
10311 | TargetLowering::DAGCombinerInfo &DCI, | |||
10312 | const ARMSubtarget *Subtarget) { | |||
10313 | SelectionDAG &DAG(DCI.DAG); | |||
10314 | ||||
10315 | if (N->getOpcode() == ARMISD::SUBC) { | |||
10316 | // (SUBC (ADDE 0, 0, C), 1) -> C | |||
10317 | SDValue LHS = N->getOperand(0); | |||
10318 | SDValue RHS = N->getOperand(1); | |||
10319 | if (LHS->getOpcode() == ARMISD::ADDE && | |||
10320 | isNullConstant(LHS->getOperand(0)) && | |||
10321 | isNullConstant(LHS->getOperand(1)) && isOneConstant(RHS)) { | |||
10322 | return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2)); | |||
10323 | } | |||
10324 | } | |||
10325 | ||||
10326 | if (Subtarget->isThumb1Only()) { | |||
10327 | SDValue RHS = N->getOperand(1); | |||
10328 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { | |||
10329 | int32_t imm = C->getSExtValue(); | |||
10330 | if (imm < 0 && imm > std::numeric_limits<int>::min()) { | |||
10331 | SDLoc DL(N); | |||
10332 | RHS = DAG.getConstant(-imm, DL, MVT::i32); | |||
10333 | unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC | |||
10334 | : ARMISD::ADDC; | |||
10335 | return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS); | |||
10336 | } | |||
10337 | } | |||
10338 | } | |||
10339 | ||||
10340 | return SDValue(); | |||
10341 | } | |||
10342 | ||||
10343 | static SDValue PerformAddeSubeCombine(SDNode *N, | |||
10344 | TargetLowering::DAGCombinerInfo &DCI, | |||
10345 | const ARMSubtarget *Subtarget) { | |||
10346 | if (Subtarget->isThumb1Only()) { | |||
10347 | SelectionDAG &DAG = DCI.DAG; | |||
10348 | SDValue RHS = N->getOperand(1); | |||
10349 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { | |||
10350 | int64_t imm = C->getSExtValue(); | |||
10351 | if (imm < 0) { | |||
10352 | SDLoc DL(N); | |||
10353 | ||||
10354 | // The with-carry-in form matches bitwise not instead of the negation. | |||
10355 | // Effectively, the inverse interpretation of the carry flag already | |||
10356 | // accounts for part of the negation. | |||
10357 | RHS = DAG.getConstant(~imm, DL, MVT::i32); | |||
10358 | ||||
10359 | unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE | |||
10360 | : ARMISD::ADDE; | |||
10361 | return DAG.getNode(Opcode, DL, N->getVTList(), | |||
10362 | N->getOperand(0), RHS, N->getOperand(2)); | |||
10363 | } | |||
10364 | } | |||
10365 | } else if (N->getOperand(1)->getOpcode() == ISD::SMUL_LOHI) { | |||
10366 | return AddCombineTo64bitMLAL(N, DCI, Subtarget); | |||
10367 | } | |||
10368 | return SDValue(); | |||
10369 | } | |||
10370 | ||||
10371 | static SDValue PerformABSCombine(SDNode *N, | |||
10372 | TargetLowering::DAGCombinerInfo &DCI, | |||
10373 | const ARMSubtarget *Subtarget) { | |||
10374 | SDValue res; | |||
10375 | SelectionDAG &DAG = DCI.DAG; | |||
10376 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
10377 | ||||
10378 | if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0))) | |||
10379 | return SDValue(); | |||
10380 | ||||
10381 | if (!TLI.expandABS(N, res, DAG)) | |||
10382 | return SDValue(); | |||
10383 | ||||
10384 | return res; | |||
10385 | } | |||
10386 | ||||
10387 | /// PerformADDECombine - Target-specific dag combine transform from | |||
10388 | /// ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or | |||
10389 | /// ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL | |||
10390 | static SDValue PerformADDECombine(SDNode *N, | |||
10391 | TargetLowering::DAGCombinerInfo &DCI, | |||
10392 | const ARMSubtarget *Subtarget) { | |||
10393 | // Only ARM and Thumb2 support UMLAL/SMLAL. | |||
10394 | if (Subtarget->isThumb1Only()) | |||
10395 | return PerformAddeSubeCombine(N, DCI, Subtarget); | |||
10396 | ||||
10397 | // Only perform the checks after legalize when the pattern is available. | |||
10398 | if (DCI.isBeforeLegalize()) return SDValue(); | |||
10399 | ||||
10400 | return AddCombineTo64bitUMAAL(N, DCI, Subtarget); | |||
10401 | } | |||
10402 | ||||
10403 | /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with | |||
10404 | /// operands N0 and N1. This is a helper for PerformADDCombine that is | |||
10405 | /// called with the default operands, and if that fails, with commuted | |||
10406 | /// operands. | |||
10407 | static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, | |||
10408 | TargetLowering::DAGCombinerInfo &DCI, | |||
10409 | const ARMSubtarget *Subtarget){ | |||
10410 | // Attempt to create vpadd for this add. | |||
10411 | if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) | |||
10412 | return Result; | |||
10413 | ||||
10414 | // Attempt to create vpaddl for this add. | |||
10415 | if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) | |||
10416 | return Result; | |||
10417 | if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI, | |||
10418 | Subtarget)) | |||
10419 | return Result; | |||
10420 | ||||
10421 | // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) | |||
10422 | if (N0.getNode()->hasOneUse()) | |||
10423 | if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) | |||
10424 | return Result; | |||
10425 | return SDValue(); | |||
10426 | } | |||
10427 | ||||
10428 | bool | |||
10429 | ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N, | |||
10430 | CombineLevel Level) const { | |||
10431 | if (Level == BeforeLegalizeTypes) | |||
10432 | return true; | |||
10433 | ||||
10434 | if (N->getOpcode() != ISD::SHL) | |||
10435 | return true; | |||
10436 | ||||
10437 | if (Subtarget->isThumb1Only()) { | |||
10438 | // Avoid making expensive immediates by commuting shifts. (This logic | |||
10439 | // only applies to Thumb1 because ARM and Thumb2 immediates can be shifted | |||
10440 | // for free.) | |||
10441 | if (N->getOpcode() != ISD::SHL) | |||
10442 | return true; | |||
10443 | SDValue N1 = N->getOperand(0); | |||
10444 | if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND && | |||
10445 | N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR) | |||
10446 | return true; | |||
10447 | if (auto *Const = dyn_cast<ConstantSDNode>(N1->getOperand(1))) { | |||
10448 | if (Const->getAPIntValue().ult(256)) | |||
10449 | return false; | |||
10450 | if (N1->getOpcode() == ISD::ADD && Const->getAPIntValue().slt(0) && | |||
10451 | Const->getAPIntValue().sgt(-256)) | |||
10452 | return false; | |||
10453 | } | |||
10454 | return true; | |||
10455 | } | |||
10456 | ||||
10457 | // Turn off commute-with-shift transform after legalization, so it doesn't | |||
10458 | // conflict with PerformSHLSimplify. (We could try to detect when | |||
10459 | // PerformSHLSimplify would trigger more precisely, but it isn't | |||
10460 | // really necessary.) | |||
10461 | return false; | |||
10462 | } | |||
10463 | ||||
10464 | bool ARMTargetLowering::shouldFoldConstantShiftPairToMask( | |||
10465 | const SDNode *N, CombineLevel Level) const { | |||
10466 | if (!Subtarget->isThumb1Only()) | |||
10467 | return true; | |||
10468 | ||||
10469 | if (Level == BeforeLegalizeTypes) | |||
10470 | return true; | |||
10471 | ||||
10472 | return false; | |||
10473 | } | |||
10474 | ||||
10475 | static SDValue PerformSHLSimplify(SDNode *N, | |||
10476 | TargetLowering::DAGCombinerInfo &DCI, | |||
10477 | const ARMSubtarget *ST) { | |||
10478 | // Allow the generic combiner to identify potential bswaps. | |||
10479 | if (DCI.isBeforeLegalize()) | |||
10480 | return SDValue(); | |||
10481 | ||||
10482 | // DAG combiner will fold: | |||
10483 | // (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) | |||
10484 | // (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2 | |||
10485 | // Other code patterns that can be also be modified have the following form: | |||
10486 | // b + ((a << 1) | 510) | |||
10487 | // b + ((a << 1) & 510) | |||
10488 | // b + ((a << 1) ^ 510) | |||
10489 | // b + ((a << 1) + 510) | |||
10490 | ||||
10491 | // Many instructions can perform the shift for free, but it requires both | |||
10492 | // the operands to be registers. If c1 << c2 is too large, a mov immediate | |||
10493 | // instruction will needed. So, unfold back to the original pattern if: | |||
10494 | // - if c1 and c2 are small enough that they don't require mov imms. | |||
10495 | // - the user(s) of the node can perform an shl | |||
10496 | ||||
10497 | // No shifted operands for 16-bit instructions. | |||
10498 | if (ST->isThumb() && ST->isThumb1Only()) | |||
10499 | return SDValue(); | |||
10500 | ||||
10501 | // Check that all the users could perform the shl themselves. | |||
10502 | for (auto U : N->uses()) { | |||
10503 | switch(U->getOpcode()) { | |||
10504 | default: | |||
10505 | return SDValue(); | |||
10506 | case ISD::SUB: | |||
10507 | case ISD::ADD: | |||
10508 | case ISD::AND: | |||
10509 | case ISD::OR: | |||
10510 | case ISD::XOR: | |||
10511 | case ISD::SETCC: | |||
10512 | case ARMISD::CMP: | |||
10513 | // Check that the user isn't already using a constant because there | |||
10514 | // aren't any instructions that support an immediate operand and a | |||
10515 | // shifted operand. | |||
10516 | if (isa<ConstantSDNode>(U->getOperand(0)) || | |||
10517 | isa<ConstantSDNode>(U->getOperand(1))) | |||
10518 | return SDValue(); | |||
10519 | ||||
10520 | // Check that it's not already using a shift. | |||
10521 | if (U->getOperand(0).getOpcode() == ISD::SHL || | |||
10522 | U->getOperand(1).getOpcode() == ISD::SHL) | |||
10523 | return SDValue(); | |||
10524 | break; | |||
10525 | } | |||
10526 | } | |||
10527 | ||||
10528 | if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR && | |||
10529 | N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND) | |||
10530 | return SDValue(); | |||
10531 | ||||
10532 | if (N->getOperand(0).getOpcode() != ISD::SHL) | |||
10533 | return SDValue(); | |||
10534 | ||||
10535 | SDValue SHL = N->getOperand(0); | |||
10536 | ||||
10537 | auto *C1ShlC2 = dyn_cast<ConstantSDNode>(N->getOperand(1)); | |||
10538 | auto *C2 = dyn_cast<ConstantSDNode>(SHL.getOperand(1)); | |||
10539 | if (!C1ShlC2 || !C2) | |||
10540 | return SDValue(); | |||
10541 | ||||
10542 | APInt C2Int = C2->getAPIntValue(); | |||
10543 | APInt C1Int = C1ShlC2->getAPIntValue(); | |||
10544 | ||||
10545 | // Check that performing a lshr will not lose any information. | |||
10546 | APInt Mask = APInt::getHighBitsSet(C2Int.getBitWidth(), | |||
10547 | C2Int.getBitWidth() - C2->getZExtValue()); | |||
10548 | if ((C1Int & Mask) != C1Int) | |||
10549 | return SDValue(); | |||
10550 | ||||
10551 | // Shift the first constant. | |||
10552 | C1Int.lshrInPlace(C2Int); | |||
10553 | ||||
10554 | // The immediates are encoded as an 8-bit value that can be rotated. | |||
10555 | auto LargeImm = [](const APInt &Imm) { | |||
10556 | unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros(); | |||
10557 | return Imm.getBitWidth() - Zeros > 8; | |||
10558 | }; | |||
10559 | ||||
10560 | if (LargeImm(C1Int) || LargeImm(C2Int)) | |||
10561 | return SDValue(); | |||
10562 | ||||
10563 | SelectionDAG &DAG = DCI.DAG; | |||
10564 | SDLoc dl(N); | |||
10565 | SDValue X = SHL.getOperand(0); | |||
10566 | SDValue BinOp = DAG.getNode(N->getOpcode(), dl, MVT::i32, X, | |||
10567 | DAG.getConstant(C1Int, dl, MVT::i32)); | |||
10568 | // Shift left to compensate for the lshr of C1Int. | |||
10569 | SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); | |||
10570 | ||||
10571 | LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { dbgs() << "Simplify shl use:\n"; SHL.getOperand (0).dump(); SHL.dump(); N->dump(); } } while (false) | |||
10572 | SHL.dump(); N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { dbgs() << "Simplify shl use:\n"; SHL.getOperand (0).dump(); SHL.dump(); N->dump(); } } while (false); | |||
10573 | LLVM_DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { dbgs() << "Into:\n"; X.dump(); BinOp.dump (); Res.dump(); } } while (false); | |||
10574 | return Res; | |||
10575 | } | |||
10576 | ||||
10577 | ||||
10578 | /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. | |||
10579 | /// | |||
10580 | static SDValue PerformADDCombine(SDNode *N, | |||
10581 | TargetLowering::DAGCombinerInfo &DCI, | |||
10582 | const ARMSubtarget *Subtarget) { | |||
10583 | SDValue N0 = N->getOperand(0); | |||
10584 | SDValue N1 = N->getOperand(1); | |||
10585 | ||||
10586 | // Only works one way, because it needs an immediate operand. | |||
10587 | if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) | |||
10588 | return Result; | |||
10589 | ||||
10590 | // First try with the default operand order. | |||
10591 | if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) | |||
10592 | return Result; | |||
10593 | ||||
10594 | // If that didn't work, try again with the operands commuted. | |||
10595 | return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); | |||
10596 | } | |||
10597 | ||||
10598 | /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. | |||
10599 | /// | |||
10600 | static SDValue PerformSUBCombine(SDNode *N, | |||
10601 | TargetLowering::DAGCombinerInfo &DCI) { | |||
10602 | SDValue N0 = N->getOperand(0); | |||
10603 | SDValue N1 = N->getOperand(1); | |||
10604 | ||||
10605 | // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) | |||
10606 | if (N1.getNode()->hasOneUse()) | |||
10607 | if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) | |||
10608 | return Result; | |||
10609 | ||||
10610 | return SDValue(); | |||
10611 | } | |||
10612 | ||||
10613 | /// PerformVMULCombine | |||
10614 | /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the | |||
10615 | /// special multiplier accumulator forwarding. | |||
10616 | /// vmul d3, d0, d2 | |||
10617 | /// vmla d3, d1, d2 | |||
10618 | /// is faster than | |||
10619 | /// vadd d3, d0, d1 | |||
10620 | /// vmul d3, d3, d2 | |||
10621 | // However, for (A + B) * (A + B), | |||
10622 | // vadd d2, d0, d1 | |||
10623 | // vmul d3, d0, d2 | |||
10624 | // vmla d3, d1, d2 | |||
10625 | // is slower than | |||
10626 | // vadd d2, d0, d1 | |||
10627 | // vmul d3, d2, d2 | |||
10628 | static SDValue PerformVMULCombine(SDNode *N, | |||
10629 | TargetLowering::DAGCombinerInfo &DCI, | |||
10630 | const ARMSubtarget *Subtarget) { | |||
10631 | if (!Subtarget->hasVMLxForwarding()) | |||
10632 | return SDValue(); | |||
10633 | ||||
10634 | SelectionDAG &DAG = DCI.DAG; | |||
10635 | SDValue N0 = N->getOperand(0); | |||
10636 | SDValue N1 = N->getOperand(1); | |||
10637 | unsigned Opcode = N0.getOpcode(); | |||
10638 | if (Opcode != ISD::ADD && Opcode != ISD::SUB && | |||
10639 | Opcode != ISD::FADD && Opcode != ISD::FSUB) { | |||
10640 | Opcode = N1.getOpcode(); | |||
10641 | if (Opcode != ISD::ADD && Opcode != ISD::SUB && | |||
10642 | Opcode != ISD::FADD && Opcode != ISD::FSUB) | |||
10643 | return SDValue(); | |||
10644 | std::swap(N0, N1); | |||
10645 | } | |||
10646 | ||||
10647 | if (N0 == N1) | |||
10648 | return SDValue(); | |||
10649 | ||||
10650 | EVT VT = N->getValueType(0); | |||
10651 | SDLoc DL(N); | |||
10652 | SDValue N00 = N0->getOperand(0); | |||
10653 | SDValue N01 = N0->getOperand(1); | |||
10654 | return DAG.getNode(Opcode, DL, VT, | |||
10655 | DAG.getNode(ISD::MUL, DL, VT, N00, N1), | |||
10656 | DAG.getNode(ISD::MUL, DL, VT, N01, N1)); | |||
10657 | } | |||
10658 | ||||
10659 | static SDValue PerformMULCombine(SDNode *N, | |||
10660 | TargetLowering::DAGCombinerInfo &DCI, | |||
10661 | const ARMSubtarget *Subtarget) { | |||
10662 | SelectionDAG &DAG = DCI.DAG; | |||
10663 | ||||
10664 | if (Subtarget->isThumb1Only()) | |||
10665 | return SDValue(); | |||
10666 | ||||
10667 | if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) | |||
10668 | return SDValue(); | |||
10669 | ||||
10670 | EVT VT = N->getValueType(0); | |||
10671 | if (VT.is64BitVector() || VT.is128BitVector()) | |||
10672 | return PerformVMULCombine(N, DCI, Subtarget); | |||
10673 | if (VT != MVT::i32) | |||
10674 | return SDValue(); | |||
10675 | ||||
10676 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); | |||
10677 | if (!C) | |||
10678 | return SDValue(); | |||
10679 | ||||
10680 | int64_t MulAmt = C->getSExtValue(); | |||
10681 | unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt); | |||
10682 | ||||
10683 | ShiftAmt = ShiftAmt & (32 - 1); | |||
10684 | SDValue V = N->getOperand(0); | |||
10685 | SDLoc DL(N); | |||
10686 | ||||
10687 | SDValue Res; | |||
10688 | MulAmt >>= ShiftAmt; | |||
10689 | ||||
10690 | if (MulAmt >= 0) { | |||
10691 | if (isPowerOf2_32(MulAmt - 1)) { | |||
10692 | // (mul x, 2^N + 1) => (add (shl x, N), x) | |||
10693 | Res = DAG.getNode(ISD::ADD, DL, VT, | |||
10694 | V, | |||
10695 | DAG.getNode(ISD::SHL, DL, VT, | |||
10696 | V, | |||
10697 | DAG.getConstant(Log2_32(MulAmt - 1), DL, | |||
10698 | MVT::i32))); | |||
10699 | } else if (isPowerOf2_32(MulAmt + 1)) { | |||
10700 | // (mul x, 2^N - 1) => (sub (shl x, N), x) | |||
10701 | Res = DAG.getNode(ISD::SUB, DL, VT, | |||
10702 | DAG.getNode(ISD::SHL, DL, VT, | |||
10703 | V, | |||
10704 | DAG.getConstant(Log2_32(MulAmt + 1), DL, | |||
10705 | MVT::i32)), | |||
10706 | V); | |||
10707 | } else | |||
10708 | return SDValue(); | |||
10709 | } else { | |||
10710 | uint64_t MulAmtAbs = -MulAmt; | |||
10711 | if (isPowerOf2_32(MulAmtAbs + 1)) { | |||
10712 | // (mul x, -(2^N - 1)) => (sub x, (shl x, N)) | |||
10713 | Res = DAG.getNode(ISD::SUB, DL, VT, | |||
10714 | V, | |||
10715 | DAG.getNode(ISD::SHL, DL, VT, | |||
10716 | V, | |||
10717 | DAG.getConstant(Log2_32(MulAmtAbs + 1), DL, | |||
10718 | MVT::i32))); | |||
10719 | } else if (isPowerOf2_32(MulAmtAbs - 1)) { | |||
10720 | // (mul x, -(2^N + 1)) => - (add (shl x, N), x) | |||
10721 | Res = DAG.getNode(ISD::ADD, DL, VT, | |||
10722 | V, | |||
10723 | DAG.getNode(ISD::SHL, DL, VT, | |||
10724 | V, | |||
10725 | DAG.getConstant(Log2_32(MulAmtAbs - 1), DL, | |||
10726 | MVT::i32))); | |||
10727 | Res = DAG.getNode(ISD::SUB, DL, VT, | |||
10728 | DAG.getConstant(0, DL, MVT::i32), Res); | |||
10729 | } else | |||
10730 | return SDValue(); | |||
10731 | } | |||
10732 | ||||
10733 | if (ShiftAmt != 0) | |||
10734 | Res = DAG.getNode(ISD::SHL, DL, VT, | |||
10735 | Res, DAG.getConstant(ShiftAmt, DL, MVT::i32)); | |||
10736 | ||||
10737 | // Do not add new nodes to DAG combiner worklist. | |||
10738 | DCI.CombineTo(N, Res, false); | |||
10739 | return SDValue(); | |||
10740 | } | |||
10741 | ||||
10742 | static SDValue CombineANDShift(SDNode *N, | |||
10743 | TargetLowering::DAGCombinerInfo &DCI, | |||
10744 | const ARMSubtarget *Subtarget) { | |||
10745 | // Allow DAGCombine to pattern-match before we touch the canonical form. | |||
10746 | if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) | |||
10747 | return SDValue(); | |||
10748 | ||||
10749 | if (N->getValueType(0) != MVT::i32) | |||
10750 | return SDValue(); | |||
10751 | ||||
10752 | ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)); | |||
10753 | if (!N1C) | |||
10754 | return SDValue(); | |||
10755 | ||||
10756 | uint32_t C1 = (uint32_t)N1C->getZExtValue(); | |||
10757 | // Don't transform uxtb/uxth. | |||
10758 | if (C1 == 255 || C1 == 65535) | |||
10759 | return SDValue(); | |||
10760 | ||||
10761 | SDNode *N0 = N->getOperand(0).getNode(); | |||
10762 | if (!N0->hasOneUse()) | |||
10763 | return SDValue(); | |||
10764 | ||||
10765 | if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL) | |||
10766 | return SDValue(); | |||
10767 | ||||
10768 | bool LeftShift = N0->getOpcode() == ISD::SHL; | |||
10769 | ||||
10770 | ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1)); | |||
10771 | if (!N01C) | |||
10772 | return SDValue(); | |||
10773 | ||||
10774 | uint32_t C2 = (uint32_t)N01C->getZExtValue(); | |||
10775 | if (!C2 || C2 >= 32) | |||
10776 | return SDValue(); | |||
10777 | ||||
10778 | // Clear irrelevant bits in the mask. | |||
10779 | if (LeftShift) | |||
10780 | C1 &= (-1U << C2); | |||
10781 | else | |||
10782 | C1 &= (-1U >> C2); | |||
10783 | ||||
10784 | SelectionDAG &DAG = DCI.DAG; | |||
10785 | SDLoc DL(N); | |||
10786 | ||||
10787 | // We have a pattern of the form "(and (shl x, c2) c1)" or | |||
10788 | // "(and (srl x, c2) c1)", where c1 is a shifted mask. Try to | |||
10789 | // transform to a pair of shifts, to save materializing c1. | |||
10790 | ||||
10791 | // First pattern: right shift, then mask off leading bits. | |||
10792 | // FIXME: Use demanded bits? | |||
10793 | if (!LeftShift && isMask_32(C1)) { | |||
10794 | uint32_t C3 = countLeadingZeros(C1); | |||
10795 | if (C2 < C3) { | |||
10796 | SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), | |||
10797 | DAG.getConstant(C3 - C2, DL, MVT::i32)); | |||
10798 | return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, | |||
10799 | DAG.getConstant(C3, DL, MVT::i32)); | |||
10800 | } | |||
10801 | } | |||
10802 | ||||
10803 | // First pattern, reversed: left shift, then mask off trailing bits. | |||
10804 | if (LeftShift && isMask_32(~C1)) { | |||
10805 | uint32_t C3 = countTrailingZeros(C1); | |||
10806 | if (C2 < C3) { | |||
10807 | SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), | |||
10808 | DAG.getConstant(C3 - C2, DL, MVT::i32)); | |||
10809 | return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, | |||
10810 | DAG.getConstant(C3, DL, MVT::i32)); | |||
10811 | } | |||
10812 | } | |||
10813 | ||||
10814 | // Second pattern: left shift, then mask off leading bits. | |||
10815 | // FIXME: Use demanded bits? | |||
10816 | if (LeftShift && isShiftedMask_32(C1)) { | |||
10817 | uint32_t Trailing = countTrailingZeros(C1); | |||
10818 | uint32_t C3 = countLeadingZeros(C1); | |||
10819 | if (Trailing == C2 && C2 + C3 < 32) { | |||
10820 | SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), | |||
10821 | DAG.getConstant(C2 + C3, DL, MVT::i32)); | |||
10822 | return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, | |||
10823 | DAG.getConstant(C3, DL, MVT::i32)); | |||
10824 | } | |||
10825 | } | |||
10826 | ||||
10827 | // Second pattern, reversed: right shift, then mask off trailing bits. | |||
10828 | // FIXME: Handle other patterns of known/demanded bits. | |||
10829 | if (!LeftShift && isShiftedMask_32(C1)) { | |||
10830 | uint32_t Leading = countLeadingZeros(C1); | |||
10831 | uint32_t C3 = countTrailingZeros(C1); | |||
10832 | if (Leading == C2 && C2 + C3 < 32) { | |||
10833 | SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), | |||
10834 | DAG.getConstant(C2 + C3, DL, MVT::i32)); | |||
10835 | return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, | |||
10836 | DAG.getConstant(C3, DL, MVT::i32)); | |||
10837 | } | |||
10838 | } | |||
10839 | ||||
10840 | // FIXME: Transform "(and (shl x, c2) c1)" -> | |||
10841 | // "(shl (and x, c1>>c2), c2)" if "c1 >> c2" is a cheaper immediate than | |||
10842 | // c1. | |||
10843 | return SDValue(); | |||
10844 | } | |||
10845 | ||||
10846 | static SDValue PerformANDCombine(SDNode *N, | |||
10847 | TargetLowering::DAGCombinerInfo &DCI, | |||
10848 | const ARMSubtarget *Subtarget) { | |||
10849 | // Attempt to use immediate-form VBIC | |||
10850 | BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); | |||
10851 | SDLoc dl(N); | |||
10852 | EVT VT = N->getValueType(0); | |||
10853 | SelectionDAG &DAG = DCI.DAG; | |||
10854 | ||||
10855 | if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) | |||
10856 | return SDValue(); | |||
10857 | ||||
10858 | APInt SplatBits, SplatUndef; | |||
10859 | unsigned SplatBitSize; | |||
10860 | bool HasAnyUndefs; | |||
10861 | if (BVN && | |||
10862 | BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { | |||
10863 | if (SplatBitSize <= 64) { | |||
10864 | EVT VbicVT; | |||
10865 | SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), | |||
10866 | SplatUndef.getZExtValue(), SplatBitSize, | |||
10867 | DAG, dl, VbicVT, VT.is128BitVector(), | |||
10868 | OtherModImm); | |||
10869 | if (Val.getNode()) { | |||
10870 | SDValue Input = | |||
10871 | DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); | |||
10872 | SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); | |||
10873 | return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); | |||
10874 | } | |||
10875 | } | |||
10876 | } | |||
10877 | ||||
10878 | if (!Subtarget->isThumb1Only()) { | |||
10879 | // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) | |||
10880 | if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI)) | |||
10881 | return Result; | |||
10882 | ||||
10883 | if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) | |||
10884 | return Result; | |||
10885 | } | |||
10886 | ||||
10887 | if (Subtarget->isThumb1Only()) | |||
10888 | if (SDValue Result = CombineANDShift(N, DCI, Subtarget)) | |||
10889 | return Result; | |||
10890 | ||||
10891 | return SDValue(); | |||
10892 | } | |||
10893 | ||||
10894 | // Try combining OR nodes to SMULWB, SMULWT. | |||
10895 | static SDValue PerformORCombineToSMULWBT(SDNode *OR, | |||
10896 | TargetLowering::DAGCombinerInfo &DCI, | |||
10897 | const ARMSubtarget *Subtarget) { | |||
10898 | if (!Subtarget->hasV6Ops() || | |||
10899 | (Subtarget->isThumb() && | |||
10900 | (!Subtarget->hasThumb2() || !Subtarget->hasDSP()))) | |||
10901 | return SDValue(); | |||
10902 | ||||
10903 | SDValue SRL = OR->getOperand(0); | |||
10904 | SDValue SHL = OR->getOperand(1); | |||
10905 | ||||
10906 | if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) { | |||
10907 | SRL = OR->getOperand(1); | |||
10908 | SHL = OR->getOperand(0); | |||
10909 | } | |||
10910 | if (!isSRL16(SRL) || !isSHL16(SHL)) | |||
10911 | return SDValue(); | |||
10912 | ||||
10913 | // The first operands to the shifts need to be the two results from the | |||
10914 | // same smul_lohi node. | |||
10915 | if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) || | |||
10916 | SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI) | |||
10917 | return SDValue(); | |||
10918 | ||||
10919 | SDNode *SMULLOHI = SRL.getOperand(0).getNode(); | |||
10920 | if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) || | |||
10921 | SHL.getOperand(0) != SDValue(SMULLOHI, 1)) | |||
10922 | return SDValue(); | |||
10923 | ||||
10924 | // Now we have: | |||
10925 | // (or (srl (smul_lohi ?, ?), 16), (shl (smul_lohi ?, ?), 16))) | |||
10926 | // For SMUL[B|T] smul_lohi will take a 32-bit and a 16-bit arguments. | |||
10927 | // For SMUWB the 16-bit value will signed extended somehow. | |||
10928 | // For SMULWT only the SRA is required. | |||
10929 | // Check both sides of SMUL_LOHI | |||
10930 | SDValue OpS16 = SMULLOHI->getOperand(0); | |||
10931 | SDValue OpS32 = SMULLOHI->getOperand(1); | |||
10932 | ||||
10933 | SelectionDAG &DAG = DCI.DAG; | |||
10934 | if (!isS16(OpS16, DAG) && !isSRA16(OpS16)) { | |||
10935 | OpS16 = OpS32; | |||
10936 | OpS32 = SMULLOHI->getOperand(0); | |||
10937 | } | |||
10938 | ||||
10939 | SDLoc dl(OR); | |||
10940 | unsigned Opcode = 0; | |||
10941 | if (isS16(OpS16, DAG)) | |||
10942 | Opcode = ARMISD::SMULWB; | |||
10943 | else if (isSRA16(OpS16)) { | |||
10944 | Opcode = ARMISD::SMULWT; | |||
10945 | OpS16 = OpS16->getOperand(0); | |||
10946 | } | |||
10947 | else | |||
10948 | return SDValue(); | |||
10949 | ||||
10950 | SDValue Res = DAG.getNode(Opcode, dl, MVT::i32, OpS32, OpS16); | |||
10951 | DAG.ReplaceAllUsesOfValueWith(SDValue(OR, 0), Res); | |||
10952 | return SDValue(OR, 0); | |||
10953 | } | |||
10954 | ||||
10955 | static SDValue PerformORCombineToBFI(SDNode *N, | |||
10956 | TargetLowering::DAGCombinerInfo &DCI, | |||
10957 | const ARMSubtarget *Subtarget) { | |||
10958 | // BFI is only available on V6T2+ | |||
10959 | if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) | |||
10960 | return SDValue(); | |||
10961 | ||||
10962 | EVT VT = N->getValueType(0); | |||
10963 | SDValue N0 = N->getOperand(0); | |||
10964 | SDValue N1 = N->getOperand(1); | |||
10965 | SelectionDAG &DAG = DCI.DAG; | |||
10966 | SDLoc DL(N); | |||
10967 | // 1) or (and A, mask), val => ARMbfi A, val, mask | |||
10968 | // iff (val & mask) == val | |||
10969 | // | |||
10970 | // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask | |||
10971 | // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) | |||
10972 | // && mask == ~mask2 | |||
10973 | // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) | |||
10974 | // && ~mask == mask2 | |||
10975 | // (i.e., copy a bitfield value into another bitfield of the same width) | |||
10976 | ||||
10977 | if (VT != MVT::i32) | |||
10978 | return SDValue(); | |||
10979 | ||||
10980 | SDValue N00 = N0.getOperand(0); | |||
10981 | ||||
10982 | // The value and the mask need to be constants so we can verify this is | |||
10983 | // actually a bitfield set. If the mask is 0xffff, we can do better | |||
10984 | // via a movt instruction, so don't use BFI in that case. | |||
10985 | SDValue MaskOp = N0.getOperand(1); | |||
10986 | ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); | |||
10987 | if (!MaskC) | |||
10988 | return SDValue(); | |||
10989 | unsigned Mask = MaskC->getZExtValue(); | |||
10990 | if (Mask == 0xffff) | |||
10991 | return SDValue(); | |||
10992 | SDValue Res; | |||
10993 | // Case (1): or (and A, mask), val => ARMbfi A, val, mask | |||
10994 | ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); | |||
10995 | if (N1C) { | |||
10996 | unsigned Val = N1C->getZExtValue(); | |||
10997 | if ((Val & ~Mask) != Val) | |||
10998 | return SDValue(); | |||
10999 | ||||
11000 | if (ARM::isBitFieldInvertedMask(Mask)) { | |||
11001 | Val >>= countTrailingZeros(~Mask); | |||
11002 | ||||
11003 | Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, | |||
11004 | DAG.getConstant(Val, DL, MVT::i32), | |||
11005 | DAG.getConstant(Mask, DL, MVT::i32)); | |||
11006 | ||||
11007 | DCI.CombineTo(N, Res, false); | |||
11008 | // Return value from the original node to inform the combiner than N is | |||
11009 | // now dead. | |||
11010 | return SDValue(N, 0); | |||
11011 | } | |||
11012 | } else if (N1.getOpcode() == ISD::AND) { | |||
11013 | // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask | |||
11014 | ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); | |||
11015 | if (!N11C) | |||
11016 | return SDValue(); | |||
11017 | unsigned Mask2 = N11C->getZExtValue(); | |||
11018 | ||||
11019 | // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern | |||
11020 | // as is to match. | |||
11021 | if (ARM::isBitFieldInvertedMask(Mask) && | |||
11022 | (Mask == ~Mask2)) { | |||
11023 | // The pack halfword instruction works better for masks that fit it, | |||
11024 | // so use that when it's available. | |||
11025 | if (Subtarget->hasDSP() && | |||
11026 | (Mask == 0xffff || Mask == 0xffff0000)) | |||
11027 | return SDValue(); | |||
11028 | // 2a | |||
11029 | unsigned amt = countTrailingZeros(Mask2); | |||
11030 | Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), | |||
11031 | DAG.getConstant(amt, DL, MVT::i32)); | |||
11032 | Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, | |||
11033 | DAG.getConstant(Mask, DL, MVT::i32)); | |||
11034 | DCI.CombineTo(N, Res, false); | |||
11035 | // Return value from the original node to inform the combiner than N is | |||
11036 | // now dead. | |||
11037 | return SDValue(N, 0); | |||
11038 | } else if (ARM::isBitFieldInvertedMask(~Mask) && | |||
11039 | (~Mask == Mask2)) { | |||
11040 | // The pack halfword instruction works better for masks that fit it, | |||
11041 | // so use that when it's available. | |||
11042 | if (Subtarget->hasDSP() && | |||
11043 | (Mask2 == 0xffff || Mask2 == 0xffff0000)) | |||
11044 | return SDValue(); | |||
11045 | // 2b | |||
11046 | unsigned lsb = countTrailingZeros(Mask); | |||
11047 | Res = DAG.getNode(ISD::SRL, DL, VT, N00, | |||
11048 | DAG.getConstant(lsb, DL, MVT::i32)); | |||
11049 | Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, | |||
11050 | DAG.getConstant(Mask2, DL, MVT::i32)); | |||
11051 | DCI.CombineTo(N, Res, false); | |||
11052 | // Return value from the original node to inform the combiner than N is | |||
11053 | // now dead. | |||
11054 | return SDValue(N, 0); | |||
11055 | } | |||
11056 | } | |||
11057 | ||||
11058 | if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && | |||
11059 | N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && | |||
11060 | ARM::isBitFieldInvertedMask(~Mask)) { | |||
11061 | // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask | |||
11062 | // where lsb(mask) == #shamt and masked bits of B are known zero. | |||
11063 | SDValue ShAmt = N00.getOperand(1); | |||
11064 | unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); | |||
11065 | unsigned LSB = countTrailingZeros(Mask); | |||
11066 | if (ShAmtC != LSB) | |||
11067 | return SDValue(); | |||
11068 | ||||
11069 | Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), | |||
11070 | DAG.getConstant(~Mask, DL, MVT::i32)); | |||
11071 | ||||
11072 | DCI.CombineTo(N, Res, false); | |||
11073 | // Return value from the original node to inform the combiner than N is | |||
11074 | // now dead. | |||
11075 | return SDValue(N, 0); | |||
11076 | } | |||
11077 | ||||
11078 | return SDValue(); | |||
11079 | } | |||
11080 | ||||
11081 | /// PerformORCombine - Target-specific dag combine xforms for ISD::OR | |||
11082 | static SDValue PerformORCombine(SDNode *N, | |||
11083 | TargetLowering::DAGCombinerInfo &DCI, | |||
11084 | const ARMSubtarget *Subtarget) { | |||
11085 | // Attempt to use immediate-form VORR | |||
11086 | BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); | |||
11087 | SDLoc dl(N); | |||
11088 | EVT VT = N->getValueType(0); | |||
11089 | SelectionDAG &DAG = DCI.DAG; | |||
11090 | ||||
11091 | if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) | |||
11092 | return SDValue(); | |||
11093 | ||||
11094 | APInt SplatBits, SplatUndef; | |||
11095 | unsigned SplatBitSize; | |||
11096 | bool HasAnyUndefs; | |||
11097 | if (BVN && Subtarget->hasNEON() && | |||
11098 | BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { | |||
11099 | if (SplatBitSize <= 64) { | |||
11100 | EVT VorrVT; | |||
11101 | SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), | |||
11102 | SplatUndef.getZExtValue(), SplatBitSize, | |||
11103 | DAG, dl, VorrVT, VT.is128BitVector(), | |||
11104 | OtherModImm); | |||
11105 | if (Val.getNode()) { | |||
11106 | SDValue Input = | |||
11107 | DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); | |||
11108 | SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); | |||
11109 | return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); | |||
11110 | } | |||
11111 | } | |||
11112 | } | |||
11113 | ||||
11114 | if (!Subtarget->isThumb1Only()) { | |||
11115 | // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) | |||
11116 | if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) | |||
11117 | return Result; | |||
11118 | if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget)) | |||
11119 | return Result; | |||
11120 | } | |||
11121 | ||||
11122 | SDValue N0 = N->getOperand(0); | |||
11123 | SDValue N1 = N->getOperand(1); | |||
11124 | ||||
11125 | // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. | |||
11126 | if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && | |||
11127 | DAG.getTargetLoweringInfo().isTypeLegal(VT)) { | |||
11128 | ||||
11129 | // The code below optimizes (or (and X, Y), Z). | |||
11130 | // The AND operand needs to have a single user to make these optimizations | |||
11131 | // profitable. | |||
11132 | if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) | |||
11133 | return SDValue(); | |||
11134 | ||||
11135 | APInt SplatUndef; | |||
11136 | unsigned SplatBitSize; | |||
11137 | bool HasAnyUndefs; | |||
11138 | ||||
11139 | APInt SplatBits0, SplatBits1; | |||
11140 | BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); | |||
11141 | BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); | |||
11142 | // Ensure that the second operand of both ands are constants | |||
11143 | if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, | |||
11144 | HasAnyUndefs) && !HasAnyUndefs) { | |||
11145 | if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, | |||
11146 | HasAnyUndefs) && !HasAnyUndefs) { | |||
11147 | // Ensure that the bit width of the constants are the same and that | |||
11148 | // the splat arguments are logical inverses as per the pattern we | |||
11149 | // are trying to simplify. | |||
11150 | if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() && | |||
11151 | SplatBits0 == ~SplatBits1) { | |||
11152 | // Canonicalize the vector type to make instruction selection | |||
11153 | // simpler. | |||
11154 | EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; | |||
11155 | SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, | |||
11156 | N0->getOperand(1), | |||
11157 | N0->getOperand(0), | |||
11158 | N1->getOperand(0)); | |||
11159 | return DAG.getNode(ISD::BITCAST, dl, VT, Result); | |||
11160 | } | |||
11161 | } | |||
11162 | } | |||
11163 | } | |||
11164 | ||||
11165 | // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when | |||
11166 | // reasonable. | |||
11167 | if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) { | |||
11168 | if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget)) | |||
11169 | return Res; | |||
11170 | } | |||
11171 | ||||
11172 | if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) | |||
11173 | return Result; | |||
11174 | ||||
11175 | return SDValue(); | |||
11176 | } | |||
11177 | ||||
11178 | static SDValue PerformXORCombine(SDNode *N, | |||
11179 | TargetLowering::DAGCombinerInfo &DCI, | |||
11180 | const ARMSubtarget *Subtarget) { | |||
11181 | EVT VT = N->getValueType(0); | |||
11182 | SelectionDAG &DAG = DCI.DAG; | |||
11183 | ||||
11184 | if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) | |||
11185 | return SDValue(); | |||
11186 | ||||
11187 | if (!Subtarget->isThumb1Only()) { | |||
11188 | // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) | |||
11189 | if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) | |||
11190 | return Result; | |||
11191 | ||||
11192 | if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) | |||
11193 | return Result; | |||
11194 | } | |||
11195 | ||||
11196 | return SDValue(); | |||
11197 | } | |||
11198 | ||||
11199 | // ParseBFI - given a BFI instruction in N, extract the "from" value (Rn) and return it, | |||
11200 | // and fill in FromMask and ToMask with (consecutive) bits in "from" to be extracted and | |||
11201 | // their position in "to" (Rd). | |||
11202 | static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) { | |||
11203 | assert(N->getOpcode() == ARMISD::BFI)((N->getOpcode() == ARMISD::BFI) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ARMISD::BFI", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11203, __PRETTY_FUNCTION__)); | |||
11204 | ||||
11205 | SDValue From = N->getOperand(1); | |||
11206 | ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue(); | |||
11207 | FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation()); | |||
11208 | ||||
11209 | // If the Base came from a SHR #C, we can deduce that it is really testing bit | |||
11210 | // #C in the base of the SHR. | |||
11211 | if (From->getOpcode() == ISD::SRL && | |||
11212 | isa<ConstantSDNode>(From->getOperand(1))) { | |||
11213 | APInt Shift = cast<ConstantSDNode>(From->getOperand(1))->getAPIntValue(); | |||
11214 | assert(Shift.getLimitedValue() < 32 && "Shift too large!")((Shift.getLimitedValue() < 32 && "Shift too large!" ) ? static_cast<void> (0) : __assert_fail ("Shift.getLimitedValue() < 32 && \"Shift too large!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11214, __PRETTY_FUNCTION__)); | |||
11215 | FromMask <<= Shift.getLimitedValue(31); | |||
11216 | From = From->getOperand(0); | |||
11217 | } | |||
11218 | ||||
11219 | return From; | |||
11220 | } | |||
11221 | ||||
11222 | // If A and B contain one contiguous set of bits, does A | B == A . B? | |||
11223 | // | |||
11224 | // Neither A nor B must be zero. | |||
11225 | static bool BitsProperlyConcatenate(const APInt &A, const APInt &B) { | |||
11226 | unsigned LastActiveBitInA = A.countTrailingZeros(); | |||
11227 | unsigned FirstActiveBitInB = B.getBitWidth() - B.countLeadingZeros() - 1; | |||
11228 | return LastActiveBitInA - 1 == FirstActiveBitInB; | |||
11229 | } | |||
11230 | ||||
11231 | static SDValue FindBFIToCombineWith(SDNode *N) { | |||
11232 | // We have a BFI in N. Follow a possible chain of BFIs and find a BFI it can combine with, | |||
11233 | // if one exists. | |||
11234 | APInt ToMask, FromMask; | |||
11235 | SDValue From = ParseBFI(N, ToMask, FromMask); | |||
11236 | SDValue To = N->getOperand(0); | |||
11237 | ||||
11238 | // Now check for a compatible BFI to merge with. We can pass through BFIs that | |||
11239 | // aren't compatible, but not if they set the same bit in their destination as | |||
11240 | // we do (or that of any BFI we're going to combine with). | |||
11241 | SDValue V = To; | |||
11242 | APInt CombinedToMask = ToMask; | |||
11243 | while (V.getOpcode() == ARMISD::BFI) { | |||
11244 | APInt NewToMask, NewFromMask; | |||
11245 | SDValue NewFrom = ParseBFI(V.getNode(), NewToMask, NewFromMask); | |||
11246 | if (NewFrom != From) { | |||
11247 | // This BFI has a different base. Keep going. | |||
11248 | CombinedToMask |= NewToMask; | |||
11249 | V = V.getOperand(0); | |||
11250 | continue; | |||
11251 | } | |||
11252 | ||||
11253 | // Do the written bits conflict with any we've seen so far? | |||
11254 | if ((NewToMask & CombinedToMask).getBoolValue()) | |||
11255 | // Conflicting bits - bail out because going further is unsafe. | |||
11256 | return SDValue(); | |||
11257 | ||||
11258 | // Are the new bits contiguous when combined with the old bits? | |||
11259 | if (BitsProperlyConcatenate(ToMask, NewToMask) && | |||
11260 | BitsProperlyConcatenate(FromMask, NewFromMask)) | |||
11261 | return V; | |||
11262 | if (BitsProperlyConcatenate(NewToMask, ToMask) && | |||
11263 | BitsProperlyConcatenate(NewFromMask, FromMask)) | |||
11264 | return V; | |||
11265 | ||||
11266 | // We've seen a write to some bits, so track it. | |||
11267 | CombinedToMask |= NewToMask; | |||
11268 | // Keep going... | |||
11269 | V = V.getOperand(0); | |||
11270 | } | |||
11271 | ||||
11272 | return SDValue(); | |||
11273 | } | |||
11274 | ||||
11275 | static SDValue PerformBFICombine(SDNode *N, | |||
11276 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11277 | SDValue N1 = N->getOperand(1); | |||
11278 | if (N1.getOpcode() == ISD::AND) { | |||
11279 | // (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff | |||
11280 | // the bits being cleared by the AND are not demanded by the BFI. | |||
11281 | ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); | |||
11282 | if (!N11C) | |||
11283 | return SDValue(); | |||
11284 | unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); | |||
11285 | unsigned LSB = countTrailingZeros(~InvMask); | |||
11286 | unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB; | |||
11287 | assert(Width <((Width < static_cast<unsigned>(std::numeric_limits< unsigned>::digits) && "undefined behavior") ? static_cast <void> (0) : __assert_fail ("Width < static_cast<unsigned>(std::numeric_limits<unsigned>::digits) && \"undefined behavior\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11289, __PRETTY_FUNCTION__)) | |||
11288 | static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&((Width < static_cast<unsigned>(std::numeric_limits< unsigned>::digits) && "undefined behavior") ? static_cast <void> (0) : __assert_fail ("Width < static_cast<unsigned>(std::numeric_limits<unsigned>::digits) && \"undefined behavior\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11289, __PRETTY_FUNCTION__)) | |||
11289 | "undefined behavior")((Width < static_cast<unsigned>(std::numeric_limits< unsigned>::digits) && "undefined behavior") ? static_cast <void> (0) : __assert_fail ("Width < static_cast<unsigned>(std::numeric_limits<unsigned>::digits) && \"undefined behavior\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11289, __PRETTY_FUNCTION__)); | |||
11290 | unsigned Mask = (1u << Width) - 1; | |||
11291 | unsigned Mask2 = N11C->getZExtValue(); | |||
11292 | if ((Mask & (~Mask2)) == 0) | |||
11293 | return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0), | |||
11294 | N->getOperand(0), N1.getOperand(0), | |||
11295 | N->getOperand(2)); | |||
11296 | } else if (N->getOperand(0).getOpcode() == ARMISD::BFI) { | |||
11297 | // We have a BFI of a BFI. Walk up the BFI chain to see how long it goes. | |||
11298 | // Keep track of any consecutive bits set that all come from the same base | |||
11299 | // value. We can combine these together into a single BFI. | |||
11300 | SDValue CombineBFI = FindBFIToCombineWith(N); | |||
11301 | if (CombineBFI == SDValue()) | |||
11302 | return SDValue(); | |||
11303 | ||||
11304 | // We've found a BFI. | |||
11305 | APInt ToMask1, FromMask1; | |||
11306 | SDValue From1 = ParseBFI(N, ToMask1, FromMask1); | |||
11307 | ||||
11308 | APInt ToMask2, FromMask2; | |||
11309 | SDValue From2 = ParseBFI(CombineBFI.getNode(), ToMask2, FromMask2); | |||
11310 | assert(From1 == From2)((From1 == From2) ? static_cast<void> (0) : __assert_fail ("From1 == From2", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11310, __PRETTY_FUNCTION__)); | |||
11311 | (void)From2; | |||
11312 | ||||
11313 | // First, unlink CombineBFI. | |||
11314 | DCI.DAG.ReplaceAllUsesWith(CombineBFI, CombineBFI.getOperand(0)); | |||
11315 | // Then create a new BFI, combining the two together. | |||
11316 | APInt NewFromMask = FromMask1 | FromMask2; | |||
11317 | APInt NewToMask = ToMask1 | ToMask2; | |||
11318 | ||||
11319 | EVT VT = N->getValueType(0); | |||
11320 | SDLoc dl(N); | |||
11321 | ||||
11322 | if (NewFromMask[0] == 0) | |||
11323 | From1 = DCI.DAG.getNode( | |||
11324 | ISD::SRL, dl, VT, From1, | |||
11325 | DCI.DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT)); | |||
11326 | return DCI.DAG.getNode(ARMISD::BFI, dl, VT, N->getOperand(0), From1, | |||
11327 | DCI.DAG.getConstant(~NewToMask, dl, VT)); | |||
11328 | } | |||
11329 | return SDValue(); | |||
11330 | } | |||
11331 | ||||
11332 | /// PerformVMOVRRDCombine - Target-specific dag combine xforms for | |||
11333 | /// ARMISD::VMOVRRD. | |||
11334 | static SDValue PerformVMOVRRDCombine(SDNode *N, | |||
11335 | TargetLowering::DAGCombinerInfo &DCI, | |||
11336 | const ARMSubtarget *Subtarget) { | |||
11337 | // vmovrrd(vmovdrr x, y) -> x,y | |||
11338 | SDValue InDouble = N->getOperand(0); | |||
11339 | if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP()) | |||
11340 | return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); | |||
11341 | ||||
11342 | // vmovrrd(load f64) -> (load i32), (load i32) | |||
11343 | SDNode *InNode = InDouble.getNode(); | |||
11344 | if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && | |||
11345 | InNode->getValueType(0) == MVT::f64 && | |||
11346 | InNode->getOperand(1).getOpcode() == ISD::FrameIndex && | |||
11347 | !cast<LoadSDNode>(InNode)->isVolatile()) { | |||
11348 | // TODO: Should this be done for non-FrameIndex operands? | |||
11349 | LoadSDNode *LD = cast<LoadSDNode>(InNode); | |||
11350 | ||||
11351 | SelectionDAG &DAG = DCI.DAG; | |||
11352 | SDLoc DL(LD); | |||
11353 | SDValue BasePtr = LD->getBasePtr(); | |||
11354 | SDValue NewLD1 = | |||
11355 | DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, LD->getPointerInfo(), | |||
11356 | LD->getAlignment(), LD->getMemOperand()->getFlags()); | |||
11357 | ||||
11358 | SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, | |||
11359 | DAG.getConstant(4, DL, MVT::i32)); | |||
11360 | SDValue NewLD2 = DAG.getLoad( | |||
11361 | MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, LD->getPointerInfo(), | |||
11362 | std::min(4U, LD->getAlignment() / 2), LD->getMemOperand()->getFlags()); | |||
11363 | ||||
11364 | DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); | |||
11365 | if (DCI.DAG.getDataLayout().isBigEndian()) | |||
11366 | std::swap (NewLD1, NewLD2); | |||
11367 | SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); | |||
11368 | return Result; | |||
11369 | } | |||
11370 | ||||
11371 | return SDValue(); | |||
11372 | } | |||
11373 | ||||
11374 | /// PerformVMOVDRRCombine - Target-specific dag combine xforms for | |||
11375 | /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. | |||
11376 | static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { | |||
11377 | // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) | |||
11378 | SDValue Op0 = N->getOperand(0); | |||
11379 | SDValue Op1 = N->getOperand(1); | |||
11380 | if (Op0.getOpcode() == ISD::BITCAST) | |||
11381 | Op0 = Op0.getOperand(0); | |||
11382 | if (Op1.getOpcode() == ISD::BITCAST) | |||
11383 | Op1 = Op1.getOperand(0); | |||
11384 | if (Op0.getOpcode() == ARMISD::VMOVRRD && | |||
11385 | Op0.getNode() == Op1.getNode() && | |||
11386 | Op0.getResNo() == 0 && Op1.getResNo() == 1) | |||
11387 | return DAG.getNode(ISD::BITCAST, SDLoc(N), | |||
11388 | N->getValueType(0), Op0.getOperand(0)); | |||
11389 | return SDValue(); | |||
11390 | } | |||
11391 | ||||
11392 | /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node | |||
11393 | /// are normal, non-volatile loads. If so, it is profitable to bitcast an | |||
11394 | /// i64 vector to have f64 elements, since the value can then be loaded | |||
11395 | /// directly into a VFP register. | |||
11396 | static bool hasNormalLoadOperand(SDNode *N) { | |||
11397 | unsigned NumElts = N->getValueType(0).getVectorNumElements(); | |||
11398 | for (unsigned i = 0; i < NumElts; ++i) { | |||
11399 | SDNode *Elt = N->getOperand(i).getNode(); | |||
11400 | if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) | |||
11401 | return true; | |||
11402 | } | |||
11403 | return false; | |||
11404 | } | |||
11405 | ||||
11406 | /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for | |||
11407 | /// ISD::BUILD_VECTOR. | |||
11408 | static SDValue PerformBUILD_VECTORCombine(SDNode *N, | |||
11409 | TargetLowering::DAGCombinerInfo &DCI, | |||
11410 | const ARMSubtarget *Subtarget) { | |||
11411 | // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): | |||
11412 | // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value | |||
11413 | // into a pair of GPRs, which is fine when the value is used as a scalar, | |||
11414 | // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. | |||
11415 | SelectionDAG &DAG = DCI.DAG; | |||
11416 | if (N->getNumOperands() == 2) | |||
11417 | if (SDValue RV = PerformVMOVDRRCombine(N, DAG)) | |||
11418 | return RV; | |||
11419 | ||||
11420 | // Load i64 elements as f64 values so that type legalization does not split | |||
11421 | // them up into i32 values. | |||
11422 | EVT VT = N->getValueType(0); | |||
11423 | if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) | |||
11424 | return SDValue(); | |||
11425 | SDLoc dl(N); | |||
11426 | SmallVector<SDValue, 8> Ops; | |||
11427 | unsigned NumElts = VT.getVectorNumElements(); | |||
11428 | for (unsigned i = 0; i < NumElts; ++i) { | |||
11429 | SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); | |||
11430 | Ops.push_back(V); | |||
11431 | // Make the DAGCombiner fold the bitcast. | |||
11432 | DCI.AddToWorklist(V.getNode()); | |||
11433 | } | |||
11434 | EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); | |||
11435 | SDValue BV = DAG.getBuildVector(FloatVT, dl, Ops); | |||
11436 | return DAG.getNode(ISD::BITCAST, dl, VT, BV); | |||
11437 | } | |||
11438 | ||||
11439 | /// Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. | |||
11440 | static SDValue | |||
11441 | PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { | |||
11442 | // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR. | |||
11443 | // At that time, we may have inserted bitcasts from integer to float. | |||
11444 | // If these bitcasts have survived DAGCombine, change the lowering of this | |||
11445 | // BUILD_VECTOR in something more vector friendly, i.e., that does not | |||
11446 | // force to use floating point types. | |||
11447 | ||||
11448 | // Make sure we can change the type of the vector. | |||
11449 | // This is possible iff: | |||
11450 | // 1. The vector is only used in a bitcast to a integer type. I.e., | |||
11451 | // 1.1. Vector is used only once. | |||
11452 | // 1.2. Use is a bit convert to an integer type. | |||
11453 | // 2. The size of its operands are 32-bits (64-bits are not legal). | |||
11454 | EVT VT = N->getValueType(0); | |||
11455 | EVT EltVT = VT.getVectorElementType(); | |||
11456 | ||||
11457 | // Check 1.1. and 2. | |||
11458 | if (EltVT.getSizeInBits() != 32 || !N->hasOneUse()) | |||
11459 | return SDValue(); | |||
11460 | ||||
11461 | // By construction, the input type must be float. | |||
11462 | assert(EltVT == MVT::f32 && "Unexpected type!")((EltVT == MVT::f32 && "Unexpected type!") ? static_cast <void> (0) : __assert_fail ("EltVT == MVT::f32 && \"Unexpected type!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11462, __PRETTY_FUNCTION__)); | |||
11463 | ||||
11464 | // Check 1.2. | |||
11465 | SDNode *Use = *N->use_begin(); | |||
11466 | if (Use->getOpcode() != ISD::BITCAST || | |||
11467 | Use->getValueType(0).isFloatingPoint()) | |||
11468 | return SDValue(); | |||
11469 | ||||
11470 | // Check profitability. | |||
11471 | // Model is, if more than half of the relevant operands are bitcast from | |||
11472 | // i32, turn the build_vector into a sequence of insert_vector_elt. | |||
11473 | // Relevant operands are everything that is not statically | |||
11474 | // (i.e., at compile time) bitcasted. | |||
11475 | unsigned NumOfBitCastedElts = 0; | |||
11476 | unsigned NumElts = VT.getVectorNumElements(); | |||
11477 | unsigned NumOfRelevantElts = NumElts; | |||
11478 | for (unsigned Idx = 0; Idx < NumElts; ++Idx) { | |||
11479 | SDValue Elt = N->getOperand(Idx); | |||
11480 | if (Elt->getOpcode() == ISD::BITCAST) { | |||
11481 | // Assume only bit cast to i32 will go away. | |||
11482 | if (Elt->getOperand(0).getValueType() == MVT::i32) | |||
11483 | ++NumOfBitCastedElts; | |||
11484 | } else if (Elt.isUndef() || isa<ConstantSDNode>(Elt)) | |||
11485 | // Constants are statically casted, thus do not count them as | |||
11486 | // relevant operands. | |||
11487 | --NumOfRelevantElts; | |||
11488 | } | |||
11489 | ||||
11490 | // Check if more than half of the elements require a non-free bitcast. | |||
11491 | if (NumOfBitCastedElts <= NumOfRelevantElts / 2) | |||
11492 | return SDValue(); | |||
11493 | ||||
11494 | SelectionDAG &DAG = DCI.DAG; | |||
11495 | // Create the new vector type. | |||
11496 | EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); | |||
11497 | // Check if the type is legal. | |||
11498 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
11499 | if (!TLI.isTypeLegal(VecVT)) | |||
11500 | return SDValue(); | |||
11501 | ||||
11502 | // Combine: | |||
11503 | // ARMISD::BUILD_VECTOR E1, E2, ..., EN. | |||
11504 | // => BITCAST INSERT_VECTOR_ELT | |||
11505 | // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1), | |||
11506 | // (BITCAST EN), N. | |||
11507 | SDValue Vec = DAG.getUNDEF(VecVT); | |||
11508 | SDLoc dl(N); | |||
11509 | for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) { | |||
11510 | SDValue V = N->getOperand(Idx); | |||
11511 | if (V.isUndef()) | |||
11512 | continue; | |||
11513 | if (V.getOpcode() == ISD::BITCAST && | |||
11514 | V->getOperand(0).getValueType() == MVT::i32) | |||
11515 | // Fold obvious case. | |||
11516 | V = V.getOperand(0); | |||
11517 | else { | |||
11518 | V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); | |||
11519 | // Make the DAGCombiner fold the bitcasts. | |||
11520 | DCI.AddToWorklist(V.getNode()); | |||
11521 | } | |||
11522 | SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); | |||
11523 | Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); | |||
11524 | } | |||
11525 | Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec); | |||
11526 | // Make the DAGCombiner fold the bitcasts. | |||
11527 | DCI.AddToWorklist(Vec.getNode()); | |||
11528 | return Vec; | |||
11529 | } | |||
11530 | ||||
11531 | /// PerformInsertEltCombine - Target-specific dag combine xforms for | |||
11532 | /// ISD::INSERT_VECTOR_ELT. | |||
11533 | static SDValue PerformInsertEltCombine(SDNode *N, | |||
11534 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11535 | // Bitcast an i64 load inserted into a vector to f64. | |||
11536 | // Otherwise, the i64 value will be legalized to a pair of i32 values. | |||
11537 | EVT VT = N->getValueType(0); | |||
11538 | SDNode *Elt = N->getOperand(1).getNode(); | |||
11539 | if (VT.getVectorElementType() != MVT::i64 || | |||
11540 | !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) | |||
11541 | return SDValue(); | |||
11542 | ||||
11543 | SelectionDAG &DAG = DCI.DAG; | |||
11544 | SDLoc dl(N); | |||
11545 | EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, | |||
11546 | VT.getVectorNumElements()); | |||
11547 | SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); | |||
11548 | SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); | |||
11549 | // Make the DAGCombiner fold the bitcasts. | |||
11550 | DCI.AddToWorklist(Vec.getNode()); | |||
11551 | DCI.AddToWorklist(V.getNode()); | |||
11552 | SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, | |||
11553 | Vec, V, N->getOperand(2)); | |||
11554 | return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); | |||
11555 | } | |||
11556 | ||||
11557 | /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for | |||
11558 | /// ISD::VECTOR_SHUFFLE. | |||
11559 | static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { | |||
11560 | // The LLVM shufflevector instruction does not require the shuffle mask | |||
11561 | // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does | |||
11562 | // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the | |||
11563 | // operands do not match the mask length, they are extended by concatenating | |||
11564 | // them with undef vectors. That is probably the right thing for other | |||
11565 | // targets, but for NEON it is better to concatenate two double-register | |||
11566 | // size vector operands into a single quad-register size vector. Do that | |||
11567 | // transformation here: | |||
11568 | // shuffle(concat(v1, undef), concat(v2, undef)) -> | |||
11569 | // shuffle(concat(v1, v2), undef) | |||
11570 | SDValue Op0 = N->getOperand(0); | |||
11571 | SDValue Op1 = N->getOperand(1); | |||
11572 | if (Op0.getOpcode() != ISD::CONCAT_VECTORS || | |||
11573 | Op1.getOpcode() != ISD::CONCAT_VECTORS || | |||
11574 | Op0.getNumOperands() != 2 || | |||
11575 | Op1.getNumOperands() != 2) | |||
11576 | return SDValue(); | |||
11577 | SDValue Concat0Op1 = Op0.getOperand(1); | |||
11578 | SDValue Concat1Op1 = Op1.getOperand(1); | |||
11579 | if (!Concat0Op1.isUndef() || !Concat1Op1.isUndef()) | |||
11580 | return SDValue(); | |||
11581 | // Skip the transformation if any of the types are illegal. | |||
11582 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
11583 | EVT VT = N->getValueType(0); | |||
11584 | if (!TLI.isTypeLegal(VT) || | |||
11585 | !TLI.isTypeLegal(Concat0Op1.getValueType()) || | |||
11586 | !TLI.isTypeLegal(Concat1Op1.getValueType())) | |||
11587 | return SDValue(); | |||
11588 | ||||
11589 | SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, | |||
11590 | Op0.getOperand(0), Op1.getOperand(0)); | |||
11591 | // Translate the shuffle mask. | |||
11592 | SmallVector<int, 16> NewMask; | |||
11593 | unsigned NumElts = VT.getVectorNumElements(); | |||
11594 | unsigned HalfElts = NumElts/2; | |||
11595 | ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); | |||
11596 | for (unsigned n = 0; n < NumElts; ++n) { | |||
11597 | int MaskElt = SVN->getMaskElt(n); | |||
11598 | int NewElt = -1; | |||
11599 | if (MaskElt < (int)HalfElts) | |||
11600 | NewElt = MaskElt; | |||
11601 | else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) | |||
11602 | NewElt = HalfElts + MaskElt - NumElts; | |||
11603 | NewMask.push_back(NewElt); | |||
11604 | } | |||
11605 | return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat, | |||
11606 | DAG.getUNDEF(VT), NewMask); | |||
11607 | } | |||
11608 | ||||
11609 | /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, | |||
11610 | /// NEON load/store intrinsics, and generic vector load/stores, to merge | |||
11611 | /// base address updates. | |||
11612 | /// For generic load/stores, the memory type is assumed to be a vector. | |||
11613 | /// The caller is assumed to have checked legality. | |||
11614 | static SDValue CombineBaseUpdate(SDNode *N, | |||
11615 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11616 | SelectionDAG &DAG = DCI.DAG; | |||
11617 | const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || | |||
11618 | N->getOpcode() == ISD::INTRINSIC_W_CHAIN); | |||
11619 | const bool isStore = N->getOpcode() == ISD::STORE; | |||
11620 | const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1); | |||
11621 | SDValue Addr = N->getOperand(AddrOpIdx); | |||
11622 | MemSDNode *MemN = cast<MemSDNode>(N); | |||
11623 | SDLoc dl(N); | |||
11624 | ||||
11625 | // Search for a use of the address operand that is an increment. | |||
11626 | for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), | |||
11627 | UE = Addr.getNode()->use_end(); UI != UE; ++UI) { | |||
11628 | SDNode *User = *UI; | |||
11629 | if (User->getOpcode() != ISD::ADD || | |||
11630 | UI.getUse().getResNo() != Addr.getResNo()) | |||
11631 | continue; | |||
11632 | ||||
11633 | // Check that the add is independent of the load/store. Otherwise, folding | |||
11634 | // it would create a cycle. We can avoid searching through Addr as it's a | |||
11635 | // predecessor to both. | |||
11636 | SmallPtrSet<const SDNode *, 32> Visited; | |||
11637 | SmallVector<const SDNode *, 16> Worklist; | |||
11638 | Visited.insert(Addr.getNode()); | |||
11639 | Worklist.push_back(N); | |||
11640 | Worklist.push_back(User); | |||
11641 | if (SDNode::hasPredecessorHelper(N, Visited, Worklist) || | |||
11642 | SDNode::hasPredecessorHelper(User, Visited, Worklist)) | |||
11643 | continue; | |||
11644 | ||||
11645 | // Find the new opcode for the updating load/store. | |||
11646 | bool isLoadOp = true; | |||
11647 | bool isLaneOp = false; | |||
11648 | unsigned NewOpc = 0; | |||
11649 | unsigned NumVecs = 0; | |||
11650 | if (isIntrinsic) { | |||
11651 | unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); | |||
11652 | switch (IntNo) { | |||
11653 | default: llvm_unreachable("unexpected intrinsic for Neon base update")::llvm::llvm_unreachable_internal("unexpected intrinsic for Neon base update" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11653); | |||
11654 | case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; | |||
11655 | NumVecs = 1; break; | |||
11656 | case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; | |||
11657 | NumVecs = 2; break; | |||
11658 | case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; | |||
11659 | NumVecs = 3; break; | |||
11660 | case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; | |||
11661 | NumVecs = 4; break; | |||
11662 | case Intrinsic::arm_neon_vld2dup: | |||
11663 | case Intrinsic::arm_neon_vld3dup: | |||
11664 | case Intrinsic::arm_neon_vld4dup: | |||
11665 | // TODO: Support updating VLDxDUP nodes. For now, we just skip | |||
11666 | // combining base updates for such intrinsics. | |||
11667 | continue; | |||
11668 | case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; | |||
11669 | NumVecs = 2; isLaneOp = true; break; | |||
11670 | case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; | |||
11671 | NumVecs = 3; isLaneOp = true; break; | |||
11672 | case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; | |||
11673 | NumVecs = 4; isLaneOp = true; break; | |||
11674 | case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; | |||
11675 | NumVecs = 1; isLoadOp = false; break; | |||
11676 | case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; | |||
11677 | NumVecs = 2; isLoadOp = false; break; | |||
11678 | case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; | |||
11679 | NumVecs = 3; isLoadOp = false; break; | |||
11680 | case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; | |||
11681 | NumVecs = 4; isLoadOp = false; break; | |||
11682 | case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; | |||
11683 | NumVecs = 2; isLoadOp = false; isLaneOp = true; break; | |||
11684 | case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; | |||
11685 | NumVecs = 3; isLoadOp = false; isLaneOp = true; break; | |||
11686 | case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; | |||
11687 | NumVecs = 4; isLoadOp = false; isLaneOp = true; break; | |||
11688 | } | |||
11689 | } else { | |||
11690 | isLaneOp = true; | |||
11691 | switch (N->getOpcode()) { | |||
11692 | default: llvm_unreachable("unexpected opcode for Neon base update")::llvm::llvm_unreachable_internal("unexpected opcode for Neon base update" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11692); | |||
11693 | case ARMISD::VLD1DUP: NewOpc = ARMISD::VLD1DUP_UPD; NumVecs = 1; break; | |||
11694 | case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; | |||
11695 | case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; | |||
11696 | case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; | |||
11697 | case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD; | |||
11698 | NumVecs = 1; isLaneOp = false; break; | |||
11699 | case ISD::STORE: NewOpc = ARMISD::VST1_UPD; | |||
11700 | NumVecs = 1; isLaneOp = false; isLoadOp = false; break; | |||
11701 | } | |||
11702 | } | |||
11703 | ||||
11704 | // Find the size of memory referenced by the load/store. | |||
11705 | EVT VecTy; | |||
11706 | if (isLoadOp) { | |||
11707 | VecTy = N->getValueType(0); | |||
11708 | } else if (isIntrinsic) { | |||
11709 | VecTy = N->getOperand(AddrOpIdx+1).getValueType(); | |||
11710 | } else { | |||
11711 | assert(isStore && "Node has to be a load, a store, or an intrinsic!")((isStore && "Node has to be a load, a store, or an intrinsic!" ) ? static_cast<void> (0) : __assert_fail ("isStore && \"Node has to be a load, a store, or an intrinsic!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11711, __PRETTY_FUNCTION__)); | |||
11712 | VecTy = N->getOperand(1).getValueType(); | |||
11713 | } | |||
11714 | ||||
11715 | unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; | |||
11716 | if (isLaneOp) | |||
11717 | NumBytes /= VecTy.getVectorNumElements(); | |||
11718 | ||||
11719 | // If the increment is a constant, it must match the memory ref size. | |||
11720 | SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); | |||
11721 | ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode()); | |||
11722 | if (NumBytes >= 3 * 16 && (!CInc || CInc->getZExtValue() != NumBytes)) { | |||
11723 | // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two | |||
11724 | // separate instructions that make it harder to use a non-constant update. | |||
11725 | continue; | |||
11726 | } | |||
11727 | ||||
11728 | // OK, we found an ADD we can fold into the base update. | |||
11729 | // Now, create a _UPD node, taking care of not breaking alignment. | |||
11730 | ||||
11731 | EVT AlignedVecTy = VecTy; | |||
11732 | unsigned Alignment = MemN->getAlignment(); | |||
11733 | ||||
11734 | // If this is a less-than-standard-aligned load/store, change the type to | |||
11735 | // match the standard alignment. | |||
11736 | // The alignment is overlooked when selecting _UPD variants; and it's | |||
11737 | // easier to introduce bitcasts here than fix that. | |||
11738 | // There are 3 ways to get to this base-update combine: | |||
11739 | // - intrinsics: they are assumed to be properly aligned (to the standard | |||
11740 | // alignment of the memory type), so we don't need to do anything. | |||
11741 | // - ARMISD::VLDx nodes: they are only generated from the aforementioned | |||
11742 | // intrinsics, so, likewise, there's nothing to do. | |||
11743 | // - generic load/store instructions: the alignment is specified as an | |||
11744 | // explicit operand, rather than implicitly as the standard alignment | |||
11745 | // of the memory type (like the intrisics). We need to change the | |||
11746 | // memory type to match the explicit alignment. That way, we don't | |||
11747 | // generate non-standard-aligned ARMISD::VLDx nodes. | |||
11748 | if (isa<LSBaseSDNode>(N)) { | |||
11749 | if (Alignment == 0) | |||
11750 | Alignment = 1; | |||
11751 | if (Alignment < VecTy.getScalarSizeInBits() / 8) { | |||
11752 | MVT EltTy = MVT::getIntegerVT(Alignment * 8); | |||
11753 | assert(NumVecs == 1 && "Unexpected multi-element generic load/store.")((NumVecs == 1 && "Unexpected multi-element generic load/store." ) ? static_cast<void> (0) : __assert_fail ("NumVecs == 1 && \"Unexpected multi-element generic load/store.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11753, __PRETTY_FUNCTION__)); | |||
11754 | assert(!isLaneOp && "Unexpected generic load/store lane.")((!isLaneOp && "Unexpected generic load/store lane.") ? static_cast<void> (0) : __assert_fail ("!isLaneOp && \"Unexpected generic load/store lane.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 11754, __PRETTY_FUNCTION__)); | |||
11755 | unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8); | |||
11756 | AlignedVecTy = MVT::getVectorVT(EltTy, NumElts); | |||
11757 | } | |||
11758 | // Don't set an explicit alignment on regular load/stores that we want | |||
11759 | // to transform to VLD/VST 1_UPD nodes. | |||
11760 | // This matches the behavior of regular load/stores, which only get an | |||
11761 | // explicit alignment if the MMO alignment is larger than the standard | |||
11762 | // alignment of the memory type. | |||
11763 | // Intrinsics, however, always get an explicit alignment, set to the | |||
11764 | // alignment of the MMO. | |||
11765 | Alignment = 1; | |||
11766 | } | |||
11767 | ||||
11768 | // Create the new updating load/store node. | |||
11769 | // First, create an SDVTList for the new updating node's results. | |||
11770 | EVT Tys[6]; | |||
11771 | unsigned NumResultVecs = (isLoadOp ? NumVecs : 0); | |||
11772 | unsigned n; | |||
11773 | for (n = 0; n < NumResultVecs; ++n) | |||
11774 | Tys[n] = AlignedVecTy; | |||
11775 | Tys[n++] = MVT::i32; | |||
11776 | Tys[n] = MVT::Other; | |||
11777 | SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2)); | |||
11778 | ||||
11779 | // Then, gather the new node's operands. | |||
11780 | SmallVector<SDValue, 8> Ops; | |||
11781 | Ops.push_back(N->getOperand(0)); // incoming chain | |||
11782 | Ops.push_back(N->getOperand(AddrOpIdx)); | |||
11783 | Ops.push_back(Inc); | |||
11784 | ||||
11785 | if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) { | |||
11786 | // Try to match the intrinsic's signature | |||
11787 | Ops.push_back(StN->getValue()); | |||
11788 | } else { | |||
11789 | // Loads (and of course intrinsics) match the intrinsics' signature, | |||
11790 | // so just add all but the alignment operand. | |||
11791 | for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i) | |||
11792 | Ops.push_back(N->getOperand(i)); | |||
11793 | } | |||
11794 | ||||
11795 | // For all node types, the alignment operand is always the last one. | |||
11796 | Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32)); | |||
11797 | ||||
11798 | // If this is a non-standard-aligned STORE, the penultimate operand is the | |||
11799 | // stored value. Bitcast it to the aligned type. | |||
11800 | if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) { | |||
11801 | SDValue &StVal = Ops[Ops.size()-2]; | |||
11802 | StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); | |||
11803 | } | |||
11804 | ||||
11805 | EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; | |||
11806 | SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, | |||
11807 | MemN->getMemOperand()); | |||
11808 | ||||
11809 | // Update the uses. | |||
11810 | SmallVector<SDValue, 5> NewResults; | |||
11811 | for (unsigned i = 0; i < NumResultVecs; ++i) | |||
11812 | NewResults.push_back(SDValue(UpdN.getNode(), i)); | |||
11813 | ||||
11814 | // If this is an non-standard-aligned LOAD, the first result is the loaded | |||
11815 | // value. Bitcast it to the expected result type. | |||
11816 | if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) { | |||
11817 | SDValue &LdVal = NewResults[0]; | |||
11818 | LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal); | |||
11819 | } | |||
11820 | ||||
11821 | NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain | |||
11822 | DCI.CombineTo(N, NewResults); | |||
11823 | DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); | |||
11824 | ||||
11825 | break; | |||
11826 | } | |||
11827 | return SDValue(); | |||
11828 | } | |||
11829 | ||||
11830 | static SDValue PerformVLDCombine(SDNode *N, | |||
11831 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11832 | if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) | |||
11833 | return SDValue(); | |||
11834 | ||||
11835 | return CombineBaseUpdate(N, DCI); | |||
11836 | } | |||
11837 | ||||
11838 | /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a | |||
11839 | /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic | |||
11840 | /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and | |||
11841 | /// return true. | |||
11842 | static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { | |||
11843 | SelectionDAG &DAG = DCI.DAG; | |||
11844 | EVT VT = N->getValueType(0); | |||
11845 | // vldN-dup instructions only support 64-bit vectors for N > 1. | |||
11846 | if (!VT.is64BitVector()) | |||
11847 | return false; | |||
11848 | ||||
11849 | // Check if the VDUPLANE operand is a vldN-dup intrinsic. | |||
11850 | SDNode *VLD = N->getOperand(0).getNode(); | |||
11851 | if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) | |||
11852 | return false; | |||
11853 | unsigned NumVecs = 0; | |||
11854 | unsigned NewOpc = 0; | |||
11855 | unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); | |||
11856 | if (IntNo == Intrinsic::arm_neon_vld2lane) { | |||
11857 | NumVecs = 2; | |||
11858 | NewOpc = ARMISD::VLD2DUP; | |||
11859 | } else if (IntNo == Intrinsic::arm_neon_vld3lane) { | |||
11860 | NumVecs = 3; | |||
11861 | NewOpc = ARMISD::VLD3DUP; | |||
11862 | } else if (IntNo == Intrinsic::arm_neon_vld4lane) { | |||
11863 | NumVecs = 4; | |||
11864 | NewOpc = ARMISD::VLD4DUP; | |||
11865 | } else { | |||
11866 | return false; | |||
11867 | } | |||
11868 | ||||
11869 | // First check that all the vldN-lane uses are VDUPLANEs and that the lane | |||
11870 | // numbers match the load. | |||
11871 | unsigned VLDLaneNo = | |||
11872 | cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); | |||
11873 | for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); | |||
11874 | UI != UE; ++UI) { | |||
11875 | // Ignore uses of the chain result. | |||
11876 | if (UI.getUse().getResNo() == NumVecs) | |||
11877 | continue; | |||
11878 | SDNode *User = *UI; | |||
11879 | if (User->getOpcode() != ARMISD::VDUPLANE || | |||
11880 | VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) | |||
11881 | return false; | |||
11882 | } | |||
11883 | ||||
11884 | // Create the vldN-dup node. | |||
11885 | EVT Tys[5]; | |||
11886 | unsigned n; | |||
11887 | for (n = 0; n < NumVecs; ++n) | |||
11888 | Tys[n] = VT; | |||
11889 | Tys[n] = MVT::Other; | |||
11890 | SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1)); | |||
11891 | SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; | |||
11892 | MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); | |||
11893 | SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, | |||
11894 | Ops, VLDMemInt->getMemoryVT(), | |||
11895 | VLDMemInt->getMemOperand()); | |||
11896 | ||||
11897 | // Update the uses. | |||
11898 | for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); | |||
11899 | UI != UE; ++UI) { | |||
11900 | unsigned ResNo = UI.getUse().getResNo(); | |||
11901 | // Ignore uses of the chain result. | |||
11902 | if (ResNo == NumVecs) | |||
11903 | continue; | |||
11904 | SDNode *User = *UI; | |||
11905 | DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); | |||
11906 | } | |||
11907 | ||||
11908 | // Now the vldN-lane intrinsic is dead except for its chain result. | |||
11909 | // Update uses of the chain. | |||
11910 | std::vector<SDValue> VLDDupResults; | |||
11911 | for (unsigned n = 0; n < NumVecs; ++n) | |||
11912 | VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); | |||
11913 | VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); | |||
11914 | DCI.CombineTo(VLD, VLDDupResults); | |||
11915 | ||||
11916 | return true; | |||
11917 | } | |||
11918 | ||||
11919 | /// PerformVDUPLANECombine - Target-specific dag combine xforms for | |||
11920 | /// ARMISD::VDUPLANE. | |||
11921 | static SDValue PerformVDUPLANECombine(SDNode *N, | |||
11922 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11923 | SDValue Op = N->getOperand(0); | |||
11924 | ||||
11925 | // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses | |||
11926 | // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. | |||
11927 | if (CombineVLDDUP(N, DCI)) | |||
11928 | return SDValue(N, 0); | |||
11929 | ||||
11930 | // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is | |||
11931 | // redundant. Ignore bit_converts for now; element sizes are checked below. | |||
11932 | while (Op.getOpcode() == ISD::BITCAST) | |||
11933 | Op = Op.getOperand(0); | |||
11934 | if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) | |||
11935 | return SDValue(); | |||
11936 | ||||
11937 | // Make sure the VMOV element size is not bigger than the VDUPLANE elements. | |||
11938 | unsigned EltSize = Op.getScalarValueSizeInBits(); | |||
11939 | // The canonical VMOV for a zero vector uses a 32-bit element size. | |||
11940 | unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); | |||
11941 | unsigned EltBits; | |||
11942 | if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) | |||
11943 | EltSize = 8; | |||
11944 | EVT VT = N->getValueType(0); | |||
11945 | if (EltSize > VT.getScalarSizeInBits()) | |||
11946 | return SDValue(); | |||
11947 | ||||
11948 | return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); | |||
11949 | } | |||
11950 | ||||
11951 | /// PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. | |||
11952 | static SDValue PerformVDUPCombine(SDNode *N, | |||
11953 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11954 | SelectionDAG &DAG = DCI.DAG; | |||
11955 | SDValue Op = N->getOperand(0); | |||
11956 | ||||
11957 | // Match VDUP(LOAD) -> VLD1DUP. | |||
11958 | // We match this pattern here rather than waiting for isel because the | |||
11959 | // transform is only legal for unindexed loads. | |||
11960 | LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode()); | |||
11961 | if (LD && Op.hasOneUse() && LD->isUnindexed() && | |||
11962 | LD->getMemoryVT() == N->getValueType(0).getVectorElementType()) { | |||
11963 | SDValue Ops[] = { LD->getOperand(0), LD->getOperand(1), | |||
11964 | DAG.getConstant(LD->getAlignment(), SDLoc(N), MVT::i32) }; | |||
11965 | SDVTList SDTys = DAG.getVTList(N->getValueType(0), MVT::Other); | |||
11966 | SDValue VLDDup = DAG.getMemIntrinsicNode(ARMISD::VLD1DUP, SDLoc(N), SDTys, | |||
11967 | Ops, LD->getMemoryVT(), | |||
11968 | LD->getMemOperand()); | |||
11969 | DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), VLDDup.getValue(1)); | |||
11970 | return VLDDup; | |||
11971 | } | |||
11972 | ||||
11973 | return SDValue(); | |||
11974 | } | |||
11975 | ||||
11976 | static SDValue PerformLOADCombine(SDNode *N, | |||
11977 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11978 | EVT VT = N->getValueType(0); | |||
11979 | ||||
11980 | // If this is a legal vector load, try to combine it into a VLD1_UPD. | |||
11981 | if (ISD::isNormalLoad(N) && VT.isVector() && | |||
11982 | DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) | |||
11983 | return CombineBaseUpdate(N, DCI); | |||
11984 | ||||
11985 | return SDValue(); | |||
11986 | } | |||
11987 | ||||
11988 | /// PerformSTORECombine - Target-specific dag combine xforms for | |||
11989 | /// ISD::STORE. | |||
11990 | static SDValue PerformSTORECombine(SDNode *N, | |||
11991 | TargetLowering::DAGCombinerInfo &DCI) { | |||
11992 | StoreSDNode *St = cast<StoreSDNode>(N); | |||
11993 | if (St->isVolatile()) | |||
11994 | return SDValue(); | |||
11995 | ||||
11996 | // Optimize trunc store (of multiple scalars) to shuffle and store. First, | |||
11997 | // pack all of the elements in one place. Next, store to memory in fewer | |||
11998 | // chunks. | |||
11999 | SDValue StVal = St->getValue(); | |||
12000 | EVT VT = StVal.getValueType(); | |||
12001 | if (St->isTruncatingStore() && VT.isVector()) { | |||
12002 | SelectionDAG &DAG = DCI.DAG; | |||
12003 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
12004 | EVT StVT = St->getMemoryVT(); | |||
12005 | unsigned NumElems = VT.getVectorNumElements(); | |||
12006 | assert(StVT != VT && "Cannot truncate to the same type")((StVT != VT && "Cannot truncate to the same type") ? static_cast<void> (0) : __assert_fail ("StVT != VT && \"Cannot truncate to the same type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12006, __PRETTY_FUNCTION__)); | |||
12007 | unsigned FromEltSz = VT.getScalarSizeInBits(); | |||
12008 | unsigned ToEltSz = StVT.getScalarSizeInBits(); | |||
12009 | ||||
12010 | // From, To sizes and ElemCount must be pow of two | |||
12011 | if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue(); | |||
12012 | ||||
12013 | // We are going to use the original vector elt for storing. | |||
12014 | // Accumulated smaller vector elements must be a multiple of the store size. | |||
12015 | if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue(); | |||
12016 | ||||
12017 | unsigned SizeRatio = FromEltSz / ToEltSz; | |||
12018 | assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits())((SizeRatio * NumElems * ToEltSz == VT.getSizeInBits()) ? static_cast <void> (0) : __assert_fail ("SizeRatio * NumElems * ToEltSz == VT.getSizeInBits()" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12018, __PRETTY_FUNCTION__)); | |||
12019 | ||||
12020 | // Create a type on which we perform the shuffle. | |||
12021 | EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(), | |||
12022 | NumElems*SizeRatio); | |||
12023 | assert(WideVecVT.getSizeInBits() == VT.getSizeInBits())((WideVecVT.getSizeInBits() == VT.getSizeInBits()) ? static_cast <void> (0) : __assert_fail ("WideVecVT.getSizeInBits() == VT.getSizeInBits()" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12023, __PRETTY_FUNCTION__)); | |||
12024 | ||||
12025 | SDLoc DL(St); | |||
12026 | SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); | |||
12027 | SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); | |||
12028 | for (unsigned i = 0; i < NumElems; ++i) | |||
12029 | ShuffleVec[i] = DAG.getDataLayout().isBigEndian() | |||
12030 | ? (i + 1) * SizeRatio - 1 | |||
12031 | : i * SizeRatio; | |||
12032 | ||||
12033 | // Can't shuffle using an illegal type. | |||
12034 | if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); | |||
12035 | ||||
12036 | SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec, | |||
12037 | DAG.getUNDEF(WideVec.getValueType()), | |||
12038 | ShuffleVec); | |||
12039 | // At this point all of the data is stored at the bottom of the | |||
12040 | // register. We now need to save it to mem. | |||
12041 | ||||
12042 | // Find the largest store unit | |||
12043 | MVT StoreType = MVT::i8; | |||
12044 | for (MVT Tp : MVT::integer_valuetypes()) { | |||
12045 | if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz) | |||
12046 | StoreType = Tp; | |||
12047 | } | |||
12048 | // Didn't find a legal store type. | |||
12049 | if (!TLI.isTypeLegal(StoreType)) | |||
12050 | return SDValue(); | |||
12051 | ||||
12052 | // Bitcast the original vector into a vector of store-size units | |||
12053 | EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), | |||
12054 | StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); | |||
12055 | assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits())((StoreVecVT.getSizeInBits() == VT.getSizeInBits()) ? static_cast <void> (0) : __assert_fail ("StoreVecVT.getSizeInBits() == VT.getSizeInBits()" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12055, __PRETTY_FUNCTION__)); | |||
12056 | SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); | |||
12057 | SmallVector<SDValue, 8> Chains; | |||
12058 | SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL, | |||
12059 | TLI.getPointerTy(DAG.getDataLayout())); | |||
12060 | SDValue BasePtr = St->getBasePtr(); | |||
12061 | ||||
12062 | // Perform one or more big stores into memory. | |||
12063 | unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits(); | |||
12064 | for (unsigned I = 0; I < E; I++) { | |||
12065 | SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, | |||
12066 | StoreType, ShuffWide, | |||
12067 | DAG.getIntPtrConstant(I, DL)); | |||
12068 | SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr, | |||
12069 | St->getPointerInfo(), St->getAlignment(), | |||
12070 | St->getMemOperand()->getFlags()); | |||
12071 | BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr, | |||
12072 | Increment); | |||
12073 | Chains.push_back(Ch); | |||
12074 | } | |||
12075 | return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); | |||
12076 | } | |||
12077 | ||||
12078 | if (!ISD::isNormalStore(St)) | |||
12079 | return SDValue(); | |||
12080 | ||||
12081 | // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and | |||
12082 | // ARM stores of arguments in the same cache line. | |||
12083 | if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && | |||
12084 | StVal.getNode()->hasOneUse()) { | |||
12085 | SelectionDAG &DAG = DCI.DAG; | |||
12086 | bool isBigEndian = DAG.getDataLayout().isBigEndian(); | |||
12087 | SDLoc DL(St); | |||
12088 | SDValue BasePtr = St->getBasePtr(); | |||
12089 | SDValue NewST1 = DAG.getStore( | |||
12090 | St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0), | |||
12091 | BasePtr, St->getPointerInfo(), St->getAlignment(), | |||
12092 | St->getMemOperand()->getFlags()); | |||
12093 | ||||
12094 | SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, | |||
12095 | DAG.getConstant(4, DL, MVT::i32)); | |||
12096 | return DAG.getStore(NewST1.getValue(0), DL, | |||
12097 | StVal.getNode()->getOperand(isBigEndian ? 0 : 1), | |||
12098 | OffsetPtr, St->getPointerInfo(), | |||
12099 | std::min(4U, St->getAlignment() / 2), | |||
12100 | St->getMemOperand()->getFlags()); | |||
12101 | } | |||
12102 | ||||
12103 | if (StVal.getValueType() == MVT::i64 && | |||
12104 | StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { | |||
12105 | ||||
12106 | // Bitcast an i64 store extracted from a vector to f64. | |||
12107 | // Otherwise, the i64 value will be legalized to a pair of i32 values. | |||
12108 | SelectionDAG &DAG = DCI.DAG; | |||
12109 | SDLoc dl(StVal); | |||
12110 | SDValue IntVec = StVal.getOperand(0); | |||
12111 | EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, | |||
12112 | IntVec.getValueType().getVectorNumElements()); | |||
12113 | SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); | |||
12114 | SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, | |||
12115 | Vec, StVal.getOperand(1)); | |||
12116 | dl = SDLoc(N); | |||
12117 | SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); | |||
12118 | // Make the DAGCombiner fold the bitcasts. | |||
12119 | DCI.AddToWorklist(Vec.getNode()); | |||
12120 | DCI.AddToWorklist(ExtElt.getNode()); | |||
12121 | DCI.AddToWorklist(V.getNode()); | |||
12122 | return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), | |||
12123 | St->getPointerInfo(), St->getAlignment(), | |||
12124 | St->getMemOperand()->getFlags(), St->getAAInfo()); | |||
12125 | } | |||
12126 | ||||
12127 | // If this is a legal vector store, try to combine it into a VST1_UPD. | |||
12128 | if (ISD::isNormalStore(N) && VT.isVector() && | |||
12129 | DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) | |||
12130 | return CombineBaseUpdate(N, DCI); | |||
12131 | ||||
12132 | return SDValue(); | |||
12133 | } | |||
12134 | ||||
12135 | /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) | |||
12136 | /// can replace combinations of VMUL and VCVT (floating-point to integer) | |||
12137 | /// when the VMUL has a constant operand that is a power of 2. | |||
12138 | /// | |||
12139 | /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): | |||
12140 | /// vmul.f32 d16, d17, d16 | |||
12141 | /// vcvt.s32.f32 d16, d16 | |||
12142 | /// becomes: | |||
12143 | /// vcvt.s32.f32 d16, d16, #3 | |||
12144 | static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, | |||
12145 | const ARMSubtarget *Subtarget) { | |||
12146 | if (!Subtarget->hasNEON()) | |||
12147 | return SDValue(); | |||
12148 | ||||
12149 | SDValue Op = N->getOperand(0); | |||
12150 | if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || | |||
12151 | Op.getOpcode() != ISD::FMUL) | |||
12152 | return SDValue(); | |||
12153 | ||||
12154 | SDValue ConstVec = Op->getOperand(1); | |||
12155 | if (!isa<BuildVectorSDNode>(ConstVec)) | |||
12156 | return SDValue(); | |||
12157 | ||||
12158 | MVT FloatTy = Op.getSimpleValueType().getVectorElementType(); | |||
12159 | uint32_t FloatBits = FloatTy.getSizeInBits(); | |||
12160 | MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); | |||
12161 | uint32_t IntBits = IntTy.getSizeInBits(); | |||
12162 | unsigned NumLanes = Op.getValueType().getVectorNumElements(); | |||
12163 | if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { | |||
12164 | // These instructions only exist converting from f32 to i32. We can handle | |||
12165 | // smaller integers by generating an extra truncate, but larger ones would | |||
12166 | // be lossy. We also can't handle anything other than 2 or 4 lanes, since | |||
12167 | // these intructions only support v2i32/v4i32 types. | |||
12168 | return SDValue(); | |||
12169 | } | |||
12170 | ||||
12171 | BitVector UndefElements; | |||
12172 | BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec); | |||
12173 | int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33); | |||
12174 | if (C == -1 || C == 0 || C > 32) | |||
12175 | return SDValue(); | |||
12176 | ||||
12177 | SDLoc dl(N); | |||
12178 | bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; | |||
12179 | unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : | |||
12180 | Intrinsic::arm_neon_vcvtfp2fxu; | |||
12181 | SDValue FixConv = DAG.getNode( | |||
12182 | ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, | |||
12183 | DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0), | |||
12184 | DAG.getConstant(C, dl, MVT::i32)); | |||
12185 | ||||
12186 | if (IntBits < FloatBits) | |||
12187 | FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv); | |||
12188 | ||||
12189 | return FixConv; | |||
12190 | } | |||
12191 | ||||
12192 | /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) | |||
12193 | /// can replace combinations of VCVT (integer to floating-point) and VDIV | |||
12194 | /// when the VDIV has a constant operand that is a power of 2. | |||
12195 | /// | |||
12196 | /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): | |||
12197 | /// vcvt.f32.s32 d16, d16 | |||
12198 | /// vdiv.f32 d16, d17, d16 | |||
12199 | /// becomes: | |||
12200 | /// vcvt.f32.s32 d16, d16, #3 | |||
12201 | static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, | |||
12202 | const ARMSubtarget *Subtarget) { | |||
12203 | if (!Subtarget->hasNEON()) | |||
12204 | return SDValue(); | |||
12205 | ||||
12206 | SDValue Op = N->getOperand(0); | |||
12207 | unsigned OpOpcode = Op.getNode()->getOpcode(); | |||
12208 | if (!N->getValueType(0).isVector() || !N->getValueType(0).isSimple() || | |||
12209 | (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) | |||
12210 | return SDValue(); | |||
12211 | ||||
12212 | SDValue ConstVec = N->getOperand(1); | |||
12213 | if (!isa<BuildVectorSDNode>(ConstVec)) | |||
12214 | return SDValue(); | |||
12215 | ||||
12216 | MVT FloatTy = N->getSimpleValueType(0).getVectorElementType(); | |||
12217 | uint32_t FloatBits = FloatTy.getSizeInBits(); | |||
12218 | MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); | |||
12219 | uint32_t IntBits = IntTy.getSizeInBits(); | |||
12220 | unsigned NumLanes = Op.getValueType().getVectorNumElements(); | |||
12221 | if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { | |||
12222 | // These instructions only exist converting from i32 to f32. We can handle | |||
12223 | // smaller integers by generating an extra extend, but larger ones would | |||
12224 | // be lossy. We also can't handle anything other than 2 or 4 lanes, since | |||
12225 | // these intructions only support v2i32/v4i32 types. | |||
12226 | return SDValue(); | |||
12227 | } | |||
12228 | ||||
12229 | BitVector UndefElements; | |||
12230 | BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec); | |||
12231 | int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33); | |||
12232 | if (C == -1 || C == 0 || C > 32) | |||
12233 | return SDValue(); | |||
12234 | ||||
12235 | SDLoc dl(N); | |||
12236 | bool isSigned = OpOpcode == ISD::SINT_TO_FP; | |||
12237 | SDValue ConvInput = Op.getOperand(0); | |||
12238 | if (IntBits < FloatBits) | |||
12239 | ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, | |||
12240 | dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, | |||
12241 | ConvInput); | |||
12242 | ||||
12243 | unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : | |||
12244 | Intrinsic::arm_neon_vcvtfxu2fp; | |||
12245 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, | |||
12246 | Op.getValueType(), | |||
12247 | DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), | |||
12248 | ConvInput, DAG.getConstant(C, dl, MVT::i32)); | |||
12249 | } | |||
12250 | ||||
12251 | /// Getvshiftimm - Check if this is a valid build_vector for the immediate | |||
12252 | /// operand of a vector shift operation, where all the elements of the | |||
12253 | /// build_vector must have the same constant integer value. | |||
12254 | static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { | |||
12255 | // Ignore bit_converts. | |||
12256 | while (Op.getOpcode() == ISD::BITCAST) | |||
12257 | Op = Op.getOperand(0); | |||
12258 | BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); | |||
12259 | APInt SplatBits, SplatUndef; | |||
12260 | unsigned SplatBitSize; | |||
12261 | bool HasAnyUndefs; | |||
12262 | if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, | |||
12263 | HasAnyUndefs, ElementBits) || | |||
12264 | SplatBitSize > ElementBits) | |||
12265 | return false; | |||
12266 | Cnt = SplatBits.getSExtValue(); | |||
12267 | return true; | |||
12268 | } | |||
12269 | ||||
12270 | /// isVShiftLImm - Check if this is a valid build_vector for the immediate | |||
12271 | /// operand of a vector shift left operation. That value must be in the range: | |||
12272 | /// 0 <= Value < ElementBits for a left shift; or | |||
12273 | /// 0 <= Value <= ElementBits for a long left shift. | |||
12274 | static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { | |||
12275 | assert(VT.isVector() && "vector shift count is not a vector type")((VT.isVector() && "vector shift count is not a vector type" ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"vector shift count is not a vector type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12275, __PRETTY_FUNCTION__)); | |||
12276 | int64_t ElementBits = VT.getScalarSizeInBits(); | |||
12277 | if (! getVShiftImm(Op, ElementBits, Cnt)) | |||
12278 | return false; | |||
12279 | return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); | |||
12280 | } | |||
12281 | ||||
12282 | /// isVShiftRImm - Check if this is a valid build_vector for the immediate | |||
12283 | /// operand of a vector shift right operation. For a shift opcode, the value | |||
12284 | /// is positive, but for an intrinsic the value count must be negative. The | |||
12285 | /// absolute value must be in the range: | |||
12286 | /// 1 <= |Value| <= ElementBits for a right shift; or | |||
12287 | /// 1 <= |Value| <= ElementBits/2 for a narrow right shift. | |||
12288 | static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, | |||
12289 | int64_t &Cnt) { | |||
12290 | assert(VT.isVector() && "vector shift count is not a vector type")((VT.isVector() && "vector shift count is not a vector type" ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"vector shift count is not a vector type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12290, __PRETTY_FUNCTION__)); | |||
12291 | int64_t ElementBits = VT.getScalarSizeInBits(); | |||
12292 | if (! getVShiftImm(Op, ElementBits, Cnt)) | |||
12293 | return false; | |||
12294 | if (!isIntrinsic) | |||
12295 | return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); | |||
12296 | if (Cnt >= -(isNarrow ? ElementBits/2 : ElementBits) && Cnt <= -1) { | |||
12297 | Cnt = -Cnt; | |||
12298 | return true; | |||
12299 | } | |||
12300 | return false; | |||
12301 | } | |||
12302 | ||||
12303 | /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. | |||
12304 | static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { | |||
12305 | unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); | |||
12306 | switch (IntNo) { | |||
12307 | default: | |||
12308 | // Don't do anything for most intrinsics. | |||
12309 | break; | |||
12310 | ||||
12311 | // Vector shifts: check for immediate versions and lower them. | |||
12312 | // Note: This is done during DAG combining instead of DAG legalizing because | |||
12313 | // the build_vectors for 64-bit vector element shift counts are generally | |||
12314 | // not legal, and it is hard to see their values after they get legalized to | |||
12315 | // loads from a constant pool. | |||
12316 | case Intrinsic::arm_neon_vshifts: | |||
12317 | case Intrinsic::arm_neon_vshiftu: | |||
12318 | case Intrinsic::arm_neon_vrshifts: | |||
12319 | case Intrinsic::arm_neon_vrshiftu: | |||
12320 | case Intrinsic::arm_neon_vrshiftn: | |||
12321 | case Intrinsic::arm_neon_vqshifts: | |||
12322 | case Intrinsic::arm_neon_vqshiftu: | |||
12323 | case Intrinsic::arm_neon_vqshiftsu: | |||
12324 | case Intrinsic::arm_neon_vqshiftns: | |||
12325 | case Intrinsic::arm_neon_vqshiftnu: | |||
12326 | case Intrinsic::arm_neon_vqshiftnsu: | |||
12327 | case Intrinsic::arm_neon_vqrshiftns: | |||
12328 | case Intrinsic::arm_neon_vqrshiftnu: | |||
12329 | case Intrinsic::arm_neon_vqrshiftnsu: { | |||
12330 | EVT VT = N->getOperand(1).getValueType(); | |||
12331 | int64_t Cnt; | |||
12332 | unsigned VShiftOpc = 0; | |||
12333 | ||||
12334 | switch (IntNo) { | |||
12335 | case Intrinsic::arm_neon_vshifts: | |||
12336 | case Intrinsic::arm_neon_vshiftu: | |||
12337 | if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { | |||
12338 | VShiftOpc = ARMISD::VSHL; | |||
12339 | break; | |||
12340 | } | |||
12341 | if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { | |||
12342 | VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? | |||
12343 | ARMISD::VSHRs : ARMISD::VSHRu); | |||
12344 | break; | |||
12345 | } | |||
12346 | return SDValue(); | |||
12347 | ||||
12348 | case Intrinsic::arm_neon_vrshifts: | |||
12349 | case Intrinsic::arm_neon_vrshiftu: | |||
12350 | if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) | |||
12351 | break; | |||
12352 | return SDValue(); | |||
12353 | ||||
12354 | case Intrinsic::arm_neon_vqshifts: | |||
12355 | case Intrinsic::arm_neon_vqshiftu: | |||
12356 | if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) | |||
12357 | break; | |||
12358 | return SDValue(); | |||
12359 | ||||
12360 | case Intrinsic::arm_neon_vqshiftsu: | |||
12361 | if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) | |||
12362 | break; | |||
12363 | llvm_unreachable("invalid shift count for vqshlu intrinsic")::llvm::llvm_unreachable_internal("invalid shift count for vqshlu intrinsic" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12363); | |||
12364 | ||||
12365 | case Intrinsic::arm_neon_vrshiftn: | |||
12366 | case Intrinsic::arm_neon_vqshiftns: | |||
12367 | case Intrinsic::arm_neon_vqshiftnu: | |||
12368 | case Intrinsic::arm_neon_vqshiftnsu: | |||
12369 | case Intrinsic::arm_neon_vqrshiftns: | |||
12370 | case Intrinsic::arm_neon_vqrshiftnu: | |||
12371 | case Intrinsic::arm_neon_vqrshiftnsu: | |||
12372 | // Narrowing shifts require an immediate right shift. | |||
12373 | if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) | |||
12374 | break; | |||
12375 | llvm_unreachable("invalid shift count for narrowing vector shift "::llvm::llvm_unreachable_internal("invalid shift count for narrowing vector shift " "intrinsic", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12376) | |||
12376 | "intrinsic")::llvm::llvm_unreachable_internal("invalid shift count for narrowing vector shift " "intrinsic", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12376); | |||
12377 | ||||
12378 | default: | |||
12379 | llvm_unreachable("unhandled vector shift")::llvm::llvm_unreachable_internal("unhandled vector shift", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12379); | |||
12380 | } | |||
12381 | ||||
12382 | switch (IntNo) { | |||
12383 | case Intrinsic::arm_neon_vshifts: | |||
12384 | case Intrinsic::arm_neon_vshiftu: | |||
12385 | // Opcode already set above. | |||
12386 | break; | |||
12387 | case Intrinsic::arm_neon_vrshifts: | |||
12388 | VShiftOpc = ARMISD::VRSHRs; break; | |||
12389 | case Intrinsic::arm_neon_vrshiftu: | |||
12390 | VShiftOpc = ARMISD::VRSHRu; break; | |||
12391 | case Intrinsic::arm_neon_vrshiftn: | |||
12392 | VShiftOpc = ARMISD::VRSHRN; break; | |||
12393 | case Intrinsic::arm_neon_vqshifts: | |||
12394 | VShiftOpc = ARMISD::VQSHLs; break; | |||
12395 | case Intrinsic::arm_neon_vqshiftu: | |||
12396 | VShiftOpc = ARMISD::VQSHLu; break; | |||
12397 | case Intrinsic::arm_neon_vqshiftsu: | |||
12398 | VShiftOpc = ARMISD::VQSHLsu; break; | |||
12399 | case Intrinsic::arm_neon_vqshiftns: | |||
12400 | VShiftOpc = ARMISD::VQSHRNs; break; | |||
12401 | case Intrinsic::arm_neon_vqshiftnu: | |||
12402 | VShiftOpc = ARMISD::VQSHRNu; break; | |||
12403 | case Intrinsic::arm_neon_vqshiftnsu: | |||
12404 | VShiftOpc = ARMISD::VQSHRNsu; break; | |||
12405 | case Intrinsic::arm_neon_vqrshiftns: | |||
12406 | VShiftOpc = ARMISD::VQRSHRNs; break; | |||
12407 | case Intrinsic::arm_neon_vqrshiftnu: | |||
12408 | VShiftOpc = ARMISD::VQRSHRNu; break; | |||
12409 | case Intrinsic::arm_neon_vqrshiftnsu: | |||
12410 | VShiftOpc = ARMISD::VQRSHRNsu; break; | |||
12411 | } | |||
12412 | ||||
12413 | SDLoc dl(N); | |||
12414 | return DAG.getNode(VShiftOpc, dl, N->getValueType(0), | |||
12415 | N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32)); | |||
12416 | } | |||
12417 | ||||
12418 | case Intrinsic::arm_neon_vshiftins: { | |||
12419 | EVT VT = N->getOperand(1).getValueType(); | |||
12420 | int64_t Cnt; | |||
12421 | unsigned VShiftOpc = 0; | |||
12422 | ||||
12423 | if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) | |||
12424 | VShiftOpc = ARMISD::VSLI; | |||
12425 | else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) | |||
12426 | VShiftOpc = ARMISD::VSRI; | |||
12427 | else { | |||
12428 | llvm_unreachable("invalid shift count for vsli/vsri intrinsic")::llvm::llvm_unreachable_internal("invalid shift count for vsli/vsri intrinsic" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12428); | |||
12429 | } | |||
12430 | ||||
12431 | SDLoc dl(N); | |||
12432 | return DAG.getNode(VShiftOpc, dl, N->getValueType(0), | |||
12433 | N->getOperand(1), N->getOperand(2), | |||
12434 | DAG.getConstant(Cnt, dl, MVT::i32)); | |||
12435 | } | |||
12436 | ||||
12437 | case Intrinsic::arm_neon_vqrshifts: | |||
12438 | case Intrinsic::arm_neon_vqrshiftu: | |||
12439 | // No immediate versions of these to check for. | |||
12440 | break; | |||
12441 | } | |||
12442 | ||||
12443 | return SDValue(); | |||
12444 | } | |||
12445 | ||||
12446 | /// PerformShiftCombine - Checks for immediate versions of vector shifts and | |||
12447 | /// lowers them. As with the vector shift intrinsics, this is done during DAG | |||
12448 | /// combining instead of DAG legalizing because the build_vectors for 64-bit | |||
12449 | /// vector element shift counts are generally not legal, and it is hard to see | |||
12450 | /// their values after they get legalized to loads from a constant pool. | |||
12451 | static SDValue PerformShiftCombine(SDNode *N, | |||
12452 | TargetLowering::DAGCombinerInfo &DCI, | |||
12453 | const ARMSubtarget *ST) { | |||
12454 | SelectionDAG &DAG = DCI.DAG; | |||
12455 | EVT VT = N->getValueType(0); | |||
12456 | if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) { | |||
12457 | // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high | |||
12458 | // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16. | |||
12459 | SDValue N1 = N->getOperand(1); | |||
12460 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { | |||
12461 | SDValue N0 = N->getOperand(0); | |||
12462 | if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP && | |||
12463 | DAG.MaskedValueIsZero(N0.getOperand(0), | |||
12464 | APInt::getHighBitsSet(32, 16))) | |||
12465 | return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1); | |||
12466 | } | |||
12467 | } | |||
12468 | ||||
12469 | if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 && | |||
12470 | N->getOperand(0)->getOpcode() == ISD::AND && | |||
12471 | N->getOperand(0)->hasOneUse()) { | |||
12472 | if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) | |||
12473 | return SDValue(); | |||
12474 | // Look for the pattern (shl (and x, AndMask), ShiftAmt). This doesn't | |||
12475 | // usually show up because instcombine prefers to canonicalize it to | |||
12476 | // (and (shl x, ShiftAmt) (shl AndMask, ShiftAmt)), but the shift can come | |||
12477 | // out of GEP lowering in some cases. | |||
12478 | SDValue N0 = N->getOperand(0); | |||
12479 | ConstantSDNode *ShiftAmtNode = dyn_cast<ConstantSDNode>(N->getOperand(1)); | |||
12480 | if (!ShiftAmtNode) | |||
12481 | return SDValue(); | |||
12482 | uint32_t ShiftAmt = static_cast<uint32_t>(ShiftAmtNode->getZExtValue()); | |||
12483 | ConstantSDNode *AndMaskNode = dyn_cast<ConstantSDNode>(N0->getOperand(1)); | |||
12484 | if (!AndMaskNode) | |||
12485 | return SDValue(); | |||
12486 | uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); | |||
12487 | // Don't transform uxtb/uxth. | |||
12488 | if (AndMask == 255 || AndMask == 65535) | |||
12489 | return SDValue(); | |||
12490 | if (isMask_32(AndMask)) { | |||
12491 | uint32_t MaskedBits = countLeadingZeros(AndMask); | |||
12492 | if (MaskedBits > ShiftAmt) { | |||
12493 | SDLoc DL(N); | |||
12494 | SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), | |||
12495 | DAG.getConstant(MaskedBits, DL, MVT::i32)); | |||
12496 | return DAG.getNode( | |||
12497 | ISD::SRL, DL, MVT::i32, SHL, | |||
12498 | DAG.getConstant(MaskedBits - ShiftAmt, DL, MVT::i32)); | |||
12499 | } | |||
12500 | } | |||
12501 | } | |||
12502 | ||||
12503 | // Nothing to be done for scalar shifts. | |||
12504 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
12505 | if (!VT.isVector() || !TLI.isTypeLegal(VT)) | |||
12506 | return SDValue(); | |||
12507 | ||||
12508 | assert(ST->hasNEON() && "unexpected vector shift")((ST->hasNEON() && "unexpected vector shift") ? static_cast <void> (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12508, __PRETTY_FUNCTION__)); | |||
12509 | int64_t Cnt; | |||
12510 | ||||
12511 | switch (N->getOpcode()) { | |||
12512 | default: llvm_unreachable("unexpected shift opcode")::llvm::llvm_unreachable_internal("unexpected shift opcode", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12512); | |||
12513 | ||||
12514 | case ISD::SHL: | |||
12515 | if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) { | |||
12516 | SDLoc dl(N); | |||
12517 | return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0), | |||
12518 | DAG.getConstant(Cnt, dl, MVT::i32)); | |||
12519 | } | |||
12520 | break; | |||
12521 | ||||
12522 | case ISD::SRA: | |||
12523 | case ISD::SRL: | |||
12524 | if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { | |||
12525 | unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? | |||
12526 | ARMISD::VSHRs : ARMISD::VSHRu); | |||
12527 | SDLoc dl(N); | |||
12528 | return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0), | |||
12529 | DAG.getConstant(Cnt, dl, MVT::i32)); | |||
12530 | } | |||
12531 | } | |||
12532 | return SDValue(); | |||
12533 | } | |||
12534 | ||||
12535 | /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, | |||
12536 | /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. | |||
12537 | static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, | |||
12538 | const ARMSubtarget *ST) { | |||
12539 | SDValue N0 = N->getOperand(0); | |||
12540 | ||||
12541 | // Check for sign- and zero-extensions of vector extract operations of 8- | |||
12542 | // and 16-bit vector elements. NEON supports these directly. They are | |||
12543 | // handled during DAG combining because type legalization will promote them | |||
12544 | // to 32-bit types and it is messy to recognize the operations after that. | |||
12545 | if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { | |||
12546 | SDValue Vec = N0.getOperand(0); | |||
12547 | SDValue Lane = N0.getOperand(1); | |||
12548 | EVT VT = N->getValueType(0); | |||
12549 | EVT EltVT = N0.getValueType(); | |||
12550 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
12551 | ||||
12552 | if (VT == MVT::i32 && | |||
12553 | (EltVT == MVT::i8 || EltVT == MVT::i16) && | |||
12554 | TLI.isTypeLegal(Vec.getValueType()) && | |||
12555 | isa<ConstantSDNode>(Lane)) { | |||
12556 | ||||
12557 | unsigned Opc = 0; | |||
12558 | switch (N->getOpcode()) { | |||
12559 | default: llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12559); | |||
12560 | case ISD::SIGN_EXTEND: | |||
12561 | Opc = ARMISD::VGETLANEs; | |||
12562 | break; | |||
12563 | case ISD::ZERO_EXTEND: | |||
12564 | case ISD::ANY_EXTEND: | |||
12565 | Opc = ARMISD::VGETLANEu; | |||
12566 | break; | |||
12567 | } | |||
12568 | return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane); | |||
12569 | } | |||
12570 | } | |||
12571 | ||||
12572 | return SDValue(); | |||
12573 | } | |||
12574 | ||||
12575 | static const APInt *isPowerOf2Constant(SDValue V) { | |||
12576 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); | |||
12577 | if (!C) | |||
12578 | return nullptr; | |||
12579 | const APInt *CV = &C->getAPIntValue(); | |||
12580 | return CV->isPowerOf2() ? CV : nullptr; | |||
12581 | } | |||
12582 | ||||
12583 | SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const { | |||
12584 | // If we have a CMOV, OR and AND combination such as: | |||
12585 | // if (x & CN) | |||
12586 | // y |= CM; | |||
12587 | // | |||
12588 | // And: | |||
12589 | // * CN is a single bit; | |||
12590 | // * All bits covered by CM are known zero in y | |||
12591 | // | |||
12592 | // Then we can convert this into a sequence of BFI instructions. This will | |||
12593 | // always be a win if CM is a single bit, will always be no worse than the | |||
12594 | // TST&OR sequence if CM is two bits, and for thumb will be no worse if CM is | |||
12595 | // three bits (due to the extra IT instruction). | |||
12596 | ||||
12597 | SDValue Op0 = CMOV->getOperand(0); | |||
12598 | SDValue Op1 = CMOV->getOperand(1); | |||
12599 | auto CCNode = cast<ConstantSDNode>(CMOV->getOperand(2)); | |||
12600 | auto CC = CCNode->getAPIntValue().getLimitedValue(); | |||
12601 | SDValue CmpZ = CMOV->getOperand(4); | |||
12602 | ||||
12603 | // The compare must be against zero. | |||
12604 | if (!isNullConstant(CmpZ->getOperand(1))) | |||
12605 | return SDValue(); | |||
12606 | ||||
12607 | assert(CmpZ->getOpcode() == ARMISD::CMPZ)((CmpZ->getOpcode() == ARMISD::CMPZ) ? static_cast<void > (0) : __assert_fail ("CmpZ->getOpcode() == ARMISD::CMPZ" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12607, __PRETTY_FUNCTION__)); | |||
12608 | SDValue And = CmpZ->getOperand(0); | |||
12609 | if (And->getOpcode() != ISD::AND) | |||
12610 | return SDValue(); | |||
12611 | const APInt *AndC = isPowerOf2Constant(And->getOperand(1)); | |||
12612 | if (!AndC) | |||
12613 | return SDValue(); | |||
12614 | SDValue X = And->getOperand(0); | |||
12615 | ||||
12616 | if (CC == ARMCC::EQ) { | |||
12617 | // We're performing an "equal to zero" compare. Swap the operands so we | |||
12618 | // canonicalize on a "not equal to zero" compare. | |||
12619 | std::swap(Op0, Op1); | |||
12620 | } else { | |||
12621 | assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?")((CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?" ) ? static_cast<void> (0) : __assert_fail ("CC == ARMCC::NE && \"How can a CMPZ node not be EQ or NE?\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 12621, __PRETTY_FUNCTION__)); | |||
12622 | } | |||
12623 | ||||
12624 | if (Op1->getOpcode() != ISD::OR) | |||
12625 | return SDValue(); | |||
12626 | ||||
12627 | ConstantSDNode *OrC = dyn_cast<ConstantSDNode>(Op1->getOperand(1)); | |||
12628 | if (!OrC) | |||
12629 | return SDValue(); | |||
12630 | SDValue Y = Op1->getOperand(0); | |||
12631 | ||||
12632 | if (Op0 != Y) | |||
12633 | return SDValue(); | |||
12634 | ||||
12635 | // Now, is it profitable to continue? | |||
12636 | APInt OrCI = OrC->getAPIntValue(); | |||
12637 | unsigned Heuristic = Subtarget->isThumb() ? 3 : 2; | |||
12638 | if (OrCI.countPopulation() > Heuristic) | |||
12639 | return SDValue(); | |||
12640 | ||||
12641 | // Lastly, can we determine that the bits defined by OrCI | |||
12642 | // are zero in Y? | |||
12643 | KnownBits Known = DAG.computeKnownBits(Y); | |||
12644 | if ((OrCI & Known.Zero) != OrCI) | |||
12645 | return SDValue(); | |||
12646 | ||||
12647 | // OK, we can do the combine. | |||
12648 | SDValue V = Y; | |||
12649 | SDLoc dl(X); | |||
12650 | EVT VT = X.getValueType(); | |||
12651 | unsigned BitInX = AndC->logBase2(); | |||
12652 | ||||
12653 | if (BitInX != 0) { | |||
12654 | // We must shift X first. | |||
12655 | X = DAG.getNode(ISD::SRL, dl, VT, X, | |||
12656 | DAG.getConstant(BitInX, dl, VT)); | |||
12657 | } | |||
12658 | ||||
12659 | for (unsigned BitInY = 0, NumActiveBits = OrCI.getActiveBits(); | |||
12660 | BitInY < NumActiveBits; ++BitInY) { | |||
12661 | if (OrCI[BitInY] == 0) | |||
12662 | continue; | |||
12663 | APInt Mask(VT.getSizeInBits(), 0); | |||
12664 | Mask.setBit(BitInY); | |||
12665 | V = DAG.getNode(ARMISD::BFI, dl, VT, V, X, | |||
12666 | // Confusingly, the operand is an *inverted* mask. | |||
12667 | DAG.getConstant(~Mask, dl, VT)); | |||
12668 | } | |||
12669 | ||||
12670 | return V; | |||
12671 | } | |||
12672 | ||||
12673 | /// PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND. | |||
12674 | SDValue | |||
12675 | ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const { | |||
12676 | SDValue Cmp = N->getOperand(4); | |||
12677 | if (Cmp.getOpcode() != ARMISD::CMPZ) | |||
12678 | // Only looking at NE cases. | |||
12679 | return SDValue(); | |||
12680 | ||||
12681 | EVT VT = N->getValueType(0); | |||
12682 | SDLoc dl(N); | |||
12683 | SDValue LHS = Cmp.getOperand(0); | |||
12684 | SDValue RHS = Cmp.getOperand(1); | |||
12685 | SDValue Chain = N->getOperand(0); | |||
12686 | SDValue BB = N->getOperand(1); | |||
12687 | SDValue ARMcc = N->getOperand(2); | |||
12688 | ARMCC::CondCodes CC = | |||
12689 | (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); | |||
12690 | ||||
12691 | // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0)) | |||
12692 | // -> (brcond Chain BB CC CPSR Cmp) | |||
12693 | if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() && | |||
12694 | LHS->getOperand(0)->getOpcode() == ARMISD::CMOV && | |||
12695 | LHS->getOperand(0)->hasOneUse()) { | |||
12696 | auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0)); | |||
12697 | auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1)); | |||
12698 | auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); | |||
12699 | auto *RHSC = dyn_cast<ConstantSDNode>(RHS); | |||
12700 | if ((LHS00C && LHS00C->getZExtValue() == 0) && | |||
12701 | (LHS01C && LHS01C->getZExtValue() == 1) && | |||
12702 | (LHS1C && LHS1C->getZExtValue() == 1) && | |||
12703 | (RHSC && RHSC->getZExtValue() == 0)) { | |||
12704 | return DAG.getNode( | |||
12705 | ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2), | |||
12706 | LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4)); | |||
12707 | } | |||
12708 | } | |||
12709 | ||||
12710 | return SDValue(); | |||
12711 | } | |||
12712 | ||||
12713 | /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. | |||
12714 | SDValue | |||
12715 | ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { | |||
12716 | SDValue Cmp = N->getOperand(4); | |||
12717 | if (Cmp.getOpcode() != ARMISD::CMPZ) | |||
12718 | // Only looking at EQ and NE cases. | |||
12719 | return SDValue(); | |||
12720 | ||||
12721 | EVT VT = N->getValueType(0); | |||
12722 | SDLoc dl(N); | |||
12723 | SDValue LHS = Cmp.getOperand(0); | |||
12724 | SDValue RHS = Cmp.getOperand(1); | |||
12725 | SDValue FalseVal = N->getOperand(0); | |||
12726 | SDValue TrueVal = N->getOperand(1); | |||
12727 | SDValue ARMcc = N->getOperand(2); | |||
12728 | ARMCC::CondCodes CC = | |||
12729 | (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); | |||
12730 | ||||
12731 | // BFI is only available on V6T2+. | |||
12732 | if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) { | |||
12733 | SDValue R = PerformCMOVToBFICombine(N, DAG); | |||
12734 | if (R) | |||
12735 | return R; | |||
12736 | } | |||
12737 | ||||
12738 | // Simplify | |||
12739 | // mov r1, r0 | |||
12740 | // cmp r1, x | |||
12741 | // mov r0, y | |||
12742 | // moveq r0, x | |||
12743 | // to | |||
12744 | // cmp r0, x | |||
12745 | // movne r0, y | |||
12746 | // | |||
12747 | // mov r1, r0 | |||
12748 | // cmp r1, x | |||
12749 | // mov r0, x | |||
12750 | // movne r0, y | |||
12751 | // to | |||
12752 | // cmp r0, x | |||
12753 | // movne r0, y | |||
12754 | /// FIXME: Turn this into a target neutral optimization? | |||
12755 | SDValue Res; | |||
12756 | if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { | |||
12757 | Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, | |||
12758 | N->getOperand(3), Cmp); | |||
12759 | } else if (CC == ARMCC::EQ && TrueVal == RHS) { | |||
12760 | SDValue ARMcc; | |||
12761 | SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); | |||
12762 | Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, | |||
12763 | N->getOperand(3), NewCmp); | |||
12764 | } | |||
12765 | ||||
12766 | // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0)) | |||
12767 | // -> (cmov F T CC CPSR Cmp) | |||
12768 | if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) { | |||
12769 | auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)); | |||
12770 | auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); | |||
12771 | auto *RHSC = dyn_cast<ConstantSDNode>(RHS); | |||
12772 | if ((LHS0C && LHS0C->getZExtValue() == 0) && | |||
12773 | (LHS1C && LHS1C->getZExtValue() == 1) && | |||
12774 | (RHSC && RHSC->getZExtValue() == 0)) { | |||
12775 | return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, | |||
12776 | LHS->getOperand(2), LHS->getOperand(3), | |||
12777 | LHS->getOperand(4)); | |||
12778 | } | |||
12779 | } | |||
12780 | ||||
12781 | if (!VT.isInteger()) | |||
12782 | return SDValue(); | |||
12783 | ||||
12784 | // Materialize a boolean comparison for integers so we can avoid branching. | |||
12785 | if (isNullConstant(FalseVal)) { | |||
12786 | if (CC == ARMCC::EQ && isOneConstant(TrueVal)) { | |||
12787 | if (!Subtarget->isThumb1Only() && Subtarget->hasV5TOps()) { | |||
12788 | // If x == y then x - y == 0 and ARM's CLZ will return 32, shifting it | |||
12789 | // right 5 bits will make that 32 be 1, otherwise it will be 0. | |||
12790 | // CMOV 0, 1, ==, (CMPZ x, y) -> SRL (CTLZ (SUB x, y)), 5 | |||
12791 | SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS); | |||
12792 | Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub), | |||
12793 | DAG.getConstant(5, dl, MVT::i32)); | |||
12794 | } else { | |||
12795 | // CMOV 0, 1, ==, (CMPZ x, y) -> | |||
12796 | // (ADDCARRY (SUB x, y), t:0, t:1) | |||
12797 | // where t = (SUBCARRY 0, (SUB x, y), 0) | |||
12798 | // | |||
12799 | // The SUBCARRY computes 0 - (x - y) and this will give a borrow when | |||
12800 | // x != y. In other words, a carry C == 1 when x == y, C == 0 | |||
12801 | // otherwise. | |||
12802 | // The final ADDCARRY computes | |||
12803 | // x - y + (0 - (x - y)) + C == C | |||
12804 | SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS); | |||
12805 | SDVTList VTs = DAG.getVTList(VT, MVT::i32); | |||
12806 | SDValue Neg = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, Sub); | |||
12807 | // ISD::SUBCARRY returns a borrow but we want the carry here | |||
12808 | // actually. | |||
12809 | SDValue Carry = | |||
12810 | DAG.getNode(ISD::SUB, dl, MVT::i32, | |||
12811 | DAG.getConstant(1, dl, MVT::i32), Neg.getValue(1)); | |||
12812 | Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry); | |||
12813 | } | |||
12814 | } else if (CC == ARMCC::NE && !isNullConstant(RHS) && | |||
12815 | (!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) { | |||
12816 | // This seems pointless but will allow us to combine it further below. | |||
12817 | // CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1 | |||
12818 | SDValue Sub = | |||
12819 | DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); | |||
12820 | SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, | |||
12821 | Sub.getValue(1), SDValue()); | |||
12822 | Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, TrueVal, ARMcc, | |||
12823 | N->getOperand(3), CPSRGlue.getValue(1)); | |||
12824 | FalseVal = Sub; | |||
12825 | } | |||
12826 | } else if (isNullConstant(TrueVal)) { | |||
12827 | if (CC == ARMCC::EQ && !isNullConstant(RHS) && | |||
12828 | (!Subtarget->isThumb1Only() || isPowerOf2Constant(FalseVal))) { | |||
12829 | // This seems pointless but will allow us to combine it further below | |||
12830 | // Note that we change == for != as this is the dual for the case above. | |||
12831 | // CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1 | |||
12832 | SDValue Sub = | |||
12833 | DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); | |||
12834 | SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, | |||
12835 | Sub.getValue(1), SDValue()); | |||
12836 | Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal, | |||
12837 | DAG.getConstant(ARMCC::NE, dl, MVT::i32), | |||
12838 | N->getOperand(3), CPSRGlue.getValue(1)); | |||
12839 | FalseVal = Sub; | |||
12840 | } | |||
12841 | } | |||
12842 | ||||
12843 | // On Thumb1, the DAG above may be further combined if z is a power of 2 | |||
12844 | // (z == 2 ^ K). | |||
12845 | // CMOV (SUBS x, y), z, !=, (SUBS x, y):1 -> | |||
12846 | // t1 = (USUBO (SUB x, y), 1) | |||
12847 | // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1) | |||
12848 | // Result = if K != 0 then (SHL t2:0, K) else t2:0 | |||
12849 | // | |||
12850 | // This also handles the special case of comparing against zero; it's | |||
12851 | // essentially, the same pattern, except there's no SUBS: | |||
12852 | // CMOV x, z, !=, (CMPZ x, 0) -> | |||
12853 | // t1 = (USUBO x, 1) | |||
12854 | // t2 = (SUBCARRY x, t1:0, t1:1) | |||
12855 | // Result = if K != 0 then (SHL t2:0, K) else t2:0 | |||
12856 | const APInt *TrueConst; | |||
12857 | if (Subtarget->isThumb1Only() && CC == ARMCC::NE && | |||
12858 | ((FalseVal.getOpcode() == ARMISD::SUBS && | |||
12859 | FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) || | |||
12860 | (FalseVal == LHS && isNullConstant(RHS))) && | |||
12861 | (TrueConst = isPowerOf2Constant(TrueVal))) { | |||
12862 | SDVTList VTs = DAG.getVTList(VT, MVT::i32); | |||
12863 | unsigned ShiftAmount = TrueConst->logBase2(); | |||
12864 | if (ShiftAmount) | |||
12865 | TrueVal = DAG.getConstant(1, dl, VT); | |||
12866 | SDValue Subc = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, TrueVal); | |||
12867 | Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1)); | |||
12868 | ||||
12869 | if (ShiftAmount) | |||
12870 | Res = DAG.getNode(ISD::SHL, dl, VT, Res, | |||
12871 | DAG.getConstant(ShiftAmount, dl, MVT::i32)); | |||
12872 | } | |||
12873 | ||||
12874 | if (Res.getNode()) { | |||
12875 | KnownBits Known = DAG.computeKnownBits(SDValue(N,0)); | |||
12876 | // Capture demanded bits information that would be otherwise lost. | |||
12877 | if (Known.Zero == 0xfffffffe) | |||
12878 | Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, | |||
12879 | DAG.getValueType(MVT::i1)); | |||
12880 | else if (Known.Zero == 0xffffff00) | |||
12881 | Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, | |||
12882 | DAG.getValueType(MVT::i8)); | |||
12883 | else if (Known.Zero == 0xffff0000) | |||
12884 | Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, | |||
12885 | DAG.getValueType(MVT::i16)); | |||
12886 | } | |||
12887 | ||||
12888 | return Res; | |||
12889 | } | |||
12890 | ||||
12891 | SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, | |||
12892 | DAGCombinerInfo &DCI) const { | |||
12893 | switch (N->getOpcode()) { | |||
12894 | default: break; | |||
12895 | case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); | |||
12896 | case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); | |||
12897 | case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); | |||
12898 | case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); | |||
12899 | case ISD::SUB: return PerformSUBCombine(N, DCI); | |||
12900 | case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); | |||
12901 | case ISD::OR: return PerformORCombine(N, DCI, Subtarget); | |||
12902 | case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); | |||
12903 | case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); | |||
12904 | case ARMISD::ADDC: | |||
12905 | case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); | |||
12906 | case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); | |||
12907 | case ARMISD::BFI: return PerformBFICombine(N, DCI); | |||
12908 | case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); | |||
12909 | case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); | |||
12910 | case ISD::STORE: return PerformSTORECombine(N, DCI); | |||
12911 | case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); | |||
12912 | case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); | |||
12913 | case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); | |||
12914 | case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); | |||
12915 | case ARMISD::VDUP: return PerformVDUPCombine(N, DCI); | |||
12916 | case ISD::FP_TO_SINT: | |||
12917 | case ISD::FP_TO_UINT: | |||
12918 | return PerformVCVTCombine(N, DCI.DAG, Subtarget); | |||
12919 | case ISD::FDIV: | |||
12920 | return PerformVDIVCombine(N, DCI.DAG, Subtarget); | |||
12921 | case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); | |||
12922 | case ISD::SHL: | |||
12923 | case ISD::SRA: | |||
12924 | case ISD::SRL: | |||
12925 | return PerformShiftCombine(N, DCI, Subtarget); | |||
12926 | case ISD::SIGN_EXTEND: | |||
12927 | case ISD::ZERO_EXTEND: | |||
12928 | case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); | |||
12929 | case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); | |||
12930 | case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG); | |||
12931 | case ISD::LOAD: return PerformLOADCombine(N, DCI); | |||
12932 | case ARMISD::VLD1DUP: | |||
12933 | case ARMISD::VLD2DUP: | |||
12934 | case ARMISD::VLD3DUP: | |||
12935 | case ARMISD::VLD4DUP: | |||
12936 | return PerformVLDCombine(N, DCI); | |||
12937 | case ARMISD::BUILD_VECTOR: | |||
12938 | return PerformARMBUILD_VECTORCombine(N, DCI); | |||
12939 | case ARMISD::SMULWB: { | |||
12940 | unsigned BitWidth = N->getValueType(0).getSizeInBits(); | |||
12941 | APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16); | |||
12942 | if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) | |||
12943 | return SDValue(); | |||
12944 | break; | |||
12945 | } | |||
12946 | case ARMISD::SMULWT: { | |||
12947 | unsigned BitWidth = N->getValueType(0).getSizeInBits(); | |||
12948 | APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 16); | |||
12949 | if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) | |||
12950 | return SDValue(); | |||
12951 | break; | |||
12952 | } | |||
12953 | case ARMISD::SMLALBB: { | |||
12954 | unsigned BitWidth = N->getValueType(0).getSizeInBits(); | |||
12955 | APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16); | |||
12956 | if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || | |||
12957 | (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) | |||
12958 | return SDValue(); | |||
12959 | break; | |||
12960 | } | |||
12961 | case ARMISD::SMLALBT: { | |||
12962 | unsigned LowWidth = N->getOperand(0).getValueType().getSizeInBits(); | |||
12963 | APInt LowMask = APInt::getLowBitsSet(LowWidth, 16); | |||
12964 | unsigned HighWidth = N->getOperand(1).getValueType().getSizeInBits(); | |||
12965 | APInt HighMask = APInt::getHighBitsSet(HighWidth, 16); | |||
12966 | if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || | |||
12967 | (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) | |||
12968 | return SDValue(); | |||
12969 | break; | |||
12970 | } | |||
12971 | case ARMISD::SMLALTB: { | |||
12972 | unsigned HighWidth = N->getOperand(0).getValueType().getSizeInBits(); | |||
12973 | APInt HighMask = APInt::getHighBitsSet(HighWidth, 16); | |||
12974 | unsigned LowWidth = N->getOperand(1).getValueType().getSizeInBits(); | |||
12975 | APInt LowMask = APInt::getLowBitsSet(LowWidth, 16); | |||
12976 | if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) || | |||
12977 | (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI))) | |||
12978 | return SDValue(); | |||
12979 | break; | |||
12980 | } | |||
12981 | case ARMISD::SMLALTT: { | |||
12982 | unsigned BitWidth = N->getValueType(0).getSizeInBits(); | |||
12983 | APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 16); | |||
12984 | if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || | |||
12985 | (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) | |||
12986 | return SDValue(); | |||
12987 | break; | |||
12988 | } | |||
12989 | case ISD::INTRINSIC_VOID: | |||
12990 | case ISD::INTRINSIC_W_CHAIN: | |||
12991 | switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { | |||
12992 | case Intrinsic::arm_neon_vld1: | |||
12993 | case Intrinsic::arm_neon_vld1x2: | |||
12994 | case Intrinsic::arm_neon_vld1x3: | |||
12995 | case Intrinsic::arm_neon_vld1x4: | |||
12996 | case Intrinsic::arm_neon_vld2: | |||
12997 | case Intrinsic::arm_neon_vld3: | |||
12998 | case Intrinsic::arm_neon_vld4: | |||
12999 | case Intrinsic::arm_neon_vld2lane: | |||
13000 | case Intrinsic::arm_neon_vld3lane: | |||
13001 | case Intrinsic::arm_neon_vld4lane: | |||
13002 | case Intrinsic::arm_neon_vld2dup: | |||
13003 | case Intrinsic::arm_neon_vld3dup: | |||
13004 | case Intrinsic::arm_neon_vld4dup: | |||
13005 | case Intrinsic::arm_neon_vst1: | |||
13006 | case Intrinsic::arm_neon_vst1x2: | |||
13007 | case Intrinsic::arm_neon_vst1x3: | |||
13008 | case Intrinsic::arm_neon_vst1x4: | |||
13009 | case Intrinsic::arm_neon_vst2: | |||
13010 | case Intrinsic::arm_neon_vst3: | |||
13011 | case Intrinsic::arm_neon_vst4: | |||
13012 | case Intrinsic::arm_neon_vst2lane: | |||
13013 | case Intrinsic::arm_neon_vst3lane: | |||
13014 | case Intrinsic::arm_neon_vst4lane: | |||
13015 | return PerformVLDCombine(N, DCI); | |||
13016 | default: break; | |||
13017 | } | |||
13018 | break; | |||
13019 | } | |||
13020 | return SDValue(); | |||
13021 | } | |||
13022 | ||||
13023 | bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, | |||
13024 | EVT VT) const { | |||
13025 | return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); | |||
13026 | } | |||
13027 | ||||
13028 | bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, | |||
13029 | unsigned, | |||
13030 | unsigned, | |||
13031 | bool *Fast) const { | |||
13032 | // Depends what it gets converted into if the type is weird. | |||
13033 | if (!VT.isSimple()) | |||
13034 | return false; | |||
13035 | ||||
13036 | // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus | |||
13037 | bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); | |||
13038 | ||||
13039 | switch (VT.getSimpleVT().SimpleTy) { | |||
13040 | default: | |||
13041 | return false; | |||
13042 | case MVT::i8: | |||
13043 | case MVT::i16: | |||
13044 | case MVT::i32: { | |||
13045 | // Unaligned access can use (for example) LRDB, LRDH, LDR | |||
13046 | if (AllowsUnaligned) { | |||
13047 | if (Fast) | |||
13048 | *Fast = Subtarget->hasV7Ops(); | |||
13049 | return true; | |||
13050 | } | |||
13051 | return false; | |||
13052 | } | |||
13053 | case MVT::f64: | |||
13054 | case MVT::v2f64: { | |||
13055 | // For any little-endian targets with neon, we can support unaligned ld/st | |||
13056 | // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8. | |||
13057 | // A big-endian target may also explicitly support unaligned accesses | |||
13058 | if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) { | |||
13059 | if (Fast) | |||
13060 | *Fast = true; | |||
13061 | return true; | |||
13062 | } | |||
13063 | return false; | |||
13064 | } | |||
13065 | } | |||
13066 | } | |||
13067 | ||||
13068 | static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, | |||
13069 | unsigned AlignCheck) { | |||
13070 | return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) && | |||
13071 | (DstAlign == 0 || DstAlign % AlignCheck == 0)); | |||
13072 | } | |||
13073 | ||||
13074 | EVT ARMTargetLowering::getOptimalMemOpType( | |||
13075 | uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, | |||
13076 | bool ZeroMemset, bool MemcpyStrSrc, | |||
13077 | const AttributeList &FuncAttributes) const { | |||
13078 | // See if we can use NEON instructions for this... | |||
13079 | if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() && | |||
13080 | !FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat)) { | |||
13081 | bool Fast; | |||
13082 | if (Size >= 16 && | |||
13083 | (memOpAlign(SrcAlign, DstAlign, 16) || | |||
13084 | (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) { | |||
13085 | return MVT::v2f64; | |||
13086 | } else if (Size >= 8 && | |||
13087 | (memOpAlign(SrcAlign, DstAlign, 8) || | |||
13088 | (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) && | |||
13089 | Fast))) { | |||
13090 | return MVT::f64; | |||
13091 | } | |||
13092 | } | |||
13093 | ||||
13094 | // Let the target-independent logic figure it out. | |||
13095 | return MVT::Other; | |||
13096 | } | |||
13097 | ||||
13098 | // 64-bit integers are split into their high and low parts and held in two | |||
13099 | // different registers, so the trunc is free since the low register can just | |||
13100 | // be used. | |||
13101 | bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { | |||
13102 | if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) | |||
13103 | return false; | |||
13104 | unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); | |||
13105 | unsigned DestBits = DstTy->getPrimitiveSizeInBits(); | |||
13106 | return (SrcBits == 64 && DestBits == 32); | |||
13107 | } | |||
13108 | ||||
13109 | bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { | |||
13110 | if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || | |||
13111 | !DstVT.isInteger()) | |||
13112 | return false; | |||
13113 | unsigned SrcBits = SrcVT.getSizeInBits(); | |||
13114 | unsigned DestBits = DstVT.getSizeInBits(); | |||
13115 | return (SrcBits == 64 && DestBits == 32); | |||
13116 | } | |||
13117 | ||||
13118 | bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { | |||
13119 | if (Val.getOpcode() != ISD::LOAD) | |||
13120 | return false; | |||
13121 | ||||
13122 | EVT VT1 = Val.getValueType(); | |||
13123 | if (!VT1.isSimple() || !VT1.isInteger() || | |||
13124 | !VT2.isSimple() || !VT2.isInteger()) | |||
13125 | return false; | |||
13126 | ||||
13127 | switch (VT1.getSimpleVT().SimpleTy) { | |||
13128 | default: break; | |||
13129 | case MVT::i1: | |||
13130 | case MVT::i8: | |||
13131 | case MVT::i16: | |||
13132 | // 8-bit and 16-bit loads implicitly zero-extend to 32-bits. | |||
13133 | return true; | |||
13134 | } | |||
13135 | ||||
13136 | return false; | |||
13137 | } | |||
13138 | ||||
13139 | bool ARMTargetLowering::isFNegFree(EVT VT) const { | |||
13140 | if (!VT.isSimple()) | |||
13141 | return false; | |||
13142 | ||||
13143 | // There are quite a few FP16 instructions (e.g. VNMLA, VNMLS, etc.) that | |||
13144 | // negate values directly (fneg is free). So, we don't want to let the DAG | |||
13145 | // combiner rewrite fneg into xors and some other instructions. For f16 and | |||
13146 | // FullFP16 argument passing, some bitcast nodes may be introduced, | |||
13147 | // triggering this DAG combine rewrite, so we are avoiding that with this. | |||
13148 | switch (VT.getSimpleVT().SimpleTy) { | |||
13149 | default: break; | |||
13150 | case MVT::f16: | |||
13151 | return Subtarget->hasFullFP16(); | |||
13152 | } | |||
13153 | ||||
13154 | return false; | |||
13155 | } | |||
13156 | ||||
13157 | /// Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth | |||
13158 | /// of the vector elements. | |||
13159 | static bool areExtractExts(Value *Ext1, Value *Ext2) { | |||
13160 | auto areExtDoubled = [](Instruction *Ext) { | |||
13161 | return Ext->getType()->getScalarSizeInBits() == | |||
13162 | 2 * Ext->getOperand(0)->getType()->getScalarSizeInBits(); | |||
13163 | }; | |||
13164 | ||||
13165 | if (!match(Ext1, m_ZExtOrSExt(m_Value())) || | |||
13166 | !match(Ext2, m_ZExtOrSExt(m_Value())) || | |||
13167 | !areExtDoubled(cast<Instruction>(Ext1)) || | |||
13168 | !areExtDoubled(cast<Instruction>(Ext2))) | |||
13169 | return false; | |||
13170 | ||||
13171 | return true; | |||
13172 | } | |||
13173 | ||||
13174 | /// Check if sinking \p I's operands to I's basic block is profitable, because | |||
13175 | /// the operands can be folded into a target instruction, e.g. | |||
13176 | /// sext/zext can be folded into vsubl. | |||
13177 | bool ARMTargetLowering::shouldSinkOperands(Instruction *I, | |||
13178 | SmallVectorImpl<Use *> &Ops) const { | |||
13179 | if (!Subtarget->hasNEON() || !I->getType()->isVectorTy()) | |||
13180 | return false; | |||
13181 | ||||
13182 | switch (I->getOpcode()) { | |||
13183 | case Instruction::Sub: | |||
13184 | case Instruction::Add: { | |||
13185 | if (!areExtractExts(I->getOperand(0), I->getOperand(1))) | |||
13186 | return false; | |||
13187 | Ops.push_back(&I->getOperandUse(0)); | |||
13188 | Ops.push_back(&I->getOperandUse(1)); | |||
13189 | return true; | |||
13190 | } | |||
13191 | default: | |||
13192 | return false; | |||
13193 | } | |||
13194 | return false; | |||
13195 | } | |||
13196 | ||||
13197 | bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { | |||
13198 | EVT VT = ExtVal.getValueType(); | |||
13199 | ||||
13200 | if (!isTypeLegal(VT)) | |||
13201 | return false; | |||
13202 | ||||
13203 | // Don't create a loadext if we can fold the extension into a wide/long | |||
13204 | // instruction. | |||
13205 | // If there's more than one user instruction, the loadext is desirable no | |||
13206 | // matter what. There can be two uses by the same instruction. | |||
13207 | if (ExtVal->use_empty() || | |||
13208 | !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode())) | |||
13209 | return true; | |||
13210 | ||||
13211 | SDNode *U = *ExtVal->use_begin(); | |||
13212 | if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB || | |||
13213 | U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL)) | |||
13214 | return false; | |||
13215 | ||||
13216 | return true; | |||
13217 | } | |||
13218 | ||||
13219 | bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const { | |||
13220 | if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) | |||
13221 | return false; | |||
13222 | ||||
13223 | if (!isTypeLegal(EVT::getEVT(Ty1))) | |||
13224 | return false; | |||
13225 | ||||
13226 | assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop")((Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop" ) ? static_cast<void> (0) : __assert_fail ("Ty1->getPrimitiveSizeInBits() <= 64 && \"i128 is probably not a noop\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13226, __PRETTY_FUNCTION__)); | |||
13227 | ||||
13228 | // Assuming the caller doesn't have a zeroext or signext return parameter, | |||
13229 | // truncation all the way down to i1 is valid. | |||
13230 | return true; | |||
13231 | } | |||
13232 | ||||
13233 | int ARMTargetLowering::getScalingFactorCost(const DataLayout &DL, | |||
13234 | const AddrMode &AM, Type *Ty, | |||
13235 | unsigned AS) const { | |||
13236 | if (isLegalAddressingMode(DL, AM, Ty, AS)) { | |||
13237 | if (Subtarget->hasFPAO()) | |||
13238 | return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster | |||
13239 | return 0; | |||
13240 | } | |||
13241 | return -1; | |||
13242 | } | |||
13243 | ||||
13244 | static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { | |||
13245 | if (V < 0) | |||
13246 | return false; | |||
13247 | ||||
13248 | unsigned Scale = 1; | |||
13249 | switch (VT.getSimpleVT().SimpleTy) { | |||
13250 | default: return false; | |||
13251 | case MVT::i1: | |||
13252 | case MVT::i8: | |||
13253 | // Scale == 1; | |||
13254 | break; | |||
13255 | case MVT::i16: | |||
13256 | // Scale == 2; | |||
13257 | Scale = 2; | |||
13258 | break; | |||
13259 | case MVT::i32: | |||
13260 | // Scale == 4; | |||
13261 | Scale = 4; | |||
13262 | break; | |||
13263 | } | |||
13264 | ||||
13265 | if ((V & (Scale - 1)) != 0) | |||
13266 | return false; | |||
13267 | return isUInt<5>(V / Scale); | |||
13268 | } | |||
13269 | ||||
13270 | static bool isLegalT2AddressImmediate(int64_t V, EVT VT, | |||
13271 | const ARMSubtarget *Subtarget) { | |||
13272 | if (!VT.isInteger() && !VT.isFloatingPoint()) | |||
13273 | return false; | |||
13274 | if (Subtarget->hasNEON() && VT.isVector()) | |||
13275 | return false; | |||
13276 | ||||
13277 | bool IsNeg = false; | |||
13278 | if (V < 0) { | |||
13279 | IsNeg = true; | |||
13280 | V = -V; | |||
13281 | } | |||
13282 | ||||
13283 | unsigned NumBytes = std::max(VT.getSizeInBits() / 8, 1U); | |||
13284 | ||||
13285 | // VLDR and LDRD: 4 * imm8 | |||
13286 | if ((VT.isFloatingPoint() && Subtarget->hasVFP2()) || NumBytes == 8) | |||
13287 | return isShiftedUInt<8, 2>(V); | |||
13288 | ||||
13289 | if (NumBytes == 1 || NumBytes == 2 || NumBytes == 4) { | |||
13290 | // + imm12 or - imm8 | |||
13291 | if (IsNeg) | |||
13292 | return isUInt<8>(V); | |||
13293 | return isUInt<12>(V); | |||
13294 | } | |||
13295 | ||||
13296 | return false; | |||
13297 | } | |||
13298 | ||||
13299 | /// isLegalAddressImmediate - Return true if the integer value can be used | |||
13300 | /// as the offset of the target addressing mode for load / store of the | |||
13301 | /// given type. | |||
13302 | static bool isLegalAddressImmediate(int64_t V, EVT VT, | |||
13303 | const ARMSubtarget *Subtarget) { | |||
13304 | if (V == 0) | |||
13305 | return true; | |||
13306 | ||||
13307 | if (!VT.isSimple()) | |||
13308 | return false; | |||
13309 | ||||
13310 | if (Subtarget->isThumb1Only()) | |||
13311 | return isLegalT1AddressImmediate(V, VT); | |||
13312 | else if (Subtarget->isThumb2()) | |||
13313 | return isLegalT2AddressImmediate(V, VT, Subtarget); | |||
13314 | ||||
13315 | // ARM mode. | |||
13316 | if (V < 0) | |||
13317 | V = - V; | |||
13318 | switch (VT.getSimpleVT().SimpleTy) { | |||
13319 | default: return false; | |||
13320 | case MVT::i1: | |||
13321 | case MVT::i8: | |||
13322 | case MVT::i32: | |||
13323 | // +- imm12 | |||
13324 | return isUInt<12>(V); | |||
13325 | case MVT::i16: | |||
13326 | // +- imm8 | |||
13327 | return isUInt<8>(V); | |||
13328 | case MVT::f32: | |||
13329 | case MVT::f64: | |||
13330 | if (!Subtarget->hasVFP2()) // FIXME: NEON? | |||
13331 | return false; | |||
13332 | return isShiftedUInt<8, 2>(V); | |||
13333 | } | |||
13334 | } | |||
13335 | ||||
13336 | bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, | |||
13337 | EVT VT) const { | |||
13338 | int Scale = AM.Scale; | |||
13339 | if (Scale < 0) | |||
13340 | return false; | |||
13341 | ||||
13342 | switch (VT.getSimpleVT().SimpleTy) { | |||
13343 | default: return false; | |||
13344 | case MVT::i1: | |||
13345 | case MVT::i8: | |||
13346 | case MVT::i16: | |||
13347 | case MVT::i32: | |||
13348 | if (Scale == 1) | |||
13349 | return true; | |||
13350 | // r + r << imm | |||
13351 | Scale = Scale & ~1; | |||
13352 | return Scale == 2 || Scale == 4 || Scale == 8; | |||
13353 | case MVT::i64: | |||
13354 | // FIXME: What are we trying to model here? ldrd doesn't have an r + r | |||
13355 | // version in Thumb mode. | |||
13356 | // r + r | |||
13357 | if (Scale == 1) | |||
13358 | return true; | |||
13359 | // r * 2 (this can be lowered to r + r). | |||
13360 | if (!AM.HasBaseReg && Scale == 2) | |||
13361 | return true; | |||
13362 | return false; | |||
13363 | case MVT::isVoid: | |||
13364 | // Note, we allow "void" uses (basically, uses that aren't loads or | |||
13365 | // stores), because arm allows folding a scale into many arithmetic | |||
13366 | // operations. This should be made more precise and revisited later. | |||
13367 | ||||
13368 | // Allow r << imm, but the imm has to be a multiple of two. | |||
13369 | if (Scale & 1) return false; | |||
13370 | return isPowerOf2_32(Scale); | |||
13371 | } | |||
13372 | } | |||
13373 | ||||
13374 | bool ARMTargetLowering::isLegalT1ScaledAddressingMode(const AddrMode &AM, | |||
13375 | EVT VT) const { | |||
13376 | const int Scale = AM.Scale; | |||
13377 | ||||
13378 | // Negative scales are not supported in Thumb1. | |||
13379 | if (Scale < 0) | |||
13380 | return false; | |||
13381 | ||||
13382 | // Thumb1 addressing modes do not support register scaling excepting the | |||
13383 | // following cases: | |||
13384 | // 1. Scale == 1 means no scaling. | |||
13385 | // 2. Scale == 2 this can be lowered to r + r if there is no base register. | |||
13386 | return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); | |||
13387 | } | |||
13388 | ||||
13389 | /// isLegalAddressingMode - Return true if the addressing mode represented | |||
13390 | /// by AM is legal for this target, for a load/store of the specified type. | |||
13391 | bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL, | |||
13392 | const AddrMode &AM, Type *Ty, | |||
13393 | unsigned AS, Instruction *I) const { | |||
13394 | EVT VT = getValueType(DL, Ty, true); | |||
13395 | if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) | |||
13396 | return false; | |||
13397 | ||||
13398 | // Can never fold addr of global into load/store. | |||
13399 | if (AM.BaseGV) | |||
13400 | return false; | |||
13401 | ||||
13402 | switch (AM.Scale) { | |||
13403 | case 0: // no scale reg, must be "r+i" or "r", or "i". | |||
13404 | break; | |||
13405 | default: | |||
13406 | // ARM doesn't support any R+R*scale+imm addr modes. | |||
13407 | if (AM.BaseOffs) | |||
13408 | return false; | |||
13409 | ||||
13410 | if (!VT.isSimple()) | |||
13411 | return false; | |||
13412 | ||||
13413 | if (Subtarget->isThumb1Only()) | |||
13414 | return isLegalT1ScaledAddressingMode(AM, VT); | |||
13415 | ||||
13416 | if (Subtarget->isThumb2()) | |||
13417 | return isLegalT2ScaledAddressingMode(AM, VT); | |||
13418 | ||||
13419 | int Scale = AM.Scale; | |||
13420 | switch (VT.getSimpleVT().SimpleTy) { | |||
13421 | default: return false; | |||
13422 | case MVT::i1: | |||
13423 | case MVT::i8: | |||
13424 | case MVT::i32: | |||
13425 | if (Scale < 0) Scale = -Scale; | |||
13426 | if (Scale == 1) | |||
13427 | return true; | |||
13428 | // r + r << imm | |||
13429 | return isPowerOf2_32(Scale & ~1); | |||
13430 | case MVT::i16: | |||
13431 | case MVT::i64: | |||
13432 | // r +/- r | |||
13433 | if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) | |||
13434 | return true; | |||
13435 | // r * 2 (this can be lowered to r + r). | |||
13436 | if (!AM.HasBaseReg && Scale == 2) | |||
13437 | return true; | |||
13438 | return false; | |||
13439 | ||||
13440 | case MVT::isVoid: | |||
13441 | // Note, we allow "void" uses (basically, uses that aren't loads or | |||
13442 | // stores), because arm allows folding a scale into many arithmetic | |||
13443 | // operations. This should be made more precise and revisited later. | |||
13444 | ||||
13445 | // Allow r << imm, but the imm has to be a multiple of two. | |||
13446 | if (Scale & 1) return false; | |||
13447 | return isPowerOf2_32(Scale); | |||
13448 | } | |||
13449 | } | |||
13450 | return true; | |||
13451 | } | |||
13452 | ||||
13453 | /// isLegalICmpImmediate - Return true if the specified immediate is legal | |||
13454 | /// icmp immediate, that is the target has icmp instructions which can compare | |||
13455 | /// a register against the immediate without having to materialize the | |||
13456 | /// immediate into a register. | |||
13457 | bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { | |||
13458 | // Thumb2 and ARM modes can use cmn for negative immediates. | |||
13459 | if (!Subtarget->isThumb()) | |||
13460 | return ARM_AM::getSOImmVal((uint32_t)Imm) != -1 || | |||
13461 | ARM_AM::getSOImmVal(-(uint32_t)Imm) != -1; | |||
13462 | if (Subtarget->isThumb2()) | |||
13463 | return ARM_AM::getT2SOImmVal((uint32_t)Imm) != -1 || | |||
13464 | ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; | |||
13465 | // Thumb1 doesn't have cmn, and only 8-bit immediates. | |||
13466 | return Imm >= 0 && Imm <= 255; | |||
13467 | } | |||
13468 | ||||
13469 | /// isLegalAddImmediate - Return true if the specified immediate is a legal add | |||
13470 | /// *or sub* immediate, that is the target has add or sub instructions which can | |||
13471 | /// add a register with the immediate without having to materialize the | |||
13472 | /// immediate into a register. | |||
13473 | bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { | |||
13474 | // Same encoding for add/sub, just flip the sign. | |||
13475 | int64_t AbsImm = std::abs(Imm); | |||
13476 | if (!Subtarget->isThumb()) | |||
13477 | return ARM_AM::getSOImmVal(AbsImm) != -1; | |||
13478 | if (Subtarget->isThumb2()) | |||
13479 | return ARM_AM::getT2SOImmVal(AbsImm) != -1; | |||
13480 | // Thumb1 only has 8-bit unsigned immediate. | |||
13481 | return AbsImm >= 0 && AbsImm <= 255; | |||
13482 | } | |||
13483 | ||||
13484 | static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, | |||
13485 | bool isSEXTLoad, SDValue &Base, | |||
13486 | SDValue &Offset, bool &isInc, | |||
13487 | SelectionDAG &DAG) { | |||
13488 | if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) | |||
13489 | return false; | |||
13490 | ||||
13491 | if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { | |||
13492 | // AddressingMode 3 | |||
13493 | Base = Ptr->getOperand(0); | |||
13494 | if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { | |||
13495 | int RHSC = (int)RHS->getZExtValue(); | |||
13496 | if (RHSC < 0 && RHSC > -256) { | |||
13497 | assert(Ptr->getOpcode() == ISD::ADD)((Ptr->getOpcode() == ISD::ADD) ? static_cast<void> ( 0) : __assert_fail ("Ptr->getOpcode() == ISD::ADD", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13497, __PRETTY_FUNCTION__)); | |||
13498 | isInc = false; | |||
13499 | Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); | |||
13500 | return true; | |||
13501 | } | |||
13502 | } | |||
13503 | isInc = (Ptr->getOpcode() == ISD::ADD); | |||
13504 | Offset = Ptr->getOperand(1); | |||
13505 | return true; | |||
13506 | } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { | |||
13507 | // AddressingMode 2 | |||
13508 | if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { | |||
13509 | int RHSC = (int)RHS->getZExtValue(); | |||
13510 | if (RHSC < 0 && RHSC > -0x1000) { | |||
13511 | assert(Ptr->getOpcode() == ISD::ADD)((Ptr->getOpcode() == ISD::ADD) ? static_cast<void> ( 0) : __assert_fail ("Ptr->getOpcode() == ISD::ADD", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13511, __PRETTY_FUNCTION__)); | |||
13512 | isInc = false; | |||
13513 | Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); | |||
13514 | Base = Ptr->getOperand(0); | |||
13515 | return true; | |||
13516 | } | |||
13517 | } | |||
13518 | ||||
13519 | if (Ptr->getOpcode() == ISD::ADD) { | |||
13520 | isInc = true; | |||
13521 | ARM_AM::ShiftOpc ShOpcVal= | |||
13522 | ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); | |||
13523 | if (ShOpcVal != ARM_AM::no_shift) { | |||
13524 | Base = Ptr->getOperand(1); | |||
13525 | Offset = Ptr->getOperand(0); | |||
13526 | } else { | |||
13527 | Base = Ptr->getOperand(0); | |||
13528 | Offset = Ptr->getOperand(1); | |||
13529 | } | |||
13530 | return true; | |||
13531 | } | |||
13532 | ||||
13533 | isInc = (Ptr->getOpcode() == ISD::ADD); | |||
13534 | Base = Ptr->getOperand(0); | |||
13535 | Offset = Ptr->getOperand(1); | |||
13536 | return true; | |||
13537 | } | |||
13538 | ||||
13539 | // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. | |||
13540 | return false; | |||
13541 | } | |||
13542 | ||||
13543 | static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, | |||
13544 | bool isSEXTLoad, SDValue &Base, | |||
13545 | SDValue &Offset, bool &isInc, | |||
13546 | SelectionDAG &DAG) { | |||
13547 | if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) | |||
13548 | return false; | |||
13549 | ||||
13550 | Base = Ptr->getOperand(0); | |||
13551 | if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { | |||
13552 | int RHSC = (int)RHS->getZExtValue(); | |||
13553 | if (RHSC < 0 && RHSC > -0x100) { // 8 bits. | |||
13554 | assert(Ptr->getOpcode() == ISD::ADD)((Ptr->getOpcode() == ISD::ADD) ? static_cast<void> ( 0) : __assert_fail ("Ptr->getOpcode() == ISD::ADD", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13554, __PRETTY_FUNCTION__)); | |||
13555 | isInc = false; | |||
13556 | Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); | |||
13557 | return true; | |||
13558 | } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. | |||
13559 | isInc = Ptr->getOpcode() == ISD::ADD; | |||
13560 | Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0)); | |||
13561 | return true; | |||
13562 | } | |||
13563 | } | |||
13564 | ||||
13565 | return false; | |||
13566 | } | |||
13567 | ||||
13568 | /// getPreIndexedAddressParts - returns true by value, base pointer and | |||
13569 | /// offset pointer and addressing mode by reference if the node's address | |||
13570 | /// can be legally represented as pre-indexed load / store address. | |||
13571 | bool | |||
13572 | ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, | |||
13573 | SDValue &Offset, | |||
13574 | ISD::MemIndexedMode &AM, | |||
13575 | SelectionDAG &DAG) const { | |||
13576 | if (Subtarget->isThumb1Only()) | |||
13577 | return false; | |||
13578 | ||||
13579 | EVT VT; | |||
13580 | SDValue Ptr; | |||
13581 | bool isSEXTLoad = false; | |||
13582 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { | |||
13583 | Ptr = LD->getBasePtr(); | |||
13584 | VT = LD->getMemoryVT(); | |||
13585 | isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; | |||
13586 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { | |||
13587 | Ptr = ST->getBasePtr(); | |||
13588 | VT = ST->getMemoryVT(); | |||
13589 | } else | |||
13590 | return false; | |||
13591 | ||||
13592 | bool isInc; | |||
13593 | bool isLegal = false; | |||
13594 | if (Subtarget->isThumb2()) | |||
13595 | isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, | |||
13596 | Offset, isInc, DAG); | |||
13597 | else | |||
13598 | isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, | |||
13599 | Offset, isInc, DAG); | |||
13600 | if (!isLegal) | |||
13601 | return false; | |||
13602 | ||||
13603 | AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; | |||
13604 | return true; | |||
13605 | } | |||
13606 | ||||
13607 | /// getPostIndexedAddressParts - returns true by value, base pointer and | |||
13608 | /// offset pointer and addressing mode by reference if this node can be | |||
13609 | /// combined with a load / store to form a post-indexed load / store. | |||
13610 | bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, | |||
13611 | SDValue &Base, | |||
13612 | SDValue &Offset, | |||
13613 | ISD::MemIndexedMode &AM, | |||
13614 | SelectionDAG &DAG) const { | |||
13615 | EVT VT; | |||
13616 | SDValue Ptr; | |||
13617 | bool isSEXTLoad = false, isNonExt; | |||
13618 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { | |||
13619 | VT = LD->getMemoryVT(); | |||
13620 | Ptr = LD->getBasePtr(); | |||
13621 | isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; | |||
13622 | isNonExt = LD->getExtensionType() == ISD::NON_EXTLOAD; | |||
13623 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { | |||
13624 | VT = ST->getMemoryVT(); | |||
13625 | Ptr = ST->getBasePtr(); | |||
13626 | isNonExt = !ST->isTruncatingStore(); | |||
13627 | } else | |||
13628 | return false; | |||
13629 | ||||
13630 | if (Subtarget->isThumb1Only()) { | |||
13631 | // Thumb-1 can do a limited post-inc load or store as an updating LDM. It | |||
13632 | // must be non-extending/truncating, i32, with an offset of 4. | |||
13633 | assert(Op->getValueType(0) == MVT::i32 && "Non-i32 post-inc op?!")((Op->getValueType(0) == MVT::i32 && "Non-i32 post-inc op?!" ) ? static_cast<void> (0) : __assert_fail ("Op->getValueType(0) == MVT::i32 && \"Non-i32 post-inc op?!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13633, __PRETTY_FUNCTION__)); | |||
13634 | if (Op->getOpcode() != ISD::ADD || !isNonExt) | |||
13635 | return false; | |||
13636 | auto *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1)); | |||
13637 | if (!RHS || RHS->getZExtValue() != 4) | |||
13638 | return false; | |||
13639 | ||||
13640 | Offset = Op->getOperand(1); | |||
13641 | Base = Op->getOperand(0); | |||
13642 | AM = ISD::POST_INC; | |||
13643 | return true; | |||
13644 | } | |||
13645 | ||||
13646 | bool isInc; | |||
13647 | bool isLegal = false; | |||
13648 | if (Subtarget->isThumb2()) | |||
13649 | isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, | |||
13650 | isInc, DAG); | |||
13651 | else | |||
13652 | isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, | |||
13653 | isInc, DAG); | |||
13654 | if (!isLegal) | |||
13655 | return false; | |||
13656 | ||||
13657 | if (Ptr != Base) { | |||
13658 | // Swap base ptr and offset to catch more post-index load / store when | |||
13659 | // it's legal. In Thumb2 mode, offset must be an immediate. | |||
13660 | if (Ptr == Offset && Op->getOpcode() == ISD::ADD && | |||
13661 | !Subtarget->isThumb2()) | |||
13662 | std::swap(Base, Offset); | |||
13663 | ||||
13664 | // Post-indexed load / store update the base pointer. | |||
13665 | if (Ptr != Base) | |||
13666 | return false; | |||
13667 | } | |||
13668 | ||||
13669 | AM = isInc ? ISD::POST_INC : ISD::POST_DEC; | |||
13670 | return true; | |||
13671 | } | |||
13672 | ||||
13673 | void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, | |||
13674 | KnownBits &Known, | |||
13675 | const APInt &DemandedElts, | |||
13676 | const SelectionDAG &DAG, | |||
13677 | unsigned Depth) const { | |||
13678 | unsigned BitWidth = Known.getBitWidth(); | |||
13679 | Known.resetAll(); | |||
13680 | switch (Op.getOpcode()) { | |||
13681 | default: break; | |||
13682 | case ARMISD::ADDC: | |||
13683 | case ARMISD::ADDE: | |||
13684 | case ARMISD::SUBC: | |||
13685 | case ARMISD::SUBE: | |||
13686 | // Special cases when we convert a carry to a boolean. | |||
13687 | if (Op.getResNo() == 0) { | |||
13688 | SDValue LHS = Op.getOperand(0); | |||
13689 | SDValue RHS = Op.getOperand(1); | |||
13690 | // (ADDE 0, 0, C) will give us a single bit. | |||
13691 | if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) && | |||
13692 | isNullConstant(RHS)) { | |||
13693 | Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); | |||
13694 | return; | |||
13695 | } | |||
13696 | } | |||
13697 | break; | |||
13698 | case ARMISD::CMOV: { | |||
13699 | // Bits are known zero/one if known on the LHS and RHS. | |||
13700 | Known = DAG.computeKnownBits(Op.getOperand(0), Depth+1); | |||
13701 | if (Known.isUnknown()) | |||
13702 | return; | |||
13703 | ||||
13704 | KnownBits KnownRHS = DAG.computeKnownBits(Op.getOperand(1), Depth+1); | |||
13705 | Known.Zero &= KnownRHS.Zero; | |||
13706 | Known.One &= KnownRHS.One; | |||
13707 | return; | |||
13708 | } | |||
13709 | case ISD::INTRINSIC_W_CHAIN: { | |||
13710 | ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1)); | |||
13711 | Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); | |||
13712 | switch (IntID) { | |||
13713 | default: return; | |||
13714 | case Intrinsic::arm_ldaex: | |||
13715 | case Intrinsic::arm_ldrex: { | |||
13716 | EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); | |||
13717 | unsigned MemBits = VT.getScalarSizeInBits(); | |||
13718 | Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits); | |||
13719 | return; | |||
13720 | } | |||
13721 | } | |||
13722 | } | |||
13723 | case ARMISD::BFI: { | |||
13724 | // Conservatively, we can recurse down the first operand | |||
13725 | // and just mask out all affected bits. | |||
13726 | Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1); | |||
13727 | ||||
13728 | // The operand to BFI is already a mask suitable for removing the bits it | |||
13729 | // sets. | |||
13730 | ConstantSDNode *CI = cast<ConstantSDNode>(Op.getOperand(2)); | |||
13731 | const APInt &Mask = CI->getAPIntValue(); | |||
13732 | Known.Zero &= Mask; | |||
13733 | Known.One &= Mask; | |||
13734 | return; | |||
13735 | } | |||
13736 | case ARMISD::VGETLANEs: | |||
13737 | case ARMISD::VGETLANEu: { | |||
13738 | const SDValue &SrcSV = Op.getOperand(0); | |||
13739 | EVT VecVT = SrcSV.getValueType(); | |||
13740 | assert(VecVT.isVector() && "VGETLANE expected a vector type")((VecVT.isVector() && "VGETLANE expected a vector type" ) ? static_cast<void> (0) : __assert_fail ("VecVT.isVector() && \"VGETLANE expected a vector type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13740, __PRETTY_FUNCTION__)); | |||
13741 | const unsigned NumSrcElts = VecVT.getVectorNumElements(); | |||
13742 | ConstantSDNode *Pos = cast<ConstantSDNode>(Op.getOperand(1).getNode()); | |||
13743 | assert(Pos->getAPIntValue().ult(NumSrcElts) &&((Pos->getAPIntValue().ult(NumSrcElts) && "VGETLANE index out of bounds" ) ? static_cast<void> (0) : __assert_fail ("Pos->getAPIntValue().ult(NumSrcElts) && \"VGETLANE index out of bounds\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13744, __PRETTY_FUNCTION__)) | |||
13744 | "VGETLANE index out of bounds")((Pos->getAPIntValue().ult(NumSrcElts) && "VGETLANE index out of bounds" ) ? static_cast<void> (0) : __assert_fail ("Pos->getAPIntValue().ult(NumSrcElts) && \"VGETLANE index out of bounds\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13744, __PRETTY_FUNCTION__)); | |||
13745 | unsigned Idx = Pos->getZExtValue(); | |||
13746 | APInt DemandedElt = APInt::getOneBitSet(NumSrcElts, Idx); | |||
13747 | Known = DAG.computeKnownBits(SrcSV, DemandedElt, Depth + 1); | |||
13748 | ||||
13749 | EVT VT = Op.getValueType(); | |||
13750 | const unsigned DstSz = VT.getScalarSizeInBits(); | |||
13751 | const unsigned SrcSz = VecVT.getVectorElementType().getSizeInBits(); | |||
13752 | (void)SrcSz; | |||
13753 | assert(SrcSz == Known.getBitWidth())((SrcSz == Known.getBitWidth()) ? static_cast<void> (0) : __assert_fail ("SrcSz == Known.getBitWidth()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13753, __PRETTY_FUNCTION__)); | |||
13754 | assert(DstSz > SrcSz)((DstSz > SrcSz) ? static_cast<void> (0) : __assert_fail ("DstSz > SrcSz", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13754, __PRETTY_FUNCTION__)); | |||
13755 | if (Op.getOpcode() == ARMISD::VGETLANEs) | |||
13756 | Known = Known.sext(DstSz); | |||
13757 | else { | |||
13758 | Known = Known.zext(DstSz, true /* extended bits are known zero */); | |||
13759 | } | |||
13760 | assert(DstSz == Known.getBitWidth())((DstSz == Known.getBitWidth()) ? static_cast<void> (0) : __assert_fail ("DstSz == Known.getBitWidth()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13760, __PRETTY_FUNCTION__)); | |||
13761 | break; | |||
13762 | } | |||
13763 | } | |||
13764 | } | |||
13765 | ||||
13766 | bool | |||
13767 | ARMTargetLowering::targetShrinkDemandedConstant(SDValue Op, | |||
13768 | const APInt &DemandedAPInt, | |||
13769 | TargetLoweringOpt &TLO) const { | |||
13770 | // Delay optimization, so we don't have to deal with illegal types, or block | |||
13771 | // optimizations. | |||
13772 | if (!TLO.LegalOps) | |||
13773 | return false; | |||
13774 | ||||
13775 | // Only optimize AND for now. | |||
13776 | if (Op.getOpcode() != ISD::AND) | |||
13777 | return false; | |||
13778 | ||||
13779 | EVT VT = Op.getValueType(); | |||
13780 | ||||
13781 | // Ignore vectors. | |||
13782 | if (VT.isVector()) | |||
13783 | return false; | |||
13784 | ||||
13785 | assert(VT == MVT::i32 && "Unexpected integer type")((VT == MVT::i32 && "Unexpected integer type") ? static_cast <void> (0) : __assert_fail ("VT == MVT::i32 && \"Unexpected integer type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 13785, __PRETTY_FUNCTION__)); | |||
13786 | ||||
13787 | // Make sure the RHS really is a constant. | |||
13788 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | |||
13789 | if (!C) | |||
13790 | return false; | |||
13791 | ||||
13792 | unsigned Mask = C->getZExtValue(); | |||
13793 | ||||
13794 | unsigned Demanded = DemandedAPInt.getZExtValue(); | |||
13795 | unsigned ShrunkMask = Mask & Demanded; | |||
13796 | unsigned ExpandedMask = Mask | ~Demanded; | |||
13797 | ||||
13798 | // If the mask is all zeros, let the target-independent code replace the | |||
13799 | // result with zero. | |||
13800 | if (ShrunkMask == 0) | |||
13801 | return false; | |||
13802 | ||||
13803 | // If the mask is all ones, erase the AND. (Currently, the target-independent | |||
13804 | // code won't do this, so we have to do it explicitly to avoid an infinite | |||
13805 | // loop in obscure cases.) | |||
13806 | if (ExpandedMask == ~0U) | |||
13807 | return TLO.CombineTo(Op, Op.getOperand(0)); | |||
13808 | ||||
13809 | auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool { | |||
13810 | return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0; | |||
13811 | }; | |||
13812 | auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool { | |||
13813 | if (NewMask == Mask) | |||
13814 | return true; | |||
13815 | SDLoc DL(Op); | |||
13816 | SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT); | |||
13817 | SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC); | |||
13818 | return TLO.CombineTo(Op, NewOp); | |||
13819 | }; | |||
13820 | ||||
13821 | // Prefer uxtb mask. | |||
13822 | if (IsLegalMask(0xFF)) | |||
13823 | return UseMask(0xFF); | |||
13824 | ||||
13825 | // Prefer uxth mask. | |||
13826 | if (IsLegalMask(0xFFFF)) | |||
13827 | return UseMask(0xFFFF); | |||
13828 | ||||
13829 | // [1, 255] is Thumb1 movs+ands, legal immediate for ARM/Thumb2. | |||
13830 | // FIXME: Prefer a contiguous sequence of bits for other optimizations. | |||
13831 | if (ShrunkMask < 256) | |||
13832 | return UseMask(ShrunkMask); | |||
13833 | ||||
13834 | // [-256, -2] is Thumb1 movs+bics, legal immediate for ARM/Thumb2. | |||
13835 | // FIXME: Prefer a contiguous sequence of bits for other optimizations. | |||
13836 | if ((int)ExpandedMask <= -2 && (int)ExpandedMask >= -256) | |||
13837 | return UseMask(ExpandedMask); | |||
13838 | ||||
13839 | // Potential improvements: | |||
13840 | // | |||
13841 | // We could try to recognize lsls+lsrs or lsrs+lsls pairs here. | |||
13842 | // We could try to prefer Thumb1 immediates which can be lowered to a | |||
13843 | // two-instruction sequence. | |||
13844 | // We could try to recognize more legal ARM/Thumb2 immediates here. | |||
13845 | ||||
13846 | return false; | |||
13847 | } | |||
13848 | ||||
13849 | ||||
13850 | //===----------------------------------------------------------------------===// | |||
13851 | // ARM Inline Assembly Support | |||
13852 | //===----------------------------------------------------------------------===// | |||
13853 | ||||
13854 | bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { | |||
13855 | // Looking for "rev" which is V6+. | |||
13856 | if (!Subtarget->hasV6Ops()) | |||
13857 | return false; | |||
13858 | ||||
13859 | InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); | |||
13860 | std::string AsmStr = IA->getAsmString(); | |||
13861 | SmallVector<StringRef, 4> AsmPieces; | |||
13862 | SplitString(AsmStr, AsmPieces, ";\n"); | |||
13863 | ||||
13864 | switch (AsmPieces.size()) { | |||
13865 | default: return false; | |||
13866 | case 1: | |||
13867 | AsmStr = AsmPieces[0]; | |||
13868 | AsmPieces.clear(); | |||
13869 | SplitString(AsmStr, AsmPieces, " \t,"); | |||
13870 | ||||
13871 | // rev $0, $1 | |||
13872 | if (AsmPieces.size() == 3 && | |||
13873 | AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && | |||
13874 | IA->getConstraintString().compare(0, 4, "=l,l") == 0) { | |||
13875 | IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); | |||
13876 | if (Ty && Ty->getBitWidth() == 32) | |||
13877 | return IntrinsicLowering::LowerToByteSwap(CI); | |||
13878 | } | |||
13879 | break; | |||
13880 | } | |||
13881 | ||||
13882 | return false; | |||
13883 | } | |||
13884 | ||||
13885 | const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const { | |||
13886 | // At this point, we have to lower this constraint to something else, so we | |||
13887 | // lower it to an "r" or "w". However, by doing this we will force the result | |||
13888 | // to be in register, while the X constraint is much more permissive. | |||
13889 | // | |||
13890 | // Although we are correct (we are free to emit anything, without | |||
13891 | // constraints), we might break use cases that would expect us to be more | |||
13892 | // efficient and emit something else. | |||
13893 | if (!Subtarget->hasVFP2()) | |||
13894 | return "r"; | |||
13895 | if (ConstraintVT.isFloatingPoint()) | |||
13896 | return "w"; | |||
13897 | if (ConstraintVT.isVector() && Subtarget->hasNEON() && | |||
13898 | (ConstraintVT.getSizeInBits() == 64 || | |||
13899 | ConstraintVT.getSizeInBits() == 128)) | |||
13900 | return "w"; | |||
13901 | ||||
13902 | return "r"; | |||
13903 | } | |||
13904 | ||||
13905 | /// getConstraintType - Given a constraint letter, return the type of | |||
13906 | /// constraint it is for this target. | |||
13907 | ARMTargetLowering::ConstraintType | |||
13908 | ARMTargetLowering::getConstraintType(StringRef Constraint) const { | |||
13909 | if (Constraint.size() == 1) { | |||
13910 | switch (Constraint[0]) { | |||
13911 | default: break; | |||
13912 | case 'l': return C_RegisterClass; | |||
13913 | case 'w': return C_RegisterClass; | |||
13914 | case 'h': return C_RegisterClass; | |||
13915 | case 'x': return C_RegisterClass; | |||
13916 | case 't': return C_RegisterClass; | |||
13917 | case 'j': return C_Other; // Constant for movw. | |||
13918 | // An address with a single base register. Due to the way we | |||
13919 | // currently handle addresses it is the same as an 'r' memory constraint. | |||
13920 | case 'Q': return C_Memory; | |||
13921 | } | |||
13922 | } else if (Constraint.size() == 2) { | |||
13923 | switch (Constraint[0]) { | |||
13924 | default: break; | |||
13925 | // All 'U+' constraints are addresses. | |||
13926 | case 'U': return C_Memory; | |||
13927 | } | |||
13928 | } | |||
13929 | return TargetLowering::getConstraintType(Constraint); | |||
13930 | } | |||
13931 | ||||
13932 | /// Examine constraint type and operand type and determine a weight value. | |||
13933 | /// This object must already have been set up with the operand type | |||
13934 | /// and the current alternative constraint selected. | |||
13935 | TargetLowering::ConstraintWeight | |||
13936 | ARMTargetLowering::getSingleConstraintMatchWeight( | |||
13937 | AsmOperandInfo &info, const char *constraint) const { | |||
13938 | ConstraintWeight weight = CW_Invalid; | |||
13939 | Value *CallOperandVal = info.CallOperandVal; | |||
13940 | // If we don't have a value, we can't do a match, | |||
13941 | // but allow it at the lowest weight. | |||
13942 | if (!CallOperandVal) | |||
13943 | return CW_Default; | |||
13944 | Type *type = CallOperandVal->getType(); | |||
13945 | // Look at the constraint type. | |||
13946 | switch (*constraint) { | |||
13947 | default: | |||
13948 | weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); | |||
13949 | break; | |||
13950 | case 'l': | |||
13951 | if (type->isIntegerTy()) { | |||
13952 | if (Subtarget->isThumb()) | |||
13953 | weight = CW_SpecificReg; | |||
13954 | else | |||
13955 | weight = CW_Register; | |||
13956 | } | |||
13957 | break; | |||
13958 | case 'w': | |||
13959 | if (type->isFloatingPointTy()) | |||
13960 | weight = CW_Register; | |||
13961 | break; | |||
13962 | } | |||
13963 | return weight; | |||
13964 | } | |||
13965 | ||||
13966 | using RCPair = std::pair<unsigned, const TargetRegisterClass *>; | |||
13967 | ||||
13968 | RCPair ARMTargetLowering::getRegForInlineAsmConstraint( | |||
13969 | const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { | |||
13970 | if (Constraint.size() == 1) { | |||
13971 | // GCC ARM Constraint Letters | |||
13972 | switch (Constraint[0]) { | |||
13973 | case 'l': // Low regs or general regs. | |||
13974 | if (Subtarget->isThumb()) | |||
13975 | return RCPair(0U, &ARM::tGPRRegClass); | |||
13976 | return RCPair(0U, &ARM::GPRRegClass); | |||
13977 | case 'h': // High regs or no regs. | |||
13978 | if (Subtarget->isThumb()) | |||
13979 | return RCPair(0U, &ARM::hGPRRegClass); | |||
13980 | break; | |||
13981 | case 'r': | |||
13982 | if (Subtarget->isThumb1Only()) | |||
13983 | return RCPair(0U, &ARM::tGPRRegClass); | |||
13984 | return RCPair(0U, &ARM::GPRRegClass); | |||
13985 | case 'w': | |||
13986 | if (VT == MVT::Other) | |||
13987 | break; | |||
13988 | if (VT == MVT::f32) | |||
13989 | return RCPair(0U, &ARM::SPRRegClass); | |||
13990 | if (VT.getSizeInBits() == 64) | |||
13991 | return RCPair(0U, &ARM::DPRRegClass); | |||
13992 | if (VT.getSizeInBits() == 128) | |||
13993 | return RCPair(0U, &ARM::QPRRegClass); | |||
13994 | break; | |||
13995 | case 'x': | |||
13996 | if (VT == MVT::Other) | |||
13997 | break; | |||
13998 | if (VT == MVT::f32) | |||
13999 | return RCPair(0U, &ARM::SPR_8RegClass); | |||
14000 | if (VT.getSizeInBits() == 64) | |||
14001 | return RCPair(0U, &ARM::DPR_8RegClass); | |||
14002 | if (VT.getSizeInBits() == 128) | |||
14003 | return RCPair(0U, &ARM::QPR_8RegClass); | |||
14004 | break; | |||
14005 | case 't': | |||
14006 | if (VT == MVT::Other) | |||
14007 | break; | |||
14008 | if (VT == MVT::f32 || VT == MVT::i32) | |||
14009 | return RCPair(0U, &ARM::SPRRegClass); | |||
14010 | if (VT.getSizeInBits() == 64) | |||
14011 | return RCPair(0U, &ARM::DPR_VFP2RegClass); | |||
14012 | if (VT.getSizeInBits() == 128) | |||
14013 | return RCPair(0U, &ARM::QPR_VFP2RegClass); | |||
14014 | break; | |||
14015 | } | |||
14016 | } | |||
14017 | if (StringRef("{cc}").equals_lower(Constraint)) | |||
14018 | return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass); | |||
14019 | ||||
14020 | return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); | |||
14021 | } | |||
14022 | ||||
14023 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops | |||
14024 | /// vector. If it is invalid, don't add anything to Ops. | |||
14025 | void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, | |||
14026 | std::string &Constraint, | |||
14027 | std::vector<SDValue>&Ops, | |||
14028 | SelectionDAG &DAG) const { | |||
14029 | SDValue Result; | |||
14030 | ||||
14031 | // Currently only support length 1 constraints. | |||
14032 | if (Constraint.length() != 1) return; | |||
14033 | ||||
14034 | char ConstraintLetter = Constraint[0]; | |||
14035 | switch (ConstraintLetter) { | |||
14036 | default: break; | |||
14037 | case 'j': | |||
14038 | case 'I': case 'J': case 'K': case 'L': | |||
14039 | case 'M': case 'N': case 'O': | |||
14040 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); | |||
14041 | if (!C) | |||
14042 | return; | |||
14043 | ||||
14044 | int64_t CVal64 = C->getSExtValue(); | |||
14045 | int CVal = (int) CVal64; | |||
14046 | // None of these constraints allow values larger than 32 bits. Check | |||
14047 | // that the value fits in an int. | |||
14048 | if (CVal != CVal64) | |||
14049 | return; | |||
14050 | ||||
14051 | switch (ConstraintLetter) { | |||
14052 | case 'j': | |||
14053 | // Constant suitable for movw, must be between 0 and | |||
14054 | // 65535. | |||
14055 | if (Subtarget->hasV6T2Ops()) | |||
14056 | if (CVal >= 0 && CVal <= 65535) | |||
14057 | break; | |||
14058 | return; | |||
14059 | case 'I': | |||
14060 | if (Subtarget->isThumb1Only()) { | |||
14061 | // This must be a constant between 0 and 255, for ADD | |||
14062 | // immediates. | |||
14063 | if (CVal >= 0 && CVal <= 255) | |||
14064 | break; | |||
14065 | } else if (Subtarget->isThumb2()) { | |||
14066 | // A constant that can be used as an immediate value in a | |||
14067 | // data-processing instruction. | |||
14068 | if (ARM_AM::getT2SOImmVal(CVal) != -1) | |||
14069 | break; | |||
14070 | } else { | |||
14071 | // A constant that can be used as an immediate value in a | |||
14072 | // data-processing instruction. | |||
14073 | if (ARM_AM::getSOImmVal(CVal) != -1) | |||
14074 | break; | |||
14075 | } | |||
14076 | return; | |||
14077 | ||||
14078 | case 'J': | |||
14079 | if (Subtarget->isThumb1Only()) { | |||
14080 | // This must be a constant between -255 and -1, for negated ADD | |||
14081 | // immediates. This can be used in GCC with an "n" modifier that | |||
14082 | // prints the negated value, for use with SUB instructions. It is | |||
14083 | // not useful otherwise but is implemented for compatibility. | |||
14084 | if (CVal >= -255 && CVal <= -1) | |||
14085 | break; | |||
14086 | } else { | |||
14087 | // This must be a constant between -4095 and 4095. It is not clear | |||
14088 | // what this constraint is intended for. Implemented for | |||
14089 | // compatibility with GCC. | |||
14090 | if (CVal >= -4095 && CVal <= 4095) | |||
14091 | break; | |||
14092 | } | |||
14093 | return; | |||
14094 | ||||
14095 | case 'K': | |||
14096 | if (Subtarget->isThumb1Only()) { | |||
14097 | // A 32-bit value where only one byte has a nonzero value. Exclude | |||
14098 | // zero to match GCC. This constraint is used by GCC internally for | |||
14099 | // constants that can be loaded with a move/shift combination. | |||
14100 | // It is not useful otherwise but is implemented for compatibility. | |||
14101 | if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) | |||
14102 | break; | |||
14103 | } else if (Subtarget->isThumb2()) { | |||
14104 | // A constant whose bitwise inverse can be used as an immediate | |||
14105 | // value in a data-processing instruction. This can be used in GCC | |||
14106 | // with a "B" modifier that prints the inverted value, for use with | |||
14107 | // BIC and MVN instructions. It is not useful otherwise but is | |||
14108 | // implemented for compatibility. | |||
14109 | if (ARM_AM::getT2SOImmVal(~CVal) != -1) | |||
14110 | break; | |||
14111 | } else { | |||
14112 | // A constant whose bitwise inverse can be used as an immediate | |||
14113 | // value in a data-processing instruction. This can be used in GCC | |||
14114 | // with a "B" modifier that prints the inverted value, for use with | |||
14115 | // BIC and MVN instructions. It is not useful otherwise but is | |||
14116 | // implemented for compatibility. | |||
14117 | if (ARM_AM::getSOImmVal(~CVal) != -1) | |||
14118 | break; | |||
14119 | } | |||
14120 | return; | |||
14121 | ||||
14122 | case 'L': | |||
14123 | if (Subtarget->isThumb1Only()) { | |||
14124 | // This must be a constant between -7 and 7, | |||
14125 | // for 3-operand ADD/SUB immediate instructions. | |||
14126 | if (CVal >= -7 && CVal < 7) | |||
14127 | break; | |||
14128 | } else if (Subtarget->isThumb2()) { | |||
14129 | // A constant whose negation can be used as an immediate value in a | |||
14130 | // data-processing instruction. This can be used in GCC with an "n" | |||
14131 | // modifier that prints the negated value, for use with SUB | |||
14132 | // instructions. It is not useful otherwise but is implemented for | |||
14133 | // compatibility. | |||
14134 | if (ARM_AM::getT2SOImmVal(-CVal) != -1) | |||
14135 | break; | |||
14136 | } else { | |||
14137 | // A constant whose negation can be used as an immediate value in a | |||
14138 | // data-processing instruction. This can be used in GCC with an "n" | |||
14139 | // modifier that prints the negated value, for use with SUB | |||
14140 | // instructions. It is not useful otherwise but is implemented for | |||
14141 | // compatibility. | |||
14142 | if (ARM_AM::getSOImmVal(-CVal) != -1) | |||
14143 | break; | |||
14144 | } | |||
14145 | return; | |||
14146 | ||||
14147 | case 'M': | |||
14148 | if (Subtarget->isThumb1Only()) { | |||
14149 | // This must be a multiple of 4 between 0 and 1020, for | |||
14150 | // ADD sp + immediate. | |||
14151 | if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) | |||
14152 | break; | |||
14153 | } else { | |||
14154 | // A power of two or a constant between 0 and 32. This is used in | |||
14155 | // GCC for the shift amount on shifted register operands, but it is | |||
14156 | // useful in general for any shift amounts. | |||
14157 | if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) | |||
14158 | break; | |||
14159 | } | |||
14160 | return; | |||
14161 | ||||
14162 | case 'N': | |||
14163 | if (Subtarget->isThumb()) { // FIXME thumb2 | |||
14164 | // This must be a constant between 0 and 31, for shift amounts. | |||
14165 | if (CVal >= 0 && CVal <= 31) | |||
14166 | break; | |||
14167 | } | |||
14168 | return; | |||
14169 | ||||
14170 | case 'O': | |||
14171 | if (Subtarget->isThumb()) { // FIXME thumb2 | |||
14172 | // This must be a multiple of 4 between -508 and 508, for | |||
14173 | // ADD/SUB sp = sp + immediate. | |||
14174 | if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) | |||
14175 | break; | |||
14176 | } | |||
14177 | return; | |||
14178 | } | |||
14179 | Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType()); | |||
14180 | break; | |||
14181 | } | |||
14182 | ||||
14183 | if (Result.getNode()) { | |||
14184 | Ops.push_back(Result); | |||
14185 | return; | |||
14186 | } | |||
14187 | return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); | |||
14188 | } | |||
14189 | ||||
14190 | static RTLIB::Libcall getDivRemLibcall( | |||
14191 | const SDNode *N, MVT::SimpleValueType SVT) { | |||
14192 | assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemLibcall" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemLibcall\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14194, __PRETTY_FUNCTION__)) | |||
14193 | N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemLibcall" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemLibcall\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14194, __PRETTY_FUNCTION__)) | |||
14194 | "Unhandled Opcode in getDivRemLibcall")(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemLibcall" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemLibcall\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14194, __PRETTY_FUNCTION__)); | |||
14195 | bool isSigned = N->getOpcode() == ISD::SDIVREM || | |||
14196 | N->getOpcode() == ISD::SREM; | |||
14197 | RTLIB::Libcall LC; | |||
14198 | switch (SVT) { | |||
14199 | default: llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14199); | |||
14200 | case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; | |||
14201 | case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; | |||
14202 | case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; | |||
14203 | case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; | |||
14204 | } | |||
14205 | return LC; | |||
14206 | } | |||
14207 | ||||
14208 | static TargetLowering::ArgListTy getDivRemArgList( | |||
14209 | const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) { | |||
14210 | assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemArgList" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemArgList\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14212, __PRETTY_FUNCTION__)) | |||
14211 | N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemArgList" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemArgList\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14212, __PRETTY_FUNCTION__)) | |||
14212 | "Unhandled Opcode in getDivRemArgList")(((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD ::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode () == ISD::UREM) && "Unhandled Opcode in getDivRemArgList" ) ? static_cast<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && \"Unhandled Opcode in getDivRemArgList\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14212, __PRETTY_FUNCTION__)); | |||
14213 | bool isSigned = N->getOpcode() == ISD::SDIVREM || | |||
14214 | N->getOpcode() == ISD::SREM; | |||
14215 | TargetLowering::ArgListTy Args; | |||
14216 | TargetLowering::ArgListEntry Entry; | |||
14217 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { | |||
14218 | EVT ArgVT = N->getOperand(i).getValueType(); | |||
14219 | Type *ArgTy = ArgVT.getTypeForEVT(*Context); | |||
14220 | Entry.Node = N->getOperand(i); | |||
14221 | Entry.Ty = ArgTy; | |||
14222 | Entry.IsSExt = isSigned; | |||
14223 | Entry.IsZExt = !isSigned; | |||
14224 | Args.push_back(Entry); | |||
14225 | } | |||
14226 | if (Subtarget->isTargetWindows() && Args.size() >= 2) | |||
14227 | std::swap(Args[0], Args[1]); | |||
14228 | return Args; | |||
14229 | } | |||
14230 | ||||
14231 | SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { | |||
14232 | assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||(((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid () || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI () || Subtarget->isTargetWindows()) && "Register-based DivRem lowering only" ) ? static_cast<void> (0) : __assert_fail ("(Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || Subtarget->isTargetWindows()) && \"Register-based DivRem lowering only\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14235, __PRETTY_FUNCTION__)) | |||
14233 | Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||(((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid () || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI () || Subtarget->isTargetWindows()) && "Register-based DivRem lowering only" ) ? static_cast<void> (0) : __assert_fail ("(Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || Subtarget->isTargetWindows()) && \"Register-based DivRem lowering only\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14235, __PRETTY_FUNCTION__)) | |||
14234 | Subtarget->isTargetWindows()) &&(((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid () || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI () || Subtarget->isTargetWindows()) && "Register-based DivRem lowering only" ) ? static_cast<void> (0) : __assert_fail ("(Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || Subtarget->isTargetWindows()) && \"Register-based DivRem lowering only\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14235, __PRETTY_FUNCTION__)) | |||
14235 | "Register-based DivRem lowering only")(((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid () || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI () || Subtarget->isTargetWindows()) && "Register-based DivRem lowering only" ) ? static_cast<void> (0) : __assert_fail ("(Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || Subtarget->isTargetWindows()) && \"Register-based DivRem lowering only\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14235, __PRETTY_FUNCTION__)); | |||
14236 | unsigned Opcode = Op->getOpcode(); | |||
14237 | assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering") ? static_cast<void > (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14238, __PRETTY_FUNCTION__)) | |||
14238 | "Invalid opcode for Div/Rem lowering")(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering") ? static_cast<void > (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14238, __PRETTY_FUNCTION__)); | |||
14239 | bool isSigned = (Opcode == ISD::SDIVREM); | |||
14240 | EVT VT = Op->getValueType(0); | |||
14241 | Type *Ty = VT.getTypeForEVT(*DAG.getContext()); | |||
14242 | SDLoc dl(Op); | |||
14243 | ||||
14244 | // If the target has hardware divide, use divide + multiply + subtract: | |||
14245 | // div = a / b | |||
14246 | // rem = a - b * div | |||
14247 | // return {div, rem} | |||
14248 | // This should be lowered into UDIV/SDIV + MLS later on. | |||
14249 | bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode() | |||
14250 | : Subtarget->hasDivideInARMMode(); | |||
14251 | if (hasDivide && Op->getValueType(0).isSimple() && | |||
14252 | Op->getSimpleValueType(0) == MVT::i32) { | |||
14253 | unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV; | |||
14254 | const SDValue Dividend = Op->getOperand(0); | |||
14255 | const SDValue Divisor = Op->getOperand(1); | |||
14256 | SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor); | |||
14257 | SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor); | |||
14258 | SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul); | |||
14259 | ||||
14260 | SDValue Values[2] = {Div, Rem}; | |||
14261 | return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values); | |||
14262 | } | |||
14263 | ||||
14264 | RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(), | |||
14265 | VT.getSimpleVT().SimpleTy); | |||
14266 | SDValue InChain = DAG.getEntryNode(); | |||
14267 | ||||
14268 | TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(), | |||
14269 | DAG.getContext(), | |||
14270 | Subtarget); | |||
14271 | ||||
14272 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | |||
14273 | getPointerTy(DAG.getDataLayout())); | |||
14274 | ||||
14275 | Type *RetTy = StructType::get(Ty, Ty); | |||
14276 | ||||
14277 | if (Subtarget->isTargetWindows()) | |||
14278 | InChain = WinDBZCheckDenominator(DAG, Op.getNode(), InChain); | |||
14279 | ||||
14280 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
14281 | CLI.setDebugLoc(dl).setChain(InChain) | |||
14282 | .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) | |||
14283 | .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned); | |||
14284 | ||||
14285 | std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); | |||
14286 | return CallInfo.first; | |||
14287 | } | |||
14288 | ||||
14289 | // Lowers REM using divmod helpers | |||
14290 | // see RTABI section 4.2/4.3 | |||
14291 | SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const { | |||
14292 | // Build return types (div and rem) | |||
14293 | std::vector<Type*> RetTyParams; | |||
14294 | Type *RetTyElement; | |||
14295 | ||||
14296 | switch (N->getValueType(0).getSimpleVT().SimpleTy) { | |||
14297 | default: llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14297); | |||
14298 | case MVT::i8: RetTyElement = Type::getInt8Ty(*DAG.getContext()); break; | |||
14299 | case MVT::i16: RetTyElement = Type::getInt16Ty(*DAG.getContext()); break; | |||
14300 | case MVT::i32: RetTyElement = Type::getInt32Ty(*DAG.getContext()); break; | |||
14301 | case MVT::i64: RetTyElement = Type::getInt64Ty(*DAG.getContext()); break; | |||
14302 | } | |||
14303 | ||||
14304 | RetTyParams.push_back(RetTyElement); | |||
14305 | RetTyParams.push_back(RetTyElement); | |||
14306 | ArrayRef<Type*> ret = ArrayRef<Type*>(RetTyParams); | |||
14307 | Type *RetTy = StructType::get(*DAG.getContext(), ret); | |||
14308 | ||||
14309 | RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT(). | |||
14310 | SimpleTy); | |||
14311 | SDValue InChain = DAG.getEntryNode(); | |||
14312 | TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext(), | |||
14313 | Subtarget); | |||
14314 | bool isSigned = N->getOpcode() == ISD::SREM; | |||
14315 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | |||
14316 | getPointerTy(DAG.getDataLayout())); | |||
14317 | ||||
14318 | if (Subtarget->isTargetWindows()) | |||
14319 | InChain = WinDBZCheckDenominator(DAG, N, InChain); | |||
14320 | ||||
14321 | // Lower call | |||
14322 | CallLoweringInfo CLI(DAG); | |||
14323 | CLI.setChain(InChain) | |||
14324 | .setCallee(CallingConv::ARM_AAPCS, RetTy, Callee, std::move(Args)) | |||
14325 | .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N)); | |||
14326 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); | |||
14327 | ||||
14328 | // Return second (rem) result operand (first contains div) | |||
14329 | SDNode *ResNode = CallResult.first.getNode(); | |||
14330 | assert(ResNode->getNumOperands() == 2 && "divmod should return two operands")((ResNode->getNumOperands() == 2 && "divmod should return two operands" ) ? static_cast<void> (0) : __assert_fail ("ResNode->getNumOperands() == 2 && \"divmod should return two operands\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14330, __PRETTY_FUNCTION__)); | |||
14331 | return ResNode->getOperand(1); | |||
14332 | } | |||
14333 | ||||
14334 | SDValue | |||
14335 | ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { | |||
14336 | assert(Subtarget->isTargetWindows() && "unsupported target platform")((Subtarget->isTargetWindows() && "unsupported target platform" ) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"unsupported target platform\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14336, __PRETTY_FUNCTION__)); | |||
14337 | SDLoc DL(Op); | |||
14338 | ||||
14339 | // Get the inputs. | |||
14340 | SDValue Chain = Op.getOperand(0); | |||
14341 | SDValue Size = Op.getOperand(1); | |||
14342 | ||||
14343 | if (DAG.getMachineFunction().getFunction().hasFnAttribute( | |||
14344 | "no-stack-arg-probe")) { | |||
14345 | unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); | |||
14346 | SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); | |||
14347 | Chain = SP.getValue(1); | |||
14348 | SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size); | |||
14349 | if (Align) | |||
14350 | SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0), | |||
14351 | DAG.getConstant(-(uint64_t)Align, DL, MVT::i32)); | |||
14352 | Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP); | |||
14353 | SDValue Ops[2] = { SP, Chain }; | |||
14354 | return DAG.getMergeValues(Ops, DL); | |||
14355 | } | |||
14356 | ||||
14357 | SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size, | |||
14358 | DAG.getConstant(2, DL, MVT::i32)); | |||
14359 | ||||
14360 | SDValue Flag; | |||
14361 | Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag); | |||
14362 | Flag = Chain.getValue(1); | |||
14363 | ||||
14364 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
14365 | Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag); | |||
14366 | ||||
14367 | SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); | |||
14368 | Chain = NewSP.getValue(1); | |||
14369 | ||||
14370 | SDValue Ops[2] = { NewSP, Chain }; | |||
14371 | return DAG.getMergeValues(Ops, DL); | |||
14372 | } | |||
14373 | ||||
14374 | SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const { | |||
14375 | assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&((Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP () && "Unexpected type for custom-lowering FP_EXTEND" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && \"Unexpected type for custom-lowering FP_EXTEND\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14376, __PRETTY_FUNCTION__)) | |||
14376 | "Unexpected type for custom-lowering FP_EXTEND")((Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP () && "Unexpected type for custom-lowering FP_EXTEND" ) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && \"Unexpected type for custom-lowering FP_EXTEND\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14376, __PRETTY_FUNCTION__)); | |||
14377 | ||||
14378 | RTLIB::Libcall LC; | |||
14379 | LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType()); | |||
14380 | ||||
14381 | SDValue SrcVal = Op.getOperand(0); | |||
14382 | return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false, | |||
14383 | SDLoc(Op)).first; | |||
14384 | } | |||
14385 | ||||
14386 | SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const { | |||
14387 | assert(Op.getOperand(0).getValueType() == MVT::f64 &&((Op.getOperand(0).getValueType() == MVT::f64 && Subtarget ->isFPOnlySP() && "Unexpected type for custom-lowering FP_ROUND" ) ? static_cast<void> (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && \"Unexpected type for custom-lowering FP_ROUND\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14389, __PRETTY_FUNCTION__)) | |||
14388 | Subtarget->isFPOnlySP() &&((Op.getOperand(0).getValueType() == MVT::f64 && Subtarget ->isFPOnlySP() && "Unexpected type for custom-lowering FP_ROUND" ) ? static_cast<void> (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && \"Unexpected type for custom-lowering FP_ROUND\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14389, __PRETTY_FUNCTION__)) | |||
14389 | "Unexpected type for custom-lowering FP_ROUND")((Op.getOperand(0).getValueType() == MVT::f64 && Subtarget ->isFPOnlySP() && "Unexpected type for custom-lowering FP_ROUND" ) ? static_cast<void> (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && \"Unexpected type for custom-lowering FP_ROUND\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14389, __PRETTY_FUNCTION__)); | |||
14390 | ||||
14391 | RTLIB::Libcall LC; | |||
14392 | LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType()); | |||
14393 | ||||
14394 | SDValue SrcVal = Op.getOperand(0); | |||
14395 | return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false, | |||
14396 | SDLoc(Op)).first; | |||
14397 | } | |||
14398 | ||||
14399 | void ARMTargetLowering::lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, | |||
14400 | SelectionDAG &DAG) const { | |||
14401 | assert(N->getValueType(0) == MVT::i64 && "Unexpected type (!= i64) on ABS.")((N->getValueType(0) == MVT::i64 && "Unexpected type (!= i64) on ABS." ) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"Unexpected type (!= i64) on ABS.\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14401, __PRETTY_FUNCTION__)); | |||
14402 | MVT HalfT = MVT::i32; | |||
14403 | SDLoc dl(N); | |||
14404 | SDValue Hi, Lo, Tmp; | |||
14405 | ||||
14406 | if (!isOperationLegalOrCustom(ISD::ADDCARRY, HalfT) || | |||
14407 | !isOperationLegalOrCustom(ISD::UADDO, HalfT)) | |||
14408 | return ; | |||
14409 | ||||
14410 | unsigned OpTypeBits = HalfT.getScalarSizeInBits(); | |||
14411 | SDVTList VTList = DAG.getVTList(HalfT, MVT::i1); | |||
14412 | ||||
14413 | Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0), | |||
14414 | DAG.getConstant(0, dl, HalfT)); | |||
14415 | Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0), | |||
14416 | DAG.getConstant(1, dl, HalfT)); | |||
14417 | ||||
14418 | Tmp = DAG.getNode(ISD::SRA, dl, HalfT, Hi, | |||
14419 | DAG.getConstant(OpTypeBits - 1, dl, | |||
14420 | getShiftAmountTy(HalfT, DAG.getDataLayout()))); | |||
14421 | Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo); | |||
14422 | Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi, | |||
14423 | SDValue(Lo.getNode(), 1)); | |||
14424 | Hi = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Hi); | |||
14425 | Lo = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Lo); | |||
14426 | ||||
14427 | Results.push_back(Lo); | |||
14428 | Results.push_back(Hi); | |||
14429 | } | |||
14430 | ||||
14431 | bool | |||
14432 | ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { | |||
14433 | // The ARM target isn't yet aware of offsets. | |||
14434 | return false; | |||
14435 | } | |||
14436 | ||||
14437 | bool ARM::isBitFieldInvertedMask(unsigned v) { | |||
14438 | if (v == 0xffffffff) | |||
14439 | return false; | |||
14440 | ||||
14441 | // there can be 1's on either or both "outsides", all the "inside" | |||
14442 | // bits must be 0's | |||
14443 | return isShiftedMask_32(~v); | |||
14444 | } | |||
14445 | ||||
14446 | /// isFPImmLegal - Returns true if the target can instruction select the | |||
14447 | /// specified FP immediate natively. If false, the legalizer will | |||
14448 | /// materialize the FP immediate as a load from a constant pool. | |||
14449 | bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, | |||
14450 | bool ForCodeSize) const { | |||
14451 | if (!Subtarget->hasVFP3()) | |||
14452 | return false; | |||
14453 | if (VT == MVT::f16 && Subtarget->hasFullFP16()) | |||
14454 | return ARM_AM::getFP16Imm(Imm) != -1; | |||
14455 | if (VT == MVT::f32) | |||
14456 | return ARM_AM::getFP32Imm(Imm) != -1; | |||
14457 | if (VT == MVT::f64 && !Subtarget->isFPOnlySP()) | |||
14458 | return ARM_AM::getFP64Imm(Imm) != -1; | |||
14459 | return false; | |||
14460 | } | |||
14461 | ||||
14462 | /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as | |||
14463 | /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment | |||
14464 | /// specified in the intrinsic calls. | |||
14465 | bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, | |||
14466 | const CallInst &I, | |||
14467 | MachineFunction &MF, | |||
14468 | unsigned Intrinsic) const { | |||
14469 | switch (Intrinsic) { | |||
14470 | case Intrinsic::arm_neon_vld1: | |||
14471 | case Intrinsic::arm_neon_vld2: | |||
14472 | case Intrinsic::arm_neon_vld3: | |||
14473 | case Intrinsic::arm_neon_vld4: | |||
14474 | case Intrinsic::arm_neon_vld2lane: | |||
14475 | case Intrinsic::arm_neon_vld3lane: | |||
14476 | case Intrinsic::arm_neon_vld4lane: | |||
14477 | case Intrinsic::arm_neon_vld2dup: | |||
14478 | case Intrinsic::arm_neon_vld3dup: | |||
14479 | case Intrinsic::arm_neon_vld4dup: { | |||
14480 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14481 | // Conservatively set memVT to the entire set of vectors loaded. | |||
14482 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14483 | uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64; | |||
14484 | Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); | |||
14485 | Info.ptrVal = I.getArgOperand(0); | |||
14486 | Info.offset = 0; | |||
14487 | Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); | |||
14488 | Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); | |||
14489 | // volatile loads with NEON intrinsics not supported | |||
14490 | Info.flags = MachineMemOperand::MOLoad; | |||
14491 | return true; | |||
14492 | } | |||
14493 | case Intrinsic::arm_neon_vld1x2: | |||
14494 | case Intrinsic::arm_neon_vld1x3: | |||
14495 | case Intrinsic::arm_neon_vld1x4: { | |||
14496 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14497 | // Conservatively set memVT to the entire set of vectors loaded. | |||
14498 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14499 | uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64; | |||
14500 | Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); | |||
14501 | Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1); | |||
14502 | Info.offset = 0; | |||
14503 | Info.align = 0; | |||
14504 | // volatile loads with NEON intrinsics not supported | |||
14505 | Info.flags = MachineMemOperand::MOLoad; | |||
14506 | return true; | |||
14507 | } | |||
14508 | case Intrinsic::arm_neon_vst1: | |||
14509 | case Intrinsic::arm_neon_vst2: | |||
14510 | case Intrinsic::arm_neon_vst3: | |||
14511 | case Intrinsic::arm_neon_vst4: | |||
14512 | case Intrinsic::arm_neon_vst2lane: | |||
14513 | case Intrinsic::arm_neon_vst3lane: | |||
14514 | case Intrinsic::arm_neon_vst4lane: { | |||
14515 | Info.opc = ISD::INTRINSIC_VOID; | |||
14516 | // Conservatively set memVT to the entire set of vectors stored. | |||
14517 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14518 | unsigned NumElts = 0; | |||
14519 | for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { | |||
14520 | Type *ArgTy = I.getArgOperand(ArgI)->getType(); | |||
14521 | if (!ArgTy->isVectorTy()) | |||
14522 | break; | |||
14523 | NumElts += DL.getTypeSizeInBits(ArgTy) / 64; | |||
14524 | } | |||
14525 | Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); | |||
14526 | Info.ptrVal = I.getArgOperand(0); | |||
14527 | Info.offset = 0; | |||
14528 | Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); | |||
14529 | Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); | |||
14530 | // volatile stores with NEON intrinsics not supported | |||
14531 | Info.flags = MachineMemOperand::MOStore; | |||
14532 | return true; | |||
14533 | } | |||
14534 | case Intrinsic::arm_neon_vst1x2: | |||
14535 | case Intrinsic::arm_neon_vst1x3: | |||
14536 | case Intrinsic::arm_neon_vst1x4: { | |||
14537 | Info.opc = ISD::INTRINSIC_VOID; | |||
14538 | // Conservatively set memVT to the entire set of vectors stored. | |||
14539 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14540 | unsigned NumElts = 0; | |||
14541 | for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { | |||
14542 | Type *ArgTy = I.getArgOperand(ArgI)->getType(); | |||
14543 | if (!ArgTy->isVectorTy()) | |||
14544 | break; | |||
14545 | NumElts += DL.getTypeSizeInBits(ArgTy) / 64; | |||
14546 | } | |||
14547 | Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); | |||
14548 | Info.ptrVal = I.getArgOperand(0); | |||
14549 | Info.offset = 0; | |||
14550 | Info.align = 0; | |||
14551 | // volatile stores with NEON intrinsics not supported | |||
14552 | Info.flags = MachineMemOperand::MOStore; | |||
14553 | return true; | |||
14554 | } | |||
14555 | case Intrinsic::arm_ldaex: | |||
14556 | case Intrinsic::arm_ldrex: { | |||
14557 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14558 | PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType()); | |||
14559 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14560 | Info.memVT = MVT::getVT(PtrTy->getElementType()); | |||
14561 | Info.ptrVal = I.getArgOperand(0); | |||
14562 | Info.offset = 0; | |||
14563 | Info.align = DL.getABITypeAlignment(PtrTy->getElementType()); | |||
14564 | Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; | |||
14565 | return true; | |||
14566 | } | |||
14567 | case Intrinsic::arm_stlex: | |||
14568 | case Intrinsic::arm_strex: { | |||
14569 | auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); | |||
14570 | PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType()); | |||
14571 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14572 | Info.memVT = MVT::getVT(PtrTy->getElementType()); | |||
14573 | Info.ptrVal = I.getArgOperand(1); | |||
14574 | Info.offset = 0; | |||
14575 | Info.align = DL.getABITypeAlignment(PtrTy->getElementType()); | |||
14576 | Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; | |||
14577 | return true; | |||
14578 | } | |||
14579 | case Intrinsic::arm_stlexd: | |||
14580 | case Intrinsic::arm_strexd: | |||
14581 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14582 | Info.memVT = MVT::i64; | |||
14583 | Info.ptrVal = I.getArgOperand(2); | |||
14584 | Info.offset = 0; | |||
14585 | Info.align = 8; | |||
14586 | Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; | |||
14587 | return true; | |||
14588 | ||||
14589 | case Intrinsic::arm_ldaexd: | |||
14590 | case Intrinsic::arm_ldrexd: | |||
14591 | Info.opc = ISD::INTRINSIC_W_CHAIN; | |||
14592 | Info.memVT = MVT::i64; | |||
14593 | Info.ptrVal = I.getArgOperand(0); | |||
14594 | Info.offset = 0; | |||
14595 | Info.align = 8; | |||
14596 | Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; | |||
14597 | return true; | |||
14598 | ||||
14599 | default: | |||
14600 | break; | |||
14601 | } | |||
14602 | ||||
14603 | return false; | |||
14604 | } | |||
14605 | ||||
14606 | /// Returns true if it is beneficial to convert a load of a constant | |||
14607 | /// to just the constant itself. | |||
14608 | bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, | |||
14609 | Type *Ty) const { | |||
14610 | assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14610, __PRETTY_FUNCTION__)); | |||
14611 | ||||
14612 | unsigned Bits = Ty->getPrimitiveSizeInBits(); | |||
14613 | if (Bits == 0 || Bits > 32) | |||
14614 | return false; | |||
14615 | return true; | |||
14616 | } | |||
14617 | ||||
14618 | bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, | |||
14619 | unsigned Index) const { | |||
14620 | if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) | |||
14621 | return false; | |||
14622 | ||||
14623 | return (Index == 0 || Index == ResVT.getVectorNumElements()); | |||
14624 | } | |||
14625 | ||||
14626 | Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder, | |||
14627 | ARM_MB::MemBOpt Domain) const { | |||
14628 | Module *M = Builder.GetInsertBlock()->getParent()->getParent(); | |||
14629 | ||||
14630 | // First, if the target has no DMB, see what fallback we can use. | |||
14631 | if (!Subtarget->hasDataBarrier()) { | |||
14632 | // Some ARMv6 cpus can support data barriers with an mcr instruction. | |||
14633 | // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get | |||
14634 | // here. | |||
14635 | if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { | |||
14636 | Function *MCR = Intrinsic::getDeclaration(M, Intrinsic::arm_mcr); | |||
14637 | Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0), | |||
14638 | Builder.getInt32(0), Builder.getInt32(7), | |||
14639 | Builder.getInt32(10), Builder.getInt32(5)}; | |||
14640 | return Builder.CreateCall(MCR, args); | |||
14641 | } else { | |||
14642 | // Instead of using barriers, atomic accesses on these subtargets use | |||
14643 | // libcalls. | |||
14644 | llvm_unreachable("makeDMB on a target so old that it has no barriers")::llvm::llvm_unreachable_internal("makeDMB on a target so old that it has no barriers" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14644); | |||
14645 | } | |||
14646 | } else { | |||
14647 | Function *DMB = Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); | |||
14648 | // Only a full system barrier exists in the M-class architectures. | |||
14649 | Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; | |||
14650 | Constant *CDomain = Builder.getInt32(Domain); | |||
14651 | return Builder.CreateCall(DMB, CDomain); | |||
14652 | } | |||
14653 | } | |||
14654 | ||||
14655 | // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html | |||
14656 | Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder, | |||
14657 | Instruction *Inst, | |||
14658 | AtomicOrdering Ord) const { | |||
14659 | switch (Ord) { | |||
14660 | case AtomicOrdering::NotAtomic: | |||
14661 | case AtomicOrdering::Unordered: | |||
14662 | llvm_unreachable("Invalid fence: unordered/non-atomic")::llvm::llvm_unreachable_internal("Invalid fence: unordered/non-atomic" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14662); | |||
14663 | case AtomicOrdering::Monotonic: | |||
14664 | case AtomicOrdering::Acquire: | |||
14665 | return nullptr; // Nothing to do | |||
14666 | case AtomicOrdering::SequentiallyConsistent: | |||
14667 | if (!Inst->hasAtomicStore()) | |||
14668 | return nullptr; // Nothing to do | |||
14669 | LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
14670 | case AtomicOrdering::Release: | |||
14671 | case AtomicOrdering::AcquireRelease: | |||
14672 | if (Subtarget->preferISHSTBarriers()) | |||
14673 | return makeDMB(Builder, ARM_MB::ISHST); | |||
14674 | // FIXME: add a comment with a link to documentation justifying this. | |||
14675 | else | |||
14676 | return makeDMB(Builder, ARM_MB::ISH); | |||
14677 | } | |||
14678 | llvm_unreachable("Unknown fence ordering in emitLeadingFence")::llvm::llvm_unreachable_internal("Unknown fence ordering in emitLeadingFence" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14678); | |||
14679 | } | |||
14680 | ||||
14681 | Instruction *ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder, | |||
14682 | Instruction *Inst, | |||
14683 | AtomicOrdering Ord) const { | |||
14684 | switch (Ord) { | |||
14685 | case AtomicOrdering::NotAtomic: | |||
14686 | case AtomicOrdering::Unordered: | |||
14687 | llvm_unreachable("Invalid fence: unordered/not-atomic")::llvm::llvm_unreachable_internal("Invalid fence: unordered/not-atomic" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14687); | |||
14688 | case AtomicOrdering::Monotonic: | |||
14689 | case AtomicOrdering::Release: | |||
14690 | return nullptr; // Nothing to do | |||
14691 | case AtomicOrdering::Acquire: | |||
14692 | case AtomicOrdering::AcquireRelease: | |||
14693 | case AtomicOrdering::SequentiallyConsistent: | |||
14694 | return makeDMB(Builder, ARM_MB::ISH); | |||
14695 | } | |||
14696 | llvm_unreachable("Unknown fence ordering in emitTrailingFence")::llvm::llvm_unreachable_internal("Unknown fence ordering in emitTrailingFence" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14696); | |||
14697 | } | |||
14698 | ||||
14699 | // Loads and stores less than 64-bits are already atomic; ones above that | |||
14700 | // are doomed anyway, so defer to the default libcall and blame the OS when | |||
14701 | // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit | |||
14702 | // anything for those. | |||
14703 | bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { | |||
14704 | unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits(); | |||
14705 | return (Size == 64) && !Subtarget->isMClass(); | |||
14706 | } | |||
14707 | ||||
14708 | // Loads and stores less than 64-bits are already atomic; ones above that | |||
14709 | // are doomed anyway, so defer to the default libcall and blame the OS when | |||
14710 | // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit | |||
14711 | // anything for those. | |||
14712 | // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that | |||
14713 | // guarantee, see DDI0406C ARM architecture reference manual, | |||
14714 | // sections A8.8.72-74 LDRD) | |||
14715 | TargetLowering::AtomicExpansionKind | |||
14716 | ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { | |||
14717 | unsigned Size = LI->getType()->getPrimitiveSizeInBits(); | |||
14718 | return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly | |||
14719 | : AtomicExpansionKind::None; | |||
14720 | } | |||
14721 | ||||
14722 | // For the real atomic operations, we have ldrex/strex up to 32 bits, | |||
14723 | // and up to 64 bits on the non-M profiles | |||
14724 | TargetLowering::AtomicExpansionKind | |||
14725 | ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { | |||
14726 | if (AI->isFloatingPointOperation()) | |||
14727 | return AtomicExpansionKind::CmpXChg; | |||
14728 | ||||
14729 | unsigned Size = AI->getType()->getPrimitiveSizeInBits(); | |||
14730 | bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps(); | |||
14731 | return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW) | |||
14732 | ? AtomicExpansionKind::LLSC | |||
14733 | : AtomicExpansionKind::None; | |||
14734 | } | |||
14735 | ||||
14736 | TargetLowering::AtomicExpansionKind | |||
14737 | ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const { | |||
14738 | // At -O0, fast-regalloc cannot cope with the live vregs necessary to | |||
14739 | // implement cmpxchg without spilling. If the address being exchanged is also | |||
14740 | // on the stack and close enough to the spill slot, this can lead to a | |||
14741 | // situation where the monitor always gets cleared and the atomic operation | |||
14742 | // can never succeed. So at -O0 we need a late-expanded pseudo-inst instead. | |||
14743 | bool HasAtomicCmpXchg = | |||
14744 | !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps(); | |||
14745 | if (getTargetMachine().getOptLevel() != 0 && HasAtomicCmpXchg) | |||
14746 | return AtomicExpansionKind::LLSC; | |||
14747 | return AtomicExpansionKind::None; | |||
14748 | } | |||
14749 | ||||
14750 | bool ARMTargetLowering::shouldInsertFencesForAtomic( | |||
14751 | const Instruction *I) const { | |||
14752 | return InsertFencesForAtomic; | |||
14753 | } | |||
14754 | ||||
14755 | // This has so far only been implemented for MachO. | |||
14756 | bool ARMTargetLowering::useLoadStackGuardNode() const { | |||
14757 | return Subtarget->isTargetMachO(); | |||
14758 | } | |||
14759 | ||||
14760 | bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx, | |||
14761 | unsigned &Cost) const { | |||
14762 | // If we do not have NEON, vector types are not natively supported. | |||
14763 | if (!Subtarget->hasNEON()) | |||
14764 | return false; | |||
14765 | ||||
14766 | // Floating point values and vector values map to the same register file. | |||
14767 | // Therefore, although we could do a store extract of a vector type, this is | |||
14768 | // better to leave at float as we have more freedom in the addressing mode for | |||
14769 | // those. | |||
14770 | if (VectorTy->isFPOrFPVectorTy()) | |||
14771 | return false; | |||
14772 | ||||
14773 | // If the index is unknown at compile time, this is very expensive to lower | |||
14774 | // and it is not possible to combine the store with the extract. | |||
14775 | if (!isa<ConstantInt>(Idx)) | |||
14776 | return false; | |||
14777 | ||||
14778 | assert(VectorTy->isVectorTy() && "VectorTy is not a vector type")((VectorTy->isVectorTy() && "VectorTy is not a vector type" ) ? static_cast<void> (0) : __assert_fail ("VectorTy->isVectorTy() && \"VectorTy is not a vector type\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14778, __PRETTY_FUNCTION__)); | |||
14779 | unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth(); | |||
14780 | // We can do a store + vector extract on any vector that fits perfectly in a D | |||
14781 | // or Q register. | |||
14782 | if (BitWidth == 64 || BitWidth == 128) { | |||
14783 | Cost = 0; | |||
14784 | return true; | |||
14785 | } | |||
14786 | return false; | |||
14787 | } | |||
14788 | ||||
14789 | bool ARMTargetLowering::isCheapToSpeculateCttz() const { | |||
14790 | return Subtarget->hasV6T2Ops(); | |||
14791 | } | |||
14792 | ||||
14793 | bool ARMTargetLowering::isCheapToSpeculateCtlz() const { | |||
14794 | return Subtarget->hasV6T2Ops(); | |||
14795 | } | |||
14796 | ||||
14797 | bool ARMTargetLowering::shouldExpandShift(SelectionDAG &DAG, SDNode *N) const { | |||
14798 | return !Subtarget->hasMinSize(); | |||
14799 | } | |||
14800 | ||||
14801 | Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, | |||
14802 | AtomicOrdering Ord) const { | |||
14803 | Module *M = Builder.GetInsertBlock()->getParent()->getParent(); | |||
14804 | Type *ValTy = cast<PointerType>(Addr->getType())->getElementType(); | |||
14805 | bool IsAcquire = isAcquireOrStronger(Ord); | |||
14806 | ||||
14807 | // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd | |||
14808 | // intrinsic must return {i32, i32} and we have to recombine them into a | |||
14809 | // single i64 here. | |||
14810 | if (ValTy->getPrimitiveSizeInBits() == 64) { | |||
14811 | Intrinsic::ID Int = | |||
14812 | IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd; | |||
14813 | Function *Ldrex = Intrinsic::getDeclaration(M, Int); | |||
14814 | ||||
14815 | Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); | |||
14816 | Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi"); | |||
14817 | ||||
14818 | Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo"); | |||
14819 | Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi"); | |||
14820 | if (!Subtarget->isLittle()) | |||
14821 | std::swap (Lo, Hi); | |||
14822 | Lo = Builder.CreateZExt(Lo, ValTy, "lo64"); | |||
14823 | Hi = Builder.CreateZExt(Hi, ValTy, "hi64"); | |||
14824 | return Builder.CreateOr( | |||
14825 | Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64"); | |||
14826 | } | |||
14827 | ||||
14828 | Type *Tys[] = { Addr->getType() }; | |||
14829 | Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex; | |||
14830 | Function *Ldrex = Intrinsic::getDeclaration(M, Int, Tys); | |||
14831 | ||||
14832 | return Builder.CreateTruncOrBitCast( | |||
14833 | Builder.CreateCall(Ldrex, Addr), | |||
14834 | cast<PointerType>(Addr->getType())->getElementType()); | |||
14835 | } | |||
14836 | ||||
14837 | void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance( | |||
14838 | IRBuilder<> &Builder) const { | |||
14839 | if (!Subtarget->hasV7Ops()) | |||
14840 | return; | |||
14841 | Module *M = Builder.GetInsertBlock()->getParent()->getParent(); | |||
14842 | Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex)); | |||
14843 | } | |||
14844 | ||||
14845 | Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val, | |||
14846 | Value *Addr, | |||
14847 | AtomicOrdering Ord) const { | |||
14848 | Module *M = Builder.GetInsertBlock()->getParent()->getParent(); | |||
14849 | bool IsRelease = isReleaseOrStronger(Ord); | |||
14850 | ||||
14851 | // Since the intrinsics must have legal type, the i64 intrinsics take two | |||
14852 | // parameters: "i32, i32". We must marshal Val into the appropriate form | |||
14853 | // before the call. | |||
14854 | if (Val->getType()->getPrimitiveSizeInBits() == 64) { | |||
14855 | Intrinsic::ID Int = | |||
14856 | IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd; | |||
14857 | Function *Strex = Intrinsic::getDeclaration(M, Int); | |||
14858 | Type *Int32Ty = Type::getInt32Ty(M->getContext()); | |||
14859 | ||||
14860 | Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo"); | |||
14861 | Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi"); | |||
14862 | if (!Subtarget->isLittle()) | |||
14863 | std::swap(Lo, Hi); | |||
14864 | Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); | |||
14865 | return Builder.CreateCall(Strex, {Lo, Hi, Addr}); | |||
14866 | } | |||
14867 | ||||
14868 | Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex; | |||
14869 | Type *Tys[] = { Addr->getType() }; | |||
14870 | Function *Strex = Intrinsic::getDeclaration(M, Int, Tys); | |||
14871 | ||||
14872 | return Builder.CreateCall( | |||
14873 | Strex, {Builder.CreateZExtOrBitCast( | |||
14874 | Val, Strex->getFunctionType()->getParamType(0)), | |||
14875 | Addr}); | |||
14876 | } | |||
14877 | ||||
14878 | ||||
14879 | bool ARMTargetLowering::alignLoopsWithOptSize() const { | |||
14880 | return Subtarget->isMClass(); | |||
14881 | } | |||
14882 | ||||
14883 | /// A helper function for determining the number of interleaved accesses we | |||
14884 | /// will generate when lowering accesses of the given type. | |||
14885 | unsigned | |||
14886 | ARMTargetLowering::getNumInterleavedAccesses(VectorType *VecTy, | |||
14887 | const DataLayout &DL) const { | |||
14888 | return (DL.getTypeSizeInBits(VecTy) + 127) / 128; | |||
14889 | } | |||
14890 | ||||
14891 | bool ARMTargetLowering::isLegalInterleavedAccessType( | |||
14892 | VectorType *VecTy, const DataLayout &DL) const { | |||
14893 | ||||
14894 | unsigned VecSize = DL.getTypeSizeInBits(VecTy); | |||
14895 | unsigned ElSize = DL.getTypeSizeInBits(VecTy->getElementType()); | |||
14896 | ||||
14897 | // Ensure the vector doesn't have f16 elements. Even though we could do an | |||
14898 | // i16 vldN, we can't hold the f16 vectors and will end up converting via | |||
14899 | // f32. | |||
14900 | if (VecTy->getElementType()->isHalfTy()) | |||
14901 | return false; | |||
14902 | ||||
14903 | // Ensure the number of vector elements is greater than 1. | |||
14904 | if (VecTy->getNumElements() < 2) | |||
14905 | return false; | |||
14906 | ||||
14907 | // Ensure the element type is legal. | |||
14908 | if (ElSize != 8 && ElSize != 16 && ElSize != 32) | |||
14909 | return false; | |||
14910 | ||||
14911 | // Ensure the total vector size is 64 or a multiple of 128. Types larger than | |||
14912 | // 128 will be split into multiple interleaved accesses. | |||
14913 | return VecSize == 64 || VecSize % 128 == 0; | |||
14914 | } | |||
14915 | ||||
14916 | /// Lower an interleaved load into a vldN intrinsic. | |||
14917 | /// | |||
14918 | /// E.g. Lower an interleaved load (Factor = 2): | |||
14919 | /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4 | |||
14920 | /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements | |||
14921 | /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements | |||
14922 | /// | |||
14923 | /// Into: | |||
14924 | /// %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4) | |||
14925 | /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0 | |||
14926 | /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1 | |||
14927 | bool ARMTargetLowering::lowerInterleavedLoad( | |||
14928 | LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles, | |||
14929 | ArrayRef<unsigned> Indices, unsigned Factor) const { | |||
14930 | assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&((Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor () && "Invalid interleave factor") ? static_cast<void > (0) : __assert_fail ("Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() && \"Invalid interleave factor\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14931, __PRETTY_FUNCTION__)) | |||
14931 | "Invalid interleave factor")((Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor () && "Invalid interleave factor") ? static_cast<void > (0) : __assert_fail ("Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() && \"Invalid interleave factor\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14931, __PRETTY_FUNCTION__)); | |||
14932 | assert(!Shuffles.empty() && "Empty shufflevector input")((!Shuffles.empty() && "Empty shufflevector input") ? static_cast<void> (0) : __assert_fail ("!Shuffles.empty() && \"Empty shufflevector input\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14932, __PRETTY_FUNCTION__)); | |||
14933 | assert(Shuffles.size() == Indices.size() &&((Shuffles.size() == Indices.size() && "Unmatched number of shufflevectors and indices" ) ? static_cast<void> (0) : __assert_fail ("Shuffles.size() == Indices.size() && \"Unmatched number of shufflevectors and indices\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14934, __PRETTY_FUNCTION__)) | |||
14934 | "Unmatched number of shufflevectors and indices")((Shuffles.size() == Indices.size() && "Unmatched number of shufflevectors and indices" ) ? static_cast<void> (0) : __assert_fail ("Shuffles.size() == Indices.size() && \"Unmatched number of shufflevectors and indices\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14934, __PRETTY_FUNCTION__)); | |||
14935 | ||||
14936 | VectorType *VecTy = Shuffles[0]->getType(); | |||
14937 | Type *EltTy = VecTy->getVectorElementType(); | |||
14938 | ||||
14939 | const DataLayout &DL = LI->getModule()->getDataLayout(); | |||
14940 | ||||
14941 | // Skip if we do not have NEON and skip illegal vector types. We can | |||
14942 | // "legalize" wide vector types into multiple interleaved accesses as long as | |||
14943 | // the vector types are divisible by 128. | |||
14944 | if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(VecTy, DL)) | |||
14945 | return false; | |||
14946 | ||||
14947 | unsigned NumLoads = getNumInterleavedAccesses(VecTy, DL); | |||
14948 | ||||
14949 | // A pointer vector can not be the return type of the ldN intrinsics. Need to | |||
14950 | // load integer vectors first and then convert to pointer vectors. | |||
14951 | if (EltTy->isPointerTy()) | |||
14952 | VecTy = | |||
14953 | VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements()); | |||
14954 | ||||
14955 | IRBuilder<> Builder(LI); | |||
14956 | ||||
14957 | // The base address of the load. | |||
14958 | Value *BaseAddr = LI->getPointerOperand(); | |||
14959 | ||||
14960 | if (NumLoads > 1) { | |||
14961 | // If we're going to generate more than one load, reset the sub-vector type | |||
14962 | // to something legal. | |||
14963 | VecTy = VectorType::get(VecTy->getVectorElementType(), | |||
14964 | VecTy->getVectorNumElements() / NumLoads); | |||
14965 | ||||
14966 | // We will compute the pointer operand of each load from the original base | |||
14967 | // address using GEPs. Cast the base address to a pointer to the scalar | |||
14968 | // element type. | |||
14969 | BaseAddr = Builder.CreateBitCast( | |||
14970 | BaseAddr, VecTy->getVectorElementType()->getPointerTo( | |||
14971 | LI->getPointerAddressSpace())); | |||
14972 | } | |||
14973 | ||||
14974 | assert(isTypeLegal(EVT::getEVT(VecTy)) && "Illegal vldN vector type!")((isTypeLegal(EVT::getEVT(VecTy)) && "Illegal vldN vector type!" ) ? static_cast<void> (0) : __assert_fail ("isTypeLegal(EVT::getEVT(VecTy)) && \"Illegal vldN vector type!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 14974, __PRETTY_FUNCTION__)); | |||
14975 | ||||
14976 | Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace()); | |||
14977 | Type *Tys[] = {VecTy, Int8Ptr}; | |||
14978 | static const Intrinsic::ID LoadInts[3] = {Intrinsic::arm_neon_vld2, | |||
14979 | Intrinsic::arm_neon_vld3, | |||
14980 | Intrinsic::arm_neon_vld4}; | |||
14981 | Function *VldnFunc = | |||
14982 | Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys); | |||
14983 | ||||
14984 | // Holds sub-vectors extracted from the load intrinsic return values. The | |||
14985 | // sub-vectors are associated with the shufflevector instructions they will | |||
14986 | // replace. | |||
14987 | DenseMap<ShuffleVectorInst *, SmallVector<Value *, 4>> SubVecs; | |||
14988 | ||||
14989 | for (unsigned LoadCount = 0; LoadCount < NumLoads; ++LoadCount) { | |||
14990 | // If we're generating more than one load, compute the base address of | |||
14991 | // subsequent loads as an offset from the previous. | |||
14992 | if (LoadCount > 0) | |||
14993 | BaseAddr = | |||
14994 | Builder.CreateConstGEP1_32(VecTy->getVectorElementType(), BaseAddr, | |||
14995 | VecTy->getVectorNumElements() * Factor); | |||
14996 | ||||
14997 | SmallVector<Value *, 2> Ops; | |||
14998 | Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr)); | |||
14999 | Ops.push_back(Builder.getInt32(LI->getAlignment())); | |||
15000 | ||||
15001 | CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN"); | |||
15002 | ||||
15003 | // Replace uses of each shufflevector with the corresponding vector loaded | |||
15004 | // by ldN. | |||
15005 | for (unsigned i = 0; i < Shuffles.size(); i++) { | |||
15006 | ShuffleVectorInst *SV = Shuffles[i]; | |||
15007 | unsigned Index = Indices[i]; | |||
15008 | ||||
15009 | Value *SubVec = Builder.CreateExtractValue(VldN, Index); | |||
15010 | ||||
15011 | // Convert the integer vector to pointer vector if the element is pointer. | |||
15012 | if (EltTy->isPointerTy()) | |||
15013 | SubVec = Builder.CreateIntToPtr( | |||
15014 | SubVec, VectorType::get(SV->getType()->getVectorElementType(), | |||
15015 | VecTy->getVectorNumElements())); | |||
15016 | ||||
15017 | SubVecs[SV].push_back(SubVec); | |||
15018 | } | |||
15019 | } | |||
15020 | ||||
15021 | // Replace uses of the shufflevector instructions with the sub-vectors | |||
15022 | // returned by the load intrinsic. If a shufflevector instruction is | |||
15023 | // associated with more than one sub-vector, those sub-vectors will be | |||
15024 | // concatenated into a single wide vector. | |||
15025 | for (ShuffleVectorInst *SVI : Shuffles) { | |||
15026 | auto &SubVec = SubVecs[SVI]; | |||
15027 | auto *WideVec = | |||
15028 | SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; | |||
15029 | SVI->replaceAllUsesWith(WideVec); | |||
15030 | } | |||
15031 | ||||
15032 | return true; | |||
15033 | } | |||
15034 | ||||
15035 | /// Lower an interleaved store into a vstN intrinsic. | |||
15036 | /// | |||
15037 | /// E.g. Lower an interleaved store (Factor = 3): | |||
15038 | /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, | |||
15039 | /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> | |||
15040 | /// store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4 | |||
15041 | /// | |||
15042 | /// Into: | |||
15043 | /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3> | |||
15044 | /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7> | |||
15045 | /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11> | |||
15046 | /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4) | |||
15047 | /// | |||
15048 | /// Note that the new shufflevectors will be removed and we'll only generate one | |||
15049 | /// vst3 instruction in CodeGen. | |||
15050 | /// | |||
15051 | /// Example for a more general valid mask (Factor 3). Lower: | |||
15052 | /// %i.vec = shuffle <32 x i32> %v0, <32 x i32> %v1, | |||
15053 | /// <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19> | |||
15054 | /// store <12 x i32> %i.vec, <12 x i32>* %ptr | |||
15055 | /// | |||
15056 | /// Into: | |||
15057 | /// %sub.v0 = shuffle <32 x i32> %v0, <32 x i32> v1, <4, 5, 6, 7> | |||
15058 | /// %sub.v1 = shuffle <32 x i32> %v0, <32 x i32> v1, <32, 33, 34, 35> | |||
15059 | /// %sub.v2 = shuffle <32 x i32> %v0, <32 x i32> v1, <16, 17, 18, 19> | |||
15060 | /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4) | |||
15061 | bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI, | |||
15062 | ShuffleVectorInst *SVI, | |||
15063 | unsigned Factor) const { | |||
15064 | assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&((Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor () && "Invalid interleave factor") ? static_cast<void > (0) : __assert_fail ("Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() && \"Invalid interleave factor\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15065, __PRETTY_FUNCTION__)) | |||
15065 | "Invalid interleave factor")((Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor () && "Invalid interleave factor") ? static_cast<void > (0) : __assert_fail ("Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() && \"Invalid interleave factor\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15065, __PRETTY_FUNCTION__)); | |||
15066 | ||||
15067 | VectorType *VecTy = SVI->getType(); | |||
15068 | assert(VecTy->getVectorNumElements() % Factor == 0 &&((VecTy->getVectorNumElements() % Factor == 0 && "Invalid interleaved store" ) ? static_cast<void> (0) : __assert_fail ("VecTy->getVectorNumElements() % Factor == 0 && \"Invalid interleaved store\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15069, __PRETTY_FUNCTION__)) | |||
15069 | "Invalid interleaved store")((VecTy->getVectorNumElements() % Factor == 0 && "Invalid interleaved store" ) ? static_cast<void> (0) : __assert_fail ("VecTy->getVectorNumElements() % Factor == 0 && \"Invalid interleaved store\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15069, __PRETTY_FUNCTION__)); | |||
15070 | ||||
15071 | unsigned LaneLen = VecTy->getVectorNumElements() / Factor; | |||
15072 | Type *EltTy = VecTy->getVectorElementType(); | |||
15073 | VectorType *SubVecTy = VectorType::get(EltTy, LaneLen); | |||
15074 | ||||
15075 | const DataLayout &DL = SI->getModule()->getDataLayout(); | |||
15076 | ||||
15077 | // Skip if we do not have NEON and skip illegal vector types. We can | |||
15078 | // "legalize" wide vector types into multiple interleaved accesses as long as | |||
15079 | // the vector types are divisible by 128. | |||
15080 | if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(SubVecTy, DL)) | |||
15081 | return false; | |||
15082 | ||||
15083 | unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL); | |||
15084 | ||||
15085 | Value *Op0 = SVI->getOperand(0); | |||
15086 | Value *Op1 = SVI->getOperand(1); | |||
15087 | IRBuilder<> Builder(SI); | |||
15088 | ||||
15089 | // StN intrinsics don't support pointer vectors as arguments. Convert pointer | |||
15090 | // vectors to integer vectors. | |||
15091 | if (EltTy->isPointerTy()) { | |||
15092 | Type *IntTy = DL.getIntPtrType(EltTy); | |||
15093 | ||||
15094 | // Convert to the corresponding integer vector. | |||
15095 | Type *IntVecTy = | |||
15096 | VectorType::get(IntTy, Op0->getType()->getVectorNumElements()); | |||
15097 | Op0 = Builder.CreatePtrToInt(Op0, IntVecTy); | |||
15098 | Op1 = Builder.CreatePtrToInt(Op1, IntVecTy); | |||
15099 | ||||
15100 | SubVecTy = VectorType::get(IntTy, LaneLen); | |||
15101 | } | |||
15102 | ||||
15103 | // The base address of the store. | |||
15104 | Value *BaseAddr = SI->getPointerOperand(); | |||
15105 | ||||
15106 | if (NumStores > 1) { | |||
15107 | // If we're going to generate more than one store, reset the lane length | |||
15108 | // and sub-vector type to something legal. | |||
15109 | LaneLen /= NumStores; | |||
15110 | SubVecTy = VectorType::get(SubVecTy->getVectorElementType(), LaneLen); | |||
15111 | ||||
15112 | // We will compute the pointer operand of each store from the original base | |||
15113 | // address using GEPs. Cast the base address to a pointer to the scalar | |||
15114 | // element type. | |||
15115 | BaseAddr = Builder.CreateBitCast( | |||
15116 | BaseAddr, SubVecTy->getVectorElementType()->getPointerTo( | |||
15117 | SI->getPointerAddressSpace())); | |||
15118 | } | |||
15119 | ||||
15120 | assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!")((isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!" ) ? static_cast<void> (0) : __assert_fail ("isTypeLegal(EVT::getEVT(SubVecTy)) && \"Illegal vstN vector type!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15120, __PRETTY_FUNCTION__)); | |||
15121 | ||||
15122 | auto Mask = SVI->getShuffleMask(); | |||
15123 | ||||
15124 | Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace()); | |||
15125 | Type *Tys[] = {Int8Ptr, SubVecTy}; | |||
15126 | static const Intrinsic::ID StoreInts[3] = {Intrinsic::arm_neon_vst2, | |||
15127 | Intrinsic::arm_neon_vst3, | |||
15128 | Intrinsic::arm_neon_vst4}; | |||
15129 | ||||
15130 | for (unsigned StoreCount = 0; StoreCount < NumStores; ++StoreCount) { | |||
15131 | // If we generating more than one store, we compute the base address of | |||
15132 | // subsequent stores as an offset from the previous. | |||
15133 | if (StoreCount > 0) | |||
15134 | BaseAddr = Builder.CreateConstGEP1_32(SubVecTy->getVectorElementType(), | |||
15135 | BaseAddr, LaneLen * Factor); | |||
15136 | ||||
15137 | SmallVector<Value *, 6> Ops; | |||
15138 | Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr)); | |||
15139 | ||||
15140 | Function *VstNFunc = | |||
15141 | Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys); | |||
15142 | ||||
15143 | // Split the shufflevector operands into sub vectors for the new vstN call. | |||
15144 | for (unsigned i = 0; i < Factor; i++) { | |||
15145 | unsigned IdxI = StoreCount * LaneLen * Factor + i; | |||
15146 | if (Mask[IdxI] >= 0) { | |||
15147 | Ops.push_back(Builder.CreateShuffleVector( | |||
15148 | Op0, Op1, createSequentialMask(Builder, Mask[IdxI], LaneLen, 0))); | |||
15149 | } else { | |||
15150 | unsigned StartMask = 0; | |||
15151 | for (unsigned j = 1; j < LaneLen; j++) { | |||
15152 | unsigned IdxJ = StoreCount * LaneLen * Factor + j; | |||
15153 | if (Mask[IdxJ * Factor + IdxI] >= 0) { | |||
15154 | StartMask = Mask[IdxJ * Factor + IdxI] - IdxJ; | |||
15155 | break; | |||
15156 | } | |||
15157 | } | |||
15158 | // Note: If all elements in a chunk are undefs, StartMask=0! | |||
15159 | // Note: Filling undef gaps with random elements is ok, since | |||
15160 | // those elements were being written anyway (with undefs). | |||
15161 | // In the case of all undefs we're defaulting to using elems from 0 | |||
15162 | // Note: StartMask cannot be negative, it's checked in | |||
15163 | // isReInterleaveMask | |||
15164 | Ops.push_back(Builder.CreateShuffleVector( | |||
15165 | Op0, Op1, createSequentialMask(Builder, StartMask, LaneLen, 0))); | |||
15166 | } | |||
15167 | } | |||
15168 | ||||
15169 | Ops.push_back(Builder.getInt32(SI->getAlignment())); | |||
15170 | Builder.CreateCall(VstNFunc, Ops); | |||
15171 | } | |||
15172 | return true; | |||
15173 | } | |||
15174 | ||||
15175 | enum HABaseType { | |||
15176 | HA_UNKNOWN = 0, | |||
15177 | HA_FLOAT, | |||
15178 | HA_DOUBLE, | |||
15179 | HA_VECT64, | |||
15180 | HA_VECT128 | |||
15181 | }; | |||
15182 | ||||
15183 | static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base, | |||
15184 | uint64_t &Members) { | |||
15185 | if (auto *ST = dyn_cast<StructType>(Ty)) { | |||
15186 | for (unsigned i = 0; i < ST->getNumElements(); ++i) { | |||
15187 | uint64_t SubMembers = 0; | |||
15188 | if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers)) | |||
15189 | return false; | |||
15190 | Members += SubMembers; | |||
15191 | } | |||
15192 | } else if (auto *AT = dyn_cast<ArrayType>(Ty)) { | |||
15193 | uint64_t SubMembers = 0; | |||
15194 | if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers)) | |||
15195 | return false; | |||
15196 | Members += SubMembers * AT->getNumElements(); | |||
15197 | } else if (Ty->isFloatTy()) { | |||
15198 | if (Base != HA_UNKNOWN && Base != HA_FLOAT) | |||
15199 | return false; | |||
15200 | Members = 1; | |||
15201 | Base = HA_FLOAT; | |||
15202 | } else if (Ty->isDoubleTy()) { | |||
15203 | if (Base != HA_UNKNOWN && Base != HA_DOUBLE) | |||
15204 | return false; | |||
15205 | Members = 1; | |||
15206 | Base = HA_DOUBLE; | |||
15207 | } else if (auto *VT = dyn_cast<VectorType>(Ty)) { | |||
15208 | Members = 1; | |||
15209 | switch (Base) { | |||
15210 | case HA_FLOAT: | |||
15211 | case HA_DOUBLE: | |||
15212 | return false; | |||
15213 | case HA_VECT64: | |||
15214 | return VT->getBitWidth() == 64; | |||
15215 | case HA_VECT128: | |||
15216 | return VT->getBitWidth() == 128; | |||
15217 | case HA_UNKNOWN: | |||
15218 | switch (VT->getBitWidth()) { | |||
15219 | case 64: | |||
15220 | Base = HA_VECT64; | |||
15221 | return true; | |||
15222 | case 128: | |||
15223 | Base = HA_VECT128; | |||
15224 | return true; | |||
15225 | default: | |||
15226 | return false; | |||
15227 | } | |||
15228 | } | |||
15229 | } | |||
15230 | ||||
15231 | return (Members > 0 && Members <= 4); | |||
15232 | } | |||
15233 | ||||
15234 | /// Return the correct alignment for the current calling convention. | |||
15235 | unsigned | |||
15236 | ARMTargetLowering::getABIAlignmentForCallingConv(Type *ArgTy, | |||
15237 | DataLayout DL) const { | |||
15238 | if (!ArgTy->isVectorTy()) | |||
15239 | return DL.getABITypeAlignment(ArgTy); | |||
15240 | ||||
15241 | // Avoid over-aligning vector parameters. It would require realigning the | |||
15242 | // stack and waste space for no real benefit. | |||
15243 | return std::min(DL.getABITypeAlignment(ArgTy), DL.getStackAlignment()); | |||
15244 | } | |||
15245 | ||||
15246 | /// Return true if a type is an AAPCS-VFP homogeneous aggregate or one of | |||
15247 | /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when | |||
15248 | /// passing according to AAPCS rules. | |||
15249 | bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters( | |||
15250 | Type *Ty, CallingConv::ID CallConv, bool isVarArg) const { | |||
15251 | if (getEffectiveCallingConv(CallConv, isVarArg) != | |||
15252 | CallingConv::ARM_AAPCS_VFP) | |||
15253 | return false; | |||
15254 | ||||
15255 | HABaseType Base = HA_UNKNOWN; | |||
15256 | uint64_t Members = 0; | |||
15257 | bool IsHA = isHomogeneousAggregate(Ty, Base, Members); | |||
15258 | LLVM_DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("arm-isel")) { dbgs() << "isHA: " << IsHA << " "; Ty->dump(); } } while (false); | |||
15259 | ||||
15260 | bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy(); | |||
15261 | return IsHA || IsIntArray; | |||
15262 | } | |||
15263 | ||||
15264 | unsigned ARMTargetLowering::getExceptionPointerRegister( | |||
15265 | const Constant *PersonalityFn) const { | |||
15266 | // Platforms which do not use SjLj EH may return values in these registers | |||
15267 | // via the personality function. | |||
15268 | return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R0; | |||
15269 | } | |||
15270 | ||||
15271 | unsigned ARMTargetLowering::getExceptionSelectorRegister( | |||
15272 | const Constant *PersonalityFn) const { | |||
15273 | // Platforms which do not use SjLj EH may return values in these registers | |||
15274 | // via the personality function. | |||
15275 | return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R1; | |||
15276 | } | |||
15277 | ||||
15278 | void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const { | |||
15279 | // Update IsSplitCSR in ARMFunctionInfo. | |||
15280 | ARMFunctionInfo *AFI = Entry->getParent()->getInfo<ARMFunctionInfo>(); | |||
15281 | AFI->setIsSplitCSR(true); | |||
15282 | } | |||
15283 | ||||
15284 | void ARMTargetLowering::insertCopiesSplitCSR( | |||
15285 | MachineBasicBlock *Entry, | |||
15286 | const SmallVectorImpl<MachineBasicBlock *> &Exits) const { | |||
15287 | const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); | |||
15288 | const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent()); | |||
15289 | if (!IStart) | |||
15290 | return; | |||
15291 | ||||
15292 | const TargetInstrInfo *TII = Subtarget->getInstrInfo(); | |||
15293 | MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo(); | |||
15294 | MachineBasicBlock::iterator MBBI = Entry->begin(); | |||
15295 | for (const MCPhysReg *I = IStart; *I; ++I) { | |||
15296 | const TargetRegisterClass *RC = nullptr; | |||
15297 | if (ARM::GPRRegClass.contains(*I)) | |||
15298 | RC = &ARM::GPRRegClass; | |||
15299 | else if (ARM::DPRRegClass.contains(*I)) | |||
15300 | RC = &ARM::DPRRegClass; | |||
15301 | else | |||
15302 | llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15302); | |||
15303 | ||||
15304 | unsigned NewVR = MRI->createVirtualRegister(RC); | |||
15305 | // Create copy from CSR to a virtual register. | |||
15306 | // FIXME: this currently does not emit CFI pseudo-instructions, it works | |||
15307 | // fine for CXX_FAST_TLS since the C++-style TLS access functions should be | |||
15308 | // nounwind. If we want to generalize this later, we may need to emit | |||
15309 | // CFI pseudo-instructions. | |||
15310 | assert(Entry->getParent()->getFunction().hasFnAttribute(((Entry->getParent()->getFunction().hasFnAttribute( Attribute ::NoUnwind) && "Function should be nounwind in insertCopiesSplitCSR!" ) ? static_cast<void> (0) : __assert_fail ("Entry->getParent()->getFunction().hasFnAttribute( Attribute::NoUnwind) && \"Function should be nounwind in insertCopiesSplitCSR!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15312, __PRETTY_FUNCTION__)) | |||
15311 | Attribute::NoUnwind) &&((Entry->getParent()->getFunction().hasFnAttribute( Attribute ::NoUnwind) && "Function should be nounwind in insertCopiesSplitCSR!" ) ? static_cast<void> (0) : __assert_fail ("Entry->getParent()->getFunction().hasFnAttribute( Attribute::NoUnwind) && \"Function should be nounwind in insertCopiesSplitCSR!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15312, __PRETTY_FUNCTION__)) | |||
15312 | "Function should be nounwind in insertCopiesSplitCSR!")((Entry->getParent()->getFunction().hasFnAttribute( Attribute ::NoUnwind) && "Function should be nounwind in insertCopiesSplitCSR!" ) ? static_cast<void> (0) : __assert_fail ("Entry->getParent()->getFunction().hasFnAttribute( Attribute::NoUnwind) && \"Function should be nounwind in insertCopiesSplitCSR!\"" , "/build/llvm-toolchain-snapshot-9~svn361465/lib/Target/ARM/ARMISelLowering.cpp" , 15312, __PRETTY_FUNCTION__)); | |||
15313 | Entry->addLiveIn(*I); | |||
15314 | BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) | |||
15315 | .addReg(*I); | |||
15316 | ||||
15317 | // Insert the copy-back instructions right before the terminator. | |||
15318 | for (auto *Exit : Exits) | |||
15319 | BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(), | |||
15320 | TII->get(TargetOpcode::COPY), *I) | |||
15321 | .addReg(NewVR); | |||
15322 | } | |||
15323 | } | |||
15324 | ||||
15325 | void ARMTargetLowering::finalizeLowering(MachineFunction &MF) const { | |||
15326 | MF.getFrameInfo().computeMaxCallFrameSize(MF); | |||
15327 | TargetLoweringBase::finalizeLowering(MF); | |||
15328 | } |