Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 7034, column 14
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp -faddrsig
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/Type.h"
84#include "llvm/IR/User.h"
85#include "llvm/IR/Value.h"
86#include "llvm/MC/MCInstrDesc.h"
87#include "llvm/MC/MCInstrItineraries.h"
88#include "llvm/MC/MCRegisterInfo.h"
89#include "llvm/MC/MCSchedule.h"
90#include "llvm/Support/AtomicOrdering.h"
91#include "llvm/Support/BranchProbability.h"
92#include "llvm/Support/Casting.h"
93#include "llvm/Support/CodeGen.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/ErrorHandling.h"
98#include "llvm/Support/KnownBits.h"
99#include "llvm/Support/MachineValueType.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311 }
312
313 // These libcalls are not available in 32-bit.
314 setLibcallName(RTLIB::SHL_I128, nullptr);
315 setLibcallName(RTLIB::SRL_I128, nullptr);
316 setLibcallName(RTLIB::SRA_I128, nullptr);
317
318 // RTLIB
319 if (Subtarget->isAAPCS_ABI() &&
320 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
321 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
322 static const struct {
323 const RTLIB::Libcall Op;
324 const char * const Name;
325 const CallingConv::ID CC;
326 const ISD::CondCode Cond;
327 } LibraryCalls[] = {
328 // Double-precision floating-point arithmetic helper functions
329 // RTABI chapter 4.1.2, Table 2
330 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334
335 // Double-precision floating-point comparison helper functions
336 // RTABI chapter 4.1.2, Table 3
337 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
338 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
339 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
340 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
341 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
342 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
343 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
344 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
345
346 // Single-precision floating-point arithmetic helper functions
347 // RTABI chapter 4.1.2, Table 4
348 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352
353 // Single-precision floating-point comparison helper functions
354 // RTABI chapter 4.1.2, Table 5
355 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
356 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
357 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
358 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
359 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
360 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
361 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
362 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
363
364 // Floating-point to integer conversions.
365 // RTABI chapter 4.1.2, Table 6
366 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
368 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
369 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
371 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
372 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
373 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374
375 // Conversions between floating types.
376 // RTABI chapter 4.1.2, Table 7
377 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380
381 // Integer to floating-point conversions.
382 // RTABI chapter 4.1.2, Table 8
383 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
384 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
388 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
389 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
390 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391
392 // Long long helper functions
393 // RTABI chapter 4.2, Table 9
394 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Integer division functions
400 // RTABI chapter 4.3.1
401 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
406 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
407 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
408 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 };
410
411 for (const auto &LC : LibraryCalls) {
412 setLibcallName(LC.Op, LC.Name);
413 setLibcallCallingConv(LC.Op, LC.CC);
414 if (LC.Cond != ISD::SETCC_INVALID)
415 setCmpLibcallCC(LC.Op, LC.Cond);
416 }
417
418 // EABI dependent RTLIB
419 if (TM.Options.EABIVersion == EABI::EABI4 ||
420 TM.Options.EABIVersion == EABI::EABI5) {
421 static const struct {
422 const RTLIB::Libcall Op;
423 const char *const Name;
424 const CallingConv::ID CC;
425 const ISD::CondCode Cond;
426 } MemOpsLibraryCalls[] = {
427 // Memory operations
428 // RTABI chapter 4.3.4
429 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
430 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
431 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
432 };
433
434 for (const auto &LC : MemOpsLibraryCalls) {
435 setLibcallName(LC.Op, LC.Name);
436 setLibcallCallingConv(LC.Op, LC.CC);
437 if (LC.Cond != ISD::SETCC_INVALID)
438 setCmpLibcallCC(LC.Op, LC.Cond);
439 }
440 }
441 }
442
443 if (Subtarget->isTargetWindows()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const CallingConv::ID CC;
448 } LibraryCalls[] = {
449 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
450 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
451 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
452 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
453 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
454 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
455 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
456 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
457 };
458
459 for (const auto &LC : LibraryCalls) {
460 setLibcallName(LC.Op, LC.Name);
461 setLibcallCallingConv(LC.Op, LC.CC);
462 }
463 }
464
465 // Use divmod compiler-rt calls for iOS 5.0 and later.
466 if (Subtarget->isTargetMachO() &&
467 !(Subtarget->isTargetIOS() &&
468 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
469 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
470 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
471 }
472
473 // The half <-> float conversion functions are always soft-float on
474 // non-watchos platforms, but are needed for some targets which use a
475 // hard-float calling convention by default.
476 if (!Subtarget->isTargetWatchABI()) {
477 if (Subtarget->isAAPCS_ABI()) {
478 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
479 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
480 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
481 } else {
482 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
483 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
484 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
485 }
486 }
487
488 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
489 // a __gnu_ prefix (which is the default).
490 if (Subtarget->isTargetAEABI()) {
491 static const struct {
492 const RTLIB::Libcall Op;
493 const char * const Name;
494 const CallingConv::ID CC;
495 } LibraryCalls[] = {
496 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
497 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
498 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
499 };
500
501 for (const auto &LC : LibraryCalls) {
502 setLibcallName(LC.Op, LC.Name);
503 setLibcallCallingConv(LC.Op, LC.CC);
504 }
505 }
506
507 if (Subtarget->isThumb1Only())
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
509 else
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
511
512 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
513 !Subtarget->isThumb1Only()) {
514 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
515 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
516 }
517
518 if (Subtarget->hasFullFP16()) {
519 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
520 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
522 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
523
524 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
526 }
527
528 for (MVT VT : MVT::vector_valuetypes()) {
529 for (MVT InnerVT : MVT::vector_valuetypes()) {
530 setTruncStoreAction(VT, InnerVT, Expand);
531 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
532 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
533 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
534 }
535
536 setOperationAction(ISD::MULHS, VT, Expand);
537 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
538 setOperationAction(ISD::MULHU, VT, Expand);
539 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
540
541 setOperationAction(ISD::BSWAP, VT, Expand);
542 }
543
544 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
546
547 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
548 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
549
550 if (Subtarget->hasNEON()) {
551 addDRTypeForNEON(MVT::v2f32);
552 addDRTypeForNEON(MVT::v8i8);
553 addDRTypeForNEON(MVT::v4i16);
554 addDRTypeForNEON(MVT::v2i32);
555 addDRTypeForNEON(MVT::v1i64);
556
557 addQRTypeForNEON(MVT::v4f32);
558 addQRTypeForNEON(MVT::v2f64);
559 addQRTypeForNEON(MVT::v16i8);
560 addQRTypeForNEON(MVT::v8i16);
561 addQRTypeForNEON(MVT::v4i32);
562 addQRTypeForNEON(MVT::v2i64);
563
564 if (Subtarget->hasFullFP16()) {
565 addQRTypeForNEON(MVT::v8f16);
566 addDRTypeForNEON(MVT::v4f16);
567 }
568
569 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
570 // neither Neon nor VFP support any arithmetic operations on it.
571 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
572 // supported for v4f32.
573 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
574 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
575 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
576 // FIXME: Code duplication: FDIV and FREM are expanded always, see
577 // ARMTargetLowering::addTypeForNEON method for details.
578 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
580 // FIXME: Create unittest.
581 // In another words, find a way when "copysign" appears in DAG with vector
582 // operands.
583 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
584 // FIXME: Code duplication: SETCC has custom operation action, see
585 // ARMTargetLowering::addTypeForNEON method for details.
586 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
587 // FIXME: Create unittest for FNEG and for FABS.
588 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
589 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
591 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
593 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
596 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
599 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
600 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
601 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
602 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
604 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
605 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
606
607 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
608 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
610 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
613 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
616 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
617 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
618 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
621
622 // Mark v2f32 intrinsics.
623 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
624 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
626 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
629 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
632 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
633 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
634 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
636 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
637
638 // Neon does not support some operations on v1i64 and v2i64 types.
639 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
640 // Custom handling for some quad-vector types to detect VMULL.
641 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
642 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
643 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
644 // Custom handling for some vector types to avoid expensive expansions
645 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
646 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
647 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
648 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
649 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
650 // a destination type that is wider than the source, and nor does
651 // it have a FP_TO_[SU]INT instruction with a narrower destination than
652 // source.
653 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
655 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
656 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
657 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
658 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
659 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
660 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
661
662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
663 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
664
665 // NEON does not have single instruction CTPOP for vectors with element
666 // types wider than 8-bits. However, custom lowering can leverage the
667 // v8i8/v16i8 vcnt instruction.
668 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
670 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
671 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
672 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
673 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
674
675 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
676 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
677
678 // NEON does not have single instruction CTTZ for vectors.
679 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
683
684 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
685 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
686 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
687 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
688
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
693
694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
696 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
697 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
698
699 // NEON only has FMA instructions as of VFP4.
700 if (!Subtarget->hasVFP4()) {
701 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
702 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
703 }
704
705 setTargetDAGCombine(ISD::INTRINSIC_VOID);
706 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
707 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
708 setTargetDAGCombine(ISD::SHL);
709 setTargetDAGCombine(ISD::SRL);
710 setTargetDAGCombine(ISD::SRA);
711 setTargetDAGCombine(ISD::SIGN_EXTEND);
712 setTargetDAGCombine(ISD::ZERO_EXTEND);
713 setTargetDAGCombine(ISD::ANY_EXTEND);
714 setTargetDAGCombine(ISD::BUILD_VECTOR);
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
717 setTargetDAGCombine(ISD::STORE);
718 setTargetDAGCombine(ISD::FP_TO_SINT);
719 setTargetDAGCombine(ISD::FP_TO_UINT);
720 setTargetDAGCombine(ISD::FDIV);
721 setTargetDAGCombine(ISD::LOAD);
722
723 // It is legal to extload from v4i8 to v4i16 or v4i32.
724 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
725 MVT::v2i32}) {
726 for (MVT VT : MVT::integer_vector_valuetypes()) {
727 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
728 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
729 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
730 }
731 }
732 }
733
734 if (Subtarget->isFPOnlySP()) {
735 // When targeting a floating-point unit with only single-precision
736 // operations, f64 is legal for the few double-precision instructions which
737 // are present However, no double-precision operations other than moves,
738 // loads and stores are provided by the hardware.
739 setOperationAction(ISD::FADD, MVT::f64, Expand);
740 setOperationAction(ISD::FSUB, MVT::f64, Expand);
741 setOperationAction(ISD::FMUL, MVT::f64, Expand);
742 setOperationAction(ISD::FMA, MVT::f64, Expand);
743 setOperationAction(ISD::FDIV, MVT::f64, Expand);
744 setOperationAction(ISD::FREM, MVT::f64, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
747 setOperationAction(ISD::FNEG, MVT::f64, Expand);
748 setOperationAction(ISD::FABS, MVT::f64, Expand);
749 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
750 setOperationAction(ISD::FSIN, MVT::f64, Expand);
751 setOperationAction(ISD::FCOS, MVT::f64, Expand);
752 setOperationAction(ISD::FPOW, MVT::f64, Expand);
753 setOperationAction(ISD::FLOG, MVT::f64, Expand);
754 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
755 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
756 setOperationAction(ISD::FEXP, MVT::f64, Expand);
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
760 setOperationAction(ISD::FRINT, MVT::f64, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
762 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
766 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
768 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
770 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
771 }
772
773 computeRegisterProperties(Subtarget->getRegisterInfo());
774
775 // ARM does not have floating-point extending loads.
776 for (MVT VT : MVT::fp_valuetypes()) {
777 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
778 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
779 }
780
781 // ... or truncating stores
782 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
783 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
784 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
785
786 // ARM does not have i1 sign extending load.
787 for (MVT VT : MVT::integer_valuetypes())
788 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
789
790 // ARM supports all 4 flavors of integer indexed load / store.
791 if (!Subtarget->isThumb1Only()) {
792 for (unsigned im = (unsigned)ISD::PRE_INC;
793 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
794 setIndexedLoadAction(im, MVT::i1, Legal);
795 setIndexedLoadAction(im, MVT::i8, Legal);
796 setIndexedLoadAction(im, MVT::i16, Legal);
797 setIndexedLoadAction(im, MVT::i32, Legal);
798 setIndexedStoreAction(im, MVT::i1, Legal);
799 setIndexedStoreAction(im, MVT::i8, Legal);
800 setIndexedStoreAction(im, MVT::i16, Legal);
801 setIndexedStoreAction(im, MVT::i32, Legal);
802 }
803 } else {
804 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
805 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
806 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
807 }
808
809 setOperationAction(ISD::SADDO, MVT::i32, Custom);
810 setOperationAction(ISD::UADDO, MVT::i32, Custom);
811 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
812 setOperationAction(ISD::USUBO, MVT::i32, Custom);
813
814 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
815 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
816
817 // i64 operation support.
818 setOperationAction(ISD::MUL, MVT::i64, Expand);
819 setOperationAction(ISD::MULHU, MVT::i32, Expand);
820 if (Subtarget->isThumb1Only()) {
821 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
822 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
823 }
824 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
825 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
826 setOperationAction(ISD::MULHS, MVT::i32, Expand);
827
828 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
829 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
830 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
831 setOperationAction(ISD::SRL, MVT::i64, Custom);
832 setOperationAction(ISD::SRA, MVT::i64, Custom);
833 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
834
835 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
836 if (Subtarget->isThumb1Only()) {
837 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
838 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
839 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
840 }
841
842 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
844
845 // ARM does not have ROTL.
846 setOperationAction(ISD::ROTL, MVT::i32, Expand);
847 for (MVT VT : MVT::vector_valuetypes()) {
848 setOperationAction(ISD::ROTL, VT, Expand);
849 setOperationAction(ISD::ROTR, VT, Expand);
850 }
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
853 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
856 }
857
858 // @llvm.readcyclecounter requires the Performance Monitors extension.
859 // Default to the 0 expansion on unsupported platforms.
860 // FIXME: Technically there are older ARM CPUs that have
861 // implementation-specific ways of obtaining this information.
862 if (Subtarget->hasPerfMon())
863 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
864
865 // Only ARMv6 has BSWAP.
866 if (!Subtarget->hasV6Ops())
867 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
868
869 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
870 : Subtarget->hasDivideInARMMode();
871 if (!hasDivide) {
872 // These are expanded into libcalls if the cpu doesn't have HW divider.
873 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
874 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
875 }
876
877 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
878 setOperationAction(ISD::SDIV, MVT::i32, Custom);
879 setOperationAction(ISD::UDIV, MVT::i32, Custom);
880
881 setOperationAction(ISD::SDIV, MVT::i64, Custom);
882 setOperationAction(ISD::UDIV, MVT::i64, Custom);
883 }
884
885 setOperationAction(ISD::SREM, MVT::i32, Expand);
886 setOperationAction(ISD::UREM, MVT::i32, Expand);
887
888 // Register based DivRem for AEABI (RTABI 4.2)
889 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
890 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
891 Subtarget->isTargetWindows()) {
892 setOperationAction(ISD::SREM, MVT::i64, Custom);
893 setOperationAction(ISD::UREM, MVT::i64, Custom);
894 HasStandaloneRem = false;
895
896 if (Subtarget->isTargetWindows()) {
897 const struct {
898 const RTLIB::Libcall Op;
899 const char * const Name;
900 const CallingConv::ID CC;
901 } LibraryCalls[] = {
902 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
903 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
904 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
905 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
906
907 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
908 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
909 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
910 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
911 };
912
913 for (const auto &LC : LibraryCalls) {
914 setLibcallName(LC.Op, LC.Name);
915 setLibcallCallingConv(LC.Op, LC.CC);
916 }
917 } else {
918 const struct {
919 const RTLIB::Libcall Op;
920 const char * const Name;
921 const CallingConv::ID CC;
922 } LibraryCalls[] = {
923 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
925 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
926 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
927
928 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
930 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
931 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
932 };
933
934 for (const auto &LC : LibraryCalls) {
935 setLibcallName(LC.Op, LC.Name);
936 setLibcallCallingConv(LC.Op, LC.CC);
937 }
938 }
939
940 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
941 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
942 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
943 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
944 } else {
945 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
946 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
947 }
948
949 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
950 for (auto &VT : {MVT::f32, MVT::f64})
951 setOperationAction(ISD::FPOWI, VT, Custom);
952
953 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
954 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
955 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
956 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
957
958 setOperationAction(ISD::TRAP, MVT::Other, Legal);
959 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
960
961 // Use the default implementation.
962 setOperationAction(ISD::VASTART, MVT::Other, Custom);
963 setOperationAction(ISD::VAARG, MVT::Other, Expand);
964 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
965 setOperationAction(ISD::VAEND, MVT::Other, Expand);
966 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
967 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
968
969 if (Subtarget->isTargetWindows())
970 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
971 else
972 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
973
974 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
975 // the default expansion.
976 InsertFencesForAtomic = false;
977 if (Subtarget->hasAnyDataBarrier() &&
978 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
979 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
980 // to ldrex/strex loops already.
981 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
982 if (!Subtarget->isThumb() || !Subtarget->isMClass())
983 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
984
985 // On v8, we have particularly efficient implementations of atomic fences
986 // if they can be combined with nearby atomic loads and stores.
987 if (!Subtarget->hasAcquireRelease() ||
988 getTargetMachine().getOptLevel() == 0) {
989 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
990 InsertFencesForAtomic = true;
991 }
992 } else {
993 // If there's anything we can use as a barrier, go through custom lowering
994 // for ATOMIC_FENCE.
995 // If target has DMB in thumb, Fences can be inserted.
996 if (Subtarget->hasDataBarrier())
997 InsertFencesForAtomic = true;
998
999 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1000 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1001
1002 // Set them all for expansion, which will force libcalls.
1003 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1011 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1012 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1013 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1014 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1015 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1016 // Unordered/Monotonic case.
1017 if (!InsertFencesForAtomic) {
1018 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1019 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1020 }
1021 }
1022
1023 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1024
1025 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1026 if (!Subtarget->hasV6Ops()) {
1027 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1028 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1029 }
1030 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1031
1032 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1033 !Subtarget->isThumb1Only()) {
1034 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1035 // iff target supports vfp2.
1036 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1037 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1038 }
1039
1040 // We want to custom lower some of our intrinsics.
1041 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1042 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1043 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1044 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1045 if (Subtarget->useSjLjEH())
1046 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1047
1048 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1049 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1050 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1051 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1052 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1053 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1054 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1055 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1056 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1057 if (Subtarget->hasFullFP16()) {
1058 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1059 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1060 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1061 }
1062
1063 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1064
1065 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1066 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1067 if (Subtarget->hasFullFP16())
1068 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1069 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1070 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1071 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1072
1073 // We don't support sin/cos/fmod/copysign/pow
1074 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1075 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1076 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1077 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1078 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1079 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1080 setOperationAction(ISD::FREM, MVT::f64, Expand);
1081 setOperationAction(ISD::FREM, MVT::f32, Expand);
1082 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1083 !Subtarget->isThumb1Only()) {
1084 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1085 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1086 }
1087 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1088 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1089
1090 if (!Subtarget->hasVFP4()) {
1091 setOperationAction(ISD::FMA, MVT::f64, Expand);
1092 setOperationAction(ISD::FMA, MVT::f32, Expand);
1093 }
1094
1095 // Various VFP goodness
1096 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1097 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1098 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1099 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1100 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1101 }
1102
1103 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1104 if (!Subtarget->hasFP16()) {
1105 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1106 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1107 }
1108 }
1109
1110 // Use __sincos_stret if available.
1111 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1112 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1113 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1114 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1115 }
1116
1117 // FP-ARMv8 implements a lot of rounding-like FP operations.
1118 if (Subtarget->hasFPARMv8()) {
1119 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1120 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1121 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1122 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1123 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1124 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1125 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1126 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1127 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1128 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1129 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1130 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1131
1132 if (!Subtarget->isFPOnlySP()) {
1133 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1135 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1138 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1139 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1140 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1141 }
1142 }
1143
1144 if (Subtarget->hasNEON()) {
1145 // vmin and vmax aren't available in a scalar form, so we use
1146 // a NEON instruction with an undef lane instead.
1147 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1148 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1149 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1150 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1151 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1152 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1153 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1154 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1155
1156 if (Subtarget->hasFullFP16()) {
1157 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1158 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1159 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1160 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1161
1162 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1163 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1164 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1165 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1166 }
1167 }
1168
1169 // We have target-specific dag combine patterns for the following nodes:
1170 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1171 setTargetDAGCombine(ISD::ADD);
1172 setTargetDAGCombine(ISD::SUB);
1173 setTargetDAGCombine(ISD::MUL);
1174 setTargetDAGCombine(ISD::AND);
1175 setTargetDAGCombine(ISD::OR);
1176 setTargetDAGCombine(ISD::XOR);
1177
1178 if (Subtarget->hasV6Ops())
1179 setTargetDAGCombine(ISD::SRL);
1180
1181 setStackPointerRegisterToSaveRestore(ARM::SP);
1182
1183 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1184 !Subtarget->hasVFP2())
1185 setSchedulingPreference(Sched::RegPressure);
1186 else
1187 setSchedulingPreference(Sched::Hybrid);
1188
1189 //// temporary - rewrite interface to use type
1190 MaxStoresPerMemset = 8;
1191 MaxStoresPerMemsetOptSize = 4;
1192 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1193 MaxStoresPerMemcpyOptSize = 2;
1194 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1195 MaxStoresPerMemmoveOptSize = 2;
1196
1197 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1198 // are at least 4 bytes aligned.
1199 setMinStackArgumentAlignment(4);
1200
1201 // Prefer likely predicted branches to selects on out-of-order cores.
1202 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1203
1204 setPrefLoopAlignment(Subtarget->getPrefLoopAlignment());
1205
1206 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1207}
1208
1209bool ARMTargetLowering::useSoftFloat() const {
1210 return Subtarget->useSoftFloat();
1211}
1212
1213// FIXME: It might make sense to define the representative register class as the
1214// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1215// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1216// SPR's representative would be DPR_VFP2. This should work well if register
1217// pressure tracking were modified such that a register use would increment the
1218// pressure of the register class's representative and all of it's super
1219// classes' representatives transitively. We have not implemented this because
1220// of the difficulty prior to coalescing of modeling operand register classes
1221// due to the common occurrence of cross class copies and subregister insertions
1222// and extractions.
1223std::pair<const TargetRegisterClass *, uint8_t>
1224ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1225 MVT VT) const {
1226 const TargetRegisterClass *RRC = nullptr;
1227 uint8_t Cost = 1;
1228 switch (VT.SimpleTy) {
1229 default:
1230 return TargetLowering::findRepresentativeClass(TRI, VT);
1231 // Use DPR as representative register class for all floating point
1232 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1233 // the cost is 1 for both f32 and f64.
1234 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1235 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1236 RRC = &ARM::DPRRegClass;
1237 // When NEON is used for SP, only half of the register file is available
1238 // because operations that define both SP and DP results will be constrained
1239 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1240 // coalescing by double-counting the SP regs. See the FIXME above.
1241 if (Subtarget->useNEONForSinglePrecisionFP())
1242 Cost = 2;
1243 break;
1244 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1245 case MVT::v4f32: case MVT::v2f64:
1246 RRC = &ARM::DPRRegClass;
1247 Cost = 2;
1248 break;
1249 case MVT::v4i64:
1250 RRC = &ARM::DPRRegClass;
1251 Cost = 4;
1252 break;
1253 case MVT::v8i64:
1254 RRC = &ARM::DPRRegClass;
1255 Cost = 8;
1256 break;
1257 }
1258 return std::make_pair(RRC, Cost);
1259}
1260
1261const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1262 switch ((ARMISD::NodeType)Opcode) {
1263 case ARMISD::FIRST_NUMBER: break;
1264 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1265 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1266 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1267 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1268 case ARMISD::CALL: return "ARMISD::CALL";
1269 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1270 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1271 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1272 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1273 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1274 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1275 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1276 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1277 case ARMISD::CMP: return "ARMISD::CMP";
1278 case ARMISD::CMN: return "ARMISD::CMN";
1279 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1280 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1281 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1282 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1283 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1284
1285 case ARMISD::CMOV: return "ARMISD::CMOV";
1286 case ARMISD::SUBS: return "ARMISD::SUBS";
1287
1288 case ARMISD::SSAT: return "ARMISD::SSAT";
1289 case ARMISD::USAT: return "ARMISD::USAT";
1290
1291 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1292 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1293 case ARMISD::RRX: return "ARMISD::RRX";
1294
1295 case ARMISD::ADDC: return "ARMISD::ADDC";
1296 case ARMISD::ADDE: return "ARMISD::ADDE";
1297 case ARMISD::SUBC: return "ARMISD::SUBC";
1298 case ARMISD::SUBE: return "ARMISD::SUBE";
1299
1300 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1301 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1302 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1303 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1304 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1305
1306 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1307 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1308 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1309
1310 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1311
1312 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1313
1314 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1315
1316 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1317
1318 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1319
1320 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1321 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1322
1323 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1324 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1325 case ARMISD::VCGE: return "ARMISD::VCGE";
1326 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1327 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1328 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1329 case ARMISD::VCGT: return "ARMISD::VCGT";
1330 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1331 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1332 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1333 case ARMISD::VTST: return "ARMISD::VTST";
1334
1335 case ARMISD::VSHL: return "ARMISD::VSHL";
1336 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1337 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1338 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1339 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1340 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1341 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1342 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1343 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1344 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1345 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1346 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1347 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1348 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1349 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1350 case ARMISD::VSLI: return "ARMISD::VSLI";
1351 case ARMISD::VSRI: return "ARMISD::VSRI";
1352 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1353 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1354 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1355 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1356 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1357 case ARMISD::VDUP: return "ARMISD::VDUP";
1358 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1359 case ARMISD::VEXT: return "ARMISD::VEXT";
1360 case ARMISD::VREV64: return "ARMISD::VREV64";
1361 case ARMISD::VREV32: return "ARMISD::VREV32";
1362 case ARMISD::VREV16: return "ARMISD::VREV16";
1363 case ARMISD::VZIP: return "ARMISD::VZIP";
1364 case ARMISD::VUZP: return "ARMISD::VUZP";
1365 case ARMISD::VTRN: return "ARMISD::VTRN";
1366 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1367 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1368 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1369 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1370 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1371 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1372 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1373 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1374 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1375 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1376 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1377 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1378 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1379 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1380 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1381 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1382 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1383 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1384 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1385 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1386 case ARMISD::BFI: return "ARMISD::BFI";
1387 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1388 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1389 case ARMISD::VBSL: return "ARMISD::VBSL";
1390 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1391 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1392 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1393 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1394 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1395 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1396 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1397 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1398 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1399 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1400 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1401 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1402 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1403 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1404 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1405 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1406 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1407 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1408 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1409 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1410 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1411 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1412 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1413 }
1414 return nullptr;
1415}
1416
1417EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1418 EVT VT) const {
1419 if (!VT.isVector())
1420 return getPointerTy(DL);
1421 return VT.changeVectorElementTypeToInteger();
1422}
1423
1424/// getRegClassFor - Return the register class that should be used for the
1425/// specified value type.
1426const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1427 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1428 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1429 // load / store 4 to 8 consecutive D registers.
1430 if (Subtarget->hasNEON()) {
1431 if (VT == MVT::v4i64)
1432 return &ARM::QQPRRegClass;
1433 if (VT == MVT::v8i64)
1434 return &ARM::QQQQPRRegClass;
1435 }
1436 return TargetLowering::getRegClassFor(VT);
1437}
1438
1439// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1440// source/dest is aligned and the copy size is large enough. We therefore want
1441// to align such objects passed to memory intrinsics.
1442bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1443 unsigned &PrefAlign) const {
1444 if (!isa<MemIntrinsic>(CI))
1445 return false;
1446 MinSize = 8;
1447 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1448 // cycle faster than 4-byte aligned LDM.
1449 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1450 return true;
1451}
1452
1453// Create a fast isel object.
1454FastISel *
1455ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1456 const TargetLibraryInfo *libInfo) const {
1457 return ARM::createFastISel(funcInfo, libInfo);
1458}
1459
1460Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1461 unsigned NumVals = N->getNumValues();
1462 if (!NumVals)
1463 return Sched::RegPressure;
1464
1465 for (unsigned i = 0; i != NumVals; ++i) {
1466 EVT VT = N->getValueType(i);
1467 if (VT == MVT::Glue || VT == MVT::Other)
1468 continue;
1469 if (VT.isFloatingPoint() || VT.isVector())
1470 return Sched::ILP;
1471 }
1472
1473 if (!N->isMachineOpcode())
1474 return Sched::RegPressure;
1475
1476 // Load are scheduled for latency even if there instruction itinerary
1477 // is not available.
1478 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1479 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1480
1481 if (MCID.getNumDefs() == 0)
1482 return Sched::RegPressure;
1483 if (!Itins->isEmpty() &&
1484 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1485 return Sched::ILP;
1486
1487 return Sched::RegPressure;
1488}
1489
1490//===----------------------------------------------------------------------===//
1491// Lowering Code
1492//===----------------------------------------------------------------------===//
1493
1494static bool isSRL16(const SDValue &Op) {
1495 if (Op.getOpcode() != ISD::SRL)
1496 return false;
1497 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1498 return Const->getZExtValue() == 16;
1499 return false;
1500}
1501
1502static bool isSRA16(const SDValue &Op) {
1503 if (Op.getOpcode() != ISD::SRA)
1504 return false;
1505 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1506 return Const->getZExtValue() == 16;
1507 return false;
1508}
1509
1510static bool isSHL16(const SDValue &Op) {
1511 if (Op.getOpcode() != ISD::SHL)
1512 return false;
1513 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1514 return Const->getZExtValue() == 16;
1515 return false;
1516}
1517
1518// Check for a signed 16-bit value. We special case SRA because it makes it
1519// more simple when also looking for SRAs that aren't sign extending a
1520// smaller value. Without the check, we'd need to take extra care with
1521// checking order for some operations.
1522static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1523 if (isSRA16(Op))
1524 return isSHL16(Op.getOperand(0));
1525 return DAG.ComputeNumSignBits(Op) == 17;
1526}
1527
1528/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1529static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1530 switch (CC) {
1531 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1531)
;
1532 case ISD::SETNE: return ARMCC::NE;
1533 case ISD::SETEQ: return ARMCC::EQ;
1534 case ISD::SETGT: return ARMCC::GT;
1535 case ISD::SETGE: return ARMCC::GE;
1536 case ISD::SETLT: return ARMCC::LT;
1537 case ISD::SETLE: return ARMCC::LE;
1538 case ISD::SETUGT: return ARMCC::HI;
1539 case ISD::SETUGE: return ARMCC::HS;
1540 case ISD::SETULT: return ARMCC::LO;
1541 case ISD::SETULE: return ARMCC::LS;
1542 }
1543}
1544
1545/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1546static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1547 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1548 CondCode2 = ARMCC::AL;
1549 InvalidOnQNaN = true;
1550 switch (CC) {
1551 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1551)
;
1552 case ISD::SETEQ:
1553 case ISD::SETOEQ:
1554 CondCode = ARMCC::EQ;
1555 InvalidOnQNaN = false;
1556 break;
1557 case ISD::SETGT:
1558 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1559 case ISD::SETGE:
1560 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1561 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1562 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1563 case ISD::SETONE:
1564 CondCode = ARMCC::MI;
1565 CondCode2 = ARMCC::GT;
1566 InvalidOnQNaN = false;
1567 break;
1568 case ISD::SETO: CondCode = ARMCC::VC; break;
1569 case ISD::SETUO: CondCode = ARMCC::VS; break;
1570 case ISD::SETUEQ:
1571 CondCode = ARMCC::EQ;
1572 CondCode2 = ARMCC::VS;
1573 InvalidOnQNaN = false;
1574 break;
1575 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1576 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1577 case ISD::SETLT:
1578 case ISD::SETULT: CondCode = ARMCC::LT; break;
1579 case ISD::SETLE:
1580 case ISD::SETULE: CondCode = ARMCC::LE; break;
1581 case ISD::SETNE:
1582 case ISD::SETUNE:
1583 CondCode = ARMCC::NE;
1584 InvalidOnQNaN = false;
1585 break;
1586 }
1587}
1588
1589//===----------------------------------------------------------------------===//
1590// Calling Convention Implementation
1591//===----------------------------------------------------------------------===//
1592
1593#include "ARMGenCallingConv.inc"
1594
1595/// getEffectiveCallingConv - Get the effective calling convention, taking into
1596/// account presence of floating point hardware and calling convention
1597/// limitations, such as support for variadic functions.
1598CallingConv::ID
1599ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1600 bool isVarArg) const {
1601 switch (CC) {
1602 default:
1603 report_fatal_error("Unsupported calling convention");
1604 case CallingConv::ARM_AAPCS:
1605 case CallingConv::ARM_APCS:
1606 case CallingConv::GHC:
1607 return CC;
1608 case CallingConv::PreserveMost:
1609 return CallingConv::PreserveMost;
1610 case CallingConv::ARM_AAPCS_VFP:
1611 case CallingConv::Swift:
1612 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1613 case CallingConv::C:
1614 if (!Subtarget->isAAPCS_ABI())
1615 return CallingConv::ARM_APCS;
1616 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1617 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1618 !isVarArg)
1619 return CallingConv::ARM_AAPCS_VFP;
1620 else
1621 return CallingConv::ARM_AAPCS;
1622 case CallingConv::Fast:
1623 case CallingConv::CXX_FAST_TLS:
1624 if (!Subtarget->isAAPCS_ABI()) {
1625 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1626 return CallingConv::Fast;
1627 return CallingConv::ARM_APCS;
1628 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1629 return CallingConv::ARM_AAPCS_VFP;
1630 else
1631 return CallingConv::ARM_AAPCS;
1632 }
1633}
1634
1635CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1636 bool isVarArg) const {
1637 return CCAssignFnForNode(CC, false, isVarArg);
1638}
1639
1640CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1641 bool isVarArg) const {
1642 return CCAssignFnForNode(CC, true, isVarArg);
1643}
1644
1645/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1646/// CallingConvention.
1647CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1648 bool Return,
1649 bool isVarArg) const {
1650 switch (getEffectiveCallingConv(CC, isVarArg)) {
1651 default:
1652 report_fatal_error("Unsupported calling convention");
1653 case CallingConv::ARM_APCS:
1654 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1655 case CallingConv::ARM_AAPCS:
1656 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1657 case CallingConv::ARM_AAPCS_VFP:
1658 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1659 case CallingConv::Fast:
1660 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1661 case CallingConv::GHC:
1662 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1663 case CallingConv::PreserveMost:
1664 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1665 }
1666}
1667
1668/// LowerCallResult - Lower the result values of a call into the
1669/// appropriate copies out of appropriate physical registers.
1670SDValue ARMTargetLowering::LowerCallResult(
1671 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1672 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1673 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1674 SDValue ThisVal) const {
1675 // Assign locations to each value returned by this call.
1676 SmallVector<CCValAssign, 16> RVLocs;
1677 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1678 *DAG.getContext());
1679 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1680
1681 // Copy all of the result registers out of their specified physreg.
1682 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1683 CCValAssign VA = RVLocs[i];
1684
1685 // Pass 'this' value directly from the argument to return value, to avoid
1686 // reg unit interference
1687 if (i == 0 && isThisReturn) {
1688 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1689, __PRETTY_FUNCTION__))
1689 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1689, __PRETTY_FUNCTION__))
;
1690 InVals.push_back(ThisVal);
1691 continue;
1692 }
1693
1694 SDValue Val;
1695 if (VA.needsCustom()) {
1696 // Handle f64 or half of a v2f64.
1697 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1698 InFlag);
1699 Chain = Lo.getValue(1);
1700 InFlag = Lo.getValue(2);
1701 VA = RVLocs[++i]; // skip ahead to next loc
1702 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1703 InFlag);
1704 Chain = Hi.getValue(1);
1705 InFlag = Hi.getValue(2);
1706 if (!Subtarget->isLittle())
1707 std::swap (Lo, Hi);
1708 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1709
1710 if (VA.getLocVT() == MVT::v2f64) {
1711 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1712 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1713 DAG.getConstant(0, dl, MVT::i32));
1714
1715 VA = RVLocs[++i]; // skip ahead to next loc
1716 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1717 Chain = Lo.getValue(1);
1718 InFlag = Lo.getValue(2);
1719 VA = RVLocs[++i]; // skip ahead to next loc
1720 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1721 Chain = Hi.getValue(1);
1722 InFlag = Hi.getValue(2);
1723 if (!Subtarget->isLittle())
1724 std::swap (Lo, Hi);
1725 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1726 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1727 DAG.getConstant(1, dl, MVT::i32));
1728 }
1729 } else {
1730 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1731 InFlag);
1732 Chain = Val.getValue(1);
1733 InFlag = Val.getValue(2);
1734 }
1735
1736 switch (VA.getLocInfo()) {
1737 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1737)
;
1738 case CCValAssign::Full: break;
1739 case CCValAssign::BCvt:
1740 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1741 break;
1742 }
1743
1744 InVals.push_back(Val);
1745 }
1746
1747 return Chain;
1748}
1749
1750/// LowerMemOpCallTo - Store the argument to the stack.
1751SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1752 SDValue Arg, const SDLoc &dl,
1753 SelectionDAG &DAG,
1754 const CCValAssign &VA,
1755 ISD::ArgFlagsTy Flags) const {
1756 unsigned LocMemOffset = VA.getLocMemOffset();
1757 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1758 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1759 StackPtr, PtrOff);
1760 return DAG.getStore(
1761 Chain, dl, Arg, PtrOff,
1762 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1763}
1764
1765void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1766 SDValue Chain, SDValue &Arg,
1767 RegsToPassVector &RegsToPass,
1768 CCValAssign &VA, CCValAssign &NextVA,
1769 SDValue &StackPtr,
1770 SmallVectorImpl<SDValue> &MemOpChains,
1771 ISD::ArgFlagsTy Flags) const {
1772 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1773 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1774 unsigned id = Subtarget->isLittle() ? 0 : 1;
1775 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1776
1777 if (NextVA.isRegLoc())
1778 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1779 else {
1780 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1780, __PRETTY_FUNCTION__))
;
1781 if (!StackPtr.getNode())
1782 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1783 getPointerTy(DAG.getDataLayout()));
1784
1785 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1786 dl, DAG, NextVA,
1787 Flags));
1788 }
1789}
1790
1791/// LowerCall - Lowering a call into a callseq_start <-
1792/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1793/// nodes.
1794SDValue
1795ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1796 SmallVectorImpl<SDValue> &InVals) const {
1797 SelectionDAG &DAG = CLI.DAG;
1798 SDLoc &dl = CLI.DL;
1799 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1800 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1801 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1802 SDValue Chain = CLI.Chain;
1803 SDValue Callee = CLI.Callee;
1804 bool &isTailCall = CLI.IsTailCall;
1805 CallingConv::ID CallConv = CLI.CallConv;
1806 bool doesNotRet = CLI.DoesNotReturn;
1807 bool isVarArg = CLI.IsVarArg;
1808
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1811 bool isThisReturn = false;
1812 bool isSibCall = false;
1813 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1814
1815 // Disable tail calls if they're not supported.
1816 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1817 isTailCall = false;
1818
1819 if (isTailCall) {
1820 // Check if it's really possible to do a tail call.
1821 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1822 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1823 Outs, OutVals, Ins, DAG);
1824 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1825 report_fatal_error("failed to perform tail call elimination on a call "
1826 "site marked musttail");
1827 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1828 // detected sibcalls.
1829 if (isTailCall) {
1830 ++NumTailCalls;
1831 isSibCall = true;
1832 }
1833 }
1834
1835 // Analyze operands of the call, assigning locations to each operand.
1836 SmallVector<CCValAssign, 16> ArgLocs;
1837 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1838 *DAG.getContext());
1839 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1840
1841 // Get a count of how many bytes are to be pushed on the stack.
1842 unsigned NumBytes = CCInfo.getNextStackOffset();
1843
1844 // For tail calls, memory operands are available in our caller's stack.
1845 if (isSibCall)
1846 NumBytes = 0;
1847
1848 // Adjust the stack pointer for the new arguments...
1849 // These operations are automatically eliminated by the prolog/epilog pass
1850 if (!isSibCall)
1851 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1852
1853 SDValue StackPtr =
1854 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1855
1856 RegsToPassVector RegsToPass;
1857 SmallVector<SDValue, 8> MemOpChains;
1858
1859 // Walk the register/memloc assignments, inserting copies/loads. In the case
1860 // of tail call optimization, arguments are handled later.
1861 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1862 i != e;
1863 ++i, ++realArgIdx) {
1864 CCValAssign &VA = ArgLocs[i];
1865 SDValue Arg = OutVals[realArgIdx];
1866 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1867 bool isByVal = Flags.isByVal();
1868
1869 // Promote the value if needed.
1870 switch (VA.getLocInfo()) {
1871 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1871)
;
1872 case CCValAssign::Full: break;
1873 case CCValAssign::SExt:
1874 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1875 break;
1876 case CCValAssign::ZExt:
1877 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1878 break;
1879 case CCValAssign::AExt:
1880 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1881 break;
1882 case CCValAssign::BCvt:
1883 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1884 break;
1885 }
1886
1887 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1888 if (VA.needsCustom()) {
1889 if (VA.getLocVT() == MVT::v2f64) {
1890 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1891 DAG.getConstant(0, dl, MVT::i32));
1892 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1893 DAG.getConstant(1, dl, MVT::i32));
1894
1895 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1896 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1897
1898 VA = ArgLocs[++i]; // skip ahead to next loc
1899 if (VA.isRegLoc()) {
1900 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1901 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1902 } else {
1903 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1903, __PRETTY_FUNCTION__))
;
1904
1905 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1906 dl, DAG, VA, Flags));
1907 }
1908 } else {
1909 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1910 StackPtr, MemOpChains, Flags);
1911 }
1912 } else if (VA.isRegLoc()) {
1913 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1914 Outs[0].VT == MVT::i32) {
1915 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1916, __PRETTY_FUNCTION__))
1916 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1916, __PRETTY_FUNCTION__))
;
1917 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1918, __PRETTY_FUNCTION__))
1918 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1918, __PRETTY_FUNCTION__))
;
1919 isThisReturn = true;
1920 }
1921 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1922 } else if (isByVal) {
1923 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1923, __PRETTY_FUNCTION__))
;
1924 unsigned offset = 0;
1925
1926 // True if this byval aggregate will be split between registers
1927 // and memory.
1928 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1929 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1930
1931 if (CurByValIdx < ByValArgsCount) {
1932
1933 unsigned RegBegin, RegEnd;
1934 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1935
1936 EVT PtrVT =
1937 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1938 unsigned int i, j;
1939 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1940 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1941 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1942 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1943 MachinePointerInfo(),
1944 DAG.InferPtrAlignment(AddArg));
1945 MemOpChains.push_back(Load.getValue(1));
1946 RegsToPass.push_back(std::make_pair(j, Load));
1947 }
1948
1949 // If parameter size outsides register area, "offset" value
1950 // helps us to calculate stack slot for remained part properly.
1951 offset = RegEnd - RegBegin;
1952
1953 CCInfo.nextInRegsParam();
1954 }
1955
1956 if (Flags.getByValSize() > 4*offset) {
1957 auto PtrVT = getPointerTy(DAG.getDataLayout());
1958 unsigned LocMemOffset = VA.getLocMemOffset();
1959 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1960 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1961 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1962 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1963 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1964 MVT::i32);
1965 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1966 MVT::i32);
1967
1968 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1969 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1970 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1971 Ops));
1972 }
1973 } else if (!isSibCall) {
1974 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 1974, __PRETTY_FUNCTION__))
;
1975
1976 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1977 dl, DAG, VA, Flags));
1978 }
1979 }
1980
1981 if (!MemOpChains.empty())
1982 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1983
1984 // Build a sequence of copy-to-reg nodes chained together with token chain
1985 // and flag operands which copy the outgoing args into the appropriate regs.
1986 SDValue InFlag;
1987 // Tail call byval lowering might overwrite argument registers so in case of
1988 // tail call optimization the copies to registers are lowered later.
1989 if (!isTailCall)
1990 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1991 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1992 RegsToPass[i].second, InFlag);
1993 InFlag = Chain.getValue(1);
1994 }
1995
1996 // For tail calls lower the arguments to the 'real' stack slot.
1997 if (isTailCall) {
1998 // Force all the incoming stack arguments to be loaded from the stack
1999 // before any new outgoing arguments are stored to the stack, because the
2000 // outgoing stack slots may alias the incoming argument stack slots, and
2001 // the alias isn't otherwise explicit. This is slightly more conservative
2002 // than necessary, because it means that each store effectively depends
2003 // on every argument instead of just those arguments it would clobber.
2004
2005 // Do not flag preceding copytoreg stuff together with the following stuff.
2006 InFlag = SDValue();
2007 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2008 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2009 RegsToPass[i].second, InFlag);
2010 InFlag = Chain.getValue(1);
2011 }
2012 InFlag = SDValue();
2013 }
2014
2015 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2016 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2017 // node so that legalize doesn't hack it.
2018 bool isDirect = false;
2019
2020 const TargetMachine &TM = getTargetMachine();
2021 const Module *Mod = MF.getFunction().getParent();
2022 const GlobalValue *GV = nullptr;
2023 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2024 GV = G->getGlobal();
2025 bool isStub =
2026 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2027
2028 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2029 bool isLocalARMFunc = false;
2030 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2031 auto PtrVt = getPointerTy(DAG.getDataLayout());
2032
2033 if (Subtarget->genLongCalls()) {
2034 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2035, __PRETTY_FUNCTION__))
2035 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2035, __PRETTY_FUNCTION__))
;
2036 // Handle a global address or an external symbol. If it's not one of
2037 // those, the target's already in a register, so we don't need to do
2038 // anything extra.
2039 if (isa<GlobalAddressSDNode>(Callee)) {
2040 // Create a constant pool entry for the callee address
2041 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2042 ARMConstantPoolValue *CPV =
2043 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2044
2045 // Get the address of the callee into a register
2046 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2047 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2048 Callee = DAG.getLoad(
2049 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2050 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2051 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2052 const char *Sym = S->getSymbol();
2053
2054 // Create a constant pool entry for the callee address
2055 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2056 ARMConstantPoolValue *CPV =
2057 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2058 ARMPCLabelIndex, 0);
2059 // Get the address of the callee into a register
2060 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2061 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2062 Callee = DAG.getLoad(
2063 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2064 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2065 }
2066 } else if (isa<GlobalAddressSDNode>(Callee)) {
2067 // If we're optimizing for minimum size and the function is called three or
2068 // more times in this block, we can improve codesize by calling indirectly
2069 // as BLXr has a 16-bit encoding.
2070 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2071 auto *BB = CLI.CS.getParent();
2072 bool PreferIndirect =
2073 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2074 count_if(GV->users(), [&BB](const User *U) {
2075 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2076 }) > 2;
2077
2078 if (!PreferIndirect) {
2079 isDirect = true;
2080 bool isDef = GV->isStrongDefinitionForLinker();
2081
2082 // ARM call to a local ARM function is predicable.
2083 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2084 // tBX takes a register source operand.
2085 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2086 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2086, __PRETTY_FUNCTION__))
;
2087 Callee = DAG.getNode(
2088 ARMISD::WrapperPIC, dl, PtrVt,
2089 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2090 Callee = DAG.getLoad(
2091 PtrVt, dl, DAG.getEntryNode(), Callee,
2092 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2093 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2094 MachineMemOperand::MOInvariant);
2095 } else if (Subtarget->isTargetCOFF()) {
2096 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2097, __PRETTY_FUNCTION__))
2097 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2097, __PRETTY_FUNCTION__))
;
2098 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2099 ? ARMII::MO_DLLIMPORT
2100 : ARMII::MO_NO_FLAG;
2101 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2102 TargetFlags);
2103 if (GV->hasDLLImportStorageClass())
2104 Callee =
2105 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2106 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2107 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2108 } else {
2109 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2110 }
2111 }
2112 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2113 isDirect = true;
2114 // tBX takes a register source operand.
2115 const char *Sym = S->getSymbol();
2116 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2117 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2118 ARMConstantPoolValue *CPV =
2119 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2120 ARMPCLabelIndex, 4);
2121 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2122 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2123 Callee = DAG.getLoad(
2124 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2125 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2126 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2127 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2128 } else {
2129 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2130 }
2131 }
2132
2133 // FIXME: handle tail calls differently.
2134 unsigned CallOpc;
2135 if (Subtarget->isThumb()) {
2136 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2137 CallOpc = ARMISD::CALL_NOLINK;
2138 else
2139 CallOpc = ARMISD::CALL;
2140 } else {
2141 if (!isDirect && !Subtarget->hasV5TOps())
2142 CallOpc = ARMISD::CALL_NOLINK;
2143 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2144 // Emit regular call when code size is the priority
2145 !MF.getFunction().optForMinSize())
2146 // "mov lr, pc; b _foo" to avoid confusing the RSP
2147 CallOpc = ARMISD::CALL_NOLINK;
2148 else
2149 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2150 }
2151
2152 std::vector<SDValue> Ops;
2153 Ops.push_back(Chain);
2154 Ops.push_back(Callee);
2155
2156 // Add argument registers to the end of the list so that they are known live
2157 // into the call.
2158 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2159 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2160 RegsToPass[i].second.getValueType()));
2161
2162 // Add a register mask operand representing the call-preserved registers.
2163 if (!isTailCall) {
2164 const uint32_t *Mask;
2165 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2166 if (isThisReturn) {
2167 // For 'this' returns, use the R0-preserving mask if applicable
2168 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2169 if (!Mask) {
2170 // Set isThisReturn to false if the calling convention is not one that
2171 // allows 'returned' to be modeled in this way, so LowerCallResult does
2172 // not try to pass 'this' straight through
2173 isThisReturn = false;
2174 Mask = ARI->getCallPreservedMask(MF, CallConv);
2175 }
2176 } else
2177 Mask = ARI->getCallPreservedMask(MF, CallConv);
2178
2179 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2179, __PRETTY_FUNCTION__))
;
2180 Ops.push_back(DAG.getRegisterMask(Mask));
2181 }
2182
2183 if (InFlag.getNode())
2184 Ops.push_back(InFlag);
2185
2186 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2187 if (isTailCall) {
2188 MF.getFrameInfo().setHasTailCall();
2189 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2190 }
2191
2192 // Returns a chain and a flag for retval copy to use.
2193 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2194 InFlag = Chain.getValue(1);
2195
2196 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2197 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2198 if (!Ins.empty())
2199 InFlag = Chain.getValue(1);
2200
2201 // Handle result values, copying them out of physregs into vregs that we
2202 // return.
2203 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2204 InVals, isThisReturn,
2205 isThisReturn ? OutVals[0] : SDValue());
2206}
2207
2208/// HandleByVal - Every parameter *after* a byval parameter is passed
2209/// on the stack. Remember the next parameter register to allocate,
2210/// and then confiscate the rest of the parameter registers to insure
2211/// this.
2212void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2213 unsigned Align) const {
2214 // Byval (as with any stack) slots are always at least 4 byte aligned.
2215 Align = std::max(Align, 4U);
2216
2217 unsigned Reg = State->AllocateReg(GPRArgRegs);
2218 if (!Reg)
2219 return;
2220
2221 unsigned AlignInRegs = Align / 4;
2222 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2223 for (unsigned i = 0; i < Waste; ++i)
2224 Reg = State->AllocateReg(GPRArgRegs);
2225
2226 if (!Reg)
2227 return;
2228
2229 unsigned Excess = 4 * (ARM::R4 - Reg);
2230
2231 // Special case when NSAA != SP and parameter size greater than size of
2232 // all remained GPR regs. In that case we can't split parameter, we must
2233 // send it to stack. We also must set NCRN to R4, so waste all
2234 // remained registers.
2235 const unsigned NSAAOffset = State->getNextStackOffset();
2236 if (NSAAOffset != 0 && Size > Excess) {
2237 while (State->AllocateReg(GPRArgRegs))
2238 ;
2239 return;
2240 }
2241
2242 // First register for byval parameter is the first register that wasn't
2243 // allocated before this method call, so it would be "reg".
2244 // If parameter is small enough to be saved in range [reg, r4), then
2245 // the end (first after last) register would be reg + param-size-in-regs,
2246 // else parameter would be splitted between registers and stack,
2247 // end register would be r4 in this case.
2248 unsigned ByValRegBegin = Reg;
2249 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2250 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2251 // Note, first register is allocated in the beginning of function already,
2252 // allocate remained amount of registers we need.
2253 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2254 State->AllocateReg(GPRArgRegs);
2255 // A byval parameter that is split between registers and memory needs its
2256 // size truncated here.
2257 // In the case where the entire structure fits in registers, we set the
2258 // size in memory to zero.
2259 Size = std::max<int>(Size - Excess, 0);
2260}
2261
2262/// MatchingStackOffset - Return true if the given stack call argument is
2263/// already available in the same position (relatively) of the caller's
2264/// incoming argument stack.
2265static
2266bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2267 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2268 const TargetInstrInfo *TII) {
2269 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2270 int FI = std::numeric_limits<int>::max();
2271 if (Arg.getOpcode() == ISD::CopyFromReg) {
2272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2273 if (!TargetRegisterInfo::isVirtualRegister(VR))
2274 return false;
2275 MachineInstr *Def = MRI->getVRegDef(VR);
2276 if (!Def)
2277 return false;
2278 if (!Flags.isByVal()) {
2279 if (!TII->isLoadFromStackSlot(*Def, FI))
2280 return false;
2281 } else {
2282 return false;
2283 }
2284 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2285 if (Flags.isByVal())
2286 // ByVal argument is passed in as a pointer but it's now being
2287 // dereferenced. e.g.
2288 // define @foo(%struct.X* %A) {
2289 // tail call @bar(%struct.X* byval %A)
2290 // }
2291 return false;
2292 SDValue Ptr = Ld->getBasePtr();
2293 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2294 if (!FINode)
2295 return false;
2296 FI = FINode->getIndex();
2297 } else
2298 return false;
2299
2300 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2300, __PRETTY_FUNCTION__))
;
2301 if (!MFI.isFixedObjectIndex(FI))
2302 return false;
2303 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2304}
2305
2306/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2307/// for tail call optimization. Targets which want to do tail call
2308/// optimization should implement this function.
2309bool
2310ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2311 CallingConv::ID CalleeCC,
2312 bool isVarArg,
2313 bool isCalleeStructRet,
2314 bool isCallerStructRet,
2315 const SmallVectorImpl<ISD::OutputArg> &Outs,
2316 const SmallVectorImpl<SDValue> &OutVals,
2317 const SmallVectorImpl<ISD::InputArg> &Ins,
2318 SelectionDAG& DAG) const {
2319 MachineFunction &MF = DAG.getMachineFunction();
2320 const Function &CallerF = MF.getFunction();
2321 CallingConv::ID CallerCC = CallerF.getCallingConv();
2322
2323 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2323, __PRETTY_FUNCTION__))
;
2324
2325 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2326 // to the call take up r0-r3. The reason is that there are no legal registers
2327 // left to hold the pointer to the function to be called.
2328 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2329 !isa<GlobalAddressSDNode>(Callee.getNode()))
2330 return false;
2331
2332 // Look for obvious safe cases to perform tail call optimization that do not
2333 // require ABI changes. This is what gcc calls sibcall.
2334
2335 // Exception-handling functions need a special set of instructions to indicate
2336 // a return to the hardware. Tail-calling another function would probably
2337 // break this.
2338 if (CallerF.hasFnAttribute("interrupt"))
2339 return false;
2340
2341 // Also avoid sibcall optimization if either caller or callee uses struct
2342 // return semantics.
2343 if (isCalleeStructRet || isCallerStructRet)
2344 return false;
2345
2346 // Externally-defined functions with weak linkage should not be
2347 // tail-called on ARM when the OS does not support dynamic
2348 // pre-emption of symbols, as the AAELF spec requires normal calls
2349 // to undefined weak functions to be replaced with a NOP or jump to the
2350 // next instruction. The behaviour of branch instructions in this
2351 // situation (as used for tail calls) is implementation-defined, so we
2352 // cannot rely on the linker replacing the tail call with a return.
2353 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2354 const GlobalValue *GV = G->getGlobal();
2355 const Triple &TT = getTargetMachine().getTargetTriple();
2356 if (GV->hasExternalWeakLinkage() &&
2357 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2358 return false;
2359 }
2360
2361 // Check that the call results are passed in the same way.
2362 LLVMContext &C = *DAG.getContext();
2363 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2364 CCAssignFnForReturn(CalleeCC, isVarArg),
2365 CCAssignFnForReturn(CallerCC, isVarArg)))
2366 return false;
2367 // The callee has to preserve all registers the caller needs to preserve.
2368 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2369 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2370 if (CalleeCC != CallerCC) {
2371 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2372 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2373 return false;
2374 }
2375
2376 // If Caller's vararg or byval argument has been split between registers and
2377 // stack, do not perform tail call, since part of the argument is in caller's
2378 // local frame.
2379 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2380 if (AFI_Caller->getArgRegsSaveSize())
2381 return false;
2382
2383 // If the callee takes no arguments then go on to check the results of the
2384 // call.
2385 if (!Outs.empty()) {
2386 // Check if stack adjustment is needed. For now, do not do this if any
2387 // argument is passed on the stack.
2388 SmallVector<CCValAssign, 16> ArgLocs;
2389 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2390 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2391 if (CCInfo.getNextStackOffset()) {
2392 // Check if the arguments are already laid out in the right way as
2393 // the caller's fixed stack objects.
2394 MachineFrameInfo &MFI = MF.getFrameInfo();
2395 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2396 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2397 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2398 i != e;
2399 ++i, ++realArgIdx) {
2400 CCValAssign &VA = ArgLocs[i];
2401 EVT RegVT = VA.getLocVT();
2402 SDValue Arg = OutVals[realArgIdx];
2403 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2404 if (VA.getLocInfo() == CCValAssign::Indirect)
2405 return false;
2406 if (VA.needsCustom()) {
2407 // f64 and vector types are split into multiple registers or
2408 // register/stack-slot combinations. The types will not match
2409 // the registers; give up on memory f64 refs until we figure
2410 // out what to do about this.
2411 if (!VA.isRegLoc())
2412 return false;
2413 if (!ArgLocs[++i].isRegLoc())
2414 return false;
2415 if (RegVT == MVT::v2f64) {
2416 if (!ArgLocs[++i].isRegLoc())
2417 return false;
2418 if (!ArgLocs[++i].isRegLoc())
2419 return false;
2420 }
2421 } else if (!VA.isRegLoc()) {
2422 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2423 MFI, MRI, TII))
2424 return false;
2425 }
2426 }
2427 }
2428
2429 const MachineRegisterInfo &MRI = MF.getRegInfo();
2430 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2431 return false;
2432 }
2433
2434 return true;
2435}
2436
2437bool
2438ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2439 MachineFunction &MF, bool isVarArg,
2440 const SmallVectorImpl<ISD::OutputArg> &Outs,
2441 LLVMContext &Context) const {
2442 SmallVector<CCValAssign, 16> RVLocs;
2443 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2444 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2445}
2446
2447static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2448 const SDLoc &DL, SelectionDAG &DAG) {
2449 const MachineFunction &MF = DAG.getMachineFunction();
2450 const Function &F = MF.getFunction();
2451
2452 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2453
2454 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2455 // version of the "preferred return address". These offsets affect the return
2456 // instruction if this is a return from PL1 without hypervisor extensions.
2457 // IRQ/FIQ: +4 "subs pc, lr, #4"
2458 // SWI: 0 "subs pc, lr, #0"
2459 // ABORT: +4 "subs pc, lr, #4"
2460 // UNDEF: +4/+2 "subs pc, lr, #0"
2461 // UNDEF varies depending on where the exception came from ARM or Thumb
2462 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2463
2464 int64_t LROffset;
2465 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2466 IntKind == "ABORT")
2467 LROffset = 4;
2468 else if (IntKind == "SWI" || IntKind == "UNDEF")
2469 LROffset = 0;
2470 else
2471 report_fatal_error("Unsupported interrupt attribute. If present, value "
2472 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2473
2474 RetOps.insert(RetOps.begin() + 1,
2475 DAG.getConstant(LROffset, DL, MVT::i32, false));
2476
2477 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2478}
2479
2480SDValue
2481ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2482 bool isVarArg,
2483 const SmallVectorImpl<ISD::OutputArg> &Outs,
2484 const SmallVectorImpl<SDValue> &OutVals,
2485 const SDLoc &dl, SelectionDAG &DAG) const {
2486 // CCValAssign - represent the assignment of the return value to a location.
2487 SmallVector<CCValAssign, 16> RVLocs;
2488
2489 // CCState - Info about the registers and stack slots.
2490 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2491 *DAG.getContext());
2492
2493 // Analyze outgoing return values.
2494 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2495
2496 SDValue Flag;
2497 SmallVector<SDValue, 4> RetOps;
2498 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2499 bool isLittleEndian = Subtarget->isLittle();
2500
2501 MachineFunction &MF = DAG.getMachineFunction();
2502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2503 AFI->setReturnRegsCount(RVLocs.size());
2504
2505 // Copy the result values into the output registers.
2506 for (unsigned i = 0, realRVLocIdx = 0;
2507 i != RVLocs.size();
2508 ++i, ++realRVLocIdx) {
2509 CCValAssign &VA = RVLocs[i];
2510 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2510, __PRETTY_FUNCTION__))
;
2511
2512 SDValue Arg = OutVals[realRVLocIdx];
2513 bool ReturnF16 = false;
2514
2515 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2516 // Half-precision return values can be returned like this:
2517 //
2518 // t11 f16 = fadd ...
2519 // t12: i16 = bitcast t11
2520 // t13: i32 = zero_extend t12
2521 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2522 //
2523 // to avoid code generation for bitcasts, we simply set Arg to the node
2524 // that produces the f16 value, t11 in this case.
2525 //
2526 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2527 SDValue ZE = Arg.getOperand(0);
2528 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2529 SDValue BC = ZE.getOperand(0);
2530 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2531 Arg = BC.getOperand(0);
2532 ReturnF16 = true;
2533 }
2534 }
2535 }
2536 }
2537
2538 switch (VA.getLocInfo()) {
2539 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2539)
;
2540 case CCValAssign::Full: break;
2541 case CCValAssign::BCvt:
2542 if (!ReturnF16)
2543 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2544 break;
2545 }
2546
2547 if (VA.needsCustom()) {
2548 if (VA.getLocVT() == MVT::v2f64) {
2549 // Extract the first half and return it in two registers.
2550 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2551 DAG.getConstant(0, dl, MVT::i32));
2552 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2553 DAG.getVTList(MVT::i32, MVT::i32), Half);
2554
2555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2556 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2557 Flag);
2558 Flag = Chain.getValue(1);
2559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2560 VA = RVLocs[++i]; // skip ahead to next loc
2561 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2562 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2563 Flag);
2564 Flag = Chain.getValue(1);
2565 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2566 VA = RVLocs[++i]; // skip ahead to next loc
2567
2568 // Extract the 2nd half and fall through to handle it as an f64 value.
2569 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2570 DAG.getConstant(1, dl, MVT::i32));
2571 }
2572 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2573 // available.
2574 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2575 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2576 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2577 fmrrd.getValue(isLittleEndian ? 0 : 1),
2578 Flag);
2579 Flag = Chain.getValue(1);
2580 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2581 VA = RVLocs[++i]; // skip ahead to next loc
2582 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2583 fmrrd.getValue(isLittleEndian ? 1 : 0),
2584 Flag);
2585 } else
2586 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2587
2588 // Guarantee that all emitted copies are
2589 // stuck together, avoiding something bad.
2590 Flag = Chain.getValue(1);
2591 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2592 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2593 }
2594 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2595 const MCPhysReg *I =
2596 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2597 if (I) {
2598 for (; *I; ++I) {
2599 if (ARM::GPRRegClass.contains(*I))
2600 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2601 else if (ARM::DPRRegClass.contains(*I))
2602 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2603 else
2604 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2604)
;
2605 }
2606 }
2607
2608 // Update chain and glue.
2609 RetOps[0] = Chain;
2610 if (Flag.getNode())
2611 RetOps.push_back(Flag);
2612
2613 // CPUs which aren't M-class use a special sequence to return from
2614 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2615 // though we use "subs pc, lr, #N").
2616 //
2617 // M-class CPUs actually use a normal return sequence with a special
2618 // (hardware-provided) value in LR, so the normal code path works.
2619 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2620 !Subtarget->isMClass()) {
2621 if (Subtarget->isThumb1Only())
2622 report_fatal_error("interrupt attribute is not supported in Thumb1");
2623 return LowerInterruptReturn(RetOps, dl, DAG);
2624 }
2625
2626 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2627}
2628
2629bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2630 if (N->getNumValues() != 1)
2631 return false;
2632 if (!N->hasNUsesOfValue(1, 0))
2633 return false;
2634
2635 SDValue TCChain = Chain;
2636 SDNode *Copy = *N->use_begin();
2637 if (Copy->getOpcode() == ISD::CopyToReg) {
2638 // If the copy has a glue operand, we conservatively assume it isn't safe to
2639 // perform a tail call.
2640 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2641 return false;
2642 TCChain = Copy->getOperand(0);
2643 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2644 SDNode *VMov = Copy;
2645 // f64 returned in a pair of GPRs.
2646 SmallPtrSet<SDNode*, 2> Copies;
2647 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2648 UI != UE; ++UI) {
2649 if (UI->getOpcode() != ISD::CopyToReg)
2650 return false;
2651 Copies.insert(*UI);
2652 }
2653 if (Copies.size() > 2)
2654 return false;
2655
2656 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2657 UI != UE; ++UI) {
2658 SDValue UseChain = UI->getOperand(0);
2659 if (Copies.count(UseChain.getNode()))
2660 // Second CopyToReg
2661 Copy = *UI;
2662 else {
2663 // We are at the top of this chain.
2664 // If the copy has a glue operand, we conservatively assume it
2665 // isn't safe to perform a tail call.
2666 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2667 return false;
2668 // First CopyToReg
2669 TCChain = UseChain;
2670 }
2671 }
2672 } else if (Copy->getOpcode() == ISD::BITCAST) {
2673 // f32 returned in a single GPR.
2674 if (!Copy->hasOneUse())
2675 return false;
2676 Copy = *Copy->use_begin();
2677 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2678 return false;
2679 // If the copy has a glue operand, we conservatively assume it isn't safe to
2680 // perform a tail call.
2681 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2682 return false;
2683 TCChain = Copy->getOperand(0);
2684 } else {
2685 return false;
2686 }
2687
2688 bool HasRet = false;
2689 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2690 UI != UE; ++UI) {
2691 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2692 UI->getOpcode() != ARMISD::INTRET_FLAG)
2693 return false;
2694 HasRet = true;
2695 }
2696
2697 if (!HasRet)
2698 return false;
2699
2700 Chain = TCChain;
2701 return true;
2702}
2703
2704bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2705 if (!Subtarget->supportsTailCall())
2706 return false;
2707
2708 auto Attr =
2709 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2710 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2711 return false;
2712
2713 return true;
2714}
2715
2716// Trying to write a 64 bit value so need to split into two 32 bit values first,
2717// and pass the lower and high parts through.
2718static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2719 SDLoc DL(Op);
2720 SDValue WriteValue = Op->getOperand(2);
2721
2722 // This function is only supposed to be called for i64 type argument.
2723 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2724, __PRETTY_FUNCTION__))
2724 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2724, __PRETTY_FUNCTION__))
;
2725
2726 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2727 DAG.getConstant(0, DL, MVT::i32));
2728 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2729 DAG.getConstant(1, DL, MVT::i32));
2730 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2731 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2732}
2733
2734// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2735// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2736// one of the above mentioned nodes. It has to be wrapped because otherwise
2737// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2738// be used to form addressing mode. These wrapped nodes will be selected
2739// into MOVi.
2740SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2741 SelectionDAG &DAG) const {
2742 EVT PtrVT = Op.getValueType();
2743 // FIXME there is no actual debug info here
2744 SDLoc dl(Op);
2745 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2746 SDValue Res;
2747
2748 // When generating execute-only code Constant Pools must be promoted to the
2749 // global data section. It's a bit ugly that we can't share them across basic
2750 // blocks, but this way we guarantee that execute-only behaves correct with
2751 // position-independent addressing modes.
2752 if (Subtarget->genExecuteOnly()) {
2753 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2754 auto T = const_cast<Type*>(CP->getType());
2755 auto C = const_cast<Constant*>(CP->getConstVal());
2756 auto M = const_cast<Module*>(DAG.getMachineFunction().
2757 getFunction().getParent());
2758 auto GV = new GlobalVariable(
2759 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2760 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2761 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2762 Twine(AFI->createPICLabelUId())
2763 );
2764 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2765 dl, PtrVT);
2766 return LowerGlobalAddress(GA, DAG);
2767 }
2768
2769 if (CP->isMachineConstantPoolEntry())
2770 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2771 CP->getAlignment());
2772 else
2773 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2774 CP->getAlignment());
2775 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2776}
2777
2778unsigned ARMTargetLowering::getJumpTableEncoding() const {
2779 return MachineJumpTableInfo::EK_Inline;
2780}
2781
2782SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2783 SelectionDAG &DAG) const {
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2786 unsigned ARMPCLabelIndex = 0;
2787 SDLoc DL(Op);
2788 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2789 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2790 SDValue CPAddr;
2791 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2792 if (!IsPositionIndependent) {
2793 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2794 } else {
2795 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2796 ARMPCLabelIndex = AFI->createPICLabelUId();
2797 ARMConstantPoolValue *CPV =
2798 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2799 ARMCP::CPBlockAddress, PCAdj);
2800 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2801 }
2802 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2803 SDValue Result = DAG.getLoad(
2804 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2805 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2806 if (!IsPositionIndependent)
2807 return Result;
2808 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2809 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2810}
2811
2812/// Convert a TLS address reference into the correct sequence of loads
2813/// and calls to compute the variable's address for Darwin, and return an
2814/// SDValue containing the final node.
2815
2816/// Darwin only has one TLS scheme which must be capable of dealing with the
2817/// fully general situation, in the worst case. This means:
2818/// + "extern __thread" declaration.
2819/// + Defined in a possibly unknown dynamic library.
2820///
2821/// The general system is that each __thread variable has a [3 x i32] descriptor
2822/// which contains information used by the runtime to calculate the address. The
2823/// only part of this the compiler needs to know about is the first word, which
2824/// contains a function pointer that must be called with the address of the
2825/// entire descriptor in "r0".
2826///
2827/// Since this descriptor may be in a different unit, in general access must
2828/// proceed along the usual ARM rules. A common sequence to produce is:
2829///
2830/// movw rT1, :lower16:_var$non_lazy_ptr
2831/// movt rT1, :upper16:_var$non_lazy_ptr
2832/// ldr r0, [rT1]
2833/// ldr rT2, [r0]
2834/// blx rT2
2835/// [...address now in r0...]
2836SDValue
2837ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2838 SelectionDAG &DAG) const {
2839 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2840, __PRETTY_FUNCTION__))
2840 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2840, __PRETTY_FUNCTION__))
;
2841 SDLoc DL(Op);
2842
2843 // First step is to get the address of the actua global symbol. This is where
2844 // the TLS descriptor lives.
2845 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2846
2847 // The first entry in the descriptor is a function pointer that we must call
2848 // to obtain the address of the variable.
2849 SDValue Chain = DAG.getEntryNode();
2850 SDValue FuncTLVGet = DAG.getLoad(
2851 MVT::i32, DL, Chain, DescAddr,
2852 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2853 /* Alignment = */ 4,
2854 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2855 MachineMemOperand::MOInvariant);
2856 Chain = FuncTLVGet.getValue(1);
2857
2858 MachineFunction &F = DAG.getMachineFunction();
2859 MachineFrameInfo &MFI = F.getFrameInfo();
2860 MFI.setAdjustsStack(true);
2861
2862 // TLS calls preserve all registers except those that absolutely must be
2863 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2864 // silly).
2865 auto TRI =
2866 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2867 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2868 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2869
2870 // Finally, we can make the call. This is just a degenerate version of a
2871 // normal AArch64 call node: r0 takes the address of the descriptor, and
2872 // returns the address of the variable in this thread.
2873 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2874 Chain =
2875 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2876 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2877 DAG.getRegisterMask(Mask), Chain.getValue(1));
2878 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2879}
2880
2881SDValue
2882ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2883 SelectionDAG &DAG) const {
2884 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 2884, __PRETTY_FUNCTION__))
;
2885
2886 SDValue Chain = DAG.getEntryNode();
2887 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2888 SDLoc DL(Op);
2889
2890 // Load the current TEB (thread environment block)
2891 SDValue Ops[] = {Chain,
2892 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2893 DAG.getConstant(15, DL, MVT::i32),
2894 DAG.getConstant(0, DL, MVT::i32),
2895 DAG.getConstant(13, DL, MVT::i32),
2896 DAG.getConstant(0, DL, MVT::i32),
2897 DAG.getConstant(2, DL, MVT::i32)};
2898 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2899 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2900
2901 SDValue TEB = CurrentTEB.getValue(0);
2902 Chain = CurrentTEB.getValue(1);
2903
2904 // Load the ThreadLocalStoragePointer from the TEB
2905 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2906 SDValue TLSArray =
2907 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2908 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2909
2910 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2911 // offset into the TLSArray.
2912
2913 // Load the TLS index from the C runtime
2914 SDValue TLSIndex =
2915 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2916 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2917 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2918
2919 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2920 DAG.getConstant(2, DL, MVT::i32));
2921 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2922 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2923 MachinePointerInfo());
2924
2925 // Get the offset of the start of the .tls section (section base)
2926 const auto *GA = cast<GlobalAddressSDNode>(Op);
2927 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2928 SDValue Offset = DAG.getLoad(
2929 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2930 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2931 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2932
2933 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2934}
2935
2936// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2937SDValue
2938ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2939 SelectionDAG &DAG) const {
2940 SDLoc dl(GA);
2941 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2942 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2943 MachineFunction &MF = DAG.getMachineFunction();
2944 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2945 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2946 ARMConstantPoolValue *CPV =
2947 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2948 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2949 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2950 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2951 Argument = DAG.getLoad(
2952 PtrVT, dl, DAG.getEntryNode(), Argument,
2953 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2954 SDValue Chain = Argument.getValue(1);
2955
2956 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2957 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2958
2959 // call __tls_get_addr.
2960 ArgListTy Args;
2961 ArgListEntry Entry;
2962 Entry.Node = Argument;
2963 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2964 Args.push_back(Entry);
2965
2966 // FIXME: is there useful debug info available here?
2967 TargetLowering::CallLoweringInfo CLI(DAG);
2968 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2969 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2970 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2971
2972 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2973 return CallResult.first;
2974}
2975
2976// Lower ISD::GlobalTLSAddress using the "initial exec" or
2977// "local exec" model.
2978SDValue
2979ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2980 SelectionDAG &DAG,
2981 TLSModel::Model model) const {
2982 const GlobalValue *GV = GA->getGlobal();
2983 SDLoc dl(GA);
2984 SDValue Offset;
2985 SDValue Chain = DAG.getEntryNode();
2986 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2987 // Get the Thread Pointer
2988 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2989
2990 if (model == TLSModel::InitialExec) {
2991 MachineFunction &MF = DAG.getMachineFunction();
2992 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2993 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2994 // Initial exec model.
2995 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2996 ARMConstantPoolValue *CPV =
2997 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2998 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2999 true);
3000 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3001 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3002 Offset = DAG.getLoad(
3003 PtrVT, dl, Chain, Offset,
3004 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3005 Chain = Offset.getValue(1);
3006
3007 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3008 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3009
3010 Offset = DAG.getLoad(
3011 PtrVT, dl, Chain, Offset,
3012 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3013 } else {
3014 // local exec model
3015 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3015, __PRETTY_FUNCTION__))
;
3016 ARMConstantPoolValue *CPV =
3017 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3018 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3019 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3020 Offset = DAG.getLoad(
3021 PtrVT, dl, Chain, Offset,
3022 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3023 }
3024
3025 // The address of the thread local variable is the add of the thread
3026 // pointer with the offset of the variable.
3027 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3028}
3029
3030SDValue
3031ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3032 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3033 if (DAG.getTarget().useEmulatedTLS())
3034 return LowerToTLSEmulatedModel(GA, DAG);
3035
3036 if (Subtarget->isTargetDarwin())
3037 return LowerGlobalTLSAddressDarwin(Op, DAG);
3038
3039 if (Subtarget->isTargetWindows())
3040 return LowerGlobalTLSAddressWindows(Op, DAG);
3041
3042 // TODO: implement the "local dynamic" model
3043 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3043, __PRETTY_FUNCTION__))
;
3044 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3045
3046 switch (model) {
3047 case TLSModel::GeneralDynamic:
3048 case TLSModel::LocalDynamic:
3049 return LowerToTLSGeneralDynamicModel(GA, DAG);
3050 case TLSModel::InitialExec:
3051 case TLSModel::LocalExec:
3052 return LowerToTLSExecModels(GA, DAG, model);
3053 }
3054 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3054)
;
3055}
3056
3057/// Return true if all users of V are within function F, looking through
3058/// ConstantExprs.
3059static bool allUsersAreInFunction(const Value *V, const Function *F) {
3060 SmallVector<const User*,4> Worklist;
3061 for (auto *U : V->users())
3062 Worklist.push_back(U);
3063 while (!Worklist.empty()) {
3064 auto *U = Worklist.pop_back_val();
3065 if (isa<ConstantExpr>(U)) {
3066 for (auto *UU : U->users())
3067 Worklist.push_back(UU);
3068 continue;
3069 }
3070
3071 auto *I = dyn_cast<Instruction>(U);
3072 if (!I || I->getParent()->getParent() != F)
3073 return false;
3074 }
3075 return true;
3076}
3077
3078static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3079 const GlobalValue *GV, SelectionDAG &DAG,
3080 EVT PtrVT, const SDLoc &dl) {
3081 // If we're creating a pool entry for a constant global with unnamed address,
3082 // and the global is small enough, we can emit it inline into the constant pool
3083 // to save ourselves an indirection.
3084 //
3085 // This is a win if the constant is only used in one function (so it doesn't
3086 // need to be duplicated) or duplicating the constant wouldn't increase code
3087 // size (implying the constant is no larger than 4 bytes).
3088 const Function &F = DAG.getMachineFunction().getFunction();
3089
3090 // We rely on this decision to inline being idemopotent and unrelated to the
3091 // use-site. We know that if we inline a variable at one use site, we'll
3092 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3093 // doesn't know about this optimization, so bail out if it's enabled else
3094 // we could decide to inline here (and thus never emit the GV) but require
3095 // the GV from fast-isel generated code.
3096 if (!EnableConstpoolPromotion ||
3097 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3098 return SDValue();
3099
3100 auto *GVar = dyn_cast<GlobalVariable>(GV);
3101 if (!GVar || !GVar->hasInitializer() ||
3102 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3103 !GVar->hasLocalLinkage())
3104 return SDValue();
3105
3106 // If we inline a value that contains relocations, we move the relocations
3107 // from .data to .text. This is not allowed in position-independent code.
3108 auto *Init = GVar->getInitializer();
3109 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3110 Init->needsRelocation())
3111 return SDValue();
3112
3113 // The constant islands pass can only really deal with alignment requests
3114 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3115 // any type wanting greater alignment requirements than 4 bytes. We also
3116 // can only promote constants that are multiples of 4 bytes in size or
3117 // are paddable to a multiple of 4. Currently we only try and pad constants
3118 // that are strings for simplicity.
3119 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3120 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3121 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3122 unsigned RequiredPadding = 4 - (Size % 4);
3123 bool PaddingPossible =
3124 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3125 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3126 Size == 0)
3127 return SDValue();
3128
3129 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3130 MachineFunction &MF = DAG.getMachineFunction();
3131 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3132
3133 // We can't bloat the constant pool too much, else the ConstantIslands pass
3134 // may fail to converge. If we haven't promoted this global yet (it may have
3135 // multiple uses), and promoting it would increase the constant pool size (Sz
3136 // > 4), ensure we have space to do so up to MaxTotal.
3137 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3138 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3139 ConstpoolPromotionMaxTotal)
3140 return SDValue();
3141
3142 // This is only valid if all users are in a single function; we can't clone
3143 // the constant in general. The LLVM IR unnamed_addr allows merging
3144 // constants, but not cloning them.
3145 //
3146 // We could potentially allow cloning if we could prove all uses of the
3147 // constant in the current function don't care about the address, like
3148 // printf format strings. But that isn't implemented for now.
3149 if (!allUsersAreInFunction(GVar, &F))
3150 return SDValue();
3151
3152 // We're going to inline this global. Pad it out if needed.
3153 if (RequiredPadding != 4) {
3154 StringRef S = CDAInit->getAsString();
3155
3156 SmallVector<uint8_t,16> V(S.size());
3157 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3158 while (RequiredPadding--)
3159 V.push_back(0);
3160 Init = ConstantDataArray::get(*DAG.getContext(), V);
3161 }
3162
3163 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3164 SDValue CPAddr =
3165 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3166 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3167 AFI->markGlobalAsPromotedToConstantPool(GVar);
3168 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3169 PaddedSize - 4);
3170 }
3171 ++NumConstpoolPromoted;
3172 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3173}
3174
3175bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3176 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3177 if (!(GV = GA->getBaseObject()))
3178 return false;
3179 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3180 return V->isConstant();
3181 return isa<Function>(GV);
3182}
3183
3184SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3185 SelectionDAG &DAG) const {
3186 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3187 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3187)
;
3188 case Triple::COFF:
3189 return LowerGlobalAddressWindows(Op, DAG);
3190 case Triple::ELF:
3191 return LowerGlobalAddressELF(Op, DAG);
3192 case Triple::MachO:
3193 return LowerGlobalAddressDarwin(Op, DAG);
3194 }
3195}
3196
3197SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3198 SelectionDAG &DAG) const {
3199 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3200 SDLoc dl(Op);
3201 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3202 const TargetMachine &TM = getTargetMachine();
3203 bool IsRO = isReadOnly(GV);
3204
3205 // promoteToConstantPool only if not generating XO text section
3206 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3207 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3208 return V;
3209
3210 if (isPositionIndependent()) {
3211 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3212 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3213 UseGOT_PREL ? ARMII::MO_GOT : 0);
3214 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3215 if (UseGOT_PREL)
3216 Result =
3217 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3218 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3219 return Result;
3220 } else if (Subtarget->isROPI() && IsRO) {
3221 // PC-relative.
3222 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3223 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3224 return Result;
3225 } else if (Subtarget->isRWPI() && !IsRO) {
3226 // SB-relative.
3227 SDValue RelAddr;
3228 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3229 ++NumMovwMovt;
3230 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3231 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3232 } else { // use literal pool for address constant
3233 ARMConstantPoolValue *CPV =
3234 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3235 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3236 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3237 RelAddr = DAG.getLoad(
3238 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3239 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3240 }
3241 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3242 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3243 return Result;
3244 }
3245
3246 // If we have T2 ops, we can materialize the address directly via movt/movw
3247 // pair. This is always cheaper.
3248 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3249 ++NumMovwMovt;
3250 // FIXME: Once remat is capable of dealing with instructions with register
3251 // operands, expand this into two nodes.
3252 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3253 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3254 } else {
3255 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3256 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3257 return DAG.getLoad(
3258 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3259 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3260 }
3261}
3262
3263SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3264 SelectionDAG &DAG) const {
3265 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3266, __PRETTY_FUNCTION__))
3266 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3266, __PRETTY_FUNCTION__))
;
3267 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3268 SDLoc dl(Op);
3269 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3270
3271 if (Subtarget->useMovt(DAG.getMachineFunction()))
3272 ++NumMovwMovt;
3273
3274 // FIXME: Once remat is capable of dealing with instructions with register
3275 // operands, expand this into multiple nodes
3276 unsigned Wrapper =
3277 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3278
3279 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3280 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3281
3282 if (Subtarget->isGVIndirectSymbol(GV))
3283 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3284 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3285 return Result;
3286}
3287
3288SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3289 SelectionDAG &DAG) const {
3290 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3290, __PRETTY_FUNCTION__))
;
3291 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&((Subtarget->useMovt(DAG.getMachineFunction()) && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3292, __PRETTY_FUNCTION__))
3292 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt(DAG.getMachineFunction()) && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3292, __PRETTY_FUNCTION__))
;
3293 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3294, __PRETTY_FUNCTION__))
3294 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3294, __PRETTY_FUNCTION__))
;
3295
3296 const TargetMachine &TM = getTargetMachine();
3297 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3298 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3299 if (GV->hasDLLImportStorageClass())
3300 TargetFlags = ARMII::MO_DLLIMPORT;
3301 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3302 TargetFlags = ARMII::MO_COFFSTUB;
3303 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3304 SDValue Result;
3305 SDLoc DL(Op);
3306
3307 ++NumMovwMovt;
3308
3309 // FIXME: Once remat is capable of dealing with instructions with register
3310 // operands, expand this into two nodes.
3311 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3312 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3313 TargetFlags));
3314 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3315 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3316 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3317 return Result;
3318}
3319
3320SDValue
3321ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3322 SDLoc dl(Op);
3323 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3324 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3325 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3326 Op.getOperand(1), Val);
3327}
3328
3329SDValue
3330ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3331 SDLoc dl(Op);
3332 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3333 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3334}
3335
3336SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3337 SelectionDAG &DAG) const {
3338 SDLoc dl(Op);
3339 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3340 Op.getOperand(0));
3341}
3342
3343SDValue
3344ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3345 const ARMSubtarget *Subtarget) const {
3346 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3347 SDLoc dl(Op);
3348 switch (IntNo) {
3349 default: return SDValue(); // Don't custom lower most intrinsics.
3350 case Intrinsic::thread_pointer: {
3351 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3352 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3353 }
3354 case Intrinsic::eh_sjlj_lsda: {
3355 MachineFunction &MF = DAG.getMachineFunction();
3356 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3357 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3359 SDValue CPAddr;
3360 bool IsPositionIndependent = isPositionIndependent();
3361 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3362 ARMConstantPoolValue *CPV =
3363 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3364 ARMCP::CPLSDA, PCAdj);
3365 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3366 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3367 SDValue Result = DAG.getLoad(
3368 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3369 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3370
3371 if (IsPositionIndependent) {
3372 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3373 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3374 }
3375 return Result;
3376 }
3377 case Intrinsic::arm_neon_vabs:
3378 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3379 Op.getOperand(1));
3380 case Intrinsic::arm_neon_vmulls:
3381 case Intrinsic::arm_neon_vmullu: {
3382 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3383 ? ARMISD::VMULLs : ARMISD::VMULLu;
3384 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3385 Op.getOperand(1), Op.getOperand(2));
3386 }
3387 case Intrinsic::arm_neon_vminnm:
3388 case Intrinsic::arm_neon_vmaxnm: {
3389 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3390 ? ISD::FMINNUM : ISD::FMAXNUM;
3391 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3392 Op.getOperand(1), Op.getOperand(2));
3393 }
3394 case Intrinsic::arm_neon_vminu:
3395 case Intrinsic::arm_neon_vmaxu: {
3396 if (Op.getValueType().isFloatingPoint())
3397 return SDValue();
3398 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3399 ? ISD::UMIN : ISD::UMAX;
3400 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3401 Op.getOperand(1), Op.getOperand(2));
3402 }
3403 case Intrinsic::arm_neon_vmins:
3404 case Intrinsic::arm_neon_vmaxs: {
3405 // v{min,max}s is overloaded between signed integers and floats.
3406 if (!Op.getValueType().isFloatingPoint()) {
3407 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3408 ? ISD::SMIN : ISD::SMAX;
3409 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3410 Op.getOperand(1), Op.getOperand(2));
3411 }
3412 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3413 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3414 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3415 Op.getOperand(1), Op.getOperand(2));
3416 }
3417 case Intrinsic::arm_neon_vtbl1:
3418 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3419 Op.getOperand(1), Op.getOperand(2));
3420 case Intrinsic::arm_neon_vtbl2:
3421 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3422 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3423 }
3424}
3425
3426static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3427 const ARMSubtarget *Subtarget) {
3428 SDLoc dl(Op);
3429 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3430 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3431 if (SSID == SyncScope::SingleThread)
3432 return Op;
3433
3434 if (!Subtarget->hasDataBarrier()) {
3435 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3436 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3437 // here.
3438 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3439, __PRETTY_FUNCTION__))
3439 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3439, __PRETTY_FUNCTION__))
;
3440 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3441 DAG.getConstant(0, dl, MVT::i32));
3442 }
3443
3444 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3445 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3446 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3447 if (Subtarget->isMClass()) {
3448 // Only a full system barrier exists in the M-class architectures.
3449 Domain = ARM_MB::SY;
3450 } else if (Subtarget->preferISHSTBarriers() &&
3451 Ord == AtomicOrdering::Release) {
3452 // Swift happens to implement ISHST barriers in a way that's compatible with
3453 // Release semantics but weaker than ISH so we'd be fools not to use
3454 // it. Beware: other processors probably don't!
3455 Domain = ARM_MB::ISHST;
3456 }
3457
3458 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3459 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3460 DAG.getConstant(Domain, dl, MVT::i32));
3461}
3462
3463static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3464 const ARMSubtarget *Subtarget) {
3465 // ARM pre v5TE and Thumb1 does not have preload instructions.
3466 if (!(Subtarget->isThumb2() ||
3467 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3468 // Just preserve the chain.
3469 return Op.getOperand(0);
3470
3471 SDLoc dl(Op);
3472 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3473 if (!isRead &&
3474 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3475 // ARMv7 with MP extension has PLDW.
3476 return Op.getOperand(0);
3477
3478 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3479 if (Subtarget->isThumb()) {
3480 // Invert the bits.
3481 isRead = ~isRead & 1;
3482 isData = ~isData & 1;
3483 }
3484
3485 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3486 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3487 DAG.getConstant(isData, dl, MVT::i32));
3488}
3489
3490static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3491 MachineFunction &MF = DAG.getMachineFunction();
3492 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3493
3494 // vastart just stores the address of the VarArgsFrameIndex slot into the
3495 // memory location argument.
3496 SDLoc dl(Op);
3497 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3499 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3500 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3501 MachinePointerInfo(SV));
3502}
3503
3504SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3505 CCValAssign &NextVA,
3506 SDValue &Root,
3507 SelectionDAG &DAG,
3508 const SDLoc &dl) const {
3509 MachineFunction &MF = DAG.getMachineFunction();
3510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3511
3512 const TargetRegisterClass *RC;
3513 if (AFI->isThumb1OnlyFunction())
3514 RC = &ARM::tGPRRegClass;
3515 else
3516 RC = &ARM::GPRRegClass;
3517
3518 // Transform the arguments stored in physical registers into virtual ones.
3519 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3520 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3521
3522 SDValue ArgValue2;
3523 if (NextVA.isMemLoc()) {
3524 MachineFrameInfo &MFI = MF.getFrameInfo();
3525 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3526
3527 // Create load node to retrieve arguments from the stack.
3528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3529 ArgValue2 = DAG.getLoad(
3530 MVT::i32, dl, Root, FIN,
3531 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3532 } else {
3533 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3534 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3535 }
3536 if (!Subtarget->isLittle())
3537 std::swap (ArgValue, ArgValue2);
3538 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3539}
3540
3541// The remaining GPRs hold either the beginning of variable-argument
3542// data, or the beginning of an aggregate passed by value (usually
3543// byval). Either way, we allocate stack slots adjacent to the data
3544// provided by our caller, and store the unallocated registers there.
3545// If this is a variadic function, the va_list pointer will begin with
3546// these values; otherwise, this reassembles a (byval) structure that
3547// was split between registers and memory.
3548// Return: The frame index registers were stored into.
3549int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3550 const SDLoc &dl, SDValue &Chain,
3551 const Value *OrigArg,
3552 unsigned InRegsParamRecordIdx,
3553 int ArgOffset, unsigned ArgSize) const {
3554 // Currently, two use-cases possible:
3555 // Case #1. Non-var-args function, and we meet first byval parameter.
3556 // Setup first unallocated register as first byval register;
3557 // eat all remained registers
3558 // (these two actions are performed by HandleByVal method).
3559 // Then, here, we initialize stack frame with
3560 // "store-reg" instructions.
3561 // Case #2. Var-args function, that doesn't contain byval parameters.
3562 // The same: eat all remained unallocated registers,
3563 // initialize stack frame.
3564
3565 MachineFunction &MF = DAG.getMachineFunction();
3566 MachineFrameInfo &MFI = MF.getFrameInfo();
3567 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3568 unsigned RBegin, REnd;
3569 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3570 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3571 } else {
3572 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3573 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3574 REnd = ARM::R4;
3575 }
3576
3577 if (REnd != RBegin)
3578 ArgOffset = -4 * (ARM::R4 - RBegin);
3579
3580 auto PtrVT = getPointerTy(DAG.getDataLayout());
3581 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3582 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3583
3584 SmallVector<SDValue, 4> MemOps;
3585 const TargetRegisterClass *RC =
3586 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3587
3588 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3589 unsigned VReg = MF.addLiveIn(Reg, RC);
3590 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3591 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3592 MachinePointerInfo(OrigArg, 4 * i));
3593 MemOps.push_back(Store);
3594 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3595 }
3596
3597 if (!MemOps.empty())
3598 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3599 return FrameIndex;
3600}
3601
3602// Setup stack frame, the va_list pointer will start from.
3603void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3604 const SDLoc &dl, SDValue &Chain,
3605 unsigned ArgOffset,
3606 unsigned TotalArgRegsSaveSize,
3607 bool ForceMutable) const {
3608 MachineFunction &MF = DAG.getMachineFunction();
3609 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3610
3611 // Try to store any remaining integer argument regs
3612 // to their spots on the stack so that they may be loaded by dereferencing
3613 // the result of va_next.
3614 // If there is no regs to be stored, just point address after last
3615 // argument passed via stack.
3616 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3617 CCInfo.getInRegsParamsCount(),
3618 CCInfo.getNextStackOffset(), 4);
3619 AFI->setVarArgsFrameIndex(FrameIndex);
3620}
3621
3622SDValue ARMTargetLowering::LowerFormalArguments(
3623 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3624 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3625 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 MachineFrameInfo &MFI = MF.getFrameInfo();
3628
3629 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3630
3631 // Assign locations to all of the incoming arguments.
3632 SmallVector<CCValAssign, 16> ArgLocs;
3633 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3634 *DAG.getContext());
3635 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3636
3637 SmallVector<SDValue, 16> ArgValues;
3638 SDValue ArgValue;
3639 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3640 unsigned CurArgIdx = 0;
3641
3642 // Initially ArgRegsSaveSize is zero.
3643 // Then we increase this value each time we meet byval parameter.
3644 // We also increase this value in case of varargs function.
3645 AFI->setArgRegsSaveSize(0);
3646
3647 // Calculate the amount of stack space that we need to allocate to store
3648 // byval and variadic arguments that are passed in registers.
3649 // We need to know this before we allocate the first byval or variadic
3650 // argument, as they will be allocated a stack slot below the CFA (Canonical
3651 // Frame Address, the stack pointer at entry to the function).
3652 unsigned ArgRegBegin = ARM::R4;
3653 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3654 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3655 break;
3656
3657 CCValAssign &VA = ArgLocs[i];
3658 unsigned Index = VA.getValNo();
3659 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3660 if (!Flags.isByVal())
3661 continue;
3662
3663 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3663, __PRETTY_FUNCTION__))
;
3664 unsigned RBegin, REnd;
3665 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3666 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3667
3668 CCInfo.nextInRegsParam();
3669 }
3670 CCInfo.rewindByValRegsInfo();
3671
3672 int lastInsIndex = -1;
3673 if (isVarArg && MFI.hasVAStart()) {
3674 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3675 if (RegIdx != array_lengthof(GPRArgRegs))
3676 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3677 }
3678
3679 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3680 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3681 auto PtrVT = getPointerTy(DAG.getDataLayout());
3682
3683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3684 CCValAssign &VA = ArgLocs[i];
3685 if (Ins[VA.getValNo()].isOrigArg()) {
3686 std::advance(CurOrigArg,
3687 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3688 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3689 }
3690 // Arguments stored in registers.
3691 if (VA.isRegLoc()) {
3692 EVT RegVT = VA.getLocVT();
3693
3694 if (VA.needsCustom()) {
3695 // f64 and vector types are split up into multiple registers or
3696 // combinations of registers and stack slots.
3697 if (VA.getLocVT() == MVT::v2f64) {
3698 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3699 Chain, DAG, dl);
3700 VA = ArgLocs[++i]; // skip ahead to next loc
3701 SDValue ArgValue2;
3702 if (VA.isMemLoc()) {
3703 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3704 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3705 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3706 MachinePointerInfo::getFixedStack(
3707 DAG.getMachineFunction(), FI));
3708 } else {
3709 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3710 Chain, DAG, dl);
3711 }
3712 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3713 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3714 ArgValue, ArgValue1,
3715 DAG.getIntPtrConstant(0, dl));
3716 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3717 ArgValue, ArgValue2,
3718 DAG.getIntPtrConstant(1, dl));
3719 } else
3720 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3721 } else {
3722 const TargetRegisterClass *RC;
3723
3724
3725 if (RegVT == MVT::f16)
3726 RC = &ARM::HPRRegClass;
3727 else if (RegVT == MVT::f32)
3728 RC = &ARM::SPRRegClass;
3729 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3730 RC = &ARM::DPRRegClass;
3731 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3732 RC = &ARM::QPRRegClass;
3733 else if (RegVT == MVT::i32)
3734 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3735 : &ARM::GPRRegClass;
3736 else
3737 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3737)
;
3738
3739 // Transform the arguments in physical registers into virtual ones.
3740 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3741 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3742 }
3743
3744 // If this is an 8 or 16-bit value, it is really passed promoted
3745 // to 32 bits. Insert an assert[sz]ext to capture this, then
3746 // truncate to the right size.
3747 switch (VA.getLocInfo()) {
3748 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3748)
;
3749 case CCValAssign::Full: break;
3750 case CCValAssign::BCvt:
3751 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3752 break;
3753 case CCValAssign::SExt:
3754 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3755 DAG.getValueType(VA.getValVT()));
3756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3757 break;
3758 case CCValAssign::ZExt:
3759 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3760 DAG.getValueType(VA.getValVT()));
3761 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3762 break;
3763 }
3764
3765 InVals.push_back(ArgValue);
3766 } else { // VA.isRegLoc()
3767 // sanity check
3768 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3768, __PRETTY_FUNCTION__))
;
3769 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3769, __PRETTY_FUNCTION__))
;
3770
3771 int index = VA.getValNo();
3772
3773 // Some Ins[] entries become multiple ArgLoc[] entries.
3774 // Process them only once.
3775 if (index != lastInsIndex)
3776 {
3777 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3778 // FIXME: For now, all byval parameter objects are marked mutable.
3779 // This can be changed with more analysis.
3780 // In case of tail call optimization mark all arguments mutable.
3781 // Since they could be overwritten by lowering of arguments in case of
3782 // a tail call.
3783 if (Flags.isByVal()) {
3784 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __PRETTY_FUNCTION__))
3785 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __PRETTY_FUNCTION__))
;
3786 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3787
3788 int FrameIndex = StoreByValRegs(
3789 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3790 VA.getLocMemOffset(), Flags.getByValSize());
3791 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3792 CCInfo.nextInRegsParam();
3793 } else {
3794 unsigned FIOffset = VA.getLocMemOffset();
3795 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3796 FIOffset, true);
3797
3798 // Create load nodes to retrieve arguments from the stack.
3799 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3800 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3801 MachinePointerInfo::getFixedStack(
3802 DAG.getMachineFunction(), FI)));
3803 }
3804 lastInsIndex = index;
3805 }
3806 }
3807 }
3808
3809 // varargs
3810 if (isVarArg && MFI.hasVAStart())
3811 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3812 CCInfo.getNextStackOffset(),
3813 TotalArgRegsSaveSize);
3814
3815 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3816
3817 return Chain;
3818}
3819
3820/// isFloatingPointZero - Return true if this is +0.0.
3821static bool isFloatingPointZero(SDValue Op) {
3822 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3823 return CFP->getValueAPF().isPosZero();
3824 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3825 // Maybe this has already been legalized into the constant pool?
3826 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3827 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3828 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3829 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3830 return CFP->getValueAPF().isPosZero();
3831 }
3832 } else if (Op->getOpcode() == ISD::BITCAST &&
3833 Op->getValueType(0) == MVT::f64) {
3834 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3835 // created by LowerConstantFP().
3836 SDValue BitcastOp = Op->getOperand(0);
3837 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3838 isNullConstant(BitcastOp->getOperand(0)))
3839 return true;
3840 }
3841 return false;
3842}
3843
3844/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3845/// the given operands.
3846SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3847 SDValue &ARMcc, SelectionDAG &DAG,
3848 const SDLoc &dl) const {
3849 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3850 unsigned C = RHSC->getZExtValue();
3851 if (!isLegalICmpImmediate((int32_t)C)) {
3852 // Constant does not fit, try adjusting it by one.
3853 switch (CC) {
3854 default: break;
3855 case ISD::SETLT:
3856 case ISD::SETGE:
3857 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3858 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3859 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3860 }
3861 break;
3862 case ISD::SETULT:
3863 case ISD::SETUGE:
3864 if (C != 0 && isLegalICmpImmediate(C-1)) {
3865 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3866 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3867 }
3868 break;
3869 case ISD::SETLE:
3870 case ISD::SETGT:
3871 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3872 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3873 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3874 }
3875 break;
3876 case ISD::SETULE:
3877 case ISD::SETUGT:
3878 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3879 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3880 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3881 }
3882 break;
3883 }
3884 }
3885 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3886 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3887 // In ARM and Thumb-2, the compare instructions can shift their second
3888 // operand.
3889 CC = ISD::getSetCCSwappedOperands(CC);
3890 std::swap(LHS, RHS);
3891 }
3892
3893 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3894 ARMISD::NodeType CompareType;
3895 switch (CondCode) {
3896 default:
3897 CompareType = ARMISD::CMP;
3898 break;
3899 case ARMCC::EQ:
3900 case ARMCC::NE:
3901 // Uses only Z Flag
3902 CompareType = ARMISD::CMPZ;
3903 break;
3904 }
3905 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3906 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3907}
3908
3909/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3910SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3911 SelectionDAG &DAG, const SDLoc &dl,
3912 bool InvalidOnQNaN) const {
3913 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)((!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3913, __PRETTY_FUNCTION__))
;
3914 SDValue Cmp;
3915 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3916 if (!isFloatingPointZero(RHS))
3917 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3918 else
3919 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3920 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3921}
3922
3923/// duplicateCmp - Glue values can have only one use, so this function
3924/// duplicates a comparison node.
3925SDValue
3926ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3927 unsigned Opc = Cmp.getOpcode();
3928 SDLoc DL(Cmp);
3929 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3930 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3931
3932 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3932, __PRETTY_FUNCTION__))
;
3933 Cmp = Cmp.getOperand(0);
3934 Opc = Cmp.getOpcode();
3935 if (Opc == ARMISD::CMPFP)
3936 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3937 Cmp.getOperand(1), Cmp.getOperand(2));
3938 else {
3939 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3939, __PRETTY_FUNCTION__))
;
3940 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3941 Cmp.getOperand(1));
3942 }
3943 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3944}
3945
3946// This function returns three things: the arithmetic computation itself
3947// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3948// comparison and the condition code define the case in which the arithmetic
3949// computation *does not* overflow.
3950std::pair<SDValue, SDValue>
3951ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3952 SDValue &ARMcc) const {
3953 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3953, __PRETTY_FUNCTION__))
;
3954
3955 SDValue Value, OverflowCmp;
3956 SDValue LHS = Op.getOperand(0);
3957 SDValue RHS = Op.getOperand(1);
3958 SDLoc dl(Op);
3959
3960 // FIXME: We are currently always generating CMPs because we don't support
3961 // generating CMN through the backend. This is not as good as the natural
3962 // CMP case because it causes a register dependency and cannot be folded
3963 // later.
3964
3965 switch (Op.getOpcode()) {
3966 default:
3967 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 3967)
;
3968 case ISD::SADDO:
3969 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3970 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3971 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3972 break;
3973 case ISD::UADDO:
3974 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3975 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3976 // We do not use it in the USUBO case as Value may not be used.
3977 Value = DAG.getNode(ARMISD::ADDC, dl,
3978 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3979 .getValue(0);
3980 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3981 break;
3982 case ISD::SSUBO:
3983 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3984 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3985 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3986 break;
3987 case ISD::USUBO:
3988 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3989 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3990 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3991 break;
3992 case ISD::UMULO:
3993 // We generate a UMUL_LOHI and then check if the high word is 0.
3994 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3995 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3996 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3997 LHS, RHS);
3998 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3999 DAG.getConstant(0, dl, MVT::i32));
4000 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4001 break;
4002 case ISD::SMULO:
4003 // We generate a SMUL_LOHI and then check if all the bits of the high word
4004 // are the same as the sign bit of the low word.
4005 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4006 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4007 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4008 LHS, RHS);
4009 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4010 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4011 Value.getValue(0),
4012 DAG.getConstant(31, dl, MVT::i32)));
4013 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4014 break;
4015 } // switch (...)
4016
4017 return std::make_pair(Value, OverflowCmp);
4018}
4019
4020SDValue
4021ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4022 // Let legalize expand this if it isn't a legal type yet.
4023 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4024 return SDValue();
4025
4026 SDValue Value, OverflowCmp;
4027 SDValue ARMcc;
4028 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4029 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4030 SDLoc dl(Op);
4031 // We use 0 and 1 as false and true values.
4032 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4033 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4034 EVT VT = Op.getValueType();
4035
4036 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4037 ARMcc, CCR, OverflowCmp);
4038
4039 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4040 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4041}
4042
4043static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4044 SelectionDAG &DAG) {
4045 SDLoc DL(BoolCarry);
4046 EVT CarryVT = BoolCarry.getValueType();
4047
4048 // This converts the boolean value carry into the carry flag by doing
4049 // ARMISD::SUBC Carry, 1
4050 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4051 DAG.getVTList(CarryVT, MVT::i32),
4052 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4053 return Carry.getValue(1);
4054}
4055
4056static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4057 SelectionDAG &DAG) {
4058 SDLoc DL(Flags);
4059
4060 // Now convert the carry flag into a boolean carry. We do this
4061 // using ARMISD:ADDE 0, 0, Carry
4062 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4063 DAG.getConstant(0, DL, MVT::i32),
4064 DAG.getConstant(0, DL, MVT::i32), Flags);
4065}
4066
4067SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4068 SelectionDAG &DAG) const {
4069 // Let legalize expand this if it isn't a legal type yet.
4070 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4071 return SDValue();
4072
4073 SDValue LHS = Op.getOperand(0);
4074 SDValue RHS = Op.getOperand(1);
4075 SDLoc dl(Op);
4076
4077 EVT VT = Op.getValueType();
4078 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4079 SDValue Value;
4080 SDValue Overflow;
4081 switch (Op.getOpcode()) {
4082 default:
4083 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4083)
;
4084 case ISD::UADDO:
4085 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4086 // Convert the carry flag into a boolean value.
4087 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4088 break;
4089 case ISD::USUBO: {
4090 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4091 // Convert the carry flag into a boolean value.
4092 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4093 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4094 // value. So compute 1 - C.
4095 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4096 DAG.getConstant(1, dl, MVT::i32), Overflow);
4097 break;
4098 }
4099 }
4100
4101 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4102}
4103
4104SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4105 SDValue Cond = Op.getOperand(0);
4106 SDValue SelectTrue = Op.getOperand(1);
4107 SDValue SelectFalse = Op.getOperand(2);
4108 SDLoc dl(Op);
4109 unsigned Opc = Cond.getOpcode();
4110
4111 if (Cond.getResNo() == 1 &&
4112 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4113 Opc == ISD::USUBO)) {
4114 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4115 return SDValue();
4116
4117 SDValue Value, OverflowCmp;
4118 SDValue ARMcc;
4119 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4120 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4121 EVT VT = Op.getValueType();
4122
4123 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4124 OverflowCmp, DAG);
4125 }
4126
4127 // Convert:
4128 //
4129 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4130 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4131 //
4132 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4133 const ConstantSDNode *CMOVTrue =
4134 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4135 const ConstantSDNode *CMOVFalse =
4136 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4137
4138 if (CMOVTrue && CMOVFalse) {
4139 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4140 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4141
4142 SDValue True;
4143 SDValue False;
4144 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4145 True = SelectTrue;
4146 False = SelectFalse;
4147 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4148 True = SelectFalse;
4149 False = SelectTrue;
4150 }
4151
4152 if (True.getNode() && False.getNode()) {
4153 EVT VT = Op.getValueType();
4154 SDValue ARMcc = Cond.getOperand(2);
4155 SDValue CCR = Cond.getOperand(3);
4156 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4157 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4157, __PRETTY_FUNCTION__))
;
4158 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4159 }
4160 }
4161 }
4162
4163 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4164 // undefined bits before doing a full-word comparison with zero.
4165 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4166 DAG.getConstant(1, dl, Cond.getValueType()));
4167
4168 return DAG.getSelectCC(dl, Cond,
4169 DAG.getConstant(0, dl, Cond.getValueType()),
4170 SelectTrue, SelectFalse, ISD::SETNE);
4171}
4172
4173static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4174 bool &swpCmpOps, bool &swpVselOps) {
4175 // Start by selecting the GE condition code for opcodes that return true for
4176 // 'equality'
4177 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4178 CC == ISD::SETULE)
4179 CondCode = ARMCC::GE;
4180
4181 // and GT for opcodes that return false for 'equality'.
4182 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4183 CC == ISD::SETULT)
4184 CondCode = ARMCC::GT;
4185
4186 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4187 // to swap the compare operands.
4188 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4189 CC == ISD::SETULT)
4190 swpCmpOps = true;
4191
4192 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4193 // If we have an unordered opcode, we need to swap the operands to the VSEL
4194 // instruction (effectively negating the condition).
4195 //
4196 // This also has the effect of swapping which one of 'less' or 'greater'
4197 // returns true, so we also swap the compare operands. It also switches
4198 // whether we return true for 'equality', so we compensate by picking the
4199 // opposite condition code to our original choice.
4200 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4201 CC == ISD::SETUGT) {
4202 swpCmpOps = !swpCmpOps;
4203 swpVselOps = !swpVselOps;
4204 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4205 }
4206
4207 // 'ordered' is 'anything but unordered', so use the VS condition code and
4208 // swap the VSEL operands.
4209 if (CC == ISD::SETO) {
4210 CondCode = ARMCC::VS;
4211 swpVselOps = true;
4212 }
4213
4214 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4215 // code and swap the VSEL operands.
4216 if (CC == ISD::SETUNE) {
4217 CondCode = ARMCC::EQ;
4218 swpVselOps = true;
4219 }
4220}
4221
4222SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4223 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4224 SDValue Cmp, SelectionDAG &DAG) const {
4225 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4226 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4227 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4228 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4229 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4230
4231 SDValue TrueLow = TrueVal.getValue(0);
4232 SDValue TrueHigh = TrueVal.getValue(1);
4233 SDValue FalseLow = FalseVal.getValue(0);
4234 SDValue FalseHigh = FalseVal.getValue(1);
4235
4236 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4237 ARMcc, CCR, Cmp);
4238 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4239 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4240
4241 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4242 } else {
4243 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4244 Cmp);
4245 }
4246}
4247
4248static bool isGTorGE(ISD::CondCode CC) {
4249 return CC == ISD::SETGT || CC == ISD::SETGE;
4250}
4251
4252static bool isLTorLE(ISD::CondCode CC) {
4253 return CC == ISD::SETLT || CC == ISD::SETLE;
4254}
4255
4256// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4257// All of these conditions (and their <= and >= counterparts) will do:
4258// x < k ? k : x
4259// x > k ? x : k
4260// k < x ? x : k
4261// k > x ? k : x
4262static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4263 const SDValue TrueVal, const SDValue FalseVal,
4264 const ISD::CondCode CC, const SDValue K) {
4265 return (isGTorGE(CC) &&
4266 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4267 (isLTorLE(CC) &&
4268 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4269}
4270
4271// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4272static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4273 const SDValue TrueVal, const SDValue FalseVal,
4274 const ISD::CondCode CC, const SDValue K) {
4275 return (isGTorGE(CC) &&
4276 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4277 (isLTorLE(CC) &&
4278 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4279}
4280
4281// Check if two chained conditionals could be converted into SSAT or USAT.
4282//
4283// SSAT can replace a set of two conditional selectors that bound a number to an
4284// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4285//
4286// x < -k ? -k : (x > k ? k : x)
4287// x < -k ? -k : (x < k ? x : k)
4288// x > -k ? (x > k ? k : x) : -k
4289// x < k ? (x < -k ? -k : x) : k
4290// etc.
4291//
4292// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4293// a power of 2.
4294//
4295// It returns true if the conversion can be done, false otherwise.
4296// Additionally, the variable is returned in parameter V, the constant in K and
4297// usat is set to true if the conditional represents an unsigned saturation
4298static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4299 uint64_t &K, bool &usat) {
4300 SDValue LHS1 = Op.getOperand(0);
4301 SDValue RHS1 = Op.getOperand(1);
4302 SDValue TrueVal1 = Op.getOperand(2);
4303 SDValue FalseVal1 = Op.getOperand(3);
4304 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4305
4306 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4307 if (Op2.getOpcode() != ISD::SELECT_CC)
4308 return false;
4309
4310 SDValue LHS2 = Op2.getOperand(0);
4311 SDValue RHS2 = Op2.getOperand(1);
4312 SDValue TrueVal2 = Op2.getOperand(2);
4313 SDValue FalseVal2 = Op2.getOperand(3);
4314 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4315
4316 // Find out which are the constants and which are the variables
4317 // in each conditional
4318 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4319 ? &RHS1
4320 : nullptr;
4321 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4322 ? &RHS2
4323 : nullptr;
4324 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4325 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4326 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4327 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4328
4329 // We must detect cases where the original operations worked with 16- or
4330 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4331 // must work with sign-extended values but the select operations return
4332 // the original non-extended value.
4333 SDValue V2TmpReg = V2Tmp;
4334 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4335 V2TmpReg = V2Tmp->getOperand(0);
4336
4337 // Check that the registers and the constants have the correct values
4338 // in both conditionals
4339 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4340 V2TmpReg != V2)
4341 return false;
4342
4343 // Figure out which conditional is saturating the lower/upper bound.
4344 const SDValue *LowerCheckOp =
4345 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4346 ? &Op
4347 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4348 ? &Op2
4349 : nullptr;
4350 const SDValue *UpperCheckOp =
4351 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4352 ? &Op
4353 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4354 ? &Op2
4355 : nullptr;
4356
4357 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4358 return false;
4359
4360 // Check that the constant in the lower-bound check is
4361 // the opposite of the constant in the upper-bound check
4362 // in 1's complement.
4363 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4364 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4365 int64_t PosVal = std::max(Val1, Val2);
4366 int64_t NegVal = std::min(Val1, Val2);
4367
4368 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4369 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4370 isPowerOf2_64(PosVal + 1)) {
4371
4372 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4373 if (Val1 == ~Val2)
4374 usat = false;
4375 else if (NegVal == 0)
4376 usat = true;
4377 else
4378 return false;
4379
4380 V = V2;
4381 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4382
4383 return true;
4384 }
4385
4386 return false;
4387}
4388
4389// Check if a condition of the type x < k ? k : x can be converted into a
4390// bit operation instead of conditional moves.
4391// Currently this is allowed given:
4392// - The conditions and values match up
4393// - k is 0 or -1 (all ones)
4394// This function will not check the last condition, thats up to the caller
4395// It returns true if the transformation can be made, and in such case
4396// returns x in V, and k in SatK.
4397static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4398 SDValue &SatK)
4399{
4400 SDValue LHS = Op.getOperand(0);
4401 SDValue RHS = Op.getOperand(1);
4402 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4403 SDValue TrueVal = Op.getOperand(2);
4404 SDValue FalseVal = Op.getOperand(3);
4405
4406 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4407 ? &RHS
4408 : nullptr;
4409
4410 // No constant operation in comparison, early out
4411 if (!K)
4412 return false;
4413
4414 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4415 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4416 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4417
4418 // If the constant on left and right side, or variable on left and right,
4419 // does not match, early out
4420 if (*K != KTmp || V != VTmp)
4421 return false;
4422
4423 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4424 SatK = *K;
4425 return true;
4426 }
4427
4428 return false;
4429}
4430
4431SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4432 EVT VT = Op.getValueType();
4433 SDLoc dl(Op);
4434
4435 // Try to convert two saturating conditional selects into a single SSAT
4436 SDValue SatValue;
4437 uint64_t SatConstant;
4438 bool SatUSat;
4439 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4440 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4441 if (SatUSat)
4442 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4443 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4444 else
4445 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4446 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4447 }
4448
4449 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4450 // into more efficient bit operations, which is possible when k is 0 or -1
4451 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4452 // single instructions. On Thumb the shift and the bit operation will be two
4453 // instructions.
4454 // Only allow this transformation on full-width (32-bit) operations
4455 SDValue LowerSatConstant;
4456 if (VT == MVT::i32 &&
4457 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4458 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4459 DAG.getConstant(31, dl, VT));
4460 if (isNullConstant(LowerSatConstant)) {
4461 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4462 DAG.getAllOnesConstant(dl, VT));
4463 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4464 } else if (isAllOnesConstant(LowerSatConstant))
4465 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4466 }
4467
4468 SDValue LHS = Op.getOperand(0);
4469 SDValue RHS = Op.getOperand(1);
4470 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4471 SDValue TrueVal = Op.getOperand(2);
4472 SDValue FalseVal = Op.getOperand(3);
4473
4474 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4475 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4476 dl);
4477
4478 // If softenSetCCOperands only returned one value, we should compare it to
4479 // zero.
4480 if (!RHS.getNode()) {
4481 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4482 CC = ISD::SETNE;
4483 }
4484 }
4485
4486 if (LHS.getValueType() == MVT::i32) {
4487 // Try to generate VSEL on ARMv8.
4488 // The VSEL instruction can't use all the usual ARM condition
4489 // codes: it only has two bits to select the condition code, so it's
4490 // constrained to use only GE, GT, VS and EQ.
4491 //
4492 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4493 // swap the operands of the previous compare instruction (effectively
4494 // inverting the compare condition, swapping 'less' and 'greater') and
4495 // sometimes need to swap the operands to the VSEL (which inverts the
4496 // condition in the sense of firing whenever the previous condition didn't)
4497 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4498 TrueVal.getValueType() == MVT::f64)) {
4499 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4500 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4501 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4502 CC = ISD::getSetCCInverse(CC, true);
4503 std::swap(TrueVal, FalseVal);
4504 }
4505 }
4506
4507 SDValue ARMcc;
4508 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4509 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4510 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4511 }
4512
4513 ARMCC::CondCodes CondCode, CondCode2;
4514 bool InvalidOnQNaN;
4515 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4516
4517 // Normalize the fp compare. If RHS is zero we keep it there so we match
4518 // CMPFPw0 instead of CMPFP.
4519 if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
4520 (TrueVal.getValueType() == MVT::f16 ||
4521 TrueVal.getValueType() == MVT::f32 ||
4522 TrueVal.getValueType() == MVT::f64)) {
4523 bool swpCmpOps = false;
4524 bool swpVselOps = false;
4525 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4526
4527 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4528 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4529 if (swpCmpOps)
4530 std::swap(LHS, RHS);
4531 if (swpVselOps)
4532 std::swap(TrueVal, FalseVal);
4533 }
4534 }
4535
4536 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4537 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4538 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4539 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4540 if (CondCode2 != ARMCC::AL) {
4541 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4542 // FIXME: Needs another CMP because flag can have but one use.
4543 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4544 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4545 }
4546 return Result;
4547}
4548
4549/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4550/// to morph to an integer compare sequence.
4551static bool canChangeToInt(SDValue Op, bool &SeenZero,
4552 const ARMSubtarget *Subtarget) {
4553 SDNode *N = Op.getNode();
4554 if (!N->hasOneUse())
4555 // Otherwise it requires moving the value from fp to integer registers.
4556 return false;
4557 if (!N->getNumValues())
4558 return false;
4559 EVT VT = Op.getValueType();
4560 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4561 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4562 // vmrs are very slow, e.g. cortex-a8.
4563 return false;
4564
4565 if (isFloatingPointZero(Op)) {
4566 SeenZero = true;
4567 return true;
4568 }
4569 return ISD::isNormalLoad(N);
4570}
4571
4572static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4573 if (isFloatingPointZero(Op))
4574 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4575
4576 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4577 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4578 Ld->getPointerInfo(), Ld->getAlignment(),
4579 Ld->getMemOperand()->getFlags());
4580
4581 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4581)
;
4582}
4583
4584static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4585 SDValue &RetVal1, SDValue &RetVal2) {
4586 SDLoc dl(Op);
4587
4588 if (isFloatingPointZero(Op)) {
4589 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4590 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4591 return;
4592 }
4593
4594 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4595 SDValue Ptr = Ld->getBasePtr();
4596 RetVal1 =
4597 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4598 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4599
4600 EVT PtrType = Ptr.getValueType();
4601 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4602 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4603 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4604 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4605 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4606 Ld->getMemOperand()->getFlags());
4607 return;
4608 }
4609
4610 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4610)
;
4611}
4612
4613/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4614/// f32 and even f64 comparisons to integer ones.
4615SDValue
4616ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4617 SDValue Chain = Op.getOperand(0);
4618 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4619 SDValue LHS = Op.getOperand(2);
4620 SDValue RHS = Op.getOperand(3);
4621 SDValue Dest = Op.getOperand(4);
4622 SDLoc dl(Op);
4623
4624 bool LHSSeenZero = false;
4625 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4626 bool RHSSeenZero = false;
4627 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4628 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4629 // If unsafe fp math optimization is enabled and there are no other uses of
4630 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4631 // to an integer comparison.
4632 if (CC == ISD::SETOEQ)
4633 CC = ISD::SETEQ;
4634 else if (CC == ISD::SETUNE)
4635 CC = ISD::SETNE;
4636
4637 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4638 SDValue ARMcc;
4639 if (LHS.getValueType() == MVT::f32) {
4640 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4641 bitcastf32Toi32(LHS, DAG), Mask);
4642 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4643 bitcastf32Toi32(RHS, DAG), Mask);
4644 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4645 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4646 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4647 Chain, Dest, ARMcc, CCR, Cmp);
4648 }
4649
4650 SDValue LHS1, LHS2;
4651 SDValue RHS1, RHS2;
4652 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4653 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4654 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4655 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4656 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4657 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4658 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4659 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4660 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4661 }
4662
4663 return SDValue();
4664}
4665
4666SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4667 SDValue Chain = Op.getOperand(0);
4668 SDValue Cond = Op.getOperand(1);
4669 SDValue Dest = Op.getOperand(2);
4670 SDLoc dl(Op);
4671
4672 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4673 // instruction.
4674 unsigned Opc = Cond.getOpcode();
4675 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4676 !Subtarget->isThumb1Only();
4677 if (Cond.getResNo() == 1 &&
4678 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4679 Opc == ISD::USUBO || OptimizeMul)) {
4680 // Only lower legal XALUO ops.
4681 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4682 return SDValue();
4683
4684 // The actual operation with overflow check.
4685 SDValue Value, OverflowCmp;
4686 SDValue ARMcc;
4687 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4688
4689 // Reverse the condition code.
4690 ARMCC::CondCodes CondCode =
4691 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4692 CondCode = ARMCC::getOppositeCondition(CondCode);
4693 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4694 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4695
4696 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4697 OverflowCmp);
4698 }
4699
4700 return SDValue();
4701}
4702
4703SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4704 SDValue Chain = Op.getOperand(0);
4705 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4706 SDValue LHS = Op.getOperand(2);
4707 SDValue RHS = Op.getOperand(3);
4708 SDValue Dest = Op.getOperand(4);
4709 SDLoc dl(Op);
4710
4711 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4712 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4713 dl);
4714
4715 // If softenSetCCOperands only returned one value, we should compare it to
4716 // zero.
4717 if (!RHS.getNode()) {
4718 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4719 CC = ISD::SETNE;
4720 }
4721 }
4722
4723 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4724 // instruction.
4725 unsigned Opc = LHS.getOpcode();
4726 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4727 !Subtarget->isThumb1Only();
4728 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4729 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4730 Opc == ISD::USUBO || OptimizeMul) &&
4731 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4732 // Only lower legal XALUO ops.
4733 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4734 return SDValue();
4735
4736 // The actual operation with overflow check.
4737 SDValue Value, OverflowCmp;
4738 SDValue ARMcc;
4739 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4740
4741 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4742 // Reverse the condition code.
4743 ARMCC::CondCodes CondCode =
4744 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4745 CondCode = ARMCC::getOppositeCondition(CondCode);
4746 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4747 }
4748 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4749
4750 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4751 OverflowCmp);
4752 }
4753
4754 if (LHS.getValueType() == MVT::i32) {
4755 SDValue ARMcc;
4756 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4757 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4758 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4759 Chain, Dest, ARMcc, CCR, Cmp);
4760 }
4761
4762 if (getTargetMachine().Options.UnsafeFPMath &&
4763 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4764 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4765 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4766 return Result;
4767 }
4768
4769 ARMCC::CondCodes CondCode, CondCode2;
4770 bool InvalidOnQNaN;
4771 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4772
4773 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4774 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4775 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4776 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4777 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4778 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4779 if (CondCode2 != ARMCC::AL) {
4780 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4781 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4782 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4783 }
4784 return Res;
4785}
4786
4787SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4788 SDValue Chain = Op.getOperand(0);
4789 SDValue Table = Op.getOperand(1);
4790 SDValue Index = Op.getOperand(2);
4791 SDLoc dl(Op);
4792
4793 EVT PTy = getPointerTy(DAG.getDataLayout());
4794 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4795 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4796 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4797 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4798 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4799 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4800 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4801 // which does another jump to the destination. This also makes it easier
4802 // to translate it to TBB / TBH later (Thumb2 only).
4803 // FIXME: This might not work if the function is extremely large.
4804 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4805 Addr, Op.getOperand(2), JTI);
4806 }
4807 if (isPositionIndependent() || Subtarget->isROPI()) {
4808 Addr =
4809 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4810 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4811 Chain = Addr.getValue(1);
4812 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4813 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4814 } else {
4815 Addr =
4816 DAG.getLoad(PTy, dl, Chain, Addr,
4817 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4818 Chain = Addr.getValue(1);
4819 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4820 }
4821}
4822
4823static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4824 EVT VT = Op.getValueType();
4825 SDLoc dl(Op);
4826
4827 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4828 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4829 return Op;
4830 return DAG.UnrollVectorOp(Op.getNode());
4831 }
4832
4833 const bool HasFullFP16 =
4834 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4835
4836 EVT NewTy;
4837 const EVT OpTy = Op.getOperand(0).getValueType();
4838 if (OpTy == MVT::v4f32)
4839 NewTy = MVT::v4i32;
4840 else if (OpTy == MVT::v4f16 && HasFullFP16)
4841 NewTy = MVT::v4i16;
4842 else if (OpTy == MVT::v8f16 && HasFullFP16)
4843 NewTy = MVT::v8i16;
4844 else
4845 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4845)
;
4846
4847 if (VT != MVT::v4i16 && VT != MVT::v8i16)
4848 return DAG.UnrollVectorOp(Op.getNode());
4849
4850 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
4851 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4852}
4853
4854SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4855 EVT VT = Op.getValueType();
4856 if (VT.isVector())
4857 return LowerVectorFP_TO_INT(Op, DAG);
4858 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4859 RTLIB::Libcall LC;
4860 if (Op.getOpcode() == ISD::FP_TO_SINT)
4861 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4862 Op.getValueType());
4863 else
4864 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4865 Op.getValueType());
4866 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4867 /*isSigned*/ false, SDLoc(Op)).first;
4868 }
4869
4870 return Op;
4871}
4872
4873static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4874 EVT VT = Op.getValueType();
4875 SDLoc dl(Op);
4876
4877 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4878 if (VT.getVectorElementType() == MVT::f32)
4879 return Op;
4880 return DAG.UnrollVectorOp(Op.getNode());
4881 }
4882
4883 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4885, __PRETTY_FUNCTION__))
4884 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4885, __PRETTY_FUNCTION__))
4885 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4885, __PRETTY_FUNCTION__))
;
4886
4887 const bool HasFullFP16 =
4888 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
4889
4890 EVT DestVecType;
4891 if (VT == MVT::v4f32)
4892 DestVecType = MVT::v4i32;
4893 else if (VT == MVT::v4f16 && HasFullFP16)
4894 DestVecType = MVT::v4i16;
4895 else if (VT == MVT::v8f16 && HasFullFP16)
4896 DestVecType = MVT::v8i16;
4897 else
4898 return DAG.UnrollVectorOp(Op.getNode());
4899
4900 unsigned CastOpc;
4901 unsigned Opc;
4902 switch (Op.getOpcode()) {
4903 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 4903)
;
4904 case ISD::SINT_TO_FP:
4905 CastOpc = ISD::SIGN_EXTEND;
4906 Opc = ISD::SINT_TO_FP;
4907 break;
4908 case ISD::UINT_TO_FP:
4909 CastOpc = ISD::ZERO_EXTEND;
4910 Opc = ISD::UINT_TO_FP;
4911 break;
4912 }
4913
4914 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
4915 return DAG.getNode(Opc, dl, VT, Op);
4916}
4917
4918SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4919 EVT VT = Op.getValueType();
4920 if (VT.isVector())
4921 return LowerVectorINT_TO_FP(Op, DAG);
4922 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4923 RTLIB::Libcall LC;
4924 if (Op.getOpcode() == ISD::SINT_TO_FP)
4925 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4926 Op.getValueType());
4927 else
4928 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4929 Op.getValueType());
4930 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4931 /*isSigned*/ false, SDLoc(Op)).first;
4932 }
4933
4934 return Op;
4935}
4936
4937SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4938 // Implement fcopysign with a fabs and a conditional fneg.
4939 SDValue Tmp0 = Op.getOperand(0);
4940 SDValue Tmp1 = Op.getOperand(1);
4941 SDLoc dl(Op);
4942 EVT VT = Op.getValueType();
4943 EVT SrcVT = Tmp1.getValueType();
4944 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4945 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4946 bool UseNEON = !InGPR && Subtarget->hasNEON();
4947
4948 if (UseNEON) {
4949 // Use VBSL to copy the sign bit.
4950 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4951 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4952 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4953 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4954 if (VT == MVT::f64)
4955 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4956 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4957 DAG.getConstant(32, dl, MVT::i32));
4958 else /*if (VT == MVT::f32)*/
4959 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4960 if (SrcVT == MVT::f32) {
4961 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4962 if (VT == MVT::f64)
4963 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4964 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4965 DAG.getConstant(32, dl, MVT::i32));
4966 } else if (VT == MVT::f32)
4967 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4968 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4969 DAG.getConstant(32, dl, MVT::i32));
4970 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4971 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4972
4973 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4974 dl, MVT::i32);
4975 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4976 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4977 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4978
4979 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4980 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4981 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4982 if (VT == MVT::f32) {
4983 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4984 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4985 DAG.getConstant(0, dl, MVT::i32));
4986 } else {
4987 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4988 }
4989
4990 return Res;
4991 }
4992
4993 // Bitcast operand 1 to i32.
4994 if (SrcVT == MVT::f64)
4995 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4996 Tmp1).getValue(1);
4997 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4998
4999 // Or in the signbit with integer operations.
5000 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5001 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5002 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5003 if (VT == MVT::f32) {
5004 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5005 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5006 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5007 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5008 }
5009
5010 // f64: Or the high part with signbit and then combine two parts.
5011 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5012 Tmp0);
5013 SDValue Lo = Tmp0.getValue(0);
5014 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5015 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5016 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5017}
5018
5019SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5020 MachineFunction &MF = DAG.getMachineFunction();
5021 MachineFrameInfo &MFI = MF.getFrameInfo();
5022 MFI.setReturnAddressIsTaken(true);
5023
5024 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5025 return SDValue();
5026
5027 EVT VT = Op.getValueType();
5028 SDLoc dl(Op);
5029 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5030 if (Depth) {
5031 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5032 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5033 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5034 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5035 MachinePointerInfo());
5036 }
5037
5038 // Return LR, which contains the return address. Mark it an implicit live-in.
5039 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5040 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5041}
5042
5043SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5044 const ARMBaseRegisterInfo &ARI =
5045 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5046 MachineFunction &MF = DAG.getMachineFunction();
5047 MachineFrameInfo &MFI = MF.getFrameInfo();
5048 MFI.setFrameAddressIsTaken(true);
5049
5050 EVT VT = Op.getValueType();
5051 SDLoc dl(Op); // FIXME probably not meaningful
5052 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5053 unsigned FrameReg = ARI.getFrameRegister(MF);
5054 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5055 while (Depth--)
5056 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5057 MachinePointerInfo());
5058 return FrameAddr;
5059}
5060
5061// FIXME? Maybe this could be a TableGen attribute on some registers and
5062// this table could be generated automatically from RegInfo.
5063unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5064 SelectionDAG &DAG) const {
5065 unsigned Reg = StringSwitch<unsigned>(RegName)
5066 .Case("sp", ARM::SP)
5067 .Default(0);
5068 if (Reg)
5069 return Reg;
5070 report_fatal_error(Twine("Invalid register name \""
5071 + StringRef(RegName) + "\"."));
5072}
5073
5074// Result is 64 bit value so split into two 32 bit values and return as a
5075// pair of values.
5076static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5077 SelectionDAG &DAG) {
5078 SDLoc DL(N);
5079
5080 // This function is only supposed to be called for i64 type destination.
5081 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5082, __PRETTY_FUNCTION__))
5082 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5082, __PRETTY_FUNCTION__))
;
5083
5084 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5085 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5086 N->getOperand(0),
5087 N->getOperand(1));
5088
5089 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5090 Read.getValue(1)));
5091 Results.push_back(Read.getOperand(0));
5092}
5093
5094/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5095/// When \p DstVT, the destination type of \p BC, is on the vector
5096/// register bank and the source of bitcast, \p Op, operates on the same bank,
5097/// it might be possible to combine them, such that everything stays on the
5098/// vector register bank.
5099/// \p return The node that would replace \p BT, if the combine
5100/// is possible.
5101static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5102 SelectionDAG &DAG) {
5103 SDValue Op = BC->getOperand(0);
5104 EVT DstVT = BC->getValueType(0);
5105
5106 // The only vector instruction that can produce a scalar (remember,
5107 // since the bitcast was about to be turned into VMOVDRR, the source
5108 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5109 // Moreover, we can do this combine only if there is one use.
5110 // Finally, if the destination type is not a vector, there is not
5111 // much point on forcing everything on the vector bank.
5112 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5113 !Op.hasOneUse())
5114 return SDValue();
5115
5116 // If the index is not constant, we will introduce an additional
5117 // multiply that will stick.
5118 // Give up in that case.
5119 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5120 if (!Index)
5121 return SDValue();
5122 unsigned DstNumElt = DstVT.getVectorNumElements();
5123
5124 // Compute the new index.
5125 const APInt &APIntIndex = Index->getAPIntValue();
5126 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5127 NewIndex *= APIntIndex;
5128 // Check if the new constant index fits into i32.
5129 if (NewIndex.getBitWidth() > 32)
5130 return SDValue();
5131
5132 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5133 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5134 SDLoc dl(Op);
5135 SDValue ExtractSrc = Op.getOperand(0);
5136 EVT VecVT = EVT::getVectorVT(
5137 *DAG.getContext(), DstVT.getScalarType(),
5138 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5139 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5140 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5141 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5142}
5143
5144/// ExpandBITCAST - If the target supports VFP, this function is called to
5145/// expand a bit convert where either the source or destination type is i64 to
5146/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5147/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5148/// vectors), since the legalizer won't know what to do with that.
5149static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5150 const ARMSubtarget *Subtarget) {
5151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5152 SDLoc dl(N);
5153 SDValue Op = N->getOperand(0);
5154
5155 // This function is only supposed to be called for i64 types, either as the
5156 // source or destination of the bit convert.
5157 EVT SrcVT = Op.getValueType();
5158 EVT DstVT = N->getValueType(0);
5159 const bool HasFullFP16 = Subtarget->hasFullFP16();
5160
5161 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5162 // FullFP16: half values are passed in S-registers, and we don't
5163 // need any of the bitcast and moves:
5164 //
5165 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5166 // t5: i32 = bitcast t2
5167 // t18: f16 = ARMISD::VMOVhr t5
5168 if (Op.getOpcode() != ISD::CopyFromReg ||
5169 Op.getValueType() != MVT::f32)
5170 return SDValue();
5171
5172 auto Move = N->use_begin();
5173 if (Move->getOpcode() != ARMISD::VMOVhr)
5174 return SDValue();
5175
5176 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5177 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5178 DAG.ReplaceAllUsesWith(*Move, &Copy);
5179 return Copy;
5180 }
5181
5182 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5183 if (!HasFullFP16)
5184 return SDValue();
5185 // SoftFP: read half-precision arguments:
5186 //
5187 // t2: i32,ch = ...
5188 // t7: i16 = truncate t2 <~~~~ Op
5189 // t8: f16 = bitcast t7 <~~~~ N
5190 //
5191 if (Op.getOperand(0).getValueType() == MVT::i32)
5192 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5193 MVT::f16, Op.getOperand(0));
5194
5195 return SDValue();
5196 }
5197
5198 // Half-precision return values
5199 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5200 if (!HasFullFP16)
5201 return SDValue();
5202 //
5203 // t11: f16 = fadd t8, t10
5204 // t12: i16 = bitcast t11 <~~~ SDNode N
5205 // t13: i32 = zero_extend t12
5206 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5207 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5208 //
5209 // transform this into:
5210 //
5211 // t20: i32 = ARMISD::VMOVrh t11
5212 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5213 //
5214 auto ZeroExtend = N->use_begin();
5215 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5216 ZeroExtend->getValueType(0) != MVT::i32)
5217 return SDValue();
5218
5219 auto Copy = ZeroExtend->use_begin();
5220 if (Copy->getOpcode() == ISD::CopyToReg &&
5221 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5222 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5223 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5224 return Cvt;
5225 }
5226 return SDValue();
5227 }
5228
5229 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5230 return SDValue();
5231
5232 // Turn i64->f64 into VMOVDRR.
5233 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5234 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5235 // if we can combine the bitcast with its source.
5236 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5237 return Val;
5238
5239 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5240 DAG.getConstant(0, dl, MVT::i32));
5241 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5242 DAG.getConstant(1, dl, MVT::i32));
5243 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5244 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5245 }
5246
5247 // Turn f64->i64 into VMOVRRD.
5248 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5249 SDValue Cvt;
5250 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5251 SrcVT.getVectorNumElements() > 1)
5252 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5253 DAG.getVTList(MVT::i32, MVT::i32),
5254 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5255 else
5256 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5257 DAG.getVTList(MVT::i32, MVT::i32), Op);
5258 // Merge the pieces into a single i64 value.
5259 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5260 }
5261
5262 return SDValue();
5263}
5264
5265/// getZeroVector - Returns a vector of specified type with all zero elements.
5266/// Zero vectors are used to represent vector negation and in those cases
5267/// will be implemented with the NEON VNEG instruction. However, VNEG does
5268/// not support i64 elements, so sometimes the zero vectors will need to be
5269/// explicitly constructed. Regardless, use a canonical VMOV to create the
5270/// zero vector.
5271static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5272 assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5272, __PRETTY_FUNCTION__))
;
5273 // The canonical modified immediate encoding of a zero vector is....0!
5274 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5275 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5276 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5277 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5278}
5279
5280/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5281/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5282SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5283 SelectionDAG &DAG) const {
5284 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5284, __PRETTY_FUNCTION__))
;
5285 EVT VT = Op.getValueType();
5286 unsigned VTBits = VT.getSizeInBits();
5287 SDLoc dl(Op);
5288 SDValue ShOpLo = Op.getOperand(0);
5289 SDValue ShOpHi = Op.getOperand(1);
5290 SDValue ShAmt = Op.getOperand(2);
5291 SDValue ARMcc;
5292 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5293 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5294
5295 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::
SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5295, __PRETTY_FUNCTION__))
;
5296
5297 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5298 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5299 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5300 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5301 DAG.getConstant(VTBits, dl, MVT::i32));
5302 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5303 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5304 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5305 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5306 ISD::SETGE, ARMcc, DAG, dl);
5307 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5308 ARMcc, CCR, CmpLo);
5309
5310 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5311 SDValue HiBigShift = Opc == ISD::SRA
5312 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5313 DAG.getConstant(VTBits - 1, dl, VT))
5314 : DAG.getConstant(0, dl, VT);
5315 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5316 ISD::SETGE, ARMcc, DAG, dl);
5317 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5318 ARMcc, CCR, CmpHi);
5319
5320 SDValue Ops[2] = { Lo, Hi };
5321 return DAG.getMergeValues(Ops, dl);
5322}
5323
5324/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5325/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5326SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5327 SelectionDAG &DAG) const {
5328 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5328, __PRETTY_FUNCTION__))
;
5329 EVT VT = Op.getValueType();
5330 unsigned VTBits = VT.getSizeInBits();
5331 SDLoc dl(Op);
5332 SDValue ShOpLo = Op.getOperand(0);
5333 SDValue ShOpHi = Op.getOperand(1);
5334 SDValue ShAmt = Op.getOperand(2);
5335 SDValue ARMcc;
5336 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5337
5338 assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void>
(0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5338, __PRETTY_FUNCTION__))
;
5339 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5340 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5341 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5342 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5343 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5344
5345 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5346 DAG.getConstant(VTBits, dl, MVT::i32));
5347 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5348 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5349 ISD::SETGE, ARMcc, DAG, dl);
5350 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5351 ARMcc, CCR, CmpHi);
5352
5353 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5354 ISD::SETGE, ARMcc, DAG, dl);
5355 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5356 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5357 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5358
5359 SDValue Ops[2] = { Lo, Hi };
5360 return DAG.getMergeValues(Ops, dl);
5361}
5362
5363SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5364 SelectionDAG &DAG) const {
5365 // The rounding mode is in bits 23:22 of the FPSCR.
5366 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5367 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5368 // so that the shift + and get folded into a bitfield extract.
5369 SDLoc dl(Op);
5370 SDValue Ops[] = { DAG.getEntryNode(),
5371 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5372
5373 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5374 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5375 DAG.getConstant(1U << 22, dl, MVT::i32));
5376 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5377 DAG.getConstant(22, dl, MVT::i32));
5378 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5379 DAG.getConstant(3, dl, MVT::i32));
5380}
5381
5382static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5383 const ARMSubtarget *ST) {
5384 SDLoc dl(N);
5385 EVT VT = N->getValueType(0);
5386 if (VT.isVector()) {
5387 assert(ST->hasNEON())((ST->hasNEON()) ? static_cast<void> (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5387, __PRETTY_FUNCTION__))
;
5388
5389 // Compute the least significant set bit: LSB = X & -X
5390 SDValue X = N->getOperand(0);
5391 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5392 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5393
5394 EVT ElemTy = VT.getVectorElementType();
5395
5396 if (ElemTy == MVT::i8) {
5397 // Compute with: cttz(x) = ctpop(lsb - 1)
5398 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5399 DAG.getTargetConstant(1, dl, ElemTy));
5400 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5401 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5402 }
5403
5404 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5405 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5406 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5407 unsigned NumBits = ElemTy.getSizeInBits();
5408 SDValue WidthMinus1 =
5409 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5410 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5411 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5412 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5413 }
5414
5415 // Compute with: cttz(x) = ctpop(lsb - 1)
5416
5417 // Compute LSB - 1.
5418 SDValue Bits;
5419 if (ElemTy == MVT::i64) {
5420 // Load constant 0xffff'ffff'ffff'ffff to register.
5421 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5422 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5423 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5424 } else {
5425 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5426 DAG.getTargetConstant(1, dl, ElemTy));
5427 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5428 }
5429 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5430 }
5431
5432 if (!ST->hasV6T2Ops())
5433 return SDValue();
5434
5435 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5436 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5437}
5438
5439static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5440 const ARMSubtarget *ST) {
5441 EVT VT = N->getValueType(0);
5442 SDLoc DL(N);
5443
5444 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")((ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? static_cast<void> (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5444, __PRETTY_FUNCTION__))
;
5445 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5447, __PRETTY_FUNCTION__))
5446 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5447, __PRETTY_FUNCTION__))
5447 "Unexpected type for custom ctpop lowering")(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5447, __PRETTY_FUNCTION__))
;
5448
5449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5450 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5451 SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0));
5452 Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res);
5453
5454 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
5455 unsigned EltSize = 8;
5456 unsigned NumElts = VT.is64BitVector() ? 8 : 16;
5457 while (EltSize != VT.getScalarSizeInBits()) {
5458 SmallVector<SDValue, 8> Ops;
5459 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddlu, DL,
5460 TLI.getPointerTy(DAG.getDataLayout())));
5461 Ops.push_back(Res);
5462
5463 EltSize *= 2;
5464 NumElts /= 2;
5465 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts);
5466 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops);
5467 }
5468
5469 return Res;
5470}
5471
5472static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5473 const ARMSubtarget *ST) {
5474 EVT VT = N->getValueType(0);
5475 SDLoc dl(N);
5476
5477 if (!VT.isVector())
5478 return SDValue();
5479
5480 // Lower vector shifts on NEON to use VSHL.
5481 assert(ST->hasNEON() && "unexpected vector shift")((ST->hasNEON() && "unexpected vector shift") ? static_cast
<void> (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5481, __PRETTY_FUNCTION__))
;
5482
5483 // Left shifts translate directly to the vshiftu intrinsic.
5484 if (N->getOpcode() == ISD::SHL)
5485 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5486 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5487 MVT::i32),
5488 N->getOperand(0), N->getOperand(1));
5489
5490 assert((N->getOpcode() == ISD::SRA ||(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "unexpected vector shift opcode") ? static_cast
<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5491, __PRETTY_FUNCTION__))
5491 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::
SRL) && "unexpected vector shift opcode") ? static_cast
<void> (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5491, __PRETTY_FUNCTION__))
;
5492
5493 // NEON uses the same intrinsics for both left and right shifts. For
5494 // right shifts, the shift amounts are negative, so negate the vector of
5495 // shift amounts.
5496 EVT ShiftVT = N->getOperand(1).getValueType();
5497 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5498 getZeroVector(ShiftVT, DAG, dl),
5499 N->getOperand(1));
5500 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5501 Intrinsic::arm_neon_vshifts :
5502 Intrinsic::arm_neon_vshiftu);
5503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5504 DAG.getConstant(vshiftInt, dl, MVT::i32),
5505 N->getOperand(0), NegatedCount);
5506}
5507
5508static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5509 const ARMSubtarget *ST) {
5510 EVT VT = N->getValueType(0);
5511 SDLoc dl(N);
5512
5513 // We can get here for a node like i32 = ISD::SHL i32, i64
5514 if (VT != MVT::i64)
5515 return SDValue();
5516
5517 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::
SRA) && "Unknown shift to lower!") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5518, __PRETTY_FUNCTION__))
5518 "Unknown shift to lower!")(((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::
SRA) && "Unknown shift to lower!") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5518, __PRETTY_FUNCTION__))
;
5519
5520 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5521 if (!isOneConstant(N->getOperand(1)))
5522 return SDValue();
5523
5524 // If we are in thumb mode, we don't have RRX.
5525 if (ST->isThumb1Only()) return SDValue();
5526
5527 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5528 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5529 DAG.getConstant(0, dl, MVT::i32));
5530 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5531 DAG.getConstant(1, dl, MVT::i32));
5532
5533 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5534 // captures the result into a carry flag.
5535 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5536 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5537
5538 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5539 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5540
5541 // Merge the pieces into a single i64 value.
5542 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5543}
5544
5545static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5546 SDValue TmpOp0, TmpOp1;
5547 bool Invert = false;
5548 bool Swap = false;
5549 unsigned Opc = 0;
5550
5551 SDValue Op0 = Op.getOperand(0);
5552 SDValue Op1 = Op.getOperand(1);
5553 SDValue CC = Op.getOperand(2);
5554 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5555 EVT VT = Op.getValueType();
5556 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5557 SDLoc dl(Op);
5558
5559 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5560 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5561 // Special-case integer 64-bit equality comparisons. They aren't legal,
5562 // but they can be lowered with a few vector instructions.
5563 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5564 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5565 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5566 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5567 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5568 DAG.getCondCode(ISD::SETEQ));
5569 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5570 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5571 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5572 if (SetCCOpcode == ISD::SETNE)
5573 Merged = DAG.getNOT(dl, Merged, CmpVT);
5574 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5575 return Merged;
5576 }
5577
5578 if (CmpVT.getVectorElementType() == MVT::i64)
5579 // 64-bit comparisons are not legal in general.
5580 return SDValue();
5581
5582 if (Op1.getValueType().isFloatingPoint()) {
5583 switch (SetCCOpcode) {
5584 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5584)
;
5585 case ISD::SETUNE:
5586 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5587 case ISD::SETOEQ:
5588 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5589 case ISD::SETOLT:
5590 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5591 case ISD::SETOGT:
5592 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5593 case ISD::SETOLE:
5594 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5595 case ISD::SETOGE:
5596 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5597 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5598 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5599 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5600 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5601 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5602 case ISD::SETONE:
5603 // Expand this to (OLT | OGT).
5604 TmpOp0 = Op0;
5605 TmpOp1 = Op1;
5606 Opc = ISD::OR;
5607 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5608 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5609 break;
5610 case ISD::SETUO:
5611 Invert = true;
5612 LLVM_FALLTHROUGH[[clang::fallthrough]];
5613 case ISD::SETO:
5614 // Expand this to (OLT | OGE).
5615 TmpOp0 = Op0;
5616 TmpOp1 = Op1;
5617 Opc = ISD::OR;
5618 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5619 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5620 break;
5621 }
5622 } else {
5623 // Integer comparisons.
5624 switch (SetCCOpcode) {
5625 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5625)
;
5626 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5627 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5628 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5629 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5630 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5631 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5632 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5633 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5634 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5635 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5636 }
5637
5638 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5639 if (Opc == ARMISD::VCEQ) {
5640 SDValue AndOp;
5641 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5642 AndOp = Op0;
5643 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5644 AndOp = Op1;
5645
5646 // Ignore bitconvert.
5647 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5648 AndOp = AndOp.getOperand(0);
5649
5650 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5651 Opc = ARMISD::VTST;
5652 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5653 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5654 Invert = !Invert;
5655 }
5656 }
5657 }
5658
5659 if (Swap)
5660 std::swap(Op0, Op1);
5661
5662 // If one of the operands is a constant vector zero, attempt to fold the
5663 // comparison to a specialized compare-against-zero form.
5664 SDValue SingleOp;
5665 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5666 SingleOp = Op0;
5667 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5668 if (Opc == ARMISD::VCGE)
5669 Opc = ARMISD::VCLEZ;
5670 else if (Opc == ARMISD::VCGT)
5671 Opc = ARMISD::VCLTZ;
5672 SingleOp = Op1;
5673 }
5674
5675 SDValue Result;
5676 if (SingleOp.getNode()) {
5677 switch (Opc) {
5678 case ARMISD::VCEQ:
5679 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5680 case ARMISD::VCGE:
5681 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5682 case ARMISD::VCLEZ:
5683 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5684 case ARMISD::VCGT:
5685 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5686 case ARMISD::VCLTZ:
5687 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5688 default:
5689 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5690 }
5691 } else {
5692 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5693 }
5694
5695 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5696
5697 if (Invert)
5698 Result = DAG.getNOT(dl, Result, VT);
5699
5700 return Result;
5701}
5702
5703static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
5704 SDValue LHS = Op.getOperand(0);
5705 SDValue RHS = Op.getOperand(1);
5706 SDValue Carry = Op.getOperand(2);
5707 SDValue Cond = Op.getOperand(3);
5708 SDLoc DL(Op);
5709
5710 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.")((LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only."
) ? static_cast<void> (0) : __assert_fail ("LHS.getSimpleValueType().isInteger() && \"SETCCCARRY is integer only.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5710, __PRETTY_FUNCTION__))
;
5711
5712 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
5713 // have to invert the carry first.
5714 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
5715 DAG.getConstant(1, DL, MVT::i32), Carry);
5716 // This converts the boolean value carry into the carry flag.
5717 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
5718
5719 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5720 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5721
5722 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5723 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5724 SDValue ARMcc = DAG.getConstant(
5725 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5727 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5728 Cmp.getValue(1), SDValue());
5729 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5730 CCR, Chain.getValue(1));
5731}
5732
5733/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5734/// valid vector constant for a NEON instruction with a "modified immediate"
5735/// operand (e.g., VMOV). If so, return the encoded value.
5736static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5737 unsigned SplatBitSize, SelectionDAG &DAG,
5738 const SDLoc &dl, EVT &VT, bool is128Bits,
5739 NEONModImmType type) {
5740 unsigned OpCmode, Imm;
5741
5742 // SplatBitSize is set to the smallest size that splats the vector, so a
5743 // zero vector will always have SplatBitSize == 8. However, NEON modified
5744 // immediate instructions others than VMOV do not support the 8-bit encoding
5745 // of a zero vector, and the default encoding of zero is supposed to be the
5746 // 32-bit version.
5747 if (SplatBits == 0)
5748 SplatBitSize = 32;
5749
5750 switch (SplatBitSize) {
5751 case 8:
5752 if (type != VMOVModImm)
5753 return SDValue();
5754 // Any 1-byte value is OK. Op=0, Cmode=1110.
5755 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(((SplatBits & ~0xff) == 0 && "one byte splat value is too big"
) ? static_cast<void> (0) : __assert_fail ("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5755, __PRETTY_FUNCTION__))
;
5756 OpCmode = 0xe;
5757 Imm = SplatBits;
5758 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5759 break;
5760
5761 case 16:
5762 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5763 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5764 if ((SplatBits & ~0xff) == 0) {
5765 // Value = 0x00nn: Op=x, Cmode=100x.
5766 OpCmode = 0x8;
5767 Imm = SplatBits;
5768 break;
5769 }
5770 if ((SplatBits & ~0xff00) == 0) {
5771 // Value = 0xnn00: Op=x, Cmode=101x.
5772 OpCmode = 0xa;
5773 Imm = SplatBits >> 8;
5774 break;
5775 }
5776 return SDValue();
5777
5778 case 32:
5779 // NEON's 32-bit VMOV supports splat values where:
5780 // * only one byte is nonzero, or
5781 // * the least significant byte is 0xff and the second byte is nonzero, or
5782 // * the least significant 2 bytes are 0xff and the third is nonzero.
5783 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5784 if ((SplatBits & ~0xff) == 0) {
5785 // Value = 0x000000nn: Op=x, Cmode=000x.
5786 OpCmode = 0;
5787 Imm = SplatBits;
5788 break;
5789 }
5790 if ((SplatBits & ~0xff00) == 0) {
5791 // Value = 0x0000nn00: Op=x, Cmode=001x.
5792 OpCmode = 0x2;
5793 Imm = SplatBits >> 8;
5794 break;
5795 }
5796 if ((SplatBits & ~0xff0000) == 0) {
5797 // Value = 0x00nn0000: Op=x, Cmode=010x.
5798 OpCmode = 0x4;
5799 Imm = SplatBits >> 16;
5800 break;
5801 }
5802 if ((SplatBits & ~0xff000000) == 0) {
5803 // Value = 0xnn000000: Op=x, Cmode=011x.
5804 OpCmode = 0x6;
5805 Imm = SplatBits >> 24;
5806 break;
5807 }
5808
5809 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5810 if (type == OtherModImm) return SDValue();
5811
5812 if ((SplatBits & ~0xffff) == 0 &&
5813 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5814 // Value = 0x0000nnff: Op=x, Cmode=1100.
5815 OpCmode = 0xc;
5816 Imm = SplatBits >> 8;
5817 break;
5818 }
5819
5820 if ((SplatBits & ~0xffffff) == 0 &&
5821 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5822 // Value = 0x00nnffff: Op=x, Cmode=1101.
5823 OpCmode = 0xd;
5824 Imm = SplatBits >> 16;
5825 break;
5826 }
5827
5828 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5829 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5830 // VMOV.I32. A (very) minor optimization would be to replicate the value
5831 // and fall through here to test for a valid 64-bit splat. But, then the
5832 // caller would also need to check and handle the change in size.
5833 return SDValue();
5834
5835 case 64: {
5836 if (type != VMOVModImm)
5837 return SDValue();
5838 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5839 uint64_t BitMask = 0xff;
5840 uint64_t Val = 0;
5841 unsigned ImmMask = 1;
5842 Imm = 0;
5843 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5844 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5845 Val |= BitMask;
5846 Imm |= ImmMask;
5847 } else if ((SplatBits & BitMask) != 0) {
5848 return SDValue();
5849 }
5850 BitMask <<= 8;
5851 ImmMask <<= 1;
5852 }
5853
5854 if (DAG.getDataLayout().isBigEndian())
5855 // swap higher and lower 32 bit word
5856 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5857
5858 // Op=1, Cmode=1110.
5859 OpCmode = 0x1e;
5860 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5861 break;
5862 }
5863
5864 default:
5865 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5865)
;
5866 }
5867
5868 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5869 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5870}
5871
5872SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5873 const ARMSubtarget *ST) const {
5874 EVT VT = Op.getValueType();
5875 bool IsDouble = (VT == MVT::f64);
5876 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5877 const APFloat &FPVal = CFP->getValueAPF();
5878
5879 // Prevent floating-point constants from using literal loads
5880 // when execute-only is enabled.
5881 if (ST->genExecuteOnly()) {
5882 // If we can represent the constant as an immediate, don't lower it
5883 if (isFPImmLegal(FPVal, VT))
5884 return Op;
5885 // Otherwise, construct as integer, and move to float register
5886 APInt INTVal = FPVal.bitcastToAPInt();
5887 SDLoc DL(CFP);
5888 switch (VT.getSimpleVT().SimpleTy) {
5889 default:
5890 llvm_unreachable("Unknown floating point type!")::llvm::llvm_unreachable_internal("Unknown floating point type!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/ARM/ARMISelLowering.cpp"
, 5890)
;
5891 break;
5892 case MVT::f64: {
5893 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
5894 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
5895 if (!ST->isLittle())
5896 std::swap(Lo, Hi);
5897 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
5898 }
5899 case MVT::f32:
5900 return DAG.getNode(ARMISD::VMOVSR, DL, VT,
5901 DAG.getConstant(INTVal, DL, MVT::i32));
5902 }
5903 }
5904
5905 if (!ST->hasVFP3())
5906 return SDValue();
5907
5908 // Use the default (constant pool) lowering for double constants when we have
5909 // an SP-only FPU
5910 if (IsDouble && Subtarget->isFPOnlySP())
5911 return SDValue();
5912
5913 // Try splatting with a VMOV.f32...
5914 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
5915
5916 if (ImmVal != -1) {
5917 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
5918 // We have code in place to select a valid ConstantFP already, no need to
5919 // do any mangling.
5920 return Op;
5921 }
5922
5923 // It's a float and we are trying to use NEON operations where
5924 // possible. Lower it to a splat followed by an extract.
5925 SDLoc DL(Op);
5926 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
5927 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5928 NewVal);
5929 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
5930 DAG.getConstant(0, DL, MVT::i32));
5931 }
5932
5933 // The rest of our options are NEON only, make sure that's allowed before
5934 // proceeding..
5935 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
5936 return SDValue();
5937
5938 EVT VMovVT;
5939 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
5940
5941 // It wouldn't really be worth bothering for doubles except for one very
5942 // important value, which does happen to match: 0.0. So make sure we don't do
5943 // anything stupid.
5944 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
5945 return SDValue();
5946
5947 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
5948 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5949 VMovVT, false, VMOVModImm);
5950 if (NewVal != SDValue()) {
5951 SDLoc DL(Op);
5952 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5953 NewVal);
5954 if (IsDouble)
5955 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5956
5957 // It's a float: cast and extract a vector element.
5958 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5959 VecConstant);
5960 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5961 DAG.getConstant(0, DL, MVT::i32));
5962 }
5963
5964 // Finally, try a VMVN.i32
5965 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5966 false, VMVNModImm);
5967 if (NewVal != SDValue()) {
5968 SDLoc DL(Op);
5969 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5970
5971 if (IsDouble)
5972 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5973
5974 // It's a float: cast and extract a vector element.
5975 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5976 VecConstant);
5977 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,