Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 6782, column 18
Division by zero

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/IntrinsicsARM.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/PatternMatch.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MachineValueType.h"
101#include "llvm/Support/MathExtras.h"
102#include "llvm/Support/raw_ostream.h"
103#include "llvm/Target/TargetMachine.h"
104#include "llvm/Target/TargetOptions.h"
105#include <algorithm>
106#include <cassert>
107#include <cstdint>
108#include <cstdlib>
109#include <iterator>
110#include <limits>
111#include <string>
112#include <tuple>
113#include <utility>
114#include <vector>
115
116using namespace llvm;
117using namespace llvm::PatternMatch;
118
119#define DEBUG_TYPE"arm-isel" "arm-isel"
120
121STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
122STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
123STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
124STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
125 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
126
127static cl::opt<bool>
128ARMInterworking("arm-interworking", cl::Hidden,
129 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 cl::init(true));
131
132static cl::opt<bool> EnableConstpoolPromotion(
133 "arm-promote-constant", cl::Hidden,
134 cl::desc("Enable / disable promotion of unnamed_addr constants into "
135 "constant pools"),
136 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
137static cl::opt<unsigned> ConstpoolPromotionMaxSize(
138 "arm-promote-constant-max-size", cl::Hidden,
139 cl::desc("Maximum size of constant to promote into a constant pool"),
140 cl::init(64));
141static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
142 "arm-promote-constant-max-total", cl::Hidden,
143 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 cl::init(128));
145
146static cl::opt<unsigned>
147MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
148 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
149 cl::init(2));
150
151// The APCS parameter registers.
152static const MCPhysReg GPRArgRegs[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154};
155
156void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
157 MVT PromotedBitwiseVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Promote all bit-wise operations.
197 if (VT.isInteger() && VT != PromotedBitwiseVT) {
198 setOperationAction(ISD::AND, VT, Promote);
199 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
200 setOperationAction(ISD::OR, VT, Promote);
201 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
202 setOperationAction(ISD::XOR, VT, Promote);
203 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
204 }
205
206 // Neon does not support vector divide/remainder operations.
207 setOperationAction(ISD::SDIV, VT, Expand);
208 setOperationAction(ISD::UDIV, VT, Expand);
209 setOperationAction(ISD::FDIV, VT, Expand);
210 setOperationAction(ISD::SREM, VT, Expand);
211 setOperationAction(ISD::UREM, VT, Expand);
212 setOperationAction(ISD::FREM, VT, Expand);
213
214 if (!VT.isFloatingPoint() &&
215 VT != MVT::v2i64 && VT != MVT::v1i64)
216 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
217 setOperationAction(Opcode, VT, Legal);
218 if (!VT.isFloatingPoint())
219 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
220 setOperationAction(Opcode, VT, Legal);
221}
222
223void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
224 addRegisterClass(VT, &ARM::DPRRegClass);
225 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
226}
227
228void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
229 addRegisterClass(VT, &ARM::DPairRegClass);
230 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
231}
232
233void ARMTargetLowering::setAllExpand(MVT VT) {
234 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
235 setOperationAction(Opc, VT, Expand);
236
237 // We support these really simple operations even on types where all
238 // the actual arithmetic has to be broken down into simpler
239 // operations or turned into library calls.
240 setOperationAction(ISD::BITCAST, VT, Legal);
241 setOperationAction(ISD::LOAD, VT, Legal);
242 setOperationAction(ISD::STORE, VT, Legal);
243 setOperationAction(ISD::UNDEF, VT, Legal);
244}
245
246void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
247 LegalizeAction Action) {
248 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
249 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
250 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
251}
252
253void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
254 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
255
256 for (auto VT : IntTypes) {
257 addRegisterClass(VT, &ARM::MQPRRegClass);
258 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
259 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
260 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
261 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
262 setOperationAction(ISD::SHL, VT, Custom);
263 setOperationAction(ISD::SRA, VT, Custom);
264 setOperationAction(ISD::SRL, VT, Custom);
265 setOperationAction(ISD::SMIN, VT, Legal);
266 setOperationAction(ISD::SMAX, VT, Legal);
267 setOperationAction(ISD::UMIN, VT, Legal);
268 setOperationAction(ISD::UMAX, VT, Legal);
269 setOperationAction(ISD::ABS, VT, Legal);
270 setOperationAction(ISD::SETCC, VT, Custom);
271 setOperationAction(ISD::MLOAD, VT, Custom);
272 setOperationAction(ISD::MSTORE, VT, Legal);
273 setOperationAction(ISD::CTLZ, VT, Legal);
274 setOperationAction(ISD::CTTZ, VT, Custom);
275 setOperationAction(ISD::BITREVERSE, VT, Legal);
276 setOperationAction(ISD::BSWAP, VT, Legal);
277 setOperationAction(ISD::SADDSAT, VT, Legal);
278 setOperationAction(ISD::UADDSAT, VT, Legal);
279 setOperationAction(ISD::SSUBSAT, VT, Legal);
280 setOperationAction(ISD::USUBSAT, VT, Legal);
281
282 // No native support for these.
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SDIV, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
286 setOperationAction(ISD::SREM, VT, Expand);
287 setOperationAction(ISD::CTPOP, VT, Expand);
288
289 // Vector reductions
290 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
291 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
292 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
295
296 if (!HasMVEFP) {
297 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
298 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
301 }
302
303 // Pre and Post inc are supported on loads and stores
304 for (unsigned im = (unsigned)ISD::PRE_INC;
305 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
306 setIndexedLoadAction(im, VT, Legal);
307 setIndexedStoreAction(im, VT, Legal);
308 setIndexedMaskedLoadAction(im, VT, Legal);
309 setIndexedMaskedStoreAction(im, VT, Legal);
310 }
311 }
312
313 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
314 for (auto VT : FloatTypes) {
315 addRegisterClass(VT, &ARM::MQPRRegClass);
316 if (!HasMVEFP)
317 setAllExpand(VT);
318
319 // These are legal or custom whether we have MVE.fp or not
320 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
324 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
325 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
326 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
327 setOperationAction(ISD::SETCC, VT, Custom);
328 setOperationAction(ISD::MLOAD, VT, Custom);
329 setOperationAction(ISD::MSTORE, VT, Legal);
330
331 // Pre and Post inc are supported on loads and stores
332 for (unsigned im = (unsigned)ISD::PRE_INC;
333 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
334 setIndexedLoadAction(im, VT, Legal);
335 setIndexedStoreAction(im, VT, Legal);
336 setIndexedMaskedLoadAction(im, VT, Legal);
337 setIndexedMaskedStoreAction(im, VT, Legal);
338 }
339
340 if (HasMVEFP) {
341 setOperationAction(ISD::FMINNUM, VT, Legal);
342 setOperationAction(ISD::FMAXNUM, VT, Legal);
343 setOperationAction(ISD::FROUND, VT, Legal);
344
345 // No native support for these.
346 setOperationAction(ISD::FDIV, VT, Expand);
347 setOperationAction(ISD::FREM, VT, Expand);
348 setOperationAction(ISD::FSQRT, VT, Expand);
349 setOperationAction(ISD::FSIN, VT, Expand);
350 setOperationAction(ISD::FCOS, VT, Expand);
351 setOperationAction(ISD::FPOW, VT, Expand);
352 setOperationAction(ISD::FLOG, VT, Expand);
353 setOperationAction(ISD::FLOG2, VT, Expand);
354 setOperationAction(ISD::FLOG10, VT, Expand);
355 setOperationAction(ISD::FEXP, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FNEARBYINT, VT, Expand);
358 }
359 }
360
361 // We 'support' these types up to bitcast/load/store level, regardless of
362 // MVE integer-only / float support. Only doing FP data processing on the FP
363 // vector types is inhibited at integer-only level.
364 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
365 for (auto VT : LongTypes) {
366 addRegisterClass(VT, &ARM::MQPRRegClass);
367 setAllExpand(VT);
368 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
369 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
370 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
371 }
372 // We can do bitwise operations on v2i64 vectors
373 setOperationAction(ISD::AND, MVT::v2i64, Legal);
374 setOperationAction(ISD::OR, MVT::v2i64, Legal);
375 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
376
377 // It is legal to extload from v4i8 to v4i16 or v4i32.
378 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
379 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
380 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
381
382 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
383 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
386 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
388
389 // Some truncating stores are legal too.
390 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
392 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
393
394 // Pre and Post inc on these are legal, given the correct extends
395 for (unsigned im = (unsigned)ISD::PRE_INC;
396 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
397 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
398 setIndexedLoadAction(im, VT, Legal);
399 setIndexedStoreAction(im, VT, Legal);
400 setIndexedMaskedLoadAction(im, VT, Legal);
401 setIndexedMaskedStoreAction(im, VT, Legal);
402 }
403 }
404
405 // Predicate types
406 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
407 for (auto VT : pTypes) {
408 addRegisterClass(VT, &ARM::VCCRRegClass);
409 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
410 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
411 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
412 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
413 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
415 setOperationAction(ISD::SETCC, VT, Custom);
416 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
417 setOperationAction(ISD::LOAD, VT, Custom);
418 setOperationAction(ISD::STORE, VT, Custom);
419 }
420}
421
422ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
423 const ARMSubtarget &STI)
424 : TargetLowering(TM), Subtarget(&STI) {
425 RegInfo = Subtarget->getRegisterInfo();
426 Itins = Subtarget->getInstrItineraryData();
427
428 setBooleanContents(ZeroOrOneBooleanContent);
429 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
430
431 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
432 !Subtarget->isTargetWatchOS()) {
433 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
434 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
435 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
436 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
437 : CallingConv::ARM_AAPCS);
438 }
439
440 if (Subtarget->isTargetMachO()) {
441 // Uses VFP for Thumb libfuncs if available.
442 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
443 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const ISD::CondCode Cond;
448 } LibraryCalls[] = {
449 // Single-precision floating-point arithmetic.
450 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
451 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
452 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
453 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
454
455 // Double-precision floating-point arithmetic.
456 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
457 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
458 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
459 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
460
461 // Single-precision comparisons.
462 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
463 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
464 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
465 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
466 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
467 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
468 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
469
470 // Double-precision comparisons.
471 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
472 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
473 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
474 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
475 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
476 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
477 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
478
479 // Floating-point to integer conversions.
480 // i64 conversions are done via library routines even when generating VFP
481 // instructions, so use the same ones.
482 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
483 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
484 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
485 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
486
487 // Conversions between floating types.
488 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
489 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
490
491 // Integer to floating-point conversions.
492 // i64 conversions are done via library routines even when generating VFP
493 // instructions, so use the same ones.
494 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
495 // e.g., __floatunsidf vs. __floatunssidfvfp.
496 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
497 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
498 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
499 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
500 };
501
502 for (const auto &LC : LibraryCalls) {
503 setLibcallName(LC.Op, LC.Name);
504 if (LC.Cond != ISD::SETCC_INVALID)
505 setCmpLibcallCC(LC.Op, LC.Cond);
506 }
507 }
508 }
509
510 // These libcalls are not available in 32-bit.
511 setLibcallName(RTLIB::SHL_I128, nullptr);
512 setLibcallName(RTLIB::SRL_I128, nullptr);
513 setLibcallName(RTLIB::SRA_I128, nullptr);
514
515 // RTLIB
516 if (Subtarget->isAAPCS_ABI() &&
517 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
518 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
519 static const struct {
520 const RTLIB::Libcall Op;
521 const char * const Name;
522 const CallingConv::ID CC;
523 const ISD::CondCode Cond;
524 } LibraryCalls[] = {
525 // Double-precision floating-point arithmetic helper functions
526 // RTABI chapter 4.1.2, Table 2
527 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
528 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
529 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
530 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
531
532 // Double-precision floating-point comparison helper functions
533 // RTABI chapter 4.1.2, Table 3
534 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
535 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
536 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
537 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
538 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
539 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
540 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
541
542 // Single-precision floating-point arithmetic helper functions
543 // RTABI chapter 4.1.2, Table 4
544 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
545 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
546 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
547 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
548
549 // Single-precision floating-point comparison helper functions
550 // RTABI chapter 4.1.2, Table 5
551 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
552 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
553 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
554 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
555 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
556 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
557 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
558
559 // Floating-point to integer conversions.
560 // RTABI chapter 4.1.2, Table 6
561 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
562 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
563 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
565 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
566 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
567 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
568 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
569
570 // Conversions between floating types.
571 // RTABI chapter 4.1.2, Table 7
572 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
573 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
574 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
575
576 // Integer to floating-point conversions.
577 // RTABI chapter 4.1.2, Table 8
578 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
579 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
580 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
582 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
583 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
584 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
585 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
586
587 // Long long helper functions
588 // RTABI chapter 4.2, Table 9
589 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
590 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593
594 // Integer division functions
595 // RTABI chapter 4.3.1
596 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
600 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
601 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 };
605
606 for (const auto &LC : LibraryCalls) {
607 setLibcallName(LC.Op, LC.Name);
608 setLibcallCallingConv(LC.Op, LC.CC);
609 if (LC.Cond != ISD::SETCC_INVALID)
610 setCmpLibcallCC(LC.Op, LC.Cond);
611 }
612
613 // EABI dependent RTLIB
614 if (TM.Options.EABIVersion == EABI::EABI4 ||
615 TM.Options.EABIVersion == EABI::EABI5) {
616 static const struct {
617 const RTLIB::Libcall Op;
618 const char *const Name;
619 const CallingConv::ID CC;
620 const ISD::CondCode Cond;
621 } MemOpsLibraryCalls[] = {
622 // Memory operations
623 // RTABI chapter 4.3.4
624 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 };
628
629 for (const auto &LC : MemOpsLibraryCalls) {
630 setLibcallName(LC.Op, LC.Name);
631 setLibcallCallingConv(LC.Op, LC.CC);
632 if (LC.Cond != ISD::SETCC_INVALID)
633 setCmpLibcallCC(LC.Op, LC.Cond);
634 }
635 }
636 }
637
638 if (Subtarget->isTargetWindows()) {
639 static const struct {
640 const RTLIB::Libcall Op;
641 const char * const Name;
642 const CallingConv::ID CC;
643 } LibraryCalls[] = {
644 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
645 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
646 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
647 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
648 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
649 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
650 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
651 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
652 };
653
654 for (const auto &LC : LibraryCalls) {
655 setLibcallName(LC.Op, LC.Name);
656 setLibcallCallingConv(LC.Op, LC.CC);
657 }
658 }
659
660 // Use divmod compiler-rt calls for iOS 5.0 and later.
661 if (Subtarget->isTargetMachO() &&
662 !(Subtarget->isTargetIOS() &&
663 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
664 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
665 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
666 }
667
668 // The half <-> float conversion functions are always soft-float on
669 // non-watchos platforms, but are needed for some targets which use a
670 // hard-float calling convention by default.
671 if (!Subtarget->isTargetWatchABI()) {
672 if (Subtarget->isAAPCS_ABI()) {
673 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
674 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
675 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
676 } else {
677 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
678 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
679 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
680 }
681 }
682
683 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
684 // a __gnu_ prefix (which is the default).
685 if (Subtarget->isTargetAEABI()) {
686 static const struct {
687 const RTLIB::Libcall Op;
688 const char * const Name;
689 const CallingConv::ID CC;
690 } LibraryCalls[] = {
691 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
692 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
693 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
694 };
695
696 for (const auto &LC : LibraryCalls) {
697 setLibcallName(LC.Op, LC.Name);
698 setLibcallCallingConv(LC.Op, LC.CC);
699 }
700 }
701
702 if (Subtarget->isThumb1Only())
703 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
704 else
705 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
706
707 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
708 Subtarget->hasFPRegs()) {
709 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
710 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
711 if (!Subtarget->hasVFP2Base())
712 setAllExpand(MVT::f32);
713 if (!Subtarget->hasFP64())
714 setAllExpand(MVT::f64);
715 }
716
717 if (Subtarget->hasFullFP16()) {
718 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
719 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
720 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
721
722 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
723 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
724 }
725
726 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
727 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
728 setTruncStoreAction(VT, InnerVT, Expand);
729 addAllExtLoads(VT, InnerVT, Expand);
730 }
731
732 setOperationAction(ISD::MULHS, VT, Expand);
733 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
734 setOperationAction(ISD::MULHU, VT, Expand);
735 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
736
737 setOperationAction(ISD::BSWAP, VT, Expand);
738 }
739
740 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
741 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
742
743 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
744 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
745
746 if (Subtarget->hasMVEIntegerOps())
747 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
748
749 // Combine low-overhead loop intrinsics so that we can lower i1 types.
750 if (Subtarget->hasLOB()) {
751 setTargetDAGCombine(ISD::BRCOND);
752 setTargetDAGCombine(ISD::BR_CC);
753 }
754
755 if (Subtarget->hasNEON()) {
756 addDRTypeForNEON(MVT::v2f32);
757 addDRTypeForNEON(MVT::v8i8);
758 addDRTypeForNEON(MVT::v4i16);
759 addDRTypeForNEON(MVT::v2i32);
760 addDRTypeForNEON(MVT::v1i64);
761
762 addQRTypeForNEON(MVT::v4f32);
763 addQRTypeForNEON(MVT::v2f64);
764 addQRTypeForNEON(MVT::v16i8);
765 addQRTypeForNEON(MVT::v8i16);
766 addQRTypeForNEON(MVT::v4i32);
767 addQRTypeForNEON(MVT::v2i64);
768
769 if (Subtarget->hasFullFP16()) {
770 addQRTypeForNEON(MVT::v8f16);
771 addDRTypeForNEON(MVT::v4f16);
772 }
773 }
774
775 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
776 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
777 // none of Neon, MVE or VFP supports any arithmetic operations on it.
778 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
779 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
780 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
781 // FIXME: Code duplication: FDIV and FREM are expanded always, see
782 // ARMTargetLowering::addTypeForNEON method for details.
783 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
784 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
785 // FIXME: Create unittest.
786 // In another words, find a way when "copysign" appears in DAG with vector
787 // operands.
788 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
789 // FIXME: Code duplication: SETCC has custom operation action, see
790 // ARMTargetLowering::addTypeForNEON method for details.
791 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
792 // FIXME: Create unittest for FNEG and for FABS.
793 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
794 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
795 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
796 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
797 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
798 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
799 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
800 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
801 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
802 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
803 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
804 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
805 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
806 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
807 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
808 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
809 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
810 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
811 }
812
813 if (Subtarget->hasNEON()) {
814 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
815 // supported for v4f32.
816 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
817 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
818 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
819 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
820 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
821 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
822 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
823 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
824 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
825 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
826 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
827 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
828 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
829 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
830
831 // Mark v2f32 intrinsics.
832 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
833 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
834 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
835 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
836 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
837 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
838 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
839 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
840 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
841 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
842 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
843 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
844 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
845 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
846
847 // Neon does not support some operations on v1i64 and v2i64 types.
848 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
849 // Custom handling for some quad-vector types to detect VMULL.
850 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
851 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
852 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
853 // Custom handling for some vector types to avoid expensive expansions
854 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
855 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
856 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
857 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
858 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
859 // a destination type that is wider than the source, and nor does
860 // it have a FP_TO_[SU]INT instruction with a narrower destination than
861 // source.
862 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
863 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
864 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
865 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
866 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
867 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
868 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
869 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
870
871 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
872 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
873
874 // NEON does not have single instruction CTPOP for vectors with element
875 // types wider than 8-bits. However, custom lowering can leverage the
876 // v8i8/v16i8 vcnt instruction.
877 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
878 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
879 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
880 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
881 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
882 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
883
884 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
885 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
886
887 // NEON does not have single instruction CTTZ for vectors.
888 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
889 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
890 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
891 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
892
893 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
894 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
895 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
896 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
897
898 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
899 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
900 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
901 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
902
903 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
904 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
905 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
906 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
907
908 // NEON only has FMA instructions as of VFP4.
909 if (!Subtarget->hasVFP4Base()) {
910 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
911 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
912 }
913
914 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
915 setTargetDAGCombine(ISD::SHL);
916 setTargetDAGCombine(ISD::SRL);
917 setTargetDAGCombine(ISD::SRA);
918 setTargetDAGCombine(ISD::FP_TO_SINT);
919 setTargetDAGCombine(ISD::FP_TO_UINT);
920 setTargetDAGCombine(ISD::FDIV);
921 setTargetDAGCombine(ISD::LOAD);
922
923 // It is legal to extload from v4i8 to v4i16 or v4i32.
924 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
925 MVT::v2i32}) {
926 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
927 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
928 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
929 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
930 }
931 }
932 }
933
934 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
935 setTargetDAGCombine(ISD::BUILD_VECTOR);
936 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
937 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
938 setTargetDAGCombine(ISD::STORE);
939 setTargetDAGCombine(ISD::SIGN_EXTEND);
940 setTargetDAGCombine(ISD::ZERO_EXTEND);
941 setTargetDAGCombine(ISD::ANY_EXTEND);
942 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
943 setTargetDAGCombine(ISD::INTRINSIC_VOID);
944 setTargetDAGCombine(ISD::VECREDUCE_ADD);
945 setTargetDAGCombine(ISD::ADD);
946 }
947
948 if (!Subtarget->hasFP64()) {
949 // When targeting a floating-point unit with only single-precision
950 // operations, f64 is legal for the few double-precision instructions which
951 // are present However, no double-precision operations other than moves,
952 // loads and stores are provided by the hardware.
953 setOperationAction(ISD::FADD, MVT::f64, Expand);
954 setOperationAction(ISD::FSUB, MVT::f64, Expand);
955 setOperationAction(ISD::FMUL, MVT::f64, Expand);
956 setOperationAction(ISD::FMA, MVT::f64, Expand);
957 setOperationAction(ISD::FDIV, MVT::f64, Expand);
958 setOperationAction(ISD::FREM, MVT::f64, Expand);
959 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
960 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
961 setOperationAction(ISD::FNEG, MVT::f64, Expand);
962 setOperationAction(ISD::FABS, MVT::f64, Expand);
963 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
964 setOperationAction(ISD::FSIN, MVT::f64, Expand);
965 setOperationAction(ISD::FCOS, MVT::f64, Expand);
966 setOperationAction(ISD::FPOW, MVT::f64, Expand);
967 setOperationAction(ISD::FLOG, MVT::f64, Expand);
968 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
969 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
970 setOperationAction(ISD::FEXP, MVT::f64, Expand);
971 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
972 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
973 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
974 setOperationAction(ISD::FRINT, MVT::f64, Expand);
975 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
976 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
977 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
978 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
979 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
980 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
981 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
982 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
983 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
984 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
985 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
986 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
987 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
988 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
989 }
990
991 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
992 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
993 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
994 if (Subtarget->hasFullFP16()) {
995 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
996 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
997 }
998 }
999
1000 if (!Subtarget->hasFP16()) {
1001 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1002 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1003 }
1004
1005 computeRegisterProperties(Subtarget->getRegisterInfo());
1006
1007 // ARM does not have floating-point extending loads.
1008 for (MVT VT : MVT::fp_valuetypes()) {
1009 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1010 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1011 }
1012
1013 // ... or truncating stores
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1016 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1017
1018 // ARM does not have i1 sign extending load.
1019 for (MVT VT : MVT::integer_valuetypes())
1020 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1021
1022 // ARM supports all 4 flavors of integer indexed load / store.
1023 if (!Subtarget->isThumb1Only()) {
1024 for (unsigned im = (unsigned)ISD::PRE_INC;
1025 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1026 setIndexedLoadAction(im, MVT::i1, Legal);
1027 setIndexedLoadAction(im, MVT::i8, Legal);
1028 setIndexedLoadAction(im, MVT::i16, Legal);
1029 setIndexedLoadAction(im, MVT::i32, Legal);
1030 setIndexedStoreAction(im, MVT::i1, Legal);
1031 setIndexedStoreAction(im, MVT::i8, Legal);
1032 setIndexedStoreAction(im, MVT::i16, Legal);
1033 setIndexedStoreAction(im, MVT::i32, Legal);
1034 }
1035 } else {
1036 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1037 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1038 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1039 }
1040
1041 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1042 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1043 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1044 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1045
1046 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1047 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1048 if (Subtarget->hasDSP()) {
1049 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1050 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1051 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1052 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1053 }
1054 if (Subtarget->hasBaseDSP()) {
1055 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1056 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1057 }
1058
1059 // i64 operation support.
1060 setOperationAction(ISD::MUL, MVT::i64, Expand);
1061 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1062 if (Subtarget->isThumb1Only()) {
1063 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1064 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1065 }
1066 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1067 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1068 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1069
1070 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1071 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1072 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1073 setOperationAction(ISD::SRL, MVT::i64, Custom);
1074 setOperationAction(ISD::SRA, MVT::i64, Custom);
1075 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1076 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1077
1078 // MVE lowers 64 bit shifts to lsll and lsrl
1079 // assuming that ISD::SRL and SRA of i64 are already marked custom
1080 if (Subtarget->hasMVEIntegerOps())
1081 setOperationAction(ISD::SHL, MVT::i64, Custom);
1082
1083 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1084 if (Subtarget->isThumb1Only()) {
1085 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1086 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1087 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1088 }
1089
1090 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1091 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1092
1093 // ARM does not have ROTL.
1094 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1095 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1096 setOperationAction(ISD::ROTL, VT, Expand);
1097 setOperationAction(ISD::ROTR, VT, Expand);
1098 }
1099 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1100 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1101 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1102 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1103 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1104 }
1105
1106 // @llvm.readcyclecounter requires the Performance Monitors extension.
1107 // Default to the 0 expansion on unsupported platforms.
1108 // FIXME: Technically there are older ARM CPUs that have
1109 // implementation-specific ways of obtaining this information.
1110 if (Subtarget->hasPerfMon())
1111 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1112
1113 // Only ARMv6 has BSWAP.
1114 if (!Subtarget->hasV6Ops())
1115 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1116
1117 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1118 : Subtarget->hasDivideInARMMode();
1119 if (!hasDivide) {
1120 // These are expanded into libcalls if the cpu doesn't have HW divider.
1121 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1122 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1123 }
1124
1125 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1126 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1127 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1128
1129 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1130 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1131 }
1132
1133 setOperationAction(ISD::SREM, MVT::i32, Expand);
1134 setOperationAction(ISD::UREM, MVT::i32, Expand);
1135
1136 // Register based DivRem for AEABI (RTABI 4.2)
1137 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1138 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1139 Subtarget->isTargetWindows()) {
1140 setOperationAction(ISD::SREM, MVT::i64, Custom);
1141 setOperationAction(ISD::UREM, MVT::i64, Custom);
1142 HasStandaloneRem = false;
1143
1144 if (Subtarget->isTargetWindows()) {
1145 const struct {
1146 const RTLIB::Libcall Op;
1147 const char * const Name;
1148 const CallingConv::ID CC;
1149 } LibraryCalls[] = {
1150 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1151 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1152 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1153 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1154
1155 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1156 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1157 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1158 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1159 };
1160
1161 for (const auto &LC : LibraryCalls) {
1162 setLibcallName(LC.Op, LC.Name);
1163 setLibcallCallingConv(LC.Op, LC.CC);
1164 }
1165 } else {
1166 const struct {
1167 const RTLIB::Libcall Op;
1168 const char * const Name;
1169 const CallingConv::ID CC;
1170 } LibraryCalls[] = {
1171 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1172 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1173 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1174 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1175
1176 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1177 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1178 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1179 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1180 };
1181
1182 for (const auto &LC : LibraryCalls) {
1183 setLibcallName(LC.Op, LC.Name);
1184 setLibcallCallingConv(LC.Op, LC.CC);
1185 }
1186 }
1187
1188 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1189 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1190 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1191 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1192 } else {
1193 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1194 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1195 }
1196
1197 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1198 // MSVCRT doesn't have powi; fall back to pow
1199 setLibcallName(RTLIB::POWI_F32, nullptr);
1200 setLibcallName(RTLIB::POWI_F64, nullptr);
1201 }
1202
1203 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1204 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1205 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1206 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1207
1208 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1209 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1210
1211 // Use the default implementation.
1212 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1213 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1214 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1215 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1216 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1217 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1218
1219 if (Subtarget->isTargetWindows())
1220 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1221 else
1222 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1223
1224 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1225 // the default expansion.
1226 InsertFencesForAtomic = false;
1227 if (Subtarget->hasAnyDataBarrier() &&
1228 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1229 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1230 // to ldrex/strex loops already.
1231 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1232 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1233 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1234
1235 // On v8, we have particularly efficient implementations of atomic fences
1236 // if they can be combined with nearby atomic loads and stores.
1237 if (!Subtarget->hasAcquireRelease() ||
1238 getTargetMachine().getOptLevel() == 0) {
1239 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1240 InsertFencesForAtomic = true;
1241 }
1242 } else {
1243 // If there's anything we can use as a barrier, go through custom lowering
1244 // for ATOMIC_FENCE.
1245 // If target has DMB in thumb, Fences can be inserted.
1246 if (Subtarget->hasDataBarrier())
1247 InsertFencesForAtomic = true;
1248
1249 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1250 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1251
1252 // Set them all for expansion, which will force libcalls.
1253 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1254 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1255 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1256 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1257 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1258 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1259 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1260 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1261 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1262 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1263 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1264 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1265 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1266 // Unordered/Monotonic case.
1267 if (!InsertFencesForAtomic) {
1268 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1269 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1270 }
1271 }
1272
1273 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1274
1275 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1276 if (!Subtarget->hasV6Ops()) {
1277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1279 }
1280 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1281
1282 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1283 !Subtarget->isThumb1Only()) {
1284 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1285 // iff target supports vfp2.
1286 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1287 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1288 }
1289
1290 // We want to custom lower some of our intrinsics.
1291 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1292 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1293 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1294 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1295 if (Subtarget->useSjLjEH())
1296 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1297
1298 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1299 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1300 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1301 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1302 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1303 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1304 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1305 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1306 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1307 if (Subtarget->hasFullFP16()) {
1308 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1309 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1310 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1311 }
1312
1313 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1314
1315 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1316 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1317 if (Subtarget->hasFullFP16())
1318 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1319 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1320 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1321 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1322
1323 // We don't support sin/cos/fmod/copysign/pow
1324 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1325 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1326 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1327 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1328 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1329 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1330 setOperationAction(ISD::FREM, MVT::f64, Expand);
1331 setOperationAction(ISD::FREM, MVT::f32, Expand);
1332 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1333 !Subtarget->isThumb1Only()) {
1334 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1335 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1336 }
1337 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1338 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1339
1340 if (!Subtarget->hasVFP4Base()) {
1341 setOperationAction(ISD::FMA, MVT::f64, Expand);
1342 setOperationAction(ISD::FMA, MVT::f32, Expand);
1343 }
1344
1345 // Various VFP goodness
1346 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1347 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1348 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1349 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1350 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1351 }
1352
1353 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1354 if (!Subtarget->hasFP16()) {
1355 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1356 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1357 }
1358
1359 // Strict floating-point comparisons need custom lowering.
1360 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1361 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1362 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1363 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1364 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1365 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1366 }
1367
1368 // Use __sincos_stret if available.
1369 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1370 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1371 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1372 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1373 }
1374
1375 // FP-ARMv8 implements a lot of rounding-like FP operations.
1376 if (Subtarget->hasFPARMv8Base()) {
1377 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1378 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1379 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1380 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1381 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1382 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1383 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1384 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1385 if (Subtarget->hasNEON()) {
1386 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1387 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1388 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1389 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1390 }
1391
1392 if (Subtarget->hasFP64()) {
1393 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1394 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1395 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1396 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1397 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1398 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1399 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1400 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1401 }
1402 }
1403
1404 // FP16 often need to be promoted to call lib functions
1405 if (Subtarget->hasFullFP16()) {
1406 setOperationAction(ISD::FREM, MVT::f16, Promote);
1407 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1408 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1409 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1410 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1411 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1412 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1413 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1414 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1415 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1416 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1417 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1418
1419 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1420 }
1421
1422 if (Subtarget->hasNEON()) {
1423 // vmin and vmax aren't available in a scalar form, so we use
1424 // a NEON instruction with an undef lane instead.
1425 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1426 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1427 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1428 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1429 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1430 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1431 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1432 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1433
1434 if (Subtarget->hasFullFP16()) {
1435 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1436 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1437 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1438 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1439
1440 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1441 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1442 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1443 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1444 }
1445 }
1446
1447 // We have target-specific dag combine patterns for the following nodes:
1448 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1449 setTargetDAGCombine(ISD::ADD);
1450 setTargetDAGCombine(ISD::SUB);
1451 setTargetDAGCombine(ISD::MUL);
1452 setTargetDAGCombine(ISD::AND);
1453 setTargetDAGCombine(ISD::OR);
1454 setTargetDAGCombine(ISD::XOR);
1455
1456 if (Subtarget->hasV6Ops())
1457 setTargetDAGCombine(ISD::SRL);
1458 if (Subtarget->isThumb1Only())
1459 setTargetDAGCombine(ISD::SHL);
1460
1461 setStackPointerRegisterToSaveRestore(ARM::SP);
1462
1463 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1464 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1465 setSchedulingPreference(Sched::RegPressure);
1466 else
1467 setSchedulingPreference(Sched::Hybrid);
1468
1469 //// temporary - rewrite interface to use type
1470 MaxStoresPerMemset = 8;
1471 MaxStoresPerMemsetOptSize = 4;
1472 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1473 MaxStoresPerMemcpyOptSize = 2;
1474 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1475 MaxStoresPerMemmoveOptSize = 2;
1476
1477 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1478 // are at least 4 bytes aligned.
1479 setMinStackArgumentAlignment(Align(4));
1480
1481 // Prefer likely predicted branches to selects on out-of-order cores.
1482 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1483
1484 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1485
1486 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1487
1488 if (Subtarget->isThumb() || Subtarget->isThumb2())
1489 setTargetDAGCombine(ISD::ABS);
1490}
1491
1492bool ARMTargetLowering::useSoftFloat() const {
1493 return Subtarget->useSoftFloat();
1494}
1495
1496// FIXME: It might make sense to define the representative register class as the
1497// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1498// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1499// SPR's representative would be DPR_VFP2. This should work well if register
1500// pressure tracking were modified such that a register use would increment the
1501// pressure of the register class's representative and all of it's super
1502// classes' representatives transitively. We have not implemented this because
1503// of the difficulty prior to coalescing of modeling operand register classes
1504// due to the common occurrence of cross class copies and subregister insertions
1505// and extractions.
1506std::pair<const TargetRegisterClass *, uint8_t>
1507ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1508 MVT VT) const {
1509 const TargetRegisterClass *RRC = nullptr;
1510 uint8_t Cost = 1;
1511 switch (VT.SimpleTy) {
1512 default:
1513 return TargetLowering::findRepresentativeClass(TRI, VT);
1514 // Use DPR as representative register class for all floating point
1515 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1516 // the cost is 1 for both f32 and f64.
1517 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1518 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1519 RRC = &ARM::DPRRegClass;
1520 // When NEON is used for SP, only half of the register file is available
1521 // because operations that define both SP and DP results will be constrained
1522 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1523 // coalescing by double-counting the SP regs. See the FIXME above.
1524 if (Subtarget->useNEONForSinglePrecisionFP())
1525 Cost = 2;
1526 break;
1527 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1528 case MVT::v4f32: case MVT::v2f64:
1529 RRC = &ARM::DPRRegClass;
1530 Cost = 2;
1531 break;
1532 case MVT::v4i64:
1533 RRC = &ARM::DPRRegClass;
1534 Cost = 4;
1535 break;
1536 case MVT::v8i64:
1537 RRC = &ARM::DPRRegClass;
1538 Cost = 8;
1539 break;
1540 }
1541 return std::make_pair(RRC, Cost);
1542}
1543
1544const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1545 switch ((ARMISD::NodeType)Opcode) {
1546 case ARMISD::FIRST_NUMBER: break;
1547 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1548 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1549 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1550 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1551 case ARMISD::CALL: return "ARMISD::CALL";
1552 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1553 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1554 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1555 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1556 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1557 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1558 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1559 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1560 case ARMISD::CMP: return "ARMISD::CMP";
1561 case ARMISD::CMN: return "ARMISD::CMN";
1562 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1563 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1564 case ARMISD::CMPFPE: return "ARMISD::CMPFPE";
1565 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1566 case ARMISD::CMPFPEw0: return "ARMISD::CMPFPEw0";
1567 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1568 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1569
1570 case ARMISD::CMOV: return "ARMISD::CMOV";
1571 case ARMISD::SUBS: return "ARMISD::SUBS";
1572
1573 case ARMISD::SSAT: return "ARMISD::SSAT";
1574 case ARMISD::USAT: return "ARMISD::USAT";
1575
1576 case ARMISD::ASRL: return "ARMISD::ASRL";
1577 case ARMISD::LSRL: return "ARMISD::LSRL";
1578 case ARMISD::LSLL: return "ARMISD::LSLL";
1579
1580 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1581 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1582 case ARMISD::RRX: return "ARMISD::RRX";
1583
1584 case ARMISD::ADDC: return "ARMISD::ADDC";
1585 case ARMISD::ADDE: return "ARMISD::ADDE";
1586 case ARMISD::SUBC: return "ARMISD::SUBC";
1587 case ARMISD::SUBE: return "ARMISD::SUBE";
1588 case ARMISD::LSLS: return "ARMISD::LSLS";
1589
1590 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1591 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1592 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1593 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1594 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1595
1596 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1597 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1598 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1599
1600 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1601
1602 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1603
1604 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1605
1606 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1607
1608 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1609
1610 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1611 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1612
1613 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1614 case ARMISD::VECTOR_REG_CAST: return "ARMISD::VECTOR_REG_CAST";
1615 case ARMISD::VCMP: return "ARMISD::VCMP";
1616 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1617 case ARMISD::VTST: return "ARMISD::VTST";
1618
1619 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1620 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1621 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1622 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1623 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1624 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1625 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1626 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1627 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1628 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1629 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1630 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1631 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1632 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1633 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1634 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1635 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1636 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1637 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1638 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1639 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1640 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1641 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1642 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1643 case ARMISD::VDUP: return "ARMISD::VDUP";
1644 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1645 case ARMISD::VEXT: return "ARMISD::VEXT";
1646 case ARMISD::VREV64: return "ARMISD::VREV64";
1647 case ARMISD::VREV32: return "ARMISD::VREV32";
1648 case ARMISD::VREV16: return "ARMISD::VREV16";
1649 case ARMISD::VZIP: return "ARMISD::VZIP";
1650 case ARMISD::VUZP: return "ARMISD::VUZP";
1651 case ARMISD::VTRN: return "ARMISD::VTRN";
1652 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1653 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1654 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1655 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1656 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1657 case ARMISD::VADDVs: return "ARMISD::VADDVs";
1658 case ARMISD::VADDVu: return "ARMISD::VADDVu";
1659 case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
1660 case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
1661 case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
1662 case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu";
1663 case ARMISD::VMLAVs: return "ARMISD::VMLAVs";
1664 case ARMISD::VMLAVu: return "ARMISD::VMLAVu";
1665 case ARMISD::VMLALVs: return "ARMISD::VMLALVs";
1666 case ARMISD::VMLALVu: return "ARMISD::VMLALVu";
1667 case ARMISD::VMLALVAs: return "ARMISD::VMLALVAs";
1668 case ARMISD::VMLALVAu: return "ARMISD::VMLALVAu";
1669 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1670 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1671 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1672 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1673 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1674 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1675 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1676 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1677 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1678 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1679 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1680 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1681 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1682 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1683 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1684 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1685 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1686 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1687 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1688 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1689 case ARMISD::BFI: return "ARMISD::BFI";
1690 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1691 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1692 case ARMISD::VBSL: return "ARMISD::VBSL";
1693 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1694 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1695 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1696 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1697 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1698 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1699 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1700 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1701 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1702 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1703 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1704 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1705 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1706 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1707 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1708 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1709 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1710 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1711 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1712 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1713 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1714 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1715 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1716 case ARMISD::WLS: return "ARMISD::WLS";
1717 case ARMISD::LE: return "ARMISD::LE";
1718 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1719 case ARMISD::CSINV: return "ARMISD::CSINV";
1720 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1721 case ARMISD::CSINC: return "ARMISD::CSINC";
1722 }
1723 return nullptr;
1724}
1725
1726EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1727 EVT VT) const {
1728 if (!VT.isVector())
1729 return getPointerTy(DL);
1730
1731 // MVE has a predicate register.
1732 if (Subtarget->hasMVEIntegerOps() &&
1733 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1734 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1735 return VT.changeVectorElementTypeToInteger();
1736}
1737
1738/// getRegClassFor - Return the register class that should be used for the
1739/// specified value type.
1740const TargetRegisterClass *
1741ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1742 (void)isDivergent;
1743 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1744 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1745 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1746 // MVE Q registers.
1747 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1748 if (VT == MVT::v4i64)
1749 return &ARM::QQPRRegClass;
1750 if (VT == MVT::v8i64)
1751 return &ARM::QQQQPRRegClass;
1752 }
1753 return TargetLowering::getRegClassFor(VT);
1754}
1755
1756// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1757// source/dest is aligned and the copy size is large enough. We therefore want
1758// to align such objects passed to memory intrinsics.
1759bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1760 unsigned &PrefAlign) const {
1761 if (!isa<MemIntrinsic>(CI))
1762 return false;
1763 MinSize = 8;
1764 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1765 // cycle faster than 4-byte aligned LDM.
1766 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1767 return true;
1768}
1769
1770// Create a fast isel object.
1771FastISel *
1772ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1773 const TargetLibraryInfo *libInfo) const {
1774 return ARM::createFastISel(funcInfo, libInfo);
1775}
1776
1777Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1778 unsigned NumVals = N->getNumValues();
1779 if (!NumVals)
1780 return Sched::RegPressure;
1781
1782 for (unsigned i = 0; i != NumVals; ++i) {
1783 EVT VT = N->getValueType(i);
1784 if (VT == MVT::Glue || VT == MVT::Other)
1785 continue;
1786 if (VT.isFloatingPoint() || VT.isVector())
1787 return Sched::ILP;
1788 }
1789
1790 if (!N->isMachineOpcode())
1791 return Sched::RegPressure;
1792
1793 // Load are scheduled for latency even if there instruction itinerary
1794 // is not available.
1795 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1796 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1797
1798 if (MCID.getNumDefs() == 0)
1799 return Sched::RegPressure;
1800 if (!Itins->isEmpty() &&
1801 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1802 return Sched::ILP;
1803
1804 return Sched::RegPressure;
1805}
1806
1807//===----------------------------------------------------------------------===//
1808// Lowering Code
1809//===----------------------------------------------------------------------===//
1810
1811static bool isSRL16(const SDValue &Op) {
1812 if (Op.getOpcode() != ISD::SRL)
1813 return false;
1814 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1815 return Const->getZExtValue() == 16;
1816 return false;
1817}
1818
1819static bool isSRA16(const SDValue &Op) {
1820 if (Op.getOpcode() != ISD::SRA)
1821 return false;
1822 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1823 return Const->getZExtValue() == 16;
1824 return false;
1825}
1826
1827static bool isSHL16(const SDValue &Op) {
1828 if (Op.getOpcode() != ISD::SHL)
1829 return false;
1830 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1831 return Const->getZExtValue() == 16;
1832 return false;
1833}
1834
1835// Check for a signed 16-bit value. We special case SRA because it makes it
1836// more simple when also looking for SRAs that aren't sign extending a
1837// smaller value. Without the check, we'd need to take extra care with
1838// checking order for some operations.
1839static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1840 if (isSRA16(Op))
1841 return isSHL16(Op.getOperand(0));
1842 return DAG.ComputeNumSignBits(Op) == 17;
1843}
1844
1845/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1846static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1847 switch (CC) {
1848 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1848)
;
1849 case ISD::SETNE: return ARMCC::NE;
1850 case ISD::SETEQ: return ARMCC::EQ;
1851 case ISD::SETGT: return ARMCC::GT;
1852 case ISD::SETGE: return ARMCC::GE;
1853 case ISD::SETLT: return ARMCC::LT;
1854 case ISD::SETLE: return ARMCC::LE;
1855 case ISD::SETUGT: return ARMCC::HI;
1856 case ISD::SETUGE: return ARMCC::HS;
1857 case ISD::SETULT: return ARMCC::LO;
1858 case ISD::SETULE: return ARMCC::LS;
1859 }
1860}
1861
1862/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1863static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1864 ARMCC::CondCodes &CondCode2) {
1865 CondCode2 = ARMCC::AL;
1866 switch (CC) {
1867 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1867)
;
1868 case ISD::SETEQ:
1869 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1870 case ISD::SETGT:
1871 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1872 case ISD::SETGE:
1873 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1874 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1875 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1876 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1877 case ISD::SETO: CondCode = ARMCC::VC; break;
1878 case ISD::SETUO: CondCode = ARMCC::VS; break;
1879 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1880 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1881 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1882 case ISD::SETLT:
1883 case ISD::SETULT: CondCode = ARMCC::LT; break;
1884 case ISD::SETLE:
1885 case ISD::SETULE: CondCode = ARMCC::LE; break;
1886 case ISD::SETNE:
1887 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1888 }
1889}
1890
1891//===----------------------------------------------------------------------===//
1892// Calling Convention Implementation
1893//===----------------------------------------------------------------------===//
1894
1895/// getEffectiveCallingConv - Get the effective calling convention, taking into
1896/// account presence of floating point hardware and calling convention
1897/// limitations, such as support for variadic functions.
1898CallingConv::ID
1899ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1900 bool isVarArg) const {
1901 switch (CC) {
1902 default:
1903 report_fatal_error("Unsupported calling convention");
1904 case CallingConv::ARM_AAPCS:
1905 case CallingConv::ARM_APCS:
1906 case CallingConv::GHC:
1907 case CallingConv::CFGuard_Check:
1908 return CC;
1909 case CallingConv::PreserveMost:
1910 return CallingConv::PreserveMost;
1911 case CallingConv::ARM_AAPCS_VFP:
1912 case CallingConv::Swift:
1913 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1914 case CallingConv::C:
1915 if (!Subtarget->isAAPCS_ABI())
1916 return CallingConv::ARM_APCS;
1917 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
1918 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1919 !isVarArg)
1920 return CallingConv::ARM_AAPCS_VFP;
1921 else
1922 return CallingConv::ARM_AAPCS;
1923 case CallingConv::Fast:
1924 case CallingConv::CXX_FAST_TLS:
1925 if (!Subtarget->isAAPCS_ABI()) {
1926 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
1927 return CallingConv::Fast;
1928 return CallingConv::ARM_APCS;
1929 } else if (Subtarget->hasVFP2Base() &&
1930 !Subtarget->isThumb1Only() && !isVarArg)
1931 return CallingConv::ARM_AAPCS_VFP;
1932 else
1933 return CallingConv::ARM_AAPCS;
1934 }
1935}
1936
1937CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1938 bool isVarArg) const {
1939 return CCAssignFnForNode(CC, false, isVarArg);
1940}
1941
1942CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1943 bool isVarArg) const {
1944 return CCAssignFnForNode(CC, true, isVarArg);
1945}
1946
1947/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1948/// CallingConvention.
1949CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1950 bool Return,
1951 bool isVarArg) const {
1952 switch (getEffectiveCallingConv(CC, isVarArg)) {
1953 default:
1954 report_fatal_error("Unsupported calling convention");
1955 case CallingConv::ARM_APCS:
1956 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1957 case CallingConv::ARM_AAPCS:
1958 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1959 case CallingConv::ARM_AAPCS_VFP:
1960 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1961 case CallingConv::Fast:
1962 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1963 case CallingConv::GHC:
1964 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1965 case CallingConv::PreserveMost:
1966 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1967 case CallingConv::CFGuard_Check:
1968 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1969 }
1970}
1971
1972/// LowerCallResult - Lower the result values of a call into the
1973/// appropriate copies out of appropriate physical registers.
1974SDValue ARMTargetLowering::LowerCallResult(
1975 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1977 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1978 SDValue ThisVal) const {
1979 // Assign locations to each value returned by this call.
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1982 *DAG.getContext());
1983 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1984
1985 // Copy all of the result registers out of their specified physreg.
1986 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1987 CCValAssign VA = RVLocs[i];
1988
1989 // Pass 'this' value directly from the argument to return value, to avoid
1990 // reg unit interference
1991 if (i == 0 && isThisReturn) {
1992 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1993, __PRETTY_FUNCTION__))
1993 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1993, __PRETTY_FUNCTION__))
;
1994 InVals.push_back(ThisVal);
1995 continue;
1996 }
1997
1998 SDValue Val;
1999 if (VA.needsCustom()) {
2000 // Handle f64 or half of a v2f64.
2001 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2002 InFlag);
2003 Chain = Lo.getValue(1);
2004 InFlag = Lo.getValue(2);
2005 VA = RVLocs[++i]; // skip ahead to next loc
2006 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2007 InFlag);
2008 Chain = Hi.getValue(1);
2009 InFlag = Hi.getValue(2);
2010 if (!Subtarget->isLittle())
2011 std::swap (Lo, Hi);
2012 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2013
2014 if (VA.getLocVT() == MVT::v2f64) {
2015 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2016 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2017 DAG.getConstant(0, dl, MVT::i32));
2018
2019 VA = RVLocs[++i]; // skip ahead to next loc
2020 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2021 Chain = Lo.getValue(1);
2022 InFlag = Lo.getValue(2);
2023 VA = RVLocs[++i]; // skip ahead to next loc
2024 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2025 Chain = Hi.getValue(1);
2026 InFlag = Hi.getValue(2);
2027 if (!Subtarget->isLittle())
2028 std::swap (Lo, Hi);
2029 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2030 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2031 DAG.getConstant(1, dl, MVT::i32));
2032 }
2033 } else {
2034 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2035 InFlag);
2036 Chain = Val.getValue(1);
2037 InFlag = Val.getValue(2);
2038 }
2039
2040 switch (VA.getLocInfo()) {
2041 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2041)
;
2042 case CCValAssign::Full: break;
2043 case CCValAssign::BCvt:
2044 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2045 break;
2046 }
2047
2048 InVals.push_back(Val);
2049 }
2050
2051 return Chain;
2052}
2053
2054/// LowerMemOpCallTo - Store the argument to the stack.
2055SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2056 SDValue Arg, const SDLoc &dl,
2057 SelectionDAG &DAG,
2058 const CCValAssign &VA,
2059 ISD::ArgFlagsTy Flags) const {
2060 unsigned LocMemOffset = VA.getLocMemOffset();
2061 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2062 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2063 StackPtr, PtrOff);
2064 return DAG.getStore(
2065 Chain, dl, Arg, PtrOff,
2066 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2067}
2068
2069void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2070 SDValue Chain, SDValue &Arg,
2071 RegsToPassVector &RegsToPass,
2072 CCValAssign &VA, CCValAssign &NextVA,
2073 SDValue &StackPtr,
2074 SmallVectorImpl<SDValue> &MemOpChains,
2075 ISD::ArgFlagsTy Flags) const {
2076 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2077 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2078 unsigned id = Subtarget->isLittle() ? 0 : 1;
2079 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2080
2081 if (NextVA.isRegLoc())
2082 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2083 else {
2084 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2084, __PRETTY_FUNCTION__))
;
2085 if (!StackPtr.getNode())
2086 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2087 getPointerTy(DAG.getDataLayout()));
2088
2089 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2090 dl, DAG, NextVA,
2091 Flags));
2092 }
2093}
2094
2095/// LowerCall - Lowering a call into a callseq_start <-
2096/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2097/// nodes.
2098SDValue
2099ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2100 SmallVectorImpl<SDValue> &InVals) const {
2101 SelectionDAG &DAG = CLI.DAG;
2102 SDLoc &dl = CLI.DL;
2103 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2104 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2105 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2106 SDValue Chain = CLI.Chain;
2107 SDValue Callee = CLI.Callee;
2108 bool &isTailCall = CLI.IsTailCall;
2109 CallingConv::ID CallConv = CLI.CallConv;
2110 bool doesNotRet = CLI.DoesNotReturn;
2111 bool isVarArg = CLI.IsVarArg;
2112
2113 MachineFunction &MF = DAG.getMachineFunction();
2114 MachineFunction::CallSiteInfo CSInfo;
2115 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2116 bool isThisReturn = false;
2117 bool PreferIndirect = false;
2118
2119 // Disable tail calls if they're not supported.
2120 if (!Subtarget->supportsTailCall())
2121 isTailCall = false;
2122
2123 if (isa<GlobalAddressSDNode>(Callee)) {
2124 // If we're optimizing for minimum size and the function is called three or
2125 // more times in this block, we can improve codesize by calling indirectly
2126 // as BLXr has a 16-bit encoding.
2127 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2128 if (CLI.CS) {
2129 auto *BB = CLI.CS.getParent();
2130 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2131 count_if(GV->users(), [&BB](const User *U) {
2132 return isa<Instruction>(U) &&
2133 cast<Instruction>(U)->getParent() == BB;
2134 }) > 2;
2135 }
2136 }
2137 if (isTailCall) {
2138 // Check if it's really possible to do a tail call.
2139 isTailCall = IsEligibleForTailCallOptimization(
2140 Callee, CallConv, isVarArg, isStructRet,
2141 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2142 PreferIndirect);
2143 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
2144 report_fatal_error("failed to perform tail call elimination on a call "
2145 "site marked musttail");
2146 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2147 // detected sibcalls.
2148 if (isTailCall)
2149 ++NumTailCalls;
2150 }
2151
2152 // Analyze operands of the call, assigning locations to each operand.
2153 SmallVector<CCValAssign, 16> ArgLocs;
2154 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2155 *DAG.getContext());
2156 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2157
2158 // Get a count of how many bytes are to be pushed on the stack.
2159 unsigned NumBytes = CCInfo.getNextStackOffset();
2160
2161 if (isTailCall) {
2162 // For tail calls, memory operands are available in our caller's stack.
2163 NumBytes = 0;
2164 } else {
2165 // Adjust the stack pointer for the new arguments...
2166 // These operations are automatically eliminated by the prolog/epilog pass
2167 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2168 }
2169
2170 SDValue StackPtr =
2171 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2172
2173 RegsToPassVector RegsToPass;
2174 SmallVector<SDValue, 8> MemOpChains;
2175
2176 // Walk the register/memloc assignments, inserting copies/loads. In the case
2177 // of tail call optimization, arguments are handled later.
2178 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2179 i != e;
2180 ++i, ++realArgIdx) {
2181 CCValAssign &VA = ArgLocs[i];
2182 SDValue Arg = OutVals[realArgIdx];
2183 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2184 bool isByVal = Flags.isByVal();
2185
2186 // Promote the value if needed.
2187 switch (VA.getLocInfo()) {
2188 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2188)
;
2189 case CCValAssign::Full: break;
2190 case CCValAssign::SExt:
2191 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2192 break;
2193 case CCValAssign::ZExt:
2194 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2195 break;
2196 case CCValAssign::AExt:
2197 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2198 break;
2199 case CCValAssign::BCvt:
2200 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2201 break;
2202 }
2203
2204 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2205 if (VA.needsCustom()) {
2206 if (VA.getLocVT() == MVT::v2f64) {
2207 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2208 DAG.getConstant(0, dl, MVT::i32));
2209 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2210 DAG.getConstant(1, dl, MVT::i32));
2211
2212 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
2213 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2214
2215 VA = ArgLocs[++i]; // skip ahead to next loc
2216 if (VA.isRegLoc()) {
2217 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
2218 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2219 } else {
2220 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2220, __PRETTY_FUNCTION__))
;
2221
2222 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
2223 dl, DAG, VA, Flags));
2224 }
2225 } else {
2226 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2227 StackPtr, MemOpChains, Flags);
2228 }
2229 } else if (VA.isRegLoc()) {
2230 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2231 Outs[0].VT == MVT::i32) {
2232 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2233, __PRETTY_FUNCTION__))
2233 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2233, __PRETTY_FUNCTION__))
;
2234 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2235, __PRETTY_FUNCTION__))
2235 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2235, __PRETTY_FUNCTION__))
;
2236 isThisReturn = true;
2237 }
2238 const TargetOptions &Options = DAG.getTarget().Options;
2239 if (Options.EnableDebugEntryValues)
2240 CSInfo.emplace_back(VA.getLocReg(), i);
2241 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2242 } else if (isByVal) {
2243 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2243, __PRETTY_FUNCTION__))
;
2244 unsigned offset = 0;
2245
2246 // True if this byval aggregate will be split between registers
2247 // and memory.
2248 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2249 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2250
2251 if (CurByValIdx < ByValArgsCount) {
2252
2253 unsigned RegBegin, RegEnd;
2254 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2255
2256 EVT PtrVT =
2257 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2258 unsigned int i, j;
2259 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2260 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2261 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2262 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
2263 MachinePointerInfo(),
2264 DAG.InferPtrAlignment(AddArg));
2265 MemOpChains.push_back(Load.getValue(1));
2266 RegsToPass.push_back(std::make_pair(j, Load));
2267 }
2268
2269 // If parameter size outsides register area, "offset" value
2270 // helps us to calculate stack slot for remained part properly.
2271 offset = RegEnd - RegBegin;
2272
2273 CCInfo.nextInRegsParam();
2274 }
2275
2276 if (Flags.getByValSize() > 4*offset) {
2277 auto PtrVT = getPointerTy(DAG.getDataLayout());
2278 unsigned LocMemOffset = VA.getLocMemOffset();
2279 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2280 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2281 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2282 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2283 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2284 MVT::i32);
2285 SDValue AlignNode =
2286 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2287
2288 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2289 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2290 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2291 Ops));
2292 }
2293 } else if (!isTailCall) {
2294 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2294, __PRETTY_FUNCTION__))
;
2295
2296 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2297 dl, DAG, VA, Flags));
2298 }
2299 }
2300
2301 if (!MemOpChains.empty())
2302 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2303
2304 // Build a sequence of copy-to-reg nodes chained together with token chain
2305 // and flag operands which copy the outgoing args into the appropriate regs.
2306 SDValue InFlag;
2307 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2308 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2309 RegsToPass[i].second, InFlag);
2310 InFlag = Chain.getValue(1);
2311 }
2312
2313 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2314 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2315 // node so that legalize doesn't hack it.
2316 bool isDirect = false;
2317
2318 const TargetMachine &TM = getTargetMachine();
2319 const Module *Mod = MF.getFunction().getParent();
2320 const GlobalValue *GV = nullptr;
2321 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2322 GV = G->getGlobal();
2323 bool isStub =
2324 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2325
2326 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2327 bool isLocalARMFunc = false;
2328 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2329 auto PtrVt = getPointerTy(DAG.getDataLayout());
2330
2331 if (Subtarget->genLongCalls()) {
2332 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2333, __PRETTY_FUNCTION__))
2333 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2333, __PRETTY_FUNCTION__))
;
2334 // Handle a global address or an external symbol. If it's not one of
2335 // those, the target's already in a register, so we don't need to do
2336 // anything extra.
2337 if (isa<GlobalAddressSDNode>(Callee)) {
2338 // Create a constant pool entry for the callee address
2339 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2340 ARMConstantPoolValue *CPV =
2341 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2342
2343 // Get the address of the callee into a register
2344 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2345 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2346 Callee = DAG.getLoad(
2347 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2348 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2349 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2350 const char *Sym = S->getSymbol();
2351
2352 // Create a constant pool entry for the callee address
2353 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2354 ARMConstantPoolValue *CPV =
2355 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2356 ARMPCLabelIndex, 0);
2357 // Get the address of the callee into a register
2358 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2359 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2360 Callee = DAG.getLoad(
2361 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2362 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2363 }
2364 } else if (isa<GlobalAddressSDNode>(Callee)) {
2365 if (!PreferIndirect) {
2366 isDirect = true;
2367 bool isDef = GV->isStrongDefinitionForLinker();
2368
2369 // ARM call to a local ARM function is predicable.
2370 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2371 // tBX takes a register source operand.
2372 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2373 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2373, __PRETTY_FUNCTION__))
;
2374 Callee = DAG.getNode(
2375 ARMISD::WrapperPIC, dl, PtrVt,
2376 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2377 Callee = DAG.getLoad(
2378 PtrVt, dl, DAG.getEntryNode(), Callee,
2379 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2380 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2381 MachineMemOperand::MOInvariant);
2382 } else if (Subtarget->isTargetCOFF()) {
2383 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2384, __PRETTY_FUNCTION__))
2384 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2384, __PRETTY_FUNCTION__))
;
2385 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2386 if (GV->hasDLLImportStorageClass())
2387 TargetFlags = ARMII::MO_DLLIMPORT;
2388 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2389 TargetFlags = ARMII::MO_COFFSTUB;
2390 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2391 TargetFlags);
2392 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2393 Callee =
2394 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2395 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2396 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2397 } else {
2398 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2399 }
2400 }
2401 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2402 isDirect = true;
2403 // tBX takes a register source operand.
2404 const char *Sym = S->getSymbol();
2405 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2406 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2407 ARMConstantPoolValue *CPV =
2408 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2409 ARMPCLabelIndex, 4);
2410 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2411 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2412 Callee = DAG.getLoad(
2413 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2414 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2415 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2416 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2417 } else {
2418 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2419 }
2420 }
2421
2422 // FIXME: handle tail calls differently.
2423 unsigned CallOpc;
2424 if (Subtarget->isThumb()) {
2425 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2426 CallOpc = ARMISD::CALL_NOLINK;
2427 else
2428 CallOpc = ARMISD::CALL;
2429 } else {
2430 if (!isDirect && !Subtarget->hasV5TOps())
2431 CallOpc = ARMISD::CALL_NOLINK;
2432 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2433 // Emit regular call when code size is the priority
2434 !Subtarget->hasMinSize())
2435 // "mov lr, pc; b _foo" to avoid confusing the RSP
2436 CallOpc = ARMISD::CALL_NOLINK;
2437 else
2438 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2439 }
2440
2441 std::vector<SDValue> Ops;
2442 Ops.push_back(Chain);
2443 Ops.push_back(Callee);
2444
2445 // Add argument registers to the end of the list so that they are known live
2446 // into the call.
2447 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2448 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2449 RegsToPass[i].second.getValueType()));
2450
2451 // Add a register mask operand representing the call-preserved registers.
2452 if (!isTailCall) {
2453 const uint32_t *Mask;
2454 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2455 if (isThisReturn) {
2456 // For 'this' returns, use the R0-preserving mask if applicable
2457 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2458 if (!Mask) {
2459 // Set isThisReturn to false if the calling convention is not one that
2460 // allows 'returned' to be modeled in this way, so LowerCallResult does
2461 // not try to pass 'this' straight through
2462 isThisReturn = false;
2463 Mask = ARI->getCallPreservedMask(MF, CallConv);
2464 }
2465 } else
2466 Mask = ARI->getCallPreservedMask(MF, CallConv);
2467
2468 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2468, __PRETTY_FUNCTION__))
;
2469 Ops.push_back(DAG.getRegisterMask(Mask));
2470 }
2471
2472 if (InFlag.getNode())
2473 Ops.push_back(InFlag);
2474
2475 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2476 if (isTailCall) {
2477 MF.getFrameInfo().setHasTailCall();
2478 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2479 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2480 return Ret;
2481 }
2482
2483 // Returns a chain and a flag for retval copy to use.
2484 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2485 InFlag = Chain.getValue(1);
2486 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2487
2488 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2489 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2490 if (!Ins.empty())
2491 InFlag = Chain.getValue(1);
2492
2493 // Handle result values, copying them out of physregs into vregs that we
2494 // return.
2495 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2496 InVals, isThisReturn,
2497 isThisReturn ? OutVals[0] : SDValue());
2498}
2499
2500/// HandleByVal - Every parameter *after* a byval parameter is passed
2501/// on the stack. Remember the next parameter register to allocate,
2502/// and then confiscate the rest of the parameter registers to insure
2503/// this.
2504void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2505 unsigned Align) const {
2506 // Byval (as with any stack) slots are always at least 4 byte aligned.
2507 Align = std::max(Align, 4U);
2508
2509 unsigned Reg = State->AllocateReg(GPRArgRegs);
2510 if (!Reg)
2511 return;
2512
2513 unsigned AlignInRegs = Align / 4;
2514 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2515 for (unsigned i = 0; i < Waste; ++i)
2516 Reg = State->AllocateReg(GPRArgRegs);
2517
2518 if (!Reg)
2519 return;
2520
2521 unsigned Excess = 4 * (ARM::R4 - Reg);
2522
2523 // Special case when NSAA != SP and parameter size greater than size of
2524 // all remained GPR regs. In that case we can't split parameter, we must
2525 // send it to stack. We also must set NCRN to R4, so waste all
2526 // remained registers.
2527 const unsigned NSAAOffset = State->getNextStackOffset();
2528 if (NSAAOffset != 0 && Size > Excess) {
2529 while (State->AllocateReg(GPRArgRegs))
2530 ;
2531 return;
2532 }
2533
2534 // First register for byval parameter is the first register that wasn't
2535 // allocated before this method call, so it would be "reg".
2536 // If parameter is small enough to be saved in range [reg, r4), then
2537 // the end (first after last) register would be reg + param-size-in-regs,
2538 // else parameter would be splitted between registers and stack,
2539 // end register would be r4 in this case.
2540 unsigned ByValRegBegin = Reg;
2541 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2542 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2543 // Note, first register is allocated in the beginning of function already,
2544 // allocate remained amount of registers we need.
2545 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2546 State->AllocateReg(GPRArgRegs);
2547 // A byval parameter that is split between registers and memory needs its
2548 // size truncated here.
2549 // In the case where the entire structure fits in registers, we set the
2550 // size in memory to zero.
2551 Size = std::max<int>(Size - Excess, 0);
2552}
2553
2554/// MatchingStackOffset - Return true if the given stack call argument is
2555/// already available in the same position (relatively) of the caller's
2556/// incoming argument stack.
2557static
2558bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2559 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2560 const TargetInstrInfo *TII) {
2561 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2562 int FI = std::numeric_limits<int>::max();
2563 if (Arg.getOpcode() == ISD::CopyFromReg) {
2564 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2565 if (!Register::isVirtualRegister(VR))
2566 return false;
2567 MachineInstr *Def = MRI->getVRegDef(VR);
2568 if (!Def)
2569 return false;
2570 if (!Flags.isByVal()) {
2571 if (!TII->isLoadFromStackSlot(*Def, FI))
2572 return false;
2573 } else {
2574 return false;
2575 }
2576 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2577 if (Flags.isByVal())
2578 // ByVal argument is passed in as a pointer but it's now being
2579 // dereferenced. e.g.
2580 // define @foo(%struct.X* %A) {
2581 // tail call @bar(%struct.X* byval %A)
2582 // }
2583 return false;
2584 SDValue Ptr = Ld->getBasePtr();
2585 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2586 if (!FINode)
2587 return false;
2588 FI = FINode->getIndex();
2589 } else
2590 return false;
2591
2592 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2592, __PRETTY_FUNCTION__))
;
2593 if (!MFI.isFixedObjectIndex(FI))
2594 return false;
2595 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2596}
2597
2598/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2599/// for tail call optimization. Targets which want to do tail call
2600/// optimization should implement this function.
2601bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2602 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2603 bool isCalleeStructRet, bool isCallerStructRet,
2604 const SmallVectorImpl<ISD::OutputArg> &Outs,
2605 const SmallVectorImpl<SDValue> &OutVals,
2606 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2607 const bool isIndirect) const {
2608 MachineFunction &MF = DAG.getMachineFunction();
2609 const Function &CallerF = MF.getFunction();
2610 CallingConv::ID CallerCC = CallerF.getCallingConv();
2611
2612 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2612, __PRETTY_FUNCTION__))
;
2613
2614 // Indirect tail calls cannot be optimized for Thumb1 if the args
2615 // to the call take up r0-r3. The reason is that there are no legal registers
2616 // left to hold the pointer to the function to be called.
2617 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2618 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2619 return false;
2620
2621 // Look for obvious safe cases to perform tail call optimization that do not
2622 // require ABI changes. This is what gcc calls sibcall.
2623
2624 // Exception-handling functions need a special set of instructions to indicate
2625 // a return to the hardware. Tail-calling another function would probably
2626 // break this.
2627 if (CallerF.hasFnAttribute("interrupt"))
2628 return false;
2629
2630 // Also avoid sibcall optimization if either caller or callee uses struct
2631 // return semantics.
2632 if (isCalleeStructRet || isCallerStructRet)
2633 return false;
2634
2635 // Externally-defined functions with weak linkage should not be
2636 // tail-called on ARM when the OS does not support dynamic
2637 // pre-emption of symbols, as the AAELF spec requires normal calls
2638 // to undefined weak functions to be replaced with a NOP or jump to the
2639 // next instruction. The behaviour of branch instructions in this
2640 // situation (as used for tail calls) is implementation-defined, so we
2641 // cannot rely on the linker replacing the tail call with a return.
2642 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2643 const GlobalValue *GV = G->getGlobal();
2644 const Triple &TT = getTargetMachine().getTargetTriple();
2645 if (GV->hasExternalWeakLinkage() &&
2646 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2647 return false;
2648 }
2649
2650 // Check that the call results are passed in the same way.
2651 LLVMContext &C = *DAG.getContext();
2652 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2653 CCAssignFnForReturn(CalleeCC, isVarArg),
2654 CCAssignFnForReturn(CallerCC, isVarArg)))
2655 return false;
2656 // The callee has to preserve all registers the caller needs to preserve.
2657 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2658 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2659 if (CalleeCC != CallerCC) {
2660 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2661 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2662 return false;
2663 }
2664
2665 // If Caller's vararg or byval argument has been split between registers and
2666 // stack, do not perform tail call, since part of the argument is in caller's
2667 // local frame.
2668 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2669 if (AFI_Caller->getArgRegsSaveSize())
2670 return false;
2671
2672 // If the callee takes no arguments then go on to check the results of the
2673 // call.
2674 if (!Outs.empty()) {
2675 // Check if stack adjustment is needed. For now, do not do this if any
2676 // argument is passed on the stack.
2677 SmallVector<CCValAssign, 16> ArgLocs;
2678 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2679 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2680 if (CCInfo.getNextStackOffset()) {
2681 // Check if the arguments are already laid out in the right way as
2682 // the caller's fixed stack objects.
2683 MachineFrameInfo &MFI = MF.getFrameInfo();
2684 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2685 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2686 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2687 i != e;
2688 ++i, ++realArgIdx) {
2689 CCValAssign &VA = ArgLocs[i];
2690 EVT RegVT = VA.getLocVT();
2691 SDValue Arg = OutVals[realArgIdx];
2692 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2693 if (VA.getLocInfo() == CCValAssign::Indirect)
2694 return false;
2695 if (VA.needsCustom()) {
2696 // f64 and vector types are split into multiple registers or
2697 // register/stack-slot combinations. The types will not match
2698 // the registers; give up on memory f64 refs until we figure
2699 // out what to do about this.
2700 if (!VA.isRegLoc())
2701 return false;
2702 if (!ArgLocs[++i].isRegLoc())
2703 return false;
2704 if (RegVT == MVT::v2f64) {
2705 if (!ArgLocs[++i].isRegLoc())
2706 return false;
2707 if (!ArgLocs[++i].isRegLoc())
2708 return false;
2709 }
2710 } else if (!VA.isRegLoc()) {
2711 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2712 MFI, MRI, TII))
2713 return false;
2714 }
2715 }
2716 }
2717
2718 const MachineRegisterInfo &MRI = MF.getRegInfo();
2719 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2720 return false;
2721 }
2722
2723 return true;
2724}
2725
2726bool
2727ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2728 MachineFunction &MF, bool isVarArg,
2729 const SmallVectorImpl<ISD::OutputArg> &Outs,
2730 LLVMContext &Context) const {
2731 SmallVector<CCValAssign, 16> RVLocs;
2732 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2733 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2734}
2735
2736static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2737 const SDLoc &DL, SelectionDAG &DAG) {
2738 const MachineFunction &MF = DAG.getMachineFunction();
2739 const Function &F = MF.getFunction();
2740
2741 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2742
2743 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2744 // version of the "preferred return address". These offsets affect the return
2745 // instruction if this is a return from PL1 without hypervisor extensions.
2746 // IRQ/FIQ: +4 "subs pc, lr, #4"
2747 // SWI: 0 "subs pc, lr, #0"
2748 // ABORT: +4 "subs pc, lr, #4"
2749 // UNDEF: +4/+2 "subs pc, lr, #0"
2750 // UNDEF varies depending on where the exception came from ARM or Thumb
2751 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2752
2753 int64_t LROffset;
2754 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2755 IntKind == "ABORT")
2756 LROffset = 4;
2757 else if (IntKind == "SWI" || IntKind == "UNDEF")
2758 LROffset = 0;
2759 else
2760 report_fatal_error("Unsupported interrupt attribute. If present, value "
2761 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2762
2763 RetOps.insert(RetOps.begin() + 1,
2764 DAG.getConstant(LROffset, DL, MVT::i32, false));
2765
2766 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2767}
2768
2769SDValue
2770ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2771 bool isVarArg,
2772 const SmallVectorImpl<ISD::OutputArg> &Outs,
2773 const SmallVectorImpl<SDValue> &OutVals,
2774 const SDLoc &dl, SelectionDAG &DAG) const {
2775 // CCValAssign - represent the assignment of the return value to a location.
2776 SmallVector<CCValAssign, 16> RVLocs;
2777
2778 // CCState - Info about the registers and stack slots.
2779 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2780 *DAG.getContext());
2781
2782 // Analyze outgoing return values.
2783 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2784
2785 SDValue Flag;
2786 SmallVector<SDValue, 4> RetOps;
2787 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2788 bool isLittleEndian = Subtarget->isLittle();
2789
2790 MachineFunction &MF = DAG.getMachineFunction();
2791 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2792 AFI->setReturnRegsCount(RVLocs.size());
2793
2794 // Copy the result values into the output registers.
2795 for (unsigned i = 0, realRVLocIdx = 0;
2796 i != RVLocs.size();
2797 ++i, ++realRVLocIdx) {
2798 CCValAssign &VA = RVLocs[i];
2799 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2799, __PRETTY_FUNCTION__))
;
2800
2801 SDValue Arg = OutVals[realRVLocIdx];
2802 bool ReturnF16 = false;
2803
2804 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2805 // Half-precision return values can be returned like this:
2806 //
2807 // t11 f16 = fadd ...
2808 // t12: i16 = bitcast t11
2809 // t13: i32 = zero_extend t12
2810 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2811 //
2812 // to avoid code generation for bitcasts, we simply set Arg to the node
2813 // that produces the f16 value, t11 in this case.
2814 //
2815 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2816 SDValue ZE = Arg.getOperand(0);
2817 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2818 SDValue BC = ZE.getOperand(0);
2819 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2820 Arg = BC.getOperand(0);
2821 ReturnF16 = true;
2822 }
2823 }
2824 }
2825 }
2826
2827 switch (VA.getLocInfo()) {
2828 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2828)
;
2829 case CCValAssign::Full: break;
2830 case CCValAssign::BCvt:
2831 if (!ReturnF16)
2832 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2833 break;
2834 }
2835
2836 if (VA.needsCustom()) {
2837 if (VA.getLocVT() == MVT::v2f64) {
2838 // Extract the first half and return it in two registers.
2839 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2840 DAG.getConstant(0, dl, MVT::i32));
2841 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2842 DAG.getVTList(MVT::i32, MVT::i32), Half);
2843
2844 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2845 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2846 Flag);
2847 Flag = Chain.getValue(1);
2848 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2849 VA = RVLocs[++i]; // skip ahead to next loc
2850 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2851 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2852 Flag);
2853 Flag = Chain.getValue(1);
2854 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2855 VA = RVLocs[++i]; // skip ahead to next loc
2856
2857 // Extract the 2nd half and fall through to handle it as an f64 value.
2858 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2859 DAG.getConstant(1, dl, MVT::i32));
2860 }
2861 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2862 // available.
2863 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2864 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2865 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2866 fmrrd.getValue(isLittleEndian ? 0 : 1),
2867 Flag);
2868 Flag = Chain.getValue(1);
2869 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2870 VA = RVLocs[++i]; // skip ahead to next loc
2871 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2872 fmrrd.getValue(isLittleEndian ? 1 : 0),
2873 Flag);
2874 } else
2875 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2876
2877 // Guarantee that all emitted copies are
2878 // stuck together, avoiding something bad.
2879 Flag = Chain.getValue(1);
2880 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2881 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2882 }
2883 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2884 const MCPhysReg *I =
2885 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2886 if (I) {
2887 for (; *I; ++I) {
2888 if (ARM::GPRRegClass.contains(*I))
2889 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2890 else if (ARM::DPRRegClass.contains(*I))
2891 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2892 else
2893 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2893)
;
2894 }
2895 }
2896
2897 // Update chain and glue.
2898 RetOps[0] = Chain;
2899 if (Flag.getNode())
2900 RetOps.push_back(Flag);
2901
2902 // CPUs which aren't M-class use a special sequence to return from
2903 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2904 // though we use "subs pc, lr, #N").
2905 //
2906 // M-class CPUs actually use a normal return sequence with a special
2907 // (hardware-provided) value in LR, so the normal code path works.
2908 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2909 !Subtarget->isMClass()) {
2910 if (Subtarget->isThumb1Only())
2911 report_fatal_error("interrupt attribute is not supported in Thumb1");
2912 return LowerInterruptReturn(RetOps, dl, DAG);
2913 }
2914
2915 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2916}
2917
2918bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2919 if (N->getNumValues() != 1)
2920 return false;
2921 if (!N->hasNUsesOfValue(1, 0))
2922 return false;
2923
2924 SDValue TCChain = Chain;
2925 SDNode *Copy = *N->use_begin();
2926 if (Copy->getOpcode() == ISD::CopyToReg) {
2927 // If the copy has a glue operand, we conservatively assume it isn't safe to
2928 // perform a tail call.
2929 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2930 return false;
2931 TCChain = Copy->getOperand(0);
2932 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2933 SDNode *VMov = Copy;
2934 // f64 returned in a pair of GPRs.
2935 SmallPtrSet<SDNode*, 2> Copies;
2936 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2937 UI != UE; ++UI) {
2938 if (UI->getOpcode() != ISD::CopyToReg)
2939 return false;
2940 Copies.insert(*UI);
2941 }
2942 if (Copies.size() > 2)
2943 return false;
2944
2945 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2946 UI != UE; ++UI) {
2947 SDValue UseChain = UI->getOperand(0);
2948 if (Copies.count(UseChain.getNode()))
2949 // Second CopyToReg
2950 Copy = *UI;
2951 else {
2952 // We are at the top of this chain.
2953 // If the copy has a glue operand, we conservatively assume it
2954 // isn't safe to perform a tail call.
2955 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2956 return false;
2957 // First CopyToReg
2958 TCChain = UseChain;
2959 }
2960 }
2961 } else if (Copy->getOpcode() == ISD::BITCAST) {
2962 // f32 returned in a single GPR.
2963 if (!Copy->hasOneUse())
2964 return false;
2965 Copy = *Copy->use_begin();
2966 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2967 return false;
2968 // If the copy has a glue operand, we conservatively assume it isn't safe to
2969 // perform a tail call.
2970 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2971 return false;
2972 TCChain = Copy->getOperand(0);
2973 } else {
2974 return false;
2975 }
2976
2977 bool HasRet = false;
2978 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2979 UI != UE; ++UI) {
2980 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2981 UI->getOpcode() != ARMISD::INTRET_FLAG)
2982 return false;
2983 HasRet = true;
2984 }
2985
2986 if (!HasRet)
2987 return false;
2988
2989 Chain = TCChain;
2990 return true;
2991}
2992
2993bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2994 if (!Subtarget->supportsTailCall())
2995 return false;
2996
2997 if (!CI->isTailCall())
2998 return false;
2999
3000 return true;
3001}
3002
3003// Trying to write a 64 bit value so need to split into two 32 bit values first,
3004// and pass the lower and high parts through.
3005static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3006 SDLoc DL(Op);
3007 SDValue WriteValue = Op->getOperand(2);
3008
3009 // This function is only supposed to be called for i64 type argument.
3010 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3011, __PRETTY_FUNCTION__))
3011 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3011, __PRETTY_FUNCTION__))
;
3012
3013 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3014 DAG.getConstant(0, DL, MVT::i32));
3015 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3016 DAG.getConstant(1, DL, MVT::i32));
3017 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3018 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3019}
3020
3021// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3022// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3023// one of the above mentioned nodes. It has to be wrapped because otherwise
3024// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3025// be used to form addressing mode. These wrapped nodes will be selected
3026// into MOVi.
3027SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3028 SelectionDAG &DAG) const {
3029 EVT PtrVT = Op.getValueType();
3030 // FIXME there is no actual debug info here
3031 SDLoc dl(Op);
3032 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3033 SDValue Res;
3034
3035 // When generating execute-only code Constant Pools must be promoted to the
3036 // global data section. It's a bit ugly that we can't share them across basic
3037 // blocks, but this way we guarantee that execute-only behaves correct with
3038 // position-independent addressing modes.
3039 if (Subtarget->genExecuteOnly()) {
3040 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3041 auto T = const_cast<Type*>(CP->getType());
3042 auto C = const_cast<Constant*>(CP->getConstVal());
3043 auto M = const_cast<Module*>(DAG.getMachineFunction().
3044 getFunction().getParent());
3045 auto GV = new GlobalVariable(
3046 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3047 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3048 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3049 Twine(AFI->createPICLabelUId())
3050 );
3051 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3052 dl, PtrVT);
3053 return LowerGlobalAddress(GA, DAG);
3054 }
3055
3056 if (CP->isMachineConstantPoolEntry())
3057 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
3058 CP->getAlignment());
3059 else
3060 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
3061 CP->getAlignment());
3062 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3063}
3064
3065unsigned ARMTargetLowering::getJumpTableEncoding() const {
3066 return MachineJumpTableInfo::EK_Inline;
3067}
3068
3069SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3070 SelectionDAG &DAG) const {
3071 MachineFunction &MF = DAG.getMachineFunction();
3072 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3073 unsigned ARMPCLabelIndex = 0;
3074 SDLoc DL(Op);
3075 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3076 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3077 SDValue CPAddr;
3078 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3079 if (!IsPositionIndependent) {
3080 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
3081 } else {
3082 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3083 ARMPCLabelIndex = AFI->createPICLabelUId();
3084 ARMConstantPoolValue *CPV =
3085 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3086 ARMCP::CPBlockAddress, PCAdj);
3087 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3088 }
3089 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3090 SDValue Result = DAG.getLoad(
3091 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3092 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3093 if (!IsPositionIndependent)
3094 return Result;
3095 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3096 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3097}
3098
3099/// Convert a TLS address reference into the correct sequence of loads
3100/// and calls to compute the variable's address for Darwin, and return an
3101/// SDValue containing the final node.
3102
3103/// Darwin only has one TLS scheme which must be capable of dealing with the
3104/// fully general situation, in the worst case. This means:
3105/// + "extern __thread" declaration.
3106/// + Defined in a possibly unknown dynamic library.
3107///
3108/// The general system is that each __thread variable has a [3 x i32] descriptor
3109/// which contains information used by the runtime to calculate the address. The
3110/// only part of this the compiler needs to know about is the first word, which
3111/// contains a function pointer that must be called with the address of the
3112/// entire descriptor in "r0".
3113///
3114/// Since this descriptor may be in a different unit, in general access must
3115/// proceed along the usual ARM rules. A common sequence to produce is:
3116///
3117/// movw rT1, :lower16:_var$non_lazy_ptr
3118/// movt rT1, :upper16:_var$non_lazy_ptr
3119/// ldr r0, [rT1]
3120/// ldr rT2, [r0]
3121/// blx rT2
3122/// [...address now in r0...]
3123SDValue
3124ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3125 SelectionDAG &DAG) const {
3126 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3127, __PRETTY_FUNCTION__))
3127 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3127, __PRETTY_FUNCTION__))
;
3128 SDLoc DL(Op);
3129
3130 // First step is to get the address of the actua global symbol. This is where
3131 // the TLS descriptor lives.
3132 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3133
3134 // The first entry in the descriptor is a function pointer that we must call
3135 // to obtain the address of the variable.
3136 SDValue Chain = DAG.getEntryNode();
3137 SDValue FuncTLVGet = DAG.getLoad(
3138 MVT::i32, DL, Chain, DescAddr,
3139 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
3140 /* Alignment = */ 4,
3141 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3142 MachineMemOperand::MOInvariant);
3143 Chain = FuncTLVGet.getValue(1);
3144
3145 MachineFunction &F = DAG.getMachineFunction();
3146 MachineFrameInfo &MFI = F.getFrameInfo();
3147 MFI.setAdjustsStack(true);
3148
3149 // TLS calls preserve all registers except those that absolutely must be
3150 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3151 // silly).
3152 auto TRI =
3153 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3154 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3155 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3156
3157 // Finally, we can make the call. This is just a degenerate version of a
3158 // normal AArch64 call node: r0 takes the address of the descriptor, and
3159 // returns the address of the variable in this thread.
3160 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3161 Chain =
3162 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3163 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3164 DAG.getRegisterMask(Mask), Chain.getValue(1));
3165 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3166}
3167
3168SDValue
3169ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3170 SelectionDAG &DAG) const {
3171 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3171, __PRETTY_FUNCTION__))
;
3172
3173 SDValue Chain = DAG.getEntryNode();
3174 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3175 SDLoc DL(Op);
3176
3177 // Load the current TEB (thread environment block)
3178 SDValue Ops[] = {Chain,
3179 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3180 DAG.getTargetConstant(15, DL, MVT::i32),
3181 DAG.getTargetConstant(0, DL, MVT::i32),
3182 DAG.getTargetConstant(13, DL, MVT::i32),
3183 DAG.getTargetConstant(0, DL, MVT::i32),
3184 DAG.getTargetConstant(2, DL, MVT::i32)};
3185 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3186 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3187
3188 SDValue TEB = CurrentTEB.getValue(0);
3189 Chain = CurrentTEB.getValue(1);
3190
3191 // Load the ThreadLocalStoragePointer from the TEB
3192 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3193 SDValue TLSArray =
3194 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3195 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3196
3197 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3198 // offset into the TLSArray.
3199
3200 // Load the TLS index from the C runtime
3201 SDValue TLSIndex =
3202 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3203 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3204 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3205
3206 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3207 DAG.getConstant(2, DL, MVT::i32));
3208 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3209 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3210 MachinePointerInfo());
3211
3212 // Get the offset of the start of the .tls section (section base)
3213 const auto *GA = cast<GlobalAddressSDNode>(Op);
3214 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3215 SDValue Offset = DAG.getLoad(
3216 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3217 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
3218 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3219
3220 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3221}
3222
3223// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3224SDValue
3225ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3226 SelectionDAG &DAG) const {
3227 SDLoc dl(GA);
3228 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3229 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3230 MachineFunction &MF = DAG.getMachineFunction();
3231 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3232 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3233 ARMConstantPoolValue *CPV =
3234 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3235 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3236 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3237 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3238 Argument = DAG.getLoad(
3239 PtrVT, dl, DAG.getEntryNode(), Argument,
3240 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3241 SDValue Chain = Argument.getValue(1);
3242
3243 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3244 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3245
3246 // call __tls_get_addr.
3247 ArgListTy Args;
3248 ArgListEntry Entry;
3249 Entry.Node = Argument;
3250 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3251 Args.push_back(Entry);
3252
3253 // FIXME: is there useful debug info available here?
3254 TargetLowering::CallLoweringInfo CLI(DAG);
3255 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3256 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3257 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3258
3259 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3260 return CallResult.first;
3261}
3262
3263// Lower ISD::GlobalTLSAddress using the "initial exec" or
3264// "local exec" model.
3265SDValue
3266ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3267 SelectionDAG &DAG,
3268 TLSModel::Model model) const {
3269 const GlobalValue *GV = GA->getGlobal();
3270 SDLoc dl(GA);
3271 SDValue Offset;
3272 SDValue Chain = DAG.getEntryNode();
3273 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3274 // Get the Thread Pointer
3275 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3276
3277 if (model == TLSModel::InitialExec) {
3278 MachineFunction &MF = DAG.getMachineFunction();
3279 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3280 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3281 // Initial exec model.
3282 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3283 ARMConstantPoolValue *CPV =
3284 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3285 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3286 true);
3287 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3288 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3289 Offset = DAG.getLoad(
3290 PtrVT, dl, Chain, Offset,
3291 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3292 Chain = Offset.getValue(1);
3293
3294 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3295 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3296
3297 Offset = DAG.getLoad(
3298 PtrVT, dl, Chain, Offset,
3299 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3300 } else {
3301 // local exec model
3302 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3302, __PRETTY_FUNCTION__))
;
3303 ARMConstantPoolValue *CPV =
3304 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3305 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3306 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3307 Offset = DAG.getLoad(
3308 PtrVT, dl, Chain, Offset,
3309 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3310 }
3311
3312 // The address of the thread local variable is the add of the thread
3313 // pointer with the offset of the variable.
3314 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3315}
3316
3317SDValue
3318ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3319 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3320 if (DAG.getTarget().useEmulatedTLS())
3321 return LowerToTLSEmulatedModel(GA, DAG);
3322
3323 if (Subtarget->isTargetDarwin())
3324 return LowerGlobalTLSAddressDarwin(Op, DAG);
3325
3326 if (Subtarget->isTargetWindows())
3327 return LowerGlobalTLSAddressWindows(Op, DAG);
3328
3329 // TODO: implement the "local dynamic" model
3330 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3330, __PRETTY_FUNCTION__))
;
3331 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3332
3333 switch (model) {
3334 case TLSModel::GeneralDynamic:
3335 case TLSModel::LocalDynamic:
3336 return LowerToTLSGeneralDynamicModel(GA, DAG);
3337 case TLSModel::InitialExec:
3338 case TLSModel::LocalExec:
3339 return LowerToTLSExecModels(GA, DAG, model);
3340 }
3341 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3341)
;
3342}
3343
3344/// Return true if all users of V are within function F, looking through
3345/// ConstantExprs.
3346static bool allUsersAreInFunction(const Value *V, const Function *F) {
3347 SmallVector<const User*,4> Worklist;
3348 for (auto *U : V->users())
3349 Worklist.push_back(U);
3350 while (!Worklist.empty()) {
3351 auto *U = Worklist.pop_back_val();
3352 if (isa<ConstantExpr>(U)) {
3353 for (auto *UU : U->users())
3354 Worklist.push_back(UU);
3355 continue;
3356 }
3357
3358 auto *I = dyn_cast<Instruction>(U);
3359 if (!I || I->getParent()->getParent() != F)
3360 return false;
3361 }
3362 return true;
3363}
3364
3365static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3366 const GlobalValue *GV, SelectionDAG &DAG,
3367 EVT PtrVT, const SDLoc &dl) {
3368 // If we're creating a pool entry for a constant global with unnamed address,
3369 // and the global is small enough, we can emit it inline into the constant pool
3370 // to save ourselves an indirection.
3371 //
3372 // This is a win if the constant is only used in one function (so it doesn't
3373 // need to be duplicated) or duplicating the constant wouldn't increase code
3374 // size (implying the constant is no larger than 4 bytes).
3375 const Function &F = DAG.getMachineFunction().getFunction();
3376
3377 // We rely on this decision to inline being idemopotent and unrelated to the
3378 // use-site. We know that if we inline a variable at one use site, we'll
3379 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3380 // doesn't know about this optimization, so bail out if it's enabled else
3381 // we could decide to inline here (and thus never emit the GV) but require
3382 // the GV from fast-isel generated code.
3383 if (!EnableConstpoolPromotion ||
3384 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3385 return SDValue();
3386
3387 auto *GVar = dyn_cast<GlobalVariable>(GV);
3388 if (!GVar || !GVar->hasInitializer() ||
3389 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3390 !GVar->hasLocalLinkage())
3391 return SDValue();
3392
3393 // If we inline a value that contains relocations, we move the relocations
3394 // from .data to .text. This is not allowed in position-independent code.
3395 auto *Init = GVar->getInitializer();
3396 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3397 Init->needsRelocation())
3398 return SDValue();
3399
3400 // The constant islands pass can only really deal with alignment requests
3401 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3402 // any type wanting greater alignment requirements than 4 bytes. We also
3403 // can only promote constants that are multiples of 4 bytes in size or
3404 // are paddable to a multiple of 4. Currently we only try and pad constants
3405 // that are strings for simplicity.
3406 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3407 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3408 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3409 unsigned RequiredPadding = 4 - (Size % 4);
3410 bool PaddingPossible =
3411 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3412 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3413 Size == 0)
3414 return SDValue();
3415
3416 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3417 MachineFunction &MF = DAG.getMachineFunction();
3418 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3419
3420 // We can't bloat the constant pool too much, else the ConstantIslands pass
3421 // may fail to converge. If we haven't promoted this global yet (it may have
3422 // multiple uses), and promoting it would increase the constant pool size (Sz
3423 // > 4), ensure we have space to do so up to MaxTotal.
3424 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3425 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3426 ConstpoolPromotionMaxTotal)
3427 return SDValue();
3428
3429 // This is only valid if all users are in a single function; we can't clone
3430 // the constant in general. The LLVM IR unnamed_addr allows merging
3431 // constants, but not cloning them.
3432 //
3433 // We could potentially allow cloning if we could prove all uses of the
3434 // constant in the current function don't care about the address, like
3435 // printf format strings. But that isn't implemented for now.
3436 if (!allUsersAreInFunction(GVar, &F))
3437 return SDValue();
3438
3439 // We're going to inline this global. Pad it out if needed.
3440 if (RequiredPadding != 4) {
3441 StringRef S = CDAInit->getAsString();
3442
3443 SmallVector<uint8_t,16> V(S.size());
3444 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3445 while (RequiredPadding--)
3446 V.push_back(0);
3447 Init = ConstantDataArray::get(*DAG.getContext(), V);
3448 }
3449
3450 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3451 SDValue CPAddr =
3452 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3453 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3454 AFI->markGlobalAsPromotedToConstantPool(GVar);
3455 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3456 PaddedSize - 4);
3457 }
3458 ++NumConstpoolPromoted;
3459 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3460}
3461
3462bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3463 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3464 if (!(GV = GA->getBaseObject()))
3465 return false;
3466 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3467 return V->isConstant();
3468 return isa<Function>(GV);
3469}
3470
3471SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3472 SelectionDAG &DAG) const {
3473 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3474 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3474)
;
3475 case Triple::COFF:
3476 return LowerGlobalAddressWindows(Op, DAG);
3477 case Triple::ELF:
3478 return LowerGlobalAddressELF(Op, DAG);
3479 case Triple::MachO:
3480 return LowerGlobalAddressDarwin(Op, DAG);
3481 }
3482}
3483
3484SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3485 SelectionDAG &DAG) const {
3486 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3487 SDLoc dl(Op);
3488 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3489 const TargetMachine &TM = getTargetMachine();
3490 bool IsRO = isReadOnly(GV);
3491
3492 // promoteToConstantPool only if not generating XO text section
3493 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3494 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3495 return V;
3496
3497 if (isPositionIndependent()) {
3498 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3499 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3500 UseGOT_PREL ? ARMII::MO_GOT : 0);
3501 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3502 if (UseGOT_PREL)
3503 Result =
3504 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3505 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3506 return Result;
3507 } else if (Subtarget->isROPI() && IsRO) {
3508 // PC-relative.
3509 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3510 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3511 return Result;
3512 } else if (Subtarget->isRWPI() && !IsRO) {
3513 // SB-relative.
3514 SDValue RelAddr;
3515 if (Subtarget->useMovt()) {
3516 ++NumMovwMovt;
3517 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3518 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3519 } else { // use literal pool for address constant
3520 ARMConstantPoolValue *CPV =
3521 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3522 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3523 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3524 RelAddr = DAG.getLoad(
3525 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3526 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3527 }
3528 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3529 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3530 return Result;
3531 }
3532
3533 // If we have T2 ops, we can materialize the address directly via movt/movw
3534 // pair. This is always cheaper.
3535 if (Subtarget->useMovt()) {
3536 ++NumMovwMovt;
3537 // FIXME: Once remat is capable of dealing with instructions with register
3538 // operands, expand this into two nodes.
3539 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3540 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3541 } else {
3542 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3543 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3544 return DAG.getLoad(
3545 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3546 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3547 }
3548}
3549
3550SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3551 SelectionDAG &DAG) const {
3552 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3553, __PRETTY_FUNCTION__))
3553 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3553, __PRETTY_FUNCTION__))
;
3554 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3555 SDLoc dl(Op);
3556 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3557
3558 if (Subtarget->useMovt())
3559 ++NumMovwMovt;
3560
3561 // FIXME: Once remat is capable of dealing with instructions with register
3562 // operands, expand this into multiple nodes
3563 unsigned Wrapper =
3564 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3565
3566 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3567 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3568
3569 if (Subtarget->isGVIndirectSymbol(GV))
3570 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3571 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3572 return Result;
3573}
3574
3575SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3576 SelectionDAG &DAG) const {
3577 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3577, __PRETTY_FUNCTION__))
;
3578 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3579, __PRETTY_FUNCTION__))
3579 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3579, __PRETTY_FUNCTION__))
;
3580 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3581, __PRETTY_FUNCTION__))
3581 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3581, __PRETTY_FUNCTION__))
;
3582
3583 const TargetMachine &TM = getTargetMachine();
3584 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3585 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3586 if (GV->hasDLLImportStorageClass())
3587 TargetFlags = ARMII::MO_DLLIMPORT;
3588 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3589 TargetFlags = ARMII::MO_COFFSTUB;
3590 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3591 SDValue Result;
3592 SDLoc DL(Op);
3593
3594 ++NumMovwMovt;
3595
3596 // FIXME: Once remat is capable of dealing with instructions with register
3597 // operands, expand this into two nodes.
3598 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3599 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3600 TargetFlags));
3601 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3602 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3603 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3604 return Result;
3605}
3606
3607SDValue
3608ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3609 SDLoc dl(Op);
3610 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3611 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3612 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3613 Op.getOperand(1), Val);
3614}
3615
3616SDValue
3617ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3618 SDLoc dl(Op);
3619 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3620 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3621}
3622
3623SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3624 SelectionDAG &DAG) const {
3625 SDLoc dl(Op);
3626 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3627 Op.getOperand(0));
3628}
3629
3630SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3631 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3632 unsigned IntNo =
3633 cast<ConstantSDNode>(
3634 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3635 ->getZExtValue();
3636 switch (IntNo) {
3637 default:
3638 return SDValue(); // Don't custom lower most intrinsics.
3639 case Intrinsic::arm_gnu_eabi_mcount: {
3640 MachineFunction &MF = DAG.getMachineFunction();
3641 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3642 SDLoc dl(Op);
3643 SDValue Chain = Op.getOperand(0);
3644 // call "\01__gnu_mcount_nc"
3645 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3646 const uint32_t *Mask =
3647 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3648 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3648, __PRETTY_FUNCTION__))
;
3649 // Mark LR an implicit live-in.
3650 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3651 SDValue ReturnAddress =
3652 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3653 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3654 SDValue Callee =
3655 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3656 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3657 if (Subtarget->isThumb())
3658 return SDValue(
3659 DAG.getMachineNode(
3660 ARM::tBL_PUSHLR, dl, ResultTys,
3661 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3662 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3663 0);
3664 return SDValue(
3665 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3666 {ReturnAddress, Callee, RegisterMask, Chain}),
3667 0);
3668 }
3669 }
3670}
3671
3672SDValue
3673ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3674 const ARMSubtarget *Subtarget) const {
3675 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3676 SDLoc dl(Op);
3677 switch (IntNo) {
3678 default: return SDValue(); // Don't custom lower most intrinsics.
3679 case Intrinsic::thread_pointer: {
3680 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3681 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3682 }
3683 case Intrinsic::arm_cls: {
3684 const SDValue &Operand = Op.getOperand(1);
3685 const EVT VTy = Op.getValueType();
3686 SDValue SRA =
3687 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3688 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3689 SDValue SHL =
3690 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3691 SDValue OR =
3692 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3693 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3694 return Result;
3695 }
3696 case Intrinsic::arm_cls64: {
3697 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3698 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3699 const SDValue &Operand = Op.getOperand(1);
3700 const EVT VTy = Op.getValueType();
3701
3702 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3703 DAG.getConstant(1, dl, VTy));
3704 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3705 DAG.getConstant(0, dl, VTy));
3706 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3707 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3708 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3709 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3710 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3711 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3712 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3713 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3714 SDValue CheckLo =
3715 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3716 SDValue HiIsZero =
3717 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3718 SDValue AdjustedLo =
3719 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3720 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3721 SDValue Result =
3722 DAG.getSelect(dl, VTy, CheckLo,
3723 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3724 return Result;
3725 }
3726 case Intrinsic::eh_sjlj_lsda: {
3727 MachineFunction &MF = DAG.getMachineFunction();
3728 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3729 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3730 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3731 SDValue CPAddr;
3732 bool IsPositionIndependent = isPositionIndependent();
3733 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3734 ARMConstantPoolValue *CPV =
3735 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3736 ARMCP::CPLSDA, PCAdj);
3737 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3738 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3739 SDValue Result = DAG.getLoad(
3740 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3741 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3742
3743 if (IsPositionIndependent) {
3744 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3745 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3746 }
3747 return Result;
3748 }
3749 case Intrinsic::arm_neon_vabs:
3750 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3751 Op.getOperand(1));
3752 case Intrinsic::arm_neon_vmulls:
3753 case Intrinsic::arm_neon_vmullu: {
3754 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3755 ? ARMISD::VMULLs : ARMISD::VMULLu;
3756 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3757 Op.getOperand(1), Op.getOperand(2));
3758 }
3759 case Intrinsic::arm_neon_vminnm:
3760 case Intrinsic::arm_neon_vmaxnm: {
3761 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3762 ? ISD::FMINNUM : ISD::FMAXNUM;
3763 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3764 Op.getOperand(1), Op.getOperand(2));
3765 }
3766 case Intrinsic::arm_neon_vminu:
3767 case Intrinsic::arm_neon_vmaxu: {
3768 if (Op.getValueType().isFloatingPoint())
3769 return SDValue();
3770 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3771 ? ISD::UMIN : ISD::UMAX;
3772 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3773 Op.getOperand(1), Op.getOperand(2));
3774 }
3775 case Intrinsic::arm_neon_vmins:
3776 case Intrinsic::arm_neon_vmaxs: {
3777 // v{min,max}s is overloaded between signed integers and floats.
3778 if (!Op.getValueType().isFloatingPoint()) {
3779 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3780 ? ISD::SMIN : ISD::SMAX;
3781 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3782 Op.getOperand(1), Op.getOperand(2));
3783 }
3784 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3785 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3786 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3787 Op.getOperand(1), Op.getOperand(2));
3788 }
3789 case Intrinsic::arm_neon_vtbl1:
3790 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3791 Op.getOperand(1), Op.getOperand(2));
3792 case Intrinsic::arm_neon_vtbl2:
3793 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3794 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3795 case Intrinsic::arm_mve_pred_i2v:
3796 case Intrinsic::arm_mve_pred_v2i:
3797 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
3798 Op.getOperand(1));
3799 case Intrinsic::arm_mve_vreinterpretq:
3800 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
3801 Op.getOperand(1));
3802 }
3803}
3804
3805static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3806 const ARMSubtarget *Subtarget) {
3807 SDLoc dl(Op);
3808 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3809 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3810 if (SSID == SyncScope::SingleThread)
3811 return Op;
3812
3813 if (!Subtarget->hasDataBarrier()) {
3814 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3815 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3816 // here.
3817 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3818, __PRETTY_FUNCTION__))
3818 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3818, __PRETTY_FUNCTION__))
;
3819 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3820 DAG.getConstant(0, dl, MVT::i32));
3821 }
3822
3823 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3824 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3825 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3826 if (Subtarget->isMClass()) {
3827 // Only a full system barrier exists in the M-class architectures.
3828 Domain = ARM_MB::SY;
3829 } else if (Subtarget->preferISHSTBarriers() &&
3830 Ord == AtomicOrdering::Release) {
3831 // Swift happens to implement ISHST barriers in a way that's compatible with
3832 // Release semantics but weaker than ISH so we'd be fools not to use
3833 // it. Beware: other processors probably don't!
3834 Domain = ARM_MB::ISHST;
3835 }
3836
3837 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3838 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3839 DAG.getConstant(Domain, dl, MVT::i32));
3840}
3841
3842static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3843 const ARMSubtarget *Subtarget) {
3844 // ARM pre v5TE and Thumb1 does not have preload instructions.
3845 if (!(Subtarget->isThumb2() ||
3846 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3847 // Just preserve the chain.
3848 return Op.getOperand(0);
3849
3850 SDLoc dl(Op);
3851 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3852 if (!isRead &&
3853 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3854 // ARMv7 with MP extension has PLDW.
3855 return Op.getOperand(0);
3856
3857 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3858 if (Subtarget->isThumb()) {
3859 // Invert the bits.
3860 isRead = ~isRead & 1;
3861 isData = ~isData & 1;
3862 }
3863
3864 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3865 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3866 DAG.getConstant(isData, dl, MVT::i32));
3867}
3868
3869static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3870 MachineFunction &MF = DAG.getMachineFunction();
3871 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3872
3873 // vastart just stores the address of the VarArgsFrameIndex slot into the
3874 // memory location argument.
3875 SDLoc dl(Op);
3876 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3877 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3878 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3879 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3880 MachinePointerInfo(SV));
3881}
3882
3883SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3884 CCValAssign &NextVA,
3885 SDValue &Root,
3886 SelectionDAG &DAG,
3887 const SDLoc &dl) const {
3888 MachineFunction &MF = DAG.getMachineFunction();
3889 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3890
3891 const TargetRegisterClass *RC;
3892 if (AFI->isThumb1OnlyFunction())
3893 RC = &ARM::tGPRRegClass;
3894 else
3895 RC = &ARM::GPRRegClass;
3896
3897 // Transform the arguments stored in physical registers into virtual ones.
3898 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3899 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3900
3901 SDValue ArgValue2;
3902 if (NextVA.isMemLoc()) {
3903 MachineFrameInfo &MFI = MF.getFrameInfo();
3904 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3905
3906 // Create load node to retrieve arguments from the stack.
3907 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3908 ArgValue2 = DAG.getLoad(
3909 MVT::i32, dl, Root, FIN,
3910 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3911 } else {
3912 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3913 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3914 }
3915 if (!Subtarget->isLittle())
3916 std::swap (ArgValue, ArgValue2);
3917 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3918}
3919
3920// The remaining GPRs hold either the beginning of variable-argument
3921// data, or the beginning of an aggregate passed by value (usually
3922// byval). Either way, we allocate stack slots adjacent to the data
3923// provided by our caller, and store the unallocated registers there.
3924// If this is a variadic function, the va_list pointer will begin with
3925// these values; otherwise, this reassembles a (byval) structure that
3926// was split between registers and memory.
3927// Return: The frame index registers were stored into.
3928int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3929 const SDLoc &dl, SDValue &Chain,
3930 const Value *OrigArg,
3931 unsigned InRegsParamRecordIdx,
3932 int ArgOffset, unsigned ArgSize) const {
3933 // Currently, two use-cases possible:
3934 // Case #1. Non-var-args function, and we meet first byval parameter.
3935 // Setup first unallocated register as first byval register;
3936 // eat all remained registers
3937 // (these two actions are performed by HandleByVal method).
3938 // Then, here, we initialize stack frame with
3939 // "store-reg" instructions.
3940 // Case #2. Var-args function, that doesn't contain byval parameters.
3941 // The same: eat all remained unallocated registers,
3942 // initialize stack frame.
3943
3944 MachineFunction &MF = DAG.getMachineFunction();
3945 MachineFrameInfo &MFI = MF.getFrameInfo();
3946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3947 unsigned RBegin, REnd;
3948 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3949 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3950 } else {
3951 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3952 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3953 REnd = ARM::R4;
3954 }
3955
3956 if (REnd != RBegin)
3957 ArgOffset = -4 * (ARM::R4 - RBegin);
3958
3959 auto PtrVT = getPointerTy(DAG.getDataLayout());
3960 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3961 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3962
3963 SmallVector<SDValue, 4> MemOps;
3964 const TargetRegisterClass *RC =
3965 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3966
3967 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3968 unsigned VReg = MF.addLiveIn(Reg, RC);
3969 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3970 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3971 MachinePointerInfo(OrigArg, 4 * i));
3972 MemOps.push_back(Store);
3973 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3974 }
3975
3976 if (!MemOps.empty())
3977 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3978 return FrameIndex;
3979}
3980
3981// Setup stack frame, the va_list pointer will start from.
3982void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3983 const SDLoc &dl, SDValue &Chain,
3984 unsigned ArgOffset,
3985 unsigned TotalArgRegsSaveSize,
3986 bool ForceMutable) const {
3987 MachineFunction &MF = DAG.getMachineFunction();
3988 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3989
3990 // Try to store any remaining integer argument regs
3991 // to their spots on the stack so that they may be loaded by dereferencing
3992 // the result of va_next.
3993 // If there is no regs to be stored, just point address after last
3994 // argument passed via stack.
3995 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3996 CCInfo.getInRegsParamsCount(),
3997 CCInfo.getNextStackOffset(),
3998 std::max(4U, TotalArgRegsSaveSize));
3999 AFI->setVarArgsFrameIndex(FrameIndex);
4000}
4001
4002SDValue ARMTargetLowering::LowerFormalArguments(
4003 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4004 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4005 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4006 MachineFunction &MF = DAG.getMachineFunction();
4007 MachineFrameInfo &MFI = MF.getFrameInfo();
4008
4009 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4010
4011 // Assign locations to all of the incoming arguments.
4012 SmallVector<CCValAssign, 16> ArgLocs;
4013 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4014 *DAG.getContext());
4015 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4016
4017 SmallVector<SDValue, 16> ArgValues;
4018 SDValue ArgValue;
4019 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4020 unsigned CurArgIdx = 0;
4021
4022 // Initially ArgRegsSaveSize is zero.
4023 // Then we increase this value each time we meet byval parameter.
4024 // We also increase this value in case of varargs function.
4025 AFI->setArgRegsSaveSize(0);
4026
4027 // Calculate the amount of stack space that we need to allocate to store
4028 // byval and variadic arguments that are passed in registers.
4029 // We need to know this before we allocate the first byval or variadic
4030 // argument, as they will be allocated a stack slot below the CFA (Canonical
4031 // Frame Address, the stack pointer at entry to the function).
4032 unsigned ArgRegBegin = ARM::R4;
4033 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4034 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4035 break;
4036
4037 CCValAssign &VA = ArgLocs[i];
4038 unsigned Index = VA.getValNo();
4039 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4040 if (!Flags.isByVal())
4041 continue;
4042
4043 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4043, __PRETTY_FUNCTION__))
;
4044 unsigned RBegin, REnd;
4045 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4046 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4047
4048 CCInfo.nextInRegsParam();
4049 }
4050 CCInfo.rewindByValRegsInfo();
4051
4052 int lastInsIndex = -1;
4053 if (isVarArg && MFI.hasVAStart()) {
4054 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4055 if (RegIdx != array_lengthof(GPRArgRegs))
4056 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4057 }
4058
4059 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4060 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4061 auto PtrVT = getPointerTy(DAG.getDataLayout());
4062
4063 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4064 CCValAssign &VA = ArgLocs[i];
4065 if (Ins[VA.getValNo()].isOrigArg()) {
4066 std::advance(CurOrigArg,
4067 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4068 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4069 }
4070 // Arguments stored in registers.
4071 if (VA.isRegLoc()) {
4072 EVT RegVT = VA.getLocVT();
4073
4074 if (VA.needsCustom()) {
4075 // f64 and vector types are split up into multiple registers or
4076 // combinations of registers and stack slots.
4077 if (VA.getLocVT() == MVT::v2f64) {
4078 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
4079 Chain, DAG, dl);
4080 VA = ArgLocs[++i]; // skip ahead to next loc
4081 SDValue ArgValue2;
4082 if (VA.isMemLoc()) {
4083 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4084 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4085 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
4086 MachinePointerInfo::getFixedStack(
4087 DAG.getMachineFunction(), FI));
4088 } else {
4089 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
4090 Chain, DAG, dl);
4091 }
4092 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4093 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4094 ArgValue, ArgValue1,
4095 DAG.getIntPtrConstant(0, dl));
4096 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4097 ArgValue, ArgValue2,
4098 DAG.getIntPtrConstant(1, dl));
4099 } else
4100 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4101 } else {
4102 const TargetRegisterClass *RC;
4103
4104
4105 if (RegVT == MVT::f16)
4106 RC = &ARM::HPRRegClass;
4107 else if (RegVT == MVT::f32)
4108 RC = &ARM::SPRRegClass;
4109 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
4110 RC = &ARM::DPRRegClass;
4111 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
4112 RC = &ARM::QPRRegClass;
4113 else if (RegVT == MVT::i32)
4114 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4115 : &ARM::GPRRegClass;
4116 else
4117 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4117)
;
4118
4119 // Transform the arguments in physical registers into virtual ones.
4120 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4121 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4122
4123 // If this value is passed in r0 and has the returned attribute (e.g.
4124 // C++ 'structors), record this fact for later use.
4125 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4126 AFI->setPreservesR0();
4127 }
4128 }
4129
4130 // If this is an 8 or 16-bit value, it is really passed promoted
4131 // to 32 bits. Insert an assert[sz]ext to capture this, then
4132 // truncate to the right size.
4133 switch (VA.getLocInfo()) {
4134 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4134)
;
4135 case CCValAssign::Full: break;
4136 case CCValAssign::BCvt:
4137 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4138 break;
4139 case CCValAssign::SExt:
4140 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4141 DAG.getValueType(VA.getValVT()));
4142 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4143 break;
4144 case CCValAssign::ZExt:
4145 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4146 DAG.getValueType(VA.getValVT()));
4147 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4148 break;
4149 }
4150
4151 InVals.push_back(ArgValue);
4152 } else { // VA.isRegLoc()
4153 // sanity check
4154 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4154, __PRETTY_FUNCTION__))
;
4155 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __PRETTY_FUNCTION__))
;
4156
4157 int index = VA.getValNo();
4158
4159 // Some Ins[] entries become multiple ArgLoc[] entries.
4160 // Process them only once.
4161 if (index != lastInsIndex)
4162 {
4163 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4164 // FIXME: For now, all byval parameter objects are marked mutable.
4165 // This can be changed with more analysis.
4166 // In case of tail call optimization mark all arguments mutable.
4167 // Since they could be overwritten by lowering of arguments in case of
4168 // a tail call.
4169 if (Flags.isByVal()) {
4170 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4171, __PRETTY_FUNCTION__))
4171 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4171, __PRETTY_FUNCTION__))
;
4172 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4173
4174 int FrameIndex = StoreByValRegs(
4175 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4176 VA.getLocMemOffset(), Flags.getByValSize());
4177 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4178 CCInfo.nextInRegsParam();
4179 } else {
4180 unsigned FIOffset = VA.getLocMemOffset();
4181 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4182 FIOffset, true);
4183
4184 // Create load nodes to retrieve arguments from the stack.
4185 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4186 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4187 MachinePointerInfo::getFixedStack(
4188 DAG.getMachineFunction(), FI)));
4189 }
4190 lastInsIndex = index;
4191 }
4192 }
4193 }
4194
4195 // varargs
4196 if (isVarArg && MFI.hasVAStart())
4197 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
4198 CCInfo.getNextStackOffset(),
4199 TotalArgRegsSaveSize);
4200
4201 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4202
4203 return Chain;
4204}
4205
4206/// isFloatingPointZero - Return true if this is +0.0.
4207static bool isFloatingPointZero(SDValue Op) {
4208 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4209 return CFP->getValueAPF().isPosZero();
4210 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4211 // Maybe this has already been legalized into the constant pool?
4212 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4213 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4214 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4215 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4216 return CFP->getValueAPF().isPosZero();
4217 }
4218 } else if (Op->getOpcode() == ISD::BITCAST &&
4219 Op->getValueType(0) == MVT::f64) {
4220 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4221 // created by LowerConstantFP().
4222 SDValue BitcastOp = Op->getOperand(0);
4223 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4224 isNullConstant(BitcastOp->getOperand(0)))
4225 return true;
4226 }
4227 return false;
4228}
4229
4230/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4231/// the given operands.
4232SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4233 SDValue &ARMcc, SelectionDAG &DAG,
4234 const SDLoc &dl) const {
4235 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4236 unsigned C = RHSC->getZExtValue();
4237 if (!isLegalICmpImmediate((int32_t)C)) {
4238 // Constant does not fit, try adjusting it by one.
4239 switch (CC) {
4240 default: break;
4241 case ISD::SETLT:
4242 case ISD::SETGE:
4243 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4244 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4245 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4246 }
4247 break;
4248 case ISD::SETULT:
4249 case ISD::SETUGE:
4250 if (C != 0 && isLegalICmpImmediate(C-1)) {
4251 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4252 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4253 }
4254 break;
4255 case ISD::SETLE:
4256 case ISD::SETGT:
4257 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4258 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4259 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4260 }
4261 break;
4262 case ISD::SETULE:
4263 case ISD::SETUGT:
4264 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4265 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4266 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4267 }
4268 break;
4269 }
4270 }
4271 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4272 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4273 // In ARM and Thumb-2, the compare instructions can shift their second
4274 // operand.
4275 CC = ISD::getSetCCSwappedOperands(CC);
4276 std::swap(LHS, RHS);
4277 }
4278
4279 // Thumb1 has very limited immediate modes, so turning an "and" into a
4280 // shift can save multiple instructions.
4281 //
4282 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4283 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4284 // own. If it's the operand to an unsigned comparison with an immediate,
4285 // we can eliminate one of the shifts: we transform
4286 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4287 //
4288 // We avoid transforming cases which aren't profitable due to encoding
4289 // details:
4290 //
4291 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4292 // would not; in that case, we're essentially trading one immediate load for
4293 // another.
4294 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4295 // 3. C2 is zero; we have other code for this special case.
4296 //
4297 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4298 // instruction, since the AND is always one instruction anyway, but we could
4299 // use narrow instructions in some cases.
4300 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4301 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4302 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4303 !isSignedIntSetCC(CC)) {
4304 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4305 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4306 uint64_t RHSV = RHSC->getZExtValue();
4307 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4308 unsigned ShiftBits = countLeadingZeros(Mask);
4309 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4310 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4311 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4312 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4313 }
4314 }
4315 }
4316
4317 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4318 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4319 // way a cmp would.
4320 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4321 // some tweaks to the heuristics for the previous and->shift transform.
4322 // FIXME: Optimize cases where the LHS isn't a shift.
4323 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4324 isa<ConstantSDNode>(RHS) &&
4325 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4326 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4327 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4328 unsigned ShiftAmt =
4329 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4330 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4331 DAG.getVTList(MVT::i32, MVT::i32),
4332 LHS.getOperand(0),
4333 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4334 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4335 Shift.getValue(1), SDValue());
4336 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4337 return Chain.getValue(1);
4338 }
4339
4340 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4341
4342 // If the RHS is a constant zero then the V (overflow) flag will never be
4343 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4344 // simpler for other passes (like the peephole optimiser) to deal with.
4345 if (isNullConstant(RHS)) {
4346 switch (CondCode) {
4347 default: break;
4348 case ARMCC::GE:
4349 CondCode = ARMCC::PL;
4350 break;
4351 case ARMCC::LT:
4352 CondCode = ARMCC::MI;
4353 break;
4354 }
4355 }
4356
4357 ARMISD::NodeType CompareType;
4358 switch (CondCode) {
4359 default:
4360 CompareType = ARMISD::CMP;
4361 break;
4362 case ARMCC::EQ:
4363 case ARMCC::NE:
4364 // Uses only Z Flag
4365 CompareType = ARMISD::CMPZ;
4366 break;
4367 }
4368 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4369 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4370}
4371
4372/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4373SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4374 SelectionDAG &DAG, const SDLoc &dl,
4375 bool Signaling) const {
4376 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4376, __PRETTY_FUNCTION__))
;
4377 SDValue Cmp;
4378 if (!isFloatingPointZero(RHS))
4379 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4380 dl, MVT::Glue, LHS, RHS);
4381 else
4382 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4383 dl, MVT::Glue, LHS);
4384 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4385}
4386
4387/// duplicateCmp - Glue values can have only one use, so this function
4388/// duplicates a comparison node.
4389SDValue
4390ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4391 unsigned Opc = Cmp.getOpcode();
4392 SDLoc DL(Cmp);
4393 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4394 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4395
4396 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4396, __PRETTY_FUNCTION__))
;
4397 Cmp = Cmp.getOperand(0);
4398 Opc = Cmp.getOpcode();
4399 if (Opc == ARMISD::CMPFP)
4400 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4401 else {
4402 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4402, __PRETTY_FUNCTION__))
;
4403 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4404 }
4405 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4406}
4407
4408// This function returns three things: the arithmetic computation itself
4409// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4410// comparison and the condition code define the case in which the arithmetic
4411// computation *does not* overflow.
4412std::pair<SDValue, SDValue>
4413ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4414 SDValue &ARMcc) const {
4415 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4415, __PRETTY_FUNCTION__))
;
4416
4417 SDValue Value, OverflowCmp;
4418 SDValue LHS = Op.getOperand(0);
4419 SDValue RHS = Op.getOperand(1);
4420 SDLoc dl(Op);
4421
4422 // FIXME: We are currently always generating CMPs because we don't support
4423 // generating CMN through the backend. This is not as good as the natural
4424 // CMP case because it causes a register dependency and cannot be folded
4425 // later.
4426
4427 switch (Op.getOpcode()) {
4428 default:
4429 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4429)
;
4430 case ISD::SADDO:
4431 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4432 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4433 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4434 break;
4435 case ISD::UADDO:
4436 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4437 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4438 // We do not use it in the USUBO case as Value may not be used.
4439 Value = DAG.getNode(ARMISD::ADDC, dl,
4440 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4441 .getValue(0);
4442 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4443 break;
4444 case ISD::SSUBO:
4445 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4446 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4447 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4448 break;
4449 case ISD::USUBO:
4450 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4451 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4452 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4453 break;
4454 case ISD::UMULO:
4455 // We generate a UMUL_LOHI and then check if the high word is 0.
4456 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4457 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4458 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4459 LHS, RHS);
4460 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4461 DAG.getConstant(0, dl, MVT::i32));
4462 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4463 break;
4464 case ISD::SMULO:
4465 // We generate a SMUL_LOHI and then check if all the bits of the high word
4466 // are the same as the sign bit of the low word.
4467 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4468 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4469 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4470 LHS, RHS);
4471 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4472 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4473 Value.getValue(0),
4474 DAG.getConstant(31, dl, MVT::i32)));
4475 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4476 break;
4477 } // switch (...)
4478
4479 return std::make_pair(Value, OverflowCmp);
4480}
4481
4482SDValue
4483ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4484 // Let legalize expand this if it isn't a legal type yet.
4485 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4486 return SDValue();
4487
4488 SDValue Value, OverflowCmp;
4489 SDValue ARMcc;
4490 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4491 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4492 SDLoc dl(Op);
4493 // We use 0 and 1 as false and true values.
4494 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4495 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4496 EVT VT = Op.getValueType();
4497
4498 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4499 ARMcc, CCR, OverflowCmp);
4500
4501 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4502 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4503}
4504
4505static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4506 SelectionDAG &DAG) {
4507 SDLoc DL(BoolCarry);
4508 EVT CarryVT = BoolCarry.getValueType();
4509
4510 // This converts the boolean value carry into the carry flag by doing
4511 // ARMISD::SUBC Carry, 1
4512 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4513 DAG.getVTList(CarryVT, MVT::i32),
4514 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4515 return Carry.getValue(1);
4516}
4517
4518static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4519 SelectionDAG &DAG) {
4520 SDLoc DL(Flags);
4521
4522 // Now convert the carry flag into a boolean carry. We do this
4523 // using ARMISD:ADDE 0, 0, Carry
4524 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4525 DAG.getConstant(0, DL, MVT::i32),
4526 DAG.getConstant(0, DL, MVT::i32), Flags);
4527}
4528
4529SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4530 SelectionDAG &DAG) const {
4531 // Let legalize expand this if it isn't a legal type yet.
4532 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4533 return SDValue();
4534
4535 SDValue LHS = Op.getOperand(0);
4536 SDValue RHS = Op.getOperand(1);
4537 SDLoc dl(Op);
4538
4539 EVT VT = Op.getValueType();
4540 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4541 SDValue Value;
4542 SDValue Overflow;
4543 switch (Op.getOpcode()) {
4544 default:
4545 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4545)
;
4546 case ISD::UADDO:
4547 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4548 // Convert the carry flag into a boolean value.
4549 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4550 break;
4551 case ISD::USUBO: {
4552 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4553 // Convert the carry flag into a boolean value.
4554 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4555 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4556 // value. So compute 1 - C.
4557 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4558 DAG.getConstant(1, dl, MVT::i32), Overflow);
4559 break;
4560 }
4561 }
4562
4563 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4564}
4565
4566static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4567 const ARMSubtarget *Subtarget) {
4568 EVT VT = Op.getValueType();
4569 if (!Subtarget->hasDSP())
4570 return SDValue();
4571 if (!VT.isSimple())
4572 return SDValue();
4573
4574 unsigned NewOpcode;
4575 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4576 switch (VT.getSimpleVT().SimpleTy) {
4577 default:
4578 return SDValue();
4579 case MVT::i8:
4580 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4581 break;
4582 case MVT::i16:
4583 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4584 break;
4585 }
4586
4587 SDLoc dl(Op);
4588 SDValue Add =
4589 DAG.getNode(NewOpcode, dl, MVT::i32,
4590 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4591 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4592 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4593}
4594
4595SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4596 SDValue Cond = Op.getOperand(0);
4597 SDValue SelectTrue = Op.getOperand(1);
4598 SDValue SelectFalse = Op.getOperand(2);
4599 SDLoc dl(Op);
4600 unsigned Opc = Cond.getOpcode();
4601
4602 if (Cond.getResNo() == 1 &&
4603 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4604 Opc == ISD::USUBO)) {
4605 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4606 return SDValue();
4607
4608 SDValue Value, OverflowCmp;
4609 SDValue ARMcc;
4610 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4611 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4612 EVT VT = Op.getValueType();
4613
4614 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4615 OverflowCmp, DAG);
4616 }
4617
4618 // Convert:
4619 //
4620 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4621 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4622 //
4623 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4624 const ConstantSDNode *CMOVTrue =
4625 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4626 const ConstantSDNode *CMOVFalse =
4627 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4628
4629 if (CMOVTrue && CMOVFalse) {
4630 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4631 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4632
4633 SDValue True;
4634 SDValue False;
4635 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4636 True = SelectTrue;
4637 False = SelectFalse;
4638 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4639 True = SelectFalse;
4640 False = SelectTrue;
4641 }
4642
4643 if (True.getNode() && False.getNode()) {
4644 EVT VT = Op.getValueType();
4645 SDValue ARMcc = Cond.getOperand(2);
4646 SDValue CCR = Cond.getOperand(3);
4647 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4648 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4648, __PRETTY_FUNCTION__))
;
4649 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4650 }
4651 }
4652 }
4653
4654 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4655 // undefined bits before doing a full-word comparison with zero.
4656 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4657 DAG.getConstant(1, dl, Cond.getValueType()));
4658
4659 return DAG.getSelectCC(dl, Cond,
4660 DAG.getConstant(0, dl, Cond.getValueType()),
4661 SelectTrue, SelectFalse, ISD::SETNE);
4662}
4663
4664static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4665 bool &swpCmpOps, bool &swpVselOps) {
4666 // Start by selecting the GE condition code for opcodes that return true for
4667 // 'equality'
4668 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4669 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4670 CondCode = ARMCC::GE;
4671
4672 // and GT for opcodes that return false for 'equality'.
4673 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4674 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4675 CondCode = ARMCC::GT;
4676
4677 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4678 // to swap the compare operands.
4679 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4680 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4681 swpCmpOps = true;
4682
4683 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4684 // If we have an unordered opcode, we need to swap the operands to the VSEL
4685 // instruction (effectively negating the condition).
4686 //
4687 // This also has the effect of swapping which one of 'less' or 'greater'
4688 // returns true, so we also swap the compare operands. It also switches
4689 // whether we return true for 'equality', so we compensate by picking the
4690 // opposite condition code to our original choice.
4691 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4692 CC == ISD::SETUGT) {
4693 swpCmpOps = !swpCmpOps;
4694 swpVselOps = !swpVselOps;
4695 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4696 }
4697
4698 // 'ordered' is 'anything but unordered', so use the VS condition code and
4699 // swap the VSEL operands.
4700 if (CC == ISD::SETO) {
4701 CondCode = ARMCC::VS;
4702 swpVselOps = true;
4703 }
4704
4705 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4706 // code and swap the VSEL operands. Also do this if we don't care about the
4707 // unordered case.
4708 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4709 CondCode = ARMCC::EQ;
4710 swpVselOps = true;
4711 }
4712}
4713
4714SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4715 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4716 SDValue Cmp, SelectionDAG &DAG) const {
4717 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4718 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4719 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4720 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4721 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4722
4723 SDValue TrueLow = TrueVal.getValue(0);
4724 SDValue TrueHigh = TrueVal.getValue(1);
4725 SDValue FalseLow = FalseVal.getValue(0);
4726 SDValue FalseHigh = FalseVal.getValue(1);
4727
4728 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4729 ARMcc, CCR, Cmp);
4730 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4731 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4732
4733 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4734 } else {
4735 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4736 Cmp);
4737 }
4738}
4739
4740static bool isGTorGE(ISD::CondCode CC) {
4741 return CC == ISD::SETGT || CC == ISD::SETGE;
4742}
4743
4744static bool isLTorLE(ISD::CondCode CC) {
4745 return CC == ISD::SETLT || CC == ISD::SETLE;
4746}
4747
4748// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4749// All of these conditions (and their <= and >= counterparts) will do:
4750// x < k ? k : x
4751// x > k ? x : k
4752// k < x ? x : k
4753// k > x ? k : x
4754static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4755 const SDValue TrueVal, const SDValue FalseVal,
4756 const ISD::CondCode CC, const SDValue K) {
4757 return (isGTorGE(CC) &&
4758 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4759 (isLTorLE(CC) &&
4760 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4761}
4762
4763// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4764static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4765 const SDValue TrueVal, const SDValue FalseVal,
4766 const ISD::CondCode CC, const SDValue K) {
4767 return (isGTorGE(CC) &&
4768 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4769 (isLTorLE(CC) &&
4770 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4771}
4772
4773// Check if two chained conditionals could be converted into SSAT or USAT.
4774//
4775// SSAT can replace a set of two conditional selectors that bound a number to an
4776// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4777//
4778// x < -k ? -k : (x > k ? k : x)
4779// x < -k ? -k : (x < k ? x : k)
4780// x > -k ? (x > k ? k : x) : -k
4781// x < k ? (x < -k ? -k : x) : k
4782// etc.
4783//
4784// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4785// a power of 2.
4786//
4787// It returns true if the conversion can be done, false otherwise.
4788// Additionally, the variable is returned in parameter V, the constant in K and
4789// usat is set to true if the conditional represents an unsigned saturation
4790static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4791 uint64_t &K, bool &usat) {
4792 SDValue LHS1 = Op.getOperand(0);
4793 SDValue RHS1 = Op.getOperand(1);
4794 SDValue TrueVal1 = Op.getOperand(2);
4795 SDValue FalseVal1 = Op.getOperand(3);
4796 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4797
4798 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4799 if (Op2.getOpcode() != ISD::SELECT_CC)
4800 return false;
4801
4802 SDValue LHS2 = Op2.getOperand(0);
4803 SDValue RHS2 = Op2.getOperand(1);
4804 SDValue TrueVal2 = Op2.getOperand(2);
4805 SDValue FalseVal2 = Op2.getOperand(3);
4806 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4807
4808 // Find out which are the constants and which are the variables
4809 // in each conditional
4810 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4811 ? &RHS1
4812 : nullptr;
4813 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4814 ? &RHS2
4815 : nullptr;
4816 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4817 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4818 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4819 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4820
4821 // We must detect cases where the original operations worked with 16- or
4822 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4823 // must work with sign-extended values but the select operations return
4824 // the original non-extended value.
4825 SDValue V2TmpReg = V2Tmp;
4826 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4827 V2TmpReg = V2Tmp->getOperand(0);
4828
4829 // Check that the registers and the constants have the correct values
4830 // in both conditionals
4831 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4832 V2TmpReg != V2)
4833 return false;
4834
4835 // Figure out which conditional is saturating the lower/upper bound.
4836 const SDValue *LowerCheckOp =
4837 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4838 ? &Op
4839 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4840 ? &Op2
4841 : nullptr;
4842 const SDValue *UpperCheckOp =
4843 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4844 ? &Op
4845 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4846 ? &Op2
4847 : nullptr;
4848
4849 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4850 return false;
4851
4852 // Check that the constant in the lower-bound check is
4853 // the opposite of the constant in the upper-bound check
4854 // in 1's complement.
4855 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4856 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4857 int64_t PosVal = std::max(Val1, Val2);
4858 int64_t NegVal = std::min(Val1, Val2);
4859
4860 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4861 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4862 isPowerOf2_64(PosVal + 1)) {
4863
4864 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4865 if (Val1 == ~Val2)
4866 usat = false;
4867 else if (NegVal == 0)
4868 usat = true;
4869 else
4870 return false;
4871
4872 V = V2;
4873 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4874
4875 return true;
4876 }
4877
4878 return false;
4879}
4880
4881// Check if a condition of the type x < k ? k : x can be converted into a
4882// bit operation instead of conditional moves.
4883// Currently this is allowed given:
4884// - The conditions and values match up
4885// - k is 0 or -1 (all ones)
4886// This function will not check the last condition, thats up to the caller
4887// It returns true if the transformation can be made, and in such case
4888// returns x in V, and k in SatK.
4889static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4890 SDValue &SatK)
4891{
4892 SDValue LHS = Op.getOperand(0);
4893 SDValue RHS = Op.getOperand(1);
4894 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4895 SDValue TrueVal = Op.getOperand(2);
4896 SDValue FalseVal = Op.getOperand(3);
4897
4898 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4899 ? &RHS
4900 : nullptr;
4901
4902 // No constant operation in comparison, early out
4903 if (!K)
4904 return false;
4905
4906 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4907 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4908 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4909
4910 // If the constant on left and right side, or variable on left and right,
4911 // does not match, early out
4912 if (*K != KTmp || V != VTmp)
4913 return false;
4914
4915 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4916 SatK = *K;
4917 return true;
4918 }
4919
4920 return false;
4921}
4922
4923bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
4924 if (VT == MVT::f32)
4925 return !Subtarget->hasVFP2Base();
4926 if (VT == MVT::f64)
4927 return !Subtarget->hasFP64();
4928 if (VT == MVT::f16)
4929 return !Subtarget->hasFullFP16();
4930 return false;
4931}
4932
4933SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4934 EVT VT = Op.getValueType();
4935 SDLoc dl(Op);
4936
4937 // Try to convert two saturating conditional selects into a single SSAT
4938 SDValue SatValue;
4939 uint64_t SatConstant;
4940 bool SatUSat;
4941 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4942 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4943 if (SatUSat)
4944 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4945 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4946 else
4947 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4948 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4949 }
4950
4951 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4952 // into more efficient bit operations, which is possible when k is 0 or -1
4953 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4954 // single instructions. On Thumb the shift and the bit operation will be two
4955 // instructions.
4956 // Only allow this transformation on full-width (32-bit) operations
4957 SDValue LowerSatConstant;
4958 if (VT == MVT::i32 &&
4959 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4960 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4961 DAG.getConstant(31, dl, VT));
4962 if (isNullConstant(LowerSatConstant)) {
4963 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4964 DAG.getAllOnesConstant(dl, VT));
4965 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4966 } else if (isAllOnesConstant(LowerSatConstant))
4967 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4968 }
4969
4970 SDValue LHS = Op.getOperand(0);
4971 SDValue RHS = Op.getOperand(1);
4972 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4973 SDValue TrueVal = Op.getOperand(2);
4974 SDValue FalseVal = Op.getOperand(3);
4975 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
4976 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
4977
4978 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
4979 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
4980 unsigned TVal = CTVal->getZExtValue();
4981 unsigned FVal = CFVal->getZExtValue();
4982 unsigned Opcode = 0;
4983
4984 if (TVal == ~FVal) {
4985 Opcode = ARMISD::CSINV;
4986 } else if (TVal == ~FVal + 1) {
4987 Opcode = ARMISD::CSNEG;
4988 } else if (TVal + 1 == FVal) {
4989 Opcode = ARMISD::CSINC;
4990 } else if (TVal == FVal + 1) {
4991 Opcode = ARMISD::CSINC;
4992 std::swap(TrueVal, FalseVal);
4993 std::swap(TVal, FVal);
4994 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4995 }
4996
4997 if (Opcode) {
4998 // If one of the constants is cheaper than another, materialise the
4999 // cheaper one and let the csel generate the other.
5000 if (Opcode != ARMISD::CSINC &&
5001 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5002 std::swap(TrueVal, FalseVal);
5003 std::swap(TVal, FVal);
5004 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5005 }
5006
5007 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5008 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5009 // -(-a) == a, but (a+1)+1 != a).
5010 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5011 std::swap(TrueVal, FalseVal);
5012 std::swap(TVal, FVal);
5013 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5014 }
5015 if (TVal == 0)
5016 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
5017
5018 // Drops F's value because we can get it by inverting/negating TVal.
5019 FalseVal = TrueVal;
5020
5021 SDValue ARMcc;
5022 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5023 EVT VT = TrueVal.getValueType();
5024 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5025 }
5026 }
5027
5028 if (isUnsupportedFloatingType(LHS.getValueType())) {
5029 DAG.getTargetLoweringInfo().softenSetCCOperands(
5030 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5031
5032 // If softenSetCCOperands only returned one value, we should compare it to
5033 // zero.
5034 if (!RHS.getNode()) {
5035 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5036 CC = ISD::SETNE;
5037 }
5038 }
5039
5040 if (LHS.getValueType() == MVT::i32) {
5041 // Try to generate VSEL on ARMv8.
5042 // The VSEL instruction can't use all the usual ARM condition
5043 // codes: it only has two bits to select the condition code, so it's
5044 // constrained to use only GE, GT, VS and EQ.
5045 //
5046 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5047 // swap the operands of the previous compare instruction (effectively
5048 // inverting the compare condition, swapping 'less' and 'greater') and
5049 // sometimes need to swap the operands to the VSEL (which inverts the
5050 // condition in the sense of firing whenever the previous condition didn't)
5051 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5052 TrueVal.getValueType() == MVT::f32 ||
5053 TrueVal.getValueType() == MVT::f64)) {
5054 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5055 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5056 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5057 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5058 std::swap(TrueVal, FalseVal);
5059 }
5060 }
5061
5062 SDValue ARMcc;
5063 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5064 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5065 // Choose GE over PL, which vsel does now support
5066 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5067 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5068 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5069 }
5070
5071 ARMCC::CondCodes CondCode, CondCode2;
5072 FPCCToARMCC(CC, CondCode, CondCode2);
5073
5074 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5075 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5076 // must use VSEL (limited condition codes), due to not having conditional f16
5077 // moves.
5078 if (Subtarget->hasFPARMv8Base() &&
5079 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5080 (TrueVal.getValueType() == MVT::f16 ||
5081 TrueVal.getValueType() == MVT::f32 ||
5082 TrueVal.getValueType() == MVT::f64)) {
5083 bool swpCmpOps = false;
5084 bool swpVselOps = false;
5085 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5086
5087 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5088 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5089 if (swpCmpOps)
5090 std::swap(LHS, RHS);
5091 if (swpVselOps)
5092 std::swap(TrueVal, FalseVal);
5093 }
5094 }
5095
5096 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5097 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5098 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5099 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5100 if (CondCode2 != ARMCC::AL) {
5101 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5102 // FIXME: Needs another CMP because flag can have but one use.
5103 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5104 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5105 }
5106 return Result;
5107}
5108
5109/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5110/// to morph to an integer compare sequence.
5111static bool canChangeToInt(SDValue Op, bool &SeenZero,
5112 const ARMSubtarget *Subtarget) {
5113 SDNode *N = Op.getNode();
5114 if (!N->hasOneUse())
5115 // Otherwise it requires moving the value from fp to integer registers.
5116 return false;
5117 if (!N->getNumValues())
5118 return false;
5119 EVT VT = Op.getValueType();
5120 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5121 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5122 // vmrs are very slow, e.g. cortex-a8.
5123 return false;
5124
5125 if (isFloatingPointZero(Op)) {
5126 SeenZero = true;
5127 return true;
5128 }
5129 return ISD::isNormalLoad(N);
5130}
5131
5132static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5133 if (isFloatingPointZero(Op))
5134 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5135
5136 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5137 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5138 Ld->getPointerInfo(), Ld->getAlignment(),
5139 Ld->getMemOperand()->getFlags());
5140
5141 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5141)
;
5142}
5143
5144static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5145 SDValue &RetVal1, SDValue &RetVal2) {
5146 SDLoc dl(Op);
5147
5148 if (isFloatingPointZero(Op)) {
5149 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5150 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5151 return;
5152 }
5153
5154 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5155 SDValue Ptr = Ld->getBasePtr();
5156 RetVal1 =
5157 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5158 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5159
5160 EVT PtrType = Ptr.getValueType();
5161 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5162 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5163 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5164 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5165 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5166 Ld->getMemOperand()->getFlags());
5167 return;
5168 }
5169
5170 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5170)
;
5171}
5172
5173/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5174/// f32 and even f64 comparisons to integer ones.
5175SDValue
5176ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5177 SDValue Chain = Op.getOperand(0);
5178 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5179 SDValue LHS = Op.getOperand(2);
5180 SDValue RHS = Op.getOperand(3);
5181 SDValue Dest = Op.getOperand(4);
5182 SDLoc dl(Op);
5183
5184 bool LHSSeenZero = false;
5185 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5186 bool RHSSeenZero = false;
5187 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5188 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5189 // If unsafe fp math optimization is enabled and there are no other uses of
5190 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5191 // to an integer comparison.
5192 if (CC == ISD::SETOEQ)
5193 CC = ISD::SETEQ;
5194 else if (CC == ISD::SETUNE)
5195 CC = ISD::SETNE;
5196
5197 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5198 SDValue ARMcc;
5199 if (LHS.getValueType() == MVT::f32) {
5200 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5201 bitcastf32Toi32(LHS, DAG), Mask);
5202 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5203 bitcastf32Toi32(RHS, DAG), Mask);
5204 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5205 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5206 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5207 Chain, Dest, ARMcc, CCR, Cmp);
5208 }
5209
5210 SDValue LHS1, LHS2;
5211 SDValue RHS1, RHS2;
5212 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5213 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5214 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5215 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5216 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5217 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5218 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5219 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5220 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5221 }
5222
5223 return SDValue();
5224}
5225
5226SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5227 SDValue Chain = Op.getOperand(0);
5228 SDValue Cond = Op.getOperand(1);
5229 SDValue Dest = Op.getOperand(2);
5230 SDLoc dl(Op);
5231
5232 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5233 // instruction.
5234 unsigned Opc = Cond.getOpcode();
5235 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5236 !Subtarget->isThumb1Only();
5237 if (Cond.getResNo() == 1 &&
5238 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5239 Opc == ISD::USUBO || OptimizeMul)) {
5240 // Only lower legal XALUO ops.
5241 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5242 return SDValue();
5243
5244 // The actual operation with overflow check.
5245 SDValue Value, OverflowCmp;
5246 SDValue ARMcc;
5247 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5248
5249 // Reverse the condition code.
5250 ARMCC::CondCodes CondCode =
5251 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5252 CondCode = ARMCC::getOppositeCondition(CondCode);
5253 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5254 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5255
5256 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5257 OverflowCmp);
5258 }
5259
5260 return SDValue();
5261}
5262
5263SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5264 SDValue Chain = Op.getOperand(0);
5265 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5266 SDValue LHS = Op.getOperand(2);
5267 SDValue RHS = Op.getOperand(3);
5268 SDValue Dest = Op.getOperand(4);
5269 SDLoc dl(Op);
5270
5271 if (isUnsupportedFloatingType(LHS.getValueType())) {
5272 DAG.getTargetLoweringInfo().softenSetCCOperands(
5273 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5274
5275 // If softenSetCCOperands only returned one value, we should compare it to
5276 // zero.
5277 if (!RHS.getNode()) {
5278 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5279 CC = ISD::SETNE;
5280 }
5281 }
5282
5283 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5284 // instruction.
5285 unsigned Opc = LHS.getOpcode();
5286 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5287 !Subtarget->isThumb1Only();
5288 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5289 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5290 Opc == ISD::USUBO || OptimizeMul) &&
5291 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5292 // Only lower legal XALUO ops.
5293 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5294 return SDValue();
5295
5296 // The actual operation with overflow check.
5297 SDValue Value, OverflowCmp;
5298 SDValue ARMcc;
5299 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5300
5301 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5302 // Reverse the condition code.
5303 ARMCC::CondCodes CondCode =
5304 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5305 CondCode = ARMCC::getOppositeCondition(CondCode);
5306 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5307 }
5308 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5309
5310 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5311 OverflowCmp);
5312 }
5313
5314 if (LHS.getValueType() == MVT::i32) {
5315 SDValue ARMcc;
5316 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5317 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5318 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5319 Chain, Dest, ARMcc, CCR, Cmp);
5320 }
5321
5322 if (getTargetMachine().Options.UnsafeFPMath &&
5323 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5324 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5325 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5326 return Result;
5327 }
5328
5329 ARMCC::CondCodes CondCode, CondCode2;
5330 FPCCToARMCC(CC, CondCode, CondCode2);
5331
5332 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5333 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5334 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5335 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5336 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5337 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5338 if (CondCode2 != ARMCC::AL) {
5339 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5340 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5341 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5342 }
5343 return Res;
5344}
5345
5346SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5347 SDValue Chain = Op.getOperand(0);
5348 SDValue Table = Op.getOperand(1);
5349 SDValue Index = Op.getOperand(2);
5350 SDLoc dl(Op);
5351
5352 EVT PTy = getPointerTy(DAG.getDataLayout());
5353 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5354 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5355 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5356 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5357 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5358 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5359 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5360 // which does another jump to the destination. This also makes it easier
5361 // to translate it to TBB / TBH later (Thumb2 only).
5362 // FIXME: This might not work if the function is extremely large.
5363 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5364 Addr, Op.getOperand(2), JTI);
5365 }
5366 if (isPositionIndependent() || Subtarget->isROPI()) {
5367 Addr =
5368 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5369 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5370 Chain = Addr.getValue(1);
5371 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5372 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5373 } else {
5374 Addr =
5375 DAG.getLoad(PTy, dl, Chain, Addr,
5376 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5377 Chain = Addr.getValue(1);
5378 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5379 }
5380}
5381
5382static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5383 EVT VT = Op.getValueType();
5384 SDLoc dl(Op);
5385
5386 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5387 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5388 return Op;
5389 return DAG.UnrollVectorOp(Op.getNode());
5390 }
5391
5392 const bool HasFullFP16 =
5393 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5394
5395 EVT NewTy;
5396 const EVT OpTy = Op.getOperand(0).getValueType();
5397 if (OpTy == MVT::v4f32)
5398 NewTy = MVT::v4i32;
5399 else if (OpTy == MVT::v4f16 && HasFullFP16)
5400 NewTy = MVT::v4i16;
5401 else if (OpTy == MVT::v8f16 && HasFullFP16)
5402 NewTy = MVT::v8i16;
5403 else
5404 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5404)
;
5405
5406 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5407 return DAG.UnrollVectorOp(Op.getNode());
5408
5409 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5410 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5411}
5412
5413SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5414 EVT VT = Op.getValueType();
5415 if (VT.isVector())
5416 return LowerVectorFP_TO_INT(Op, DAG);
5417
5418 bool IsStrict = Op->isStrictFPOpcode();
5419 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5420
5421 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5422 RTLIB::Libcall LC;
5423 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5424 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5425 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5426 Op.getValueType());
5427 else
5428 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5429 Op.getValueType());
5430 SDLoc Loc(Op);
5431 MakeLibCallOptions CallOptions;
5432 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5433 SDValue Result;
5434 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5435 CallOptions, Loc, Chain);
5436 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5437 }
5438
5439 // FIXME: Remove this when we have strict fp instruction selection patterns
5440 if (IsStrict) {
5441 SDLoc Loc(Op);
5442 SDValue Result =
5443 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5444 : ISD::FP_TO_UINT,
5445 Loc, Op.getValueType(), SrcVal);
5446 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5447 }
5448
5449 return Op;
5450}
5451
5452static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5453 EVT VT = Op.getValueType();
5454 SDLoc dl(Op);
5455
5456 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5457 if (VT.getVectorElementType() == MVT::f32)
5458 return Op;
5459 return DAG.UnrollVectorOp(Op.getNode());
5460 }
5461
5462 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5464, __PRETTY_FUNCTION__))
5463 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5464, __PRETTY_FUNCTION__))
5464 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5464, __PRETTY_FUNCTION__))
;
5465
5466 const bool HasFullFP16 =
5467 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5468
5469 EVT DestVecType;
5470 if (VT == MVT::v4f32)
5471 DestVecType = MVT::v4i32;
5472 else if (VT == MVT::v4f16 && HasFullFP16)
5473 DestVecType = MVT::v4i16;
5474 else if (VT == MVT::v8f16 && HasFullFP16)
5475 DestVecType = MVT::v8i16;
5476 else
5477 return DAG.UnrollVectorOp(Op.getNode());
5478
5479 unsigned CastOpc;
5480 unsigned Opc;
5481 switch (Op.getOpcode()) {
5482 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5482)
;
5483 case ISD::SINT_TO_FP:
5484 CastOpc = ISD::SIGN_EXTEND;
5485 Opc = ISD::SINT_TO_FP;
5486 break;
5487 case ISD::UINT_TO_FP:
5488 CastOpc = ISD::ZERO_EXTEND;
5489 Opc = ISD::UINT_TO_FP;
5490 break;
5491 }
5492
5493 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5494 return DAG.getNode(Opc, dl, VT, Op);
5495}
5496
5497SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5498 EVT VT = Op.getValueType();
5499 if (VT.isVector())
5500 return LowerVectorINT_TO_FP(Op, DAG);
5501 if (isUnsupportedFloatingType(VT)) {
5502 RTLIB::Libcall LC;
5503 if (Op.getOpcode() == ISD::SINT_TO_FP)
5504 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5505 Op.getValueType());
5506 else
5507 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5508 Op.getValueType());
5509 MakeLibCallOptions CallOptions;
5510 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5511 CallOptions, SDLoc(Op)).first;
5512 }
5513
5514 return Op;
5515}
5516
5517SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5518 // Implement fcopysign with a fabs and a conditional fneg.
5519 SDValue Tmp0 = Op.getOperand(0);
5520 SDValue Tmp1 = Op.getOperand(1);
5521 SDLoc dl(Op);
5522 EVT VT = Op.getValueType();
5523 EVT SrcVT = Tmp1.getValueType();
5524 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5525 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5526 bool UseNEON = !InGPR && Subtarget->hasNEON();
5527
5528 if (UseNEON) {
5529 // Use VBSL to copy the sign bit.
5530 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5531 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5532 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5533 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5534 if (VT == MVT::f64)
5535 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5536 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5537 DAG.getConstant(32, dl, MVT::i32));
5538 else /*if (VT == MVT::f32)*/
5539 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5540 if (SrcVT == MVT::f32) {
5541 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5542 if (VT == MVT::f64)
5543 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5544 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5545 DAG.getConstant(32, dl, MVT::i32));
5546 } else if (VT == MVT::f32)
5547 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5548 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5549 DAG.getConstant(32, dl, MVT::i32));
5550 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5551 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5552
5553 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5554 dl, MVT::i32);
5555 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5556 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5557 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5558
5559 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5560 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5561 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5562 if (VT == MVT::f32) {
5563 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5564 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5565 DAG.getConstant(0, dl, MVT::i32));
5566 } else {
5567 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5568 }
5569
5570 return Res;
5571 }
5572
5573 // Bitcast operand 1 to i32.
5574 if (SrcVT == MVT::f64)
5575 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5576 Tmp1).getValue(1);
5577 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5578
5579 // Or in the signbit with integer operations.
5580 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5581 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5582 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5583 if (VT == MVT::f32) {
5584 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5585 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5586 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5587 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5588 }
5589
5590 // f64: Or the high part with signbit and then combine two parts.
5591 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5592 Tmp0);
5593 SDValue Lo = Tmp0.getValue(0);
5594 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5595 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5596 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5597}
5598
5599SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5600 MachineFunction &MF = DAG.getMachineFunction();
5601 MachineFrameInfo &MFI = MF.getFrameInfo();
5602 MFI.setReturnAddressIsTaken(true);
5603
5604 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5605 return SDValue();
5606
5607 EVT VT = Op.getValueType();
5608 SDLoc dl(Op);
5609 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5610 if (Depth) {
5611 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5612 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5613 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5614 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5615 MachinePointerInfo());
5616 }
5617
5618 // Return LR, which contains the return address. Mark it an implicit live-in.
5619 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5620 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5621}
5622
5623SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5624 const ARMBaseRegisterInfo &ARI =
5625 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5626 MachineFunction &MF = DAG.getMachineFunction();
5627 MachineFrameInfo &MFI = MF.getFrameInfo();
5628 MFI.setFrameAddressIsTaken(true);
5629
5630 EVT VT = Op.getValueType();
5631 SDLoc dl(Op); // FIXME probably not meaningful
5632 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5633 Register FrameReg = ARI.getFrameRegister(MF);
5634 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5635 while (Depth--)
5636 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5637 MachinePointerInfo());
5638 return FrameAddr;
5639}
5640
5641// FIXME? Maybe this could be a TableGen attribute on some registers and
5642// this table could be generated automatically from RegInfo.
5643Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5644 const MachineFunction &MF) const {
5645 Register Reg = StringSwitch<unsigned>(RegName)
5646 .Case("sp", ARM::SP)
5647 .Default(0);
5648 if (Reg)
5649 return Reg;
5650 report_fatal_error(Twine("Invalid register name \""
5651 + StringRef(RegName) + "\"."));
5652}
5653
5654// Result is 64 bit value so split into two 32 bit values and return as a
5655// pair of values.
5656static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5657 SelectionDAG &DAG) {
5658 SDLoc DL(N);
5659
5660 // This function is only supposed to be called for i64 type destination.
5661 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5662, __PRETTY_FUNCTION__))
5662 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5662, __PRETTY_FUNCTION__))
;
5663
5664 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5665 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5666 N->getOperand(0),
5667 N->getOperand(1));
5668
5669 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5670 Read.getValue(1)));
5671 Results.push_back(Read.getOperand(0));
5672}
5673
5674/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5675/// When \p DstVT, the destination type of \p BC, is on the vector
5676/// register bank and the source of bitcast, \p Op, operates on the same bank,
5677/// it might be possible to combine them, such that everything stays on the
5678/// vector register bank.
5679/// \p return The node that would replace \p BT, if the combine
5680/// is possible.
5681static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5682 SelectionDAG &DAG) {
5683 SDValue Op = BC->getOperand(0);
5684 EVT DstVT = BC->getValueType(0);
5685
5686 // The only vector instruction that can produce a scalar (remember,
5687 // since the bitcast was about to be turned into VMOVDRR, the source
5688 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5689 // Moreover, we can do this combine only if there is one use.
5690 // Finally, if the destination type is not a vector, there is not
5691 // much point on forcing everything on the vector bank.
5692 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5693 !Op.hasOneUse())
5694 return SDValue();
5695
5696 // If the index is not constant, we will introduce an additional
5697 // multiply that will stick.
5698 // Give up in that case.
5699 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5700 if (!Index)
5701 return SDValue();
5702 unsigned DstNumElt = DstVT.getVectorNumElements();
5703
5704 // Compute the new index.
5705 const APInt &APIntIndex = Index->getAPIntValue();
5706 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5707 NewIndex *= APIntIndex;
5708 // Check if the new constant index fits into i32.
5709 if (NewIndex.getBitWidth() > 32)
5710 return SDValue();
5711
5712 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5713 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5714 SDLoc dl(Op);
5715 SDValue ExtractSrc = Op.getOperand(0);
5716 EVT VecVT = EVT::getVectorVT(
5717 *DAG.getContext(), DstVT.getScalarType(),
5718 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5719 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5720 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5721 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5722}
5723
5724/// ExpandBITCAST - If the target supports VFP, this function is called to
5725/// expand a bit convert where either the source or destination type is i64 to
5726/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5727/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5728/// vectors), since the legalizer won't know what to do with that.
5729static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5730 const ARMSubtarget *Subtarget) {
5731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5732 SDLoc dl(N);
5733 SDValue Op = N->getOperand(0);
5734
5735 // This function is only supposed to be called for i64 types, either as the
5736 // source or destination of the bit convert.
5737 EVT SrcVT = Op.getValueType();
5738 EVT DstVT = N->getValueType(0);
5739 const bool HasFullFP16 = Subtarget->hasFullFP16();
5740
5741 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5742 if (!HasFullFP16)
5743 return SDValue();
5744 // SoftFP: read half-precision arguments:
5745 //
5746 // t2: i32,ch = ...
5747 // t7: i16 = truncate t2 <~~~~ Op
5748 // t8: f16 = bitcast t7 <~~~~ N
5749 //
5750 if (Op.getOperand(0).getValueType() == MVT::i32)
5751 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5752 MVT::f16, Op.getOperand(0));
5753
5754 return SDValue();
5755 }
5756
5757 // Half-precision return values
5758 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5759 if (!HasFullFP16)
5760 return SDValue();
5761 //
5762 // t11: f16 = fadd t8, t10
5763 // t12: i16 = bitcast t11 <~~~ SDNode N
5764 // t13: i32 = zero_extend t12
5765 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5766 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5767 //
5768 // transform this into:
5769 //
5770 // t20: i32 = ARMISD::VMOVrh t11
5771 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5772 //
5773 auto ZeroExtend = N->use_begin();
5774 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5775 ZeroExtend->getValueType(0) != MVT::i32)
5776 return SDValue();
5777
5778 auto Copy = ZeroExtend->use_begin();
5779 if (Copy->getOpcode() == ISD::CopyToReg &&
5780 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5781 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5782 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5783 return Cvt;
5784 }
5785 return SDValue();
5786 }
5787
5788 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5789 return SDValue();
5790
5791 // Turn i64->f64 into VMOVDRR.
5792 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5793 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5794 // if we can combine the bitcast with its source.
5795 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5796 return Val;
5797
5798 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5799 DAG.getConstant(0, dl, MVT::i32));
5800 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5801 DAG.getConstant(1, dl, MVT::i32));
5802 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5803 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5804 }
5805
5806 // Turn f64->i64 into VMOVRRD.
5807 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5808 SDValue Cvt;
5809 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5810 SrcVT.getVectorNumElements() > 1)
5811 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5812 DAG.getVTList(MVT::i32, MVT::i32),
5813 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5814 else
5815 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5816 DAG.getVTList(MVT::i32, MVT::i32), Op);
5817 // Merge the pieces into a single i64 value.
5818 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5819 }
5820
5821 return SDValue();
5822}
5823
5824/// getZeroVector - Returns a vector of specified type with all zero elements.
5825/// Zero vectors are used to represent vector negation and in those cases
5826/// will be implemented with the NEON VNEG instruction. However, VNEG does
5827/// not support i64 elements, so sometimes the zero vectors will need to be
5828/// explicitly constructed. Regardless, use a canonical VMOV to create the
5829/// zero vector.
5830static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5831 assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5831, __PRETTY_FUNCTION__))
;
5832 // The canonical modified immediate encoding of a zero vector is....0!
5833 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5834 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5835 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5836 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5837}
5838
5839/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5840/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5841SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5842 SelectionDAG &DAG) const {
5843 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5843, __PRETTY_FUNCTION__))
;
5844 EVT VT = Op.getValueType();
5845 unsigned VTBits = VT.getSizeInBits();
5846 SDLoc dl(Op);
5847 SDValue ShOpLo = Op.getOperand(0);
5848 SDValue ShOpHi = Op.getOperand(1);
5849 SDValue ShAmt = Op.getOperand(2);
5850 SDValue ARMcc;
5851 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5852 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5853
5854 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::
SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5854, __PRETTY_FUNCTION__))
;
5855
5856 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5857 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5858 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5859 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5860 DAG.getConstant(VTBits, dl, MVT::i32));
5861 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5862 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5863 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5864 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5865 ISD::SETGE, ARMcc, DAG, dl);
5866 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5867 ARMcc, CCR, CmpLo);
5868
5869 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5870 SDValue HiBigShift = Opc == ISD::SRA
5871 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5872 DAG.getConstant(VTBits - 1, dl, VT))
5873 : DAG.getConstant(0, dl, VT);
5874 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5875 ISD::SETGE, ARMcc, DAG, dl);
5876 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5877 ARMcc, CCR, CmpHi);
5878
5879 SDValue Ops[2] = { Lo, Hi };
5880 return DAG.getMergeValues(Ops, dl);
5881}
5882
5883/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5884/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5885SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5886 SelectionDAG &DAG) const {
5887 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5887, __PRETTY_FUNCTION__))
;
5888 EVT VT = Op.getValueType();
5889 unsigned VTBits = VT.getSizeInBits();
5890 SDLoc dl(Op);
5891 SDValue ShOpLo = Op.getOperand(0);
5892 SDValue ShOpHi = Op.getOperand(1);
5893 SDValue ShAmt = Op.getOperand(2);
5894 SDValue ARMcc;
5895 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5896
5897 assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void>
(0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5897, __PRETTY_FUNCTION__))
;
5898 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5899 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5900 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5901 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5902 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5903
5904 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5905 DAG.getConstant(VTBits, dl, MVT::i32));
5906 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5907 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5908 ISD::SETGE, ARMcc, DAG, dl);
5909 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5910 ARMcc, CCR, CmpHi);
5911
5912 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5913 ISD::SETGE, ARMcc, DAG, dl);
5914 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5915 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5916 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5917
5918 SDValue Ops[2] = { Lo, Hi };
5919 return DAG.getMergeValues(Ops, dl);
5920}
5921
5922SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5923 SelectionDAG &DAG) const {
5924 // The rounding mode is in bits 23:22 of the FPSCR.
5925 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5926 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5927 // so that the shift + and get folded into a bitfield extract.
5928 SDLoc dl(Op);
5929 SDValue Chain = Op.getOperand(0);
5930 SDValue Ops[] = {Chain,
5931 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32)};
5932
5933 SDValue FPSCR =
5934 DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, {MVT::i32, MVT::Other}, Ops);
5935 Chain = FPSCR.getValue(1);
5936 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5937 DAG.getConstant(1U << 22, dl, MVT::i32));
5938 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5939 DAG.getConstant(22, dl, MVT::i32));
5940 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5941 DAG.getConstant(3, dl, MVT::i32));
5942 return DAG.getMergeValues({And, Chain}, dl);
5943}
5944
5945static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5946 const ARMSubtarget *ST) {
5947 SDLoc dl(N);
5948 EVT VT = N->getValueType(0);
5949 if (VT.isVector() && ST->hasNEON()) {
5950
5951 // Compute the least significant set bit: LSB = X & -X
5952 SDValue X = N->getOperand(0);
5953 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5954 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5955
5956 EVT ElemTy = VT.getVectorElementType();
5957
5958 if (ElemTy == MVT::i8) {
5959 // Compute with: cttz(x) = ctpop(lsb - 1)
5960 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5961 DAG.getTargetConstant(1, dl, ElemTy));
5962 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5963 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5964 }
5965
5966 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5967 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5968 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5969 unsigned NumBits = ElemTy.getSizeInBits();
5970 SDValue WidthMinus1 =
5971 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5972 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5973 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5974 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5975 }
5976
5977 // Compute with: cttz(x) = ctpop(lsb - 1)
5978
5979 // Compute LSB - 1.
5980 SDValue Bits;
5981 if (ElemTy == MVT::i64) {
5982 // Load constant 0xffff'ffff'ffff'ffff to register.
5983 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5984 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5985 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5986 } else {
5987 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5988 DAG.getTargetConstant(1, dl, ElemTy));
5989 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5990 }
5991 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5992 }
5993
5994 if (!ST->hasV6T2Ops())
5995 return SDValue(