Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1162, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/IntrinsicsARM.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/PatternMatch.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MachineValueType.h"
101#include "llvm/Support/MathExtras.h"
102#include "llvm/Support/raw_ostream.h"
103#include "llvm/Target/TargetMachine.h"
104#include "llvm/Target/TargetOptions.h"
105#include <algorithm>
106#include <cassert>
107#include <cstdint>
108#include <cstdlib>
109#include <iterator>
110#include <limits>
111#include <string>
112#include <tuple>
113#include <utility>
114#include <vector>
115
116using namespace llvm;
117using namespace llvm::PatternMatch;
118
119#define DEBUG_TYPE"arm-isel" "arm-isel"
120
121STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
122STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
123STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
124STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
125 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
126
127static cl::opt<bool>
128ARMInterworking("arm-interworking", cl::Hidden,
129 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 cl::init(true));
131
132static cl::opt<bool> EnableConstpoolPromotion(
133 "arm-promote-constant", cl::Hidden,
134 cl::desc("Enable / disable promotion of unnamed_addr constants into "
135 "constant pools"),
136 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
137static cl::opt<unsigned> ConstpoolPromotionMaxSize(
138 "arm-promote-constant-max-size", cl::Hidden,
139 cl::desc("Maximum size of constant to promote into a constant pool"),
140 cl::init(64));
141static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
142 "arm-promote-constant-max-total", cl::Hidden,
143 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 cl::init(128));
145
146static cl::opt<unsigned>
147MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
148 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
149 cl::init(2));
150
151// The APCS parameter registers.
152static const MCPhysReg GPRArgRegs[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154};
155
156void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
157 MVT PromotedBitwiseVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Promote all bit-wise operations.
197 if (VT.isInteger() && VT != PromotedBitwiseVT) {
198 setOperationAction(ISD::AND, VT, Promote);
199 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
200 setOperationAction(ISD::OR, VT, Promote);
201 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
202 setOperationAction(ISD::XOR, VT, Promote);
203 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
204 }
205
206 // Neon does not support vector divide/remainder operations.
207 setOperationAction(ISD::SDIV, VT, Expand);
208 setOperationAction(ISD::UDIV, VT, Expand);
209 setOperationAction(ISD::FDIV, VT, Expand);
210 setOperationAction(ISD::SREM, VT, Expand);
211 setOperationAction(ISD::UREM, VT, Expand);
212 setOperationAction(ISD::FREM, VT, Expand);
213
214 if (!VT.isFloatingPoint() &&
215 VT != MVT::v2i64 && VT != MVT::v1i64)
216 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
217 setOperationAction(Opcode, VT, Legal);
218 if (!VT.isFloatingPoint())
219 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
220 setOperationAction(Opcode, VT, Legal);
221}
222
223void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
224 addRegisterClass(VT, &ARM::DPRRegClass);
225 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
226}
227
228void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
229 addRegisterClass(VT, &ARM::DPairRegClass);
230 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
231}
232
233void ARMTargetLowering::setAllExpand(MVT VT) {
234 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
235 setOperationAction(Opc, VT, Expand);
236
237 // We support these really simple operations even on types where all
238 // the actual arithmetic has to be broken down into simpler
239 // operations or turned into library calls.
240 setOperationAction(ISD::BITCAST, VT, Legal);
241 setOperationAction(ISD::LOAD, VT, Legal);
242 setOperationAction(ISD::STORE, VT, Legal);
243 setOperationAction(ISD::UNDEF, VT, Legal);
244}
245
246void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
247 LegalizeAction Action) {
248 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
249 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
250 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
251}
252
253void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
254 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
255
256 for (auto VT : IntTypes) {
257 addRegisterClass(VT, &ARM::MQPRRegClass);
258 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
259 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
260 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
261 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
262 setOperationAction(ISD::SHL, VT, Custom);
263 setOperationAction(ISD::SRA, VT, Custom);
264 setOperationAction(ISD::SRL, VT, Custom);
265 setOperationAction(ISD::SMIN, VT, Legal);
266 setOperationAction(ISD::SMAX, VT, Legal);
267 setOperationAction(ISD::UMIN, VT, Legal);
268 setOperationAction(ISD::UMAX, VT, Legal);
269 setOperationAction(ISD::ABS, VT, Legal);
270 setOperationAction(ISD::SETCC, VT, Custom);
271 setOperationAction(ISD::MLOAD, VT, Custom);
272 setOperationAction(ISD::MSTORE, VT, Legal);
273 setOperationAction(ISD::CTLZ, VT, Legal);
274 setOperationAction(ISD::CTTZ, VT, Custom);
275 setOperationAction(ISD::BITREVERSE, VT, Legal);
276 setOperationAction(ISD::BSWAP, VT, Legal);
277 setOperationAction(ISD::SADDSAT, VT, Legal);
278 setOperationAction(ISD::UADDSAT, VT, Legal);
279 setOperationAction(ISD::SSUBSAT, VT, Legal);
280 setOperationAction(ISD::USUBSAT, VT, Legal);
281
282 // No native support for these.
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SDIV, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
286 setOperationAction(ISD::SREM, VT, Expand);
287 setOperationAction(ISD::CTPOP, VT, Expand);
288
289 // Vector reductions
290 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
291 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
292 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
295
296 if (!HasMVEFP) {
297 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
298 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
301 }
302
303 // Pre and Post inc are supported on loads and stores
304 for (unsigned im = (unsigned)ISD::PRE_INC;
305 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
306 setIndexedLoadAction(im, VT, Legal);
307 setIndexedStoreAction(im, VT, Legal);
308 setIndexedMaskedLoadAction(im, VT, Legal);
309 setIndexedMaskedStoreAction(im, VT, Legal);
310 }
311 }
312
313 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
314 for (auto VT : FloatTypes) {
315 addRegisterClass(VT, &ARM::MQPRRegClass);
316 if (!HasMVEFP)
317 setAllExpand(VT);
318
319 // These are legal or custom whether we have MVE.fp or not
320 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
324 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
325 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
326 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
327 setOperationAction(ISD::SETCC, VT, Custom);
328 setOperationAction(ISD::MLOAD, VT, Custom);
329 setOperationAction(ISD::MSTORE, VT, Legal);
330
331 // Pre and Post inc are supported on loads and stores
332 for (unsigned im = (unsigned)ISD::PRE_INC;
333 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
334 setIndexedLoadAction(im, VT, Legal);
335 setIndexedStoreAction(im, VT, Legal);
336 setIndexedMaskedLoadAction(im, VT, Legal);
337 setIndexedMaskedStoreAction(im, VT, Legal);
338 }
339
340 if (HasMVEFP) {
341 setOperationAction(ISD::FMINNUM, VT, Legal);
342 setOperationAction(ISD::FMAXNUM, VT, Legal);
343 setOperationAction(ISD::FROUND, VT, Legal);
344
345 // No native support for these.
346 setOperationAction(ISD::FDIV, VT, Expand);
347 setOperationAction(ISD::FREM, VT, Expand);
348 setOperationAction(ISD::FSQRT, VT, Expand);
349 setOperationAction(ISD::FSIN, VT, Expand);
350 setOperationAction(ISD::FCOS, VT, Expand);
351 setOperationAction(ISD::FPOW, VT, Expand);
352 setOperationAction(ISD::FLOG, VT, Expand);
353 setOperationAction(ISD::FLOG2, VT, Expand);
354 setOperationAction(ISD::FLOG10, VT, Expand);
355 setOperationAction(ISD::FEXP, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FNEARBYINT, VT, Expand);
358 }
359 }
360
361 // We 'support' these types up to bitcast/load/store level, regardless of
362 // MVE integer-only / float support. Only doing FP data processing on the FP
363 // vector types is inhibited at integer-only level.
364 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
365 for (auto VT : LongTypes) {
366 addRegisterClass(VT, &ARM::MQPRRegClass);
367 setAllExpand(VT);
368 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
369 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
370 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
371 }
372 // We can do bitwise operations on v2i64 vectors
373 setOperationAction(ISD::AND, MVT::v2i64, Legal);
374 setOperationAction(ISD::OR, MVT::v2i64, Legal);
375 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
376
377 // It is legal to extload from v4i8 to v4i16 or v4i32.
378 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
379 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
380 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
381
382 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
383 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
386 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
388
389 // Some truncating stores are legal too.
390 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
392 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
393
394 // Pre and Post inc on these are legal, given the correct extends
395 for (unsigned im = (unsigned)ISD::PRE_INC;
396 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
397 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
398 setIndexedLoadAction(im, VT, Legal);
399 setIndexedStoreAction(im, VT, Legal);
400 setIndexedMaskedLoadAction(im, VT, Legal);
401 setIndexedMaskedStoreAction(im, VT, Legal);
402 }
403 }
404
405 // Predicate types
406 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
407 for (auto VT : pTypes) {
408 addRegisterClass(VT, &ARM::VCCRRegClass);
409 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
410 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
411 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
412 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
413 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
415 setOperationAction(ISD::SETCC, VT, Custom);
416 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
417 setOperationAction(ISD::LOAD, VT, Custom);
418 setOperationAction(ISD::STORE, VT, Custom);
419 }
420}
421
422ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
423 const ARMSubtarget &STI)
424 : TargetLowering(TM), Subtarget(&STI) {
425 RegInfo = Subtarget->getRegisterInfo();
426 Itins = Subtarget->getInstrItineraryData();
427
428 setBooleanContents(ZeroOrOneBooleanContent);
429 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
430
431 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
432 !Subtarget->isTargetWatchOS()) {
433 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
434 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
435 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
436 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
437 : CallingConv::ARM_AAPCS);
438 }
439
440 if (Subtarget->isTargetMachO()) {
441 // Uses VFP for Thumb libfuncs if available.
442 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
443 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const ISD::CondCode Cond;
448 } LibraryCalls[] = {
449 // Single-precision floating-point arithmetic.
450 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
451 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
452 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
453 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
454
455 // Double-precision floating-point arithmetic.
456 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
457 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
458 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
459 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
460
461 // Single-precision comparisons.
462 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
463 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
464 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
465 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
466 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
467 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
468 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
469
470 // Double-precision comparisons.
471 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
472 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
473 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
474 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
475 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
476 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
477 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
478
479 // Floating-point to integer conversions.
480 // i64 conversions are done via library routines even when generating VFP
481 // instructions, so use the same ones.
482 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
483 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
484 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
485 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
486
487 // Conversions between floating types.
488 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
489 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
490
491 // Integer to floating-point conversions.
492 // i64 conversions are done via library routines even when generating VFP
493 // instructions, so use the same ones.
494 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
495 // e.g., __floatunsidf vs. __floatunssidfvfp.
496 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
497 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
498 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
499 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
500 };
501
502 for (const auto &LC : LibraryCalls) {
503 setLibcallName(LC.Op, LC.Name);
504 if (LC.Cond != ISD::SETCC_INVALID)
505 setCmpLibcallCC(LC.Op, LC.Cond);
506 }
507 }
508 }
509
510 // These libcalls are not available in 32-bit.
511 setLibcallName(RTLIB::SHL_I128, nullptr);
512 setLibcallName(RTLIB::SRL_I128, nullptr);
513 setLibcallName(RTLIB::SRA_I128, nullptr);
514
515 // RTLIB
516 if (Subtarget->isAAPCS_ABI() &&
517 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
518 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
519 static const struct {
520 const RTLIB::Libcall Op;
521 const char * const Name;
522 const CallingConv::ID CC;
523 const ISD::CondCode Cond;
524 } LibraryCalls[] = {
525 // Double-precision floating-point arithmetic helper functions
526 // RTABI chapter 4.1.2, Table 2
527 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
528 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
529 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
530 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
531
532 // Double-precision floating-point comparison helper functions
533 // RTABI chapter 4.1.2, Table 3
534 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
535 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
536 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
537 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
538 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
539 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
540 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
541
542 // Single-precision floating-point arithmetic helper functions
543 // RTABI chapter 4.1.2, Table 4
544 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
545 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
546 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
547 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
548
549 // Single-precision floating-point comparison helper functions
550 // RTABI chapter 4.1.2, Table 5
551 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
552 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
553 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
554 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
555 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
556 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
557 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
558
559 // Floating-point to integer conversions.
560 // RTABI chapter 4.1.2, Table 6
561 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
562 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
563 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
565 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
566 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
567 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
568 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
569
570 // Conversions between floating types.
571 // RTABI chapter 4.1.2, Table 7
572 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
573 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
574 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
575
576 // Integer to floating-point conversions.
577 // RTABI chapter 4.1.2, Table 8
578 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
579 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
580 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
582 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
583 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
584 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
585 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
586
587 // Long long helper functions
588 // RTABI chapter 4.2, Table 9
589 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
590 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593
594 // Integer division functions
595 // RTABI chapter 4.3.1
596 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
599 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
600 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
601 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 };
605
606 for (const auto &LC : LibraryCalls) {
607 setLibcallName(LC.Op, LC.Name);
608 setLibcallCallingConv(LC.Op, LC.CC);
609 if (LC.Cond != ISD::SETCC_INVALID)
610 setCmpLibcallCC(LC.Op, LC.Cond);
611 }
612
613 // EABI dependent RTLIB
614 if (TM.Options.EABIVersion == EABI::EABI4 ||
615 TM.Options.EABIVersion == EABI::EABI5) {
616 static const struct {
617 const RTLIB::Libcall Op;
618 const char *const Name;
619 const CallingConv::ID CC;
620 const ISD::CondCode Cond;
621 } MemOpsLibraryCalls[] = {
622 // Memory operations
623 // RTABI chapter 4.3.4
624 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 };
628
629 for (const auto &LC : MemOpsLibraryCalls) {
630 setLibcallName(LC.Op, LC.Name);
631 setLibcallCallingConv(LC.Op, LC.CC);
632 if (LC.Cond != ISD::SETCC_INVALID)
633 setCmpLibcallCC(LC.Op, LC.Cond);
634 }
635 }
636 }
637
638 if (Subtarget->isTargetWindows()) {
639 static const struct {
640 const RTLIB::Libcall Op;
641 const char * const Name;
642 const CallingConv::ID CC;
643 } LibraryCalls[] = {
644 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
645 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
646 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
647 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
648 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
649 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
650 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
651 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
652 };
653
654 for (const auto &LC : LibraryCalls) {
655 setLibcallName(LC.Op, LC.Name);
656 setLibcallCallingConv(LC.Op, LC.CC);
657 }
658 }
659
660 // Use divmod compiler-rt calls for iOS 5.0 and later.
661 if (Subtarget->isTargetMachO() &&
662 !(Subtarget->isTargetIOS() &&
663 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
664 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
665 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
666 }
667
668 // The half <-> float conversion functions are always soft-float on
669 // non-watchos platforms, but are needed for some targets which use a
670 // hard-float calling convention by default.
671 if (!Subtarget->isTargetWatchABI()) {
672 if (Subtarget->isAAPCS_ABI()) {
673 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
674 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
675 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
676 } else {
677 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
678 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
679 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
680 }
681 }
682
683 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
684 // a __gnu_ prefix (which is the default).
685 if (Subtarget->isTargetAEABI()) {
686 static const struct {
687 const RTLIB::Libcall Op;
688 const char * const Name;
689 const CallingConv::ID CC;
690 } LibraryCalls[] = {
691 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
692 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
693 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
694 };
695
696 for (const auto &LC : LibraryCalls) {
697 setLibcallName(LC.Op, LC.Name);
698 setLibcallCallingConv(LC.Op, LC.CC);
699 }
700 }
701
702 if (Subtarget->isThumb1Only())
703 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
704 else
705 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
706
707 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
708 Subtarget->hasFPRegs()) {
709 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
710 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
711 if (!Subtarget->hasVFP2Base())
712 setAllExpand(MVT::f32);
713 if (!Subtarget->hasFP64())
714 setAllExpand(MVT::f64);
715 }
716
717 if (Subtarget->hasFullFP16()) {
718 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
719 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
720 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
721 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
722
723 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
724 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
725 }
726
727 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
728 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
729 setTruncStoreAction(VT, InnerVT, Expand);
730 addAllExtLoads(VT, InnerVT, Expand);
731 }
732
733 setOperationAction(ISD::MULHS, VT, Expand);
734 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
735 setOperationAction(ISD::MULHU, VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
737
738 setOperationAction(ISD::BSWAP, VT, Expand);
739 }
740
741 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
742 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
743
744 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
745 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
746
747 if (Subtarget->hasMVEIntegerOps())
748 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
749
750 // Combine low-overhead loop intrinsics so that we can lower i1 types.
751 if (Subtarget->hasLOB()) {
752 setTargetDAGCombine(ISD::BRCOND);
753 setTargetDAGCombine(ISD::BR_CC);
754 }
755
756 if (Subtarget->hasNEON()) {
757 addDRTypeForNEON(MVT::v2f32);
758 addDRTypeForNEON(MVT::v8i8);
759 addDRTypeForNEON(MVT::v4i16);
760 addDRTypeForNEON(MVT::v2i32);
761 addDRTypeForNEON(MVT::v1i64);
762
763 addQRTypeForNEON(MVT::v4f32);
764 addQRTypeForNEON(MVT::v2f64);
765 addQRTypeForNEON(MVT::v16i8);
766 addQRTypeForNEON(MVT::v8i16);
767 addQRTypeForNEON(MVT::v4i32);
768 addQRTypeForNEON(MVT::v2i64);
769
770 if (Subtarget->hasFullFP16()) {
771 addQRTypeForNEON(MVT::v8f16);
772 addDRTypeForNEON(MVT::v4f16);
773 }
774 }
775
776 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
777 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
778 // none of Neon, MVE or VFP supports any arithmetic operations on it.
779 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
780 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
781 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
782 // FIXME: Code duplication: FDIV and FREM are expanded always, see
783 // ARMTargetLowering::addTypeForNEON method for details.
784 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
785 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
786 // FIXME: Create unittest.
787 // In another words, find a way when "copysign" appears in DAG with vector
788 // operands.
789 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
790 // FIXME: Code duplication: SETCC has custom operation action, see
791 // ARMTargetLowering::addTypeForNEON method for details.
792 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
793 // FIXME: Create unittest for FNEG and for FABS.
794 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
795 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
796 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
797 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
798 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
799 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
800 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
801 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
802 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
803 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
804 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
805 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
806 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
807 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
808 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
809 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
810 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
811 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
812 }
813
814 if (Subtarget->hasNEON()) {
815 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
816 // supported for v4f32.
817 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
818 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
819 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
820 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
821 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
822 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
823 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
824 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
825 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
826 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
827 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
828 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
829 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
830 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
831
832 // Mark v2f32 intrinsics.
833 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
834 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
835 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
836 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
837 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
838 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
839 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
840 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
841 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
842 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
843 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
844 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
845 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
846 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
847
848 // Neon does not support some operations on v1i64 and v2i64 types.
849 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
850 // Custom handling for some quad-vector types to detect VMULL.
851 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
852 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
853 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
854 // Custom handling for some vector types to avoid expensive expansions
855 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
856 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
857 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
858 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
859 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
860 // a destination type that is wider than the source, and nor does
861 // it have a FP_TO_[SU]INT instruction with a narrower destination than
862 // source.
863 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
864 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
865 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
866 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
867 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
868 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
869 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
870 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
871
872 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
873 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
874
875 // NEON does not have single instruction CTPOP for vectors with element
876 // types wider than 8-bits. However, custom lowering can leverage the
877 // v8i8/v16i8 vcnt instruction.
878 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
879 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
880 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
881 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
882 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
883 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
884
885 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
886 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
887
888 // NEON does not have single instruction CTTZ for vectors.
889 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
890 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
891 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
892 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
893
894 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
895 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
896 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
897 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
898
899 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
900 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
901 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
902 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
903
904 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
905 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
906 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
907 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
908
909 // NEON only has FMA instructions as of VFP4.
910 if (!Subtarget->hasVFP4Base()) {
911 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
912 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
913 }
914
915 setTargetDAGCombine(ISD::INTRINSIC_VOID);
916 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
917 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
918 setTargetDAGCombine(ISD::SHL);
919 setTargetDAGCombine(ISD::SRL);
920 setTargetDAGCombine(ISD::SRA);
921 setTargetDAGCombine(ISD::FP_TO_SINT);
922 setTargetDAGCombine(ISD::FP_TO_UINT);
923 setTargetDAGCombine(ISD::FDIV);
924 setTargetDAGCombine(ISD::LOAD);
925
926 // It is legal to extload from v4i8 to v4i16 or v4i32.
927 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
928 MVT::v2i32}) {
929 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
930 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
931 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
932 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
933 }
934 }
935 }
936
937 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
938 setTargetDAGCombine(ISD::BUILD_VECTOR);
939 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
940 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
941 setTargetDAGCombine(ISD::STORE);
942 setTargetDAGCombine(ISD::SIGN_EXTEND);
943 setTargetDAGCombine(ISD::ZERO_EXTEND);
944 setTargetDAGCombine(ISD::ANY_EXTEND);
945 }
946
947 if (!Subtarget->hasFP64()) {
948 // When targeting a floating-point unit with only single-precision
949 // operations, f64 is legal for the few double-precision instructions which
950 // are present However, no double-precision operations other than moves,
951 // loads and stores are provided by the hardware.
952 setOperationAction(ISD::FADD, MVT::f64, Expand);
953 setOperationAction(ISD::FSUB, MVT::f64, Expand);
954 setOperationAction(ISD::FMUL, MVT::f64, Expand);
955 setOperationAction(ISD::FMA, MVT::f64, Expand);
956 setOperationAction(ISD::FDIV, MVT::f64, Expand);
957 setOperationAction(ISD::FREM, MVT::f64, Expand);
958 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
959 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
960 setOperationAction(ISD::FNEG, MVT::f64, Expand);
961 setOperationAction(ISD::FABS, MVT::f64, Expand);
962 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
963 setOperationAction(ISD::FSIN, MVT::f64, Expand);
964 setOperationAction(ISD::FCOS, MVT::f64, Expand);
965 setOperationAction(ISD::FPOW, MVT::f64, Expand);
966 setOperationAction(ISD::FLOG, MVT::f64, Expand);
967 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
968 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
969 setOperationAction(ISD::FEXP, MVT::f64, Expand);
970 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
971 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
972 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
973 setOperationAction(ISD::FRINT, MVT::f64, Expand);
974 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
975 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
976 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
977 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
978 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
979 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
980 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
981 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
982 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
983 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
984 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
985 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
986 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
987 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
988 }
989
990 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
991 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
992 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
993 if (Subtarget->hasFullFP16()) {
994 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
995 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
996 }
997 }
998
999 if (!Subtarget->hasFP16()) {
1000 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1001 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1002 }
1003
1004 computeRegisterProperties(Subtarget->getRegisterInfo());
1005
1006 // ARM does not have floating-point extending loads.
1007 for (MVT VT : MVT::fp_valuetypes()) {
1008 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1009 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1010 }
1011
1012 // ... or truncating stores
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1014 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1015 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1016
1017 // ARM does not have i1 sign extending load.
1018 for (MVT VT : MVT::integer_valuetypes())
1019 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1020
1021 // ARM supports all 4 flavors of integer indexed load / store.
1022 if (!Subtarget->isThumb1Only()) {
1023 for (unsigned im = (unsigned)ISD::PRE_INC;
1024 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1025 setIndexedLoadAction(im, MVT::i1, Legal);
1026 setIndexedLoadAction(im, MVT::i8, Legal);
1027 setIndexedLoadAction(im, MVT::i16, Legal);
1028 setIndexedLoadAction(im, MVT::i32, Legal);
1029 setIndexedStoreAction(im, MVT::i1, Legal);
1030 setIndexedStoreAction(im, MVT::i8, Legal);
1031 setIndexedStoreAction(im, MVT::i16, Legal);
1032 setIndexedStoreAction(im, MVT::i32, Legal);
1033 }
1034 } else {
1035 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1036 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1037 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1038 }
1039
1040 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1041 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1042 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1043 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1044
1045 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1046 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1047 if (Subtarget->hasDSP()) {
1048 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1049 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1050 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1051 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1052 }
1053 if (Subtarget->hasBaseDSP()) {
1054 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1055 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1056 }
1057
1058 // i64 operation support.
1059 setOperationAction(ISD::MUL, MVT::i64, Expand);
1060 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1061 if (Subtarget->isThumb1Only()) {
1062 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1063 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1064 }
1065 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1066 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1067 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1068
1069 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1070 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1071 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1072 setOperationAction(ISD::SRL, MVT::i64, Custom);
1073 setOperationAction(ISD::SRA, MVT::i64, Custom);
1074 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1075 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1076 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1077 setOperationAction(ISD::STORE, MVT::i64, Custom);
1078
1079 // MVE lowers 64 bit shifts to lsll and lsrl
1080 // assuming that ISD::SRL and SRA of i64 are already marked custom
1081 if (Subtarget->hasMVEIntegerOps())
1082 setOperationAction(ISD::SHL, MVT::i64, Custom);
1083
1084 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1085 if (Subtarget->isThumb1Only()) {
1086 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1087 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1088 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1089 }
1090
1091 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1092 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1093
1094 // ARM does not have ROTL.
1095 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1096 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1097 setOperationAction(ISD::ROTL, VT, Expand);
1098 setOperationAction(ISD::ROTR, VT, Expand);
1099 }
1100 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1101 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1102 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1103 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1104 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1105 }
1106
1107 // @llvm.readcyclecounter requires the Performance Monitors extension.
1108 // Default to the 0 expansion on unsupported platforms.
1109 // FIXME: Technically there are older ARM CPUs that have
1110 // implementation-specific ways of obtaining this information.
1111 if (Subtarget->hasPerfMon())
1112 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1113
1114 // Only ARMv6 has BSWAP.
1115 if (!Subtarget->hasV6Ops())
1116 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1117
1118 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1119 : Subtarget->hasDivideInARMMode();
1120 if (!hasDivide) {
1121 // These are expanded into libcalls if the cpu doesn't have HW divider.
1122 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1123 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1124 }
1125
1126 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1127 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1128 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1129
1130 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1131 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1132 }
1133
1134 setOperationAction(ISD::SREM, MVT::i32, Expand);
1135 setOperationAction(ISD::UREM, MVT::i32, Expand);
1136
1137 // Register based DivRem for AEABI (RTABI 4.2)
1138 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1139 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1140 Subtarget->isTargetWindows()) {
1141 setOperationAction(ISD::SREM, MVT::i64, Custom);
1142 setOperationAction(ISD::UREM, MVT::i64, Custom);
1143 HasStandaloneRem = false;
1144
1145 if (Subtarget->isTargetWindows()) {
1146 const struct {
1147 const RTLIB::Libcall Op;
1148 const char * const Name;
1149 const CallingConv::ID CC;
1150 } LibraryCalls[] = {
1151 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1152 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1153 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1154 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1155
1156 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1157 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1158 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1159 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1160 };
1161
1162 for (const auto &LC : LibraryCalls) {
1163 setLibcallName(LC.Op, LC.Name);
1164 setLibcallCallingConv(LC.Op, LC.CC);
1165 }
1166 } else {
1167 const struct {
1168 const RTLIB::Libcall Op;
1169 const char * const Name;
1170 const CallingConv::ID CC;
1171 } LibraryCalls[] = {
1172 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1173 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1174 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1175 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1176
1177 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1178 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1179 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1180 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1181 };
1182
1183 for (const auto &LC : LibraryCalls) {
1184 setLibcallName(LC.Op, LC.Name);
1185 setLibcallCallingConv(LC.Op, LC.CC);
1186 }
1187 }
1188
1189 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1190 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1191 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1192 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1193 } else {
1194 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1195 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1196 }
1197
1198 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1199 // MSVCRT doesn't have powi; fall back to pow
1200 setLibcallName(RTLIB::POWI_F32, nullptr);
1201 setLibcallName(RTLIB::POWI_F64, nullptr);
1202 }
1203
1204 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1205 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1206 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1207 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1208
1209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1210 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1211
1212 // Use the default implementation.
1213 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1214 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1215 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1216 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1217 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1218 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1219
1220 if (Subtarget->isTargetWindows())
1221 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1222 else
1223 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1224
1225 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1226 // the default expansion.
1227 InsertFencesForAtomic = false;
1228 if (Subtarget->hasAnyDataBarrier() &&
1229 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1230 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1231 // to ldrex/strex loops already.
1232 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1233 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1234 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1235
1236 // On v8, we have particularly efficient implementations of atomic fences
1237 // if they can be combined with nearby atomic loads and stores.
1238 if (!Subtarget->hasAcquireRelease() ||
1239 getTargetMachine().getOptLevel() == 0) {
1240 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1241 InsertFencesForAtomic = true;
1242 }
1243 } else {
1244 // If there's anything we can use as a barrier, go through custom lowering
1245 // for ATOMIC_FENCE.
1246 // If target has DMB in thumb, Fences can be inserted.
1247 if (Subtarget->hasDataBarrier())
1248 InsertFencesForAtomic = true;
1249
1250 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1251 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1252
1253 // Set them all for expansion, which will force libcalls.
1254 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1255 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1256 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1257 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1258 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1259 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1260 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1261 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1262 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1263 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1264 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1265 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1266 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1267 // Unordered/Monotonic case.
1268 if (!InsertFencesForAtomic) {
1269 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1270 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1271 }
1272 }
1273
1274 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1275
1276 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1277 if (!Subtarget->hasV6Ops()) {
1278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1280 }
1281 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1282
1283 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1284 !Subtarget->isThumb1Only()) {
1285 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1286 // iff target supports vfp2.
1287 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1288 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1289 }
1290
1291 // We want to custom lower some of our intrinsics.
1292 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1293 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1294 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1295 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1296 if (Subtarget->useSjLjEH())
1297 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1298
1299 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1300 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1301 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1302 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1303 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1304 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1305 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1306 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1307 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1308 if (Subtarget->hasFullFP16()) {
1309 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1310 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1311 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1312 }
1313
1314 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1315
1316 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1317 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1318 if (Subtarget->hasFullFP16())
1319 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1320 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1321 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1322 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1323
1324 // We don't support sin/cos/fmod/copysign/pow
1325 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1326 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1327 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1328 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1329 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1331 setOperationAction(ISD::FREM, MVT::f64, Expand);
1332 setOperationAction(ISD::FREM, MVT::f32, Expand);
1333 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1334 !Subtarget->isThumb1Only()) {
1335 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1336 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1337 }
1338 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1339 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1340
1341 if (!Subtarget->hasVFP4Base()) {
1342 setOperationAction(ISD::FMA, MVT::f64, Expand);
1343 setOperationAction(ISD::FMA, MVT::f32, Expand);
1344 }
1345
1346 // Various VFP goodness
1347 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1348 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1349 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1350 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1351 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1352 }
1353
1354 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1355 if (!Subtarget->hasFP16()) {
1356 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1357 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1358 }
1359 }
1360
1361 // Use __sincos_stret if available.
1362 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1363 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1364 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1365 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1366 }
1367
1368 // FP-ARMv8 implements a lot of rounding-like FP operations.
1369 if (Subtarget->hasFPARMv8Base()) {
1370 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1371 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1372 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1373 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1374 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1375 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1376 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1377 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1378 if (Subtarget->hasNEON()) {
1379 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1380 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1381 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1382 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1383 }
1384
1385 if (Subtarget->hasFP64()) {
1386 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1387 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1388 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1389 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1390 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1391 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1392 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1393 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1394 }
1395 }
1396
1397 // FP16 often need to be promoted to call lib functions
1398 if (Subtarget->hasFullFP16()) {
1399 setOperationAction(ISD::FREM, MVT::f16, Promote);
1400 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1401 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1402 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1403 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1404 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1405 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1406 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1407 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1408 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1409 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1410 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1411
1412 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1413 }
1414
1415 if (Subtarget->hasNEON()) {
1416 // vmin and vmax aren't available in a scalar form, so we use
1417 // a NEON instruction with an undef lane instead.
1418 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1419 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1420 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1421 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1422 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1423 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1424 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1425 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1426
1427 if (Subtarget->hasFullFP16()) {
1428 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1429 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1430 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1431 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1432
1433 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1434 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1435 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1436 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1437 }
1438 }
1439
1440 // We have target-specific dag combine patterns for the following nodes:
1441 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1442 setTargetDAGCombine(ISD::ADD);
1443 setTargetDAGCombine(ISD::SUB);
1444 setTargetDAGCombine(ISD::MUL);
1445 setTargetDAGCombine(ISD::AND);
1446 setTargetDAGCombine(ISD::OR);
1447 setTargetDAGCombine(ISD::XOR);
1448
1449 if (Subtarget->hasV6Ops())
1450 setTargetDAGCombine(ISD::SRL);
1451 if (Subtarget->isThumb1Only())
1452 setTargetDAGCombine(ISD::SHL);
1453
1454 setStackPointerRegisterToSaveRestore(ARM::SP);
1455
1456 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1457 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1458 setSchedulingPreference(Sched::RegPressure);
1459 else
1460 setSchedulingPreference(Sched::Hybrid);
1461
1462 //// temporary - rewrite interface to use type
1463 MaxStoresPerMemset = 8;
1464 MaxStoresPerMemsetOptSize = 4;
1465 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1466 MaxStoresPerMemcpyOptSize = 2;
1467 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1468 MaxStoresPerMemmoveOptSize = 2;
1469
1470 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1471 // are at least 4 bytes aligned.
1472 setMinStackArgumentAlignment(Align(4));
1473
1474 // Prefer likely predicted branches to selects on out-of-order cores.
1475 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1476
1477 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1478
1479 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1480
1481 if (Subtarget->isThumb() || Subtarget->isThumb2())
1482 setTargetDAGCombine(ISD::ABS);
1483}
1484
1485bool ARMTargetLowering::useSoftFloat() const {
1486 return Subtarget->useSoftFloat();
1487}
1488
1489// FIXME: It might make sense to define the representative register class as the
1490// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1491// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1492// SPR's representative would be DPR_VFP2. This should work well if register
1493// pressure tracking were modified such that a register use would increment the
1494// pressure of the register class's representative and all of it's super
1495// classes' representatives transitively. We have not implemented this because
1496// of the difficulty prior to coalescing of modeling operand register classes
1497// due to the common occurrence of cross class copies and subregister insertions
1498// and extractions.
1499std::pair<const TargetRegisterClass *, uint8_t>
1500ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1501 MVT VT) const {
1502 const TargetRegisterClass *RRC = nullptr;
1503 uint8_t Cost = 1;
1504 switch (VT.SimpleTy) {
1505 default:
1506 return TargetLowering::findRepresentativeClass(TRI, VT);
1507 // Use DPR as representative register class for all floating point
1508 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1509 // the cost is 1 for both f32 and f64.
1510 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1511 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1512 RRC = &ARM::DPRRegClass;
1513 // When NEON is used for SP, only half of the register file is available
1514 // because operations that define both SP and DP results will be constrained
1515 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1516 // coalescing by double-counting the SP regs. See the FIXME above.
1517 if (Subtarget->useNEONForSinglePrecisionFP())
1518 Cost = 2;
1519 break;
1520 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1521 case MVT::v4f32: case MVT::v2f64:
1522 RRC = &ARM::DPRRegClass;
1523 Cost = 2;
1524 break;
1525 case MVT::v4i64:
1526 RRC = &ARM::DPRRegClass;
1527 Cost = 4;
1528 break;
1529 case MVT::v8i64:
1530 RRC = &ARM::DPRRegClass;
1531 Cost = 8;
1532 break;
1533 }
1534 return std::make_pair(RRC, Cost);
1535}
1536
1537const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1538 switch ((ARMISD::NodeType)Opcode) {
1539 case ARMISD::FIRST_NUMBER: break;
1540 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1541 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1542 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1543 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1544 case ARMISD::CALL: return "ARMISD::CALL";
1545 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1546 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1547 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1548 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1549 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1550 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1551 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1552 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1553 case ARMISD::CMP: return "ARMISD::CMP";
1554 case ARMISD::CMN: return "ARMISD::CMN";
1555 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1556 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1557 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1558 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1559 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1560
1561 case ARMISD::CMOV: return "ARMISD::CMOV";
1562 case ARMISD::SUBS: return "ARMISD::SUBS";
1563
1564 case ARMISD::SSAT: return "ARMISD::SSAT";
1565 case ARMISD::USAT: return "ARMISD::USAT";
1566
1567 case ARMISD::ASRL: return "ARMISD::ASRL";
1568 case ARMISD::LSRL: return "ARMISD::LSRL";
1569 case ARMISD::LSLL: return "ARMISD::LSLL";
1570
1571 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1572 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1573 case ARMISD::RRX: return "ARMISD::RRX";
1574
1575 case ARMISD::ADDC: return "ARMISD::ADDC";
1576 case ARMISD::ADDE: return "ARMISD::ADDE";
1577 case ARMISD::SUBC: return "ARMISD::SUBC";
1578 case ARMISD::SUBE: return "ARMISD::SUBE";
1579 case ARMISD::LSLS: return "ARMISD::LSLS";
1580
1581 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1582 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1583 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1584 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1585 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1586
1587 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1588 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1589 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1590
1591 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1592
1593 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1594
1595 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1596
1597 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1598
1599 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1600
1601 case ARMISD::LDRD: return "ARMISD::LDRD";
1602 case ARMISD::STRD: return "ARMISD::STRD";
1603
1604 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1605 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1606
1607 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1608 case ARMISD::VCMP: return "ARMISD::VCMP";
1609 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1610 case ARMISD::VTST: return "ARMISD::VTST";
1611
1612 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1613 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1614 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1615 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1616 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1617 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1618 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1619 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1620 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1621 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1622 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1623 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1624 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1625 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1626 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1627 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1628 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1629 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1630 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1631 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1632 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1633 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1634 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1635 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1636 case ARMISD::VDUP: return "ARMISD::VDUP";
1637 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1638 case ARMISD::VEXT: return "ARMISD::VEXT";
1639 case ARMISD::VREV64: return "ARMISD::VREV64";
1640 case ARMISD::VREV32: return "ARMISD::VREV32";
1641 case ARMISD::VREV16: return "ARMISD::VREV16";
1642 case ARMISD::VZIP: return "ARMISD::VZIP";
1643 case ARMISD::VUZP: return "ARMISD::VUZP";
1644 case ARMISD::VTRN: return "ARMISD::VTRN";
1645 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1646 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1647 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1648 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1649 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1650 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1651 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1652 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1653 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1654 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1655 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1656 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1657 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1658 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1659 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1660 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1661 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1662 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1663 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1664 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1665 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1666 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1667 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1668 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1669 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1670 case ARMISD::BFI: return "ARMISD::BFI";
1671 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1672 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1673 case ARMISD::VBSL: return "ARMISD::VBSL";
1674 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1675 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1676 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1677 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1678 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1679 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1680 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1681 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1682 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1683 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1684 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1685 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1686 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1687 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1688 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1689 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1690 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1691 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1692 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1693 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1694 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1695 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1696 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1697 case ARMISD::WLS: return "ARMISD::WLS";
1698 case ARMISD::LE: return "ARMISD::LE";
1699 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1700 case ARMISD::CSINV: return "ARMISD::CSINV";
1701 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1702 case ARMISD::CSINC: return "ARMISD::CSINC";
1703 }
1704 return nullptr;
1705}
1706
1707EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1708 EVT VT) const {
1709 if (!VT.isVector())
1710 return getPointerTy(DL);
1711
1712 // MVE has a predicate register.
1713 if (Subtarget->hasMVEIntegerOps() &&
1714 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1715 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1716 return VT.changeVectorElementTypeToInteger();
1717}
1718
1719/// getRegClassFor - Return the register class that should be used for the
1720/// specified value type.
1721const TargetRegisterClass *
1722ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1723 (void)isDivergent;
1724 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1725 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1726 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1727 // MVE Q registers.
1728 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1729 if (VT == MVT::v4i64)
1730 return &ARM::QQPRRegClass;
1731 if (VT == MVT::v8i64)
1732 return &ARM::QQQQPRRegClass;
1733 }
1734 return TargetLowering::getRegClassFor(VT);
1735}
1736
1737// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1738// source/dest is aligned and the copy size is large enough. We therefore want
1739// to align such objects passed to memory intrinsics.
1740bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1741 unsigned &PrefAlign) const {
1742 if (!isa<MemIntrinsic>(CI))
1743 return false;
1744 MinSize = 8;
1745 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1746 // cycle faster than 4-byte aligned LDM.
1747 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1748 return true;
1749}
1750
1751// Create a fast isel object.
1752FastISel *
1753ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1754 const TargetLibraryInfo *libInfo) const {
1755 return ARM::createFastISel(funcInfo, libInfo);
1756}
1757
1758Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1759 unsigned NumVals = N->getNumValues();
1760 if (!NumVals)
1761 return Sched::RegPressure;
1762
1763 for (unsigned i = 0; i != NumVals; ++i) {
1764 EVT VT = N->getValueType(i);
1765 if (VT == MVT::Glue || VT == MVT::Other)
1766 continue;
1767 if (VT.isFloatingPoint() || VT.isVector())
1768 return Sched::ILP;
1769 }
1770
1771 if (!N->isMachineOpcode())
1772 return Sched::RegPressure;
1773
1774 // Load are scheduled for latency even if there instruction itinerary
1775 // is not available.
1776 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1777 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1778
1779 if (MCID.getNumDefs() == 0)
1780 return Sched::RegPressure;
1781 if (!Itins->isEmpty() &&
1782 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1783 return Sched::ILP;
1784
1785 return Sched::RegPressure;
1786}
1787
1788//===----------------------------------------------------------------------===//
1789// Lowering Code
1790//===----------------------------------------------------------------------===//
1791
1792static bool isSRL16(const SDValue &Op) {
1793 if (Op.getOpcode() != ISD::SRL)
1794 return false;
1795 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1796 return Const->getZExtValue() == 16;
1797 return false;
1798}
1799
1800static bool isSRA16(const SDValue &Op) {
1801 if (Op.getOpcode() != ISD::SRA)
1802 return false;
1803 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1804 return Const->getZExtValue() == 16;
1805 return false;
1806}
1807
1808static bool isSHL16(const SDValue &Op) {
1809 if (Op.getOpcode() != ISD::SHL)
1810 return false;
1811 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1812 return Const->getZExtValue() == 16;
1813 return false;
1814}
1815
1816// Check for a signed 16-bit value. We special case SRA because it makes it
1817// more simple when also looking for SRAs that aren't sign extending a
1818// smaller value. Without the check, we'd need to take extra care with
1819// checking order for some operations.
1820static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1821 if (isSRA16(Op))
1822 return isSHL16(Op.getOperand(0));
1823 return DAG.ComputeNumSignBits(Op) == 17;
1824}
1825
1826/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1827static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1828 switch (CC) {
1829 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1829)
;
1830 case ISD::SETNE: return ARMCC::NE;
1831 case ISD::SETEQ: return ARMCC::EQ;
1832 case ISD::SETGT: return ARMCC::GT;
1833 case ISD::SETGE: return ARMCC::GE;
1834 case ISD::SETLT: return ARMCC::LT;
1835 case ISD::SETLE: return ARMCC::LE;
1836 case ISD::SETUGT: return ARMCC::HI;
1837 case ISD::SETUGE: return ARMCC::HS;
1838 case ISD::SETULT: return ARMCC::LO;
1839 case ISD::SETULE: return ARMCC::LS;
1840 }
1841}
1842
1843/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1844static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1845 ARMCC::CondCodes &CondCode2) {
1846 CondCode2 = ARMCC::AL;
1847 switch (CC) {
1848 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1848)
;
1849 case ISD::SETEQ:
1850 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1851 case ISD::SETGT:
1852 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1853 case ISD::SETGE:
1854 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1855 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1856 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1857 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1858 case ISD::SETO: CondCode = ARMCC::VC; break;
1859 case ISD::SETUO: CondCode = ARMCC::VS; break;
1860 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1861 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1862 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1863 case ISD::SETLT:
1864 case ISD::SETULT: CondCode = ARMCC::LT; break;
1865 case ISD::SETLE:
1866 case ISD::SETULE: CondCode = ARMCC::LE; break;
1867 case ISD::SETNE:
1868 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1869 }
1870}
1871
1872//===----------------------------------------------------------------------===//
1873// Calling Convention Implementation
1874//===----------------------------------------------------------------------===//
1875
1876/// getEffectiveCallingConv - Get the effective calling convention, taking into
1877/// account presence of floating point hardware and calling convention
1878/// limitations, such as support for variadic functions.
1879CallingConv::ID
1880ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1881 bool isVarArg) const {
1882 switch (CC) {
1883 default:
1884 report_fatal_error("Unsupported calling convention");
1885 case CallingConv::ARM_AAPCS:
1886 case CallingConv::ARM_APCS:
1887 case CallingConv::GHC:
1888 case CallingConv::CFGuard_Check:
1889 return CC;
1890 case CallingConv::PreserveMost:
1891 return CallingConv::PreserveMost;
1892 case CallingConv::ARM_AAPCS_VFP:
1893 case CallingConv::Swift:
1894 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1895 case CallingConv::C:
1896 if (!Subtarget->isAAPCS_ABI())
1897 return CallingConv::ARM_APCS;
1898 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
1899 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1900 !isVarArg)
1901 return CallingConv::ARM_AAPCS_VFP;
1902 else
1903 return CallingConv::ARM_AAPCS;
1904 case CallingConv::Fast:
1905 case CallingConv::CXX_FAST_TLS:
1906 if (!Subtarget->isAAPCS_ABI()) {
1907 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
1908 return CallingConv::Fast;
1909 return CallingConv::ARM_APCS;
1910 } else if (Subtarget->hasVFP2Base() &&
1911 !Subtarget->isThumb1Only() && !isVarArg)
1912 return CallingConv::ARM_AAPCS_VFP;
1913 else
1914 return CallingConv::ARM_AAPCS;
1915 }
1916}
1917
1918CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1919 bool isVarArg) const {
1920 return CCAssignFnForNode(CC, false, isVarArg);
1921}
1922
1923CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1924 bool isVarArg) const {
1925 return CCAssignFnForNode(CC, true, isVarArg);
1926}
1927
1928/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1929/// CallingConvention.
1930CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1931 bool Return,
1932 bool isVarArg) const {
1933 switch (getEffectiveCallingConv(CC, isVarArg)) {
1934 default:
1935 report_fatal_error("Unsupported calling convention");
1936 case CallingConv::ARM_APCS:
1937 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1938 case CallingConv::ARM_AAPCS:
1939 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1940 case CallingConv::ARM_AAPCS_VFP:
1941 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1942 case CallingConv::Fast:
1943 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1944 case CallingConv::GHC:
1945 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1946 case CallingConv::PreserveMost:
1947 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1948 case CallingConv::CFGuard_Check:
1949 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1950 }
1951}
1952
1953/// LowerCallResult - Lower the result values of a call into the
1954/// appropriate copies out of appropriate physical registers.
1955SDValue ARMTargetLowering::LowerCallResult(
1956 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1957 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1958 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1959 SDValue ThisVal) const {
1960 // Assign locations to each value returned by this call.
1961 SmallVector<CCValAssign, 16> RVLocs;
1962 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1963 *DAG.getContext());
1964 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1965
1966 // Copy all of the result registers out of their specified physreg.
1967 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1968 CCValAssign VA = RVLocs[i];
1969
1970 // Pass 'this' value directly from the argument to return value, to avoid
1971 // reg unit interference
1972 if (i == 0 && isThisReturn) {
1973 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1974, __PRETTY_FUNCTION__))
1974 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1974, __PRETTY_FUNCTION__))
;
1975 InVals.push_back(ThisVal);
1976 continue;
1977 }
1978
1979 SDValue Val;
1980 if (VA.needsCustom()) {
1981 // Handle f64 or half of a v2f64.
1982 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1983 InFlag);
1984 Chain = Lo.getValue(1);
1985 InFlag = Lo.getValue(2);
1986 VA = RVLocs[++i]; // skip ahead to next loc
1987 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1988 InFlag);
1989 Chain = Hi.getValue(1);
1990 InFlag = Hi.getValue(2);
1991 if (!Subtarget->isLittle())
1992 std::swap (Lo, Hi);
1993 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1994
1995 if (VA.getLocVT() == MVT::v2f64) {
1996 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1997 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1998 DAG.getConstant(0, dl, MVT::i32));
1999
2000 VA = RVLocs[++i]; // skip ahead to next loc
2001 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2002 Chain = Lo.getValue(1);
2003 InFlag = Lo.getValue(2);
2004 VA = RVLocs[++i]; // skip ahead to next loc
2005 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2006 Chain = Hi.getValue(1);
2007 InFlag = Hi.getValue(2);
2008 if (!Subtarget->isLittle())
2009 std::swap (Lo, Hi);
2010 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2011 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2012 DAG.getConstant(1, dl, MVT::i32));
2013 }
2014 } else {
2015 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2016 InFlag);
2017 Chain = Val.getValue(1);
2018 InFlag = Val.getValue(2);
2019 }
2020
2021 switch (VA.getLocInfo()) {
2022 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2022)
;
2023 case CCValAssign::Full: break;
2024 case CCValAssign::BCvt:
2025 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2026 break;
2027 }
2028
2029 InVals.push_back(Val);
2030 }
2031
2032 return Chain;
2033}
2034
2035/// LowerMemOpCallTo - Store the argument to the stack.
2036SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2037 SDValue Arg, const SDLoc &dl,
2038 SelectionDAG &DAG,
2039 const CCValAssign &VA,
2040 ISD::ArgFlagsTy Flags) const {
2041 unsigned LocMemOffset = VA.getLocMemOffset();
2042 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2043 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2044 StackPtr, PtrOff);
2045 return DAG.getStore(
2046 Chain, dl, Arg, PtrOff,
2047 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2048}
2049
2050void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2051 SDValue Chain, SDValue &Arg,
2052 RegsToPassVector &RegsToPass,
2053 CCValAssign &VA, CCValAssign &NextVA,
2054 SDValue &StackPtr,
2055 SmallVectorImpl<SDValue> &MemOpChains,
2056 ISD::ArgFlagsTy Flags) const {
2057 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2058 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2059 unsigned id = Subtarget->isLittle() ? 0 : 1;
2060 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2061
2062 if (NextVA.isRegLoc())
2063 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2064 else {
2065 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2065, __PRETTY_FUNCTION__))
;
2066 if (!StackPtr.getNode())
2067 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2068 getPointerTy(DAG.getDataLayout()));
2069
2070 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2071 dl, DAG, NextVA,
2072 Flags));
2073 }
2074}
2075
2076/// LowerCall - Lowering a call into a callseq_start <-
2077/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2078/// nodes.
2079SDValue
2080ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2081 SmallVectorImpl<SDValue> &InVals) const {
2082 SelectionDAG &DAG = CLI.DAG;
2083 SDLoc &dl = CLI.DL;
2084 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2085 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2086 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2087 SDValue Chain = CLI.Chain;
2088 SDValue Callee = CLI.Callee;
2089 bool &isTailCall = CLI.IsTailCall;
2090 CallingConv::ID CallConv = CLI.CallConv;
2091 bool doesNotRet = CLI.DoesNotReturn;
2092 bool isVarArg = CLI.IsVarArg;
2093
2094 MachineFunction &MF = DAG.getMachineFunction();
2095 MachineFunction::CallSiteInfo CSInfo;
2096 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2097 bool isThisReturn = false;
2098 bool PreferIndirect = false;
2099
2100 // Disable tail calls if they're not supported.
2101 if (!Subtarget->supportsTailCall())
2102 isTailCall = false;
2103
2104 if (isa<GlobalAddressSDNode>(Callee)) {
2105 // If we're optimizing for minimum size and the function is called three or
2106 // more times in this block, we can improve codesize by calling indirectly
2107 // as BLXr has a 16-bit encoding.
2108 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2109 if (CLI.CS) {
2110 auto *BB = CLI.CS.getParent();
2111 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2112 count_if(GV->users(), [&BB](const User *U) {
2113 return isa<Instruction>(U) &&
2114 cast<Instruction>(U)->getParent() == BB;
2115 }) > 2;
2116 }
2117 }
2118 if (isTailCall) {
2119 // Check if it's really possible to do a tail call.
2120 isTailCall = IsEligibleForTailCallOptimization(
2121 Callee, CallConv, isVarArg, isStructRet,
2122 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2123 PreferIndirect);
2124 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
2125 report_fatal_error("failed to perform tail call elimination on a call "
2126 "site marked musttail");
2127 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2128 // detected sibcalls.
2129 if (isTailCall)
2130 ++NumTailCalls;
2131 }
2132
2133 // Analyze operands of the call, assigning locations to each operand.
2134 SmallVector<CCValAssign, 16> ArgLocs;
2135 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2136 *DAG.getContext());
2137 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2138
2139 // Get a count of how many bytes are to be pushed on the stack.
2140 unsigned NumBytes = CCInfo.getNextStackOffset();
2141
2142 if (isTailCall) {
2143 // For tail calls, memory operands are available in our caller's stack.
2144 NumBytes = 0;
2145 } else {
2146 // Adjust the stack pointer for the new arguments...
2147 // These operations are automatically eliminated by the prolog/epilog pass
2148 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2149 }
2150
2151 SDValue StackPtr =
2152 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2153
2154 RegsToPassVector RegsToPass;
2155 SmallVector<SDValue, 8> MemOpChains;
2156
2157 // Walk the register/memloc assignments, inserting copies/loads. In the case
2158 // of tail call optimization, arguments are handled later.
2159 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2160 i != e;
2161 ++i, ++realArgIdx) {
2162 CCValAssign &VA = ArgLocs[i];
2163 SDValue Arg = OutVals[realArgIdx];
2164 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2165 bool isByVal = Flags.isByVal();
2166
2167 // Promote the value if needed.
2168 switch (VA.getLocInfo()) {
2169 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2169)
;
2170 case CCValAssign::Full: break;
2171 case CCValAssign::SExt:
2172 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2173 break;
2174 case CCValAssign::ZExt:
2175 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2176 break;
2177 case CCValAssign::AExt:
2178 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2179 break;
2180 case CCValAssign::BCvt:
2181 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2182 break;
2183 }
2184
2185 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2186 if (VA.needsCustom()) {
2187 if (VA.getLocVT() == MVT::v2f64) {
2188 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2189 DAG.getConstant(0, dl, MVT::i32));
2190 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2191 DAG.getConstant(1, dl, MVT::i32));
2192
2193 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
2194 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2195
2196 VA = ArgLocs[++i]; // skip ahead to next loc
2197 if (VA.isRegLoc()) {
2198 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
2199 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2200 } else {
2201 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2201, __PRETTY_FUNCTION__))
;
2202
2203 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
2204 dl, DAG, VA, Flags));
2205 }
2206 } else {
2207 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2208 StackPtr, MemOpChains, Flags);
2209 }
2210 } else if (VA.isRegLoc()) {
2211 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2212 Outs[0].VT == MVT::i32) {
2213 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2214, __PRETTY_FUNCTION__))
2214 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2214, __PRETTY_FUNCTION__))
;
2215 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2216, __PRETTY_FUNCTION__))
2216 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2216, __PRETTY_FUNCTION__))
;
2217 isThisReturn = true;
2218 }
2219 const TargetOptions &Options = DAG.getTarget().Options;
2220 if (Options.EnableDebugEntryValues)
2221 CSInfo.emplace_back(VA.getLocReg(), i);
2222 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2223 } else if (isByVal) {
2224 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2224, __PRETTY_FUNCTION__))
;
2225 unsigned offset = 0;
2226
2227 // True if this byval aggregate will be split between registers
2228 // and memory.
2229 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2230 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2231
2232 if (CurByValIdx < ByValArgsCount) {
2233
2234 unsigned RegBegin, RegEnd;
2235 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2236
2237 EVT PtrVT =
2238 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2239 unsigned int i, j;
2240 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2241 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2242 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2243 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
2244 MachinePointerInfo(),
2245 DAG.InferPtrAlignment(AddArg));
2246 MemOpChains.push_back(Load.getValue(1));
2247 RegsToPass.push_back(std::make_pair(j, Load));
2248 }
2249
2250 // If parameter size outsides register area, "offset" value
2251 // helps us to calculate stack slot for remained part properly.
2252 offset = RegEnd - RegBegin;
2253
2254 CCInfo.nextInRegsParam();
2255 }
2256
2257 if (Flags.getByValSize() > 4*offset) {
2258 auto PtrVT = getPointerTy(DAG.getDataLayout());
2259 unsigned LocMemOffset = VA.getLocMemOffset();
2260 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2261 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2262 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2263 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2264 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2265 MVT::i32);
2266 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
2267 MVT::i32);
2268
2269 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2270 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2271 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2272 Ops));
2273 }
2274 } else if (!isTailCall) {
2275 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2275, __PRETTY_FUNCTION__))
;
2276
2277 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2278 dl, DAG, VA, Flags));
2279 }
2280 }
2281
2282 if (!MemOpChains.empty())
2283 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2284
2285 // Build a sequence of copy-to-reg nodes chained together with token chain
2286 // and flag operands which copy the outgoing args into the appropriate regs.
2287 SDValue InFlag;
2288 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2289 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2290 RegsToPass[i].second, InFlag);
2291 InFlag = Chain.getValue(1);
2292 }
2293
2294 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2295 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2296 // node so that legalize doesn't hack it.
2297 bool isDirect = false;
2298
2299 const TargetMachine &TM = getTargetMachine();
2300 const Module *Mod = MF.getFunction().getParent();
2301 const GlobalValue *GV = nullptr;
2302 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2303 GV = G->getGlobal();
2304 bool isStub =
2305 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2306
2307 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2308 bool isLocalARMFunc = false;
2309 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2310 auto PtrVt = getPointerTy(DAG.getDataLayout());
2311
2312 if (Subtarget->genLongCalls()) {
2313 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2314, __PRETTY_FUNCTION__))
2314 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2314, __PRETTY_FUNCTION__))
;
2315 // Handle a global address or an external symbol. If it's not one of
2316 // those, the target's already in a register, so we don't need to do
2317 // anything extra.
2318 if (isa<GlobalAddressSDNode>(Callee)) {
2319 // Create a constant pool entry for the callee address
2320 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2321 ARMConstantPoolValue *CPV =
2322 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2323
2324 // Get the address of the callee into a register
2325 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2326 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2327 Callee = DAG.getLoad(
2328 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2329 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2330 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2331 const char *Sym = S->getSymbol();
2332
2333 // Create a constant pool entry for the callee address
2334 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2335 ARMConstantPoolValue *CPV =
2336 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2337 ARMPCLabelIndex, 0);
2338 // Get the address of the callee into a register
2339 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2340 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2341 Callee = DAG.getLoad(
2342 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2343 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2344 }
2345 } else if (isa<GlobalAddressSDNode>(Callee)) {
2346 if (!PreferIndirect) {
2347 isDirect = true;
2348 bool isDef = GV->isStrongDefinitionForLinker();
2349
2350 // ARM call to a local ARM function is predicable.
2351 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2352 // tBX takes a register source operand.
2353 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2354 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2354, __PRETTY_FUNCTION__))
;
2355 Callee = DAG.getNode(
2356 ARMISD::WrapperPIC, dl, PtrVt,
2357 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2358 Callee = DAG.getLoad(
2359 PtrVt, dl, DAG.getEntryNode(), Callee,
2360 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2361 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2362 MachineMemOperand::MOInvariant);
2363 } else if (Subtarget->isTargetCOFF()) {
2364 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2365, __PRETTY_FUNCTION__))
2365 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2365, __PRETTY_FUNCTION__))
;
2366 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2367 if (GV->hasDLLImportStorageClass())
2368 TargetFlags = ARMII::MO_DLLIMPORT;
2369 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2370 TargetFlags = ARMII::MO_COFFSTUB;
2371 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2372 TargetFlags);
2373 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2374 Callee =
2375 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2376 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2377 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2378 } else {
2379 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2380 }
2381 }
2382 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2383 isDirect = true;
2384 // tBX takes a register source operand.
2385 const char *Sym = S->getSymbol();
2386 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2387 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2388 ARMConstantPoolValue *CPV =
2389 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2390 ARMPCLabelIndex, 4);
2391 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2392 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2393 Callee = DAG.getLoad(
2394 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2395 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2396 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2397 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2398 } else {
2399 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2400 }
2401 }
2402
2403 // FIXME: handle tail calls differently.
2404 unsigned CallOpc;
2405 if (Subtarget->isThumb()) {
2406 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2407 CallOpc = ARMISD::CALL_NOLINK;
2408 else
2409 CallOpc = ARMISD::CALL;
2410 } else {
2411 if (!isDirect && !Subtarget->hasV5TOps())
2412 CallOpc = ARMISD::CALL_NOLINK;
2413 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2414 // Emit regular call when code size is the priority
2415 !Subtarget->hasMinSize())
2416 // "mov lr, pc; b _foo" to avoid confusing the RSP
2417 CallOpc = ARMISD::CALL_NOLINK;
2418 else
2419 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2420 }
2421
2422 std::vector<SDValue> Ops;
2423 Ops.push_back(Chain);
2424 Ops.push_back(Callee);
2425
2426 // Add argument registers to the end of the list so that they are known live
2427 // into the call.
2428 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2429 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2430 RegsToPass[i].second.getValueType()));
2431
2432 // Add a register mask operand representing the call-preserved registers.
2433 if (!isTailCall) {
2434 const uint32_t *Mask;
2435 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2436 if (isThisReturn) {
2437 // For 'this' returns, use the R0-preserving mask if applicable
2438 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2439 if (!Mask) {
2440 // Set isThisReturn to false if the calling convention is not one that
2441 // allows 'returned' to be modeled in this way, so LowerCallResult does
2442 // not try to pass 'this' straight through
2443 isThisReturn = false;
2444 Mask = ARI->getCallPreservedMask(MF, CallConv);
2445 }
2446 } else
2447 Mask = ARI->getCallPreservedMask(MF, CallConv);
2448
2449 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2449, __PRETTY_FUNCTION__))
;
2450 Ops.push_back(DAG.getRegisterMask(Mask));
2451 }
2452
2453 if (InFlag.getNode())
2454 Ops.push_back(InFlag);
2455
2456 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2457 if (isTailCall) {
2458 MF.getFrameInfo().setHasTailCall();
2459 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2460 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2461 return Ret;
2462 }
2463
2464 // Returns a chain and a flag for retval copy to use.
2465 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2466 InFlag = Chain.getValue(1);
2467 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2468
2469 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2470 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2471 if (!Ins.empty())
2472 InFlag = Chain.getValue(1);
2473
2474 // Handle result values, copying them out of physregs into vregs that we
2475 // return.
2476 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2477 InVals, isThisReturn,
2478 isThisReturn ? OutVals[0] : SDValue());
2479}
2480
2481/// HandleByVal - Every parameter *after* a byval parameter is passed
2482/// on the stack. Remember the next parameter register to allocate,
2483/// and then confiscate the rest of the parameter registers to insure
2484/// this.
2485void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2486 unsigned Align) const {
2487 // Byval (as with any stack) slots are always at least 4 byte aligned.
2488 Align = std::max(Align, 4U);
2489
2490 unsigned Reg = State->AllocateReg(GPRArgRegs);
2491 if (!Reg)
2492 return;
2493
2494 unsigned AlignInRegs = Align / 4;
2495 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2496 for (unsigned i = 0; i < Waste; ++i)
2497 Reg = State->AllocateReg(GPRArgRegs);
2498
2499 if (!Reg)
2500 return;
2501
2502 unsigned Excess = 4 * (ARM::R4 - Reg);
2503
2504 // Special case when NSAA != SP and parameter size greater than size of
2505 // all remained GPR regs. In that case we can't split parameter, we must
2506 // send it to stack. We also must set NCRN to R4, so waste all
2507 // remained registers.
2508 const unsigned NSAAOffset = State->getNextStackOffset();
2509 if (NSAAOffset != 0 && Size > Excess) {
2510 while (State->AllocateReg(GPRArgRegs))
2511 ;
2512 return;
2513 }
2514
2515 // First register for byval parameter is the first register that wasn't
2516 // allocated before this method call, so it would be "reg".
2517 // If parameter is small enough to be saved in range [reg, r4), then
2518 // the end (first after last) register would be reg + param-size-in-regs,
2519 // else parameter would be splitted between registers and stack,
2520 // end register would be r4 in this case.
2521 unsigned ByValRegBegin = Reg;
2522 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2523 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2524 // Note, first register is allocated in the beginning of function already,
2525 // allocate remained amount of registers we need.
2526 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2527 State->AllocateReg(GPRArgRegs);
2528 // A byval parameter that is split between registers and memory needs its
2529 // size truncated here.
2530 // In the case where the entire structure fits in registers, we set the
2531 // size in memory to zero.
2532 Size = std::max<int>(Size - Excess, 0);
2533}
2534
2535/// MatchingStackOffset - Return true if the given stack call argument is
2536/// already available in the same position (relatively) of the caller's
2537/// incoming argument stack.
2538static
2539bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2540 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2541 const TargetInstrInfo *TII) {
2542 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2543 int FI = std::numeric_limits<int>::max();
2544 if (Arg.getOpcode() == ISD::CopyFromReg) {
2545 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2546 if (!Register::isVirtualRegister(VR))
2547 return false;
2548 MachineInstr *Def = MRI->getVRegDef(VR);
2549 if (!Def)
2550 return false;
2551 if (!Flags.isByVal()) {
2552 if (!TII->isLoadFromStackSlot(*Def, FI))
2553 return false;
2554 } else {
2555 return false;
2556 }
2557 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2558 if (Flags.isByVal())
2559 // ByVal argument is passed in as a pointer but it's now being
2560 // dereferenced. e.g.
2561 // define @foo(%struct.X* %A) {
2562 // tail call @bar(%struct.X* byval %A)
2563 // }
2564 return false;
2565 SDValue Ptr = Ld->getBasePtr();
2566 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2567 if (!FINode)
2568 return false;
2569 FI = FINode->getIndex();
2570 } else
2571 return false;
2572
2573 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2573, __PRETTY_FUNCTION__))
;
2574 if (!MFI.isFixedObjectIndex(FI))
2575 return false;
2576 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2577}
2578
2579/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2580/// for tail call optimization. Targets which want to do tail call
2581/// optimization should implement this function.
2582bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2583 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2584 bool isCalleeStructRet, bool isCallerStructRet,
2585 const SmallVectorImpl<ISD::OutputArg> &Outs,
2586 const SmallVectorImpl<SDValue> &OutVals,
2587 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2588 const bool isIndirect) const {
2589 MachineFunction &MF = DAG.getMachineFunction();
2590 const Function &CallerF = MF.getFunction();
2591 CallingConv::ID CallerCC = CallerF.getCallingConv();
2592
2593 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2593, __PRETTY_FUNCTION__))
;
2594
2595 // Indirect tail calls cannot be optimized for Thumb1 if the args
2596 // to the call take up r0-r3. The reason is that there are no legal registers
2597 // left to hold the pointer to the function to be called.
2598 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2599 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2600 return false;
2601
2602 // Look for obvious safe cases to perform tail call optimization that do not
2603 // require ABI changes. This is what gcc calls sibcall.
2604
2605 // Exception-handling functions need a special set of instructions to indicate
2606 // a return to the hardware. Tail-calling another function would probably
2607 // break this.
2608 if (CallerF.hasFnAttribute("interrupt"))
2609 return false;
2610
2611 // Also avoid sibcall optimization if either caller or callee uses struct
2612 // return semantics.
2613 if (isCalleeStructRet || isCallerStructRet)
2614 return false;
2615
2616 // Externally-defined functions with weak linkage should not be
2617 // tail-called on ARM when the OS does not support dynamic
2618 // pre-emption of symbols, as the AAELF spec requires normal calls
2619 // to undefined weak functions to be replaced with a NOP or jump to the
2620 // next instruction. The behaviour of branch instructions in this
2621 // situation (as used for tail calls) is implementation-defined, so we
2622 // cannot rely on the linker replacing the tail call with a return.
2623 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2624 const GlobalValue *GV = G->getGlobal();
2625 const Triple &TT = getTargetMachine().getTargetTriple();
2626 if (GV->hasExternalWeakLinkage() &&
2627 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2628 return false;
2629 }
2630
2631 // Check that the call results are passed in the same way.
2632 LLVMContext &C = *DAG.getContext();
2633 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2634 CCAssignFnForReturn(CalleeCC, isVarArg),
2635 CCAssignFnForReturn(CallerCC, isVarArg)))
2636 return false;
2637 // The callee has to preserve all registers the caller needs to preserve.
2638 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2639 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2640 if (CalleeCC != CallerCC) {
2641 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2642 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2643 return false;
2644 }
2645
2646 // If Caller's vararg or byval argument has been split between registers and
2647 // stack, do not perform tail call, since part of the argument is in caller's
2648 // local frame.
2649 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2650 if (AFI_Caller->getArgRegsSaveSize())
2651 return false;
2652
2653 // If the callee takes no arguments then go on to check the results of the
2654 // call.
2655 if (!Outs.empty()) {
2656 // Check if stack adjustment is needed. For now, do not do this if any
2657 // argument is passed on the stack.
2658 SmallVector<CCValAssign, 16> ArgLocs;
2659 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2660 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2661 if (CCInfo.getNextStackOffset()) {
2662 // Check if the arguments are already laid out in the right way as
2663 // the caller's fixed stack objects.
2664 MachineFrameInfo &MFI = MF.getFrameInfo();
2665 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2666 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2667 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2668 i != e;
2669 ++i, ++realArgIdx) {
2670 CCValAssign &VA = ArgLocs[i];
2671 EVT RegVT = VA.getLocVT();
2672 SDValue Arg = OutVals[realArgIdx];
2673 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2674 if (VA.getLocInfo() == CCValAssign::Indirect)
2675 return false;
2676 if (VA.needsCustom()) {
2677 // f64 and vector types are split into multiple registers or
2678 // register/stack-slot combinations. The types will not match
2679 // the registers; give up on memory f64 refs until we figure
2680 // out what to do about this.
2681 if (!VA.isRegLoc())
2682 return false;
2683 if (!ArgLocs[++i].isRegLoc())
2684 return false;
2685 if (RegVT == MVT::v2f64) {
2686 if (!ArgLocs[++i].isRegLoc())
2687 return false;
2688 if (!ArgLocs[++i].isRegLoc())
2689 return false;
2690 }
2691 } else if (!VA.isRegLoc()) {
2692 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2693 MFI, MRI, TII))
2694 return false;
2695 }
2696 }
2697 }
2698
2699 const MachineRegisterInfo &MRI = MF.getRegInfo();
2700 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2701 return false;
2702 }
2703
2704 return true;
2705}
2706
2707bool
2708ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2709 MachineFunction &MF, bool isVarArg,
2710 const SmallVectorImpl<ISD::OutputArg> &Outs,
2711 LLVMContext &Context) const {
2712 SmallVector<CCValAssign, 16> RVLocs;
2713 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2714 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2715}
2716
2717static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2718 const SDLoc &DL, SelectionDAG &DAG) {
2719 const MachineFunction &MF = DAG.getMachineFunction();
2720 const Function &F = MF.getFunction();
2721
2722 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2723
2724 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2725 // version of the "preferred return address". These offsets affect the return
2726 // instruction if this is a return from PL1 without hypervisor extensions.
2727 // IRQ/FIQ: +4 "subs pc, lr, #4"
2728 // SWI: 0 "subs pc, lr, #0"
2729 // ABORT: +4 "subs pc, lr, #4"
2730 // UNDEF: +4/+2 "subs pc, lr, #0"
2731 // UNDEF varies depending on where the exception came from ARM or Thumb
2732 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2733
2734 int64_t LROffset;
2735 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2736 IntKind == "ABORT")
2737 LROffset = 4;
2738 else if (IntKind == "SWI" || IntKind == "UNDEF")
2739 LROffset = 0;
2740 else
2741 report_fatal_error("Unsupported interrupt attribute. If present, value "
2742 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2743
2744 RetOps.insert(RetOps.begin() + 1,
2745 DAG.getConstant(LROffset, DL, MVT::i32, false));
2746
2747 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2748}
2749
2750SDValue
2751ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2752 bool isVarArg,
2753 const SmallVectorImpl<ISD::OutputArg> &Outs,
2754 const SmallVectorImpl<SDValue> &OutVals,
2755 const SDLoc &dl, SelectionDAG &DAG) const {
2756 // CCValAssign - represent the assignment of the return value to a location.
2757 SmallVector<CCValAssign, 16> RVLocs;
2758
2759 // CCState - Info about the registers and stack slots.
2760 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2761 *DAG.getContext());
2762
2763 // Analyze outgoing return values.
2764 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2765
2766 SDValue Flag;
2767 SmallVector<SDValue, 4> RetOps;
2768 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2769 bool isLittleEndian = Subtarget->isLittle();
2770
2771 MachineFunction &MF = DAG.getMachineFunction();
2772 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2773 AFI->setReturnRegsCount(RVLocs.size());
2774
2775 // Copy the result values into the output registers.
2776 for (unsigned i = 0, realRVLocIdx = 0;
2777 i != RVLocs.size();
2778 ++i, ++realRVLocIdx) {
2779 CCValAssign &VA = RVLocs[i];
2780 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2780, __PRETTY_FUNCTION__))
;
2781
2782 SDValue Arg = OutVals[realRVLocIdx];
2783 bool ReturnF16 = false;
2784
2785 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2786 // Half-precision return values can be returned like this:
2787 //
2788 // t11 f16 = fadd ...
2789 // t12: i16 = bitcast t11
2790 // t13: i32 = zero_extend t12
2791 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2792 //
2793 // to avoid code generation for bitcasts, we simply set Arg to the node
2794 // that produces the f16 value, t11 in this case.
2795 //
2796 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2797 SDValue ZE = Arg.getOperand(0);
2798 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2799 SDValue BC = ZE.getOperand(0);
2800 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2801 Arg = BC.getOperand(0);
2802 ReturnF16 = true;
2803 }
2804 }
2805 }
2806 }
2807
2808 switch (VA.getLocInfo()) {
2809 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2809)
;
2810 case CCValAssign::Full: break;
2811 case CCValAssign::BCvt:
2812 if (!ReturnF16)
2813 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2814 break;
2815 }
2816
2817 if (VA.needsCustom()) {
2818 if (VA.getLocVT() == MVT::v2f64) {
2819 // Extract the first half and return it in two registers.
2820 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2821 DAG.getConstant(0, dl, MVT::i32));
2822 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2823 DAG.getVTList(MVT::i32, MVT::i32), Half);
2824
2825 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2826 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2827 Flag);
2828 Flag = Chain.getValue(1);
2829 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2830 VA = RVLocs[++i]; // skip ahead to next loc
2831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2832 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2833 Flag);
2834 Flag = Chain.getValue(1);
2835 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2836 VA = RVLocs[++i]; // skip ahead to next loc
2837
2838 // Extract the 2nd half and fall through to handle it as an f64 value.
2839 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2840 DAG.getConstant(1, dl, MVT::i32));
2841 }
2842 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2843 // available.
2844 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2845 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2846 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2847 fmrrd.getValue(isLittleEndian ? 0 : 1),
2848 Flag);
2849 Flag = Chain.getValue(1);
2850 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2851 VA = RVLocs[++i]; // skip ahead to next loc
2852 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2853 fmrrd.getValue(isLittleEndian ? 1 : 0),
2854 Flag);
2855 } else
2856 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2857
2858 // Guarantee that all emitted copies are
2859 // stuck together, avoiding something bad.
2860 Flag = Chain.getValue(1);
2861 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2862 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2863 }
2864 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2865 const MCPhysReg *I =
2866 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2867 if (I) {
2868 for (; *I; ++I) {
2869 if (ARM::GPRRegClass.contains(*I))
2870 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2871 else if (ARM::DPRRegClass.contains(*I))
2872 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2873 else
2874 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2874)
;
2875 }
2876 }
2877
2878 // Update chain and glue.
2879 RetOps[0] = Chain;
2880 if (Flag.getNode())
2881 RetOps.push_back(Flag);
2882
2883 // CPUs which aren't M-class use a special sequence to return from
2884 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2885 // though we use "subs pc, lr, #N").
2886 //
2887 // M-class CPUs actually use a normal return sequence with a special
2888 // (hardware-provided) value in LR, so the normal code path works.
2889 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2890 !Subtarget->isMClass()) {
2891 if (Subtarget->isThumb1Only())
2892 report_fatal_error("interrupt attribute is not supported in Thumb1");
2893 return LowerInterruptReturn(RetOps, dl, DAG);
2894 }
2895
2896 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2897}
2898
2899bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2900 if (N->getNumValues() != 1)
2901 return false;
2902 if (!N->hasNUsesOfValue(1, 0))
2903 return false;
2904
2905 SDValue TCChain = Chain;
2906 SDNode *Copy = *N->use_begin();
2907 if (Copy->getOpcode() == ISD::CopyToReg) {
2908 // If the copy has a glue operand, we conservatively assume it isn't safe to
2909 // perform a tail call.
2910 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2911 return false;
2912 TCChain = Copy->getOperand(0);
2913 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2914 SDNode *VMov = Copy;
2915 // f64 returned in a pair of GPRs.
2916 SmallPtrSet<SDNode*, 2> Copies;
2917 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2918 UI != UE; ++UI) {
2919 if (UI->getOpcode() != ISD::CopyToReg)
2920 return false;
2921 Copies.insert(*UI);
2922 }
2923 if (Copies.size() > 2)
2924 return false;
2925
2926 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2927 UI != UE; ++UI) {
2928 SDValue UseChain = UI->getOperand(0);
2929 if (Copies.count(UseChain.getNode()))
2930 // Second CopyToReg
2931 Copy = *UI;
2932 else {
2933 // We are at the top of this chain.
2934 // If the copy has a glue operand, we conservatively assume it
2935 // isn't safe to perform a tail call.
2936 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2937 return false;
2938 // First CopyToReg
2939 TCChain = UseChain;
2940 }
2941 }
2942 } else if (Copy->getOpcode() == ISD::BITCAST) {
2943 // f32 returned in a single GPR.
2944 if (!Copy->hasOneUse())
2945 return false;
2946 Copy = *Copy->use_begin();
2947 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2948 return false;
2949 // If the copy has a glue operand, we conservatively assume it isn't safe to
2950 // perform a tail call.
2951 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2952 return false;
2953 TCChain = Copy->getOperand(0);
2954 } else {
2955 return false;
2956 }
2957
2958 bool HasRet = false;
2959 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2960 UI != UE; ++UI) {
2961 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2962 UI->getOpcode() != ARMISD::INTRET_FLAG)
2963 return false;
2964 HasRet = true;
2965 }
2966
2967 if (!HasRet)
2968 return false;
2969
2970 Chain = TCChain;
2971 return true;
2972}
2973
2974bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2975 if (!Subtarget->supportsTailCall())
2976 return false;
2977
2978 if (!CI->isTailCall())
2979 return false;
2980
2981 return true;
2982}
2983
2984// Trying to write a 64 bit value so need to split into two 32 bit values first,
2985// and pass the lower and high parts through.
2986static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2987 SDLoc DL(Op);
2988 SDValue WriteValue = Op->getOperand(2);
2989
2990 // This function is only supposed to be called for i64 type argument.
2991 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2992, __PRETTY_FUNCTION__))
2992 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2992, __PRETTY_FUNCTION__))
;
2993
2994 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2995 DAG.getConstant(0, DL, MVT::i32));
2996 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2997 DAG.getConstant(1, DL, MVT::i32));
2998 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2999 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3000}
3001
3002// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3003// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3004// one of the above mentioned nodes. It has to be wrapped because otherwise
3005// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3006// be used to form addressing mode. These wrapped nodes will be selected
3007// into MOVi.
3008SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3009 SelectionDAG &DAG) const {
3010 EVT PtrVT = Op.getValueType();
3011 // FIXME there is no actual debug info here
3012 SDLoc dl(Op);
3013 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3014 SDValue Res;
3015
3016 // When generating execute-only code Constant Pools must be promoted to the
3017 // global data section. It's a bit ugly that we can't share them across basic
3018 // blocks, but this way we guarantee that execute-only behaves correct with
3019 // position-independent addressing modes.
3020 if (Subtarget->genExecuteOnly()) {
3021 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3022 auto T = const_cast<Type*>(CP->getType());
3023 auto C = const_cast<Constant*>(CP->getConstVal());
3024 auto M = const_cast<Module*>(DAG.getMachineFunction().
3025 getFunction().getParent());
3026 auto GV = new GlobalVariable(
3027 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3028 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3029 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3030 Twine(AFI->createPICLabelUId())
3031 );
3032 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3033 dl, PtrVT);
3034 return LowerGlobalAddress(GA, DAG);
3035 }
3036
3037 if (CP->isMachineConstantPoolEntry())
3038 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
3039 CP->getAlignment());
3040 else
3041 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
3042 CP->getAlignment());
3043 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3044}
3045
3046unsigned ARMTargetLowering::getJumpTableEncoding() const {
3047 return MachineJumpTableInfo::EK_Inline;
3048}
3049
3050SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3051 SelectionDAG &DAG) const {
3052 MachineFunction &MF = DAG.getMachineFunction();
3053 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3054 unsigned ARMPCLabelIndex = 0;
3055 SDLoc DL(Op);
3056 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3057 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3058 SDValue CPAddr;
3059 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3060 if (!IsPositionIndependent) {
3061 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
3062 } else {
3063 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3064 ARMPCLabelIndex = AFI->createPICLabelUId();
3065 ARMConstantPoolValue *CPV =
3066 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3067 ARMCP::CPBlockAddress, PCAdj);
3068 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3069 }
3070 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3071 SDValue Result = DAG.getLoad(
3072 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3073 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3074 if (!IsPositionIndependent)
3075 return Result;
3076 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3077 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3078}
3079
3080/// Convert a TLS address reference into the correct sequence of loads
3081/// and calls to compute the variable's address for Darwin, and return an
3082/// SDValue containing the final node.
3083
3084/// Darwin only has one TLS scheme which must be capable of dealing with the
3085/// fully general situation, in the worst case. This means:
3086/// + "extern __thread" declaration.
3087/// + Defined in a possibly unknown dynamic library.
3088///
3089/// The general system is that each __thread variable has a [3 x i32] descriptor
3090/// which contains information used by the runtime to calculate the address. The
3091/// only part of this the compiler needs to know about is the first word, which
3092/// contains a function pointer that must be called with the address of the
3093/// entire descriptor in "r0".
3094///
3095/// Since this descriptor may be in a different unit, in general access must
3096/// proceed along the usual ARM rules. A common sequence to produce is:
3097///
3098/// movw rT1, :lower16:_var$non_lazy_ptr
3099/// movt rT1, :upper16:_var$non_lazy_ptr
3100/// ldr r0, [rT1]
3101/// ldr rT2, [r0]
3102/// blx rT2
3103/// [...address now in r0...]
3104SDValue
3105ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3106 SelectionDAG &DAG) const {
3107 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3108, __PRETTY_FUNCTION__))
3108 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3108, __PRETTY_FUNCTION__))
;
3109 SDLoc DL(Op);
3110
3111 // First step is to get the address of the actua global symbol. This is where
3112 // the TLS descriptor lives.
3113 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3114
3115 // The first entry in the descriptor is a function pointer that we must call
3116 // to obtain the address of the variable.
3117 SDValue Chain = DAG.getEntryNode();
3118 SDValue FuncTLVGet = DAG.getLoad(
3119 MVT::i32, DL, Chain, DescAddr,
3120 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
3121 /* Alignment = */ 4,
3122 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3123 MachineMemOperand::MOInvariant);
3124 Chain = FuncTLVGet.getValue(1);
3125
3126 MachineFunction &F = DAG.getMachineFunction();
3127 MachineFrameInfo &MFI = F.getFrameInfo();
3128 MFI.setAdjustsStack(true);
3129
3130 // TLS calls preserve all registers except those that absolutely must be
3131 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3132 // silly).
3133 auto TRI =
3134 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3135 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3136 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3137
3138 // Finally, we can make the call. This is just a degenerate version of a
3139 // normal AArch64 call node: r0 takes the address of the descriptor, and
3140 // returns the address of the variable in this thread.
3141 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3142 Chain =
3143 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3144 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3145 DAG.getRegisterMask(Mask), Chain.getValue(1));
3146 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3147}
3148
3149SDValue
3150ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3151 SelectionDAG &DAG) const {
3152 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3152, __PRETTY_FUNCTION__))
;
3153
3154 SDValue Chain = DAG.getEntryNode();
3155 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3156 SDLoc DL(Op);
3157
3158 // Load the current TEB (thread environment block)
3159 SDValue Ops[] = {Chain,
3160 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3161 DAG.getTargetConstant(15, DL, MVT::i32),
3162 DAG.getTargetConstant(0, DL, MVT::i32),
3163 DAG.getTargetConstant(13, DL, MVT::i32),
3164 DAG.getTargetConstant(0, DL, MVT::i32),
3165 DAG.getTargetConstant(2, DL, MVT::i32)};
3166 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3167 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3168
3169 SDValue TEB = CurrentTEB.getValue(0);
3170 Chain = CurrentTEB.getValue(1);
3171
3172 // Load the ThreadLocalStoragePointer from the TEB
3173 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3174 SDValue TLSArray =
3175 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3176 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3177
3178 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3179 // offset into the TLSArray.
3180
3181 // Load the TLS index from the C runtime
3182 SDValue TLSIndex =
3183 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3184 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3185 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3186
3187 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3188 DAG.getConstant(2, DL, MVT::i32));
3189 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3190 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3191 MachinePointerInfo());
3192
3193 // Get the offset of the start of the .tls section (section base)
3194 const auto *GA = cast<GlobalAddressSDNode>(Op);
3195 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3196 SDValue Offset = DAG.getLoad(
3197 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3198 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
3199 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3200
3201 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3202}
3203
3204// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3205SDValue
3206ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3207 SelectionDAG &DAG) const {
3208 SDLoc dl(GA);
3209 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3210 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3211 MachineFunction &MF = DAG.getMachineFunction();
3212 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3213 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3214 ARMConstantPoolValue *CPV =
3215 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3216 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3217 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3218 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3219 Argument = DAG.getLoad(
3220 PtrVT, dl, DAG.getEntryNode(), Argument,
3221 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3222 SDValue Chain = Argument.getValue(1);
3223
3224 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3225 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3226
3227 // call __tls_get_addr.
3228 ArgListTy Args;
3229 ArgListEntry Entry;
3230 Entry.Node = Argument;
3231 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3232 Args.push_back(Entry);
3233
3234 // FIXME: is there useful debug info available here?
3235 TargetLowering::CallLoweringInfo CLI(DAG);
3236 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3237 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3238 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3239
3240 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3241 return CallResult.first;
3242}
3243
3244// Lower ISD::GlobalTLSAddress using the "initial exec" or
3245// "local exec" model.
3246SDValue
3247ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3248 SelectionDAG &DAG,
3249 TLSModel::Model model) const {
3250 const GlobalValue *GV = GA->getGlobal();
3251 SDLoc dl(GA);
3252 SDValue Offset;
3253 SDValue Chain = DAG.getEntryNode();
3254 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3255 // Get the Thread Pointer
3256 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3257
3258 if (model == TLSModel::InitialExec) {
3259 MachineFunction &MF = DAG.getMachineFunction();
3260 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3261 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3262 // Initial exec model.
3263 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3264 ARMConstantPoolValue *CPV =
3265 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3266 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3267 true);
3268 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3269 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3270 Offset = DAG.getLoad(
3271 PtrVT, dl, Chain, Offset,
3272 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3273 Chain = Offset.getValue(1);
3274
3275 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3276 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3277
3278 Offset = DAG.getLoad(
3279 PtrVT, dl, Chain, Offset,
3280 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3281 } else {
3282 // local exec model
3283 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3283, __PRETTY_FUNCTION__))
;
3284 ARMConstantPoolValue *CPV =
3285 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3286 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3287 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3288 Offset = DAG.getLoad(
3289 PtrVT, dl, Chain, Offset,
3290 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3291 }
3292
3293 // The address of the thread local variable is the add of the thread
3294 // pointer with the offset of the variable.
3295 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3296}
3297
3298SDValue
3299ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3300 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3301 if (DAG.getTarget().useEmulatedTLS())
3302 return LowerToTLSEmulatedModel(GA, DAG);
3303
3304 if (Subtarget->isTargetDarwin())
3305 return LowerGlobalTLSAddressDarwin(Op, DAG);
3306
3307 if (Subtarget->isTargetWindows())
3308 return LowerGlobalTLSAddressWindows(Op, DAG);
3309
3310 // TODO: implement the "local dynamic" model
3311 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3311, __PRETTY_FUNCTION__))
;
3312 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3313
3314 switch (model) {
3315 case TLSModel::GeneralDynamic:
3316 case TLSModel::LocalDynamic:
3317 return LowerToTLSGeneralDynamicModel(GA, DAG);
3318 case TLSModel::InitialExec:
3319 case TLSModel::LocalExec:
3320 return LowerToTLSExecModels(GA, DAG, model);
3321 }
3322 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3322)
;
3323}
3324
3325/// Return true if all users of V are within function F, looking through
3326/// ConstantExprs.
3327static bool allUsersAreInFunction(const Value *V, const Function *F) {
3328 SmallVector<const User*,4> Worklist;
3329 for (auto *U : V->users())
3330 Worklist.push_back(U);
3331 while (!Worklist.empty()) {
3332 auto *U = Worklist.pop_back_val();
3333 if (isa<ConstantExpr>(U)) {
3334 for (auto *UU : U->users())
3335 Worklist.push_back(UU);
3336 continue;
3337 }
3338
3339 auto *I = dyn_cast<Instruction>(U);
3340 if (!I || I->getParent()->getParent() != F)
3341 return false;
3342 }
3343 return true;
3344}
3345
3346static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3347 const GlobalValue *GV, SelectionDAG &DAG,
3348 EVT PtrVT, const SDLoc &dl) {
3349 // If we're creating a pool entry for a constant global with unnamed address,
3350 // and the global is small enough, we can emit it inline into the constant pool
3351 // to save ourselves an indirection.
3352 //
3353 // This is a win if the constant is only used in one function (so it doesn't
3354 // need to be duplicated) or duplicating the constant wouldn't increase code
3355 // size (implying the constant is no larger than 4 bytes).
3356 const Function &F = DAG.getMachineFunction().getFunction();
3357
3358 // We rely on this decision to inline being idemopotent and unrelated to the
3359 // use-site. We know that if we inline a variable at one use site, we'll
3360 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3361 // doesn't know about this optimization, so bail out if it's enabled else
3362 // we could decide to inline here (and thus never emit the GV) but require
3363 // the GV from fast-isel generated code.
3364 if (!EnableConstpoolPromotion ||
3365 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3366 return SDValue();
3367
3368 auto *GVar = dyn_cast<GlobalVariable>(GV);
3369 if (!GVar || !GVar->hasInitializer() ||
3370 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3371 !GVar->hasLocalLinkage())
3372 return SDValue();
3373
3374 // If we inline a value that contains relocations, we move the relocations
3375 // from .data to .text. This is not allowed in position-independent code.
3376 auto *Init = GVar->getInitializer();
3377 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3378 Init->needsRelocation())
3379 return SDValue();
3380
3381 // The constant islands pass can only really deal with alignment requests
3382 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3383 // any type wanting greater alignment requirements than 4 bytes. We also
3384 // can only promote constants that are multiples of 4 bytes in size or
3385 // are paddable to a multiple of 4. Currently we only try and pad constants
3386 // that are strings for simplicity.
3387 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3388 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3389 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3390 unsigned RequiredPadding = 4 - (Size % 4);
3391 bool PaddingPossible =
3392 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3393 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3394 Size == 0)
3395 return SDValue();
3396
3397 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3398 MachineFunction &MF = DAG.getMachineFunction();
3399 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3400
3401 // We can't bloat the constant pool too much, else the ConstantIslands pass
3402 // may fail to converge. If we haven't promoted this global yet (it may have
3403 // multiple uses), and promoting it would increase the constant pool size (Sz
3404 // > 4), ensure we have space to do so up to MaxTotal.
3405 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3406 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3407 ConstpoolPromotionMaxTotal)
3408 return SDValue();
3409
3410 // This is only valid if all users are in a single function; we can't clone
3411 // the constant in general. The LLVM IR unnamed_addr allows merging
3412 // constants, but not cloning them.
3413 //
3414 // We could potentially allow cloning if we could prove all uses of the
3415 // constant in the current function don't care about the address, like
3416 // printf format strings. But that isn't implemented for now.
3417 if (!allUsersAreInFunction(GVar, &F))
3418 return SDValue();
3419
3420 // We're going to inline this global. Pad it out if needed.
3421 if (RequiredPadding != 4) {
3422 StringRef S = CDAInit->getAsString();
3423
3424 SmallVector<uint8_t,16> V(S.size());
3425 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3426 while (RequiredPadding--)
3427 V.push_back(0);
3428 Init = ConstantDataArray::get(*DAG.getContext(), V);
3429 }
3430
3431 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3432 SDValue CPAddr =
3433 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3434 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3435 AFI->markGlobalAsPromotedToConstantPool(GVar);
3436 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3437 PaddedSize - 4);
3438 }
3439 ++NumConstpoolPromoted;
3440 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3441}
3442
3443bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3444 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3445 if (!(GV = GA->getBaseObject()))
3446 return false;
3447 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3448 return V->isConstant();
3449 return isa<Function>(GV);
3450}
3451
3452SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3453 SelectionDAG &DAG) const {
3454 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3455 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3455)
;
3456 case Triple::COFF:
3457 return LowerGlobalAddressWindows(Op, DAG);
3458 case Triple::ELF:
3459 return LowerGlobalAddressELF(Op, DAG);
3460 case Triple::MachO:
3461 return LowerGlobalAddressDarwin(Op, DAG);
3462 }
3463}
3464
3465SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3466 SelectionDAG &DAG) const {
3467 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3468 SDLoc dl(Op);
3469 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3470 const TargetMachine &TM = getTargetMachine();
3471 bool IsRO = isReadOnly(GV);
3472
3473 // promoteToConstantPool only if not generating XO text section
3474 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3475 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3476 return V;
3477
3478 if (isPositionIndependent()) {
3479 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3480 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3481 UseGOT_PREL ? ARMII::MO_GOT : 0);
3482 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3483 if (UseGOT_PREL)
3484 Result =
3485 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3486 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3487 return Result;
3488 } else if (Subtarget->isROPI() && IsRO) {
3489 // PC-relative.
3490 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3491 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3492 return Result;
3493 } else if (Subtarget->isRWPI() && !IsRO) {
3494 // SB-relative.
3495 SDValue RelAddr;
3496 if (Subtarget->useMovt()) {
3497 ++NumMovwMovt;
3498 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3499 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3500 } else { // use literal pool for address constant
3501 ARMConstantPoolValue *CPV =
3502 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3503 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3504 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3505 RelAddr = DAG.getLoad(
3506 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3507 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3508 }
3509 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3510 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3511 return Result;
3512 }
3513
3514 // If we have T2 ops, we can materialize the address directly via movt/movw
3515 // pair. This is always cheaper.
3516 if (Subtarget->useMovt()) {
3517 ++NumMovwMovt;
3518 // FIXME: Once remat is capable of dealing with instructions with register
3519 // operands, expand this into two nodes.
3520 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3521 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3522 } else {
3523 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3524 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3525 return DAG.getLoad(
3526 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3527 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3528 }
3529}
3530
3531SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3532 SelectionDAG &DAG) const {
3533 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3534, __PRETTY_FUNCTION__))
3534 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3534, __PRETTY_FUNCTION__))
;
3535 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3536 SDLoc dl(Op);
3537 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3538
3539 if (Subtarget->useMovt())
3540 ++NumMovwMovt;
3541
3542 // FIXME: Once remat is capable of dealing with instructions with register
3543 // operands, expand this into multiple nodes
3544 unsigned Wrapper =
3545 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3546
3547 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3548 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3549
3550 if (Subtarget->isGVIndirectSymbol(GV))
3551 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3552 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3553 return Result;
3554}
3555
3556SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3557 SelectionDAG &DAG) const {
3558 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3558, __PRETTY_FUNCTION__))
;
3559 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3560, __PRETTY_FUNCTION__))
3560 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3560, __PRETTY_FUNCTION__))
;
3561 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3562, __PRETTY_FUNCTION__))
3562 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3562, __PRETTY_FUNCTION__))
;
3563
3564 const TargetMachine &TM = getTargetMachine();
3565 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3566 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3567 if (GV->hasDLLImportStorageClass())
3568 TargetFlags = ARMII::MO_DLLIMPORT;
3569 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3570 TargetFlags = ARMII::MO_COFFSTUB;
3571 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3572 SDValue Result;
3573 SDLoc DL(Op);
3574
3575 ++NumMovwMovt;
3576
3577 // FIXME: Once remat is capable of dealing with instructions with register
3578 // operands, expand this into two nodes.
3579 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3580 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3581 TargetFlags));
3582 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3583 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3584 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3585 return Result;
3586}
3587
3588SDValue
3589ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3590 SDLoc dl(Op);
3591 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3592 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3593 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3594 Op.getOperand(1), Val);
3595}
3596
3597SDValue
3598ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3599 SDLoc dl(Op);
3600 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3601 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3602}
3603
3604SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3605 SelectionDAG &DAG) const {
3606 SDLoc dl(Op);
3607 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3608 Op.getOperand(0));
3609}
3610
3611SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3612 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3613 unsigned IntNo =
3614 cast<ConstantSDNode>(
3615 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3616 ->getZExtValue();
3617 switch (IntNo) {
3618 default:
3619 return SDValue(); // Don't custom lower most intrinsics.
3620 case Intrinsic::arm_gnu_eabi_mcount: {
3621 MachineFunction &MF = DAG.getMachineFunction();
3622 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3623 SDLoc dl(Op);
3624 SDValue Chain = Op.getOperand(0);
3625 // call "\01__gnu_mcount_nc"
3626 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3627 const uint32_t *Mask =
3628 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3629 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3629, __PRETTY_FUNCTION__))
;
3630 // Mark LR an implicit live-in.
3631 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3632 SDValue ReturnAddress =
3633 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3634 std::vector<EVT> ResultTys = {MVT::Other, MVT::Glue};
3635 SDValue Callee =
3636 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3637 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3638 if (Subtarget->isThumb())
3639 return SDValue(
3640 DAG.getMachineNode(
3641 ARM::tBL_PUSHLR, dl, ResultTys,
3642 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3643 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3644 0);
3645 return SDValue(
3646 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3647 {ReturnAddress, Callee, RegisterMask, Chain}),
3648 0);
3649 }
3650 }
3651}
3652
3653SDValue
3654ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3655 const ARMSubtarget *Subtarget) const {
3656 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3657 SDLoc dl(Op);
3658 switch (IntNo) {
3659 default: return SDValue(); // Don't custom lower most intrinsics.
3660 case Intrinsic::thread_pointer: {
3661 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3662 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3663 }
3664 case Intrinsic::arm_cls: {
3665 const SDValue &Operand = Op.getOperand(1);
3666 const EVT VTy = Op.getValueType();
3667 SDValue SRA =
3668 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3669 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3670 SDValue SHL =
3671 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3672 SDValue OR =
3673 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3674 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3675 return Result;
3676 }
3677 case Intrinsic::arm_cls64: {
3678 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3679 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3680 const SDValue &Operand = Op.getOperand(1);
3681 const EVT VTy = Op.getValueType();
3682
3683 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3684 DAG.getConstant(1, dl, VTy));
3685 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3686 DAG.getConstant(0, dl, VTy));
3687 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3688 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3689 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3690 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3691 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3692 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3693 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3694 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3695 SDValue CheckLo =
3696 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3697 SDValue HiIsZero =
3698 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3699 SDValue AdjustedLo =
3700 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3701 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3702 SDValue Result =
3703 DAG.getSelect(dl, VTy, CheckLo,
3704 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3705 return Result;
3706 }
3707 case Intrinsic::eh_sjlj_lsda: {
3708 MachineFunction &MF = DAG.getMachineFunction();
3709 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3710 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3711 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3712 SDValue CPAddr;
3713 bool IsPositionIndependent = isPositionIndependent();
3714 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3715 ARMConstantPoolValue *CPV =
3716 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3717 ARMCP::CPLSDA, PCAdj);
3718 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3719 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3720 SDValue Result = DAG.getLoad(
3721 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3722 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3723
3724 if (IsPositionIndependent) {
3725 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3726 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3727 }
3728 return Result;
3729 }
3730 case Intrinsic::arm_neon_vabs:
3731 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3732 Op.getOperand(1));
3733 case Intrinsic::arm_neon_vmulls:
3734 case Intrinsic::arm_neon_vmullu: {
3735 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3736 ? ARMISD::VMULLs : ARMISD::VMULLu;
3737 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3738 Op.getOperand(1), Op.getOperand(2));
3739 }
3740 case Intrinsic::arm_neon_vminnm:
3741 case Intrinsic::arm_neon_vmaxnm: {
3742 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3743 ? ISD::FMINNUM : ISD::FMAXNUM;
3744 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3745 Op.getOperand(1), Op.getOperand(2));
3746 }
3747 case Intrinsic::arm_neon_vminu:
3748 case Intrinsic::arm_neon_vmaxu: {
3749 if (Op.getValueType().isFloatingPoint())
3750 return SDValue();
3751 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3752 ? ISD::UMIN : ISD::UMAX;
3753 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3754 Op.getOperand(1), Op.getOperand(2));
3755 }
3756 case Intrinsic::arm_neon_vmins:
3757 case Intrinsic::arm_neon_vmaxs: {
3758 // v{min,max}s is overloaded between signed integers and floats.
3759 if (!Op.getValueType().isFloatingPoint()) {
3760 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3761 ? ISD::SMIN : ISD::SMAX;
3762 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3763 Op.getOperand(1), Op.getOperand(2));
3764 }
3765 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3766 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3767 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3768 Op.getOperand(1), Op.getOperand(2));
3769 }
3770 case Intrinsic::arm_neon_vtbl1:
3771 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3772 Op.getOperand(1), Op.getOperand(2));
3773 case Intrinsic::arm_neon_vtbl2:
3774 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3775 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3776 case Intrinsic::arm_mve_pred_i2v:
3777 case Intrinsic::arm_mve_pred_v2i:
3778 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
3779 Op.getOperand(1));
3780 }
3781}
3782
3783static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3784 const ARMSubtarget *Subtarget) {
3785 SDLoc dl(Op);
3786 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3787 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3788 if (SSID == SyncScope::SingleThread)
3789 return Op;
3790
3791 if (!Subtarget->hasDataBarrier()) {
3792 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3793 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3794 // here.
3795 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3796, __PRETTY_FUNCTION__))
3796 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3796, __PRETTY_FUNCTION__))
;
3797 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3798 DAG.getConstant(0, dl, MVT::i32));
3799 }
3800
3801 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3802 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3803 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3804 if (Subtarget->isMClass()) {
3805 // Only a full system barrier exists in the M-class architectures.
3806 Domain = ARM_MB::SY;
3807 } else if (Subtarget->preferISHSTBarriers() &&
3808 Ord == AtomicOrdering::Release) {
3809 // Swift happens to implement ISHST barriers in a way that's compatible with
3810 // Release semantics but weaker than ISH so we'd be fools not to use
3811 // it. Beware: other processors probably don't!
3812 Domain = ARM_MB::ISHST;
3813 }
3814
3815 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3816 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3817 DAG.getConstant(Domain, dl, MVT::i32));
3818}
3819
3820static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3821 const ARMSubtarget *Subtarget) {
3822 // ARM pre v5TE and Thumb1 does not have preload instructions.
3823 if (!(Subtarget->isThumb2() ||
3824 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3825 // Just preserve the chain.
3826 return Op.getOperand(0);
3827
3828 SDLoc dl(Op);
3829 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3830 if (!isRead &&
3831 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3832 // ARMv7 with MP extension has PLDW.
3833 return Op.getOperand(0);
3834
3835 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3836 if (Subtarget->isThumb()) {
3837 // Invert the bits.
3838 isRead = ~isRead & 1;
3839 isData = ~isData & 1;
3840 }
3841
3842 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3843 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3844 DAG.getConstant(isData, dl, MVT::i32));
3845}
3846
3847static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3848 MachineFunction &MF = DAG.getMachineFunction();
3849 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3850
3851 // vastart just stores the address of the VarArgsFrameIndex slot into the
3852 // memory location argument.
3853 SDLoc dl(Op);
3854 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3855 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3856 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3857 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3858 MachinePointerInfo(SV));
3859}
3860
3861SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3862 CCValAssign &NextVA,
3863 SDValue &Root,
3864 SelectionDAG &DAG,
3865 const SDLoc &dl) const {
3866 MachineFunction &MF = DAG.getMachineFunction();
3867 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3868
3869 const TargetRegisterClass *RC;
3870 if (AFI->isThumb1OnlyFunction())
3871 RC = &ARM::tGPRRegClass;
3872 else
3873 RC = &ARM::GPRRegClass;
3874
3875 // Transform the arguments stored in physical registers into virtual ones.
3876 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3877 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3878
3879 SDValue ArgValue2;
3880 if (NextVA.isMemLoc()) {
3881 MachineFrameInfo &MFI = MF.getFrameInfo();
3882 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3883
3884 // Create load node to retrieve arguments from the stack.
3885 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3886 ArgValue2 = DAG.getLoad(
3887 MVT::i32, dl, Root, FIN,
3888 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3889 } else {
3890 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3891 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3892 }
3893 if (!Subtarget->isLittle())
3894 std::swap (ArgValue, ArgValue2);
3895 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3896}
3897
3898// The remaining GPRs hold either the beginning of variable-argument
3899// data, or the beginning of an aggregate passed by value (usually
3900// byval). Either way, we allocate stack slots adjacent to the data
3901// provided by our caller, and store the unallocated registers there.
3902// If this is a variadic function, the va_list pointer will begin with
3903// these values; otherwise, this reassembles a (byval) structure that
3904// was split between registers and memory.
3905// Return: The frame index registers were stored into.
3906int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3907 const SDLoc &dl, SDValue &Chain,
3908 const Value *OrigArg,
3909 unsigned InRegsParamRecordIdx,
3910 int ArgOffset, unsigned ArgSize) const {
3911 // Currently, two use-cases possible:
3912 // Case #1. Non-var-args function, and we meet first byval parameter.
3913 // Setup first unallocated register as first byval register;
3914 // eat all remained registers
3915 // (these two actions are performed by HandleByVal method).
3916 // Then, here, we initialize stack frame with
3917 // "store-reg" instructions.
3918 // Case #2. Var-args function, that doesn't contain byval parameters.
3919 // The same: eat all remained unallocated registers,
3920 // initialize stack frame.
3921
3922 MachineFunction &MF = DAG.getMachineFunction();
3923 MachineFrameInfo &MFI = MF.getFrameInfo();
3924 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3925 unsigned RBegin, REnd;
3926 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3927 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3928 } else {
3929 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3930 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3931 REnd = ARM::R4;
3932 }
3933
3934 if (REnd != RBegin)
3935 ArgOffset = -4 * (ARM::R4 - RBegin);
3936
3937 auto PtrVT = getPointerTy(DAG.getDataLayout());
3938 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3939 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3940
3941 SmallVector<SDValue, 4> MemOps;
3942 const TargetRegisterClass *RC =
3943 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3944
3945 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3946 unsigned VReg = MF.addLiveIn(Reg, RC);
3947 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3948 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3949 MachinePointerInfo(OrigArg, 4 * i));
3950 MemOps.push_back(Store);
3951 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3952 }
3953
3954 if (!MemOps.empty())
3955 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3956 return FrameIndex;
3957}
3958
3959// Setup stack frame, the va_list pointer will start from.
3960void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3961 const SDLoc &dl, SDValue &Chain,
3962 unsigned ArgOffset,
3963 unsigned TotalArgRegsSaveSize,
3964 bool ForceMutable) const {
3965 MachineFunction &MF = DAG.getMachineFunction();
3966 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3967
3968 // Try to store any remaining integer argument regs
3969 // to their spots on the stack so that they may be loaded by dereferencing
3970 // the result of va_next.
3971 // If there is no regs to be stored, just point address after last
3972 // argument passed via stack.
3973 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3974 CCInfo.getInRegsParamsCount(),
3975 CCInfo.getNextStackOffset(),
3976 std::max(4U, TotalArgRegsSaveSize));
3977 AFI->setVarArgsFrameIndex(FrameIndex);
3978}
3979
3980SDValue ARMTargetLowering::LowerFormalArguments(
3981 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3982 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3983 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3984 MachineFunction &MF = DAG.getMachineFunction();
3985 MachineFrameInfo &MFI = MF.getFrameInfo();
3986
3987 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3988
3989 // Assign locations to all of the incoming arguments.
3990 SmallVector<CCValAssign, 16> ArgLocs;
3991 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3992 *DAG.getContext());
3993 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3994
3995 SmallVector<SDValue, 16> ArgValues;
3996 SDValue ArgValue;
3997 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3998 unsigned CurArgIdx = 0;
3999
4000 // Initially ArgRegsSaveSize is zero.
4001 // Then we increase this value each time we meet byval parameter.
4002 // We also increase this value in case of varargs function.
4003 AFI->setArgRegsSaveSize(0);
4004
4005 // Calculate the amount of stack space that we need to allocate to store
4006 // byval and variadic arguments that are passed in registers.
4007 // We need to know this before we allocate the first byval or variadic
4008 // argument, as they will be allocated a stack slot below the CFA (Canonical
4009 // Frame Address, the stack pointer at entry to the function).
4010 unsigned ArgRegBegin = ARM::R4;
4011 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4012 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4013 break;
4014
4015 CCValAssign &VA = ArgLocs[i];
4016 unsigned Index = VA.getValNo();
4017 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4018 if (!Flags.isByVal())
4019 continue;
4020
4021 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4021, __PRETTY_FUNCTION__))
;
4022 unsigned RBegin, REnd;
4023 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4024 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4025
4026 CCInfo.nextInRegsParam();
4027 }
4028 CCInfo.rewindByValRegsInfo();
4029
4030 int lastInsIndex = -1;
4031 if (isVarArg && MFI.hasVAStart()) {
4032 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4033 if (RegIdx != array_lengthof(GPRArgRegs))
4034 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4035 }
4036
4037 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4038 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4039 auto PtrVT = getPointerTy(DAG.getDataLayout());
4040
4041 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4042 CCValAssign &VA = ArgLocs[i];
4043 if (Ins[VA.getValNo()].isOrigArg()) {
4044 std::advance(CurOrigArg,
4045 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4046 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4047 }
4048 // Arguments stored in registers.
4049 if (VA.isRegLoc()) {
4050 EVT RegVT = VA.getLocVT();
4051
4052 if (VA.needsCustom()) {
4053 // f64 and vector types are split up into multiple registers or
4054 // combinations of registers and stack slots.
4055 if (VA.getLocVT() == MVT::v2f64) {
4056 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
4057 Chain, DAG, dl);
4058 VA = ArgLocs[++i]; // skip ahead to next loc
4059 SDValue ArgValue2;
4060 if (VA.isMemLoc()) {
4061 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4062 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4063 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
4064 MachinePointerInfo::getFixedStack(
4065 DAG.getMachineFunction(), FI));
4066 } else {
4067 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
4068 Chain, DAG, dl);
4069 }
4070 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4071 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4072 ArgValue, ArgValue1,
4073 DAG.getIntPtrConstant(0, dl));
4074 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4075 ArgValue, ArgValue2,
4076 DAG.getIntPtrConstant(1, dl));
4077 } else
4078 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4079 } else {
4080 const TargetRegisterClass *RC;
4081
4082
4083 if (RegVT == MVT::f16)
4084 RC = &ARM::HPRRegClass;
4085 else if (RegVT == MVT::f32)
4086 RC = &ARM::SPRRegClass;
4087 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
4088 RC = &ARM::DPRRegClass;
4089 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
4090 RC = &ARM::QPRRegClass;
4091 else if (RegVT == MVT::i32)
4092 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4093 : &ARM::GPRRegClass;
4094 else
4095 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4095)
;
4096
4097 // Transform the arguments in physical registers into virtual ones.
4098 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4099 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4100
4101 // If this value is passed in r0 and has the returned attribute (e.g.
4102 // C++ 'structors), record this fact for later use.
4103 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4104 AFI->setPreservesR0();
4105 }
4106 }
4107
4108 // If this is an 8 or 16-bit value, it is really passed promoted
4109 // to 32 bits. Insert an assert[sz]ext to capture this, then
4110 // truncate to the right size.
4111 switch (VA.getLocInfo()) {
4112 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4112)
;
4113 case CCValAssign::Full: break;
4114 case CCValAssign::BCvt:
4115 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4116 break;
4117 case CCValAssign::SExt:
4118 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4119 DAG.getValueType(VA.getValVT()));
4120 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4121 break;
4122 case CCValAssign::ZExt:
4123 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4124 DAG.getValueType(VA.getValVT()));
4125 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4126 break;
4127 }
4128
4129 InVals.push_back(ArgValue);
4130 } else { // VA.isRegLoc()
4131 // sanity check
4132 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4132, __PRETTY_FUNCTION__))
;
4133 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4133, __PRETTY_FUNCTION__))
;
4134
4135 int index = VA.getValNo();
4136
4137 // Some Ins[] entries become multiple ArgLoc[] entries.
4138 // Process them only once.
4139 if (index != lastInsIndex)
4140 {
4141 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4142 // FIXME: For now, all byval parameter objects are marked mutable.
4143 // This can be changed with more analysis.
4144 // In case of tail call optimization mark all arguments mutable.
4145 // Since they could be overwritten by lowering of arguments in case of
4146 // a tail call.
4147 if (Flags.isByVal()) {
4148 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4149, __PRETTY_FUNCTION__))
4149 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4149, __PRETTY_FUNCTION__))
;
4150 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4151
4152 int FrameIndex = StoreByValRegs(
4153 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4154 VA.getLocMemOffset(), Flags.getByValSize());
4155 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4156 CCInfo.nextInRegsParam();
4157 } else {
4158 unsigned FIOffset = VA.getLocMemOffset();
4159 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4160 FIOffset, true);
4161
4162 // Create load nodes to retrieve arguments from the stack.
4163 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4164 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4165 MachinePointerInfo::getFixedStack(
4166 DAG.getMachineFunction(), FI)));
4167 }
4168 lastInsIndex = index;
4169 }
4170 }
4171 }
4172
4173 // varargs
4174 if (isVarArg && MFI.hasVAStart())
4175 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
4176 CCInfo.getNextStackOffset(),
4177 TotalArgRegsSaveSize);
4178
4179 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4180
4181 return Chain;
4182}
4183
4184/// isFloatingPointZero - Return true if this is +0.0.
4185static bool isFloatingPointZero(SDValue Op) {
4186 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3
Calling 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
18
Returning from 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
19
Assuming 'CFP' is null
20
Taking false branch
4187 return CFP->getValueAPF().isPosZero();
4188 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4189 // Maybe this has already been legalized into the constant pool?
4190 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
21
Calling 'SDValue::getOperand'
4191 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4192 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4193 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4194 return CFP->getValueAPF().isPosZero();
4195 }
4196 } else if (Op->getOpcode() == ISD::BITCAST &&
4197 Op->getValueType(0) == MVT::f64) {
4198 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4199 // created by LowerConstantFP().
4200 SDValue BitcastOp = Op->getOperand(0);
4201 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4202 isNullConstant(BitcastOp->getOperand(0)))
4203 return true;
4204 }
4205 return false;
4206}
4207
4208/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4209/// the given operands.
4210SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4211 SDValue &ARMcc, SelectionDAG &DAG,
4212 const SDLoc &dl) const {
4213 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4214 unsigned C = RHSC->getZExtValue();
4215 if (!isLegalICmpImmediate((int32_t)C)) {
4216 // Constant does not fit, try adjusting it by one.
4217 switch (CC) {
4218 default: break;
4219 case ISD::SETLT:
4220 case ISD::SETGE:
4221 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4222 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4223 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4224 }
4225 break;
4226 case ISD::SETULT:
4227 case ISD::SETUGE:
4228 if (C != 0 && isLegalICmpImmediate(C-1)) {
4229 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4230 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4231 }
4232 break;
4233 case ISD::SETLE:
4234 case ISD::SETGT:
4235 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4236 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4237 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4238 }
4239 break;
4240 case ISD::SETULE:
4241 case ISD::SETUGT:
4242 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4243 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4244 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4245 }
4246 break;
4247 }
4248 }
4249 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4250 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4251 // In ARM and Thumb-2, the compare instructions can shift their second
4252 // operand.
4253 CC = ISD::getSetCCSwappedOperands(CC);
4254 std::swap(LHS, RHS);
4255 }
4256
4257 // Thumb1 has very limited immediate modes, so turning an "and" into a
4258 // shift can save multiple instructions.
4259 //
4260 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4261 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4262 // own. If it's the operand to an unsigned comparison with an immediate,
4263 // we can eliminate one of the shifts: we transform
4264 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4265 //
4266 // We avoid transforming cases which aren't profitable due to encoding
4267 // details:
4268 //
4269 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4270 // would not; in that case, we're essentially trading one immediate load for
4271 // another.
4272 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4273 // 3. C2 is zero; we have other code for this special case.
4274 //
4275 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4276 // instruction, since the AND is always one instruction anyway, but we could
4277 // use narrow instructions in some cases.
4278 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4279 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4280 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4281 !isSignedIntSetCC(CC)) {
4282 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4283 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4284 uint64_t RHSV = RHSC->getZExtValue();
4285 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4286 unsigned ShiftBits = countLeadingZeros(Mask);
4287 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4288 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4289 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4290 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4291 }
4292 }
4293 }
4294
4295 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4296 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4297 // way a cmp would.
4298 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4299 // some tweaks to the heuristics for the previous and->shift transform.
4300 // FIXME: Optimize cases where the LHS isn't a shift.
4301 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4302 isa<ConstantSDNode>(RHS) &&
4303 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4304 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4305 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4306 unsigned ShiftAmt =
4307 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4308 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4309 DAG.getVTList(MVT::i32, MVT::i32),
4310 LHS.getOperand(0),
4311 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4312 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4313 Shift.getValue(1), SDValue());
4314 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4315 return Chain.getValue(1);
4316 }
4317
4318 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4319
4320 // If the RHS is a constant zero then the V (overflow) flag will never be
4321 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4322 // simpler for other passes (like the peephole optimiser) to deal with.
4323 if (isNullConstant(RHS)) {
4324 switch (CondCode) {
4325 default: break;
4326 case ARMCC::GE:
4327 CondCode = ARMCC::PL;
4328 break;
4329 case ARMCC::LT:
4330 CondCode = ARMCC::MI;
4331 break;
4332 }
4333 }
4334
4335 ARMISD::NodeType CompareType;
4336 switch (CondCode) {
4337 default:
4338 CompareType = ARMISD::CMP;
4339 break;
4340 case ARMCC::EQ:
4341 case ARMCC::NE:
4342 // Uses only Z Flag
4343 CompareType = ARMISD::CMPZ;
4344 break;
4345 }
4346 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4347 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4348}
4349
4350/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4351SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4352 SelectionDAG &DAG, const SDLoc &dl) const {
4353 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4353, __PRETTY_FUNCTION__))
;
4354 SDValue Cmp;
4355 if (!isFloatingPointZero(RHS))
4356 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
4357 else
4358 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
4359 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4360}
4361
4362/// duplicateCmp - Glue values can have only one use, so this function
4363/// duplicates a comparison node.
4364SDValue
4365ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4366 unsigned Opc = Cmp.getOpcode();
4367 SDLoc DL(Cmp);
4368 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4369 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4370
4371 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4371, __PRETTY_FUNCTION__))
;
4372 Cmp = Cmp.getOperand(0);
4373 Opc = Cmp.getOpcode();
4374 if (Opc == ARMISD::CMPFP)
4375 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4376 else {
4377 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4377, __PRETTY_FUNCTION__))
;
4378 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4379 }
4380 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4381}
4382
4383// This function returns three things: the arithmetic computation itself
4384// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4385// comparison and the condition code define the case in which the arithmetic
4386// computation *does not* overflow.
4387std::pair<SDValue, SDValue>
4388ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4389 SDValue &ARMcc) const {
4390 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4390, __PRETTY_FUNCTION__))
;
4391
4392 SDValue Value, OverflowCmp;
4393 SDValue LHS = Op.getOperand(0);
4394 SDValue RHS = Op.getOperand(1);
4395 SDLoc dl(Op);
4396
4397 // FIXME: We are currently always generating CMPs because we don't support
4398 // generating CMN through the backend. This is not as good as the natural
4399 // CMP case because it causes a register dependency and cannot be folded
4400 // later.
4401
4402 switch (Op.getOpcode()) {
4403 default:
4404 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4404)
;
4405 case ISD::SADDO:
4406 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4407 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4408 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4409 break;
4410 case ISD::UADDO:
4411 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4412 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4413 // We do not use it in the USUBO case as Value may not be used.
4414 Value = DAG.getNode(ARMISD::ADDC, dl,
4415 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4416 .getValue(0);
4417 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4418 break;
4419 case ISD::SSUBO:
4420 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4421 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4422 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4423 break;
4424 case ISD::USUBO:
4425 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4426 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4427 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4428 break;
4429 case ISD::UMULO:
4430 // We generate a UMUL_LOHI and then check if the high word is 0.
4431 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4432 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4433 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4434 LHS, RHS);
4435 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4436 DAG.getConstant(0, dl, MVT::i32));
4437 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4438 break;
4439 case ISD::SMULO:
4440 // We generate a SMUL_LOHI and then check if all the bits of the high word
4441 // are the same as the sign bit of the low word.
4442 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4443 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4444 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4445 LHS, RHS);
4446 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4447 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4448 Value.getValue(0),
4449 DAG.getConstant(31, dl, MVT::i32)));
4450 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4451 break;
4452 } // switch (...)
4453
4454 return std::make_pair(Value, OverflowCmp);
4455}
4456
4457SDValue
4458ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4459 // Let legalize expand this if it isn't a legal type yet.
4460 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4461 return SDValue();
4462
4463 SDValue Value, OverflowCmp;
4464 SDValue ARMcc;
4465 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4466 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4467 SDLoc dl(Op);
4468 // We use 0 and 1 as false and true values.
4469 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4470 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4471 EVT VT = Op.getValueType();
4472
4473 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4474 ARMcc, CCR, OverflowCmp);
4475
4476 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4477 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4478}
4479
4480static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4481 SelectionDAG &DAG) {
4482 SDLoc DL(BoolCarry);
4483 EVT CarryVT = BoolCarry.getValueType();
4484
4485 // This converts the boolean value carry into the carry flag by doing
4486 // ARMISD::SUBC Carry, 1
4487 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4488 DAG.getVTList(CarryVT, MVT::i32),
4489 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4490 return Carry.getValue(1);
4491}
4492
4493static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4494 SelectionDAG &DAG) {
4495 SDLoc DL(Flags);
4496
4497 // Now convert the carry flag into a boolean carry. We do this
4498 // using ARMISD:ADDE 0, 0, Carry
4499 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4500 DAG.getConstant(0, DL, MVT::i32),
4501 DAG.getConstant(0, DL, MVT::i32), Flags);
4502}
4503
4504SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4505 SelectionDAG &DAG) const {
4506 // Let legalize expand this if it isn't a legal type yet.
4507 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4508 return SDValue();
4509
4510 SDValue LHS = Op.getOperand(0);
4511 SDValue RHS = Op.getOperand(1);
4512 SDLoc dl(Op);
4513
4514 EVT VT = Op.getValueType();
4515 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4516 SDValue Value;
4517 SDValue Overflow;
4518 switch (Op.getOpcode()) {
4519 default:
4520 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4520)
;
4521 case ISD::UADDO:
4522 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4523 // Convert the carry flag into a boolean value.
4524 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4525 break;
4526 case ISD::USUBO: {
4527 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4528 // Convert the carry flag into a boolean value.
4529 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4530 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4531 // value. So compute 1 - C.
4532 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4533 DAG.getConstant(1, dl, MVT::i32), Overflow);
4534 break;
4535 }
4536 }
4537
4538 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4539}
4540
4541static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4542 const ARMSubtarget *Subtarget) {
4543 EVT VT = Op.getValueType();
4544 if (!Subtarget->hasDSP())
4545 return SDValue();
4546 if (!VT.isSimple())
4547 return SDValue();
4548
4549 unsigned NewOpcode;
4550 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4551 switch (VT.getSimpleVT().SimpleTy) {
4552 default:
4553 return SDValue();
4554 case MVT::i8:
4555 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4556 break;
4557 case MVT::i16:
4558 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4559 break;
4560 }
4561
4562 SDLoc dl(Op);
4563 SDValue Add =
4564 DAG.getNode(NewOpcode, dl, MVT::i32,
4565 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4566 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4567 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4568}
4569
4570SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4571 SDValue Cond = Op.getOperand(0);
4572 SDValue SelectTrue = Op.getOperand(1);
4573 SDValue SelectFalse = Op.getOperand(2);
4574 SDLoc dl(Op);
4575 unsigned Opc = Cond.getOpcode();
4576
4577 if (Cond.getResNo() == 1 &&
4578 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4579 Opc == ISD::USUBO)) {
4580 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4581 return SDValue();
4582
4583 SDValue Value, OverflowCmp;
4584 SDValue ARMcc;
4585 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4586 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4587 EVT VT = Op.getValueType();
4588
4589 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4590 OverflowCmp, DAG);
4591 }
4592
4593 // Convert:
4594 //
4595 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4596 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4597 //
4598 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4599 const ConstantSDNode *CMOVTrue =
4600 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4601 const ConstantSDNode *CMOVFalse =
4602 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4603
4604 if (CMOVTrue && CMOVFalse) {
4605 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4606 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4607
4608 SDValue True;
4609 SDValue False;
4610 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4611 True = SelectTrue;
4612 False = SelectFalse;
4613 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4614 True = SelectFalse;
4615 False = SelectTrue;
4616 }
4617
4618 if (True.getNode() && False.getNode()) {
4619 EVT VT = Op.getValueType();
4620 SDValue ARMcc = Cond.getOperand(2);
4621 SDValue CCR = Cond.getOperand(3);
4622 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4623 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4623, __PRETTY_FUNCTION__))
;
4624 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4625 }
4626 }
4627 }
4628
4629 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4630 // undefined bits before doing a full-word comparison with zero.
4631 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4632 DAG.getConstant(1, dl, Cond.getValueType()));
4633
4634 return DAG.getSelectCC(dl, Cond,
4635 DAG.getConstant(0, dl, Cond.getValueType()),
4636 SelectTrue, SelectFalse, ISD::SETNE);
4637}
4638
4639static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4640 bool &swpCmpOps, bool &swpVselOps) {
4641 // Start by selecting the GE condition code for opcodes that return true for
4642 // 'equality'
4643 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4644 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4645 CondCode = ARMCC::GE;
4646
4647 // and GT for opcodes that return false for 'equality'.
4648 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4649 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4650 CondCode = ARMCC::GT;
4651
4652 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4653 // to swap the compare operands.
4654 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4655 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4656 swpCmpOps = true;
4657
4658 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4659 // If we have an unordered opcode, we need to swap the operands to the VSEL
4660 // instruction (effectively negating the condition).
4661 //
4662 // This also has the effect of swapping which one of 'less' or 'greater'
4663 // returns true, so we also swap the compare operands. It also switches
4664 // whether we return true for 'equality', so we compensate by picking the
4665 // opposite condition code to our original choice.
4666 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4667 CC == ISD::SETUGT) {
4668 swpCmpOps = !swpCmpOps;
4669 swpVselOps = !swpVselOps;
4670 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4671 }
4672
4673 // 'ordered' is 'anything but unordered', so use the VS condition code and
4674 // swap the VSEL operands.
4675 if (CC == ISD::SETO) {
4676 CondCode = ARMCC::VS;
4677 swpVselOps = true;
4678 }
4679
4680 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4681 // code and swap the VSEL operands. Also do this if we don't care about the
4682 // unordered case.
4683 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4684 CondCode = ARMCC::EQ;
4685 swpVselOps = true;
4686 }
4687}
4688
4689SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4690 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4691 SDValue Cmp, SelectionDAG &DAG) const {
4692 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4693 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4694 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4695 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4696 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4697
4698 SDValue TrueLow = TrueVal.getValue(0);
4699 SDValue TrueHigh = TrueVal.getValue(1);
4700 SDValue FalseLow = FalseVal.getValue(0);
4701 SDValue FalseHigh = FalseVal.getValue(1);
4702
4703 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4704 ARMcc, CCR, Cmp);
4705 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4706 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4707
4708 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4709 } else {
4710 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4711 Cmp);
4712 }
4713}
4714
4715static bool isGTorGE(ISD::CondCode CC) {
4716 return CC == ISD::SETGT || CC == ISD::SETGE;
4717}
4718
4719static bool isLTorLE(ISD::CondCode CC) {
4720 return CC == ISD::SETLT || CC == ISD::SETLE;
4721}
4722
4723// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4724// All of these conditions (and their <= and >= counterparts) will do:
4725// x < k ? k : x
4726// x > k ? x : k
4727// k < x ? x : k
4728// k > x ? k : x
4729static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4730 const SDValue TrueVal, const SDValue FalseVal,
4731 const ISD::CondCode CC, const SDValue K) {
4732 return (isGTorGE(CC) &&
4733 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4734 (isLTorLE(CC) &&
4735 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4736}
4737
4738// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4739static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4740 const SDValue TrueVal, const SDValue FalseVal,
4741 const ISD::CondCode CC, const SDValue K) {
4742 return (isGTorGE(CC) &&
4743 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4744 (isLTorLE(CC) &&
4745 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4746}
4747
4748// Check if two chained conditionals could be converted into SSAT or USAT.
4749//
4750// SSAT can replace a set of two conditional selectors that bound a number to an
4751// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4752//
4753// x < -k ? -k : (x > k ? k : x)
4754// x < -k ? -k : (x < k ? x : k)
4755// x > -k ? (x > k ? k : x) : -k
4756// x < k ? (x < -k ? -k : x) : k
4757// etc.
4758//
4759// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4760// a power of 2.
4761//
4762// It returns true if the conversion can be done, false otherwise.
4763// Additionally, the variable is returned in parameter V, the constant in K and
4764// usat is set to true if the conditional represents an unsigned saturation
4765static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4766 uint64_t &K, bool &usat) {
4767 SDValue LHS1 = Op.getOperand(0);
4768 SDValue RHS1 = Op.getOperand(1);
4769 SDValue TrueVal1 = Op.getOperand(2);
4770 SDValue FalseVal1 = Op.getOperand(3);
4771 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4772
4773 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4774 if (Op2.getOpcode() != ISD::SELECT_CC)
4775 return false;
4776
4777 SDValue LHS2 = Op2.getOperand(0);
4778 SDValue RHS2 = Op2.getOperand(1);
4779 SDValue TrueVal2 = Op2.getOperand(2);
4780 SDValue FalseVal2 = Op2.getOperand(3);
4781 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4782
4783 // Find out which are the constants and which are the variables
4784 // in each conditional
4785 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4786 ? &RHS1
4787 : nullptr;
4788 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4789 ? &RHS2
4790 : nullptr;
4791 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4792 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4793 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4794 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4795
4796 // We must detect cases where the original operations worked with 16- or
4797 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4798 // must work with sign-extended values but the select operations return
4799 // the original non-extended value.
4800 SDValue V2TmpReg = V2Tmp;
4801 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4802 V2TmpReg = V2Tmp->getOperand(0);
4803
4804 // Check that the registers and the constants have the correct values
4805 // in both conditionals
4806 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4807 V2TmpReg != V2)
4808 return false;
4809
4810 // Figure out which conditional is saturating the lower/upper bound.
4811 const SDValue *LowerCheckOp =
4812 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4813 ? &Op
4814 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4815 ? &Op2
4816 : nullptr;
4817 const SDValue *UpperCheckOp =
4818 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4819 ? &Op
4820 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4821 ? &Op2
4822 : nullptr;
4823
4824 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4825 return false;
4826
4827 // Check that the constant in the lower-bound check is
4828 // the opposite of the constant in the upper-bound check
4829 // in 1's complement.
4830 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4831 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4832 int64_t PosVal = std::max(Val1, Val2);
4833 int64_t NegVal = std::min(Val1, Val2);
4834
4835 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4836 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4837 isPowerOf2_64(PosVal + 1)) {
4838
4839 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4840 if (Val1 == ~Val2)
4841 usat = false;
4842 else if (NegVal == 0)
4843 usat = true;
4844 else
4845 return false;
4846
4847 V = V2;
4848 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4849
4850 return true;
4851 }
4852
4853 return false;
4854}
4855
4856// Check if a condition of the type x < k ? k : x can be converted into a
4857// bit operation instead of conditional moves.
4858// Currently this is allowed given:
4859// - The conditions and values match up
4860// - k is 0 or -1 (all ones)
4861// This function will not check the last condition, thats up to the caller
4862// It returns true if the transformation can be made, and in such case
4863// returns x in V, and k in SatK.
4864static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4865 SDValue &SatK)
4866{
4867 SDValue LHS = Op.getOperand(0);
4868 SDValue RHS = Op.getOperand(1);
4869 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4870 SDValue TrueVal = Op.getOperand(2);
4871 SDValue FalseVal = Op.getOperand(3);
4872
4873 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4874 ? &RHS
4875 : nullptr;
4876
4877 // No constant operation in comparison, early out
4878 if (!K)
4879 return false;
4880
4881 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4882 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4883 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4884
4885 // If the constant on left and right side, or variable on left and right,
4886 // does not match, early out
4887 if (*K != KTmp || V != VTmp)
4888 return false;
4889
4890 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4891 SatK = *K;
4892 return true;
4893 }
4894
4895 return false;
4896}
4897
4898bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
4899 if (VT == MVT::f32)
4900 return !Subtarget->hasVFP2Base();
4901 if (VT == MVT::f64)
4902 return !Subtarget->hasFP64();
4903 if (VT == MVT::f16)
4904 return !Subtarget->hasFullFP16();
4905 return false;
4906}
4907
4908SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4909 EVT VT = Op.getValueType();
4910 SDLoc dl(Op);
4911
4912 // Try to convert two saturating conditional selects into a single SSAT
4913 SDValue SatValue;
4914 uint64_t SatConstant;
4915 bool SatUSat;
4916 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4917 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4918 if (SatUSat)
4919 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4920 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4921 else
4922 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4923 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4924 }
4925
4926 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4927 // into more efficient bit operations, which is possible when k is 0 or -1
4928 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4929 // single instructions. On Thumb the shift and the bit operation will be two
4930 // instructions.
4931 // Only allow this transformation on full-width (32-bit) operations
4932 SDValue LowerSatConstant;
4933 if (VT == MVT::i32 &&
4934 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4935 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4936 DAG.getConstant(31, dl, VT));
4937 if (isNullConstant(LowerSatConstant)) {
4938 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4939 DAG.getAllOnesConstant(dl, VT));
4940 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4941 } else if (isAllOnesConstant(LowerSatConstant))
4942 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4943 }
4944
4945 SDValue LHS = Op.getOperand(0);
4946 SDValue RHS = Op.getOperand(1);
4947 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4948 SDValue TrueVal = Op.getOperand(2);
4949 SDValue FalseVal = Op.getOperand(3);
4950 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
4951 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
4952
4953 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
4954 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
4955 unsigned TVal = CTVal->getZExtValue();
4956 unsigned FVal = CFVal->getZExtValue();
4957 unsigned Opcode = 0;
4958
4959 if (TVal == ~FVal) {
4960 Opcode = ARMISD::CSINV;
4961 } else if (TVal == ~FVal + 1) {
4962 Opcode = ARMISD::CSNEG;
4963 } else if (TVal + 1 == FVal) {
4964 Opcode = ARMISD::CSINC;
4965 } else if (TVal == FVal + 1) {
4966 Opcode = ARMISD::CSINC;
4967 std::swap(TrueVal, FalseVal);
4968 std::swap(TVal, FVal);
4969 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4970 }
4971
4972 if (Opcode) {
4973 // If one of the constants is cheaper than another, materialise the
4974 // cheaper one and let the csel generate the other.
4975 if (Opcode != ARMISD::CSINC &&
4976 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
4977 std::swap(TrueVal, FalseVal);
4978 std::swap(TVal, FVal);
4979 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4980 }
4981
4982 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
4983 // to get there. CSINC not is invertable like the other two (~(~a) == a,
4984 // -(-a) == a, but (a+1)+1 != a).
4985 if (FVal == 0 && Opcode != ARMISD::CSINC) {
4986 std::swap(TrueVal, FalseVal);
4987 std::swap(TVal, FVal);
4988 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4989 }
4990 if (TVal == 0)
4991 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
4992
4993 // Drops F's value because we can get it by inverting/negating TVal.
4994 FalseVal = TrueVal;
4995
4996 SDValue ARMcc;
4997 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4998 EVT VT = TrueVal.getValueType();
4999 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5000 }
5001 }
5002
5003 if (isUnsupportedFloatingType(LHS.getValueType())) {
5004 DAG.getTargetLoweringInfo().softenSetCCOperands(
5005 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5006
5007 // If softenSetCCOperands only returned one value, we should compare it to
5008 // zero.
5009 if (!RHS.getNode()) {
5010 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5011 CC = ISD::SETNE;
5012 }
5013 }
5014
5015 if (LHS.getValueType() == MVT::i32) {
5016 // Try to generate VSEL on ARMv8.
5017 // The VSEL instruction can't use all the usual ARM condition
5018 // codes: it only has two bits to select the condition code, so it's
5019 // constrained to use only GE, GT, VS and EQ.
5020 //
5021 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5022 // swap the operands of the previous compare instruction (effectively
5023 // inverting the compare condition, swapping 'less' and 'greater') and
5024 // sometimes need to swap the operands to the VSEL (which inverts the
5025 // condition in the sense of firing whenever the previous condition didn't)
5026 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5027 TrueVal.getValueType() == MVT::f32 ||
5028 TrueVal.getValueType() == MVT::f64)) {
5029 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5030 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5031 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5032 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5033 std::swap(TrueVal, FalseVal);
5034 }
5035 }
5036
5037 SDValue ARMcc;
5038 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5039 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5040 // Choose GE over PL, which vsel does now support
5041 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5042 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5043 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5044 }
5045
5046 ARMCC::CondCodes CondCode, CondCode2;
5047 FPCCToARMCC(CC, CondCode, CondCode2);
5048
5049 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5050 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5051 // must use VSEL (limited condition codes), due to not having conditional f16
5052 // moves.
5053 if (Subtarget->hasFPARMv8Base() &&
5054 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5055 (TrueVal.getValueType() == MVT::f16 ||
5056 TrueVal.getValueType() == MVT::f32 ||
5057 TrueVal.getValueType() == MVT::f64)) {
5058 bool swpCmpOps = false;
5059 bool swpVselOps = false;
5060 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5061
5062 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5063 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5064 if (swpCmpOps)
5065 std::swap(LHS, RHS);
5066 if (swpVselOps)
5067 std::swap(TrueVal, FalseVal);
5068 }
5069 }
5070
5071 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5072 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5073 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5074 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5075 if (CondCode2 != ARMCC::AL) {
5076 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5077 // FIXME: Needs another CMP because flag can have but one use.
5078 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5079 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5080 }
5081 return Result;
5082}
5083
5084/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5085/// to morph to an integer compare sequence.
5086static bool canChangeToInt(SDValue Op, bool &SeenZero,
5087 const ARMSubtarget *Subtarget) {
5088 SDNode *N = Op.getNode();
5089 if (!N->hasOneUse())
5090 // Otherwise it requires moving the value from fp to integer registers.
5091 return false;
5092 if (!N->getNumValues())
5093 return false;
5094 EVT VT = Op.getValueType();
5095 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5096 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5097 // vmrs are very slow, e.g. cortex-a8.
5098 return false;
5099
5100 if (isFloatingPointZero(Op)) {
5101 SeenZero = true;
5102 return true;
5103 }
5104 return ISD::isNormalLoad(N);
5105}
5106
5107static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5108 if (isFloatingPointZero(Op))
1
Value assigned to 'Op.Node'
2
Calling 'isFloatingPointZero'
5109 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5110
5111 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5112 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5113 Ld->getPointerInfo(), Ld->getAlignment(),
5114 Ld->getMemOperand()->getFlags());
5115
5116 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5116)
;
5117}
5118
5119static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5120 SDValue &RetVal1, SDValue &RetVal2) {
5121 SDLoc dl(Op);
5122
5123 if (isFloatingPointZero(Op)) {
5124 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5125 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5126 return;
5127 }
5128
5129 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5130 SDValue Ptr = Ld->getBasePtr();
5131 RetVal1 =
5132 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5133 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5134
5135 EVT PtrType = Ptr.getValueType();
5136 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5137 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5138 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5139 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5140 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5141 Ld->getMemOperand()->getFlags());
5142 return;
5143 }
5144
5145 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5145)
;
5146}
5147
5148/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5149/// f32 and even f64 comparisons to integer ones.
5150SDValue
5151ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5152 SDValue Chain = Op.getOperand(0);
5153 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5154 SDValue LHS = Op.getOperand(2);
5155 SDValue RHS = Op.getOperand(3);
5156 SDValue Dest = Op.getOperand(4);
5157 SDLoc dl(Op);
5158
5159 bool LHSSeenZero = false;
5160 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5161 bool RHSSeenZero = false;
5162 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5163 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5164 // If unsafe fp math optimization is enabled and there are no other uses of
5165 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5166 // to an integer comparison.
5167 if (CC == ISD::SETOEQ)
5168 CC = ISD::SETEQ;
5169 else if (CC == ISD::SETUNE)
5170 CC = ISD::SETNE;
5171
5172 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5173 SDValue ARMcc;
5174 if (LHS.getValueType() == MVT::f32) {
5175 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5176 bitcastf32Toi32(LHS, DAG), Mask);
5177 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5178 bitcastf32Toi32(RHS, DAG), Mask);
5179 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5180 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5181 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5182 Chain, Dest, ARMcc, CCR, Cmp);
5183 }
5184
5185 SDValue LHS1, LHS2;
5186 SDValue RHS1, RHS2;
5187 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5188 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5189 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5190 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5191 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5192 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5193 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5194 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5195 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5196 }
5197
5198 return SDValue();
5199}
5200
5201SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5202 SDValue Chain = Op.getOperand(0);
5203 SDValue Cond = Op.getOperand(1);
5204 SDValue Dest = Op.getOperand(2);
5205 SDLoc dl(Op);
5206
5207 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5208 // instruction.
5209 unsigned Opc = Cond.getOpcode();
5210 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5211 !Subtarget->isThumb1Only();
5212 if (Cond.getResNo() == 1 &&
5213 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5214 Opc == ISD::USUBO || OptimizeMul)) {
5215 // Only lower legal XALUO ops.
5216 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5217 return SDValue();
5218
5219 // The actual operation with overflow check.
5220 SDValue Value, OverflowCmp;
5221 SDValue ARMcc;
5222 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5223
5224 // Reverse the condition code.
5225 ARMCC::CondCodes CondCode =
5226 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5227 CondCode = ARMCC::getOppositeCondition(CondCode);
5228 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5229 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5230
5231 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5232 OverflowCmp);
5233 }
5234
5235 return SDValue();
5236}
5237
5238SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5239 SDValue Chain = Op.getOperand(0);
5240 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5241 SDValue LHS = Op.getOperand(2);
5242 SDValue RHS = Op.getOperand(3);
5243 SDValue Dest = Op.getOperand(4);
5244 SDLoc dl(Op);
5245
5246 if (isUnsupportedFloatingType(LHS.getValueType())) {
5247 DAG.getTargetLoweringInfo().softenSetCCOperands(
5248 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5249
5250 // If softenSetCCOperands only returned one value, we should compare it to
5251 // zero.
5252 if (!RHS.getNode()) {
5253 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5254 CC = ISD::SETNE;
5255 }
5256 }
5257
5258 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5259 // instruction.
5260 unsigned Opc = LHS.getOpcode();
5261 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5262 !Subtarget->isThumb1Only();
5263 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5264 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5265 Opc == ISD::USUBO || OptimizeMul) &&
5266 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5267 // Only lower legal XALUO ops.
5268 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5269 return SDValue();
5270
5271 // The actual operation with overflow check.
5272 SDValue Value, OverflowCmp;
5273 SDValue ARMcc;
5274 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5275
5276 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5277 // Reverse the condition code.
5278 ARMCC::CondCodes CondCode =
5279 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5280 CondCode = ARMCC::getOppositeCondition(CondCode);
5281 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5282 }
5283 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5284
5285 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5286 OverflowCmp);
5287 }
5288
5289 if (LHS.getValueType() == MVT::i32) {
5290 SDValue ARMcc;
5291 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5292 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5293 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5294 Chain, Dest, ARMcc, CCR, Cmp);
5295 }
5296
5297 if (getTargetMachine().Options.UnsafeFPMath &&
5298 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5299 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5300 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5301 return Result;
5302 }
5303
5304 ARMCC::CondCodes CondCode, CondCode2;
5305 FPCCToARMCC(CC, CondCode, CondCode2);
5306
5307 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5308 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5309 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5310 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5311 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5312 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5313 if (CondCode2 != ARMCC::AL) {
5314 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5315 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5316 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5317 }
5318 return Res;
5319}
5320
5321SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5322 SDValue Chain = Op.getOperand(0);
5323 SDValue Table = Op.getOperand(1);
5324 SDValue Index = Op.getOperand(2);
5325 SDLoc dl(Op);
5326
5327 EVT PTy = getPointerTy(DAG.getDataLayout());
5328 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5329 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5330 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5331 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5332 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5333 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5334 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5335 // which does another jump to the destination. This also makes it easier
5336 // to translate it to TBB / TBH later (Thumb2 only).
5337 // FIXME: This might not work if the function is extremely large.
5338 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5339 Addr, Op.getOperand(2), JTI);
5340 }
5341 if (isPositionIndependent() || Subtarget->isROPI()) {
5342 Addr =
5343 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5344 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5345 Chain = Addr.getValue(1);
5346 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5347 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5348 } else {
5349 Addr =
5350 DAG.getLoad(PTy, dl, Chain, Addr,
5351 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5352 Chain = Addr.getValue(1);
5353 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5354 }
5355}
5356
5357static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5358 EVT VT = Op.getValueType();
5359 SDLoc dl(Op);
5360
5361 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5362 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5363 return Op;
5364 return DAG.UnrollVectorOp(Op.getNode());
5365 }
5366
5367 const bool HasFullFP16 =
5368 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5369
5370 EVT NewTy;
5371 const EVT OpTy = Op.getOperand(0).getValueType();
5372 if (OpTy == MVT::v4f32)
5373 NewTy = MVT::v4i32;
5374 else if (OpTy == MVT::v4f16 && HasFullFP16)
5375 NewTy = MVT::v4i16;
5376 else if (OpTy == MVT::v8f16 && HasFullFP16)
5377 NewTy = MVT::v8i16;
5378 else
5379 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5379)
;
5380
5381 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5382 return DAG.UnrollVectorOp(Op.getNode());
5383
5384 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5385 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5386}
5387
5388SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5389 EVT VT = Op.getValueType();
5390 if (VT.isVector())
5391 return LowerVectorFP_TO_INT(Op, DAG);
5392
5393 bool IsStrict = Op->isStrictFPOpcode();
5394 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5395
5396 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5397 RTLIB::Libcall LC;
5398 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5399 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5400 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5401 Op.getValueType());
5402 else
5403 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5404 Op.getValueType());
5405 SDLoc Loc(Op);
5406 MakeLibCallOptions CallOptions;
5407 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5408 SDValue Result;
5409 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5410 CallOptions, Loc, Chain);
5411 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5412 }
5413
5414 // FIXME: Remove this when we have strict fp instruction selection patterns
5415 if (IsStrict) {
5416 DAG.mutateStrictFPToFP(Op.getNode());
5417 }
5418
5419 return Op;
5420}
5421
5422static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5423 EVT VT = Op.getValueType();
5424 SDLoc dl(Op);
5425
5426 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5427 if (VT.getVectorElementType() == MVT::f32)
5428 return Op;
5429 return DAG.UnrollVectorOp(Op.getNode());
5430 }
5431
5432 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5434, __PRETTY_FUNCTION__))
5433 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5434, __PRETTY_FUNCTION__))
5434 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5434, __PRETTY_FUNCTION__))
;
5435
5436 const bool HasFullFP16 =
5437 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5438
5439 EVT DestVecType;
5440 if (VT == MVT::v4f32)
5441 DestVecType = MVT::v4i32;
5442 else if (VT == MVT::v4f16 && HasFullFP16)
5443 DestVecType = MVT::v4i16;
5444 else if (VT == MVT::v8f16 && HasFullFP16)
5445 DestVecType = MVT::v8i16;
5446 else
5447 return DAG.UnrollVectorOp(Op.getNode());
5448
5449 unsigned CastOpc;
5450 unsigned Opc;
5451 switch (Op.getOpcode()) {
5452 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5452)
;
5453 case ISD::SINT_TO_FP:
5454 CastOpc = ISD::SIGN_EXTEND;
5455 Opc = ISD::SINT_TO_FP;
5456 break;
5457 case ISD::UINT_TO_FP:
5458 CastOpc = ISD::ZERO_EXTEND;
5459 Opc = ISD::UINT_TO_FP;
5460 break;
5461 }
5462
5463 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5464 return DAG.getNode(Opc, dl, VT, Op);
5465}
5466
5467SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5468 EVT VT = Op.getValueType();
5469 if (VT.isVector())
5470 return LowerVectorINT_TO_FP(Op, DAG);
5471 if (isUnsupportedFloatingType(VT)) {
5472 RTLIB::Libcall LC;
5473 if (Op.getOpcode() == ISD::SINT_TO_FP)
5474 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5475 Op.getValueType());
5476 else
5477 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5478 Op.getValueType());
5479 MakeLibCallOptions CallOptions;
5480 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5481 CallOptions, SDLoc(Op)).first;
5482 }
5483
5484 return Op;
5485}
5486
5487SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5488 // Implement fcopysign with a fabs and a conditional fneg.
5489 SDValue Tmp0 = Op.getOperand(0);
5490 SDValue Tmp1 = Op.getOperand(1);
5491 SDLoc dl(Op);
5492 EVT VT = Op.getValueType();
5493 EVT SrcVT = Tmp1.getValueType();
5494 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5495 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5496 bool UseNEON = !InGPR && Subtarget->hasNEON();
5497
5498 if (UseNEON) {
5499 // Use VBSL to copy the sign bit.
5500 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5501 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5502 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5503 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5504 if (VT == MVT::f64)
5505 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5506 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5507 DAG.getConstant(32, dl, MVT::i32));
5508 else /*if (VT == MVT::f32)*/
5509 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5510 if (SrcVT == MVT::f32) {
5511 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5512 if (VT == MVT::f64)
5513 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5514 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5515 DAG.getConstant(32, dl, MVT::i32));
5516 } else if (VT == MVT::f32)
5517 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5518 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5519 DAG.getConstant(32, dl, MVT::i32));
5520 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5521 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5522
5523 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5524 dl, MVT::i32);
5525 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5526 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5527 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5528
5529 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5530 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5531 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5532 if (VT == MVT::f32) {
5533 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5534 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5535 DAG.getConstant(0, dl, MVT::i32));
5536 } else {
5537 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5538 }
5539
5540 return Res;
5541 }
5542
5543 // Bitcast operand 1 to i32.
5544 if (SrcVT == MVT::f64)
5545 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5546 Tmp1).getValue(1);
5547 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5548
5549 // Or in the signbit with integer operations.
5550 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5551 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5552 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5553 if (VT == MVT::f32) {
5554 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5555 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5556 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5557 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5558 }
5559
5560 // f64: Or the high part with signbit and then combine two parts.
5561 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5562 Tmp0);
5563 SDValue Lo = Tmp0.getValue(0);
5564 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5565 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5566 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5567}
5568
5569SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5570 MachineFunction &MF = DAG.getMachineFunction();
5571 MachineFrameInfo &MFI = MF.getFrameInfo();
5572 MFI.setReturnAddressIsTaken(true);
5573
5574 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5575 return SDValue();
5576
5577 EVT VT = Op.getValueType();
5578 SDLoc dl(Op);
5579 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5580 if (Depth) {
5581 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5582 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5583 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5584 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5585 MachinePointerInfo());
5586 }
5587
5588 // Return LR, which contains the return address. Mark it an implicit live-in.
5589 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5590 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5591}
5592
5593SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5594 const ARMBaseRegisterInfo &ARI =
5595 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5596 MachineFunction &MF = DAG.getMachineFunction();
5597 MachineFrameInfo &MFI = MF.getFrameInfo();
5598 MFI.setFrameAddressIsTaken(true);
5599
5600 EVT VT = Op.getValueType();
5601 SDLoc dl(Op); // FIXME probably not meaningful
5602 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5603 Register FrameReg = ARI.getFrameRegister(MF);
5604 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5605 while (Depth--)
5606 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5607 MachinePointerInfo());
5608 return FrameAddr;
5609}
5610
5611// FIXME? Maybe this could be a TableGen attribute on some registers and
5612// this table could be generated automatically from RegInfo.
5613Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5614 const MachineFunction &MF) const {
5615 Register Reg = StringSwitch<unsigned>(RegName)
5616 .Case("sp", ARM::SP)
5617 .Default(0);
5618 if (Reg)
5619 return Reg;
5620 report_fatal_error(Twine("Invalid register name \""
5621 + StringRef(RegName) + "\"."));
5622}
5623
5624// Result is 64 bit value so split into two 32 bit values and return as a
5625// pair of values.
5626static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5627 SelectionDAG &DAG) {
5628 SDLoc DL(N);
5629
5630 // This function is only supposed to be called for i64 type destination.
5631 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5632, __PRETTY_FUNCTION__))
5632 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5632, __PRETTY_FUNCTION__))
;
5633
5634 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5635 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5636 N->getOperand(0),
5637 N->getOperand(1));
5638
5639 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5640 Read.getValue(1)));
5641 Results.push_back(Read.getOperand(0));
5642}
5643
5644/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5645/// When \p DstVT, the destination type of \p BC, is on the vector
5646/// register bank and the source of bitcast, \p Op, operates on the same bank,
5647/// it might be possible to combine them, such that everything stays on the
5648/// vector register bank.
5649/// \p return The node that would replace \p BT, if the combine
5650/// is possible.
5651static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5652 SelectionDAG &DAG) {
5653 SDValue Op = BC->getOperand(0);
5654 EVT DstVT = BC->getValueType(0);
5655
5656 // The only vector instruction that can produce a scalar (remember,
5657 // since the bitcast was about to be turned into VMOVDRR, the source
5658 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5659 // Moreover, we can do this combine only if there is one use.
5660 // Finally, if the destination type is not a vector, there is not
5661 // much point on forcing everything on the vector bank.
5662 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5663 !Op.hasOneUse())
5664 return SDValue();
5665
5666 // If the index is not constant, we will introduce an additional
5667 // multiply that will stick.
5668 // Give up in that case.
5669 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5670 if (!Index)
5671 return SDValue();
5672 unsigned DstNumElt = DstVT.getVectorNumElements();
5673
5674 // Compute the new index.
5675 const APInt &APIntIndex = Index->getAPIntValue();
5676 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5677 NewIndex *= APIntIndex;
5678 // Check if the new constant index fits into i32.
5679 if (NewIndex.getBitWidth() > 32)
5680 return SDValue();
5681
5682 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5683 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5684 SDLoc dl(Op);
5685 SDValue ExtractSrc = Op.getOperand(0);
5686 EVT VecVT = EVT::getVectorVT(
5687 *DAG.getContext(), DstVT.getScalarType(),
5688 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5689 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5690 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5691 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5692}
5693
5694/// ExpandBITCAST - If the target supports VFP, this function is called to
5695/// expand a bit convert where either the source or destination type is i64 to
5696/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5697/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5698/// vectors), since the legalizer won't know what to do with that.
5699static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5700 const ARMSubtarget *Subtarget) {
5701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5702 SDLoc dl(N);
5703 SDValue Op = N->getOperand(0);
5704
5705 // This function is only supposed to be called for i64 types, either as the
5706 // source or destination of the bit convert.
5707 EVT SrcVT = Op.getValueType();
5708 EVT DstVT = N->getValueType(0);
5709 const bool HasFullFP16 = Subtarget->hasFullFP16();
5710
5711 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5712 // FullFP16: half values are passed in S-registers, and we don't
5713 // need any of the bitcast and moves:
5714 //
5715 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5716 // t5: i32 = bitcast t2
5717 // t18: f16 = ARMISD::VMOVhr t5
5718 if (Op.getOpcode() != ISD::CopyFromReg ||
5719 Op.getValueType() != MVT::f32)
5720 return SDValue();
5721
5722 auto Move = N->use_begin();
5723 if (Move->getOpcode() != ARMISD::VMOVhr)
5724 return SDValue();
5725
5726 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5727 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5728 DAG.ReplaceAllUsesWith(*Move, &Copy);
5729 return Copy;
5730 }
5731
5732 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5733 if (!HasFullFP16)
5734 return SDValue();
5735 // SoftFP: read half-precision arguments:
5736 //
5737 // t2: i32,ch = ...
5738 // t7: i16 = truncate t2 <~~~~ Op
5739 // t8: f16 = bitcast t7 <~~~~ N
5740 //
5741 if (Op.getOperand(0).getValueType() == MVT::i32)
5742 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5743 MVT::f16, Op.getOperand(0));
5744
5745 return SDValue();
5746 }
5747
5748 // Half-precision return values
5749 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5750 if (!HasFullFP16)
5751 return SDValue();
5752 //
5753 // t11: f16 = fadd t8, t10
5754 // t12: i16 = bitcast t11 <~~~ SDNode N
5755 // t13: i32 = zero_extend t12
5756 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5757 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5758 //
5759 // transform this into:
5760 //
5761 // t20: i32 = ARMISD::VMOVrh t11
5762 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5763 //
5764 auto ZeroExtend = N->use_begin();
5765 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5766 ZeroExtend->getValueType(0) != MVT::i32)
5767 return SDValue();
5768
5769 auto Copy = ZeroExtend->use_begin();
5770 if (Copy->getOpcode() == ISD::CopyToReg &&
5771 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5772 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5773 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5774 return Cvt;
5775 }
5776 return SDValue();
5777 }
5778
5779 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5780 return SDValue();
5781
5782 // Turn i64->f64 into VMOVDRR.
5783 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5784 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5785 // if we can combine the bitcast with its source.
5786 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5787 return Val;
5788
5789 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5790 DAG.getConstant(0, dl, MVT::i32));
5791 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5792 DAG.getConstant(1, dl, MVT::i32));
5793 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5794 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5795 }
5796
5797 // Turn f64->i64 into VMOVRRD.
5798 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5799 SDValue Cvt;
5800 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5801 SrcVT.getVectorNumElements() > 1)
5802 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5803 DAG.getVTList(MVT::i32, MVT::i32),
5804 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5805 else
5806 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5807 DAG.getVTList(MVT::i32, MVT::i32), Op);
5808 // Merge the pieces into a single i64 value.
5809 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5810 }
5811
5812 return SDValue();
5813}
5814
5815/// getZeroVector - Returns a vector of specified type with all zero elements.
5816/// Zero vectors are used to represent vector negation and in those cases
5817/// will be implemented with the NEON VNEG instruction. However, VNEG does
5818/// not support i64 elements, so sometimes the zero vectors will need to be
5819/// explicitly constructed. Regardless, use a canonical VMOV to create the
5820/// zero vector.
5821static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5822 assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5822, __PRETTY_FUNCTION__))
;
5823 // The canonical modified immediate encoding of a zero vector is....0!
5824 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5825 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5826 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5827 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5828}
5829
5830/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5831/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5832SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5833 SelectionDAG &DAG) const {
5834 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5834, __PRETTY_FUNCTION__))
;
5835 EVT VT = Op.getValueType();
5836 unsigned VTBits = VT.getSizeInBits();
5837 SDLoc dl(Op);
5838 SDValue ShOpLo = Op.getOperand(0);
5839 SDValue ShOpHi = Op.getOperand(1);
5840 SDValue ShAmt = Op.getOperand(2);
5841 SDValue ARMcc;
5842 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5843 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5844
5845 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::
SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5845, __PRETTY_FUNCTION__))
;
5846
5847 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5848 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5849 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5850 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5851 DAG.getConstant(VTBits, dl, MVT::i32));
5852 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5853 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5854 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5855 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5856 ISD::SETGE, ARMcc, DAG, dl);
5857 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5858 ARMcc, CCR, CmpLo);
5859
5860 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5861 SDValue HiBigShift = Opc == ISD::SRA
5862 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5863 DAG.getConstant(VTBits - 1, dl, VT))
5864 : DAG.getConstant(0, dl, VT);
5865 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5866 ISD::SETGE, ARMcc, DAG, dl);
5867 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5868 ARMcc, CCR, CmpHi);
5869
5870 SDValue Ops[2] = { Lo, Hi };
5871 return DAG.getMergeValues(Ops, dl);
5872}
5873
5874/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5875/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5876SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5877 SelectionDAG &DAG) const {
5878 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5878, __PRETTY_FUNCTION__))
;
5879 EVT VT = Op.getValueType();
5880 unsigned VTBits = VT.getSizeInBits();
5881 SDLoc dl(Op);
5882 SDValue ShOpLo = Op.getOperand(0);
5883 SDValue ShOpHi = Op.getOperand(1);
5884 SDValue ShAmt = Op.getOperand(2);
5885 SDValue ARMcc;
5886 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5887
5888 assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void>
(0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5888, __PRETTY_FUNCTION__))
;
5889 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5890 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5891 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5892 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5893 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5894
5895 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5896 DAG.getConstant(VTBits, dl, MVT::i32));
5897 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5898 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5899 ISD::SETGE, ARMcc, DAG, dl);
5900 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5901 ARMcc, CCR, CmpHi);
5902
5903 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5904 ISD::SETGE, ARMcc, DAG, dl);
5905 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5906 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5907 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5908
5909 SDValue Ops[2] = { Lo, Hi };
5910 return DAG.getMergeValues(Ops, dl);
5911}
5912
5913SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5914 SelectionDAG &DAG) const {
5915 // The rounding mode is in bits 23:22 of the FPSCR.
5916 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5917 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5918 // so that the shift + and get folded into a bitfield extract.
5919 SDLoc dl(Op);
5920 SDValue Ops[] = { DAG.getEntryNode(),
5921 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5922
5923 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5924 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5925 DAG.getConstant(1U << 22, dl, MVT::i32));
5926 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5927 DAG.getConstant(22, dl, MVT::i32));
5928 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5929 DAG.getConstant(3, dl, MVT::i32));
5930}
5931
5932static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5933 const ARMSubtarget *ST) {
5934 SDLoc dl(N);
5935 EVT VT = N->getValueType(0);
5936 if (VT.isVector() && ST->hasNEON()) {
5937
5938 // Compute the least significant set bit: LSB = X & -X
5939 SDValue X = N->getOperand(0);
5940 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5941 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5942
5943 EVT ElemTy = VT.getVectorElementType();
5944
5945 if (ElemTy == MVT::i8) {
5946 // Compute with: cttz(x) = ctpop(lsb - 1)
5947 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5948 DAG.getTargetConstant(1, dl, ElemTy));
5949 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5950 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5951 }
5952
5953 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5954 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5955 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5956 unsigned NumBits = ElemTy.getSizeInBits();
5957 SDValue WidthMinus1 =
5958 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5959 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5960 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5961 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5962 }
5963
5964 // Compute with: cttz(x) = ctpop(lsb - 1)
5965
5966 // Compute LSB - 1.
5967 SDValue Bits;
5968 if (ElemTy == MVT::i64) {
5969 // Load constant 0xffff'ffff'ffff'ffff to register.
5970 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5971 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5972 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5973 } else {
5974 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5975 DAG.getTargetConstant(1, dl, ElemTy));
5976 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5977 }
5978 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5979 }
5980
5981 if (!ST->hasV6T2Ops())
5982 return SDValue();
5983
5984 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5985 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5986}