/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Bug Summary

File:	llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Warning:	line 1049, column 44 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMLowOverheadLoops.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

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1//===-- ARMLowOverheadLoops.cpp - CodeGen Low-overhead Loops ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Finalize v8.1-m low-overhead loops by converting the associated pseudo
10/// instructions into machine operations.
11/// The expectation is that the loop contains three pseudo instructions:
12/// - t2*LoopStart - placed in the preheader or pre-preheader. The do-loop
13///   form should be in the preheader, whereas the while form should be in the
14///   preheaders only predecessor.
15/// - t2LoopDec - placed within in the loop body.
16/// - t2LoopEnd - the loop latch terminator.
17///
18/// In addition to this, we also look for the presence of the VCTP instruction,
19/// which determines whether we can generated the tail-predicated low-overhead
20/// loop form.
21///
22/// Assumptions and Dependencies:
23/// Low-overhead loops are constructed and executed using a setup instruction:
24/// DLS, WLS, DLSTP or WLSTP and an instruction that loops back: LE or LETP.
25/// WLS(TP) and LE(TP) are branching instructions with a (large) limited range
26/// but fixed polarity: WLS can only branch forwards and LE can only branch
27/// backwards. These restrictions mean that this pass is dependent upon block
28/// layout and block sizes, which is why it's the last pass to run. The same is
29/// true for ConstantIslands, but this pass does not increase the size of the
30/// basic blocks, nor does it change the CFG. Instructions are mainly removed
31/// during the transform and pseudo instructions are replaced by real ones. In
32/// some cases, when we have to revert to a 'normal' loop, we have to introduce
33/// multiple instructions for a single pseudo (see RevertWhile and
34/// RevertLoopEnd). To handle this situation, t2WhileLoopStart and t2LoopEnd
35/// are defined to be as large as this maximum sequence of replacement
36/// instructions.
37///
38//===----------------------------------------------------------------------===//

40#include "ARM.h"
41#include "ARMBaseInstrInfo.h"
42#include "ARMBaseRegisterInfo.h"
43#include "ARMBasicBlockInfo.h"
44#include "ARMSubtarget.h"
45#include "Thumb2InstrInfo.h"
46#include "llvm/ADT/SetOperations.h"
47#include "llvm/ADT/SmallSet.h"
48#include "llvm/CodeGen/LivePhysRegs.h"
49#include "llvm/CodeGen/MachineFunctionPass.h"
50#include "llvm/CodeGen/MachineLoopInfo.h"
51#include "llvm/CodeGen/MachineLoopUtils.h"
52#include "llvm/CodeGen/MachineRegisterInfo.h"
53#include "llvm/CodeGen/Passes.h"
54#include "llvm/CodeGen/ReachingDefAnalysis.h"
55#include "llvm/MC/MCInstrDesc.h"

57using namespace llvm;

59#define DEBUG_TYPE"arm-low-overhead-loops" "arm-low-overhead-loops"
60#define ARM_LOW_OVERHEAD_LOOPS_NAME"ARM Low Overhead Loops pass" "ARM Low Overhead Loops pass"

62namespace {

class PostOrderLoopTraversal {
  MachineLoop &ML;
  MachineLoopInfo &MLI;
  SmallPtrSet<MachineBasicBlock*, 4> Visited;
  SmallVector<MachineBasicBlock*, 4> Order;

public:
  PostOrderLoopTraversal(MachineLoop &ML, MachineLoopInfo &MLI)
    : ML(ML), MLI(MLI) { }

  const SmallVectorImpl<MachineBasicBlock*> &getOrder() const {
    return Order;
  }

  // Visit all the blocks within the loop, as well as exit blocks and any
  // blocks properly dominating the header.
  void ProcessLoop() {
    std::function<void(MachineBasicBlock*)> Search = [this, &Search]
      (MachineBasicBlock *MBB) -> void {
      if (Visited.count(MBB))
        return;

      Visited.insert(MBB);
      for (auto *Succ : MBB->successors()) {
        if (!ML.contains(Succ))
          continue;
        Search(Succ);
      }
      Order.push_back(MBB);
    };

    // Insert exit blocks.
    SmallVector<MachineBasicBlock*, 2> ExitBlocks;
    ML.getExitBlocks(ExitBlocks);
    for (auto *MBB : ExitBlocks)
      Order.push_back(MBB);

    // Then add the loop body.
    Search(ML.getHeader());

    // Then try the preheader and its predecessors.
    std::function<void(MachineBasicBlock*)> GetPredecessor =
      [this, &GetPredecessor] (MachineBasicBlock *MBB) -> void {
      Order.push_back(MBB);
      if (MBB->pred_size() == 1)
        GetPredecessor(*MBB->pred_begin());
    };

    if (auto *Preheader = ML.getLoopPreheader())
      GetPredecessor(Preheader);
    else if (auto *Preheader = MLI.findLoopPreheader(&ML, true))
      GetPredecessor(Preheader);
  }
};

struct PredicatedMI {
  MachineInstr *MI = nullptr;
  SetVector<MachineInstr*> Predicates;

public:
  PredicatedMI(MachineInstr *I, SetVector<MachineInstr*> &Preds) :
    MI(I) { Predicates.insert(Preds.begin(), Preds.end()); }
};

// Represent a VPT block, a list of instructions that begins with a VPST and
// has a maximum of four proceeding instructions. All instructions within the
// block are predicated upon the vpr and we allow instructions to define the
// vpr within in the block too.
class VPTBlock {
  std::unique_ptr<PredicatedMI> VPST;
  PredicatedMI *Divergent = nullptr;
  SmallVector<PredicatedMI, 4> Insts;

public:
  VPTBlock(MachineInstr *MI, SetVector<MachineInstr*> &Preds) {
    VPST = std::make_unique<PredicatedMI>(MI, Preds);
  }

  void addInst(MachineInstr *MI, SetVector<MachineInstr*> &Preds) {
    LLVM_DEBUG(dbgs() << "ARM Loops: Adding predicated MI: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Adding predicated MI: "
 << *MI; } } while (false);
    if (!Divergent && !set_difference(Preds, VPST->Predicates).empty()) {
      Divergent = &Insts.back();
      LLVM_DEBUG(dbgs() << " - has divergent predicate: " << *Divergent->MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << " - has divergent predicate: "
 << *Divergent->MI; } } while (false);
    }
    Insts.emplace_back(MI, Preds);
    assert(Insts.size() <= 4 && "Too many instructions in VPT block!")((Insts.size() <= 4 && "Too many instructions in VPT block!"
) ? static_cast<void> (0) : __assert_fail ("Insts.size() <= 4 && \"Too many instructions in VPT block!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 149, __PRETTY_FUNCTION__));
  }

  // Have we found an instruction within the block which defines the vpr? If
  // so, not all the instructions in the block will have the same predicate.
  bool HasNonUniformPredicate() const {
    return Divergent != nullptr;
3
←
Assuming the condition is true→
4
←
Returning the value 1, which participates in a condition later→
  }

  // Is the given instruction part of the predicate set controlling the entry
  // to the block.
  bool IsPredicatedOn(MachineInstr *MI) const {
    return VPST->Predicates.count(MI);
  }

  // Is the given instruction the only predicate which controls the entry to
  // the block.
  bool IsOnlyPredicatedOn(MachineInstr *MI) const {
    return IsPredicatedOn(MI) && VPST->Predicates.size() == 1;
14
←
Assuming the condition is true→
15
←
Assuming the condition is true→
16
←
Returning the value 1, which participates in a condition later→
  }

  unsigned size() const { return Insts.size(); }
  SmallVectorImpl<PredicatedMI> &getInsts() { return Insts; }
  MachineInstr *getVPST() const { return VPST->MI; }
  PredicatedMI *getDivergent() const { return Divergent; }
};

struct LowOverheadLoop {

  MachineLoop &ML;
  MachineLoopInfo &MLI;
  ReachingDefAnalysis &RDA;
  const TargetRegisterInfo &TRI;
  MachineFunction *MF = nullptr;
  MachineInstr *InsertPt = nullptr;
  MachineInstr *Start = nullptr;
  MachineInstr *Dec = nullptr;
  MachineInstr *End = nullptr;
  MachineInstr *VCTP = nullptr;
  VPTBlock *CurrentBlock = nullptr;
  SetVector<MachineInstr*> CurrentPredicate;
  SmallVector<VPTBlock, 4> VPTBlocks;
  SmallPtrSet<MachineInstr*, 4> ToRemove;
  bool Revert = false;
  bool CannotTailPredicate = false;

  LowOverheadLoop(MachineLoop &ML, MachineLoopInfo &MLI,
                  ReachingDefAnalysis &RDA, const TargetRegisterInfo &TRI)
    : ML(ML), MLI(MLI), RDA(RDA), TRI(TRI) {
    MF = ML.getHeader()->getParent();
  }

  // If this is an MVE instruction, check that we know how to use tail
  // predication with it. Record VPT blocks and return whether the
  // instruction is valid for tail predication.
  bool ValidateMVEInst(MachineInstr *MI);

  void AnalyseMVEInst(MachineInstr *MI) {
    CannotTailPredicate = !ValidateMVEInst(MI);
  }

  bool IsTailPredicationLegal() const {
    // For now, let's keep things really simple and only support a single
    // block for tail predication.
    return !Revert && FoundAllComponents() && VCTP &&
           !CannotTailPredicate && ML.getNumBlocks() == 1;
  }

  // Check that the predication in the loop will be equivalent once we
  // perform the conversion. Also ensure that we can provide the number
  // of elements to the loop start instruction.
  bool ValidateTailPredicate(MachineInstr *StartInsertPt);

  // Check that any values available outside of the loop will be the same
  // after tail predication conversion.
  bool ValidateLiveOuts() const;

  // Is it safe to define LR with DLS/WLS?
  // LR can be defined if it is the operand to start, because it's the same
  // value, or if it's going to be equivalent to the operand to Start.
  MachineInstr *isSafeToDefineLR();

  // Check the branch targets are within range and we satisfy our
  // restrictions.
  void CheckLegality(ARMBasicBlockUtils *BBUtils);

  bool FoundAllComponents() const {
    return Start && Dec && End;
  }

  SmallVectorImpl<VPTBlock> &getVPTBlocks() { return VPTBlocks; }

  // Return the loop iteration count, or the number of elements if we're tail
  // predicating.
  MachineOperand &getCount() {
    return IsTailPredicationLegal() ?
      VCTP->getOperand(1) : Start->getOperand(0);
  }

  unsigned getStartOpcode() const {
    bool IsDo = Start->getOpcode() == ARM::t2DoLoopStart;
    if (!IsTailPredicationLegal())
      return IsDo ? ARM::t2DLS : ARM::t2WLS;

    return VCTPOpcodeToLSTP(VCTP->getOpcode(), IsDo);
  }

  void dump() const {
    if (Start) dbgs() << "ARM Loops: Found Loop Start: " << *Start;
    if (Dec) dbgs() << "ARM Loops: Found Loop Dec: " << *Dec;
    if (End) dbgs() << "ARM Loops: Found Loop End: " << *End;
    if (VCTP) dbgs() << "ARM Loops: Found VCTP: " << *VCTP;
    if (!FoundAllComponents())
      dbgs() << "ARM Loops: Not a low-overhead loop.\n";
    else if (!(Start && Dec && End))
      dbgs() << "ARM Loops: Failed to find all loop components.\n";
  }
};

class ARMLowOverheadLoops : public MachineFunctionPass {
  MachineFunction           *MF = nullptr;
  MachineLoopInfo           *MLI = nullptr;
  ReachingDefAnalysis       *RDA = nullptr;
  const ARMBaseInstrInfo    *TII = nullptr;
  MachineRegisterInfo       *MRI = nullptr;
  const TargetRegisterInfo  *TRI = nullptr;
  std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;

public:
  static char ID;

  ARMLowOverheadLoops() : MachineFunctionPass(ID) { }

  void getAnalysisUsage(AnalysisUsage &AU) const override {
    AU.setPreservesCFG();
    AU.addRequired<MachineLoopInfo>();
    AU.addRequired<ReachingDefAnalysis>();
    MachineFunctionPass::getAnalysisUsage(AU);
  }

  bool runOnMachineFunction(MachineFunction &MF) override;

  MachineFunctionProperties getRequiredProperties() const override {
    return MachineFunctionProperties().set(
        MachineFunctionProperties::Property::NoVRegs).set(
        MachineFunctionProperties::Property::TracksLiveness);
  }

  StringRef getPassName() const override {
    return ARM_LOW_OVERHEAD_LOOPS_NAME"ARM Low Overhead Loops pass";
  }

private:
  bool ProcessLoop(MachineLoop *ML);

  bool RevertNonLoops();

  void RevertWhile(MachineInstr *MI) const;

  bool RevertLoopDec(MachineInstr *MI) const;

  void RevertLoopEnd(MachineInstr *MI, bool SkipCmp = false) const;

  void ConvertVPTBlocks(LowOverheadLoop &LoLoop);

  MachineInstr *ExpandLoopStart(LowOverheadLoop &LoLoop);

  void Expand(LowOverheadLoop &LoLoop);

  void IterationCountDCE(LowOverheadLoop &LoLoop);
};
320}

322char ARMLowOverheadLoops::ID = 0;

324INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,static void *initializeARMLowOverheadLoopsPassOnce(PassRegistry
 &Registry) { PassInfo *PI = new PassInfo( "ARM Low Overhead Loops pass"
, "arm-low-overhead-loops", &ARMLowOverheadLoops::ID, PassInfo
::NormalCtor_t(callDefaultCtor<ARMLowOverheadLoops>), false
, false); Registry.registerPass(*PI, true); return PI; } static
 llvm::once_flag InitializeARMLowOverheadLoopsPassFlag; void llvm
::initializeARMLowOverheadLoopsPass(PassRegistry &Registry
) { llvm::call_once(InitializeARMLowOverheadLoopsPassFlag, initializeARMLowOverheadLoopsPassOnce
, std::ref(Registry)); }
              false, false)static void *initializeARMLowOverheadLoopsPassOnce(PassRegistry
 &Registry) { PassInfo *PI = new PassInfo( "ARM Low Overhead Loops pass"
, "arm-low-overhead-loops", &ARMLowOverheadLoops::ID, PassInfo
::NormalCtor_t(callDefaultCtor<ARMLowOverheadLoops>), false
, false); Registry.registerPass(*PI, true); return PI; } static
 llvm::once_flag InitializeARMLowOverheadLoopsPassFlag; void llvm
::initializeARMLowOverheadLoopsPass(PassRegistry &Registry
) { llvm::call_once(InitializeARMLowOverheadLoopsPassFlag, initializeARMLowOverheadLoopsPassOnce
, std::ref(Registry)); }

327MachineInstr *LowOverheadLoop::isSafeToDefineLR() {
// We can define LR because LR already contains the same value.
if (Start->getOperand(0).getReg() == ARM::LR)
  return Start;

unsigned CountReg = Start->getOperand(0).getReg();
auto IsMoveLR = [&CountReg](MachineInstr *MI) {
  return MI->getOpcode() == ARM::tMOVr &&
         MI->getOperand(0).getReg() == ARM::LR &&
         MI->getOperand(1).getReg() == CountReg &&
         MI->getOperand(2).getImm() == ARMCC::AL;
 };

MachineBasicBlock *MBB = Start->getParent();

// Find an insertion point:
// - Is there a (mov lr, Count) before Start? If so, and nothing else writes
//   to Count before Start, we can insert at that mov.
if (auto *LRDef = RDA.getUniqueReachingMIDef(Start, ARM::LR))
  if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg))
    return LRDef;

// - Is there a (mov lr, Count) after Start? If so, and nothing else writes
//   to Count after Start, we can insert at that mov.
if (auto *LRDef = RDA.getLocalLiveOutMIDef(MBB, ARM::LR))
  if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg))
    return LRDef;

// We've found no suitable LR def and Start doesn't use LR directly. Can we
// just define LR anyway?
return RDA.isSafeToDefRegAt(Start, ARM::LR) ? Start : nullptr;
358}

360bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) {
assert(VCTP && "VCTP instruction expected but is not set")((VCTP && "VCTP instruction expected but is not set")
 ? static_cast<void> (0) : __assert_fail ("VCTP && \"VCTP instruction expected but is not set\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 361, __PRETTY_FUNCTION__));
// All predication within the loop should be based on vctp. If the block
// isn't predicated on entry, check whether the vctp is within the block
// and that all other instructions are then predicated on it.
for (auto &Block : VPTBlocks) {
  if (Block.IsPredicatedOn(VCTP))
    continue;
  if (!Block.HasNonUniformPredicate() || !isVCTP(Block.getDivergent()->MI)) {
    LLVM_DEBUG(dbgs() << "ARM Loops: Found unsupported diverging predicate: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found unsupported diverging predicate: "
 << *Block.getDivergent()->MI; } } while (false)
               << *Block.getDivergent()->MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found unsupported diverging predicate: "
 << *Block.getDivergent()->MI; } } while (false);
    return false;
  }
  SmallVectorImpl<PredicatedMI> &Insts = Block.getInsts();
  for (auto &PredMI : Insts) {
    if (PredMI.Predicates.count(VCTP) || isVCTP(PredMI.MI))
      continue;
    LLVM_DEBUG(dbgs() << "ARM Loops: Can't convert: " << *PredMI.MIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Can't convert: "
 << *PredMI.MI << " - which is predicated on:\n";
 for (auto *MI : PredMI.Predicates) dbgs() << "   - " <<
 *MI; } } while (false)
               << " - which is predicated on:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Can't convert: "
 << *PredMI.MI << " - which is predicated on:\n";
 for (auto *MI : PredMI.Predicates) dbgs() << "   - " <<
 *MI; } } while (false)
               for (auto *MI : PredMI.Predicates)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Can't convert: "
 << *PredMI.MI << " - which is predicated on:\n";
 for (auto *MI : PredMI.Predicates) dbgs() << "   - " <<
 *MI; } } while (false)
                 dbgs() << "   - " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Can't convert: "
 << *PredMI.MI << " - which is predicated on:\n";
 for (auto *MI : PredMI.Predicates) dbgs() << "   - " <<
 *MI; } } while (false);
    return false;
  }
}

if (!ValidateLiveOuts())
  return false;

// For tail predication, we need to provide the number of elements, instead
// of the iteration count, to the loop start instruction. The number of
// elements is provided to the vctp instruction, so we need to check that
// we can use this register at InsertPt.
Register NumElements = VCTP->getOperand(1).getReg();

// If the register is defined within loop, then we can't perform TP.
// TODO: Check whether this is just a mov of a register that would be
// available.
if (RDA.hasLocalDefBefore(VCTP, NumElements)) {
  LLVM_DEBUG(dbgs() << "ARM Loops: VCTP operand is defined in the loop.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: VCTP operand is defined in the loop.\n"
; } } while (false);
  return false;
}

// The element count register maybe defined after InsertPt, in which case we
// need to try to move either InsertPt or the def so that the [w|d]lstp can
// use the value.
// TODO: On failing to move an instruction, check if the count is provided by
// a mov and whether we can use the mov operand directly.
MachineBasicBlock *InsertBB = StartInsertPt->getParent();
if (!RDA.isReachingDefLiveOut(StartInsertPt, NumElements)) {
  if (auto *ElemDef = RDA.getLocalLiveOutMIDef(InsertBB, NumElements)) {
    if (RDA.isSafeToMoveForwards(ElemDef, StartInsertPt)) {
      ElemDef->removeFromParent();
      InsertBB->insert(MachineBasicBlock::iterator(StartInsertPt), ElemDef);
      LLVM_DEBUG(dbgs() << "ARM Loops: Moved element count def: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Moved element count def: "
 << *ElemDef; } } while (false)
                 << *ElemDef)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Moved element count def: "
 << *ElemDef; } } while (false);
    } else if (RDA.isSafeToMoveBackwards(StartInsertPt, ElemDef)) {
      StartInsertPt->removeFromParent();
      InsertBB->insertAfter(MachineBasicBlock::iterator(ElemDef),
                            StartInsertPt);
      LLVM_DEBUG(dbgs() << "ARM Loops: Moved start past: " << *ElemDef)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Moved start past: "
 << *ElemDef; } } while (false);
    } else {
      LLVM_DEBUG(dbgs() << "ARM Loops: Unable to move element count to loop "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unable to move element count to loop "
 << "start instruction.\n"; } } while (false)
                 << "start instruction.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unable to move element count to loop "
 << "start instruction.\n"; } } while (false);
      return false;
    }
  }
}

// Especially in the case of while loops, InsertBB may not be the
// preheader, so we need to check that the register isn't redefined
// before entering the loop.
auto CannotProvideElements = [this](MachineBasicBlock *MBB,
                                    Register NumElements) {
  // NumElements is redefined in this block.
  if (RDA.hasLocalDefBefore(&MBB->back(), NumElements))
    return true;

  // Don't continue searching up through multiple predecessors.
  if (MBB->pred_size() > 1)
    return true;

  return false;
};

// First, find the block that looks like the preheader.
MachineBasicBlock *MBB = MLI.findLoopPreheader(&ML, true);
if (!MBB) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Didn't find preheader.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Didn't find preheader.\n"
; } } while (false);
  return false;
}

// Then search backwards for a def, until we get to InsertBB.
while (MBB != InsertBB) {
  if (CannotProvideElements(MBB, NumElements)) {
    LLVM_DEBUG(dbgs() << "ARM Loops: Unable to provide element count.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unable to provide element count.\n"
; } } while (false);
    return false;
  }
  MBB = *MBB->pred_begin();
}

// Check that the value change of the element count is what we expect and
// that the predication will be equivalent. For this we need:
// NumElements = NumElements - VectorWidth. The sub will be a sub immediate
// and we can also allow register copies within the chain too.
auto IsValidSub = [](MachineInstr *MI, unsigned ExpectedVecWidth) {
  unsigned ImmOpIdx = 0;
  switch (MI->getOpcode()) {
  default:
    llvm_unreachable("unhandled sub opcode")::llvm::llvm_unreachable_internal("unhandled sub opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 468);
  case ARM::tSUBi3:
  case ARM::tSUBi8:
    ImmOpIdx = 3;
    break;
  case ARM::t2SUBri:
  case ARM::t2SUBri12:
    ImmOpIdx = 2;
    break;
  }
  return MI->getOperand(ImmOpIdx).getImm() == ExpectedVecWidth;
};

MBB = VCTP->getParent();
if (auto *Def = RDA.getUniqueReachingMIDef(&MBB->back(), NumElements)) {
  SmallPtrSet<MachineInstr*, 2> ElementChain;
  SmallPtrSet<MachineInstr*, 2> Ignore = { VCTP };
  unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode());

  if (RDA.isSafeToRemove(Def, ElementChain, Ignore)) {
    bool FoundSub = false;

    for (auto *MI : ElementChain) {
      if (isMovRegOpcode(MI->getOpcode()))
        continue;

      if (isSubImmOpcode(MI->getOpcode())) {
        if (FoundSub || !IsValidSub(MI, ExpectedVectorWidth))
          return false;
        FoundSub = true;
      } else
        return false;
    }

    LLVM_DEBUG(dbgs() << "ARM Loops: Will remove element count chain:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove element count chain:\n"
; for (auto *MI : ElementChain) dbgs() << " - " <<
 *MI; } } while (false)
               for (auto *MI : ElementChain)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove element count chain:\n"
; for (auto *MI : ElementChain) dbgs() << " - " <<
 *MI; } } while (false)
                 dbgs() << " - " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove element count chain:\n"
; for (auto *MI : ElementChain) dbgs() << " - " <<
 *MI; } } while (false);
    ToRemove.insert(ElementChain.begin(), ElementChain.end());
  }
}
return true;
509}

511bool LowOverheadLoop::ValidateLiveOuts() const {
// Collect Q-regs that are live in the exit blocks. We don't collect scalars
// because they won't be affected by lane predication.
const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID);
SmallSet<Register, 2> LiveOuts;
SmallVector<MachineBasicBlock*, 2> ExitBlocks;
ML.getExitBlocks(ExitBlocks);
for (auto *MBB : ExitBlocks)
  for (const MachineBasicBlock::RegisterMaskPair &RegMask : MBB->liveins())
    if (QPRs->contains(RegMask.PhysReg))
      LiveOuts.insert(RegMask.PhysReg);

// Collect the instructions in the loop body that define the live-out values.
SmallPtrSet<MachineInstr*, 2> LiveMIs;
MachineBasicBlock *MBB = ML.getHeader();
for (auto Reg : LiveOuts)
  if (auto *MI = RDA.getLocalLiveOutMIDef(MBB, Reg))
    LiveMIs.insert(MI);

LLVM_DEBUG(dbgs() << "ARM Loops: Found loop live-outs:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found loop live-outs:\n"
; for (auto *MI : LiveMIs) dbgs() << " - " << *MI
; } } while (false)
           for (auto *MI : LiveMIs)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found loop live-outs:\n"
; for (auto *MI : LiveMIs) dbgs() << " - " << *MI
; } } while (false)
             dbgs() << " - " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found loop live-outs:\n"
; for (auto *MI : LiveMIs) dbgs() << " - " << *MI
; } } while (false);
// We've already validated that any VPT predication within the loop will be
// equivalent when we perform the predication transformation; so we know that
// any VPT predicated instruction is predicated upon VCTP. Any live-out
// instruction needs to be predicated, so check this here.
for (auto *MI : LiveMIs) {
  int PIdx = llvm::findFirstVPTPredOperandIdx(*MI);
  if (PIdx == -1 || MI->getOperand(PIdx+1).getReg() != ARM::VPR)
    return false;
}

return true;
544}

546void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
if (Revert)
  return;

if (!End->getOperand(1).isMBB())
  report_fatal_error("Expected LoopEnd to target basic block");

// TODO Maybe there's cases where the target doesn't have to be the header,
// but for now be safe and revert.
if (End->getOperand(1).getMBB() != ML.getHeader()) {
  LLVM_DEBUG(dbgs() << "ARM Loops: LoopEnd is not targetting header.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: LoopEnd is not targetting header.\n"
; } } while (false);
  Revert = true;
  return;
}

// The WLS and LE instructions have 12-bits for the label offset. WLS
// requires a positive offset, while LE uses negative.
if (BBUtils->getOffsetOf(End) < BBUtils->getOffsetOf(ML.getHeader()) ||
    !BBUtils->isBBInRange(End, ML.getHeader(), 4094)) {
  LLVM_DEBUG(dbgs() << "ARM Loops: LE offset is out-of-range\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: LE offset is out-of-range\n"
; } } while (false);
  Revert = true;
  return;
}

if (Start->getOpcode() == ARM::t2WhileLoopStart &&
    (BBUtils->getOffsetOf(Start) >
     BBUtils->getOffsetOf(Start->getOperand(1).getMBB()) ||
     !BBUtils->isBBInRange(Start, Start->getOperand(1).getMBB(), 4094))) {
  LLVM_DEBUG(dbgs() << "ARM Loops: WLS offset is out-of-range!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: WLS offset is out-of-range!\n"
; } } while (false);
  Revert = true;
  return;
}

InsertPt = Revert ? nullptr : isSafeToDefineLR();
if (!InsertPt) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unable to find safe insertion point.\n"
; } } while (false);
  Revert = true;
  return;
} else
  LLVM_DEBUG(dbgs() << "ARM Loops: Start insertion point: " << *InsertPt)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Start insertion point: "
 << *InsertPt; } } while (false);

if (!IsTailPredicationLegal()) {
  LLVM_DEBUG(if (!VCTP)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { if (!VCTP) dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n"
; dbgs() << "ARM Loops: Tail-predication is not valid.\n"
; } } while (false)
               dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { if (!VCTP) dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n"
; dbgs() << "ARM Loops: Tail-predication is not valid.\n"
; } } while (false)
             dbgs() << "ARM Loops: Tail-predication is not valid.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { if (!VCTP) dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n"
; dbgs() << "ARM Loops: Tail-predication is not valid.\n"
; } } while (false);
  return;
}

assert(ML.getBlocks().size() == 1 &&((ML.getBlocks().size() == 1 && "Shouldn't be processing a loop with more than one block"
) ? static_cast<void> (0) : __assert_fail ("ML.getBlocks().size() == 1 && \"Shouldn't be processing a loop with more than one block\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 595, __PRETTY_FUNCTION__))
       "Shouldn't be processing a loop with more than one block")((ML.getBlocks().size() == 1 && "Shouldn't be processing a loop with more than one block"
) ? static_cast<void> (0) : __assert_fail ("ML.getBlocks().size() == 1 && \"Shouldn't be processing a loop with more than one block\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 595, __PRETTY_FUNCTION__));
CannotTailPredicate = !ValidateTailPredicate(InsertPt);
LLVM_DEBUG(if (CannotTailPredicate)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { if (CannotTailPredicate) dbgs()
 << "ARM Loops: Couldn't validate tail predicate.\n"; }
 } while (false)
           dbgs() << "ARM Loops: Couldn't validate tail predicate.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { if (CannotTailPredicate) dbgs()
 << "ARM Loops: Couldn't validate tail predicate.\n"; }
 } while (false);
599}

601bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
if (CannotTailPredicate)
  return false;

// Only support a single vctp.
if (isVCTP(MI) && VCTP)
  return false;

// Start a new vpt block when we discover a vpt.
if (MI->getOpcode() == ARM::MVE_VPST) {
  VPTBlocks.emplace_back(MI, CurrentPredicate);
  CurrentBlock = &VPTBlocks.back();
  return true;
} else if (isVCTP(MI))
  VCTP = MI;
else if (MI->getOpcode() == ARM::MVE_VPSEL ||
         MI->getOpcode() == ARM::MVE_VPNOT)
  return false;

// TODO: Allow VPSEL and VPNOT, we currently cannot because:
// 1) It will use the VPR as a predicate operand, but doesn't have to be
//    instead a VPT block, which means we can assert while building up
//    the VPT block because we don't find another VPST to being a new
//    one.
// 2) VPSEL still requires a VPR operand even after tail predicating,
//    which means we can't remove it unless there is another
//    instruction, such as vcmp, that can provide the VPR def.

bool IsUse = false;
bool IsDef = false;
const MCInstrDesc &MCID = MI->getDesc();
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
  const MachineOperand &MO = MI->getOperand(i);
  if (!MO.isReg() || MO.getReg() != ARM::VPR)
    continue;

  if (MO.isDef()) {
    CurrentPredicate.insert(MI);
    IsDef = true;
  } else if (ARM::isVpred(MCID.OpInfo[i].OperandType)) {
    CurrentBlock->addInst(MI, CurrentPredicate);
    IsUse = true;
  } else {
    LLVM_DEBUG(dbgs() << "ARM Loops: Found instruction using vpr: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found instruction using vpr: "
 << *MI; } } while (false);
    return false;
  }
}

// If we find a vpr def that is not already predicated on the vctp, we've
// got disjoint predicates that may not be equivalent when we do the
// conversion.
if (IsDef && !IsUse && VCTP && !isVCTP(MI)) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Found disjoint vpr def: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found disjoint vpr def: "
 << *MI; } } while (false);
  return false;
}

uint64_t Flags = MCID.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
  return true;

// If we find an instruction that has been marked as not valid for tail
// predication, only allow the instruction if it's contained within a valid
// VPT block.
if ((Flags & ARMII::ValidForTailPredication) == 0 && !IsUse) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Can't tail predicate: "
 << *MI; } } while (false);
  return false;
}

// If the instruction is already explicitly predicated, then the conversion
// will be fine, but ensure that all memory operations are predicated.
return !IsUse && MI->mayLoadOrStore() ? false : true;
672}

674bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget());
if (!ST.hasLOB())
  return false;

MF = &mf;
LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops on "
 << MF->getName() << " ------------- \n"; } } while
 (false);

MLI = &getAnalysis<MachineLoopInfo>();
RDA = &getAnalysis<ReachingDefAnalysis>();
MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
MRI = &MF->getRegInfo();
TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
TRI = ST.getRegisterInfo();
BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(*MF));
BBUtils->computeAllBlockSizes();
BBUtils->adjustBBOffsetsAfter(&MF->front());

bool Changed = false;
for (auto ML : *MLI) {
  if (!ML->getParentLoop())
    Changed |= ProcessLoop(ML);
}
Changed |= RevertNonLoops();
return Changed;
699}

701bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {

bool Changed = false;

// Process inner loops first.
for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
  Changed |= ProcessLoop(*I);

LLVM_DEBUG(dbgs() << "ARM Loops: Processing loop containing:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
           if (auto *Preheader = ML->getLoopPreheader())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
             dbgs() << " - " << Preheader->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
           else if (auto *Preheader = MLI->findLoopPreheader(ML))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
             dbgs() << " - " << Preheader->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
           else if (auto *Preheader = MLI->findLoopPreheader(ML, true))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
             dbgs() << " - " << Preheader->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
           for (auto *MBB : ML->getBlocks())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
             dbgs() << " - " << MBB->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false)
          )do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Processing loop containing:\n"
; if (auto *Preheader = ML->getLoopPreheader()) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML)) dbgs() <<
 " - " << Preheader->getName() << "\n"; else if
 (auto *Preheader = MLI->findLoopPreheader(ML, true)) dbgs
() << " - " << Preheader->getName() << "\n"
; for (auto *MBB : ML->getBlocks()) dbgs() << " - " <<
 MBB->getName() << "\n";; } } while (false);

// Search the given block for a loop start instruction. If one isn't found,
// and there's only one predecessor block, search that one too.
std::function<MachineInstr*(MachineBasicBlock*)> SearchForStart =
  [&SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
  for (auto &MI : *MBB) {
    if (isLoopStart(MI))
      return &MI;
  }
  if (MBB->pred_size() == 1)
    return SearchForStart(*MBB->pred_begin());
  return nullptr;
};

LowOverheadLoop LoLoop(*ML, *MLI, *RDA, *TRI);
// Search the preheader for the start intrinsic.
// FIXME: I don't see why we shouldn't be supporting multiple predecessors
// with potentially multiple set.loop.iterations, so we need to enable this.
if (auto *Preheader = ML->getLoopPreheader())
  LoLoop.Start = SearchForStart(Preheader);
else if (auto *Preheader = MLI->findLoopPreheader(ML, true))
  LoLoop.Start = SearchForStart(Preheader);
else
  return false;

// Find the low-overhead loop components and decide whether or not to fall
// back to a normal loop. Also look for a vctp instructions and decide
// whether we can convert that predicate using tail predication.
for (auto *MBB : reverse(ML->getBlocks())) {
  for (auto &MI : *MBB) {
    if (MI.isDebugValue())
      continue;
    else if (MI.getOpcode() == ARM::t2LoopDec)
      LoLoop.Dec = &MI;
    else if (MI.getOpcode() == ARM::t2LoopEnd)
      LoLoop.End = &MI;
    else if (isLoopStart(MI))
      LoLoop.Start = &MI;
    else if (MI.getDesc().isCall()) {
      // TODO: Though the call will require LE to execute again, does this
      // mean we should revert? Always executing LE hopefully should be
      // faster than performing a sub,cmp,br or even subs,br.
      LoLoop.Revert = true;
      LLVM_DEBUG(dbgs() << "ARM Loops: Found call.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Found call.\n"
; } } while (false);
    } else {
      // Record VPR defs and build up their corresponding vpt blocks.
      // Check we know how to tail predicate any mve instructions.
      LoLoop.AnalyseMVEInst(&MI);
    }
  }
}

LLVM_DEBUG(LoLoop.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { LoLoop.dump(); } } while (false
);
if (!LoLoop.FoundAllComponents()) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Didn't find loop start, update, end\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Didn't find loop start, update, end\n"
; } } while (false);
  return false;
}

// Check that the only instruction using LoopDec is LoopEnd.
// TODO: Check for copy chains that really have no effect.
SmallPtrSet<MachineInstr*, 2> Uses;
RDA->getReachingLocalUses(LoLoop.Dec, ARM::LR, Uses);
if (Uses.size() > 1 || !Uses.count(LoLoop.End)) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Unable to remove LoopDec.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unable to remove LoopDec.\n"
; } } while (false);
  LoLoop.Revert = true;
}
LoLoop.CheckLegality(BBUtils.get());
Expand(LoLoop);
return true;
788}

790// WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
791// beq that branches to the exit branch.
792// TODO: We could also try to generate a cbz if the value in LR is also in
793// another low register.
794void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Reverting to cmp: "
 << *MI; } } while (false);
MachineBasicBlock *MBB = MI->getParent();
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                  TII->get(ARM::t2CMPri));
MIB.add(MI->getOperand(0));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::NoRegister);

MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
  ARM::tBcc : ARM::t2Bcc;

MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1));   // branch target
MIB.addImm(ARMCC::EQ);        // condition code
MIB.addReg(ARM::CPSR);
MI->eraseFromParent();
813}

815bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Reverting to sub: "
 << *MI; } } while (false);
MachineBasicBlock *MBB = MI->getParent();
SmallPtrSet<MachineInstr*, 1> Ignore;
for (auto I = MachineBasicBlock::iterator(MI), E = MBB->end(); I != E; ++I) {
  if (I->getOpcode() == ARM::t2LoopEnd) {
    Ignore.insert(&*I);
    break;
  }
}

// If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
bool SetFlags = RDA->isSafeToDefRegAt(MI, ARM::CPSR, Ignore);

MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                  TII->get(ARM::t2SUBri));
MIB.addDef(ARM::LR);
MIB.add(MI->getOperand(1));
MIB.add(MI->getOperand(2));
MIB.addImm(ARMCC::AL);
MIB.addReg(0);

if (SetFlags) {
  MIB.addReg(ARM::CPSR);
  MIB->getOperand(5).setIsDef(true);
} else
  MIB.addReg(0);

MI->eraseFromParent();
return SetFlags;
845}

847// Generate a subs, or sub and cmp, and a branch instead of an LE.
848void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI, bool SkipCmp) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Reverting to cmp, br: "
 << *MI; } } while (false);

MachineBasicBlock *MBB = MI->getParent();
// Create cmp
if (!SkipCmp) {
  MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                    TII->get(ARM::t2CMPri));
  MIB.addReg(ARM::LR);
  MIB.addImm(0);
  MIB.addImm(ARMCC::AL);
  MIB.addReg(ARM::NoRegister);
}

MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
  ARM::tBcc : ARM::t2Bcc;

// Create bne
MachineInstrBuilder MIB =
  BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1));   // branch target
MIB.addImm(ARMCC::NE);        // condition code
MIB.addReg(ARM::CPSR);
MI->eraseFromParent();
873}

875// Perform dead code elimation on the loop iteration count setup expression.
876// If we are tail-predicating, the number of elements to be processed is the
877// operand of the VCTP instruction in the vector body, see getCount(), which is
878// register $r3 in this example:
879//
880//   $lr = big-itercount-expression
881//   ..
882//   t2DoLoopStart renamable $lr
883//   vector.body:
884//     ..
885//     $vpr = MVE_VCTP32 renamable $r3
886//     renamable $lr = t2LoopDec killed renamable $lr, 1
887//     t2LoopEnd renamable $lr, %vector.body
888//     tB %end
889//
890// What we would like achieve here is to replace the do-loop start pseudo
891// instruction t2DoLoopStart with:
892//
893//    $lr = MVE_DLSTP_32 killed renamable $r3
894//
895// Thus, $r3 which defines the number of elements, is written to $lr,
896// and then we want to delete the whole chain that used to define $lr,
897// see the comment below how this chain could look like.
898//
899void ARMLowOverheadLoops::IterationCountDCE(LowOverheadLoop &LoLoop) {
if (!LoLoop.IsTailPredicationLegal())
  return;

LLVM_DEBUG(dbgs() << "ARM Loops: Trying DCE on loop iteration count.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Trying DCE on loop iteration count.\n"
; } } while (false);

MachineInstr *Def = RDA->getMIOperand(LoLoop.Start, 0);
if (!Def) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Couldn't find iteration count.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Couldn't find iteration count.\n"
; } } while (false);
  return;
}

// Collect and remove the users of iteration count.
SmallPtrSet<MachineInstr*, 4> Killed  = { LoLoop.Start, LoLoop.Dec,
                                          LoLoop.End, LoLoop.InsertPt };
SmallPtrSet<MachineInstr*, 2> Remove;
if (RDA->isSafeToRemove(Def, Remove, Killed))
  LoLoop.ToRemove.insert(Remove.begin(), Remove.end());
else {
  LLVM_DEBUG(dbgs() << "ARM Loops: Unsafe to remove loop iteration count.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Unsafe to remove loop iteration count.\n"
; } } while (false);
  return;
}

// Collect the dead code and the MBBs in which they reside.
RDA->collectKilledOperands(Def, Killed);
SmallPtrSet<MachineBasicBlock*, 2> BasicBlocks;
for (auto *MI : Killed)
  BasicBlocks.insert(MI->getParent());

// Collect IT blocks in all affected basic blocks.
std::map<MachineInstr *, SmallPtrSet<MachineInstr *, 2>> ITBlocks;
for (auto *MBB : BasicBlocks) {
  for (auto &MI : *MBB) {
    if (MI.getOpcode() != ARM::t2IT)
      continue;
    RDA->getReachingLocalUses(&MI, ARM::ITSTATE, ITBlocks[&MI]);
  }
}

// If we're removing all of the instructions within an IT block, then
// also remove the IT instruction.
SmallPtrSet<MachineInstr*, 2> ModifiedITs;
for (auto *MI : Killed) {
  if (MachineOperand *MO = MI->findRegisterUseOperand(ARM::ITSTATE)) {
    MachineInstr *IT = RDA->getMIOperand(MI, *MO);
    auto &CurrentBlock = ITBlocks[IT];
    CurrentBlock.erase(MI);
    if (CurrentBlock.empty())
      ModifiedITs.erase(IT);
    else
      ModifiedITs.insert(IT);
  }
}

// Delete the killed instructions only if we don't have any IT blocks that
// need to be modified because we need to fixup the mask.
// TODO: Handle cases where IT blocks are modified.
if (ModifiedITs.empty()) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Will remove iteration count:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove iteration count:\n"
; for (auto *MI : Killed) dbgs() << " - " << *MI;
 } } while (false)
             for (auto *MI : Killed)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove iteration count:\n"
; for (auto *MI : Killed) dbgs() << " - " << *MI;
 } } while (false)
               dbgs() << " - " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Will remove iteration count:\n"
; for (auto *MI : Killed) dbgs() << " - " << *MI;
 } } while (false);
  LoLoop.ToRemove.insert(Killed.begin(), Killed.end());
} else
  LLVM_DEBUG(dbgs() << "ARM Loops: Would need to modify IT block(s).\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Would need to modify IT block(s).\n"
; } } while (false);
963}

965MachineInstr* ARMLowOverheadLoops::ExpandLoopStart(LowOverheadLoop &LoLoop) {
LLVM_DEBUG(dbgs() << "ARM Loops: Expanding LoopStart.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Expanding LoopStart.\n"
; } } while (false);
// When using tail-predication, try to delete the dead code that was used to
// calculate the number of loop iterations.
IterationCountDCE(LoLoop);

MachineInstr *InsertPt = LoLoop.InsertPt;
MachineInstr *Start = LoLoop.Start;
MachineBasicBlock *MBB = InsertPt->getParent();
bool IsDo = Start->getOpcode() == ARM::t2DoLoopStart;
unsigned Opc = LoLoop.getStartOpcode();
MachineOperand &Count = LoLoop.getCount();

MachineInstrBuilder MIB =
  BuildMI(*MBB, InsertPt, InsertPt->getDebugLoc(), TII->get(Opc));

MIB.addDef(ARM::LR);
MIB.add(Count);
if (!IsDo)
  MIB.add(Start->getOperand(1));

// If we're inserting at a mov lr, then remove it as it's redundant.
if (InsertPt != Start)
  LoLoop.ToRemove.insert(InsertPt);
LoLoop.ToRemove.insert(Start);
LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Inserted start: "
 << *MIB; } } while (false);
return &*MIB;
992}

994void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
auto RemovePredicate = [](MachineInstr *MI) {
  LLVM_DEBUG(dbgs() << "ARM Loops: Removing predicate from: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Removing predicate from: "
 << *MI; } } while (false);
  if (int PIdx = llvm::findFirstVPTPredOperandIdx(*MI)) {
    assert(MI->getOperand(PIdx).getImm() == ARMVCC::Then &&((MI->getOperand(PIdx).getImm() == ARMVCC::Then &&
 "Expected Then predicate!") ? static_cast<void> (0) : __assert_fail
 ("MI->getOperand(PIdx).getImm() == ARMVCC::Then && \"Expected Then predicate!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 999, __PRETTY_FUNCTION__))
           "Expected Then predicate!")((MI->getOperand(PIdx).getImm() == ARMVCC::Then &&
 "Expected Then predicate!") ? static_cast<void> (0) : __assert_fail
 ("MI->getOperand(PIdx).getImm() == ARMVCC::Then && \"Expected Then predicate!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 999, __PRETTY_FUNCTION__));
    MI->getOperand(PIdx).setImm(ARMVCC::None);
    MI->getOperand(PIdx+1).setReg(0);
  } else
    llvm_unreachable("trying to unpredicate a non-predicated instruction")::llvm::llvm_unreachable_internal("trying to unpredicate a non-predicated instruction"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp"
, 1003);
};

// There are a few scenarios which we have to fix up:
// 1) A VPT block with is only predicated by the vctp and has no internal vpr
//    defs.
// 2) A VPT block which is only predicated by the vctp but has an internal
//    vpr def.
// 3) A VPT block which is predicated upon the vctp as well as another vpr
//    def.
// 4) A VPT block which is not predicated upon a vctp, but contains it and
//    all instructions within the block are predicated upon in.

for (auto &Block : LoLoop.getVPTBlocks()) {
1
Assuming '__begin1' is not equal to '__end1'→
  SmallVectorImpl<PredicatedMI> &Insts = Block.getInsts();
  if (Block.HasNonUniformPredicate()) {
2
←
Calling 'VPTBlock::HasNonUniformPredicate'→
5
←
Returning from 'VPTBlock::HasNonUniformPredicate'→
6
←
Taking true branch→
    PredicatedMI *Divergent = Block.getDivergent();
    if (isVCTP(Divergent->MI)) {
7
←
Calling 'isVCTP'→
11
←
Returning from 'isVCTP'→
12
←
Taking false branch→
      // The vctp will be removed, so the size of the vpt block needs to be
      // modified.
      uint64_t Size = getARMVPTBlockMask(Block.size() - 1);
      Block.getVPST()->getOperand(0).setImm(Size);
      LLVM_DEBUG(dbgs() << "ARM Loops: Modified VPT block mask.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Modified VPT block mask.\n"
; } } while (false);
    } else if (Block.IsOnlyPredicatedOn(LoLoop.VCTP)) {
13
←
Calling 'VPTBlock::IsOnlyPredicatedOn'→
17
←
Returning from 'VPTBlock::IsOnlyPredicatedOn'→
18
←
Taking true branch→
      // The VPT block has a non-uniform predicate but it's entry is guarded
      // only by a vctp, which means we:
      // - Need to remove the original vpst.
      // - Then need to unpredicate any following instructions, until
      //   we come across the divergent vpr def.
      // - Insert a new vpst to predicate the instruction(s) that following
      //   the divergent vpr def.
      // TODO: We could be producing more VPT blocks than necessary and could
      // fold the newly created one into a proceeding one.
      for (auto I = ++MachineBasicBlock::iterator(Block.getVPST()),
19
←
Loop condition is false. Execution continues on line 1040→
           E = ++MachineBasicBlock::iterator(Divergent->MI); I != E; ++I)
        RemovePredicate(&*I);

      unsigned Size = 0;
      auto E = MachineBasicBlock::reverse_iterator(Divergent->MI);
      auto I = MachineBasicBlock::reverse_iterator(Insts.back().MI);
      MachineInstr *InsertAt = nullptr;
20
←
'InsertAt' initialized to a null pointer value→
      while (I != E) {
21
←
Loop condition is false. Execution continues on line 1049→
        InsertAt = &*I;
        ++Size;
        ++I;
      }
      MachineInstrBuilder MIB = BuildMI(*InsertAt->getParent(), InsertAt,
22
←
Called C++ object pointer is null
                                        InsertAt->getDebugLoc(),
                                        TII->get(ARM::MVE_VPST));
      MIB.addImm(getARMVPTBlockMask(Size));
      LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *Block.getVPST())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Removing VPST: "
 << *Block.getVPST(); } } while (false);
      LLVM_DEBUG(dbgs() << "ARM Loops: Created VPST: " << *MIB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Created VPST: "
 << *MIB; } } while (false);
      LoLoop.ToRemove.insert(Block.getVPST());
    }
  } else if (Block.IsOnlyPredicatedOn(LoLoop.VCTP)) {
    // A vpt block which is only predicated upon vctp and has no internal vpr
    // defs:
    // - Remove vpst.
    // - Unpredicate the remaining instructions.
    LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *Block.getVPST())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Removing VPST: "
 << *Block.getVPST(); } } while (false);
    LoLoop.ToRemove.insert(Block.getVPST());
    for (auto &PredMI : Insts)
      RemovePredicate(PredMI.MI);
  }
}
LLVM_DEBUG(dbgs() << "ARM Loops: Removing VCTP: " << *LoLoop.VCTP)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Removing VCTP: "
 << *LoLoop.VCTP; } } while (false);
LoLoop.ToRemove.insert(LoLoop.VCTP);
1070}

1072void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) {

// Combine the LoopDec and LoopEnd instructions into LE(TP).
auto ExpandLoopEnd = [this](LowOverheadLoop &LoLoop) {
  MachineInstr *End = LoLoop.End;
  MachineBasicBlock *MBB = End->getParent();
  unsigned Opc = LoLoop.IsTailPredicationLegal() ?
    ARM::MVE_LETP : ARM::t2LEUpdate;
  MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
                                    TII->get(Opc));
  MIB.addDef(ARM::LR);
  MIB.add(End->getOperand(0));
  MIB.add(End->getOperand(1));
  LLVM_DEBUG(dbgs() << "ARM Loops: Inserted LE: " << *MIB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Inserted LE: "
 << *MIB; } } while (false);
  LoLoop.ToRemove.insert(LoLoop.Dec);
  LoLoop.ToRemove.insert(End);
  return &*MIB;
};

// TODO: We should be able to automatically remove these branches before we
// get here - probably by teaching analyzeBranch about the pseudo
// instructions.
// If there is an unconditional branch, after I, that just branches to the
// next block, remove it.
auto RemoveDeadBranch = [](MachineInstr *I) {
  MachineBasicBlock *BB = I->getParent();
  MachineInstr *Terminator = &BB->instr_back();
  if (Terminator->isUnconditionalBranch() && I != Terminator) {
    MachineBasicBlock *Succ = Terminator->getOperand(0).getMBB();
    if (BB->isLayoutSuccessor(Succ)) {
      LLVM_DEBUG(dbgs() << "ARM Loops: Removing branch: " << *Terminator)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Removing branch: "
 << *Terminator; } } while (false);
      Terminator->eraseFromParent();
    }
  }
};

if (LoLoop.Revert) {
  if (LoLoop.Start->getOpcode() == ARM::t2WhileLoopStart)
    RevertWhile(LoLoop.Start);
  else
    LoLoop.Start->eraseFromParent();
  bool FlagsAlreadySet = RevertLoopDec(LoLoop.Dec);
  RevertLoopEnd(LoLoop.End, FlagsAlreadySet);
} else {
  LoLoop.Start = ExpandLoopStart(LoLoop);
  RemoveDeadBranch(LoLoop.Start);
  LoLoop.End = ExpandLoopEnd(LoLoop);
  RemoveDeadBranch(LoLoop.End);
  if (LoLoop.IsTailPredicationLegal())
    ConvertVPTBlocks(LoLoop);
  for (auto *I : LoLoop.ToRemove) {
    LLVM_DEBUG(dbgs() << "ARM Loops: Erasing " << *I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Erasing "
 << *I; } } while (false);
    I->eraseFromParent();
  }
}

PostOrderLoopTraversal DFS(LoLoop.ML, *MLI);
DFS.ProcessLoop();
const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder();
for (auto *MBB : PostOrder) {
  recomputeLiveIns(*MBB);
  // FIXME: For some reason, the live-in print order is non-deterministic for
  // our tests and I can't out why... So just sort them.
  MBB->sortUniqueLiveIns();
}

for (auto *MBB : reverse(PostOrder))
  recomputeLivenessFlags(*MBB);

// We've moved, removed and inserted new instructions, so update RDA.
RDA->reset();
1143}

1145bool ARMLowOverheadLoops::RevertNonLoops() {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("arm-low-overhead-loops")) { dbgs() << "ARM Loops: Reverting any remaining pseudos...\n"
; } } while (false);
bool Changed = false;

for (auto &MBB : *MF) {
  SmallVector<MachineInstr*, 4> Starts;
  SmallVector<MachineInstr*, 4> Decs;
  SmallVector<MachineInstr*, 4> Ends;

  for (auto &I : MBB) {
    if (isLoopStart(I))
      Starts.push_back(&I);
    else if (I.getOpcode() == ARM::t2LoopDec)
      Decs.push_back(&I);
    else if (I.getOpcode() == ARM::t2LoopEnd)
      Ends.push_back(&I);
  }

  if (Starts.empty() && Decs.empty() && Ends.empty())
    continue;

  Changed = true;

  for (auto *Start : Starts) {
    if (Start->getOpcode() == ARM::t2WhileLoopStart)
      RevertWhile(Start);
    else
      Start->eraseFromParent();
  }
  for (auto *Dec : Decs)
    RevertLoopDec(Dec);

  for (auto *End : Ends)
    RevertLoopEnd(End);
}
return Changed;
1181}

1183FunctionPass *llvm::createARMLowOverheadLoopsPass() {
return new ARMLowOverheadLoops();
1185}

←

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMBaseInstrInfo.h

1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//

13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H

16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineOperand.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include <array>
25#include <cstdint>

27#define GET_INSTRINFO_HEADER
28#include "ARMGenInstrInfo.inc"

30namespace llvm {

32class ARMBaseRegisterInfo;
33class ARMSubtarget;

35class ARMBaseInstrInfo : public ARMGenInstrInfo {
const ARMSubtarget &Subtarget;

38protected:
// Can be only subclassed.
explicit ARMBaseInstrInfo(const ARMSubtarget &STI);

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
                              unsigned LoadImmOpc, unsigned LoadOpc) const;

/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
/// and \p DefIdx.
/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
/// the list is modeled as <Reg:SubReg, SubIdx>.
/// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
/// two elements:
/// - %1:sub1, sub0
/// - %2<:0>, sub1
///
/// \returns true if it is possible to build such an input sequence
/// with the pair \p MI, \p DefIdx. False otherwise.
///
/// \pre MI.isRegSequenceLike().
bool getRegSequenceLikeInputs(
    const MachineInstr &MI, unsigned DefIdx,
    SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;

/// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
/// and \p DefIdx.
/// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
/// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
/// - %1:sub1, sub0
///
/// \returns true if it is possible to build such an input sequence
/// with the pair \p MI, \p DefIdx. False otherwise.
///
/// \pre MI.isExtractSubregLike().
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
                                RegSubRegPairAndIdx &InputReg) const override;

/// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
/// and \p DefIdx.
/// \p [out] BaseReg and \p [out] InsertedReg contain
/// the equivalent inputs of INSERT_SUBREG.
/// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
/// - BaseReg: %0:sub0
/// - InsertedReg: %1:sub1, sub3
///
/// \returns true if it is possible to build such an input sequence
/// with the pair \p MI, \p DefIdx. False otherwise.
///
/// \pre MI.isInsertSubregLike().
bool
getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
                          RegSubRegPair &BaseReg,
                          RegSubRegPairAndIdx &InsertedReg) const override;

/// Commutes the operands in the given instruction.
/// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
///
/// Do not call this method for a non-commutable instruction or for
/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
/// Even though the instruction is commutable, the method may still
/// fail to commute the operands, null pointer is returned in such cases.
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                     unsigned OpIdx1,
                                     unsigned OpIdx2) const override;
/// If the specific machine instruction is an instruction that moves/copies
/// value from one register to another register return destination and source
/// registers as machine operands.
Optional<DestSourcePair>
isCopyInstrImpl(const MachineInstr &MI) const override;

/// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
/// enhance debug entry value descriptions for ARM targets.
Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                               Register Reg) const override;

113public:
// Return whether the target has an explicit NOP encoding.
bool hasNOP() const;

// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;

MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
                                    MachineInstr &MI,
                                    LiveVariables *LV) const override;

virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
const ARMSubtarget &getSubtarget() const { return Subtarget; }

ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
                             const ScheduleDAG *DAG) const override;

ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
                                   const ScheduleDAG *DAG) const override;

// Branch analysis.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                   MachineBasicBlock *&FBB,
                   SmallVectorImpl<MachineOperand> &Cond,
                   bool AllowModify = false) const override;
unsigned removeBranch(MachineBasicBlock &MBB,
                      int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                      MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                      const DebugLoc &DL,
                      int *BytesAdded = nullptr) const override;

bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;

// Predication support.
bool isPredicated(const MachineInstr &MI) const override;

// MIR printer helper function to annotate Operands with a comment.
std::string createMIROperandComment(const MachineInstr &MI,
                                    const MachineOperand &Op,
                                    unsigned OpIdx) const override;

ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
  int PIdx = MI.findFirstPredOperandIdx();
  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
                    : ARMCC::AL;
}

bool PredicateInstruction(MachineInstr &MI,
                          ArrayRef<MachineOperand> Pred) const override;

bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
                       ArrayRef<MachineOperand> Pred2) const override;

bool DefinesPredicate(MachineInstr &MI,
                      std::vector<MachineOperand> &Pred) const override;

bool isPredicable(const MachineInstr &MI) const override;

// CPSR defined in instruction
static bool isCPSRDefined(const MachineInstr &MI);
bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;

// Load, scaled register offset
bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
// Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Minus reg for ldstso addr mode
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
// Scaled register offset in address mode 2
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
// Load multiple, base reg in list
bool isLDMBaseRegInList(const MachineInstr &MI) const;
// get LDM variable defs size
unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;

/// GetInstSize - Returns the size of the specified MachineInstr.
///
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

unsigned isLoadFromStackSlot(const MachineInstr &MI,
                             int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
                            int &FrameIndex) const override;
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
                                   int &FrameIndex) const override;
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
                                  int &FrameIndex) const override;

void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                unsigned SrcReg, bool KillSrc,
                const ARMSubtarget &Subtarget) const;
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                  unsigned DestReg, bool KillSrc,
                  const ARMSubtarget &Subtarget) const;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
                 bool KillSrc) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator MBBI,
                         Register SrcReg, bool isKill, int FrameIndex,
                         const TargetRegisterClass *RC,
                         const TargetRegisterInfo *TRI) const override;

void loadRegFromStackSlot(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI,
                          Register DestReg, int FrameIndex,
                          const TargetRegisterClass *RC,
                          const TargetRegisterInfo *TRI) const override;

bool expandPostRAPseudo(MachineInstr &MI) const override;

bool shouldSink(const MachineInstr &MI) const override;

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                   unsigned DestReg, unsigned SubIdx,
                   const MachineInstr &Orig,
                   const TargetRegisterInfo &TRI) const override;

MachineInstr &
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
          const MachineInstr &Orig) const override;

const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
                                   unsigned SubIdx, unsigned State,
                                   const TargetRegisterInfo *TRI) const;

bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
                      const MachineRegisterInfo *MRI) const override;

/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
/// determine if two loads are loading from the same base address. It should
/// only return true if the base pointers are the same and the only
/// differences between the two addresses is the offset. It also returns the
/// offsets by reference.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
                             int64_t &Offset2) const override;

/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
/// should be scheduled togther. On some targets if two loads are loading from
/// addresses in the same cache line, it's better if they are scheduled
/// together. This function takes two integers that represent the load offsets
/// from the common base address. It returns true if it decides it's desirable
/// to schedule the two loads together. "NumLoads" is the number of loads that
/// have already been scheduled after Load1.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
                             int64_t Offset1, int64_t Offset2,
                             unsigned NumLoads) const override;

bool isSchedulingBoundary(const MachineInstr &MI,
                          const MachineBasicBlock *MBB,
                          const MachineFunction &MF) const override;

bool isProfitableToIfCvt(MachineBasicBlock &MBB,
                         unsigned NumCycles, unsigned ExtraPredCycles,
                         BranchProbability Probability) const override;

bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
                         unsigned ExtraT, MachineBasicBlock &FMBB,
                         unsigned NumF, unsigned ExtraF,
                         BranchProbability Probability) const override;

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
                               BranchProbability Probability) const override {
  return NumCycles == 1;
}

unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
                                          unsigned NumInsts) const override;
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;

bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
                               MachineBasicBlock &FMBB) const override;

/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2 if having two register operands, and the value it
/// compares against in CmpValue. Return true if the comparison instruction
/// can be analyzed.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                    unsigned &SrcReg2, int &CmpMask,
                    int &CmpValue) const override;

/// optimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero"; Remove a redundant CMP
/// instruction if the flags can be updated in the same way by an earlier
/// instruction such as SUB.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
                          unsigned SrcReg2, int CmpMask, int CmpValue,
                          const MachineRegisterInfo *MRI) const override;

bool analyzeSelect(const MachineInstr &MI,
                   SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
                   unsigned &FalseOp, bool &Optimizable) const override;

MachineInstr *optimizeSelect(MachineInstr &MI,
                             SmallPtrSetImpl<MachineInstr *> &SeenMIs,
                             bool) const override;

/// FoldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
                   MachineRegisterInfo *MRI) const override;

unsigned getNumMicroOps(const InstrItineraryData *ItinData,
                        const MachineInstr &MI) const override;

int getOperandLatency(const InstrItineraryData *ItinData,
                      const MachineInstr &DefMI, unsigned DefIdx,
                      const MachineInstr &UseMI,
                      unsigned UseIdx) const override;
int getOperandLatency(const InstrItineraryData *ItinData,
                      SDNode *DefNode, unsigned DefIdx,
                      SDNode *UseNode, unsigned UseIdx) const override;

/// VFP/NEON execution domains.
std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr &MI) const override;
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;

unsigned
getPartialRegUpdateClearance(const MachineInstr &, unsigned,
                             const TargetRegisterInfo *) const override;
void breakPartialRegDependency(MachineInstr &, unsigned,
                               const TargetRegisterInfo *TRI) const override;

/// Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned getNumLDMAddresses(const MachineInstr &MI) const;

std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const override;
ArrayRef<std::pair<unsigned, const char *>>
getSerializableBitmaskMachineOperandTargetFlags() const override;

356private:
unsigned getInstBundleLength(const MachineInstr &MI) const;

int getVLDMDefCycle(const InstrItineraryData *ItinData,
                    const MCInstrDesc &DefMCID,
                    unsigned DefClass,
                    unsigned DefIdx, unsigned DefAlign) const;
int getLDMDefCycle(const InstrItineraryData *ItinData,
                   const MCInstrDesc &DefMCID,
                   unsigned DefClass,
                   unsigned DefIdx, unsigned DefAlign) const;
int getVSTMUseCycle(const InstrItineraryData *ItinData,
                    const MCInstrDesc &UseMCID,
                    unsigned UseClass,
                    unsigned UseIdx, unsigned UseAlign) const;
int getSTMUseCycle(const InstrItineraryData *ItinData,
                   const MCInstrDesc &UseMCID,
                   unsigned UseClass,
                   unsigned UseIdx, unsigned UseAlign) const;
int getOperandLatency(const InstrItineraryData *ItinData,
                      const MCInstrDesc &DefMCID,
                      unsigned DefIdx, unsigned DefAlign,
                      const MCInstrDesc &UseMCID,
                      unsigned UseIdx, unsigned UseAlign) const;

int getOperandLatencyImpl(const InstrItineraryData *ItinData,
                          const MachineInstr &DefMI, unsigned DefIdx,
                          const MCInstrDesc &DefMCID, unsigned DefAdj,
                          const MachineOperand &DefMO, unsigned Reg,
                          const MachineInstr &UseMI, unsigned UseIdx,
                          const MCInstrDesc &UseMCID, unsigned UseAdj) const;

unsigned getPredicationCost(const MachineInstr &MI) const override;

unsigned getInstrLatency(const InstrItineraryData *ItinData,
                         const MachineInstr &MI,
                         unsigned *PredCost = nullptr) const override;

int getInstrLatency(const InstrItineraryData *ItinData,
                    SDNode *Node) const override;

bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
                           const MachineRegisterInfo *MRI,
                           const MachineInstr &DefMI, unsigned DefIdx,
                           const MachineInstr &UseMI,
                           unsigned UseIdx) const override;
bool hasLowDefLatency(const TargetSchedModel &SchedModel,
                      const MachineInstr &DefMI,
                      unsigned DefIdx) const override;

/// verifyInstruction - Perform target specific instruction verification.
bool verifyInstruction(const MachineInstr &MI,
                       StringRef &ErrInfo) const override;

virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;

void expandMEMCPY(MachineBasicBlock::iterator) const;

/// Identify instructions that can be folded into a MOVCC instruction, and
/// return the defining instruction.
MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
                               const TargetInstrInfo *TII) const;

419private:
/// Modeling special VFP / NEON fp MLA / MLS hazards.

/// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
/// MLx table.
DenseMap<unsigned, unsigned> MLxEntryMap;

/// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
/// stalls when scheduled together with fp MLA / MLS opcodes.
SmallSet<unsigned, 16> MLxHazardOpcodes;

430public:
/// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
/// instruction.
bool isFpMLxInstruction(unsigned Opcode) const {
  return MLxEntryMap.count(Opcode);
}

/// isFpMLxInstruction - This version also returns the multiply opcode and the
/// addition / subtraction opcode to expand to. Return true for 'HasLane' for
/// the MLX instructions with an extra lane operand.
bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
                        unsigned &AddSubOpc, bool &NegAcc,
                        bool &HasLane) const;

/// canCauseFpMLxStall - Return true if an instruction of the specified opcode
/// will cause stalls when scheduled after (within 4-cycle window) a fp
/// MLA / MLS instruction.
bool canCauseFpMLxStall(unsigned Opcode) const {
  return MLxHazardOpcodes.count(Opcode);
}

/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.
bool isSwiftFastImmShift(const MachineInstr *MI) const;

/// Returns predicate register associated with the given frame instruction.
unsigned getFramePred(const MachineInstr &MI) const {
  assert(isFrameInstr(MI))((isFrameInstr(MI)) ? static_cast<void> (0) : __assert_fail
 ("isFrameInstr(MI)", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMBaseInstrInfo.h"
, 457, __PRETTY_FUNCTION__));
  // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
  // - argument declared in the pattern:
  // 0 - frame size
  // 1 - arg of CALLSEQ_START/CALLSEQ_END
  // 2 - predicate code (like ARMCC::AL)
  // - added by predOps:
  // 3 - predicate reg
  return MI.getOperand(3).getReg();
}

Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                    Register Reg) const override;
470};

472/// Get the operands corresponding to the given \p Pred value. By default, the
473/// predicate register is assumed to be 0 (no register), but you can pass in a
474/// \p PredReg if that is not the case.
475static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
                                                  unsigned PredReg = 0) {
return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
         MachineOperand::CreateReg(PredReg, false)}};
479}

481/// Get the operand corresponding to the conditional code result. By default,
482/// this is 0 (no register).
483static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
return MachineOperand::CreateReg(CCReg, false);
485}

487/// Get the operand corresponding to the conditional code result for Thumb1.
488/// This operand will always refer to CPSR and it will have the Define flag set.
489/// You can optionally set the Dead flag by means of \p isDead.
490static inline MachineOperand t1CondCodeOp(bool isDead = false) {
return MachineOperand::CreateReg(ARM::CPSR,
                                 /*Define*/ true, /*Implicit*/ false,
                                 /*Kill*/ false, isDead);
494}

496static inline
497bool isUncondBranchOpcode(int Opc) {
return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
499}

501// This table shows the VPT instruction variants, i.e. the different
502// mask field encodings, see also B5.6. Predication/conditional execution in
503// the ArmARM.


506inline static unsigned getARMVPTBlockMask(unsigned NumInsts) {
switch (NumInsts) {
case 1:
  return ARMVCC::T;
case 2:
  return ARMVCC::TT;
case 3:
  return ARMVCC::TTT;
case 4:
  return ARMVCC::TTTT;
default:
  break;
};
llvm_unreachable("Unexpected number of instruction in a VPT block")::llvm::llvm_unreachable_internal("Unexpected number of instruction in a VPT block"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMBaseInstrInfo.h"
, 519);
520}


523static inline bool isVPTOpcode(int Opc) {
return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
       Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
       Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
       Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
       Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
       Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
       Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
       Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
       Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
       Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
       Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
       Opc == ARM::MVE_VPST;
536}

538static inline
539unsigned VCMPOpcodeToVPT(unsigned Opcode) {
switch (Opcode) {
default:
  return 0;
case ARM::MVE_VCMPf32:
  return ARM::MVE_VPTv4f32;
case ARM::MVE_VCMPf16:
  return ARM::MVE_VPTv8f16;
case ARM::MVE_VCMPi8:
  return ARM::MVE_VPTv16i8;
case ARM::MVE_VCMPi16:
  return ARM::MVE_VPTv8i16;
case ARM::MVE_VCMPi32:
  return ARM::MVE_VPTv4i32;
case ARM::MVE_VCMPu8:
  return ARM::MVE_VPTv16u8;
case ARM::MVE_VCMPu16:
  return ARM::MVE_VPTv8u16;
case ARM::MVE_VCMPu32:
  return ARM::MVE_VPTv4u32;
case ARM::MVE_VCMPs8:
  return ARM::MVE_VPTv16s8;
case ARM::MVE_VCMPs16:
  return ARM::MVE_VPTv8s16;
case ARM::MVE_VCMPs32:
  return ARM::MVE_VPTv4s32;

case ARM::MVE_VCMPf32r:
  return ARM::MVE_VPTv4f32r;
case ARM::MVE_VCMPf16r:
  return ARM::MVE_VPTv8f16r;
case ARM::MVE_VCMPi8r:
  return ARM::MVE_VPTv16i8r;
case ARM::MVE_VCMPi16r:
  return ARM::MVE_VPTv8i16r;
case ARM::MVE_VCMPi32r:
  return ARM::MVE_VPTv4i32r;
case ARM::MVE_VCMPu8r:
  return ARM::MVE_VPTv16u8r;
case ARM::MVE_VCMPu16r:
  return ARM::MVE_VPTv8u16r;
case ARM::MVE_VCMPu32r:
  return ARM::MVE_VPTv4u32r;
case ARM::MVE_VCMPs8r:
  return ARM::MVE_VPTv16s8r;
case ARM::MVE_VCMPs16r:
  return ARM::MVE_VPTv8s16r;
case ARM::MVE_VCMPs32r:
  return ARM::MVE_VPTv4s32r;
}
589}

591static inline
592unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop) {
switch (Opcode) {
default:
  llvm_unreachable("unhandled vctp opcode")::llvm::llvm_unreachable_internal("unhandled vctp opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMBaseInstrInfo.h"
, 595);
  break;
case ARM::MVE_VCTP8:
  return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
case ARM::MVE_VCTP16:
  return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
case ARM::MVE_VCTP32:
  return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
case ARM::MVE_VCTP64:
  return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;
}
return 0;
607}

609static inline unsigned getTailPredVectorWidth(unsigned Opcode) {
switch (Opcode) {
default:
  llvm_unreachable("unhandled vctp opcode")::llvm::llvm_unreachable_internal("unhandled vctp opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/ARM/ARMBaseInstrInfo.h"
, 612);
case ARM::MVE_VCTP8:  return 16;
case ARM::MVE_VCTP16: return 8;
case ARM::MVE_VCTP32: return 4;
case ARM::MVE_VCTP64: return 2;
}
return 0;
619}

621static inline
622bool isVCTP(MachineInstr *MI) {
switch (MI->getOpcode()) {
8
←
Control jumps to the 'default' case at line 624→
default:
  break;
9
←
 Execution continues on line 632→
case ARM::MVE_VCTP8:
case ARM::MVE_VCTP16:
case ARM::MVE_VCTP32:
case ARM::MVE_VCTP64:
  return true;
}
return false;
10
←
Returning zero, which participates in a condition later→
633}

635static inline
636bool isLoopStart(MachineInstr &MI) {
return MI.getOpcode() == ARM::t2DoLoopStart ||
       MI.getOpcode() == ARM::t2WhileLoopStart;
639}

641static inline
642bool isCondBranchOpcode(int Opc) {
return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
644}

646static inline bool isJumpTableBranchOpcode(int Opc) {
return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
       Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
       Opc == ARM::t2BR_JT;
650}

652static inline
653bool isIndirectBranchOpcode(int Opc) {
return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
655}

657static inline bool isPopOpcode(int Opc) {
return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
       Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
       Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
661}

663static inline bool isPushOpcode(int Opc) {
return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
       Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
666}

668static inline bool isSubImmOpcode(int Opc) {
return Opc == ARM::SUBri ||
       Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
       Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
       Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
673}

675static inline bool isMovRegOpcode(int Opc) {
return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
677}

679/// isValidCoprocessorNumber - decide whether an explicit coprocessor
680/// number is legal in generic instructions like CDP. The answer can
681/// vary with the subtarget.
682static inline bool isValidCoprocessorNumber(unsigned Num,
                                          const FeatureBitset& featureBits) {
// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
  return false;

// Armv7 disallows 101x (CP10 and CP11), which clash with VFP/NEON.
if (featureBits[ARM::HasV7Ops] && (Num & 0xE) == 0xA)
  return false;

// Armv8.1-M also disallows 100x (CP8,CP9) and 111x (CP14,CP15)
// which clash with MVE.
if (featureBits[ARM::HasV8_1MMainlineOps] &&
    ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
  return false;

return true;
699}

701/// getInstrPredicate - If instruction is predicated, returns its predicate
702/// condition, otherwise returns AL. It also returns the condition code
703/// register by reference.
704ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);

706unsigned getMatchingCondBranchOpcode(unsigned Opc);

708/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
709/// the instruction is encoded with an 'S' bit is determined by the optional
710/// CPSR def operand.
711unsigned convertAddSubFlagsOpcode(unsigned OldOpc);

713/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
714/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
715/// code.
716void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator &MBBI,
                           const DebugLoc &dl, unsigned DestReg,
                           unsigned BaseReg, int NumBytes,
                           ARMCC::CondCodes Pred, unsigned PredReg,
                           const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);

723void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator &MBBI,
                          const DebugLoc &dl, unsigned DestReg,
                          unsigned BaseReg, int NumBytes,
                          ARMCC::CondCodes Pred, unsigned PredReg,
                          const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
729void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator &MBBI,
                             const DebugLoc &dl, unsigned DestReg,
                             unsigned BaseReg, int NumBytes,
                             const TargetInstrInfo &TII,
                             const ARMBaseRegisterInfo &MRI,
                             unsigned MIFlags = 0);

737/// Tries to add registers to the reglist of a given base-updating
738/// push/pop instruction to adjust the stack by an additional
739/// NumBytes. This can save a few bytes per function in code-size, but
740/// obviously generates more memory traffic. As such, it only takes
741/// effect in functions being optimised for size.
742bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
                              MachineFunction &MF, MachineInstr *MI,
                              unsigned NumBytes);

746/// rewriteARMFrameIndex / rewriteT2FrameIndex -
747/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
748/// offset could not be handled directly in MI, and return the left-over
749/// portion by reference.
750bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
                        unsigned FrameReg, int &Offset,
                        const ARMBaseInstrInfo &TII);

754bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
                       unsigned FrameReg, int &Offset,
                       const ARMBaseInstrInfo &TII,
                       const TargetRegisterInfo *TRI);

759/// Return true if Reg is defd between From and To
760bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
                          MachineBasicBlock::iterator To,
                          const TargetRegisterInfo *TRI);

764/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
765/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
766MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
                                 const TargetRegisterInfo *TRI);

769void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
770void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg);

772void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
773void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
                            unsigned Inactive);

776/// Returns the number of instructions required to materialize the given
777/// constant in a register, or 3 if a literal pool load is needed.
778/// If ForCodesize is specified, an approximate cost in bytes is returned.
779unsigned ConstantMaterializationCost(unsigned Val,
                                   const ARMSubtarget *Subtarget,
                                   bool ForCodesize = false);

783/// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
784/// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
785/// specified. If the scores are equal, return the comparison for !ForCodesize.
786bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
                                       const ARMSubtarget *Subtarget,
                                       bool ForCodesize = false);

790} // end namespace llvm

792#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H