Bug Summary

File:llvm/lib/Target/AVR/AVRISelLowering.cpp
Warning:line 1035, column 7
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AVR -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp
1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/CodeGen/CallingConvLower.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23#include "llvm/IR/Function.h"
24#include "llvm/Support/ErrorHandling.h"
25
26#include "AVR.h"
27#include "AVRMachineFunctionInfo.h"
28#include "AVRSubtarget.h"
29#include "AVRTargetMachine.h"
30#include "MCTargetDesc/AVRMCTargetDesc.h"
31
32namespace llvm {
33
34AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
35 const AVRSubtarget &STI)
36 : TargetLowering(TM), Subtarget(STI) {
37 // Set up the register classes.
38 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
39 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
40
41 // Compute derived properties from the register classes.
42 computeRegisterProperties(Subtarget.getRegisterInfo());
43
44 setBooleanContents(ZeroOrOneBooleanContent);
45 setBooleanVectorContents(ZeroOrOneBooleanContent);
46 setSchedulingPreference(Sched::RegPressure);
47 setStackPointerRegisterToSaveRestore(AVR::SP);
48 setSupportsUnalignedAtomics(true);
49
50 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
51 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
52
53 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
54 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
55 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
57
58 for (MVT VT : MVT::integer_valuetypes()) {
59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
60 setLoadExtAction(N, VT, MVT::i1, Promote);
61 setLoadExtAction(N, VT, MVT::i8, Expand);
62 }
63 }
64
65 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
66
67 for (MVT VT : MVT::integer_valuetypes()) {
68 setOperationAction(ISD::ADDC, VT, Legal);
69 setOperationAction(ISD::SUBC, VT, Legal);
70 setOperationAction(ISD::ADDE, VT, Legal);
71 setOperationAction(ISD::SUBE, VT, Legal);
72 }
73
74 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
75 // revert into a sub since we don't have an add with immediate instruction.
76 setOperationAction(ISD::ADD, MVT::i32, Custom);
77 setOperationAction(ISD::ADD, MVT::i64, Custom);
78
79 // our shift instructions are only able to shift 1 bit at a time, so handle
80 // this in a custom way.
81 setOperationAction(ISD::SRA, MVT::i8, Custom);
82 setOperationAction(ISD::SHL, MVT::i8, Custom);
83 setOperationAction(ISD::SRL, MVT::i8, Custom);
84 setOperationAction(ISD::SRA, MVT::i16, Custom);
85 setOperationAction(ISD::SHL, MVT::i16, Custom);
86 setOperationAction(ISD::SRL, MVT::i16, Custom);
87 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
88 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
89 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
90
91 setOperationAction(ISD::ROTL, MVT::i8, Custom);
92 setOperationAction(ISD::ROTL, MVT::i16, Expand);
93 setOperationAction(ISD::ROTR, MVT::i8, Custom);
94 setOperationAction(ISD::ROTR, MVT::i16, Expand);
95
96 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
97 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
101
102 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
105 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
106 setOperationAction(ISD::SETCC, MVT::i8, Custom);
107 setOperationAction(ISD::SETCC, MVT::i16, Custom);
108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
109 setOperationAction(ISD::SETCC, MVT::i64, Custom);
110 setOperationAction(ISD::SELECT, MVT::i8, Expand);
111 setOperationAction(ISD::SELECT, MVT::i16, Expand);
112
113 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
114
115 // Add support for postincrement and predecrement load/stores.
116 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
117 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
118 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
120 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
121 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
122 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
124
125 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
126
127 setOperationAction(ISD::VASTART, MVT::Other, Custom);
128 setOperationAction(ISD::VAEND, MVT::Other, Expand);
129 setOperationAction(ISD::VAARG, MVT::Other, Expand);
130 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
131
132 // Atomic operations which must be lowered to rtlib calls
133 for (MVT VT : MVT::integer_valuetypes()) {
134 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
135 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
141 }
142
143 // Division/remainder
144 setOperationAction(ISD::UDIV, MVT::i8, Expand);
145 setOperationAction(ISD::UDIV, MVT::i16, Expand);
146 setOperationAction(ISD::UREM, MVT::i8, Expand);
147 setOperationAction(ISD::UREM, MVT::i16, Expand);
148 setOperationAction(ISD::SDIV, MVT::i8, Expand);
149 setOperationAction(ISD::SDIV, MVT::i16, Expand);
150 setOperationAction(ISD::SREM, MVT::i8, Expand);
151 setOperationAction(ISD::SREM, MVT::i16, Expand);
152
153 // Make division and modulus custom
154 for (MVT VT : MVT::integer_valuetypes()) {
155 setOperationAction(ISD::UDIVREM, VT, Custom);
156 setOperationAction(ISD::SDIVREM, VT, Custom);
157 }
158
159 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
160 setOperationAction(ISD::MUL, MVT::i8, Expand);
161 setOperationAction(ISD::MUL, MVT::i16, Expand);
162
163 // Expand 16 bit multiplications.
164 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
165 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
166
167 // Expand multiplications to libcalls when there is
168 // no hardware MUL.
169 if (!Subtarget.supportsMultiplication()) {
170 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
171 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
172 }
173
174 for (MVT VT : MVT::integer_valuetypes()) {
175 setOperationAction(ISD::MULHS, VT, Expand);
176 setOperationAction(ISD::MULHU, VT, Expand);
177 }
178
179 for (MVT VT : MVT::integer_valuetypes()) {
180 setOperationAction(ISD::CTPOP, VT, Expand);
181 setOperationAction(ISD::CTLZ, VT, Expand);
182 setOperationAction(ISD::CTTZ, VT, Expand);
183 }
184
185 for (MVT VT : MVT::integer_valuetypes()) {
186 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
187 // TODO: The generated code is pretty poor. Investigate using the
188 // same "shift and subtract with carry" trick that we do for
189 // extending 8-bit to 16-bit. This may require infrastructure
190 // improvements in how we treat 16-bit "registers" to be feasible.
191 }
192
193 // Division rtlib functions (not supported)
194 setLibcallName(RTLIB::SDIV_I8, nullptr);
195 setLibcallName(RTLIB::SDIV_I16, nullptr);
196 setLibcallName(RTLIB::SDIV_I32, nullptr);
197 setLibcallName(RTLIB::SDIV_I64, nullptr);
198 setLibcallName(RTLIB::SDIV_I128, nullptr);
199 setLibcallName(RTLIB::UDIV_I8, nullptr);
200 setLibcallName(RTLIB::UDIV_I16, nullptr);
201 setLibcallName(RTLIB::UDIV_I32, nullptr);
202 setLibcallName(RTLIB::UDIV_I64, nullptr);
203 setLibcallName(RTLIB::UDIV_I128, nullptr);
204
205 // Modulus rtlib functions (not supported)
206 setLibcallName(RTLIB::SREM_I8, nullptr);
207 setLibcallName(RTLIB::SREM_I16, nullptr);
208 setLibcallName(RTLIB::SREM_I32, nullptr);
209 setLibcallName(RTLIB::SREM_I64, nullptr);
210 setLibcallName(RTLIB::SREM_I128, nullptr);
211 setLibcallName(RTLIB::UREM_I8, nullptr);
212 setLibcallName(RTLIB::UREM_I16, nullptr);
213 setLibcallName(RTLIB::UREM_I32, nullptr);
214 setLibcallName(RTLIB::UREM_I64, nullptr);
215 setLibcallName(RTLIB::UREM_I128, nullptr);
216
217 // Division and modulus rtlib functions
218 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
219 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
220 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
221 setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
222 setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
223 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
224 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
225 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
226 setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
227 setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
228
229 // Several of the runtime library functions use a special calling conv
230 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
231 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
232 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
233 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
234
235 // Trigonometric rtlib functions
236 setLibcallName(RTLIB::SIN_F32, "sin");
237 setLibcallName(RTLIB::COS_F32, "cos");
238
239 setMinFunctionAlignment(Align(2));
240 setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U));
241}
242
243const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
244#define NODE(name) \
245 case AVRISD::name: \
246 return #name
247
248 switch (Opcode) {
249 default:
250 return nullptr;
251 NODE(RET_FLAG);
252 NODE(RETI_FLAG);
253 NODE(CALL);
254 NODE(WRAPPER);
255 NODE(LSL);
256 NODE(LSR);
257 NODE(ROL);
258 NODE(ROR);
259 NODE(ASR);
260 NODE(LSLLOOP);
261 NODE(LSRLOOP);
262 NODE(ASRLOOP);
263 NODE(BRCOND);
264 NODE(CMP);
265 NODE(CMPC);
266 NODE(TST);
267 NODE(SELECT_CC);
268#undef NODE
269 }
270}
271
272EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
273 EVT VT) const {
274 assert(!VT.isVector() && "No AVR SetCC type for vectors!")((!VT.isVector() && "No AVR SetCC type for vectors!")
? static_cast<void> (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 274, __PRETTY_FUNCTION__))
;
275 return MVT::i8;
276}
277
278SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
279 //:TODO: this function has to be completely rewritten to produce optimal
280 // code, for now it's producing very long but correct code.
281 unsigned Opc8;
282 const SDNode *N = Op.getNode();
283 EVT VT = Op.getValueType();
284 SDLoc dl(N);
285
286 // Expand non-constant shifts to loops.
287 if (!isa<ConstantSDNode>(N->getOperand(1))) {
288 switch (Op.getOpcode()) {
289 default:
290 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 290)
;
291 case ISD::SHL:
292 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
293 N->getOperand(1));
294 case ISD::SRL:
295 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
296 N->getOperand(1));
297 case ISD::ROTL:
298 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
299 N->getOperand(1));
300 case ISD::ROTR:
301 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
302 N->getOperand(1));
303 case ISD::SRA:
304 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
305 N->getOperand(1));
306 }
307 }
308
309 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
310 SDValue Victim = N->getOperand(0);
311
312 switch (Op.getOpcode()) {
313 case ISD::SRA:
314 Opc8 = AVRISD::ASR;
315 break;
316 case ISD::ROTL:
317 Opc8 = AVRISD::ROL;
318 break;
319 case ISD::ROTR:
320 Opc8 = AVRISD::ROR;
321 break;
322 case ISD::SRL:
323 Opc8 = AVRISD::LSR;
324 break;
325 case ISD::SHL:
326 Opc8 = AVRISD::LSL;
327 break;
328 default:
329 llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 329)
;
330 }
331
332 while (ShiftAmount--) {
333 Victim = DAG.getNode(Opc8, dl, VT, Victim);
334 }
335
336 return Victim;
337}
338
339SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
340 unsigned Opcode = Op->getOpcode();
341 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 342, __PRETTY_FUNCTION__))
342 "Invalid opcode for Div/Rem lowering")(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 342, __PRETTY_FUNCTION__))
;
343 bool IsSigned = (Opcode == ISD::SDIVREM);
344 EVT VT = Op->getValueType(0);
345 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
346
347 RTLIB::Libcall LC;
348 switch (VT.getSimpleVT().SimpleTy) {
349 default:
350 llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 350)
;
351 case MVT::i8:
352 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
353 break;
354 case MVT::i16:
355 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
356 break;
357 case MVT::i32:
358 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
359 break;
360 case MVT::i64:
361 LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
362 break;
363 case MVT::i128:
364 LC = IsSigned ? RTLIB::SDIVREM_I128 : RTLIB::UDIVREM_I128;
365 break;
366 }
367
368 SDValue InChain = DAG.getEntryNode();
369
370 TargetLowering::ArgListTy Args;
371 TargetLowering::ArgListEntry Entry;
372 for (SDValue const &Value : Op->op_values()) {
373 Entry.Node = Value;
374 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
375 Entry.IsSExt = IsSigned;
376 Entry.IsZExt = !IsSigned;
377 Args.push_back(Entry);
378 }
379
380 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
381 getPointerTy(DAG.getDataLayout()));
382
383 Type *RetTy = (Type *)StructType::get(Ty, Ty);
384
385 SDLoc dl(Op);
386 TargetLowering::CallLoweringInfo CLI(DAG);
387 CLI.setDebugLoc(dl)
388 .setChain(InChain)
389 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
390 .setInRegister()
391 .setSExtResult(IsSigned)
392 .setZExtResult(!IsSigned);
393
394 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
395 return CallInfo.first;
396}
397
398SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
399 SelectionDAG &DAG) const {
400 auto DL = DAG.getDataLayout();
401
402 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
403 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
404
405 // Create the TargetGlobalAddress node, folding in the constant offset.
406 SDValue Result =
407 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
408 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
409}
410
411SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
412 SelectionDAG &DAG) const {
413 auto DL = DAG.getDataLayout();
414 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
415
416 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
417
418 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
419}
420
421/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
422static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
423 switch (CC) {
424 default:
425 llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 425)
;
426 case ISD::SETEQ:
427 return AVRCC::COND_EQ;
428 case ISD::SETNE:
429 return AVRCC::COND_NE;
430 case ISD::SETGE:
431 return AVRCC::COND_GE;
432 case ISD::SETLT:
433 return AVRCC::COND_LT;
434 case ISD::SETUGE:
435 return AVRCC::COND_SH;
436 case ISD::SETULT:
437 return AVRCC::COND_LO;
438 }
439}
440
441/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
442/// the given operands.
443SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
444 SDValue &AVRcc, SelectionDAG &DAG,
445 SDLoc DL) const {
446 SDValue Cmp;
447 EVT VT = LHS.getValueType();
448 bool UseTest = false;
449
450 switch (CC) {
451 default:
452 break;
453 case ISD::SETLE: {
454 // Swap operands and reverse the branching condition.
455 std::swap(LHS, RHS);
456 CC = ISD::SETGE;
457 break;
458 }
459 case ISD::SETGT: {
460 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
461 switch (C->getSExtValue()) {
462 case -1: {
463 // When doing lhs > -1 use a tst instruction on the top part of lhs
464 // and use brpl instead of using a chain of cp/cpc.
465 UseTest = true;
466 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
467 break;
468 }
469 case 0: {
470 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
471 // __zero_reg__ in lhs.
472 RHS = LHS;
473 LHS = DAG.getConstant(0, DL, VT);
474 CC = ISD::SETLT;
475 break;
476 }
477 default: {
478 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
479 // us to fold the constant into the cmp instruction.
480 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
481 CC = ISD::SETGE;
482 break;
483 }
484 }
485 break;
486 }
487 // Swap operands and reverse the branching condition.
488 std::swap(LHS, RHS);
489 CC = ISD::SETLT;
490 break;
491 }
492 case ISD::SETLT: {
493 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
494 switch (C->getSExtValue()) {
495 case 1: {
496 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
497 // __zero_reg__ in lhs.
498 RHS = LHS;
499 LHS = DAG.getConstant(0, DL, VT);
500 CC = ISD::SETGE;
501 break;
502 }
503 case 0: {
504 // When doing lhs < 0 use a tst instruction on the top part of lhs
505 // and use brmi instead of using a chain of cp/cpc.
506 UseTest = true;
507 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
508 break;
509 }
510 }
511 }
512 break;
513 }
514 case ISD::SETULE: {
515 // Swap operands and reverse the branching condition.
516 std::swap(LHS, RHS);
517 CC = ISD::SETUGE;
518 break;
519 }
520 case ISD::SETUGT: {
521 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
522 // fold the constant into the cmp instruction.
523 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
524 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
525 CC = ISD::SETUGE;
526 break;
527 }
528 // Swap operands and reverse the branching condition.
529 std::swap(LHS, RHS);
530 CC = ISD::SETULT;
531 break;
532 }
533 }
534
535 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
536 // using the default and/or/xor expansion code which is much longer.
537 if (VT == MVT::i32) {
538 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
539 DAG.getIntPtrConstant(0, DL));
540 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
541 DAG.getIntPtrConstant(1, DL));
542 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
543 DAG.getIntPtrConstant(0, DL));
544 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
545 DAG.getIntPtrConstant(1, DL));
546
547 if (UseTest) {
548 // When using tst we only care about the highest part.
549 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
550 DAG.getIntPtrConstant(1, DL));
551 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
552 } else {
553 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
554 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
555 }
556 } else if (VT == MVT::i64) {
557 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
558 DAG.getIntPtrConstant(0, DL));
559 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
560 DAG.getIntPtrConstant(1, DL));
561
562 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
563 DAG.getIntPtrConstant(0, DL));
564 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
565 DAG.getIntPtrConstant(1, DL));
566 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
567 DAG.getIntPtrConstant(0, DL));
568 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
569 DAG.getIntPtrConstant(1, DL));
570
571 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
572 DAG.getIntPtrConstant(0, DL));
573 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
574 DAG.getIntPtrConstant(1, DL));
575
576 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
577 DAG.getIntPtrConstant(0, DL));
578 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
579 DAG.getIntPtrConstant(1, DL));
580 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
581 DAG.getIntPtrConstant(0, DL));
582 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
583 DAG.getIntPtrConstant(1, DL));
584
585 if (UseTest) {
586 // When using tst we only care about the highest part.
587 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
588 DAG.getIntPtrConstant(1, DL));
589 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
590 } else {
591 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
592 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
593 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
594 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
595 }
596 } else if (VT == MVT::i8 || VT == MVT::i16) {
597 if (UseTest) {
598 // When using tst we only care about the highest part.
599 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
600 (VT == MVT::i8)
601 ? LHS
602 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
603 LHS, DAG.getIntPtrConstant(1, DL)));
604 } else {
605 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
606 }
607 } else {
608 llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 608)
;
609 }
610
611 // When using a test instruction AVRcc is already set.
612 if (!UseTest) {
613 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
614 }
615
616 return Cmp;
617}
618
619SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
620 SDValue Chain = Op.getOperand(0);
621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
622 SDValue LHS = Op.getOperand(2);
623 SDValue RHS = Op.getOperand(3);
624 SDValue Dest = Op.getOperand(4);
625 SDLoc dl(Op);
626
627 SDValue TargetCC;
628 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
629
630 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
631 Cmp);
632}
633
634SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
635 SDValue LHS = Op.getOperand(0);
636 SDValue RHS = Op.getOperand(1);
637 SDValue TrueV = Op.getOperand(2);
638 SDValue FalseV = Op.getOperand(3);
639 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
640 SDLoc dl(Op);
641
642 SDValue TargetCC;
643 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
644
645 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
646 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
647
648 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
649}
650
651SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
652 SDValue LHS = Op.getOperand(0);
653 SDValue RHS = Op.getOperand(1);
654 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
655 SDLoc DL(Op);
656
657 SDValue TargetCC;
658 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
659
660 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
661 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
662 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
663 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
664
665 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
666}
667
668SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
669 const MachineFunction &MF = DAG.getMachineFunction();
670 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
671 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
672 auto DL = DAG.getDataLayout();
673 SDLoc dl(Op);
674
675 // Vastart just stores the address of the VarArgsFrameIndex slot into the
676 // memory location argument.
677 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
678
679 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
680 MachinePointerInfo(SV), 0);
681}
682
683SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
684 switch (Op.getOpcode()) {
685 default:
686 llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 686)
;
687 case ISD::SHL:
688 case ISD::SRA:
689 case ISD::SRL:
690 case ISD::ROTL:
691 case ISD::ROTR:
692 return LowerShifts(Op, DAG);
693 case ISD::GlobalAddress:
694 return LowerGlobalAddress(Op, DAG);
695 case ISD::BlockAddress:
696 return LowerBlockAddress(Op, DAG);
697 case ISD::BR_CC:
698 return LowerBR_CC(Op, DAG);
699 case ISD::SELECT_CC:
700 return LowerSELECT_CC(Op, DAG);
701 case ISD::SETCC:
702 return LowerSETCC(Op, DAG);
703 case ISD::VASTART:
704 return LowerVASTART(Op, DAG);
705 case ISD::SDIVREM:
706 case ISD::UDIVREM:
707 return LowerDivRem(Op, DAG);
708 }
709
710 return SDValue();
711}
712
713/// Replace a node with an illegal result type
714/// with a new node built out of custom code.
715void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
716 SmallVectorImpl<SDValue> &Results,
717 SelectionDAG &DAG) const {
718 SDLoc DL(N);
719
720 switch (N->getOpcode()) {
721 case ISD::ADD: {
722 // Convert add (x, imm) into sub (x, -imm).
723 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
724 SDValue Sub = DAG.getNode(
725 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
726 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
727 Results.push_back(Sub);
728 }
729 break;
730 }
731 default: {
732 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
733
734 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
735 Results.push_back(Res.getValue(I));
736
737 break;
738 }
739 }
740}
741
742/// Return true if the addressing mode represented
743/// by AM is legal for this target, for a load/store of the specified type.
744bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
745 const AddrMode &AM, Type *Ty,
746 unsigned AS, Instruction *I) const {
747 int64_t Offs = AM.BaseOffs;
748
749 // Allow absolute addresses.
750 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
751 return true;
752 }
753
754 // Flash memory instructions only allow zero offsets.
755 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
756 return false;
757 }
758
759 // Allow reg+<6bit> offset.
760 if (Offs < 0)
761 Offs = -Offs;
762 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
763 return true;
764 }
765
766 return false;
767}
768
769/// Returns true by value, base pointer and
770/// offset pointer and addressing mode by reference if the node's address
771/// can be legally represented as pre-indexed load / store address.
772bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
773 SDValue &Offset,
774 ISD::MemIndexedMode &AM,
775 SelectionDAG &DAG) const {
776 EVT VT;
777 const SDNode *Op;
778 SDLoc DL(N);
779
780 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
781 VT = LD->getMemoryVT();
782 Op = LD->getBasePtr().getNode();
783 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
784 return false;
785 if (AVR::isProgramMemoryAccess(LD)) {
786 return false;
787 }
788 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
789 VT = ST->getMemoryVT();
790 Op = ST->getBasePtr().getNode();
791 if (AVR::isProgramMemoryAccess(ST)) {
792 return false;
793 }
794 } else {
795 return false;
796 }
797
798 if (VT != MVT::i8 && VT != MVT::i16) {
799 return false;
800 }
801
802 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
803 return false;
804 }
805
806 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
807 int RHSC = RHS->getSExtValue();
808 if (Op->getOpcode() == ISD::SUB)
809 RHSC = -RHSC;
810
811 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
812 return false;
813 }
814
815 Base = Op->getOperand(0);
816 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
817 AM = ISD::PRE_DEC;
818
819 return true;
820 }
821
822 return false;
823}
824
825/// Returns true by value, base pointer and
826/// offset pointer and addressing mode by reference if this node can be
827/// combined with a load / store to form a post-indexed load / store.
828bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
829 SDValue &Base,
830 SDValue &Offset,
831 ISD::MemIndexedMode &AM,
832 SelectionDAG &DAG) const {
833 EVT VT;
834 SDLoc DL(N);
835
836 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
837 VT = LD->getMemoryVT();
838 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
839 return false;
840 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
841 VT = ST->getMemoryVT();
842 if (AVR::isProgramMemoryAccess(ST)) {
843 return false;
844 }
845 } else {
846 return false;
847 }
848
849 if (VT != MVT::i8 && VT != MVT::i16) {
850 return false;
851 }
852
853 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
854 return false;
855 }
856
857 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
858 int RHSC = RHS->getSExtValue();
859 if (Op->getOpcode() == ISD::SUB)
860 RHSC = -RHSC;
861 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
862 return false;
863 }
864
865 Base = Op->getOperand(0);
866 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
867 AM = ISD::POST_INC;
868
869 return true;
870 }
871
872 return false;
873}
874
875bool AVRTargetLowering::isOffsetFoldingLegal(
876 const GlobalAddressSDNode *GA) const {
877 return true;
878}
879
880//===----------------------------------------------------------------------===//
881// Formal Arguments Calling Convention Implementation
882//===----------------------------------------------------------------------===//
883
884#include "AVRGenCallingConv.inc"
885
886/// For each argument in a function store the number of pieces it is composed
887/// of.
888static void parseFunctionArgs(const SmallVectorImpl<ISD::InputArg> &Ins,
889 SmallVectorImpl<unsigned> &Out) {
890 for (const ISD::InputArg &Arg : Ins) {
891 if(Arg.PartOffset > 0) continue;
892 unsigned Bytes = ((Arg.ArgVT.getSizeInBits()) + 7) / 8;
893
894 Out.push_back((Bytes + 1) / 2);
895 }
896}
897
898/// For external symbols there is no function prototype information so we
899/// have to rely directly on argument sizes.
900static void parseExternFuncCallArgs(const SmallVectorImpl<ISD::OutputArg> &In,
901 SmallVectorImpl<unsigned> &Out) {
902 for (unsigned i = 0, e = In.size(); i != e;) {
903 unsigned Size = 0;
904 unsigned Offset = 0;
905 while ((i != e) && (In[i].PartOffset == Offset)) {
906 Offset += In[i].VT.getStoreSize();
907 ++i;
908 ++Size;
909 }
910 Out.push_back(Size);
911 }
912}
913
914static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI) {
915 SDValue Callee = CLI.Callee;
916
917 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
918 return G->getSymbol();
919 }
920
921 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
922 return G->getGlobal()->getName();
923 }
924
925 llvm_unreachable("don't know how to get the name for this callee")::llvm::llvm_unreachable_internal("don't know how to get the name for this callee"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 925)
;
926}
927
928/// Analyze incoming and outgoing function arguments. We need custom C++ code
929/// to handle special constraints in the ABI like reversing the order of the
930/// pieces of splitted arguments. In addition, all pieces of a certain argument
931/// have to be passed either using registers or the stack but never mixing both.
932static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI,
933 const Function *F, const DataLayout *TD,
934 const SmallVectorImpl<ISD::OutputArg> *Outs,
935 const SmallVectorImpl<ISD::InputArg> *Ins,
936 CallingConv::ID CallConv,
937 SmallVectorImpl<CCValAssign> &ArgLocs,
938 CCState &CCInfo, bool IsCall, bool IsVarArg) {
939 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
940 AVR::R18, AVR::R16, AVR::R14,
941 AVR::R12, AVR::R10, AVR::R8};
942 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
943 AVR::R19R18, AVR::R17R16, AVR::R15R14,
944 AVR::R13R12, AVR::R11R10, AVR::R9R8};
945 if (IsVarArg) {
946 // Variadic functions do not need all the analysis below.
947 if (IsCall) {
948 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
949 } else {
950 CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
951 }
952 return;
953 }
954
955 // Fill in the Args array which will contain original argument sizes.
956 SmallVector<unsigned, 8> Args;
957 if (IsCall) {
958 parseExternFuncCallArgs(*Outs, Args);
959 } else {
960 assert(F != nullptr && "function should not be null")((F != nullptr && "function should not be null") ? static_cast
<void> (0) : __assert_fail ("F != nullptr && \"function should not be null\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 960, __PRETTY_FUNCTION__))
;
961 parseFunctionArgs(*Ins, Args);
962 }
963
964 unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
965 // Variadic functions always use the stack.
966 bool UsesStack = false;
967 for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
968 unsigned Size = Args[i];
969
970 // If we have a zero-sized argument, don't attempt to lower it.
971 // AVR-GCC does not support zero-sized arguments and so we need not
972 // worry about ABI compatibility.
973 if (Size == 0) continue;
974
975 MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
976
977 // If we have plenty of regs to pass the whole argument do it.
978 if (!UsesStack && (Size <= RegsLeft)) {
979 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
980
981 for (unsigned j = 0; j != Size; ++j) {
982 unsigned Reg = CCInfo.AllocateReg(
983 ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
984 CCInfo.addLoc(
985 CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
986 --RegsLeft;
987 }
988
989 // Reverse the order of the pieces to agree with the "big endian" format
990 // required in the calling convention ABI.
991 std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
992 } else {
993 // Pass the rest of arguments using the stack.
994 UsesStack = true;
995 for (unsigned j = 0; j != Size; ++j) {
996 unsigned Offset = CCInfo.AllocateStack(
997 TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
998 TD->getABITypeAlignment(
999 EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
1000 CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
1001 CCValAssign::Full));
1002 }
1003 }
1004 pos += Size;
1005 }
1006}
1007
1008static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI,
1009 const Function *F, const DataLayout *TD,
1010 const SmallVectorImpl<ISD::OutputArg> *Outs,
1011 const SmallVectorImpl<ISD::InputArg> *Ins,
1012 CallingConv::ID CallConv,
1013 SmallVectorImpl<CCValAssign> &ArgLocs,
1014 CCState &CCInfo, bool IsCall, bool IsVarArg) {
1015 StringRef FuncName = getFunctionName(CLI);
1016
1017 if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
1018 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
1019 } else {
1020 analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1021 CallConv, ArgLocs, CCInfo,
1022 IsCall, IsVarArg);
1023 }
1024}
1025
1026static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
1027 const Function *F, const DataLayout *TD,
1028 const SmallVectorImpl<ISD::OutputArg> *Outs,
1029 const SmallVectorImpl<ISD::InputArg> *Ins,
1030 CallingConv::ID CallConv,
1031 SmallVectorImpl<CCValAssign> &ArgLocs,
1032 CCState &CCInfo, bool IsCall, bool IsVarArg) {
1033 switch (CallConv) {
3
Control jumps to 'case AVR_BUILTIN:' at line 1034
1034 case CallingConv::AVR_BUILTIN: {
1035 analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
4
Forming reference to null pointer
1036 CallConv, ArgLocs, CCInfo,
1037 IsCall, IsVarArg);
1038 return;
1039 }
1040 default: {
1041 analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1042 CallConv, ArgLocs, CCInfo,
1043 IsCall, IsVarArg);
1044 return;
1045 }
1046 }
1047}
1048
1049SDValue AVRTargetLowering::LowerFormalArguments(
1050 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1051 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1052 SmallVectorImpl<SDValue> &InVals) const {
1053 MachineFunction &MF = DAG.getMachineFunction();
1054 MachineFrameInfo &MFI = MF.getFrameInfo();
1055 auto DL = DAG.getDataLayout();
1056
1057 // Assign locations to all of the incoming arguments.
1058 SmallVector<CCValAssign, 16> ArgLocs;
1059 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1060 *DAG.getContext());
1061
1062 analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1
Passing null pointer value via 1st parameter 'CLI'
2
Calling 'analyzeArguments'
1063 false, isVarArg);
1064
1065 SDValue ArgValue;
1066 for (CCValAssign &VA : ArgLocs) {
1067
1068 // Arguments stored on registers.
1069 if (VA.isRegLoc()) {
1070 EVT RegVT = VA.getLocVT();
1071 const TargetRegisterClass *RC;
1072 if (RegVT == MVT::i8) {
1073 RC = &AVR::GPR8RegClass;
1074 } else if (RegVT == MVT::i16) {
1075 RC = &AVR::DREGSRegClass;
1076 } else {
1077 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1077)
;
1078 }
1079
1080 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1081 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1082
1083 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1084 // following code will handle zexts or sexts generated by other
1085 // front ends. Otherwise:
1086 // If this is an 8 bit value, it is really passed promoted
1087 // to 16 bits. Insert an assert[sz]ext to capture this, then
1088 // truncate to the right size.
1089 switch (VA.getLocInfo()) {
1090 default:
1091 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1091)
;
1092 case CCValAssign::Full:
1093 break;
1094 case CCValAssign::BCvt:
1095 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1096 break;
1097 case CCValAssign::SExt:
1098 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1099 DAG.getValueType(VA.getValVT()));
1100 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1101 break;
1102 case CCValAssign::ZExt:
1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1104 DAG.getValueType(VA.getValVT()));
1105 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1106 break;
1107 }
1108
1109 InVals.push_back(ArgValue);
1110 } else {
1111 // Sanity check.
1112 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1112, __PRETTY_FUNCTION__))
;
1113
1114 EVT LocVT = VA.getLocVT();
1115
1116 // Create the frame index object for this incoming parameter.
1117 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1118 VA.getLocMemOffset(), true);
1119
1120 // Create the SelectionDAG nodes corresponding to a load
1121 // from this parameter.
1122 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1123 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1124 MachinePointerInfo::getFixedStack(MF, FI),
1125 0));
1126 }
1127 }
1128
1129 // If the function takes variable number of arguments, make a frame index for
1130 // the start of the first vararg value... for expansion of llvm.va_start.
1131 if (isVarArg) {
1132 unsigned StackSize = CCInfo.getNextStackOffset();
1133 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1134
1135 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1136 }
1137
1138 return Chain;
1139}
1140
1141//===----------------------------------------------------------------------===//
1142// Call Calling Convention Implementation
1143//===----------------------------------------------------------------------===//
1144
1145SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1146 SmallVectorImpl<SDValue> &InVals) const {
1147 SelectionDAG &DAG = CLI.DAG;
1148 SDLoc &DL = CLI.DL;
1149 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1150 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1151 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1152 SDValue Chain = CLI.Chain;
1153 SDValue Callee = CLI.Callee;
1154 bool &isTailCall = CLI.IsTailCall;
1155 CallingConv::ID CallConv = CLI.CallConv;
1156 bool isVarArg = CLI.IsVarArg;
1157
1158 MachineFunction &MF = DAG.getMachineFunction();
1159
1160 // AVR does not yet support tail call optimization.
1161 isTailCall = false;
1162
1163 // Analyze operands of the call, assigning locations to each operand.
1164 SmallVector<CCValAssign, 16> ArgLocs;
1165 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1166 *DAG.getContext());
1167
1168 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1169 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1170 // node so that legalize doesn't hack it.
1171 const Function *F = nullptr;
1172 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1173 const GlobalValue *GV = G->getGlobal();
1174
1175 F = cast<Function>(GV);
1176 Callee =
1177 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1178 } else if (const ExternalSymbolSDNode *ES =
1179 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1180 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1181 getPointerTy(DAG.getDataLayout()));
1182 }
1183
1184 analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1185 true, isVarArg);
1186
1187 // Get a count of how many bytes are to be pushed on the stack.
1188 unsigned NumBytes = CCInfo.getNextStackOffset();
1189
1190 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1191
1192 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1193
1194 // First, walk the register assignments, inserting copies.
1195 unsigned AI, AE;
1196 bool HasStackArgs = false;
1197 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1198 CCValAssign &VA = ArgLocs[AI];
1199 EVT RegVT = VA.getLocVT();
1200 SDValue Arg = OutVals[AI];
1201
1202 // Promote the value if needed. With Clang this should not happen.
1203 switch (VA.getLocInfo()) {
1204 default:
1205 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1205)
;
1206 case CCValAssign::Full:
1207 break;
1208 case CCValAssign::SExt:
1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1210 break;
1211 case CCValAssign::ZExt:
1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1213 break;
1214 case CCValAssign::AExt:
1215 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1216 break;
1217 case CCValAssign::BCvt:
1218 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1219 break;
1220 }
1221
1222 // Stop when we encounter a stack argument, we need to process them
1223 // in reverse order in the loop below.
1224 if (VA.isMemLoc()) {
1225 HasStackArgs = true;
1226 break;
1227 }
1228
1229 // Arguments that can be passed on registers must be kept in the RegsToPass
1230 // vector.
1231 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1232 }
1233
1234 // Second, stack arguments have to walked in reverse order by inserting
1235 // chained stores, this ensures their order is not changed by the scheduler
1236 // and that the push instruction sequence generated is correct, otherwise they
1237 // can be freely intermixed.
1238 if (HasStackArgs) {
1239 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1240 unsigned Loc = AI - 1;
1241 CCValAssign &VA = ArgLocs[Loc];
1242 SDValue Arg = OutVals[Loc];
1243
1244 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1244, __PRETTY_FUNCTION__))
;
1245
1246 // SP points to one stack slot further so add one to adjust it.
1247 SDValue PtrOff = DAG.getNode(
1248 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1249 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1250 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1251
1252 Chain =
1253 DAG.getStore(Chain, DL, Arg, PtrOff,
1254 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()),
1255 0);
1256 }
1257 }
1258
1259 // Build a sequence of copy-to-reg nodes chained together with token chain and
1260 // flag operands which copy the outgoing args into registers. The InFlag in
1261 // necessary since all emited instructions must be stuck together.
1262 SDValue InFlag;
1263 for (auto Reg : RegsToPass) {
1264 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1265 InFlag = Chain.getValue(1);
1266 }
1267
1268 // Returns a chain & a flag for retval copy to use.
1269 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1270 SmallVector<SDValue, 8> Ops;
1271 Ops.push_back(Chain);
1272 Ops.push_back(Callee);
1273
1274 // Add argument registers to the end of the list so that they are known live
1275 // into the call.
1276 for (auto Reg : RegsToPass) {
1277 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1278 }
1279
1280 // Add a register mask operand representing the call-preserved registers.
1281 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1282 const uint32_t *Mask =
1283 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1284 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1284, __PRETTY_FUNCTION__))
;
1285 Ops.push_back(DAG.getRegisterMask(Mask));
1286
1287 if (InFlag.getNode()) {
1288 Ops.push_back(InFlag);
1289 }
1290
1291 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1292 InFlag = Chain.getValue(1);
1293
1294 // Create the CALLSEQ_END node.
1295 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1296 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1297
1298 if (!Ins.empty()) {
1299 InFlag = Chain.getValue(1);
1300 }
1301
1302 // Handle result values, copying them out of physregs into vregs that we
1303 // return.
1304 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1305 InVals);
1306}
1307
1308/// Lower the result values of a call into the
1309/// appropriate copies out of appropriate physical registers.
1310///
1311SDValue AVRTargetLowering::LowerCallResult(
1312 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1313 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1314 SmallVectorImpl<SDValue> &InVals) const {
1315
1316 // Assign locations to each value returned by this call.
1317 SmallVector<CCValAssign, 16> RVLocs;
1318 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1319 *DAG.getContext());
1320
1321 // Handle runtime calling convs.
1322 auto CCFunction = CCAssignFnForReturn(CallConv);
1323 CCInfo.AnalyzeCallResult(Ins, CCFunction);
1324
1325 if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1326 // Reverse splitted return values to get the "big endian" format required
1327 // to agree with the calling convention ABI.
1328 std::reverse(RVLocs.begin(), RVLocs.end());
1329 }
1330
1331 // Copy all of the result registers out of their specified physreg.
1332 for (CCValAssign const &RVLoc : RVLocs) {
1333 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1334 InFlag)
1335 .getValue(1);
1336 InFlag = Chain.getValue(2);
1337 InVals.push_back(Chain.getValue(0));
1338 }
1339
1340 return Chain;
1341}
1342
1343//===----------------------------------------------------------------------===//
1344// Return Value Calling Convention Implementation
1345//===----------------------------------------------------------------------===//
1346
1347CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1348 switch (CC) {
1349 case CallingConv::AVR_BUILTIN:
1350 return RetCC_AVR_BUILTIN;
1351 default:
1352 return RetCC_AVR;
1353 }
1354}
1355
1356bool
1357AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1358 MachineFunction &MF, bool isVarArg,
1359 const SmallVectorImpl<ISD::OutputArg> &Outs,
1360 LLVMContext &Context) const
1361{
1362 SmallVector<CCValAssign, 16> RVLocs;
1363 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1364
1365 auto CCFunction = CCAssignFnForReturn(CallConv);
1366 return CCInfo.CheckReturn(Outs, CCFunction);
1367}
1368
1369SDValue
1370AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1371 bool isVarArg,
1372 const SmallVectorImpl<ISD::OutputArg> &Outs,
1373 const SmallVectorImpl<SDValue> &OutVals,
1374 const SDLoc &dl, SelectionDAG &DAG) const {
1375 // CCValAssign - represent the assignment of the return value to locations.
1376 SmallVector<CCValAssign, 16> RVLocs;
1377
1378 // CCState - Info about the registers and stack slot.
1379 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1380 *DAG.getContext());
1381
1382 // Analyze return values.
1383 auto CCFunction = CCAssignFnForReturn(CallConv);
1384 CCInfo.AnalyzeReturn(Outs, CCFunction);
1385
1386 // If this is the first return lowered for this function, add the regs to
1387 // the liveout set for the function.
1388 MachineFunction &MF = DAG.getMachineFunction();
1389 unsigned e = RVLocs.size();
1390
1391 // Reverse splitted return values to get the "big endian" format required
1392 // to agree with the calling convention ABI.
1393 if (e > 1) {
1394 std::reverse(RVLocs.begin(), RVLocs.end());
1395 }
1396
1397 SDValue Flag;
1398 SmallVector<SDValue, 4> RetOps(1, Chain);
1399 // Copy the result values into the output registers.
1400 for (unsigned i = 0; i != e; ++i) {
1401 CCValAssign &VA = RVLocs[i];
1402 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1402, __PRETTY_FUNCTION__))
;
1403
1404 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1405
1406 // Guarantee that all emitted copies are stuck together with flags.
1407 Flag = Chain.getValue(1);
1408 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1409 }
1410
1411 // Don't emit the ret/reti instruction when the naked attribute is present in
1412 // the function being compiled.
1413 if (MF.getFunction().getAttributes().hasAttribute(
1414 AttributeList::FunctionIndex, Attribute::Naked)) {
1415 return Chain;
1416 }
1417
1418 unsigned RetOpc =
1419 (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1420 ? AVRISD::RETI_FLAG
1421 : AVRISD::RET_FLAG;
1422
1423 RetOps[0] = Chain; // Update chain.
1424
1425 if (Flag.getNode()) {
1426 RetOps.push_back(Flag);
1427 }
1428
1429 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1430}
1431
1432//===----------------------------------------------------------------------===//
1433// Custom Inserters
1434//===----------------------------------------------------------------------===//
1435
1436MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1437 MachineBasicBlock *BB) const {
1438 unsigned Opc;
1439 const TargetRegisterClass *RC;
1440 bool HasRepeatedOperand = false;
1441 MachineFunction *F = BB->getParent();
1442 MachineRegisterInfo &RI = F->getRegInfo();
1443 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1444 DebugLoc dl = MI.getDebugLoc();
1445
1446 switch (MI.getOpcode()) {
1447 default:
1448 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1448)
;
1449 case AVR::Lsl8:
1450 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1451 RC = &AVR::GPR8RegClass;
1452 HasRepeatedOperand = true;
1453 break;
1454 case AVR::Lsl16:
1455 Opc = AVR::LSLWRd;
1456 RC = &AVR::DREGSRegClass;
1457 break;
1458 case AVR::Asr8:
1459 Opc = AVR::ASRRd;
1460 RC = &AVR::GPR8RegClass;
1461 break;
1462 case AVR::Asr16:
1463 Opc = AVR::ASRWRd;
1464 RC = &AVR::DREGSRegClass;
1465 break;
1466 case AVR::Lsr8:
1467 Opc = AVR::LSRRd;
1468 RC = &AVR::GPR8RegClass;
1469 break;
1470 case AVR::Lsr16:
1471 Opc = AVR::LSRWRd;
1472 RC = &AVR::DREGSRegClass;
1473 break;
1474 case AVR::Rol8:
1475 Opc = AVR::ROLBRd;
1476 RC = &AVR::GPR8RegClass;
1477 break;
1478 case AVR::Rol16:
1479 Opc = AVR::ROLWRd;
1480 RC = &AVR::DREGSRegClass;
1481 break;
1482 case AVR::Ror8:
1483 Opc = AVR::RORBRd;
1484 RC = &AVR::GPR8RegClass;
1485 break;
1486 case AVR::Ror16:
1487 Opc = AVR::RORWRd;
1488 RC = &AVR::DREGSRegClass;
1489 break;
1490 }
1491
1492 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1493
1494 MachineFunction::iterator I;
1495 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1496 if (I != F->end()) ++I;
1497
1498 // Create loop block.
1499 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1500 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1501
1502 F->insert(I, LoopBB);
1503 F->insert(I, RemBB);
1504
1505 // Update machine-CFG edges by transferring all successors of the current
1506 // block to the block containing instructions after shift.
1507 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1508 BB->end());
1509 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1510
1511 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1512 BB->addSuccessor(LoopBB);
1513 BB->addSuccessor(RemBB);
1514 LoopBB->addSuccessor(RemBB);
1515 LoopBB->addSuccessor(LoopBB);
1516
1517 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1518 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1519 Register ShiftReg = RI.createVirtualRegister(RC);
1520 Register ShiftReg2 = RI.createVirtualRegister(RC);
1521 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1522 Register SrcReg = MI.getOperand(1).getReg();
1523 Register DstReg = MI.getOperand(0).getReg();
1524
1525 // BB:
1526 // cpi N, 0
1527 // breq RemBB
1528 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1529 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1530
1531 // LoopBB:
1532 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1533 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1534 // ShiftReg2 = shift ShiftReg
1535 // ShiftAmt2 = ShiftAmt - 1;
1536 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1537 .addReg(SrcReg)
1538 .addMBB(BB)
1539 .addReg(ShiftReg2)
1540 .addMBB(LoopBB);
1541 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1542 .addReg(ShiftAmtSrcReg)
1543 .addMBB(BB)
1544 .addReg(ShiftAmtReg2)
1545 .addMBB(LoopBB);
1546
1547 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1548 if (HasRepeatedOperand)
1549 ShiftMI.addReg(ShiftReg);
1550
1551 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1552 .addReg(ShiftAmtReg)
1553 .addImm(1);
1554 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1555
1556 // RemBB:
1557 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1558 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1559 .addReg(SrcReg)
1560 .addMBB(BB)
1561 .addReg(ShiftReg2)
1562 .addMBB(LoopBB);
1563
1564 MI.eraseFromParent(); // The pseudo instruction is gone now.
1565 return RemBB;
1566}
1567
1568static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
1569 if (I->getOpcode() == AVR::COPY) {
1570 Register SrcReg = I->getOperand(1).getReg();
1571 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1572 }
1573
1574 return false;
1575}
1576
1577// The mul instructions wreak havock on our zero_reg R1. We need to clear it
1578// after the result has been evacuated. This is probably not the best way to do
1579// it, but it works for now.
1580MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1581 MachineBasicBlock *BB) const {
1582 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1583 MachineBasicBlock::iterator I(MI);
1584 ++I; // in any case insert *after* the mul instruction
1585 if (isCopyMulResult(I))
1586 ++I;
1587 if (isCopyMulResult(I))
1588 ++I;
1589 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1590 .addReg(AVR::R1)
1591 .addReg(AVR::R1);
1592 return BB;
1593}
1594
1595MachineBasicBlock *
1596AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1597 MachineBasicBlock *MBB) const {
1598 int Opc = MI.getOpcode();
1599
1600 // Pseudo shift instructions with a non constant shift amount are expanded
1601 // into a loop.
1602 switch (Opc) {
1603 case AVR::Lsl8:
1604 case AVR::Lsl16:
1605 case AVR::Lsr8:
1606 case AVR::Lsr16:
1607 case AVR::Rol8:
1608 case AVR::Rol16:
1609 case AVR::Ror8:
1610 case AVR::Ror16:
1611 case AVR::Asr8:
1612 case AVR::Asr16:
1613 return insertShift(MI, MBB);
1614 case AVR::MULRdRr:
1615 case AVR::MULSRdRr:
1616 return insertMul(MI, MBB);
1617 }
1618
1619 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1620, __PRETTY_FUNCTION__))
1620 "Unexpected instr type to insert")(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1620, __PRETTY_FUNCTION__))
;
1621
1622 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1623 ->getParent()
1624 ->getSubtarget()
1625 .getInstrInfo();
1626 DebugLoc dl = MI.getDebugLoc();
1627
1628 // To "insert" a SELECT instruction, we insert the diamond
1629 // control-flow pattern. The incoming instruction knows the
1630 // destination vreg to set, the condition code register to branch
1631 // on, the true/false values to select between, and a branch opcode
1632 // to use.
1633
1634 MachineFunction *MF = MBB->getParent();
1635 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1636 MachineBasicBlock *FallThrough = MBB->getFallThrough();
1637
1638 // If the current basic block falls through to another basic block,
1639 // we must insert an unconditional branch to the fallthrough destination
1640 // if we are to insert basic blocks at the prior fallthrough point.
1641 if (FallThrough != nullptr) {
1642 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1643 }
1644
1645 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1646 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1647
1648 MachineFunction::iterator I;
1649 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1650 if (I != MF->end()) ++I;
1651 MF->insert(I, trueMBB);
1652 MF->insert(I, falseMBB);
1653
1654 // Transfer remaining instructions and all successors of the current
1655 // block to the block which will contain the Phi node for the
1656 // select.
1657 trueMBB->splice(trueMBB->begin(), MBB,
1658 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1659 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1660
1661 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1662 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1663 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1664 MBB->addSuccessor(falseMBB);
1665 MBB->addSuccessor(trueMBB);
1666
1667 // Unconditionally flow back to the true block
1668 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1669 falseMBB->addSuccessor(trueMBB);
1670
1671 // Set up the Phi node to determine where we came from
1672 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1673 .addReg(MI.getOperand(1).getReg())
1674 .addMBB(MBB)
1675 .addReg(MI.getOperand(2).getReg())
1676 .addMBB(falseMBB) ;
1677
1678 MI.eraseFromParent(); // The pseudo instruction is gone now.
1679 return trueMBB;
1680}
1681
1682//===----------------------------------------------------------------------===//
1683// Inline Asm Support
1684//===----------------------------------------------------------------------===//
1685
1686AVRTargetLowering::ConstraintType
1687AVRTargetLowering::getConstraintType(StringRef Constraint) const {
1688 if (Constraint.size() == 1) {
1689 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1690 switch (Constraint[0]) {
1691 default:
1692 break;
1693 case 'a': // Simple upper registers
1694 case 'b': // Base pointer registers pairs
1695 case 'd': // Upper register
1696 case 'l': // Lower registers
1697 case 'e': // Pointer register pairs
1698 case 'q': // Stack pointer register
1699 case 'r': // Any register
1700 case 'w': // Special upper register pairs
1701 return C_RegisterClass;
1702 case 't': // Temporary register
1703 case 'x': case 'X': // Pointer register pair X
1704 case 'y': case 'Y': // Pointer register pair Y
1705 case 'z': case 'Z': // Pointer register pair Z
1706 return C_Register;
1707 case 'Q': // A memory address based on Y or Z pointer with displacement.
1708 return C_Memory;
1709 case 'G': // Floating point constant
1710 case 'I': // 6-bit positive integer constant
1711 case 'J': // 6-bit negative integer constant
1712 case 'K': // Integer constant (Range: 2)
1713 case 'L': // Integer constant (Range: 0)
1714 case 'M': // 8-bit integer constant
1715 case 'N': // Integer constant (Range: -1)
1716 case 'O': // Integer constant (Range: 8, 16, 24)
1717 case 'P': // Integer constant (Range: 1)
1718 case 'R': // Integer constant (Range: -6 to 5)x
1719 return C_Immediate;
1720 }
1721 }
1722
1723 return TargetLowering::getConstraintType(Constraint);
1724}
1725
1726unsigned
1727AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
1728 // Not sure if this is actually the right thing to do, but we got to do
1729 // *something* [agnat]
1730 switch (ConstraintCode[0]) {
1731 case 'Q':
1732 return InlineAsm::Constraint_Q;
1733 }
1734 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1735}
1736
1737AVRTargetLowering::ConstraintWeight
1738AVRTargetLowering::getSingleConstraintMatchWeight(
1739 AsmOperandInfo &info, const char *constraint) const {
1740 ConstraintWeight weight = CW_Invalid;
1741 Value *CallOperandVal = info.CallOperandVal;
1742
1743 // If we don't have a value, we can't do a match,
1744 // but allow it at the lowest weight.
1745 // (this behaviour has been copied from the ARM backend)
1746 if (!CallOperandVal) {
1747 return CW_Default;
1748 }
1749
1750 // Look at the constraint type.
1751 switch (*constraint) {
1752 default:
1753 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1754 break;
1755 case 'd':
1756 case 'r':
1757 case 'l':
1758 weight = CW_Register;
1759 break;
1760 case 'a':
1761 case 'b':
1762 case 'e':
1763 case 'q':
1764 case 't':
1765 case 'w':
1766 case 'x': case 'X':
1767 case 'y': case 'Y':
1768 case 'z': case 'Z':
1769 weight = CW_SpecificReg;
1770 break;
1771 case 'G':
1772 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1773 if (C->isZero()) {
1774 weight = CW_Constant;
1775 }
1776 }
1777 break;
1778 case 'I':
1779 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1780 if (isUInt<6>(C->getZExtValue())) {
1781 weight = CW_Constant;
1782 }
1783 }
1784 break;
1785 case 'J':
1786 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1787 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1788 weight = CW_Constant;
1789 }
1790 }
1791 break;
1792 case 'K':
1793 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1794 if (C->getZExtValue() == 2) {
1795 weight = CW_Constant;
1796 }
1797 }
1798 break;
1799 case 'L':
1800 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1801 if (C->getZExtValue() == 0) {
1802 weight = CW_Constant;
1803 }
1804 }
1805 break;
1806 case 'M':
1807 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1808 if (isUInt<8>(C->getZExtValue())) {
1809 weight = CW_Constant;
1810 }
1811 }
1812 break;
1813 case 'N':
1814 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1815 if (C->getSExtValue() == -1) {
1816 weight = CW_Constant;
1817 }
1818 }
1819 break;
1820 case 'O':
1821 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1822 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1823 (C->getZExtValue() == 24)) {
1824 weight = CW_Constant;
1825 }
1826 }
1827 break;
1828 case 'P':
1829 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1830 if (C->getZExtValue() == 1) {
1831 weight = CW_Constant;
1832 }
1833 }
1834 break;
1835 case 'R':
1836 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1837 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1838 weight = CW_Constant;
1839 }
1840 }
1841 break;
1842 case 'Q':
1843 weight = CW_Memory;
1844 break;
1845 }
1846
1847 return weight;
1848}
1849
1850std::pair<unsigned, const TargetRegisterClass *>
1851AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1852 StringRef Constraint,
1853 MVT VT) const {
1854 // We only support i8 and i16.
1855 //
1856 //:FIXME: remove this assert for now since it gets sometimes executed
1857 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1858
1859 if (Constraint.size() == 1) {
1860 switch (Constraint[0]) {
1861 case 'a': // Simple upper registers r16..r23.
1862 return std::make_pair(0U, &AVR::LD8loRegClass);
1863 case 'b': // Base pointer registers: y, z.
1864 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1865 case 'd': // Upper registers r16..r31.
1866 return std::make_pair(0U, &AVR::LD8RegClass);
1867 case 'l': // Lower registers r0..r15.
1868 return std::make_pair(0U, &AVR::GPR8loRegClass);
1869 case 'e': // Pointer register pairs: x, y, z.
1870 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1871 case 'q': // Stack pointer register: SPH:SPL.
1872 return std::make_pair(0U, &AVR::GPRSPRegClass);
1873 case 'r': // Any register: r0..r31.
1874 if (VT == MVT::i8)
1875 return std::make_pair(0U, &AVR::GPR8RegClass);
1876
1877 assert(VT == MVT::i16 && "inline asm constraint too large")((VT == MVT::i16 && "inline asm constraint too large"
) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i16 && \"inline asm constraint too large\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1877, __PRETTY_FUNCTION__))
;
1878 return std::make_pair(0U, &AVR::DREGSRegClass);
1879 case 't': // Temporary register: r0.
1880 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1881 case 'w': // Special upper register pairs: r24, r26, r28, r30.
1882 return std::make_pair(0U, &AVR::IWREGSRegClass);
1883 case 'x': // Pointer register pair X: r27:r26.
1884 case 'X':
1885 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1886 case 'y': // Pointer register pair Y: r29:r28.
1887 case 'Y':
1888 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1889 case 'z': // Pointer register pair Z: r31:r30.
1890 case 'Z':
1891 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1892 default:
1893 break;
1894 }
1895 }
1896
1897 return TargetLowering::getRegForInlineAsmConstraint(
1898 Subtarget.getRegisterInfo(), Constraint, VT);
1899}
1900
1901void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1902 std::string &Constraint,
1903 std::vector<SDValue> &Ops,
1904 SelectionDAG &DAG) const {
1905 SDValue Result(0, 0);
1906 SDLoc DL(Op);
1907 EVT Ty = Op.getValueType();
1908
1909 // Currently only support length 1 constraints.
1910 if (Constraint.length() != 1) {
1911 return;
1912 }
1913
1914 char ConstraintLetter = Constraint[0];
1915 switch (ConstraintLetter) {
1916 default:
1917 break;
1918 // Deal with integers first:
1919 case 'I':
1920 case 'J':
1921 case 'K':
1922 case 'L':
1923 case 'M':
1924 case 'N':
1925 case 'O':
1926 case 'P':
1927 case 'R': {
1928 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1929 if (!C) {
1930 return;
1931 }
1932
1933 int64_t CVal64 = C->getSExtValue();
1934 uint64_t CUVal64 = C->getZExtValue();
1935 switch (ConstraintLetter) {
1936 case 'I': // 0..63
1937 if (!isUInt<6>(CUVal64))
1938 return;
1939 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1940 break;
1941 case 'J': // -63..0
1942 if (CVal64 < -63 || CVal64 > 0)
1943 return;
1944 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1945 break;
1946 case 'K': // 2
1947 if (CUVal64 != 2)
1948 return;
1949 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1950 break;
1951 case 'L': // 0
1952 if (CUVal64 != 0)
1953 return;
1954 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1955 break;
1956 case 'M': // 0..255
1957 if (!isUInt<8>(CUVal64))
1958 return;
1959 // i8 type may be printed as a negative number,
1960 // e.g. 254 would be printed as -2,
1961 // so we force it to i16 at least.
1962 if (Ty.getSimpleVT() == MVT::i8) {
1963 Ty = MVT::i16;
1964 }
1965 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1966 break;
1967 case 'N': // -1
1968 if (CVal64 != -1)
1969 return;
1970 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1971 break;
1972 case 'O': // 8, 16, 24
1973 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1974 return;
1975 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1976 break;
1977 case 'P': // 1
1978 if (CUVal64 != 1)
1979 return;
1980 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1981 break;
1982 case 'R': // -6..5
1983 if (CVal64 < -6 || CVal64 > 5)
1984 return;
1985 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1986 break;
1987 }
1988
1989 break;
1990 }
1991 case 'G':
1992 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
1993 if (!FC || !FC->isZero())
1994 return;
1995 // Soften float to i8 0
1996 Result = DAG.getTargetConstant(0, DL, MVT::i8);
1997 break;
1998 }
1999
2000 if (Result.getNode()) {
2001 Ops.push_back(Result);
2002 return;
2003 }
2004
2005 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2006}
2007
2008Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2009 const MachineFunction &MF) const {
2010 Register Reg;
2011
2012 if (VT == LLT::scalar(8)) {
2013 Reg = StringSwitch<unsigned>(RegName)
2014 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
2015 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
2016 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
2017 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
2018 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
2019 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
2020 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
2021 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
2022 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2023 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2024 .Case("r30", AVR::R30).Case("r31", AVR::R31)
2025 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2026 .Default(0);
2027 } else {
2028 Reg = StringSwitch<unsigned>(RegName)
2029 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2030 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2031 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2032 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2033 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2034 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2035 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2036 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2037 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2038 .Default(0);
2039 }
2040
2041 if (Reg)
2042 return Reg;
2043
2044 report_fatal_error("Invalid register name global variable");
2045}
2046
2047} // end of namespace llvm