Bug Summary

File:llvm/lib/Target/AVR/AVRISelLowering.cpp
Warning:line 1111, column 13
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AVR -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/AVR -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-04-14-063029-18377-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp

/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp

1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
53
54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
58
59 for (MVT VT : MVT::integer_valuetypes()) {
60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
61 setLoadExtAction(N, VT, MVT::i1, Promote);
62 setLoadExtAction(N, VT, MVT::i8, Expand);
63 }
64 }
65
66 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
67
68 for (MVT VT : MVT::integer_valuetypes()) {
69 setOperationAction(ISD::ADDC, VT, Legal);
70 setOperationAction(ISD::SUBC, VT, Legal);
71 setOperationAction(ISD::ADDE, VT, Legal);
72 setOperationAction(ISD::SUBE, VT, Legal);
73 }
74
75 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76 // revert into a sub since we don't have an add with immediate instruction.
77 setOperationAction(ISD::ADD, MVT::i32, Custom);
78 setOperationAction(ISD::ADD, MVT::i64, Custom);
79
80 // our shift instructions are only able to shift 1 bit at a time, so handle
81 // this in a custom way.
82 setOperationAction(ISD::SRA, MVT::i8, Custom);
83 setOperationAction(ISD::SHL, MVT::i8, Custom);
84 setOperationAction(ISD::SRL, MVT::i8, Custom);
85 setOperationAction(ISD::SRA, MVT::i16, Custom);
86 setOperationAction(ISD::SHL, MVT::i16, Custom);
87 setOperationAction(ISD::SRL, MVT::i16, Custom);
88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
91
92 setOperationAction(ISD::ROTL, MVT::i8, Custom);
93 setOperationAction(ISD::ROTL, MVT::i16, Expand);
94 setOperationAction(ISD::ROTR, MVT::i8, Custom);
95 setOperationAction(ISD::ROTR, MVT::i16, Expand);
96
97 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102
103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
107 setOperationAction(ISD::SETCC, MVT::i8, Custom);
108 setOperationAction(ISD::SETCC, MVT::i16, Custom);
109 setOperationAction(ISD::SETCC, MVT::i32, Custom);
110 setOperationAction(ISD::SETCC, MVT::i64, Custom);
111 setOperationAction(ISD::SELECT, MVT::i8, Expand);
112 setOperationAction(ISD::SELECT, MVT::i16, Expand);
113
114 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
115
116 // Add support for postincrement and predecrement load/stores.
117 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
121 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
125
126 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
127
128 setOperationAction(ISD::VASTART, MVT::Other, Custom);
129 setOperationAction(ISD::VAEND, MVT::Other, Expand);
130 setOperationAction(ISD::VAARG, MVT::Other, Expand);
131 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
132
133 // Atomic operations which must be lowered to rtlib calls
134 for (MVT VT : MVT::integer_valuetypes()) {
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
142 }
143
144 // Division/remainder
145 setOperationAction(ISD::UDIV, MVT::i8, Expand);
146 setOperationAction(ISD::UDIV, MVT::i16, Expand);
147 setOperationAction(ISD::UREM, MVT::i8, Expand);
148 setOperationAction(ISD::UREM, MVT::i16, Expand);
149 setOperationAction(ISD::SDIV, MVT::i8, Expand);
150 setOperationAction(ISD::SDIV, MVT::i16, Expand);
151 setOperationAction(ISD::SREM, MVT::i8, Expand);
152 setOperationAction(ISD::SREM, MVT::i16, Expand);
153
154 // Make division and modulus custom
155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom);
156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Custom);
159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom);
160 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
161
162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
163 setOperationAction(ISD::MUL, MVT::i8, Expand);
164 setOperationAction(ISD::MUL, MVT::i16, Expand);
165
166 // Expand 16 bit multiplications.
167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
169
170 // Expand multiplications to libcalls when there is
171 // no hardware MUL.
172 if (!Subtarget.supportsMultiplication()) {
173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
175 }
176
177 for (MVT VT : MVT::integer_valuetypes()) {
178 setOperationAction(ISD::MULHS, VT, Expand);
179 setOperationAction(ISD::MULHU, VT, Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(ISD::CTPOP, VT, Expand);
184 setOperationAction(ISD::CTLZ, VT, Expand);
185 setOperationAction(ISD::CTTZ, VT, Expand);
186 }
187
188 for (MVT VT : MVT::integer_valuetypes()) {
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 // TODO: The generated code is pretty poor. Investigate using the
191 // same "shift and subtract with carry" trick that we do for
192 // extending 8-bit to 16-bit. This may require infrastructure
193 // improvements in how we treat 16-bit "registers" to be feasible.
194 }
195
196 // Division rtlib functions (not supported), use divmod functions instead
197 setLibcallName(RTLIB::SDIV_I8, nullptr);
198 setLibcallName(RTLIB::SDIV_I16, nullptr);
199 setLibcallName(RTLIB::SDIV_I32, nullptr);
200 setLibcallName(RTLIB::UDIV_I8, nullptr);
201 setLibcallName(RTLIB::UDIV_I16, nullptr);
202 setLibcallName(RTLIB::UDIV_I32, nullptr);
203
204 // Modulus rtlib functions (not supported), use divmod functions instead
205 setLibcallName(RTLIB::SREM_I8, nullptr);
206 setLibcallName(RTLIB::SREM_I16, nullptr);
207 setLibcallName(RTLIB::SREM_I32, nullptr);
208 setLibcallName(RTLIB::UREM_I8, nullptr);
209 setLibcallName(RTLIB::UREM_I16, nullptr);
210 setLibcallName(RTLIB::UREM_I32, nullptr);
211
212 // Division and modulus rtlib functions
213 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219
220 // Several of the runtime library functions use a special calling conv
221 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
222 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
223 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
224 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225
226 // Trigonometric rtlib functions
227 setLibcallName(RTLIB::SIN_F32, "sin");
228 setLibcallName(RTLIB::COS_F32, "cos");
229
230 setMinFunctionAlignment(Align(2));
231 setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U));
232}
233
234const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235#define NODE(name) \
236 case AVRISD::name: \
237 return #name
238
239 switch (Opcode) {
240 default:
241 return nullptr;
242 NODE(RET_FLAG);
243 NODE(RETI_FLAG);
244 NODE(CALL);
245 NODE(WRAPPER);
246 NODE(LSL);
247 NODE(LSR);
248 NODE(ROL);
249 NODE(ROR);
250 NODE(ASR);
251 NODE(LSLLOOP);
252 NODE(LSRLOOP);
253 NODE(ROLLOOP);
254 NODE(RORLOOP);
255 NODE(ASRLOOP);
256 NODE(BRCOND);
257 NODE(CMP);
258 NODE(CMPC);
259 NODE(TST);
260 NODE(SELECT_CC);
261#undef NODE
262 }
263}
264
265EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
266 EVT VT) const {
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!")((!VT.isVector() && "No AVR SetCC type for vectors!")
? static_cast<void> (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 267, __PRETTY_FUNCTION__))
;
268 return MVT::i8;
269}
270
271SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272 //:TODO: this function has to be completely rewritten to produce optimal
273 // code, for now it's producing very long but correct code.
274 unsigned Opc8;
275 const SDNode *N = Op.getNode();
276 EVT VT = Op.getValueType();
277 SDLoc dl(N);
278 assert(isPowerOf2_32(VT.getSizeInBits()) &&((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
279 "Expected power-of-2 shift amount")((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
;
280
281 // Expand non-constant shifts to loops.
282 if (!isa<ConstantSDNode>(N->getOperand(1))) {
283 switch (Op.getOpcode()) {
284 default:
285 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 285)
;
286 case ISD::SHL:
287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288 N->getOperand(1));
289 case ISD::SRL:
290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291 N->getOperand(1));
292 case ISD::ROTL: {
293 SDValue Amt = N->getOperand(1);
294 EVT AmtVT = Amt.getValueType();
295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298 }
299 case ISD::ROTR: {
300 SDValue Amt = N->getOperand(1);
301 EVT AmtVT = Amt.getValueType();
302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305 }
306 case ISD::SRA:
307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308 N->getOperand(1));
309 }
310 }
311
312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313 SDValue Victim = N->getOperand(0);
314
315 switch (Op.getOpcode()) {
316 case ISD::SRA:
317 Opc8 = AVRISD::ASR;
318 break;
319 case ISD::ROTL:
320 Opc8 = AVRISD::ROL;
321 ShiftAmount = ShiftAmount % VT.getSizeInBits();
322 break;
323 case ISD::ROTR:
324 Opc8 = AVRISD::ROR;
325 ShiftAmount = ShiftAmount % VT.getSizeInBits();
326 break;
327 case ISD::SRL:
328 Opc8 = AVRISD::LSR;
329 break;
330 case ISD::SHL:
331 Opc8 = AVRISD::LSL;
332 break;
333 default:
334 llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 334)
;
335 }
336
337 // Optimize int8/int16 shifts.
338 if (VT.getSizeInBits() == 8) {
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340 // Optimize LSL when 4 <= ShiftAmount <= 6.
341 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
342 Victim =
343 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
344 ShiftAmount -= 4;
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
346 ShiftAmount < 7) {
347 // Optimize LSR when 4 <= ShiftAmount <= 6.
348 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
349 Victim =
350 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
351 ShiftAmount -= 4;
352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
353 // Optimize LSL when ShiftAmount == 7.
354 Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim);
355 ShiftAmount = 0;
356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
357 // Optimize LSR when ShiftAmount == 7.
358 Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim);
359 ShiftAmount = 0;
360 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
361 // Optimize ASR when ShiftAmount == 7.
362 Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
363 ShiftAmount = 0;
364 }
365 } else if (VT.getSizeInBits() == 16) {
366 if (4 <= ShiftAmount && ShiftAmount < 8)
367 switch (Op.getOpcode()) {
368 case ISD::SHL:
369 Victim = DAG.getNode(AVRISD::LSL4, dl, VT, Victim);
370 ShiftAmount -= 4;
371 break;
372 case ISD::SRL:
373 Victim = DAG.getNode(AVRISD::LSR4, dl, VT, Victim);
374 ShiftAmount -= 4;
375 break;
376 default:
377 break;
378 }
379 else if (8 <= ShiftAmount && ShiftAmount < 12)
380 switch (Op.getOpcode()) {
381 case ISD::SHL:
382 Victim = DAG.getNode(AVRISD::LSL8, dl, VT, Victim);
383 ShiftAmount -= 8;
384 break;
385 case ISD::SRL:
386 Victim = DAG.getNode(AVRISD::LSR8, dl, VT, Victim);
387 ShiftAmount -= 8;
388 break;
389 case ISD::SRA:
390 Victim = DAG.getNode(AVRISD::ASR8, dl, VT, Victim);
391 ShiftAmount -= 8;
392 break;
393 default:
394 break;
395 }
396 else if (12 <= ShiftAmount)
397 switch (Op.getOpcode()) {
398 case ISD::SHL:
399 Victim = DAG.getNode(AVRISD::LSL12, dl, VT, Victim);
400 ShiftAmount -= 12;
401 break;
402 case ISD::SRL:
403 Victim = DAG.getNode(AVRISD::LSR12, dl, VT, Victim);
404 ShiftAmount -= 12;
405 break;
406 default:
407 break;
408 }
409 }
410
411 while (ShiftAmount--) {
412 Victim = DAG.getNode(Opc8, dl, VT, Victim);
413 }
414
415 return Victim;
416}
417
418SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
419 unsigned Opcode = Op->getOpcode();
420 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 421, __PRETTY_FUNCTION__))
421 "Invalid opcode for Div/Rem lowering")(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 421, __PRETTY_FUNCTION__))
;
422 bool IsSigned = (Opcode == ISD::SDIVREM);
423 EVT VT = Op->getValueType(0);
424 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
425
426 RTLIB::Libcall LC;
427 switch (VT.getSimpleVT().SimpleTy) {
428 default:
429 llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 429)
;
430 case MVT::i8:
431 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
432 break;
433 case MVT::i16:
434 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
435 break;
436 case MVT::i32:
437 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
438 break;
439 }
440
441 SDValue InChain = DAG.getEntryNode();
442
443 TargetLowering::ArgListTy Args;
444 TargetLowering::ArgListEntry Entry;
445 for (SDValue const &Value : Op->op_values()) {
446 Entry.Node = Value;
447 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
448 Entry.IsSExt = IsSigned;
449 Entry.IsZExt = !IsSigned;
450 Args.push_back(Entry);
451 }
452
453 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
454 getPointerTy(DAG.getDataLayout()));
455
456 Type *RetTy = (Type *)StructType::get(Ty, Ty);
457
458 SDLoc dl(Op);
459 TargetLowering::CallLoweringInfo CLI(DAG);
460 CLI.setDebugLoc(dl)
461 .setChain(InChain)
462 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
463 .setInRegister()
464 .setSExtResult(IsSigned)
465 .setZExtResult(!IsSigned);
466
467 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
468 return CallInfo.first;
469}
470
471SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
472 SelectionDAG &DAG) const {
473 auto DL = DAG.getDataLayout();
474
475 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
476 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
477
478 // Create the TargetGlobalAddress node, folding in the constant offset.
479 SDValue Result =
480 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
481 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
482}
483
484SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
485 SelectionDAG &DAG) const {
486 auto DL = DAG.getDataLayout();
487 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
488
489 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
490
491 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
492}
493
494/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
495static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
496 switch (CC) {
497 default:
498 llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 498)
;
499 case ISD::SETEQ:
500 return AVRCC::COND_EQ;
501 case ISD::SETNE:
502 return AVRCC::COND_NE;
503 case ISD::SETGE:
504 return AVRCC::COND_GE;
505 case ISD::SETLT:
506 return AVRCC::COND_LT;
507 case ISD::SETUGE:
508 return AVRCC::COND_SH;
509 case ISD::SETULT:
510 return AVRCC::COND_LO;
511 }
512}
513
514/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
515SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
516 SelectionDAG &DAG, SDLoc DL) const {
517 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&(((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
"LHS and RHS have different types") ? static_cast<void>
(0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 518, __PRETTY_FUNCTION__))
518 "LHS and RHS have different types")(((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
"LHS and RHS have different types") ? static_cast<void>
(0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 518, __PRETTY_FUNCTION__))
;
519 assert(((LHS.getSimpleValueType() == MVT::i16) ||((((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType
() == MVT::i8)) && "invalid comparison type") ? static_cast
<void> (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 520, __PRETTY_FUNCTION__))
520 (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type")((((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType
() == MVT::i8)) && "invalid comparison type") ? static_cast
<void> (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 520, __PRETTY_FUNCTION__))
;
521
522 SDValue Cmp;
523
524 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
525 // Generate a CPI/CPC pair if RHS is a 16-bit constant.
526 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
527 DAG.getIntPtrConstant(0, DL));
528 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
529 DAG.getIntPtrConstant(1, DL));
530 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
531 DAG.getIntPtrConstant(0, DL));
532 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
533 DAG.getIntPtrConstant(1, DL));
534 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
535 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
536 } else {
537 // Generate ordinary 16-bit comparison.
538 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
539 }
540
541 return Cmp;
542}
543
544/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
545/// the given operands.
546SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
547 SDValue &AVRcc, SelectionDAG &DAG,
548 SDLoc DL) const {
549 SDValue Cmp;
550 EVT VT = LHS.getValueType();
551 bool UseTest = false;
552
553 switch (CC) {
554 default:
555 break;
556 case ISD::SETLE: {
557 // Swap operands and reverse the branching condition.
558 std::swap(LHS, RHS);
559 CC = ISD::SETGE;
560 break;
561 }
562 case ISD::SETGT: {
563 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
564 switch (C->getSExtValue()) {
565 case -1: {
566 // When doing lhs > -1 use a tst instruction on the top part of lhs
567 // and use brpl instead of using a chain of cp/cpc.
568 UseTest = true;
569 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
570 break;
571 }
572 case 0: {
573 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
574 // __zero_reg__ in lhs.
575 RHS = LHS;
576 LHS = DAG.getConstant(0, DL, VT);
577 CC = ISD::SETLT;
578 break;
579 }
580 default: {
581 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
582 // us to fold the constant into the cmp instruction.
583 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
584 CC = ISD::SETGE;
585 break;
586 }
587 }
588 break;
589 }
590 // Swap operands and reverse the branching condition.
591 std::swap(LHS, RHS);
592 CC = ISD::SETLT;
593 break;
594 }
595 case ISD::SETLT: {
596 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
597 switch (C->getSExtValue()) {
598 case 1: {
599 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
600 // __zero_reg__ in lhs.
601 RHS = LHS;
602 LHS = DAG.getConstant(0, DL, VT);
603 CC = ISD::SETGE;
604 break;
605 }
606 case 0: {
607 // When doing lhs < 0 use a tst instruction on the top part of lhs
608 // and use brmi instead of using a chain of cp/cpc.
609 UseTest = true;
610 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
611 break;
612 }
613 }
614 }
615 break;
616 }
617 case ISD::SETULE: {
618 // Swap operands and reverse the branching condition.
619 std::swap(LHS, RHS);
620 CC = ISD::SETUGE;
621 break;
622 }
623 case ISD::SETUGT: {
624 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
625 // fold the constant into the cmp instruction.
626 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
627 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
628 CC = ISD::SETUGE;
629 break;
630 }
631 // Swap operands and reverse the branching condition.
632 std::swap(LHS, RHS);
633 CC = ISD::SETULT;
634 break;
635 }
636 }
637
638 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
639 // using the default and/or/xor expansion code which is much longer.
640 if (VT == MVT::i32) {
641 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
642 DAG.getIntPtrConstant(0, DL));
643 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
644 DAG.getIntPtrConstant(1, DL));
645 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
646 DAG.getIntPtrConstant(0, DL));
647 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
648 DAG.getIntPtrConstant(1, DL));
649
650 if (UseTest) {
651 // When using tst we only care about the highest part.
652 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
653 DAG.getIntPtrConstant(1, DL));
654 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
655 } else {
656 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
657 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
658 }
659 } else if (VT == MVT::i64) {
660 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
661 DAG.getIntPtrConstant(0, DL));
662 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
663 DAG.getIntPtrConstant(1, DL));
664
665 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
666 DAG.getIntPtrConstant(0, DL));
667 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
668 DAG.getIntPtrConstant(1, DL));
669 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
670 DAG.getIntPtrConstant(0, DL));
671 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
672 DAG.getIntPtrConstant(1, DL));
673
674 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
675 DAG.getIntPtrConstant(0, DL));
676 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
677 DAG.getIntPtrConstant(1, DL));
678
679 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
680 DAG.getIntPtrConstant(0, DL));
681 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
682 DAG.getIntPtrConstant(1, DL));
683 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
684 DAG.getIntPtrConstant(0, DL));
685 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
686 DAG.getIntPtrConstant(1, DL));
687
688 if (UseTest) {
689 // When using tst we only care about the highest part.
690 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
691 DAG.getIntPtrConstant(1, DL));
692 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
693 } else {
694 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
695 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
696 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
697 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
698 }
699 } else if (VT == MVT::i8 || VT == MVT::i16) {
700 if (UseTest) {
701 // When using tst we only care about the highest part.
702 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
703 (VT == MVT::i8)
704 ? LHS
705 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
706 LHS, DAG.getIntPtrConstant(1, DL)));
707 } else {
708 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
709 }
710 } else {
711 llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 711)
;
712 }
713
714 // When using a test instruction AVRcc is already set.
715 if (!UseTest) {
716 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
717 }
718
719 return Cmp;
720}
721
722SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
723 SDValue Chain = Op.getOperand(0);
724 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
725 SDValue LHS = Op.getOperand(2);
726 SDValue RHS = Op.getOperand(3);
727 SDValue Dest = Op.getOperand(4);
728 SDLoc dl(Op);
729
730 SDValue TargetCC;
731 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
732
733 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
734 Cmp);
735}
736
737SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
738 SDValue LHS = Op.getOperand(0);
739 SDValue RHS = Op.getOperand(1);
740 SDValue TrueV = Op.getOperand(2);
741 SDValue FalseV = Op.getOperand(3);
742 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
743 SDLoc dl(Op);
744
745 SDValue TargetCC;
746 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
747
748 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
749 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
750
751 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
752}
753
754SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
755 SDValue LHS = Op.getOperand(0);
756 SDValue RHS = Op.getOperand(1);
757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
758 SDLoc DL(Op);
759
760 SDValue TargetCC;
761 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
762
763 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
764 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
765 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
766 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
767
768 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
769}
770
771SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
772 const MachineFunction &MF = DAG.getMachineFunction();
773 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
774 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
775 auto DL = DAG.getDataLayout();
776 SDLoc dl(Op);
777
778 // Vastart just stores the address of the VarArgsFrameIndex slot into the
779 // memory location argument.
780 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
781
782 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
783 MachinePointerInfo(SV));
784}
785
786SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
787 switch (Op.getOpcode()) {
788 default:
789 llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 789)
;
790 case ISD::SHL:
791 case ISD::SRA:
792 case ISD::SRL:
793 case ISD::ROTL:
794 case ISD::ROTR:
795 return LowerShifts(Op, DAG);
796 case ISD::GlobalAddress:
797 return LowerGlobalAddress(Op, DAG);
798 case ISD::BlockAddress:
799 return LowerBlockAddress(Op, DAG);
800 case ISD::BR_CC:
801 return LowerBR_CC(Op, DAG);
802 case ISD::SELECT_CC:
803 return LowerSELECT_CC(Op, DAG);
804 case ISD::SETCC:
805 return LowerSETCC(Op, DAG);
806 case ISD::VASTART:
807 return LowerVASTART(Op, DAG);
808 case ISD::SDIVREM:
809 case ISD::UDIVREM:
810 return LowerDivRem(Op, DAG);
811 }
812
813 return SDValue();
814}
815
816/// Replace a node with an illegal result type
817/// with a new node built out of custom code.
818void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
819 SmallVectorImpl<SDValue> &Results,
820 SelectionDAG &DAG) const {
821 SDLoc DL(N);
822
823 switch (N->getOpcode()) {
824 case ISD::ADD: {
825 // Convert add (x, imm) into sub (x, -imm).
826 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
827 SDValue Sub = DAG.getNode(
828 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
829 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
830 Results.push_back(Sub);
831 }
832 break;
833 }
834 default: {
835 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
836
837 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
838 Results.push_back(Res.getValue(I));
839
840 break;
841 }
842 }
843}
844
845/// Return true if the addressing mode represented
846/// by AM is legal for this target, for a load/store of the specified type.
847bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
848 const AddrMode &AM, Type *Ty,
849 unsigned AS, Instruction *I) const {
850 int64_t Offs = AM.BaseOffs;
851
852 // Allow absolute addresses.
853 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
854 return true;
855 }
856
857 // Flash memory instructions only allow zero offsets.
858 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
859 return false;
860 }
861
862 // Allow reg+<6bit> offset.
863 if (Offs < 0)
864 Offs = -Offs;
865 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
866 return true;
867 }
868
869 return false;
870}
871
872/// Returns true by value, base pointer and
873/// offset pointer and addressing mode by reference if the node's address
874/// can be legally represented as pre-indexed load / store address.
875bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
876 SDValue &Offset,
877 ISD::MemIndexedMode &AM,
878 SelectionDAG &DAG) const {
879 EVT VT;
880 const SDNode *Op;
881 SDLoc DL(N);
882
883 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
884 VT = LD->getMemoryVT();
885 Op = LD->getBasePtr().getNode();
886 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
887 return false;
888 if (AVR::isProgramMemoryAccess(LD)) {
889 return false;
890 }
891 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
892 VT = ST->getMemoryVT();
893 Op = ST->getBasePtr().getNode();
894 if (AVR::isProgramMemoryAccess(ST)) {
895 return false;
896 }
897 } else {
898 return false;
899 }
900
901 if (VT != MVT::i8 && VT != MVT::i16) {
902 return false;
903 }
904
905 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
906 return false;
907 }
908
909 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
910 int RHSC = RHS->getSExtValue();
911 if (Op->getOpcode() == ISD::SUB)
912 RHSC = -RHSC;
913
914 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
915 return false;
916 }
917
918 Base = Op->getOperand(0);
919 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
920 AM = ISD::PRE_DEC;
921
922 return true;
923 }
924
925 return false;
926}
927
928/// Returns true by value, base pointer and
929/// offset pointer and addressing mode by reference if this node can be
930/// combined with a load / store to form a post-indexed load / store.
931bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
932 SDValue &Base,
933 SDValue &Offset,
934 ISD::MemIndexedMode &AM,
935 SelectionDAG &DAG) const {
936 EVT VT;
937 SDLoc DL(N);
938
939 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
940 VT = LD->getMemoryVT();
941 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
942 return false;
943 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
944 VT = ST->getMemoryVT();
945 if (AVR::isProgramMemoryAccess(ST)) {
946 return false;
947 }
948 } else {
949 return false;
950 }
951
952 if (VT != MVT::i8 && VT != MVT::i16) {
953 return false;
954 }
955
956 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
957 return false;
958 }
959
960 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
961 int RHSC = RHS->getSExtValue();
962 if (Op->getOpcode() == ISD::SUB)
963 RHSC = -RHSC;
964 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
965 return false;
966 }
967
968 Base = Op->getOperand(0);
969 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
970 AM = ISD::POST_INC;
971
972 return true;
973 }
974
975 return false;
976}
977
978bool AVRTargetLowering::isOffsetFoldingLegal(
979 const GlobalAddressSDNode *GA) const {
980 return true;
981}
982
983//===----------------------------------------------------------------------===//
984// Formal Arguments Calling Convention Implementation
985//===----------------------------------------------------------------------===//
986
987#include "AVRGenCallingConv.inc"
988
989/// Registers for calling conventions, ordered in reverse as required by ABI.
990/// Both arrays must be of the same length.
991static const MCPhysReg RegList8[] = {
992 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
993 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
994 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
995static const MCPhysReg RegList16[] = {
996 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
997 AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
998 AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
999 AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
1000 AVR::R10R9, AVR::R9R8};
1001
1002static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
1003 "8-bit and 16-bit register arrays must be of equal length");
1004
1005/// Analyze incoming and outgoing function arguments. We need custom C++ code
1006/// to handle special constraints in the ABI.
1007/// In addition, all pieces of a certain argument have to be passed either
1008/// using registers or the stack but never mixing both.
1009template <typename ArgT>
1010static void
1011analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
1012 const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
1013 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
1014 unsigned NumArgs = Args.size();
1015 // This is the index of the last used register, in RegList*.
1016 // -1 means R26 (R26 is never actually used in CC).
1017 int RegLastIdx = -1;
1018 // Once a value is passed to the stack it will always be used
1019 bool UseStack = false;
1020 for (unsigned i = 0; i != NumArgs;) {
1021 MVT VT = Args[i].VT;
1022 // We have to count the number of bytes for each function argument, that is
1023 // those Args with the same OrigArgIndex. This is important in case the
1024 // function takes an aggregate type.
1025 // Current argument will be between [i..j).
1026 unsigned ArgIndex = Args[i].OrigArgIndex;
1027 unsigned TotalBytes = VT.getStoreSize();
1028 unsigned j = i + 1;
1029 for (; j != NumArgs; ++j) {
1030 if (Args[j].OrigArgIndex != ArgIndex)
1031 break;
1032 TotalBytes += Args[j].VT.getStoreSize();
1033 }
1034 // Round up to even number of bytes.
1035 TotalBytes = alignTo(TotalBytes, 2);
1036 // Skip zero sized arguments
1037 if (TotalBytes == 0)
1038 continue;
1039 // The index of the first register to be used
1040 unsigned RegIdx = RegLastIdx + TotalBytes;
1041 RegLastIdx = RegIdx;
1042 // If there are not enough registers, use the stack
1043 if (RegIdx >= array_lengthof(RegList8)) {
1044 UseStack = true;
1045 }
1046 for (; i != j; ++i) {
1047 MVT VT = Args[i].VT;
1048
1049 if (UseStack) {
1050 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1051 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1052 TD->getABITypeAlign(evt));
1053 CCInfo.addLoc(
1054 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
1055 } else {
1056 unsigned Reg;
1057 if (VT == MVT::i8) {
1058 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1059 } else if (VT == MVT::i16) {
1060 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1061 } else {
1062 llvm_unreachable(::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1063)
1063 "calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1063)
;
1064 }
1065 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1065, __PRETTY_FUNCTION__))
;
1066 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1067 // Registers inside a particular argument are sorted in increasing order
1068 // (remember the array is reversed).
1069 RegIdx -= VT.getStoreSize();
1070 }
1071 }
1072 }
1073}
1074
1075/// Count the total number of bytes needed to pass or return these arguments.
1076template <typename ArgT>
1077static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
1078 unsigned TotalBytes = 0;
1079
1080 for (const ArgT& Arg : Args) {
1081 TotalBytes += Arg.VT.getStoreSize();
1082 }
1083 return TotalBytes;
1084}
1085
1086/// Analyze incoming and outgoing value of returning from a function.
1087/// The algorithm is similar to analyzeArguments, but there can only be
1088/// one value, possibly an aggregate, and it is limited to 8 bytes.
1089template <typename ArgT>
1090static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
1091 CCState &CCInfo) {
1092 unsigned NumArgs = Args.size();
1093 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1094 // CanLowerReturn() guarantees this assertion.
1095 assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered")((TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"
) ? static_cast<void> (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1095, __PRETTY_FUNCTION__))
;
4
'?' condition is true
1096
1097 // GCC-ABI says that the size is rounded up to the next even number,
1098 // but actually once it is more than 4 it will always round up to 8.
1099 if (TotalBytes
4.1
'TotalBytes' is <= 4
4.1
'TotalBytes' is <= 4
> 4) {
5
Taking false branch
1100 TotalBytes = 8;
1101 } else {
1102 TotalBytes = alignTo(TotalBytes, 2);
1103 }
1104
1105 // The index of the first register to use.
1106 int RegIdx = TotalBytes - 1;
6
'RegIdx' initialized to -1
1107 for (unsigned i = 0; i != NumArgs; ++i) {
7
Assuming 'i' is not equal to 'NumArgs'
8
Loop condition is true. Entering loop body
1108 MVT VT = Args[i].VT;
1109 unsigned Reg;
1110 if (VT == MVT::i8) {
9
Calling 'MVT::operator=='
12
Returning from 'MVT::operator=='
13
Taking true branch
1111 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
14
1st function call argument is an uninitialized value
1112 } else if (VT == MVT::i16) {
1113 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1114 } else {
1115 llvm_unreachable("calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1115)
;
1116 }
1117 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1117, __PRETTY_FUNCTION__))
;
1118 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1119 // Registers sort in increasing order
1120 RegIdx -= VT.getStoreSize();
1121 }
1122}
1123
1124SDValue AVRTargetLowering::LowerFormalArguments(
1125 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1126 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1127 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1128 MachineFunction &MF = DAG.getMachineFunction();
1129 MachineFrameInfo &MFI = MF.getFrameInfo();
1130 auto DL = DAG.getDataLayout();
1131
1132 // Assign locations to all of the incoming arguments.
1133 SmallVector<CCValAssign, 16> ArgLocs;
1134 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1135 *DAG.getContext());
1136
1137 // Variadic functions do not need all the analysis below.
1138 if (isVarArg) {
1139 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1140 } else {
1141 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1142 }
1143
1144 SDValue ArgValue;
1145 for (CCValAssign &VA : ArgLocs) {
1146
1147 // Arguments stored on registers.
1148 if (VA.isRegLoc()) {
1149 EVT RegVT = VA.getLocVT();
1150 const TargetRegisterClass *RC;
1151 if (RegVT == MVT::i8) {
1152 RC = &AVR::GPR8RegClass;
1153 } else if (RegVT == MVT::i16) {
1154 RC = &AVR::DREGSRegClass;
1155 } else {
1156 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1156)
;
1157 }
1158
1159 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1160 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1161
1162 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1163 // following code will handle zexts or sexts generated by other
1164 // front ends. Otherwise:
1165 // If this is an 8 bit value, it is really passed promoted
1166 // to 16 bits. Insert an assert[sz]ext to capture this, then
1167 // truncate to the right size.
1168 switch (VA.getLocInfo()) {
1169 default:
1170 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1170)
;
1171 case CCValAssign::Full:
1172 break;
1173 case CCValAssign::BCvt:
1174 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1175 break;
1176 case CCValAssign::SExt:
1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1178 DAG.getValueType(VA.getValVT()));
1179 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1180 break;
1181 case CCValAssign::ZExt:
1182 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1183 DAG.getValueType(VA.getValVT()));
1184 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1185 break;
1186 }
1187
1188 InVals.push_back(ArgValue);
1189 } else {
1190 // Sanity check.
1191 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1191, __PRETTY_FUNCTION__))
;
1192
1193 EVT LocVT = VA.getLocVT();
1194
1195 // Create the frame index object for this incoming parameter.
1196 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1197 VA.getLocMemOffset(), true);
1198
1199 // Create the SelectionDAG nodes corresponding to a load
1200 // from this parameter.
1201 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1202 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1203 MachinePointerInfo::getFixedStack(MF, FI)));
1204 }
1205 }
1206
1207 // If the function takes variable number of arguments, make a frame index for
1208 // the start of the first vararg value... for expansion of llvm.va_start.
1209 if (isVarArg) {
1210 unsigned StackSize = CCInfo.getNextStackOffset();
1211 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1212
1213 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1214 }
1215
1216 return Chain;
1217}
1218
1219//===----------------------------------------------------------------------===//
1220// Call Calling Convention Implementation
1221//===----------------------------------------------------------------------===//
1222
1223SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1224 SmallVectorImpl<SDValue> &InVals) const {
1225 SelectionDAG &DAG = CLI.DAG;
1226 SDLoc &DL = CLI.DL;
1227 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1228 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1229 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1230 SDValue Chain = CLI.Chain;
1231 SDValue Callee = CLI.Callee;
1232 bool &isTailCall = CLI.IsTailCall;
1233 CallingConv::ID CallConv = CLI.CallConv;
1234 bool isVarArg = CLI.IsVarArg;
1235
1236 MachineFunction &MF = DAG.getMachineFunction();
1237
1238 // AVR does not yet support tail call optimization.
1239 isTailCall = false;
1240
1241 // Analyze operands of the call, assigning locations to each operand.
1242 SmallVector<CCValAssign, 16> ArgLocs;
1243 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1244 *DAG.getContext());
1245
1246 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1247 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1248 // node so that legalize doesn't hack it.
1249 const Function *F = nullptr;
1250 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1251 const GlobalValue *GV = G->getGlobal();
1252
1253 F = cast<Function>(GV);
1254 Callee =
1255 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1256 } else if (const ExternalSymbolSDNode *ES =
1257 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1258 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1259 getPointerTy(DAG.getDataLayout()));
1260 }
1261
1262 // Variadic functions do not need all the analysis below.
1263 if (isVarArg) {
1264 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1265 } else {
1266 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1267 }
1268
1269 // Get a count of how many bytes are to be pushed on the stack.
1270 unsigned NumBytes = CCInfo.getNextStackOffset();
1271
1272 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1273
1274 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1275
1276 // First, walk the register assignments, inserting copies.
1277 unsigned AI, AE;
1278 bool HasStackArgs = false;
1279 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1280 CCValAssign &VA = ArgLocs[AI];
1281 EVT RegVT = VA.getLocVT();
1282 SDValue Arg = OutVals[AI];
1283
1284 // Promote the value if needed. With Clang this should not happen.
1285 switch (VA.getLocInfo()) {
1286 default:
1287 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1287)
;
1288 case CCValAssign::Full:
1289 break;
1290 case CCValAssign::SExt:
1291 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1292 break;
1293 case CCValAssign::ZExt:
1294 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1295 break;
1296 case CCValAssign::AExt:
1297 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1298 break;
1299 case CCValAssign::BCvt:
1300 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1301 break;
1302 }
1303
1304 // Stop when we encounter a stack argument, we need to process them
1305 // in reverse order in the loop below.
1306 if (VA.isMemLoc()) {
1307 HasStackArgs = true;
1308 break;
1309 }
1310
1311 // Arguments that can be passed on registers must be kept in the RegsToPass
1312 // vector.
1313 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1314 }
1315
1316 // Second, stack arguments have to walked in reverse order by inserting
1317 // chained stores, this ensures their order is not changed by the scheduler
1318 // and that the push instruction sequence generated is correct, otherwise they
1319 // can be freely intermixed.
1320 if (HasStackArgs) {
1321 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1322 unsigned Loc = AI - 1;
1323 CCValAssign &VA = ArgLocs[Loc];
1324 SDValue Arg = OutVals[Loc];
1325
1326 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1326, __PRETTY_FUNCTION__))
;
1327
1328 // SP points to one stack slot further so add one to adjust it.
1329 SDValue PtrOff = DAG.getNode(
1330 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1331 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1332 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1333
1334 Chain =
1335 DAG.getStore(Chain, DL, Arg, PtrOff,
1336 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()));
1337 }
1338 }
1339
1340 // Build a sequence of copy-to-reg nodes chained together with token chain and
1341 // flag operands which copy the outgoing args into registers. The InFlag in
1342 // necessary since all emited instructions must be stuck together.
1343 SDValue InFlag;
1344 for (auto Reg : RegsToPass) {
1345 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1346 InFlag = Chain.getValue(1);
1347 }
1348
1349 // Returns a chain & a flag for retval copy to use.
1350 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1351 SmallVector<SDValue, 8> Ops;
1352 Ops.push_back(Chain);
1353 Ops.push_back(Callee);
1354
1355 // Add argument registers to the end of the list so that they are known live
1356 // into the call.
1357 for (auto Reg : RegsToPass) {
1358 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1359 }
1360
1361 // Add a register mask operand representing the call-preserved registers.
1362 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1363 const uint32_t *Mask =
1364 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1365 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1365, __PRETTY_FUNCTION__))
;
1366 Ops.push_back(DAG.getRegisterMask(Mask));
1367
1368 if (InFlag.getNode()) {
1369 Ops.push_back(InFlag);
1370 }
1371
1372 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1373 InFlag = Chain.getValue(1);
1374
1375 // Create the CALLSEQ_END node.
1376 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1377 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1378
1379 if (!Ins.empty()) {
1380 InFlag = Chain.getValue(1);
1381 }
1382
1383 // Handle result values, copying them out of physregs into vregs that we
1384 // return.
1385 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1386 InVals);
1387}
1388
1389/// Lower the result values of a call into the
1390/// appropriate copies out of appropriate physical registers.
1391///
1392SDValue AVRTargetLowering::LowerCallResult(
1393 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1394 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1395 SmallVectorImpl<SDValue> &InVals) const {
1396
1397 // Assign locations to each value returned by this call.
1398 SmallVector<CCValAssign, 16> RVLocs;
1399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1400 *DAG.getContext());
1401
1402 // Handle runtime calling convs.
1403 if (CallConv == CallingConv::AVR_BUILTIN) {
1404 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1405 } else {
1406 analyzeReturnValues(Ins, CCInfo);
1407 }
1408
1409 // Copy all of the result registers out of their specified physreg.
1410 for (CCValAssign const &RVLoc : RVLocs) {
1411 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1412 InFlag)
1413 .getValue(1);
1414 InFlag = Chain.getValue(2);
1415 InVals.push_back(Chain.getValue(0));
1416 }
1417
1418 return Chain;
1419}
1420
1421//===----------------------------------------------------------------------===//
1422// Return Value Calling Convention Implementation
1423//===----------------------------------------------------------------------===//
1424
1425bool AVRTargetLowering::CanLowerReturn(
1426 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1427 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1428 if (CallConv == CallingConv::AVR_BUILTIN) {
1429 SmallVector<CCValAssign, 16> RVLocs;
1430 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1431 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1432 }
1433
1434 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1435 return TotalBytes <= 8;
1436}
1437
1438SDValue
1439AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1440 bool isVarArg,
1441 const SmallVectorImpl<ISD::OutputArg> &Outs,
1442 const SmallVectorImpl<SDValue> &OutVals,
1443 const SDLoc &dl, SelectionDAG &DAG) const {
1444 // CCValAssign - represent the assignment of the return value to locations.
1445 SmallVector<CCValAssign, 16> RVLocs;
1446
1447 // CCState - Info about the registers and stack slot.
1448 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1449 *DAG.getContext());
1450
1451 MachineFunction &MF = DAG.getMachineFunction();
1452
1453 // Analyze return values.
1454 if (CallConv == CallingConv::AVR_BUILTIN) {
1
Assuming 'CallConv' is not equal to AVR_BUILTIN
2
Taking false branch
1455 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1456 } else {
1457 analyzeReturnValues(Outs, CCInfo);
3
Calling 'analyzeReturnValues<llvm::ISD::OutputArg>'
1458 }
1459
1460 SDValue Flag;
1461 SmallVector<SDValue, 4> RetOps(1, Chain);
1462 // Copy the result values into the output registers.
1463 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1464 CCValAssign &VA = RVLocs[i];
1465 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1465, __PRETTY_FUNCTION__))
;
1466
1467 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1468
1469 // Guarantee that all emitted copies are stuck together with flags.
1470 Flag = Chain.getValue(1);
1471 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1472 }
1473
1474 // Don't emit the ret/reti instruction when the naked attribute is present in
1475 // the function being compiled.
1476 if (MF.getFunction().getAttributes().hasAttribute(
1477 AttributeList::FunctionIndex, Attribute::Naked)) {
1478 return Chain;
1479 }
1480
1481 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1482
1483 unsigned RetOpc =
1484 AFI->isInterruptOrSignalHandler()
1485 ? AVRISD::RETI_FLAG
1486 : AVRISD::RET_FLAG;
1487
1488 RetOps[0] = Chain; // Update chain.
1489
1490 if (Flag.getNode()) {
1491 RetOps.push_back(Flag);
1492 }
1493
1494 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1495}
1496
1497//===----------------------------------------------------------------------===//
1498// Custom Inserters
1499//===----------------------------------------------------------------------===//
1500
1501MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1502 MachineBasicBlock *BB) const {
1503 unsigned Opc;
1504 const TargetRegisterClass *RC;
1505 bool HasRepeatedOperand = false;
1506 MachineFunction *F = BB->getParent();
1507 MachineRegisterInfo &RI = F->getRegInfo();
1508 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1509 DebugLoc dl = MI.getDebugLoc();
1510
1511 switch (MI.getOpcode()) {
1512 default:
1513 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1513)
;
1514 case AVR::Lsl8:
1515 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1516 RC = &AVR::GPR8RegClass;
1517 HasRepeatedOperand = true;
1518 break;
1519 case AVR::Lsl16:
1520 Opc = AVR::LSLWRd;
1521 RC = &AVR::DREGSRegClass;
1522 break;
1523 case AVR::Asr8:
1524 Opc = AVR::ASRRd;
1525 RC = &AVR::GPR8RegClass;
1526 break;
1527 case AVR::Asr16:
1528 Opc = AVR::ASRWRd;
1529 RC = &AVR::DREGSRegClass;
1530 break;
1531 case AVR::Lsr8:
1532 Opc = AVR::LSRRd;
1533 RC = &AVR::GPR8RegClass;
1534 break;
1535 case AVR::Lsr16:
1536 Opc = AVR::LSRWRd;
1537 RC = &AVR::DREGSRegClass;
1538 break;
1539 case AVR::Rol8:
1540 Opc = AVR::ROLBRd;
1541 RC = &AVR::GPR8RegClass;
1542 break;
1543 case AVR::Rol16:
1544 Opc = AVR::ROLWRd;
1545 RC = &AVR::DREGSRegClass;
1546 break;
1547 case AVR::Ror8:
1548 Opc = AVR::RORBRd;
1549 RC = &AVR::GPR8RegClass;
1550 break;
1551 case AVR::Ror16:
1552 Opc = AVR::RORWRd;
1553 RC = &AVR::DREGSRegClass;
1554 break;
1555 }
1556
1557 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1558
1559 MachineFunction::iterator I;
1560 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1561 if (I != F->end()) ++I;
1562
1563 // Create loop block.
1564 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1565 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1566 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1567
1568 F->insert(I, LoopBB);
1569 F->insert(I, CheckBB);
1570 F->insert(I, RemBB);
1571
1572 // Update machine-CFG edges by transferring all successors of the current
1573 // block to the block containing instructions after shift.
1574 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1575 BB->end());
1576 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1577
1578 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1579 BB->addSuccessor(CheckBB);
1580 LoopBB->addSuccessor(CheckBB);
1581 CheckBB->addSuccessor(LoopBB);
1582 CheckBB->addSuccessor(RemBB);
1583
1584 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1585 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1586 Register ShiftReg = RI.createVirtualRegister(RC);
1587 Register ShiftReg2 = RI.createVirtualRegister(RC);
1588 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1589 Register SrcReg = MI.getOperand(1).getReg();
1590 Register DstReg = MI.getOperand(0).getReg();
1591
1592 // BB:
1593 // rjmp CheckBB
1594 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1595
1596 // LoopBB:
1597 // ShiftReg2 = shift ShiftReg
1598 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1599 if (HasRepeatedOperand)
1600 ShiftMI.addReg(ShiftReg);
1601
1602 // CheckBB:
1603 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1604 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1605 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1606 // ShiftAmt2 = ShiftAmt - 1;
1607 // if (ShiftAmt2 >= 0) goto LoopBB;
1608 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1609 .addReg(SrcReg)
1610 .addMBB(BB)
1611 .addReg(ShiftReg2)
1612 .addMBB(LoopBB);
1613 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1614 .addReg(ShiftAmtSrcReg)
1615 .addMBB(BB)
1616 .addReg(ShiftAmtReg2)
1617 .addMBB(LoopBB);
1618 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1619 .addReg(SrcReg)
1620 .addMBB(BB)
1621 .addReg(ShiftReg2)
1622 .addMBB(LoopBB);
1623
1624 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2)
1625 .addReg(ShiftAmtReg);
1626 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1627
1628 MI.eraseFromParent(); // The pseudo instruction is gone now.
1629 return RemBB;
1630}
1631
1632static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
1633 if (I->getOpcode() == AVR::COPY) {
1634 Register SrcReg = I->getOperand(1).getReg();
1635 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1636 }
1637
1638 return false;
1639}
1640
1641// The mul instructions wreak havock on our zero_reg R1. We need to clear it
1642// after the result has been evacuated. This is probably not the best way to do
1643// it, but it works for now.
1644MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1645 MachineBasicBlock *BB) const {
1646 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1647 MachineBasicBlock::iterator I(MI);
1648 ++I; // in any case insert *after* the mul instruction
1649 if (isCopyMulResult(I))
1650 ++I;
1651 if (isCopyMulResult(I))
1652 ++I;
1653 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1654 .addReg(AVR::R1)
1655 .addReg(AVR::R1);
1656 return BB;
1657}
1658
1659MachineBasicBlock *
1660AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1661 MachineBasicBlock *MBB) const {
1662 int Opc = MI.getOpcode();
1663
1664 // Pseudo shift instructions with a non constant shift amount are expanded
1665 // into a loop.
1666 switch (Opc) {
1667 case AVR::Lsl8:
1668 case AVR::Lsl16:
1669 case AVR::Lsr8:
1670 case AVR::Lsr16:
1671 case AVR::Rol8:
1672 case AVR::Rol16:
1673 case AVR::Ror8:
1674 case AVR::Ror16:
1675 case AVR::Asr8:
1676 case AVR::Asr16:
1677 return insertShift(MI, MBB);
1678 case AVR::MULRdRr:
1679 case AVR::MULSRdRr:
1680 return insertMul(MI, MBB);
1681 }
1682
1683 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1684, __PRETTY_FUNCTION__))
1684 "Unexpected instr type to insert")(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1684, __PRETTY_FUNCTION__))
;
1685
1686 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1687 ->getParent()
1688 ->getSubtarget()
1689 .getInstrInfo();
1690 DebugLoc dl = MI.getDebugLoc();
1691
1692 // To "insert" a SELECT instruction, we insert the diamond
1693 // control-flow pattern. The incoming instruction knows the
1694 // destination vreg to set, the condition code register to branch
1695 // on, the true/false values to select between, and a branch opcode
1696 // to use.
1697
1698 MachineFunction *MF = MBB->getParent();
1699 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1700 MachineBasicBlock *FallThrough = MBB->getFallThrough();
1701
1702 // If the current basic block falls through to another basic block,
1703 // we must insert an unconditional branch to the fallthrough destination
1704 // if we are to insert basic blocks at the prior fallthrough point.
1705 if (FallThrough != nullptr) {
1706 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1707 }
1708
1709 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1710 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1711
1712 MachineFunction::iterator I;
1713 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1714 if (I != MF->end()) ++I;
1715 MF->insert(I, trueMBB);
1716 MF->insert(I, falseMBB);
1717
1718 // Transfer remaining instructions and all successors of the current
1719 // block to the block which will contain the Phi node for the
1720 // select.
1721 trueMBB->splice(trueMBB->begin(), MBB,
1722 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1723 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1724
1725 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1726 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1727 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1728 MBB->addSuccessor(falseMBB);
1729 MBB->addSuccessor(trueMBB);
1730
1731 // Unconditionally flow back to the true block
1732 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1733 falseMBB->addSuccessor(trueMBB);
1734
1735 // Set up the Phi node to determine where we came from
1736 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1737 .addReg(MI.getOperand(1).getReg())
1738 .addMBB(MBB)
1739 .addReg(MI.getOperand(2).getReg())
1740 .addMBB(falseMBB) ;
1741
1742 MI.eraseFromParent(); // The pseudo instruction is gone now.
1743 return trueMBB;
1744}
1745
1746//===----------------------------------------------------------------------===//
1747// Inline Asm Support
1748//===----------------------------------------------------------------------===//
1749
1750AVRTargetLowering::ConstraintType
1751AVRTargetLowering::getConstraintType(StringRef Constraint) const {
1752 if (Constraint.size() == 1) {
1753 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1754 switch (Constraint[0]) {
1755 default:
1756 break;
1757 case 'a': // Simple upper registers
1758 case 'b': // Base pointer registers pairs
1759 case 'd': // Upper register
1760 case 'l': // Lower registers
1761 case 'e': // Pointer register pairs
1762 case 'q': // Stack pointer register
1763 case 'r': // Any register
1764 case 'w': // Special upper register pairs
1765 return C_RegisterClass;
1766 case 't': // Temporary register
1767 case 'x': case 'X': // Pointer register pair X
1768 case 'y': case 'Y': // Pointer register pair Y
1769 case 'z': case 'Z': // Pointer register pair Z
1770 return C_Register;
1771 case 'Q': // A memory address based on Y or Z pointer with displacement.
1772 return C_Memory;
1773 case 'G': // Floating point constant
1774 case 'I': // 6-bit positive integer constant
1775 case 'J': // 6-bit negative integer constant
1776 case 'K': // Integer constant (Range: 2)
1777 case 'L': // Integer constant (Range: 0)
1778 case 'M': // 8-bit integer constant
1779 case 'N': // Integer constant (Range: -1)
1780 case 'O': // Integer constant (Range: 8, 16, 24)
1781 case 'P': // Integer constant (Range: 1)
1782 case 'R': // Integer constant (Range: -6 to 5)x
1783 return C_Immediate;
1784 }
1785 }
1786
1787 return TargetLowering::getConstraintType(Constraint);
1788}
1789
1790unsigned
1791AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
1792 // Not sure if this is actually the right thing to do, but we got to do
1793 // *something* [agnat]
1794 switch (ConstraintCode[0]) {
1795 case 'Q':
1796 return InlineAsm::Constraint_Q;
1797 }
1798 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1799}
1800
1801AVRTargetLowering::ConstraintWeight
1802AVRTargetLowering::getSingleConstraintMatchWeight(
1803 AsmOperandInfo &info, const char *constraint) const {
1804 ConstraintWeight weight = CW_Invalid;
1805 Value *CallOperandVal = info.CallOperandVal;
1806
1807 // If we don't have a value, we can't do a match,
1808 // but allow it at the lowest weight.
1809 // (this behaviour has been copied from the ARM backend)
1810 if (!CallOperandVal) {
1811 return CW_Default;
1812 }
1813
1814 // Look at the constraint type.
1815 switch (*constraint) {
1816 default:
1817 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1818 break;
1819 case 'd':
1820 case 'r':
1821 case 'l':
1822 weight = CW_Register;
1823 break;
1824 case 'a':
1825 case 'b':
1826 case 'e':
1827 case 'q':
1828 case 't':
1829 case 'w':
1830 case 'x': case 'X':
1831 case 'y': case 'Y':
1832 case 'z': case 'Z':
1833 weight = CW_SpecificReg;
1834 break;
1835 case 'G':
1836 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1837 if (C->isZero()) {
1838 weight = CW_Constant;
1839 }
1840 }
1841 break;
1842 case 'I':
1843 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1844 if (isUInt<6>(C->getZExtValue())) {
1845 weight = CW_Constant;
1846 }
1847 }
1848 break;
1849 case 'J':
1850 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1851 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1852 weight = CW_Constant;
1853 }
1854 }
1855 break;
1856 case 'K':
1857 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1858 if (C->getZExtValue() == 2) {
1859 weight = CW_Constant;
1860 }
1861 }
1862 break;
1863 case 'L':
1864 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1865 if (C->getZExtValue() == 0) {
1866 weight = CW_Constant;
1867 }
1868 }
1869 break;
1870 case 'M':
1871 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1872 if (isUInt<8>(C->getZExtValue())) {
1873 weight = CW_Constant;
1874 }
1875 }
1876 break;
1877 case 'N':
1878 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1879 if (C->getSExtValue() == -1) {
1880 weight = CW_Constant;
1881 }
1882 }
1883 break;
1884 case 'O':
1885 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1886 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1887 (C->getZExtValue() == 24)) {
1888 weight = CW_Constant;
1889 }
1890 }
1891 break;
1892 case 'P':
1893 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1894 if (C->getZExtValue() == 1) {
1895 weight = CW_Constant;
1896 }
1897 }
1898 break;
1899 case 'R':
1900 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1901 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1902 weight = CW_Constant;
1903 }
1904 }
1905 break;
1906 case 'Q':
1907 weight = CW_Memory;
1908 break;
1909 }
1910
1911 return weight;
1912}
1913
1914std::pair<unsigned, const TargetRegisterClass *>
1915AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1916 StringRef Constraint,
1917 MVT VT) const {
1918 // We only support i8 and i16.
1919 //
1920 //:FIXME: remove this assert for now since it gets sometimes executed
1921 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1922
1923 if (Constraint.size() == 1) {
1924 switch (Constraint[0]) {
1925 case 'a': // Simple upper registers r16..r23.
1926 return std::make_pair(0U, &AVR::LD8loRegClass);
1927 case 'b': // Base pointer registers: y, z.
1928 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1929 case 'd': // Upper registers r16..r31.
1930 return std::make_pair(0U, &AVR::LD8RegClass);
1931 case 'l': // Lower registers r0..r15.
1932 return std::make_pair(0U, &AVR::GPR8loRegClass);
1933 case 'e': // Pointer register pairs: x, y, z.
1934 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1935 case 'q': // Stack pointer register: SPH:SPL.
1936 return std::make_pair(0U, &AVR::GPRSPRegClass);
1937 case 'r': // Any register: r0..r31.
1938 if (VT == MVT::i8)
1939 return std::make_pair(0U, &AVR::GPR8RegClass);
1940
1941 return std::make_pair(0U, &AVR::DREGSRegClass);
1942 case 't': // Temporary register: r0.
1943 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1944 case 'w': // Special upper register pairs: r24, r26, r28, r30.
1945 return std::make_pair(0U, &AVR::IWREGSRegClass);
1946 case 'x': // Pointer register pair X: r27:r26.
1947 case 'X':
1948 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1949 case 'y': // Pointer register pair Y: r29:r28.
1950 case 'Y':
1951 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1952 case 'z': // Pointer register pair Z: r31:r30.
1953 case 'Z':
1954 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1955 default:
1956 break;
1957 }
1958 }
1959
1960 return TargetLowering::getRegForInlineAsmConstraint(
1961 Subtarget.getRegisterInfo(), Constraint, VT);
1962}
1963
1964void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1965 std::string &Constraint,
1966 std::vector<SDValue> &Ops,
1967 SelectionDAG &DAG) const {
1968 SDValue Result(0, 0);
1969 SDLoc DL(Op);
1970 EVT Ty = Op.getValueType();
1971
1972 // Currently only support length 1 constraints.
1973 if (Constraint.length() != 1) {
1974 return;
1975 }
1976
1977 char ConstraintLetter = Constraint[0];
1978 switch (ConstraintLetter) {
1979 default:
1980 break;
1981 // Deal with integers first:
1982 case 'I':
1983 case 'J':
1984 case 'K':
1985 case 'L':
1986 case 'M':
1987 case 'N':
1988 case 'O':
1989 case 'P':
1990 case 'R': {
1991 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1992 if (!C) {
1993 return;
1994 }
1995
1996 int64_t CVal64 = C->getSExtValue();
1997 uint64_t CUVal64 = C->getZExtValue();
1998 switch (ConstraintLetter) {
1999 case 'I': // 0..63
2000 if (!isUInt<6>(CUVal64))
2001 return;
2002 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2003 break;
2004 case 'J': // -63..0
2005 if (CVal64 < -63 || CVal64 > 0)
2006 return;
2007 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2008 break;
2009 case 'K': // 2
2010 if (CUVal64 != 2)
2011 return;
2012 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2013 break;
2014 case 'L': // 0
2015 if (CUVal64 != 0)
2016 return;
2017 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2018 break;
2019 case 'M': // 0..255
2020 if (!isUInt<8>(CUVal64))
2021 return;
2022 // i8 type may be printed as a negative number,
2023 // e.g. 254 would be printed as -2,
2024 // so we force it to i16 at least.
2025 if (Ty.getSimpleVT() == MVT::i8) {
2026 Ty = MVT::i16;
2027 }
2028 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2029 break;
2030 case 'N': // -1
2031 if (CVal64 != -1)
2032 return;
2033 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2034 break;
2035 case 'O': // 8, 16, 24
2036 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2037 return;
2038 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2039 break;
2040 case 'P': // 1
2041 if (CUVal64 != 1)
2042 return;
2043 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2044 break;
2045 case 'R': // -6..5
2046 if (CVal64 < -6 || CVal64 > 5)
2047 return;
2048 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2049 break;
2050 }
2051
2052 break;
2053 }
2054 case 'G':
2055 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2056 if (!FC || !FC->isZero())
2057 return;
2058 // Soften float to i8 0
2059 Result = DAG.getTargetConstant(0, DL, MVT::i8);
2060 break;
2061 }
2062
2063 if (Result.getNode()) {
2064 Ops.push_back(Result);
2065 return;
2066 }
2067
2068 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2069}
2070
2071Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2072 const MachineFunction &MF) const {
2073 Register Reg;
2074
2075 if (VT == LLT::scalar(8)) {
2076 Reg = StringSwitch<unsigned>(RegName)
2077 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
2078 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
2079 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
2080 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
2081 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
2082 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
2083 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
2084 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
2085 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2086 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2087 .Case("r30", AVR::R30).Case("r31", AVR::R31)
2088 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2089 .Default(0);
2090 } else {
2091 Reg = StringSwitch<unsigned>(RegName)
2092 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2093 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2094 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2095 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2096 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2097 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2098 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2099 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2100 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2101 .Default(0);
2102 }
2103
2104 if (Reg)
2105 return Reg;
2106
2107 report_fatal_error("Invalid register name global variable");
2108}
2109
2110} // end of namespace llvm

/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h

1//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of machine-level target independent types which
10// legal values in the code generator use.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H
15#define LLVM_SUPPORT_MACHINEVALUETYPE_H
16
17#include "llvm/ADT/iterator_range.h"
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Support/MathExtras.h"
20#include "llvm/Support/TypeSize.h"
21#include <cassert>
22
23namespace llvm {
24
25 class Type;
26
27 /// Machine Value Type. Every type that is supported natively by some
28 /// processor targeted by LLVM occurs here. This means that any legal value
29 /// type can be represented by an MVT.
30 class MVT {
31 public:
32 enum SimpleValueType : uint8_t {
33 // Simple value types that aren't explicitly part of this enumeration
34 // are considered extended value types.
35 INVALID_SIMPLE_VALUE_TYPE = 0,
36
37 // If you change this numbering, you must change the values in
38 // ValueTypes.td as well!
39 Other = 1, // This is a non-standard value
40 i1 = 2, // This is a 1 bit integer value
41 i8 = 3, // This is an 8 bit integer value
42 i16 = 4, // This is a 16 bit integer value
43 i32 = 5, // This is a 32 bit integer value
44 i64 = 6, // This is a 64 bit integer value
45 i128 = 7, // This is a 128 bit integer value
46
47 FIRST_INTEGER_VALUETYPE = i1,
48 LAST_INTEGER_VALUETYPE = i128,
49
50 bf16 = 8, // This is a 16 bit brain floating point value
51 f16 = 9, // This is a 16 bit floating point value
52 f32 = 10, // This is a 32 bit floating point value
53 f64 = 11, // This is a 64 bit floating point value
54 f80 = 12, // This is a 80 bit floating point value
55 f128 = 13, // This is a 128 bit floating point value
56 ppcf128 = 14, // This is a PPC 128-bit floating point value
57
58 FIRST_FP_VALUETYPE = bf16,
59 LAST_FP_VALUETYPE = ppcf128,
60
61 v1i1 = 15, // 1 x i1
62 v2i1 = 16, // 2 x i1
63 v4i1 = 17, // 4 x i1
64 v8i1 = 18, // 8 x i1
65 v16i1 = 19, // 16 x i1
66 v32i1 = 20, // 32 x i1
67 v64i1 = 21, // 64 x i1
68 v128i1 = 22, // 128 x i1
69 v256i1 = 23, // 256 x i1
70 v512i1 = 24, // 512 x i1
71 v1024i1 = 25, // 1024 x i1
72
73 v1i8 = 26, // 1 x i8
74 v2i8 = 27, // 2 x i8
75 v4i8 = 28, // 4 x i8
76 v8i8 = 29, // 8 x i8
77 v16i8 = 30, // 16 x i8
78 v32i8 = 31, // 32 x i8
79 v64i8 = 32, // 64 x i8
80 v128i8 = 33, // 128 x i8
81 v256i8 = 34, // 256 x i8
82
83 v1i16 = 35, // 1 x i16
84 v2i16 = 36, // 2 x i16
85 v3i16 = 37, // 3 x i16
86 v4i16 = 38, // 4 x i16
87 v8i16 = 39, // 8 x i16
88 v16i16 = 40, // 16 x i16
89 v32i16 = 41, // 32 x i16
90 v64i16 = 42, // 64 x i16
91 v128i16 = 43, // 128 x i16
92
93 v1i32 = 44, // 1 x i32
94 v2i32 = 45, // 2 x i32
95 v3i32 = 46, // 3 x i32
96 v4i32 = 47, // 4 x i32
97 v5i32 = 48, // 5 x i32
98 v8i32 = 49, // 8 x i32
99 v16i32 = 50, // 16 x i32
100 v32i32 = 51, // 32 x i32
101 v64i32 = 52, // 64 x i32
102 v128i32 = 53, // 128 x i32
103 v256i32 = 54, // 256 x i32
104 v512i32 = 55, // 512 x i32
105 v1024i32 = 56, // 1024 x i32
106 v2048i32 = 57, // 2048 x i32
107
108 v1i64 = 58, // 1 x i64
109 v2i64 = 59, // 2 x i64
110 v4i64 = 60, // 4 x i64
111 v8i64 = 61, // 8 x i64
112 v16i64 = 62, // 16 x i64
113 v32i64 = 63, // 32 x i64
114 v64i64 = 64, // 64 x i64
115 v128i64 = 65, // 128 x i64
116 v256i64 = 66, // 256 x i64
117
118 v1i128 = 67, // 1 x i128
119
120 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
121 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
122
123 v1f16 = 68, // 1 x f16
124 v2f16 = 69, // 2 x f16
125 v3f16 = 70, // 3 x f16
126 v4f16 = 71, // 4 x f16
127 v8f16 = 72, // 8 x f16
128 v16f16 = 73, // 16 x f16
129 v32f16 = 74, // 32 x f16
130 v64f16 = 75, // 64 x f16
131 v128f16 = 76, // 128 x f16
132
133 v2bf16 = 77, // 2 x bf16
134 v3bf16 = 78, // 3 x bf16
135 v4bf16 = 79, // 4 x bf16
136 v8bf16 = 80, // 8 x bf16
137 v16bf16 = 81, // 16 x bf16
138 v32bf16 = 82, // 32 x bf16
139 v64bf16 = 83, // 64 x bf16
140 v128bf16 = 84, // 128 x bf16
141
142 v1f32 = 85, // 1 x f32
143 v2f32 = 86, // 2 x f32
144 v3f32 = 87, // 3 x f32
145 v4f32 = 88, // 4 x f32
146 v5f32 = 89, // 5 x f32
147 v8f32 = 90, // 8 x f32
148 v16f32 = 91, // 16 x f32
149 v32f32 = 92, // 32 x f32
150 v64f32 = 93, // 64 x f32
151 v128f32 = 94, // 128 x f32
152 v256f32 = 95, // 256 x f32
153 v512f32 = 96, // 512 x f32
154 v1024f32 = 97, // 1024 x f32
155 v2048f32 = 98, // 2048 x f32
156
157 v1f64 = 99, // 1 x f64
158 v2f64 = 100, // 2 x f64
159 v4f64 = 101, // 4 x f64
160 v8f64 = 102, // 8 x f64
161 v16f64 = 103, // 16 x f64
162 v32f64 = 104, // 32 x f64
163 v64f64 = 105, // 64 x f64
164 v128f64 = 106, // 128 x f64
165 v256f64 = 107, // 256 x f64
166
167 FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
168 LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
169
170 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
171 LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
172
173 nxv1i1 = 108, // n x 1 x i1
174 nxv2i1 = 109, // n x 2 x i1
175 nxv4i1 = 110, // n x 4 x i1
176 nxv8i1 = 111, // n x 8 x i1
177 nxv16i1 = 112, // n x 16 x i1
178 nxv32i1 = 113, // n x 32 x i1
179 nxv64i1 = 114, // n x 64 x i1
180
181 nxv1i8 = 115, // n x 1 x i8
182 nxv2i8 = 116, // n x 2 x i8
183 nxv4i8 = 117, // n x 4 x i8
184 nxv8i8 = 118, // n x 8 x i8
185 nxv16i8 = 119, // n x 16 x i8
186 nxv32i8 = 120, // n x 32 x i8
187 nxv64i8 = 121, // n x 64 x i8
188
189 nxv1i16 = 122, // n x 1 x i16
190 nxv2i16 = 123, // n x 2 x i16
191 nxv4i16 = 124, // n x 4 x i16
192 nxv8i16 = 125, // n x 8 x i16
193 nxv16i16 = 126, // n x 16 x i16
194 nxv32i16 = 127, // n x 32 x i16
195
196 nxv1i32 = 128, // n x 1 x i32
197 nxv2i32 = 129, // n x 2 x i32
198 nxv4i32 = 130, // n x 4 x i32
199 nxv8i32 = 131, // n x 8 x i32
200 nxv16i32 = 132, // n x 16 x i32
201 nxv32i32 = 133, // n x 32 x i32
202
203 nxv1i64 = 134, // n x 1 x i64
204 nxv2i64 = 135, // n x 2 x i64
205 nxv4i64 = 136, // n x 4 x i64
206 nxv8i64 = 137, // n x 8 x i64
207 nxv16i64 = 138, // n x 16 x i64
208 nxv32i64 = 139, // n x 32 x i64
209
210 FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
211 LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
212
213 nxv1f16 = 140, // n x 1 x f16
214 nxv2f16 = 141, // n x 2 x f16
215 nxv4f16 = 142, // n x 4 x f16
216 nxv8f16 = 143, // n x 8 x f16
217 nxv16f16 = 144, // n x 16 x f16
218 nxv32f16 = 145, // n x 32 x f16
219
220 nxv1bf16 = 146, // n x 1 x bf16
221 nxv2bf16 = 147, // n x 2 x bf16
222 nxv4bf16 = 148, // n x 4 x bf16
223 nxv8bf16 = 149, // n x 8 x bf16
224
225 nxv1f32 = 150, // n x 1 x f32
226 nxv2f32 = 151, // n x 2 x f32
227 nxv4f32 = 152, // n x 4 x f32
228 nxv8f32 = 153, // n x 8 x f32
229 nxv16f32 = 154, // n x 16 x f32
230
231 nxv1f64 = 155, // n x 1 x f64
232 nxv2f64 = 156, // n x 2 x f64
233 nxv4f64 = 157, // n x 4 x f64
234 nxv8f64 = 158, // n x 8 x f64
235
236 FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
237 LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
238
239 FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
240 LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
241
242 FIRST_VECTOR_VALUETYPE = v1i1,
243 LAST_VECTOR_VALUETYPE = nxv8f64,
244
245 x86mmx = 159, // This is an X86 MMX value
246
247 Glue = 160, // This glues nodes together during pre-RA sched
248
249 isVoid = 161, // This has no value
250
251 Untyped = 162, // This value takes a register, but has
252 // unspecified type. The register class
253 // will be determined by the opcode.
254
255 funcref = 163, // WebAssembly's funcref type
256 externref = 164, // WebAssembly's externref type
257 x86amx = 165, // This is an X86 AMX value
258
259 FIRST_VALUETYPE = 1, // This is always the beginning of the list.
260 LAST_VALUETYPE = 166, // This always remains at the end of the list.
261
262 // This is the current maximum for LAST_VALUETYPE.
263 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
264 // This value must be a multiple of 32.
265 MAX_ALLOWED_VALUETYPE = 192,
266
267 // A value of type llvm::TokenTy
268 token = 248,
269
270 // This is MDNode or MDString.
271 Metadata = 249,
272
273 // An int value the size of the pointer of the current
274 // target to any address space. This must only be used internal to
275 // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR.
276 iPTRAny = 250,
277
278 // A vector with any length and element size. This is used
279 // for intrinsics that have overloadings based on vector types.
280 // This is only for tblgen's consumption!
281 vAny = 251,
282
283 // Any floating-point or vector floating-point value. This is used
284 // for intrinsics that have overloadings based on floating-point types.
285 // This is only for tblgen's consumption!
286 fAny = 252,
287
288 // An integer or vector integer value of any bit width. This is
289 // used for intrinsics that have overloadings based on integer bit widths.
290 // This is only for tblgen's consumption!
291 iAny = 253,
292
293 // An int value the size of the pointer of the current
294 // target. This should only be used internal to tblgen!
295 iPTR = 254,
296
297 // Any type. This is used for intrinsics that have overloadings.
298 // This is only for tblgen's consumption!
299 Any = 255
300 };
301
302 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;
303
304 constexpr MVT() = default;
305 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}
306
307 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
308 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
309 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
10
Assuming 'SimpleTy' is equal to 'S.SimpleTy'
11
Returning the value 1, which participates in a condition later
310 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
311 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
312 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
313
314 /// Return true if this is a valid simple valuetype.
315 bool isValid() const {
316 return (SimpleTy >= MVT::FIRST_VALUETYPE &&
317 SimpleTy < MVT::LAST_VALUETYPE);
318 }
319
320 /// Return true if this is a FP or a vector FP type.
321 bool isFloatingPoint() const {
322 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
323 SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
324 (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE &&
325 SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) ||
326 (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE &&
327 SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE));
328 }
329
330 /// Return true if this is an integer or a vector integer type.
331 bool isInteger() const {
332 return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
333 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
334 (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
335 SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
336 (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
337 SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
338 }
339
340 /// Return true if this is an integer, not including vectors.
341 bool isScalarInteger() const {
342 return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
343 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
344 }
345
346 /// Return true if this is a vector value type.
347 bool isVector() const {
348 return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
349 SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
350 }
351
352 /// Return true if this is a vector value type where the
353 /// runtime length is machine dependent
354 bool isScalableVector() const {
355 return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE &&
356 SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
357 }
358
359 bool isFixedLengthVector() const {
360 return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
361 SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
362 }
363
364 /// Return true if this is a 16-bit vector type.
365 bool is16BitVector() const {
366 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 ||
367 SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16);
368 }
369
370 /// Return true if this is a 32-bit vector type.
371 bool is32BitVector() const {
372 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
373 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 ||
374 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
375 SimpleTy == MVT::v1f32);
376 }
377
378 /// Return true if this is a 64-bit vector type.
379 bool is64BitVector() const {
380 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
381 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 ||
382 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 ||
383 SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 ||
384 SimpleTy == MVT::v1f64);
385 }
386
387 /// Return true if this is a 128-bit vector type.
388 bool is128BitVector() const {
389 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 ||
390 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
391 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
392 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 ||
393 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
394 }
395
396 /// Return true if this is a 256-bit vector type.
397 bool is256BitVector() const {
398 return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
399 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
400 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
401 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 ||
402 SimpleTy == MVT::v256i1);
403 }
404
405 /// Return true if this is a 512-bit vector type.
406 bool is512BitVector() const {
407 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 ||
408 SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 ||
409 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 ||
410 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
411 SimpleTy == MVT::v8i64);
412 }
413
414 /// Return true if this is a 1024-bit vector type.
415 bool is1024BitVector() const {
416 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 ||
417 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 ||
418 SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 ||
419 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 ||
420 SimpleTy == MVT::v64bf16);
421 }
422
423 /// Return true if this is a 2048-bit vector type.
424 bool is2048BitVector() const {
425 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
426 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 ||
427 SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 ||
428 SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16);
429 }
430
431 /// Return true if this is an overloaded type for TableGen.
432 bool isOverloaded() const {
433 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
434 SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
435 SimpleTy == MVT::iPTRAny);
436 }
437
438 /// Return a vector with the same number of elements as this vector, but
439 /// with the element type converted to an integer type with the same
440 /// bitwidth.
441 MVT changeVectorElementTypeToInteger() const {
442 MVT EltTy = getVectorElementType();
443 MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits());
444 MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount());
445 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 446, __PRETTY_FUNCTION__))
446 "Simple vector VT not representable by simple integer vector VT!")((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 446, __PRETTY_FUNCTION__))
;
447 return VecTy;
448 }
449
450 /// Return a VT for a vector type whose attributes match ourselves
451 /// with the exception of the element type that is chosen by the caller.
452 MVT changeVectorElementType(MVT EltVT) const {
453 MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount());
454 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 455, __PRETTY_FUNCTION__))
455 "Simple vector VT not representable by simple integer vector VT!")((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 455, __PRETTY_FUNCTION__))
;
456 return VecTy;
457 }
458
459 /// Return the type converted to an equivalently sized integer or vector
460 /// with integer element type. Similar to changeVectorElementTypeToInteger,
461 /// but also handles scalars.
462 MVT changeTypeToInteger() {
463 if (isVector())
464 return changeVectorElementTypeToInteger();
465 return MVT::getIntegerVT(getSizeInBits());
466 }
467
468 /// Return a VT for a vector type with the same element type but
469 /// half the number of elements.
470 MVT getHalfNumVectorElementsVT() const {
471 MVT EltVT = getVectorElementType();
472 auto EltCnt = getVectorElementCount();
473 assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")((EltCnt.isKnownEven() && "Splitting vector, but not in half!"
) ? static_cast<void> (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 473, __PRETTY_FUNCTION__))
;
474 return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2));
475 }
476
477 /// Returns true if the given vector is a power of 2.
478 bool isPow2VectorType() const {
479 unsigned NElts = getVectorNumElements();
480 return !(NElts & (NElts - 1));
481 }
482
483 /// Widens the length of the given vector MVT up to the nearest power of 2
484 /// and returns that type.
485 MVT getPow2VectorType() const {
486 if (isPow2VectorType())
487 return *this;
488
489 unsigned NElts = getVectorNumElements();
490 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
491 return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
492 }
493
494 /// If this is a vector, return the element type, otherwise return this.
495 MVT getScalarType() const {
496 return isVector() ? getVectorElementType() : *this;
497 }
498
499 MVT getVectorElementType() const {
500 switch (SimpleTy) {
501 default:
502 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 502)
;
503 case v1i1:
504 case v2i1:
505 case v4i1:
506 case v8i1:
507 case v16i1:
508 case v32i1:
509 case v64i1:
510 case v128i1:
511 case v256i1:
512 case v512i1:
513 case v1024i1:
514 case nxv1i1:
515 case nxv2i1:
516 case nxv4i1:
517 case nxv8i1:
518 case nxv16i1:
519 case nxv32i1:
520 case nxv64i1: return i1;
521 case v1i8:
522 case v2i8:
523 case v4i8:
524 case v8i8:
525 case v16i8:
526 case v32i8:
527 case v64i8:
528 case v128i8:
529 case v256i8:
530 case nxv1i8:
531 case nxv2i8:
532 case nxv4i8:
533 case nxv8i8:
534 case nxv16i8:
535 case nxv32i8:
536 case nxv64i8: return i8;
537 case v1i16:
538 case v2i16:
539 case v3i16:
540 case v4i16:
541 case v8i16:
542 case v16i16:
543 case v32i16:
544 case v64i16:
545 case v128i16:
546 case nxv1i16:
547 case nxv2i16:
548 case nxv4i16:
549 case nxv8i16:
550 case nxv16i16:
551 case nxv32i16: return i16;
552 case v1i32:
553 case v2i32:
554 case v3i32:
555 case v4i32:
556 case v5i32:
557 case v8i32:
558 case v16i32:
559 case v32i32:
560 case v64i32:
561 case v128i32:
562 case v256i32:
563 case v512i32:
564 case v1024i32:
565 case v2048i32:
566 case nxv1i32:
567 case nxv2i32:
568 case nxv4i32:
569 case nxv8i32:
570 case nxv16i32:
571 case nxv32i32: return i32;
572 case v1i64:
573 case v2i64:
574 case v4i64:
575 case v8i64:
576 case v16i64:
577 case v32i64:
578 case v64i64:
579 case v128i64:
580 case v256i64:
581 case nxv1i64:
582 case nxv2i64:
583 case nxv4i64:
584 case nxv8i64:
585 case nxv16i64:
586 case nxv32i64: return i64;
587 case v1i128: return i128;
588 case v1f16:
589 case v2f16:
590 case v3f16:
591 case v4f16:
592 case v8f16:
593 case v16f16:
594 case v32f16:
595 case v64f16:
596 case v128f16:
597 case nxv1f16:
598 case nxv2f16:
599 case nxv4f16:
600 case nxv8f16:
601 case nxv16f16:
602 case nxv32f16: return f16;
603 case v2bf16:
604 case v3bf16:
605 case v4bf16:
606 case v8bf16:
607 case v16bf16:
608 case v32bf16:
609 case v64bf16:
610 case v128bf16:
611 case nxv1bf16:
612 case nxv2bf16:
613 case nxv4bf16:
614 case nxv8bf16: return bf16;
615 case v1f32:
616 case v2f32:
617 case v3f32:
618 case v4f32:
619 case v5f32:
620 case v8f32:
621 case v16f32:
622 case v32f32:
623 case v64f32:
624 case v128f32:
625 case v256f32:
626 case v512f32:
627 case v1024f32:
628 case v2048f32:
629 case nxv1f32:
630 case nxv2f32:
631 case nxv4f32:
632 case nxv8f32:
633 case nxv16f32: return f32;
634 case v1f64:
635 case v2f64:
636 case v4f64:
637 case v8f64:
638 case v16f64:
639 case v32f64:
640 case v64f64:
641 case v128f64:
642 case v256f64:
643 case nxv1f64:
644 case nxv2f64:
645 case nxv4f64:
646 case nxv8f64: return f64;
647 }
648 }
649
650 unsigned getVectorNumElements() const {
651 switch (SimpleTy) {
652 default:
653 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 653)
;
654 case v2048i32:
655 case v2048f32: return 2048;
656 case v1024i1:
657 case v1024i32:
658 case v1024f32: return 1024;
659 case v512i1:
660 case v512i32:
661 case v512f32: return 512;
662 case v256i1:
663 case v256i8:
664 case v256i32:
665 case v256i64:
666 case v256f32:
667 case v256f64: return 256;
668 case v128i1:
669 case v128i8:
670 case v128i16:
671 case v128i32:
672 case v128i64:
673 case v128f16:
674 case v128bf16:
675 case v128f32:
676 case v128f64: return 128;
677 case v64i1:
678 case v64i8:
679 case v64i16:
680 case v64i32:
681 case v64i64:
682 case v64f16:
683 case v64bf16:
684 case v64f32:
685 case v64f64:
686 case nxv64i1:
687 case nxv64i8: return 64;
688 case v32i1:
689 case v32i8:
690 case v32i16:
691 case v32i32:
692 case v32i64:
693 case v32f16:
694 case v32bf16:
695 case v32f32:
696 case v32f64:
697 case nxv32i1:
698 case nxv32i8:
699 case nxv32i16:
700 case nxv32i32:
701 case nxv32i64:
702 case nxv32f16: return 32;
703 case v16i1:
704 case v16i8:
705 case v16i16:
706 case v16i32:
707 case v16i64:
708 case v16f16:
709 case v16bf16:
710 case v16f32:
711 case v16f64:
712 case nxv16i1:
713 case nxv16i8:
714 case nxv16i16:
715 case nxv16i32:
716 case nxv16i64:
717 case nxv16f16:
718 case nxv16f32: return 16;
719 case v8i1:
720 case v8i8:
721 case v8i16:
722 case v8i32:
723 case v8i64:
724 case v8f16:
725 case v8bf16:
726 case v8f32:
727 case v8f64:
728 case nxv8i1:
729 case nxv8i8:
730 case nxv8i16:
731 case nxv8i32:
732 case nxv8i64:
733 case nxv8f16:
734 case nxv8bf16:
735 case nxv8f32:
736 case nxv8f64: return 8;
737 case v5i32:
738 case v5f32: return 5;
739 case v4i1:
740 case v4i8:
741 case v4i16:
742 case v4i32:
743 case v4i64:
744 case v4f16:
745 case v4bf16:
746 case v4f32:
747 case v4f64:
748 case nxv4i1:
749 case nxv4i8:
750 case nxv4i16:
751 case nxv4i32:
752 case nxv4i64:
753 case nxv4f16:
754 case nxv4bf16:
755 case nxv4f32:
756 case nxv4f64: return 4;
757 case v3i16:
758 case v3i32:
759 case v3f16:
760 case v3bf16:
761 case v3f32: return 3;
762 case v2i1:
763 case v2i8:
764 case v2i16:
765 case v2i32:
766 case v2i64:
767 case v2f16:
768 case v2bf16:
769 case v2f32:
770 case v2f64:
771 case nxv2i1:
772 case nxv2i8:
773 case nxv2i16:
774 case nxv2i32:
775 case nxv2i64:
776 case nxv2f16:
777 case nxv2bf16:
778 case nxv2f32:
779 case nxv2f64: return 2;
780 case v1i1:
781 case v1i8:
782 case v1i16:
783 case v1i32:
784 case v1i64:
785 case v1i128:
786 case v1f16:
787 case v1f32:
788 case v1f64:
789 case nxv1i1:
790 case nxv1i8:
791 case nxv1i16:
792 case nxv1i32:
793 case nxv1i64:
794 case nxv1f16:
795 case nxv1bf16:
796 case nxv1f32:
797 case nxv1f64: return 1;
798 }
799 }
800
801 ElementCount getVectorElementCount() const {
802 return ElementCount::get(getVectorNumElements(), isScalableVector());
803 }
804
805 /// Given a vector type, return the minimum number of elements it contains.
806 unsigned getVectorMinNumElements() const {
807 return getVectorElementCount().getKnownMinValue();
808 }
809
810 /// Returns the size of the specified MVT in bits.
811 ///
812 /// If the value type is a scalable vector type, the scalable property will
813 /// be set and the runtime size will be a positive integer multiple of the
814 /// base size.
815 TypeSize getSizeInBits() const {
816 switch (SimpleTy) {
817 default:
818 llvm_unreachable("getSizeInBits called on extended MVT.")::llvm::llvm_unreachable_internal("getSizeInBits called on extended MVT."
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 818)
;
819 case Other:
820 llvm_unreachable("Value type is non-standard value, Other.")::llvm::llvm_unreachable_internal("Value type is non-standard value, Other."
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 820)
;
821 case iPTR:
822 llvm_unreachable("Value type size is target-dependent. Ask TLI.")::llvm::llvm_unreachable_internal("Value type size is target-dependent. Ask TLI."
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 822)
;
823 case iPTRAny:
824 case iAny:
825 case fAny:
826 case vAny:
827 case Any:
828 llvm_unreachable("Value type is overloaded.")::llvm::llvm_unreachable_internal("Value type is overloaded."
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 828)
;
829 case token:
830 llvm_unreachable("Token type is a sentinel that cannot be used "::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 831)
831 "in codegen and has no size")::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 831)
;
832 case Metadata:
833 llvm_unreachable("Value type is metadata.")::llvm::llvm_unreachable_internal("Value type is metadata.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 833)
;
834 case i1:
835 case v1i1: return TypeSize::Fixed(1);
836 case nxv1i1: return TypeSize::Scalable(1);
837 case v2i1: return TypeSize::Fixed(2);
838 case nxv2i1: return TypeSize::Scalable(2);
839 case v4i1: return TypeSize::Fixed(4);
840 case nxv4i1: return TypeSize::Scalable(4);
841 case i8 :
842 case v1i8:
843 case v8i1: return TypeSize::Fixed(8);
844 case nxv1i8:
845 case nxv8i1: return TypeSize::Scalable(8);
846 case i16 :
847 case f16:
848 case bf16:
849 case v16i1:
850 case v2i8:
851 case v1i16:
852 case v1f16: return TypeSize::Fixed(16);
853 case nxv16i1:
854 case nxv2i8:
855 case nxv1i16:
856 case nxv1bf16:
857 case nxv1f16: return TypeSize::Scalable(16);
858 case f32 :
859 case i32 :
860 case v32i1:
861 case v4i8:
862 case v2i16:
863 case v2f16:
864 case v2bf16:
865 case v1f32:
866 case v1i32: return TypeSize::Fixed(32);
867 case nxv32i1:
868 case nxv4i8:
869 case nxv2i16:
870 case nxv1i32:
871 case nxv2f16:
872 case nxv2bf16:
873 case nxv1f32: return TypeSize::Scalable(32);
874 case v3i16:
875 case v3f16:
876 case v3bf16: return TypeSize::Fixed(48);
877 case x86mmx:
878 case f64 :
879 case i64 :
880 case v64i1:
881 case v8i8:
882 case v4i16:
883 case v2i32:
884 case v1i64:
885 case v4f16:
886 case v4bf16:
887 case v2f32:
888 case v1f64: return TypeSize::Fixed(64);
889 case nxv64i1:
890 case nxv8i8:
891 case nxv4i16:
892 case nxv2i32:
893 case nxv1i64:
894 case nxv4f16:
895 case nxv4bf16:
896 case nxv2f32:
897 case nxv1f64: return TypeSize::Scalable(64);
898 case f80 : return TypeSize::Fixed(80);
899 case v3i32:
900 case v3f32: return TypeSize::Fixed(96);
901 case f128:
902 case ppcf128:
903 case i128:
904 case v128i1:
905 case v16i8:
906 case v8i16:
907 case v4i32:
908 case v2i64:
909 case v1i128:
910 case v8f16:
911 case v8bf16:
912 case v4f32:
913 case v2f64: return TypeSize::Fixed(128);
914 case nxv16i8:
915 case nxv8i16:
916 case nxv4i32:
917 case nxv2i64:
918 case nxv8f16:
919 case nxv8bf16:
920 case nxv4f32:
921 case nxv2f64: return TypeSize::Scalable(128);
922 case v5i32:
923 case v5f32: return TypeSize::Fixed(160);
924 case v256i1:
925 case v32i8:
926 case v16i16:
927 case v8i32:
928 case v4i64:
929 case v16f16:
930 case v16bf16:
931 case v8f32:
932 case v4f64: return TypeSize::Fixed(256);
933 case nxv32i8:
934 case nxv16i16:
935 case nxv8i32:
936 case nxv4i64:
937 case nxv16f16:
938 case nxv8f32:
939 case nxv4f64: return TypeSize::Scalable(256);
940 case v512i1:
941 case v64i8:
942 case v32i16:
943 case v16i32:
944 case v8i64:
945 case v32f16:
946 case v32bf16:
947 case v16f32:
948 case v8f64: return TypeSize::Fixed(512);
949 case nxv64i8:
950 case nxv32i16:
951 case nxv16i32:
952 case nxv8i64:
953 case nxv32f16:
954 case nxv16f32:
955 case nxv8f64: return TypeSize::Scalable(512);
956 case v1024i1:
957 case v128i8:
958 case v64i16:
959 case v32i32:
960 case v16i64:
961 case v64f16:
962 case v64bf16:
963 case v32f32:
964 case v16f64: return TypeSize::Fixed(1024);
965 case nxv32i32:
966 case nxv16i64: return TypeSize::Scalable(1024);
967 case v256i8:
968 case v128i16:
969 case v64i32:
970 case v32i64:
971 case v128f16:
972 case v128bf16:
973 case v64f32:
974 case v32f64: return TypeSize::Fixed(2048);
975 case nxv32i64: return TypeSize::Scalable(2048);
976 case v128i32:
977 case v64i64:
978 case v128f32:
979 case v64f64: return TypeSize::Fixed(4096);
980 case v256i32:
981 case v128i64:
982 case v256f32:
983 case x86amx:
984 case v128f64: return TypeSize::Fixed(8192);
985 case v512i32:
986 case v256i64:
987 case v512f32:
988 case v256f64: return TypeSize::Fixed(16384);
989 case v1024i32:
990 case v1024f32: return TypeSize::Fixed(32768);
991 case v2048i32:
992 case v2048f32: return TypeSize::Fixed(65536);
993 case funcref:
994 case externref: return TypeSize::Fixed(0); // opaque type
995 }
996 }
997
998 /// Return the size of the specified fixed width value type in bits. The
999 /// function will assert if the type is scalable.
1000 uint64_t getFixedSizeInBits() const {
1001 return getSizeInBits().getFixedSize();
1002 }
1003
1004 uint64_t getScalarSizeInBits() const {
1005 return getScalarType().getSizeInBits().getFixedSize();
1006 }
1007
1008 /// Return the number of bytes overwritten by a store of the specified value
1009 /// type.
1010 ///
1011 /// If the value type is a scalable vector type, the scalable property will
1012 /// be set and the runtime size will be a positive integer multiple of the
1013 /// base size.
1014 TypeSize getStoreSize() const {
1015 TypeSize BaseSize = getSizeInBits();
1016 return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
1017 }
1018
1019 /// Return the number of bits overwritten by a store of the specified value
1020 /// type.
1021 ///
1022 /// If the value type is a scalable vector type, the scalable property will
1023 /// be set and the runtime size will be a positive integer multiple of the
1024 /// base size.
1025 TypeSize getStoreSizeInBits() const {
1026 return getStoreSize() * 8;
1027 }
1028
1029 /// Returns true if the number of bits for the type is a multiple of an
1030 /// 8-bit byte.
1031 bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }
1032
1033 /// Return true if we know at compile time this has more bits than VT.
1034 bool knownBitsGT(MVT VT) const {
1035 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
1036 }
1037
1038 /// Return true if we know at compile time this has more than or the same
1039 /// bits as VT.
1040 bool knownBitsGE(MVT VT) const {
1041 return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits());
1042 }
1043
1044 /// Return true if we know at compile time this has fewer bits than VT.
1045 bool knownBitsLT(MVT VT) const {
1046 return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits());
1047 }
1048
1049 /// Return true if we know at compile time this has fewer than or the same
1050 /// bits as VT.
1051 bool knownBitsLE(MVT VT) const {
1052 return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits());
1053 }
1054
1055 /// Return true if this has more bits than VT.
1056 bool bitsGT(MVT VT) const {
1057 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1058, __PRETTY_FUNCTION__))
1058 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1058, __PRETTY_FUNCTION__))
;
1059 return knownBitsGT(VT);
1060 }
1061
1062 /// Return true if this has no less bits than VT.
1063 bool bitsGE(MVT VT) const {
1064 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1065, __PRETTY_FUNCTION__))
1065 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1065, __PRETTY_FUNCTION__))
;
1066 return knownBitsGE(VT);
1067 }
1068
1069 /// Return true if this has less bits than VT.
1070 bool bitsLT(MVT VT) const {
1071 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1072, __PRETTY_FUNCTION__))
1072 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1072, __PRETTY_FUNCTION__))
;
1073 return knownBitsLT(VT);
1074 }
1075
1076 /// Return true if this has no more bits than VT.
1077 bool bitsLE(MVT VT) const {
1078 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1079, __PRETTY_FUNCTION__))
1079 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1079, __PRETTY_FUNCTION__))
;
1080 return knownBitsLE(VT);
1081 }
1082
1083 static MVT getFloatingPointVT(unsigned BitWidth) {
1084 switch (BitWidth) {
1085 default:
1086 llvm_unreachable("Bad bit width!")::llvm::llvm_unreachable_internal("Bad bit width!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1086)
;
1087 case 16:
1088 return MVT::f16;
1089 case 32:
1090 return MVT::f32;
1091 case 64:
1092 return MVT::f64;
1093 case 80:
1094 return MVT::f80;
1095 case 128:
1096 return MVT::f128;
1097 }
1098 }
1099
1100 static MVT getIntegerVT(unsigned BitWidth) {
1101 switch (BitWidth) {
1102 default:
1103 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1104 case 1:
1105 return MVT::i1;
1106 case 8:
1107 return MVT::i8;
1108 case 16:
1109 return MVT::i16;
1110 case 32:
1111 return MVT::i32;
1112 case 64:
1113 return MVT::i64;
1114 case 128:
1115 return MVT::i128;
1116 }
1117 }
1118
1119 static MVT getVectorVT(MVT VT, unsigned NumElements) {
1120 switch (VT.SimpleTy) {
1121 default:
1122 break;
1123 case MVT::i1:
1124 if (NumElements == 1) return MVT::v1i1;
1125 if (NumElements == 2) return MVT::v2i1;
1126 if (NumElements == 4) return MVT::v4i1;
1127 if (NumElements == 8) return MVT::v8i1;
1128 if (NumElements == 16) return MVT::v16i1;
1129 if (NumElements == 32) return MVT::v32i1;
1130 if (NumElements == 64) return MVT::v64i1;
1131 if (NumElements == 128) return MVT::v128i1;
1132 if (NumElements == 256) return MVT::v256i1;
1133 if (NumElements == 512) return MVT::v512i1;
1134 if (NumElements == 1024) return MVT::v1024i1;
1135 break;
1136 case MVT::i8:
1137 if (NumElements == 1) return MVT::v1i8;
1138 if (NumElements == 2) return MVT::v2i8;
1139 if (NumElements == 4) return MVT::v4i8;
1140 if (NumElements == 8) return MVT::v8i8;
1141 if (NumElements == 16) return MVT::v16i8;
1142 if (NumElements == 32) return MVT::v32i8;
1143 if (NumElements == 64) return MVT::v64i8;
1144 if (NumElements == 128) return MVT::v128i8;
1145 if (NumElements == 256) return MVT::v256i8;
1146 break;
1147 case MVT::i16:
1148 if (NumElements == 1) return MVT::v1i16;
1149 if (NumElements == 2) return MVT::v2i16;
1150 if (NumElements == 3) return MVT::v3i16;
1151 if (NumElements == 4) return MVT::v4i16;
1152 if (NumElements == 8) return MVT::v8i16;
1153 if (NumElements == 16) return MVT::v16i16;
1154 if (NumElements == 32) return MVT::v32i16;
1155 if (NumElements == 64) return MVT::v64i16;
1156 if (NumElements == 128) return MVT::v128i16;
1157 break;
1158 case MVT::i32:
1159 if (NumElements == 1) return MVT::v1i32;
1160 if (NumElements == 2) return MVT::v2i32;
1161 if (NumElements == 3) return MVT::v3i32;
1162 if (NumElements == 4) return MVT::v4i32;
1163 if (NumElements == 5) return MVT::v5i32;
1164 if (NumElements == 8) return MVT::v8i32;
1165 if (NumElements == 16) return MVT::v16i32;
1166 if (NumElements == 32) return MVT::v32i32;
1167 if (NumElements == 64) return MVT::v64i32;
1168 if (NumElements == 128) return MVT::v128i32;
1169 if (NumElements == 256) return MVT::v256i32;
1170 if (NumElements == 512) return MVT::v512i32;
1171 if (NumElements == 1024) return MVT::v1024i32;
1172 if (NumElements == 2048) return MVT::v2048i32;
1173 break;
1174 case MVT::i64:
1175 if (NumElements == 1) return MVT::v1i64;
1176 if (NumElements == 2) return MVT::v2i64;
1177 if (NumElements == 4) return MVT::v4i64;
1178 if (NumElements == 8) return MVT::v8i64;
1179 if (NumElements == 16) return MVT::v16i64;
1180 if (NumElements == 32) return MVT::v32i64;
1181 if (NumElements == 64) return MVT::v64i64;
1182 if (NumElements == 128) return MVT::v128i64;
1183 if (NumElements == 256) return MVT::v256i64;
1184 break;
1185 case MVT::i128:
1186 if (NumElements == 1) return MVT::v1i128;
1187 break;
1188 case MVT::f16:
1189 if (NumElements == 1) return MVT::v1f16;
1190 if (NumElements == 2) return MVT::v2f16;
1191 if (NumElements == 3) return MVT::v3f16;
1192 if (NumElements == 4) return MVT::v4f16;
1193 if (NumElements == 8) return MVT::v8f16;
1194 if (NumElements == 16) return MVT::v16f16;
1195 if (NumElements == 32) return MVT::v32f16;
1196 if (NumElements == 64) return MVT::v64f16;
1197 if (NumElements == 128) return MVT::v128f16;
1198 break;
1199 case MVT::bf16:
1200 if (NumElements == 2) return MVT::v2bf16;
1201 if (NumElements == 3) return MVT::v3bf16;
1202 if (NumElements == 4) return MVT::v4bf16;
1203 if (NumElements == 8) return MVT::v8bf16;
1204 if (NumElements == 16) return MVT::v16bf16;
1205 if (NumElements == 32) return MVT::v32bf16;
1206 if (NumElements == 64) return MVT::v64bf16;
1207 if (NumElements == 128) return MVT::v128bf16;
1208 break;
1209 case MVT::f32:
1210 if (NumElements == 1) return MVT::v1f32;
1211 if (NumElements == 2) return MVT::v2f32;
1212 if (NumElements == 3) return MVT::v3f32;
1213 if (NumElements == 4) return MVT::v4f32;
1214 if (NumElements == 5) return MVT::v5f32;
1215 if (NumElements == 8) return MVT::v8f32;
1216 if (NumElements == 16) return MVT::v16f32;
1217 if (NumElements == 32) return MVT::v32f32;
1218 if (NumElements == 64) return MVT::v64f32;
1219 if (NumElements == 128) return MVT::v128f32;
1220 if (NumElements == 256) return MVT::v256f32;
1221 if (NumElements == 512) return MVT::v512f32;
1222 if (NumElements == 1024) return MVT::v1024f32;
1223 if (NumElements == 2048) return MVT::v2048f32;
1224 break;
1225 case MVT::f64:
1226 if (NumElements == 1) return MVT::v1f64;
1227 if (NumElements == 2) return MVT::v2f64;
1228 if (NumElements == 4) return MVT::v4f64;
1229 if (NumElements == 8) return MVT::v8f64;
1230 if (NumElements == 16) return MVT::v16f64;
1231 if (NumElements == 32) return MVT::v32f64;
1232 if (NumElements == 64) return MVT::v64f64;
1233 if (NumElements == 128) return MVT::v128f64;
1234 if (NumElements == 256) return MVT::v256f64;
1235 break;
1236 }
1237 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1238 }
1239
1240 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
1241 switch(VT.SimpleTy) {
1242 default:
1243 break;
1244 case MVT::i1:
1245 if (NumElements == 1) return MVT::nxv1i1;
1246 if (NumElements == 2) return MVT::nxv2i1;
1247 if (NumElements == 4) return MVT::nxv4i1;
1248 if (NumElements == 8) return MVT::nxv8i1;
1249 if (NumElements == 16) return MVT::nxv16i1;
1250 if (NumElements == 32) return MVT::nxv32i1;
1251 if (NumElements == 64) return MVT::nxv64i1;
1252 break;
1253 case MVT::i8:
1254 if (NumElements == 1) return MVT::nxv1i8;
1255 if (NumElements == 2) return MVT::nxv2i8;
1256 if (NumElements == 4) return MVT::nxv4i8;
1257 if (NumElements == 8) return MVT::nxv8i8;
1258 if (NumElements == 16) return MVT::nxv16i8;
1259 if (NumElements == 32) return MVT::nxv32i8;
1260 if (NumElements == 64) return MVT::nxv64i8;
1261 break;
1262 case MVT::i16:
1263 if (NumElements == 1) return MVT::nxv1i16;
1264 if (NumElements == 2) return MVT::nxv2i16;
1265 if (NumElements == 4) return MVT::nxv4i16;
1266 if (NumElements == 8) return MVT::nxv8i16;
1267 if (NumElements == 16) return MVT::nxv16i16;
1268 if (NumElements == 32) return MVT::nxv32i16;
1269 break;
1270 case MVT::i32:
1271 if (NumElements == 1) return MVT::nxv1i32;
1272 if (NumElements == 2) return MVT::nxv2i32;
1273 if (NumElements == 4) return MVT::nxv4i32;
1274 if (NumElements == 8) return MVT::nxv8i32;
1275 if (NumElements == 16) return MVT::nxv16i32;
1276 if (NumElements == 32) return MVT::nxv32i32;
1277 break;
1278 case MVT::i64:
1279 if (NumElements == 1) return MVT::nxv1i64;
1280 if (NumElements == 2) return MVT::nxv2i64;
1281 if (NumElements == 4) return MVT::nxv4i64;
1282 if (NumElements == 8) return MVT::nxv8i64;
1283 if (NumElements == 16) return MVT::nxv16i64;
1284 if (NumElements == 32) return MVT::nxv32i64;
1285 break;
1286 case MVT::f16:
1287 if (NumElements == 1) return MVT::nxv1f16;
1288 if (NumElements == 2) return MVT::nxv2f16;
1289 if (NumElements == 4) return MVT::nxv4f16;
1290 if (NumElements == 8) return MVT::nxv8f16;
1291 if (NumElements == 16) return MVT::nxv16f16;
1292 if (NumElements == 32) return MVT::nxv32f16;
1293 break;
1294 case MVT::bf16:
1295 if (NumElements == 1) return MVT::nxv1bf16;
1296 if (NumElements == 2) return MVT::nxv2bf16;
1297 if (NumElements == 4) return MVT::nxv4bf16;
1298 if (NumElements == 8) return MVT::nxv8bf16;
1299 break;
1300 case MVT::f32:
1301 if (NumElements == 1) return MVT::nxv1f32;
1302 if (NumElements == 2) return MVT::nxv2f32;
1303 if (NumElements == 4) return MVT::nxv4f32;
1304 if (NumElements == 8) return MVT::nxv8f32;
1305 if (NumElements == 16) return MVT::nxv16f32;
1306 break;
1307 case MVT::f64:
1308 if (NumElements == 1) return MVT::nxv1f64;
1309 if (NumElements == 2) return MVT::nxv2f64;
1310 if (NumElements == 4) return MVT::nxv4f64;
1311 if (NumElements == 8) return MVT::nxv8f64;
1312 break;
1313 }
1314 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1315 }
1316
1317 static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
1318 if (IsScalable)
1319 return getScalableVectorVT(VT, NumElements);
1320 return getVectorVT(VT, NumElements);
1321 }
1322
1323 static MVT getVectorVT(MVT VT, ElementCount EC) {
1324 if (EC.isScalable())
1325 return getScalableVectorVT(VT, EC.getKnownMinValue());
1326 return getVectorVT(VT, EC.getKnownMinValue());
1327 }
1328
1329 /// Return the value type corresponding to the specified type. This returns
1330 /// all pointers as iPTR. If HandleUnknown is true, unknown types are
1331 /// returned as Other, otherwise they are invalid.
1332 static MVT getVT(Type *Ty, bool HandleUnknown = false);
1333
1334 private:
1335 /// A simple iterator over the MVT::SimpleValueType enum.
1336 struct mvt_iterator {
1337 SimpleValueType VT;
1338
1339 mvt_iterator(SimpleValueType VT) : VT(VT) {}
1340
1341 MVT operator*() const { return VT; }
1342 bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; }
1343
1344 mvt_iterator& operator++() {
1345 VT = (MVT::SimpleValueType)((int)VT + 1);
1346 assert((int)VT <= MVT::MAX_ALLOWED_VALUETYPE &&(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1347, __PRETTY_FUNCTION__))
1347 "MVT iterator overflowed.")(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/Support/MachineValueType.h"
, 1347, __PRETTY_FUNCTION__))
;
1348 return *this;
1349 }
1350 };
1351
1352 /// A range of the MVT::SimpleValueType enum.
1353 using mvt_range = iterator_range<mvt_iterator>;
1354
1355 public:
1356 /// SimpleValueType Iteration
1357 /// @{
1358 static mvt_range all_valuetypes() {
1359 return mvt_range(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE);
1360 }
1361
1362 static mvt_range integer_valuetypes() {
1363 return mvt_range(MVT::FIRST_INTEGER_VALUETYPE,
1364 (MVT::SimpleValueType)(MVT::LAST_INTEGER_VALUETYPE + 1));
1365 }
1366
1367 static mvt_range fp_valuetypes() {
1368 return mvt_range(MVT::FIRST_FP_VALUETYPE,
1369 (MVT::SimpleValueType)(MVT::LAST_FP_VALUETYPE + 1));
1370 }
1371
1372 static mvt_range vector_valuetypes() {
1373 return mvt_range(MVT::FIRST_VECTOR_VALUETYPE,
1374 (MVT::SimpleValueType)(MVT::LAST_VECTOR_VALUETYPE + 1));
1375 }
1376
1377 static mvt_range fixedlen_vector_valuetypes() {
1378 return mvt_range(
1379 MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE,
1380 (MVT::SimpleValueType)(MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE + 1));
1381 }
1382
1383 static mvt_range scalable_vector_valuetypes() {
1384 return mvt_range(
1385 MVT::FIRST_SCALABLE_VECTOR_VALUETYPE,
1386 (MVT::SimpleValueType)(MVT::LAST_SCALABLE_VECTOR_VALUETYPE + 1));
1387 }
1388
1389 static mvt_range integer_fixedlen_vector_valuetypes() {
1390 return mvt_range(
1391 MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
1392 (MVT::SimpleValueType)(MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE + 1));
1393 }
1394
1395 static mvt_range fp_fixedlen_vector_valuetypes() {
1396 return mvt_range(
1397 MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE,
1398 (MVT::SimpleValueType)(MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE + 1));
1399 }
1400
1401 static mvt_range integer_scalable_vector_valuetypes() {
1402 return mvt_range(
1403 MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
1404 (MVT::SimpleValueType)(MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE + 1));
1405 }
1406
1407 static mvt_range fp_scalable_vector_valuetypes() {
1408 return mvt_range(
1409 MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
1410 (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE + 1));
1411 }
1412 /// @}
1413 };
1414
1415} // end namespace llvm
1416
1417#endif // LLVM_SUPPORT_MACHINEVALUETYPE_H