Bug Summary

File:llvm/lib/Target/AVR/AVRISelLowering.cpp
Warning:line 1007, column 13
1st function call argument is an uninitialized value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/lib/Target/AVR -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-26-161721-17566-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp

/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp

1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
53
54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
58
59 for (MVT VT : MVT::integer_valuetypes()) {
60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
61 setLoadExtAction(N, VT, MVT::i1, Promote);
62 setLoadExtAction(N, VT, MVT::i8, Expand);
63 }
64 }
65
66 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
67
68 for (MVT VT : MVT::integer_valuetypes()) {
69 setOperationAction(ISD::ADDC, VT, Legal);
70 setOperationAction(ISD::SUBC, VT, Legal);
71 setOperationAction(ISD::ADDE, VT, Legal);
72 setOperationAction(ISD::SUBE, VT, Legal);
73 }
74
75 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76 // revert into a sub since we don't have an add with immediate instruction.
77 setOperationAction(ISD::ADD, MVT::i32, Custom);
78 setOperationAction(ISD::ADD, MVT::i64, Custom);
79
80 // our shift instructions are only able to shift 1 bit at a time, so handle
81 // this in a custom way.
82 setOperationAction(ISD::SRA, MVT::i8, Custom);
83 setOperationAction(ISD::SHL, MVT::i8, Custom);
84 setOperationAction(ISD::SRL, MVT::i8, Custom);
85 setOperationAction(ISD::SRA, MVT::i16, Custom);
86 setOperationAction(ISD::SHL, MVT::i16, Custom);
87 setOperationAction(ISD::SRL, MVT::i16, Custom);
88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
91
92 setOperationAction(ISD::ROTL, MVT::i8, Custom);
93 setOperationAction(ISD::ROTL, MVT::i16, Expand);
94 setOperationAction(ISD::ROTR, MVT::i8, Custom);
95 setOperationAction(ISD::ROTR, MVT::i16, Expand);
96
97 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102
103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
107 setOperationAction(ISD::SETCC, MVT::i8, Custom);
108 setOperationAction(ISD::SETCC, MVT::i16, Custom);
109 setOperationAction(ISD::SETCC, MVT::i32, Custom);
110 setOperationAction(ISD::SETCC, MVT::i64, Custom);
111 setOperationAction(ISD::SELECT, MVT::i8, Expand);
112 setOperationAction(ISD::SELECT, MVT::i16, Expand);
113
114 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
115
116 // Add support for postincrement and predecrement load/stores.
117 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
121 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
125
126 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
127
128 setOperationAction(ISD::VASTART, MVT::Other, Custom);
129 setOperationAction(ISD::VAEND, MVT::Other, Expand);
130 setOperationAction(ISD::VAARG, MVT::Other, Expand);
131 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
132
133 // Atomic operations which must be lowered to rtlib calls
134 for (MVT VT : MVT::integer_valuetypes()) {
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
142 }
143
144 // Division/remainder
145 setOperationAction(ISD::UDIV, MVT::i8, Expand);
146 setOperationAction(ISD::UDIV, MVT::i16, Expand);
147 setOperationAction(ISD::UREM, MVT::i8, Expand);
148 setOperationAction(ISD::UREM, MVT::i16, Expand);
149 setOperationAction(ISD::SDIV, MVT::i8, Expand);
150 setOperationAction(ISD::SDIV, MVT::i16, Expand);
151 setOperationAction(ISD::SREM, MVT::i8, Expand);
152 setOperationAction(ISD::SREM, MVT::i16, Expand);
153
154 // Make division and modulus custom
155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom);
156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Custom);
159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom);
160 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
161
162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
163 setOperationAction(ISD::MUL, MVT::i8, Expand);
164 setOperationAction(ISD::MUL, MVT::i16, Expand);
165
166 // Expand 16 bit multiplications.
167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
169
170 // Expand multiplications to libcalls when there is
171 // no hardware MUL.
172 if (!Subtarget.supportsMultiplication()) {
173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
175 }
176
177 for (MVT VT : MVT::integer_valuetypes()) {
178 setOperationAction(ISD::MULHS, VT, Expand);
179 setOperationAction(ISD::MULHU, VT, Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(ISD::CTPOP, VT, Expand);
184 setOperationAction(ISD::CTLZ, VT, Expand);
185 setOperationAction(ISD::CTTZ, VT, Expand);
186 }
187
188 for (MVT VT : MVT::integer_valuetypes()) {
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 // TODO: The generated code is pretty poor. Investigate using the
191 // same "shift and subtract with carry" trick that we do for
192 // extending 8-bit to 16-bit. This may require infrastructure
193 // improvements in how we treat 16-bit "registers" to be feasible.
194 }
195
196 // Division rtlib functions (not supported), use divmod functions instead
197 setLibcallName(RTLIB::SDIV_I8, nullptr);
198 setLibcallName(RTLIB::SDIV_I16, nullptr);
199 setLibcallName(RTLIB::SDIV_I32, nullptr);
200 setLibcallName(RTLIB::UDIV_I8, nullptr);
201 setLibcallName(RTLIB::UDIV_I16, nullptr);
202 setLibcallName(RTLIB::UDIV_I32, nullptr);
203
204 // Modulus rtlib functions (not supported), use divmod functions instead
205 setLibcallName(RTLIB::SREM_I8, nullptr);
206 setLibcallName(RTLIB::SREM_I16, nullptr);
207 setLibcallName(RTLIB::SREM_I32, nullptr);
208 setLibcallName(RTLIB::UREM_I8, nullptr);
209 setLibcallName(RTLIB::UREM_I16, nullptr);
210 setLibcallName(RTLIB::UREM_I32, nullptr);
211
212 // Division and modulus rtlib functions
213 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219
220 // Several of the runtime library functions use a special calling conv
221 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
222 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
223 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
224 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225
226 // Trigonometric rtlib functions
227 setLibcallName(RTLIB::SIN_F32, "sin");
228 setLibcallName(RTLIB::COS_F32, "cos");
229
230 setMinFunctionAlignment(Align(2));
231 setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U));
232}
233
234const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235#define NODE(name) \
236 case AVRISD::name: \
237 return #name
238
239 switch (Opcode) {
240 default:
241 return nullptr;
242 NODE(RET_FLAG);
243 NODE(RETI_FLAG);
244 NODE(CALL);
245 NODE(WRAPPER);
246 NODE(LSL);
247 NODE(LSR);
248 NODE(ROL);
249 NODE(ROR);
250 NODE(ASR);
251 NODE(LSLLOOP);
252 NODE(LSRLOOP);
253 NODE(ROLLOOP);
254 NODE(RORLOOP);
255 NODE(ASRLOOP);
256 NODE(BRCOND);
257 NODE(CMP);
258 NODE(CMPC);
259 NODE(TST);
260 NODE(SELECT_CC);
261#undef NODE
262 }
263}
264
265EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
266 EVT VT) const {
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!")((!VT.isVector() && "No AVR SetCC type for vectors!")
? static_cast<void> (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 267, __PRETTY_FUNCTION__))
;
268 return MVT::i8;
269}
270
271SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272 //:TODO: this function has to be completely rewritten to produce optimal
273 // code, for now it's producing very long but correct code.
274 unsigned Opc8;
275 const SDNode *N = Op.getNode();
276 EVT VT = Op.getValueType();
277 SDLoc dl(N);
278 assert(isPowerOf2_32(VT.getSizeInBits()) &&((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
279 "Expected power-of-2 shift amount")((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
;
280
281 // Expand non-constant shifts to loops.
282 if (!isa<ConstantSDNode>(N->getOperand(1))) {
283 switch (Op.getOpcode()) {
284 default:
285 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 285)
;
286 case ISD::SHL:
287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288 N->getOperand(1));
289 case ISD::SRL:
290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291 N->getOperand(1));
292 case ISD::ROTL: {
293 SDValue Amt = N->getOperand(1);
294 EVT AmtVT = Amt.getValueType();
295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298 }
299 case ISD::ROTR: {
300 SDValue Amt = N->getOperand(1);
301 EVT AmtVT = Amt.getValueType();
302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305 }
306 case ISD::SRA:
307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308 N->getOperand(1));
309 }
310 }
311
312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313 SDValue Victim = N->getOperand(0);
314
315 switch (Op.getOpcode()) {
316 case ISD::SRA:
317 Opc8 = AVRISD::ASR;
318 break;
319 case ISD::ROTL:
320 Opc8 = AVRISD::ROL;
321 ShiftAmount = ShiftAmount % VT.getSizeInBits();
322 break;
323 case ISD::ROTR:
324 Opc8 = AVRISD::ROR;
325 ShiftAmount = ShiftAmount % VT.getSizeInBits();
326 break;
327 case ISD::SRL:
328 Opc8 = AVRISD::LSR;
329 break;
330 case ISD::SHL:
331 Opc8 = AVRISD::LSL;
332 break;
333 default:
334 llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 334)
;
335 }
336
337 while (ShiftAmount--) {
338 Victim = DAG.getNode(Opc8, dl, VT, Victim);
339 }
340
341 return Victim;
342}
343
344SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
345 unsigned Opcode = Op->getOpcode();
346 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 347, __PRETTY_FUNCTION__))
347 "Invalid opcode for Div/Rem lowering")(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 347, __PRETTY_FUNCTION__))
;
348 bool IsSigned = (Opcode == ISD::SDIVREM);
349 EVT VT = Op->getValueType(0);
350 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
351
352 RTLIB::Libcall LC;
353 switch (VT.getSimpleVT().SimpleTy) {
354 default:
355 llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 355)
;
356 case MVT::i8:
357 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
358 break;
359 case MVT::i16:
360 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
361 break;
362 case MVT::i32:
363 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
364 break;
365 }
366
367 SDValue InChain = DAG.getEntryNode();
368
369 TargetLowering::ArgListTy Args;
370 TargetLowering::ArgListEntry Entry;
371 for (SDValue const &Value : Op->op_values()) {
372 Entry.Node = Value;
373 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
374 Entry.IsSExt = IsSigned;
375 Entry.IsZExt = !IsSigned;
376 Args.push_back(Entry);
377 }
378
379 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
380 getPointerTy(DAG.getDataLayout()));
381
382 Type *RetTy = (Type *)StructType::get(Ty, Ty);
383
384 SDLoc dl(Op);
385 TargetLowering::CallLoweringInfo CLI(DAG);
386 CLI.setDebugLoc(dl)
387 .setChain(InChain)
388 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
389 .setInRegister()
390 .setSExtResult(IsSigned)
391 .setZExtResult(!IsSigned);
392
393 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
394 return CallInfo.first;
395}
396
397SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
398 SelectionDAG &DAG) const {
399 auto DL = DAG.getDataLayout();
400
401 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
402 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
403
404 // Create the TargetGlobalAddress node, folding in the constant offset.
405 SDValue Result =
406 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
407 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
408}
409
410SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
411 SelectionDAG &DAG) const {
412 auto DL = DAG.getDataLayout();
413 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
414
415 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
416
417 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
418}
419
420/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
421static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
422 switch (CC) {
423 default:
424 llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 424)
;
425 case ISD::SETEQ:
426 return AVRCC::COND_EQ;
427 case ISD::SETNE:
428 return AVRCC::COND_NE;
429 case ISD::SETGE:
430 return AVRCC::COND_GE;
431 case ISD::SETLT:
432 return AVRCC::COND_LT;
433 case ISD::SETUGE:
434 return AVRCC::COND_SH;
435 case ISD::SETULT:
436 return AVRCC::COND_LO;
437 }
438}
439
440/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
441/// the given operands.
442SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
443 SDValue &AVRcc, SelectionDAG &DAG,
444 SDLoc DL) const {
445 SDValue Cmp;
446 EVT VT = LHS.getValueType();
447 bool UseTest = false;
448
449 switch (CC) {
450 default:
451 break;
452 case ISD::SETLE: {
453 // Swap operands and reverse the branching condition.
454 std::swap(LHS, RHS);
455 CC = ISD::SETGE;
456 break;
457 }
458 case ISD::SETGT: {
459 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
460 switch (C->getSExtValue()) {
461 case -1: {
462 // When doing lhs > -1 use a tst instruction on the top part of lhs
463 // and use brpl instead of using a chain of cp/cpc.
464 UseTest = true;
465 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
466 break;
467 }
468 case 0: {
469 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
470 // __zero_reg__ in lhs.
471 RHS = LHS;
472 LHS = DAG.getConstant(0, DL, VT);
473 CC = ISD::SETLT;
474 break;
475 }
476 default: {
477 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
478 // us to fold the constant into the cmp instruction.
479 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
480 CC = ISD::SETGE;
481 break;
482 }
483 }
484 break;
485 }
486 // Swap operands and reverse the branching condition.
487 std::swap(LHS, RHS);
488 CC = ISD::SETLT;
489 break;
490 }
491 case ISD::SETLT: {
492 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
493 switch (C->getSExtValue()) {
494 case 1: {
495 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
496 // __zero_reg__ in lhs.
497 RHS = LHS;
498 LHS = DAG.getConstant(0, DL, VT);
499 CC = ISD::SETGE;
500 break;
501 }
502 case 0: {
503 // When doing lhs < 0 use a tst instruction on the top part of lhs
504 // and use brmi instead of using a chain of cp/cpc.
505 UseTest = true;
506 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
507 break;
508 }
509 }
510 }
511 break;
512 }
513 case ISD::SETULE: {
514 // Swap operands and reverse the branching condition.
515 std::swap(LHS, RHS);
516 CC = ISD::SETUGE;
517 break;
518 }
519 case ISD::SETUGT: {
520 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
521 // fold the constant into the cmp instruction.
522 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
523 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
524 CC = ISD::SETUGE;
525 break;
526 }
527 // Swap operands and reverse the branching condition.
528 std::swap(LHS, RHS);
529 CC = ISD::SETULT;
530 break;
531 }
532 }
533
534 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
535 // using the default and/or/xor expansion code which is much longer.
536 if (VT == MVT::i32) {
537 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
538 DAG.getIntPtrConstant(0, DL));
539 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
540 DAG.getIntPtrConstant(1, DL));
541 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
542 DAG.getIntPtrConstant(0, DL));
543 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
544 DAG.getIntPtrConstant(1, DL));
545
546 if (UseTest) {
547 // When using tst we only care about the highest part.
548 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
549 DAG.getIntPtrConstant(1, DL));
550 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
551 } else {
552 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
553 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
554 }
555 } else if (VT == MVT::i64) {
556 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
557 DAG.getIntPtrConstant(0, DL));
558 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
559 DAG.getIntPtrConstant(1, DL));
560
561 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
562 DAG.getIntPtrConstant(0, DL));
563 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
564 DAG.getIntPtrConstant(1, DL));
565 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
566 DAG.getIntPtrConstant(0, DL));
567 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
568 DAG.getIntPtrConstant(1, DL));
569
570 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
571 DAG.getIntPtrConstant(0, DL));
572 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
573 DAG.getIntPtrConstant(1, DL));
574
575 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
576 DAG.getIntPtrConstant(0, DL));
577 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
578 DAG.getIntPtrConstant(1, DL));
579 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
580 DAG.getIntPtrConstant(0, DL));
581 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
582 DAG.getIntPtrConstant(1, DL));
583
584 if (UseTest) {
585 // When using tst we only care about the highest part.
586 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
587 DAG.getIntPtrConstant(1, DL));
588 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
589 } else {
590 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
591 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
592 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
593 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
594 }
595 } else if (VT == MVT::i8 || VT == MVT::i16) {
596 if (UseTest) {
597 // When using tst we only care about the highest part.
598 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
599 (VT == MVT::i8)
600 ? LHS
601 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
602 LHS, DAG.getIntPtrConstant(1, DL)));
603 } else {
604 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
605 }
606 } else {
607 llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 607)
;
608 }
609
610 // When using a test instruction AVRcc is already set.
611 if (!UseTest) {
612 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
613 }
614
615 return Cmp;
616}
617
618SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
619 SDValue Chain = Op.getOperand(0);
620 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
621 SDValue LHS = Op.getOperand(2);
622 SDValue RHS = Op.getOperand(3);
623 SDValue Dest = Op.getOperand(4);
624 SDLoc dl(Op);
625
626 SDValue TargetCC;
627 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
628
629 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
630 Cmp);
631}
632
633SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
634 SDValue LHS = Op.getOperand(0);
635 SDValue RHS = Op.getOperand(1);
636 SDValue TrueV = Op.getOperand(2);
637 SDValue FalseV = Op.getOperand(3);
638 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
639 SDLoc dl(Op);
640
641 SDValue TargetCC;
642 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
643
644 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
645 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
646
647 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
648}
649
650SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
651 SDValue LHS = Op.getOperand(0);
652 SDValue RHS = Op.getOperand(1);
653 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
654 SDLoc DL(Op);
655
656 SDValue TargetCC;
657 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
658
659 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
660 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
661 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
662 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
663
664 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
665}
666
667SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
668 const MachineFunction &MF = DAG.getMachineFunction();
669 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
670 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
671 auto DL = DAG.getDataLayout();
672 SDLoc dl(Op);
673
674 // Vastart just stores the address of the VarArgsFrameIndex slot into the
675 // memory location argument.
676 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
677
678 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
679 MachinePointerInfo(SV));
680}
681
682SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
683 switch (Op.getOpcode()) {
684 default:
685 llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 685)
;
686 case ISD::SHL:
687 case ISD::SRA:
688 case ISD::SRL:
689 case ISD::ROTL:
690 case ISD::ROTR:
691 return LowerShifts(Op, DAG);
692 case ISD::GlobalAddress:
693 return LowerGlobalAddress(Op, DAG);
694 case ISD::BlockAddress:
695 return LowerBlockAddress(Op, DAG);
696 case ISD::BR_CC:
697 return LowerBR_CC(Op, DAG);
698 case ISD::SELECT_CC:
699 return LowerSELECT_CC(Op, DAG);
700 case ISD::SETCC:
701 return LowerSETCC(Op, DAG);
702 case ISD::VASTART:
703 return LowerVASTART(Op, DAG);
704 case ISD::SDIVREM:
705 case ISD::UDIVREM:
706 return LowerDivRem(Op, DAG);
707 }
708
709 return SDValue();
710}
711
712/// Replace a node with an illegal result type
713/// with a new node built out of custom code.
714void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
715 SmallVectorImpl<SDValue> &Results,
716 SelectionDAG &DAG) const {
717 SDLoc DL(N);
718
719 switch (N->getOpcode()) {
720 case ISD::ADD: {
721 // Convert add (x, imm) into sub (x, -imm).
722 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
723 SDValue Sub = DAG.getNode(
724 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
725 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
726 Results.push_back(Sub);
727 }
728 break;
729 }
730 default: {
731 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
732
733 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
734 Results.push_back(Res.getValue(I));
735
736 break;
737 }
738 }
739}
740
741/// Return true if the addressing mode represented
742/// by AM is legal for this target, for a load/store of the specified type.
743bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
744 const AddrMode &AM, Type *Ty,
745 unsigned AS, Instruction *I) const {
746 int64_t Offs = AM.BaseOffs;
747
748 // Allow absolute addresses.
749 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
750 return true;
751 }
752
753 // Flash memory instructions only allow zero offsets.
754 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
755 return false;
756 }
757
758 // Allow reg+<6bit> offset.
759 if (Offs < 0)
760 Offs = -Offs;
761 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
762 return true;
763 }
764
765 return false;
766}
767
768/// Returns true by value, base pointer and
769/// offset pointer and addressing mode by reference if the node's address
770/// can be legally represented as pre-indexed load / store address.
771bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
772 SDValue &Offset,
773 ISD::MemIndexedMode &AM,
774 SelectionDAG &DAG) const {
775 EVT VT;
776 const SDNode *Op;
777 SDLoc DL(N);
778
779 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
780 VT = LD->getMemoryVT();
781 Op = LD->getBasePtr().getNode();
782 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
783 return false;
784 if (AVR::isProgramMemoryAccess(LD)) {
785 return false;
786 }
787 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
788 VT = ST->getMemoryVT();
789 Op = ST->getBasePtr().getNode();
790 if (AVR::isProgramMemoryAccess(ST)) {
791 return false;
792 }
793 } else {
794 return false;
795 }
796
797 if (VT != MVT::i8 && VT != MVT::i16) {
798 return false;
799 }
800
801 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
802 return false;
803 }
804
805 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
806 int RHSC = RHS->getSExtValue();
807 if (Op->getOpcode() == ISD::SUB)
808 RHSC = -RHSC;
809
810 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
811 return false;
812 }
813
814 Base = Op->getOperand(0);
815 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
816 AM = ISD::PRE_DEC;
817
818 return true;
819 }
820
821 return false;
822}
823
824/// Returns true by value, base pointer and
825/// offset pointer and addressing mode by reference if this node can be
826/// combined with a load / store to form a post-indexed load / store.
827bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
828 SDValue &Base,
829 SDValue &Offset,
830 ISD::MemIndexedMode &AM,
831 SelectionDAG &DAG) const {
832 EVT VT;
833 SDLoc DL(N);
834
835 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
836 VT = LD->getMemoryVT();
837 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
838 return false;
839 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
840 VT = ST->getMemoryVT();
841 if (AVR::isProgramMemoryAccess(ST)) {
842 return false;
843 }
844 } else {
845 return false;
846 }
847
848 if (VT != MVT::i8 && VT != MVT::i16) {
849 return false;
850 }
851
852 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
853 return false;
854 }
855
856 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
857 int RHSC = RHS->getSExtValue();
858 if (Op->getOpcode() == ISD::SUB)
859 RHSC = -RHSC;
860 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
861 return false;
862 }
863
864 Base = Op->getOperand(0);
865 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
866 AM = ISD::POST_INC;
867
868 return true;
869 }
870
871 return false;
872}
873
874bool AVRTargetLowering::isOffsetFoldingLegal(
875 const GlobalAddressSDNode *GA) const {
876 return true;
877}
878
879//===----------------------------------------------------------------------===//
880// Formal Arguments Calling Convention Implementation
881//===----------------------------------------------------------------------===//
882
883#include "AVRGenCallingConv.inc"
884
885/// Registers for calling conventions, ordered in reverse as required by ABI.
886/// Both arrays must be of the same length.
887static const MCPhysReg RegList8[] = {
888 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
889 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
890 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
891static const MCPhysReg RegList16[] = {
892 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
893 AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
894 AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
895 AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
896 AVR::R10R9, AVR::R9R8};
897
898static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
899 "8-bit and 16-bit register arrays must be of equal length");
900
901/// Analyze incoming and outgoing function arguments. We need custom C++ code
902/// to handle special constraints in the ABI.
903/// In addition, all pieces of a certain argument have to be passed either
904/// using registers or the stack but never mixing both.
905template <typename ArgT>
906static void
907analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
908 const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
909 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
910 unsigned NumArgs = Args.size();
911 // This is the index of the last used register, in RegList*.
912 // -1 means R26 (R26 is never actually used in CC).
913 int RegLastIdx = -1;
914 // Once a value is passed to the stack it will always be used
915 bool UseStack = false;
916 for (unsigned i = 0; i != NumArgs;) {
917 MVT VT = Args[i].VT;
918 // We have to count the number of bytes for each function argument, that is
919 // those Args with the same OrigArgIndex. This is important in case the
920 // function takes an aggregate type.
921 // Current argument will be between [i..j).
922 unsigned ArgIndex = Args[i].OrigArgIndex;
923 unsigned TotalBytes = VT.getStoreSize();
924 unsigned j = i + 1;
925 for (; j != NumArgs; ++j) {
926 if (Args[j].OrigArgIndex != ArgIndex)
927 break;
928 TotalBytes += Args[j].VT.getStoreSize();
929 }
930 // Round up to even number of bytes.
931 TotalBytes = alignTo(TotalBytes, 2);
932 // Skip zero sized arguments
933 if (TotalBytes == 0)
934 continue;
935 // The index of the first register to be used
936 unsigned RegIdx = RegLastIdx + TotalBytes;
937 RegLastIdx = RegIdx;
938 // If there are not enough registers, use the stack
939 if (RegIdx >= array_lengthof(RegList8)) {
940 UseStack = true;
941 }
942 for (; i != j; ++i) {
943 MVT VT = Args[i].VT;
944
945 if (UseStack) {
946 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
947 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
948 TD->getABITypeAlign(evt));
949 CCInfo.addLoc(
950 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
951 } else {
952 unsigned Reg;
953 if (VT == MVT::i8) {
954 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
955 } else if (VT == MVT::i16) {
956 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
957 } else {
958 llvm_unreachable(::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 959)
959 "calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 959)
;
960 }
961 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 961, __PRETTY_FUNCTION__))
;
962 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
963 // Registers inside a particular argument are sorted in increasing order
964 // (remember the array is reversed).
965 RegIdx -= VT.getStoreSize();
966 }
967 }
968 }
969}
970
971/// Count the total number of bytes needed to pass or return these arguments.
972template <typename ArgT>
973static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
974 unsigned TotalBytes = 0;
975
976 for (const ArgT& Arg : Args) {
977 TotalBytes += Arg.VT.getStoreSize();
978 }
979 return TotalBytes;
980}
981
982/// Analyze incoming and outgoing value of returning from a function.
983/// The algorithm is similar to analyzeArguments, but there can only be
984/// one value, possibly an aggregate, and it is limited to 8 bytes.
985template <typename ArgT>
986static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
987 CCState &CCInfo) {
988 unsigned NumArgs = Args.size();
989 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
990 // CanLowerReturn() guarantees this assertion.
991 assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered")((TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"
) ? static_cast<void> (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 991, __PRETTY_FUNCTION__))
;
4
'?' condition is true
992
993 // GCC-ABI says that the size is rounded up to the next even number,
994 // but actually once it is more than 4 it will always round up to 8.
995 if (TotalBytes
4.1
'TotalBytes' is <= 4
4.1
'TotalBytes' is <= 4
> 4) {
5
Taking false branch
996 TotalBytes = 8;
997 } else {
998 TotalBytes = alignTo(TotalBytes, 2);
999 }
1000
1001 // The index of the first register to use.
1002 int RegIdx = TotalBytes - 1;
6
'RegIdx' initialized to -1
1003 for (unsigned i = 0; i != NumArgs; ++i) {
7
Assuming 'i' is not equal to 'NumArgs'
8
Loop condition is true. Entering loop body
1004 MVT VT = Args[i].VT;
1005 unsigned Reg;
1006 if (VT == MVT::i8) {
9
Calling 'MVT::operator=='
12
Returning from 'MVT::operator=='
13
Taking true branch
1007 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
14
1st function call argument is an uninitialized value
1008 } else if (VT == MVT::i16) {
1009 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1010 } else {
1011 llvm_unreachable("calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1011)
;
1012 }
1013 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1013, __PRETTY_FUNCTION__))
;
1014 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1015 // Registers sort in increasing order
1016 RegIdx -= VT.getStoreSize();
1017 }
1018}
1019
1020SDValue AVRTargetLowering::LowerFormalArguments(
1021 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1022 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1023 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1024 MachineFunction &MF = DAG.getMachineFunction();
1025 MachineFrameInfo &MFI = MF.getFrameInfo();
1026 auto DL = DAG.getDataLayout();
1027
1028 // Assign locations to all of the incoming arguments.
1029 SmallVector<CCValAssign, 16> ArgLocs;
1030 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1031 *DAG.getContext());
1032
1033 // Variadic functions do not need all the analysis below.
1034 if (isVarArg) {
1035 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1036 } else {
1037 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1038 }
1039
1040 SDValue ArgValue;
1041 for (CCValAssign &VA : ArgLocs) {
1042
1043 // Arguments stored on registers.
1044 if (VA.isRegLoc()) {
1045 EVT RegVT = VA.getLocVT();
1046 const TargetRegisterClass *RC;
1047 if (RegVT == MVT::i8) {
1048 RC = &AVR::GPR8RegClass;
1049 } else if (RegVT == MVT::i16) {
1050 RC = &AVR::DREGSRegClass;
1051 } else {
1052 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1052)
;
1053 }
1054
1055 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1056 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1057
1058 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1059 // following code will handle zexts or sexts generated by other
1060 // front ends. Otherwise:
1061 // If this is an 8 bit value, it is really passed promoted
1062 // to 16 bits. Insert an assert[sz]ext to capture this, then
1063 // truncate to the right size.
1064 switch (VA.getLocInfo()) {
1065 default:
1066 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1066)
;
1067 case CCValAssign::Full:
1068 break;
1069 case CCValAssign::BCvt:
1070 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1071 break;
1072 case CCValAssign::SExt:
1073 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1074 DAG.getValueType(VA.getValVT()));
1075 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1076 break;
1077 case CCValAssign::ZExt:
1078 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1079 DAG.getValueType(VA.getValVT()));
1080 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1081 break;
1082 }
1083
1084 InVals.push_back(ArgValue);
1085 } else {
1086 // Sanity check.
1087 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1087, __PRETTY_FUNCTION__))
;
1088
1089 EVT LocVT = VA.getLocVT();
1090
1091 // Create the frame index object for this incoming parameter.
1092 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1093 VA.getLocMemOffset(), true);
1094
1095 // Create the SelectionDAG nodes corresponding to a load
1096 // from this parameter.
1097 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1098 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1099 MachinePointerInfo::getFixedStack(MF, FI)));
1100 }
1101 }
1102
1103 // If the function takes variable number of arguments, make a frame index for
1104 // the start of the first vararg value... for expansion of llvm.va_start.
1105 if (isVarArg) {
1106 unsigned StackSize = CCInfo.getNextStackOffset();
1107 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1108
1109 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1110 }
1111
1112 return Chain;
1113}
1114
1115//===----------------------------------------------------------------------===//
1116// Call Calling Convention Implementation
1117//===----------------------------------------------------------------------===//
1118
1119SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1120 SmallVectorImpl<SDValue> &InVals) const {
1121 SelectionDAG &DAG = CLI.DAG;
1122 SDLoc &DL = CLI.DL;
1123 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1124 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1125 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1126 SDValue Chain = CLI.Chain;
1127 SDValue Callee = CLI.Callee;
1128 bool &isTailCall = CLI.IsTailCall;
1129 CallingConv::ID CallConv = CLI.CallConv;
1130 bool isVarArg = CLI.IsVarArg;
1131
1132 MachineFunction &MF = DAG.getMachineFunction();
1133
1134 // AVR does not yet support tail call optimization.
1135 isTailCall = false;
1136
1137 // Analyze operands of the call, assigning locations to each operand.
1138 SmallVector<CCValAssign, 16> ArgLocs;
1139 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1140 *DAG.getContext());
1141
1142 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1143 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1144 // node so that legalize doesn't hack it.
1145 const Function *F = nullptr;
1146 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1147 const GlobalValue *GV = G->getGlobal();
1148
1149 F = cast<Function>(GV);
1150 Callee =
1151 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1152 } else if (const ExternalSymbolSDNode *ES =
1153 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1154 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1155 getPointerTy(DAG.getDataLayout()));
1156 }
1157
1158 // Variadic functions do not need all the analysis below.
1159 if (isVarArg) {
1160 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1161 } else {
1162 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1163 }
1164
1165 // Get a count of how many bytes are to be pushed on the stack.
1166 unsigned NumBytes = CCInfo.getNextStackOffset();
1167
1168 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1169
1170 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1171
1172 // First, walk the register assignments, inserting copies.
1173 unsigned AI, AE;
1174 bool HasStackArgs = false;
1175 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1176 CCValAssign &VA = ArgLocs[AI];
1177 EVT RegVT = VA.getLocVT();
1178 SDValue Arg = OutVals[AI];
1179
1180 // Promote the value if needed. With Clang this should not happen.
1181 switch (VA.getLocInfo()) {
1182 default:
1183 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1183)
;
1184 case CCValAssign::Full:
1185 break;
1186 case CCValAssign::SExt:
1187 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1188 break;
1189 case CCValAssign::ZExt:
1190 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1191 break;
1192 case CCValAssign::AExt:
1193 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1194 break;
1195 case CCValAssign::BCvt:
1196 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1197 break;
1198 }
1199
1200 // Stop when we encounter a stack argument, we need to process them
1201 // in reverse order in the loop below.
1202 if (VA.isMemLoc()) {
1203 HasStackArgs = true;
1204 break;
1205 }
1206
1207 // Arguments that can be passed on registers must be kept in the RegsToPass
1208 // vector.
1209 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1210 }
1211
1212 // Second, stack arguments have to walked in reverse order by inserting
1213 // chained stores, this ensures their order is not changed by the scheduler
1214 // and that the push instruction sequence generated is correct, otherwise they
1215 // can be freely intermixed.
1216 if (HasStackArgs) {
1217 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1218 unsigned Loc = AI - 1;
1219 CCValAssign &VA = ArgLocs[Loc];
1220 SDValue Arg = OutVals[Loc];
1221
1222 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1222, __PRETTY_FUNCTION__))
;
1223
1224 // SP points to one stack slot further so add one to adjust it.
1225 SDValue PtrOff = DAG.getNode(
1226 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1227 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1228 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1229
1230 Chain =
1231 DAG.getStore(Chain, DL, Arg, PtrOff,
1232 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()));
1233 }
1234 }
1235
1236 // Build a sequence of copy-to-reg nodes chained together with token chain and
1237 // flag operands which copy the outgoing args into registers. The InFlag in
1238 // necessary since all emited instructions must be stuck together.
1239 SDValue InFlag;
1240 for (auto Reg : RegsToPass) {
1241 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1242 InFlag = Chain.getValue(1);
1243 }
1244
1245 // Returns a chain & a flag for retval copy to use.
1246 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1247 SmallVector<SDValue, 8> Ops;
1248 Ops.push_back(Chain);
1249 Ops.push_back(Callee);
1250
1251 // Add argument registers to the end of the list so that they are known live
1252 // into the call.
1253 for (auto Reg : RegsToPass) {
1254 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1255 }
1256
1257 // Add a register mask operand representing the call-preserved registers.
1258 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1259 const uint32_t *Mask =
1260 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1261 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1261, __PRETTY_FUNCTION__))
;
1262 Ops.push_back(DAG.getRegisterMask(Mask));
1263
1264 if (InFlag.getNode()) {
1265 Ops.push_back(InFlag);
1266 }
1267
1268 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1269 InFlag = Chain.getValue(1);
1270
1271 // Create the CALLSEQ_END node.
1272 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1273 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1274
1275 if (!Ins.empty()) {
1276 InFlag = Chain.getValue(1);
1277 }
1278
1279 // Handle result values, copying them out of physregs into vregs that we
1280 // return.
1281 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1282 InVals);
1283}
1284
1285/// Lower the result values of a call into the
1286/// appropriate copies out of appropriate physical registers.
1287///
1288SDValue AVRTargetLowering::LowerCallResult(
1289 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1290 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1291 SmallVectorImpl<SDValue> &InVals) const {
1292
1293 // Assign locations to each value returned by this call.
1294 SmallVector<CCValAssign, 16> RVLocs;
1295 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1296 *DAG.getContext());
1297
1298 // Handle runtime calling convs.
1299 if (CallConv == CallingConv::AVR_BUILTIN) {
1300 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1301 } else {
1302 analyzeReturnValues(Ins, CCInfo);
1303 }
1304
1305 // Copy all of the result registers out of their specified physreg.
1306 for (CCValAssign const &RVLoc : RVLocs) {
1307 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1308 InFlag)
1309 .getValue(1);
1310 InFlag = Chain.getValue(2);
1311 InVals.push_back(Chain.getValue(0));
1312 }
1313
1314 return Chain;
1315}
1316
1317//===----------------------------------------------------------------------===//
1318// Return Value Calling Convention Implementation
1319//===----------------------------------------------------------------------===//
1320
1321bool AVRTargetLowering::CanLowerReturn(
1322 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1323 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1324 if (CallConv == CallingConv::AVR_BUILTIN) {
1325 SmallVector<CCValAssign, 16> RVLocs;
1326 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1327 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1328 }
1329
1330 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1331 return TotalBytes <= 8;
1332}
1333
1334SDValue
1335AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1336 bool isVarArg,
1337 const SmallVectorImpl<ISD::OutputArg> &Outs,
1338 const SmallVectorImpl<SDValue> &OutVals,
1339 const SDLoc &dl, SelectionDAG &DAG) const {
1340 // CCValAssign - represent the assignment of the return value to locations.
1341 SmallVector<CCValAssign, 16> RVLocs;
1342
1343 // CCState - Info about the registers and stack slot.
1344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1345 *DAG.getContext());
1346
1347 MachineFunction &MF = DAG.getMachineFunction();
1348
1349 // Analyze return values.
1350 if (CallConv == CallingConv::AVR_BUILTIN) {
1
Assuming 'CallConv' is not equal to AVR_BUILTIN
2
Taking false branch
1351 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1352 } else {
1353 analyzeReturnValues(Outs, CCInfo);
3
Calling 'analyzeReturnValues<llvm::ISD::OutputArg>'
1354 }
1355
1356 SDValue Flag;
1357 SmallVector<SDValue, 4> RetOps(1, Chain);
1358 // Copy the result values into the output registers.
1359 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1360 CCValAssign &VA = RVLocs[i];
1361 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1361, __PRETTY_FUNCTION__))
;
1362
1363 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1364
1365 // Guarantee that all emitted copies are stuck together with flags.
1366 Flag = Chain.getValue(1);
1367 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1368 }
1369
1370 // Don't emit the ret/reti instruction when the naked attribute is present in
1371 // the function being compiled.
1372 if (MF.getFunction().getAttributes().hasAttribute(
1373 AttributeList::FunctionIndex, Attribute::Naked)) {
1374 return Chain;
1375 }
1376
1377 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1378
1379 unsigned RetOpc =
1380 AFI->isInterruptOrSignalHandler()
1381 ? AVRISD::RETI_FLAG
1382 : AVRISD::RET_FLAG;
1383
1384 RetOps[0] = Chain; // Update chain.
1385
1386 if (Flag.getNode()) {
1387 RetOps.push_back(Flag);
1388 }
1389
1390 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1391}
1392
1393//===----------------------------------------------------------------------===//
1394// Custom Inserters
1395//===----------------------------------------------------------------------===//
1396
1397MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1398 MachineBasicBlock *BB) const {
1399 unsigned Opc;
1400 const TargetRegisterClass *RC;
1401 bool HasRepeatedOperand = false;
1402 MachineFunction *F = BB->getParent();
1403 MachineRegisterInfo &RI = F->getRegInfo();
1404 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1405 DebugLoc dl = MI.getDebugLoc();
1406
1407 switch (MI.getOpcode()) {
1408 default:
1409 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1409)
;
1410 case AVR::Lsl8:
1411 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1412 RC = &AVR::GPR8RegClass;
1413 HasRepeatedOperand = true;
1414 break;
1415 case AVR::Lsl16:
1416 Opc = AVR::LSLWRd;
1417 RC = &AVR::DREGSRegClass;
1418 break;
1419 case AVR::Asr8:
1420 Opc = AVR::ASRRd;
1421 RC = &AVR::GPR8RegClass;
1422 break;
1423 case AVR::Asr16:
1424 Opc = AVR::ASRWRd;
1425 RC = &AVR::DREGSRegClass;
1426 break;
1427 case AVR::Lsr8:
1428 Opc = AVR::LSRRd;
1429 RC = &AVR::GPR8RegClass;
1430 break;
1431 case AVR::Lsr16:
1432 Opc = AVR::LSRWRd;
1433 RC = &AVR::DREGSRegClass;
1434 break;
1435 case AVR::Rol8:
1436 Opc = AVR::ROLBRd;
1437 RC = &AVR::GPR8RegClass;
1438 break;
1439 case AVR::Rol16:
1440 Opc = AVR::ROLWRd;
1441 RC = &AVR::DREGSRegClass;
1442 break;
1443 case AVR::Ror8:
1444 Opc = AVR::RORBRd;
1445 RC = &AVR::GPR8RegClass;
1446 break;
1447 case AVR::Ror16:
1448 Opc = AVR::RORWRd;
1449 RC = &AVR::DREGSRegClass;
1450 break;
1451 }
1452
1453 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1454
1455 MachineFunction::iterator I;
1456 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1457 if (I != F->end()) ++I;
1458
1459 // Create loop block.
1460 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1461 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1462
1463 F->insert(I, LoopBB);
1464 F->insert(I, RemBB);
1465
1466 // Update machine-CFG edges by transferring all successors of the current
1467 // block to the block containing instructions after shift.
1468 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1469 BB->end());
1470 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1471
1472 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1473 BB->addSuccessor(LoopBB);
1474 BB->addSuccessor(RemBB);
1475 LoopBB->addSuccessor(RemBB);
1476 LoopBB->addSuccessor(LoopBB);
1477
1478 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1479 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1480 Register ShiftReg = RI.createVirtualRegister(RC);
1481 Register ShiftReg2 = RI.createVirtualRegister(RC);
1482 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1483 Register SrcReg = MI.getOperand(1).getReg();
1484 Register DstReg = MI.getOperand(0).getReg();
1485
1486 // BB:
1487 // cpi N, 0
1488 // breq RemBB
1489 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1490 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1491
1492 // LoopBB:
1493 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1494 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1495 // ShiftReg2 = shift ShiftReg
1496 // ShiftAmt2 = ShiftAmt - 1;
1497 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1498 .addReg(SrcReg)
1499 .addMBB(BB)
1500 .addReg(ShiftReg2)
1501 .addMBB(LoopBB);
1502 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1503 .addReg(ShiftAmtSrcReg)
1504 .addMBB(BB)
1505 .addReg(ShiftAmtReg2)
1506 .addMBB(LoopBB);
1507
1508 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1509 if (HasRepeatedOperand)
1510 ShiftMI.addReg(ShiftReg);
1511
1512 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1513 .addReg(ShiftAmtReg)
1514 .addImm(1);
1515 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1516
1517 // RemBB:
1518 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1519 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1520 .addReg(SrcReg)
1521 .addMBB(BB)
1522 .addReg(ShiftReg2)
1523 .addMBB(LoopBB);
1524
1525 MI.eraseFromParent(); // The pseudo instruction is gone now.
1526 return RemBB;
1527}
1528
1529static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
1530 if (I->getOpcode() == AVR::COPY) {
1531 Register SrcReg = I->getOperand(1).getReg();
1532 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1533 }
1534
1535 return false;
1536}
1537
1538// The mul instructions wreak havock on our zero_reg R1. We need to clear it
1539// after the result has been evacuated. This is probably not the best way to do
1540// it, but it works for now.
1541MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1542 MachineBasicBlock *BB) const {
1543 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1544 MachineBasicBlock::iterator I(MI);
1545 ++I; // in any case insert *after* the mul instruction
1546 if (isCopyMulResult(I))
1547 ++I;
1548 if (isCopyMulResult(I))
1549 ++I;
1550 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1551 .addReg(AVR::R1)
1552 .addReg(AVR::R1);
1553 return BB;
1554}
1555
1556MachineBasicBlock *
1557AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1558 MachineBasicBlock *MBB) const {
1559 int Opc = MI.getOpcode();
1560
1561 // Pseudo shift instructions with a non constant shift amount are expanded
1562 // into a loop.
1563 switch (Opc) {
1564 case AVR::Lsl8:
1565 case AVR::Lsl16:
1566 case AVR::Lsr8:
1567 case AVR::Lsr16:
1568 case AVR::Rol8:
1569 case AVR::Rol16:
1570 case AVR::Ror8:
1571 case AVR::Ror16:
1572 case AVR::Asr8:
1573 case AVR::Asr16:
1574 return insertShift(MI, MBB);
1575 case AVR::MULRdRr:
1576 case AVR::MULSRdRr:
1577 return insertMul(MI, MBB);
1578 }
1579
1580 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1581, __PRETTY_FUNCTION__))
1581 "Unexpected instr type to insert")(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1581, __PRETTY_FUNCTION__))
;
1582
1583 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1584 ->getParent()
1585 ->getSubtarget()
1586 .getInstrInfo();
1587 DebugLoc dl = MI.getDebugLoc();
1588
1589 // To "insert" a SELECT instruction, we insert the diamond
1590 // control-flow pattern. The incoming instruction knows the
1591 // destination vreg to set, the condition code register to branch
1592 // on, the true/false values to select between, and a branch opcode
1593 // to use.
1594
1595 MachineFunction *MF = MBB->getParent();
1596 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1597 MachineBasicBlock *FallThrough = MBB->getFallThrough();
1598
1599 // If the current basic block falls through to another basic block,
1600 // we must insert an unconditional branch to the fallthrough destination
1601 // if we are to insert basic blocks at the prior fallthrough point.
1602 if (FallThrough != nullptr) {
1603 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1604 }
1605
1606 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1607 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1608
1609 MachineFunction::iterator I;
1610 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1611 if (I != MF->end()) ++I;
1612 MF->insert(I, trueMBB);
1613 MF->insert(I, falseMBB);
1614
1615 // Transfer remaining instructions and all successors of the current
1616 // block to the block which will contain the Phi node for the
1617 // select.
1618 trueMBB->splice(trueMBB->begin(), MBB,
1619 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1620 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1621
1622 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1623 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1624 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1625 MBB->addSuccessor(falseMBB);
1626 MBB->addSuccessor(trueMBB);
1627
1628 // Unconditionally flow back to the true block
1629 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1630 falseMBB->addSuccessor(trueMBB);
1631
1632 // Set up the Phi node to determine where we came from
1633 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1634 .addReg(MI.getOperand(1).getReg())
1635 .addMBB(MBB)
1636 .addReg(MI.getOperand(2).getReg())
1637 .addMBB(falseMBB) ;
1638
1639 MI.eraseFromParent(); // The pseudo instruction is gone now.
1640 return trueMBB;
1641}
1642
1643//===----------------------------------------------------------------------===//
1644// Inline Asm Support
1645//===----------------------------------------------------------------------===//
1646
1647AVRTargetLowering::ConstraintType
1648AVRTargetLowering::getConstraintType(StringRef Constraint) const {
1649 if (Constraint.size() == 1) {
1650 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1651 switch (Constraint[0]) {
1652 default:
1653 break;
1654 case 'a': // Simple upper registers
1655 case 'b': // Base pointer registers pairs
1656 case 'd': // Upper register
1657 case 'l': // Lower registers
1658 case 'e': // Pointer register pairs
1659 case 'q': // Stack pointer register
1660 case 'r': // Any register
1661 case 'w': // Special upper register pairs
1662 return C_RegisterClass;
1663 case 't': // Temporary register
1664 case 'x': case 'X': // Pointer register pair X
1665 case 'y': case 'Y': // Pointer register pair Y
1666 case 'z': case 'Z': // Pointer register pair Z
1667 return C_Register;
1668 case 'Q': // A memory address based on Y or Z pointer with displacement.
1669 return C_Memory;
1670 case 'G': // Floating point constant
1671 case 'I': // 6-bit positive integer constant
1672 case 'J': // 6-bit negative integer constant
1673 case 'K': // Integer constant (Range: 2)
1674 case 'L': // Integer constant (Range: 0)
1675 case 'M': // 8-bit integer constant
1676 case 'N': // Integer constant (Range: -1)
1677 case 'O': // Integer constant (Range: 8, 16, 24)
1678 case 'P': // Integer constant (Range: 1)
1679 case 'R': // Integer constant (Range: -6 to 5)x
1680 return C_Immediate;
1681 }
1682 }
1683
1684 return TargetLowering::getConstraintType(Constraint);
1685}
1686
1687unsigned
1688AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
1689 // Not sure if this is actually the right thing to do, but we got to do
1690 // *something* [agnat]
1691 switch (ConstraintCode[0]) {
1692 case 'Q':
1693 return InlineAsm::Constraint_Q;
1694 }
1695 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1696}
1697
1698AVRTargetLowering::ConstraintWeight
1699AVRTargetLowering::getSingleConstraintMatchWeight(
1700 AsmOperandInfo &info, const char *constraint) const {
1701 ConstraintWeight weight = CW_Invalid;
1702 Value *CallOperandVal = info.CallOperandVal;
1703
1704 // If we don't have a value, we can't do a match,
1705 // but allow it at the lowest weight.
1706 // (this behaviour has been copied from the ARM backend)
1707 if (!CallOperandVal) {
1708 return CW_Default;
1709 }
1710
1711 // Look at the constraint type.
1712 switch (*constraint) {
1713 default:
1714 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1715 break;
1716 case 'd':
1717 case 'r':
1718 case 'l':
1719 weight = CW_Register;
1720 break;
1721 case 'a':
1722 case 'b':
1723 case 'e':
1724 case 'q':
1725 case 't':
1726 case 'w':
1727 case 'x': case 'X':
1728 case 'y': case 'Y':
1729 case 'z': case 'Z':
1730 weight = CW_SpecificReg;
1731 break;
1732 case 'G':
1733 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1734 if (C->isZero()) {
1735 weight = CW_Constant;
1736 }
1737 }
1738 break;
1739 case 'I':
1740 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1741 if (isUInt<6>(C->getZExtValue())) {
1742 weight = CW_Constant;
1743 }
1744 }
1745 break;
1746 case 'J':
1747 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1748 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1749 weight = CW_Constant;
1750 }
1751 }
1752 break;
1753 case 'K':
1754 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1755 if (C->getZExtValue() == 2) {
1756 weight = CW_Constant;
1757 }
1758 }
1759 break;
1760 case 'L':
1761 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1762 if (C->getZExtValue() == 0) {
1763 weight = CW_Constant;
1764 }
1765 }
1766 break;
1767 case 'M':
1768 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1769 if (isUInt<8>(C->getZExtValue())) {
1770 weight = CW_Constant;
1771 }
1772 }
1773 break;
1774 case 'N':
1775 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1776 if (C->getSExtValue() == -1) {
1777 weight = CW_Constant;
1778 }
1779 }
1780 break;
1781 case 'O':
1782 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1783 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1784 (C->getZExtValue() == 24)) {
1785 weight = CW_Constant;
1786 }
1787 }
1788 break;
1789 case 'P':
1790 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1791 if (C->getZExtValue() == 1) {
1792 weight = CW_Constant;
1793 }
1794 }
1795 break;
1796 case 'R':
1797 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1798 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1799 weight = CW_Constant;
1800 }
1801 }
1802 break;
1803 case 'Q':
1804 weight = CW_Memory;
1805 break;
1806 }
1807
1808 return weight;
1809}
1810
1811std::pair<unsigned, const TargetRegisterClass *>
1812AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1813 StringRef Constraint,
1814 MVT VT) const {
1815 // We only support i8 and i16.
1816 //
1817 //:FIXME: remove this assert for now since it gets sometimes executed
1818 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1819
1820 if (Constraint.size() == 1) {
1821 switch (Constraint[0]) {
1822 case 'a': // Simple upper registers r16..r23.
1823 return std::make_pair(0U, &AVR::LD8loRegClass);
1824 case 'b': // Base pointer registers: y, z.
1825 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1826 case 'd': // Upper registers r16..r31.
1827 return std::make_pair(0U, &AVR::LD8RegClass);
1828 case 'l': // Lower registers r0..r15.
1829 return std::make_pair(0U, &AVR::GPR8loRegClass);
1830 case 'e': // Pointer register pairs: x, y, z.
1831 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1832 case 'q': // Stack pointer register: SPH:SPL.
1833 return std::make_pair(0U, &AVR::GPRSPRegClass);
1834 case 'r': // Any register: r0..r31.
1835 if (VT == MVT::i8)
1836 return std::make_pair(0U, &AVR::GPR8RegClass);
1837
1838 assert(VT == MVT::i16 && "inline asm constraint too large")((VT == MVT::i16 && "inline asm constraint too large"
) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i16 && \"inline asm constraint too large\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1838, __PRETTY_FUNCTION__))
;
1839 return std::make_pair(0U, &AVR::DREGSRegClass);
1840 case 't': // Temporary register: r0.
1841 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1842 case 'w': // Special upper register pairs: r24, r26, r28, r30.
1843 return std::make_pair(0U, &AVR::IWREGSRegClass);
1844 case 'x': // Pointer register pair X: r27:r26.
1845 case 'X':
1846 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1847 case 'y': // Pointer register pair Y: r29:r28.
1848 case 'Y':
1849 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1850 case 'z': // Pointer register pair Z: r31:r30.
1851 case 'Z':
1852 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1853 default:
1854 break;
1855 }
1856 }
1857
1858 return TargetLowering::getRegForInlineAsmConstraint(
1859 Subtarget.getRegisterInfo(), Constraint, VT);
1860}
1861
1862void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1863 std::string &Constraint,
1864 std::vector<SDValue> &Ops,
1865 SelectionDAG &DAG) const {
1866 SDValue Result(0, 0);
1867 SDLoc DL(Op);
1868 EVT Ty = Op.getValueType();
1869
1870 // Currently only support length 1 constraints.
1871 if (Constraint.length() != 1) {
1872 return;
1873 }
1874
1875 char ConstraintLetter = Constraint[0];
1876 switch (ConstraintLetter) {
1877 default:
1878 break;
1879 // Deal with integers first:
1880 case 'I':
1881 case 'J':
1882 case 'K':
1883 case 'L':
1884 case 'M':
1885 case 'N':
1886 case 'O':
1887 case 'P':
1888 case 'R': {
1889 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1890 if (!C) {
1891 return;
1892 }
1893
1894 int64_t CVal64 = C->getSExtValue();
1895 uint64_t CUVal64 = C->getZExtValue();
1896 switch (ConstraintLetter) {
1897 case 'I': // 0..63
1898 if (!isUInt<6>(CUVal64))
1899 return;
1900 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1901 break;
1902 case 'J': // -63..0
1903 if (CVal64 < -63 || CVal64 > 0)
1904 return;
1905 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1906 break;
1907 case 'K': // 2
1908 if (CUVal64 != 2)
1909 return;
1910 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1911 break;
1912 case 'L': // 0
1913 if (CUVal64 != 0)
1914 return;
1915 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1916 break;
1917 case 'M': // 0..255
1918 if (!isUInt<8>(CUVal64))
1919 return;
1920 // i8 type may be printed as a negative number,
1921 // e.g. 254 would be printed as -2,
1922 // so we force it to i16 at least.
1923 if (Ty.getSimpleVT() == MVT::i8) {
1924 Ty = MVT::i16;
1925 }
1926 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1927 break;
1928 case 'N': // -1
1929 if (CVal64 != -1)
1930 return;
1931 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1932 break;
1933 case 'O': // 8, 16, 24
1934 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1935 return;
1936 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1937 break;
1938 case 'P': // 1
1939 if (CUVal64 != 1)
1940 return;
1941 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1942 break;
1943 case 'R': // -6..5
1944 if (CVal64 < -6 || CVal64 > 5)
1945 return;
1946 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1947 break;
1948 }
1949
1950 break;
1951 }
1952 case 'G':
1953 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
1954 if (!FC || !FC->isZero())
1955 return;
1956 // Soften float to i8 0
1957 Result = DAG.getTargetConstant(0, DL, MVT::i8);
1958 break;
1959 }
1960
1961 if (Result.getNode()) {
1962 Ops.push_back(Result);
1963 return;
1964 }
1965
1966 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1967}
1968
1969Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1970 const MachineFunction &MF) const {
1971 Register Reg;
1972
1973 if (VT == LLT::scalar(8)) {
1974 Reg = StringSwitch<unsigned>(RegName)
1975 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1976 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1977 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1978 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1979 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1980 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1981 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1982 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1983 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
1984 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
1985 .Case("r30", AVR::R30).Case("r31", AVR::R31)
1986 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1987 .Default(0);
1988 } else {
1989 Reg = StringSwitch<unsigned>(RegName)
1990 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
1991 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
1992 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
1993 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
1994 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
1995 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
1996 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
1997 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
1998 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1999 .Default(0);
2000 }
2001
2002 if (Reg)
2003 return Reg;
2004
2005 report_fatal_error("Invalid register name global variable");
2006}
2007
2008} // end of namespace llvm

/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h

1//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of machine-level target independent types which
10// legal values in the code generator use.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H
15#define LLVM_SUPPORT_MACHINEVALUETYPE_H
16
17#include "llvm/ADT/iterator_range.h"
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Support/MathExtras.h"
20#include "llvm/Support/TypeSize.h"
21#include <cassert>
22
23namespace llvm {
24
25 class Type;
26
27 /// Machine Value Type. Every type that is supported natively by some
28 /// processor targeted by LLVM occurs here. This means that any legal value
29 /// type can be represented by an MVT.
30 class MVT {
31 public:
32 enum SimpleValueType : uint8_t {
33 // Simple value types that aren't explicitly part of this enumeration
34 // are considered extended value types.
35 INVALID_SIMPLE_VALUE_TYPE = 0,
36
37 // If you change this numbering, you must change the values in
38 // ValueTypes.td as well!
39 Other = 1, // This is a non-standard value
40 i1 = 2, // This is a 1 bit integer value
41 i8 = 3, // This is an 8 bit integer value
42 i16 = 4, // This is a 16 bit integer value
43 i32 = 5, // This is a 32 bit integer value
44 i64 = 6, // This is a 64 bit integer value
45 i128 = 7, // This is a 128 bit integer value
46
47 FIRST_INTEGER_VALUETYPE = i1,
48 LAST_INTEGER_VALUETYPE = i128,
49
50 bf16 = 8, // This is a 16 bit brain floating point value
51 f16 = 9, // This is a 16 bit floating point value
52 f32 = 10, // This is a 32 bit floating point value
53 f64 = 11, // This is a 64 bit floating point value
54 f80 = 12, // This is a 80 bit floating point value
55 f128 = 13, // This is a 128 bit floating point value
56 ppcf128 = 14, // This is a PPC 128-bit floating point value
57
58 FIRST_FP_VALUETYPE = bf16,
59 LAST_FP_VALUETYPE = ppcf128,
60
61 v1i1 = 15, // 1 x i1
62 v2i1 = 16, // 2 x i1
63 v4i1 = 17, // 4 x i1
64 v8i1 = 18, // 8 x i1
65 v16i1 = 19, // 16 x i1
66 v32i1 = 20, // 32 x i1
67 v64i1 = 21, // 64 x i1
68 v128i1 = 22, // 128 x i1
69 v256i1 = 23, // 256 x i1
70 v512i1 = 24, // 512 x i1
71 v1024i1 = 25, // 1024 x i1
72
73 v1i8 = 26, // 1 x i8
74 v2i8 = 27, // 2 x i8
75 v4i8 = 28, // 4 x i8
76 v8i8 = 29, // 8 x i8
77 v16i8 = 30, // 16 x i8
78 v32i8 = 31, // 32 x i8
79 v64i8 = 32, // 64 x i8
80 v128i8 = 33, //128 x i8
81 v256i8 = 34, //256 x i8
82
83 v1i16 = 35, // 1 x i16
84 v2i16 = 36, // 2 x i16
85 v3i16 = 37, // 3 x i16
86 v4i16 = 38, // 4 x i16
87 v8i16 = 39, // 8 x i16
88 v16i16 = 40, // 16 x i16
89 v32i16 = 41, // 32 x i16
90 v64i16 = 42, // 64 x i16
91 v128i16 = 43, //128 x i16
92
93 v1i32 = 44, // 1 x i32
94 v2i32 = 45, // 2 x i32
95 v3i32 = 46, // 3 x i32
96 v4i32 = 47, // 4 x i32
97 v5i32 = 48, // 5 x i32
98 v8i32 = 49, // 8 x i32
99 v16i32 = 50, // 16 x i32
100 v32i32 = 51, // 32 x i32
101 v64i32 = 52, // 64 x i32
102 v128i32 = 53, // 128 x i32
103 v256i32 = 54, // 256 x i32
104 v512i32 = 55, // 512 x i32
105 v1024i32 = 56, // 1024 x i32
106 v2048i32 = 57, // 2048 x i32
107
108 v1i64 = 58, // 1 x i64
109 v2i64 = 59, // 2 x i64
110 v4i64 = 60, // 4 x i64
111 v8i64 = 61, // 8 x i64
112 v16i64 = 62, // 16 x i64
113 v32i64 = 63, // 32 x i64
114
115 v1i128 = 64, // 1 x i128
116
117 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
118 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
119
120 v2f16 = 65, // 2 x f16
121 v3f16 = 66, // 3 x f16
122 v4f16 = 67, // 4 x f16
123 v8f16 = 68, // 8 x f16
124 v16f16 = 69, // 16 x f16
125 v32f16 = 70, // 32 x f16
126 v64f16 = 71, // 64 x f16
127 v128f16 = 72, // 128 x f16
128 v2bf16 = 73, // 2 x bf16
129 v3bf16 = 74, // 3 x bf16
130 v4bf16 = 75, // 4 x bf16
131 v8bf16 = 76, // 8 x bf16
132 v16bf16 = 77, // 16 x bf16
133 v32bf16 = 78, // 32 x bf16
134 v64bf16 = 79, // 64 x bf16
135 v128bf16 = 80, // 128 x bf16
136 v1f32 = 81, // 1 x f32
137 v2f32 = 82, // 2 x f32
138 v3f32 = 83, // 3 x f32
139 v4f32 = 84, // 4 x f32
140 v5f32 = 85, // 5 x f32
141 v8f32 = 86, // 8 x f32
142 v16f32 = 87, // 16 x f32
143 v32f32 = 88, // 32 x f32
144 v64f32 = 89, // 64 x f32
145 v128f32 = 90, // 128 x f32
146 v256f32 = 91, // 256 x f32
147 v512f32 = 92, // 512 x f32
148 v1024f32 = 93, // 1024 x f32
149 v2048f32 = 94, // 2048 x f32
150 v1f64 = 95, // 1 x f64
151 v2f64 = 96, // 2 x f64
152 v4f64 = 97, // 4 x f64
153 v8f64 = 98, // 8 x f64
154 v16f64 = 99, // 16 x f64
155 v32f64 = 100, // 32 x f64
156
157 FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v2f16,
158 LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v32f64,
159
160 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
161 LAST_FIXEDLEN_VECTOR_VALUETYPE = v32f64,
162
163 nxv1i1 = 101, // n x 1 x i1
164 nxv2i1 = 102, // n x 2 x i1
165 nxv4i1 = 103, // n x 4 x i1
166 nxv8i1 = 104, // n x 8 x i1
167 nxv16i1 = 105, // n x 16 x i1
168 nxv32i1 = 106, // n x 32 x i1
169 nxv64i1 = 107, // n x 64 x i1
170
171 nxv1i8 = 108, // n x 1 x i8
172 nxv2i8 = 109, // n x 2 x i8
173 nxv4i8 = 110, // n x 4 x i8
174 nxv8i8 = 111, // n x 8 x i8
175 nxv16i8 = 112, // n x 16 x i8
176 nxv32i8 = 113, // n x 32 x i8
177 nxv64i8 = 114, // n x 64 x i8
178
179 nxv1i16 = 115, // n x 1 x i16
180 nxv2i16 = 116, // n x 2 x i16
181 nxv4i16 = 117, // n x 4 x i16
182 nxv8i16 = 118, // n x 8 x i16
183 nxv16i16 = 119, // n x 16 x i16
184 nxv32i16 = 120, // n x 32 x i16
185
186 nxv1i32 = 121, // n x 1 x i32
187 nxv2i32 = 122, // n x 2 x i32
188 nxv4i32 = 123, // n x 4 x i32
189 nxv8i32 = 124, // n x 8 x i32
190 nxv16i32 = 125, // n x 16 x i32
191 nxv32i32 = 126, // n x 32 x i32
192
193 nxv1i64 = 127, // n x 1 x i64
194 nxv2i64 = 128, // n x 2 x i64
195 nxv4i64 = 129, // n x 4 x i64
196 nxv8i64 = 130, // n x 8 x i64
197 nxv16i64 = 131, // n x 16 x i64
198 nxv32i64 = 132, // n x 32 x i64
199
200 FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
201 LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
202
203 nxv1f16 = 133, // n x 1 x f16
204 nxv2f16 = 134, // n x 2 x f16
205 nxv4f16 = 135, // n x 4 x f16
206 nxv8f16 = 136, // n x 8 x f16
207 nxv16f16 = 137, // n x 16 x f16
208 nxv32f16 = 138, // n x 32 x f16
209 nxv2bf16 = 139, // n x 2 x bf16
210 nxv4bf16 = 140, // n x 4 x bf16
211 nxv8bf16 = 141, // n x 8 x bf16
212 nxv1f32 = 142, // n x 1 x f32
213 nxv2f32 = 143, // n x 2 x f32
214 nxv4f32 = 144, // n x 4 x f32
215 nxv8f32 = 145, // n x 8 x f32
216 nxv16f32 = 146, // n x 16 x f32
217 nxv1f64 = 147, // n x 1 x f64
218 nxv2f64 = 148, // n x 2 x f64
219 nxv4f64 = 149, // n x 4 x f64
220 nxv8f64 = 150, // n x 8 x f64
221
222 FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
223 LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
224
225 FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
226 LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
227
228 FIRST_VECTOR_VALUETYPE = v1i1,
229 LAST_VECTOR_VALUETYPE = nxv8f64,
230
231 x86mmx = 151, // This is an X86 MMX value
232
233 Glue = 152, // This glues nodes together during pre-RA sched
234
235 isVoid = 153, // This has no value
236
237 Untyped = 154, // This value takes a register, but has
238 // unspecified type. The register class
239 // will be determined by the opcode.
240
241 exnref = 155, // WebAssembly's exnref type
242
243 FIRST_VALUETYPE = 1, // This is always the beginning of the list.
244 LAST_VALUETYPE = 156, // This always remains at the end of the list.
245
246 // This is the current maximum for LAST_VALUETYPE.
247 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
248 // This value must be a multiple of 32.
249 MAX_ALLOWED_VALUETYPE = 160,
250
251 // A value of type llvm::TokenTy
252 token = 248,
253
254 // This is MDNode or MDString.
255 Metadata = 249,
256
257 // An int value the size of the pointer of the current
258 // target to any address space. This must only be used internal to
259 // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR.
260 iPTRAny = 250,
261
262 // A vector with any length and element size. This is used
263 // for intrinsics that have overloadings based on vector types.
264 // This is only for tblgen's consumption!
265 vAny = 251,
266
267 // Any floating-point or vector floating-point value. This is used
268 // for intrinsics that have overloadings based on floating-point types.
269 // This is only for tblgen's consumption!
270 fAny = 252,
271
272 // An integer or vector integer value of any bit width. This is
273 // used for intrinsics that have overloadings based on integer bit widths.
274 // This is only for tblgen's consumption!
275 iAny = 253,
276
277 // An int value the size of the pointer of the current
278 // target. This should only be used internal to tblgen!
279 iPTR = 254,
280
281 // Any type. This is used for intrinsics that have overloadings.
282 // This is only for tblgen's consumption!
283 Any = 255
284 };
285
286 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;
287
288 constexpr MVT() = default;
289 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}
290
291 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
292 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
293 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
10
Assuming 'SimpleTy' is equal to 'S.SimpleTy'
11
Returning the value 1, which participates in a condition later
294 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
295 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
296 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
297
298 /// Return true if this is a valid simple valuetype.
299 bool isValid() const {
300 return (SimpleTy >= MVT::FIRST_VALUETYPE &&
301 SimpleTy < MVT::LAST_VALUETYPE);
302 }
303
304 /// Return true if this is a FP or a vector FP type.
305 bool isFloatingPoint() const {
306 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
307 SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
308 (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE &&
309 SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) ||
310 (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE &&
311 SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE));
312 }
313
314 /// Return true if this is an integer or a vector integer type.
315 bool isInteger() const {
316 return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
317 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
318 (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
319 SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
320 (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
321 SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
322 }
323
324 /// Return true if this is an integer, not including vectors.
325 bool isScalarInteger() const {
326 return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
327 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
328 }
329
330 /// Return true if this is a vector value type.
331 bool isVector() const {
332 return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
333 SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
334 }
335
336 /// Return true if this is a vector value type where the
337 /// runtime length is machine dependent
338 bool isScalableVector() const {
339 return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE &&
340 SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
341 }
342
343 bool isFixedLengthVector() const {
344 return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
345 SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
346 }
347
348 /// Return true if this is a 16-bit vector type.
349 bool is16BitVector() const {
350 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 ||
351 SimpleTy == MVT::v16i1);
352 }
353
354 /// Return true if this is a 32-bit vector type.
355 bool is32BitVector() const {
356 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
357 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 ||
358 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
359 SimpleTy == MVT::v1f32);
360 }
361
362 /// Return true if this is a 64-bit vector type.
363 bool is64BitVector() const {
364 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
365 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 ||
366 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 ||
367 SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 ||
368 SimpleTy == MVT::v1f64);
369 }
370
371 /// Return true if this is a 128-bit vector type.
372 bool is128BitVector() const {
373 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 ||
374 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
375 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
376 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 ||
377 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
378 }
379
380 /// Return true if this is a 256-bit vector type.
381 bool is256BitVector() const {
382 return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
383 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
384 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
385 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 ||
386 SimpleTy == MVT::v256i1);
387 }
388
389 /// Return true if this is a 512-bit vector type.
390 bool is512BitVector() const {
391 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 ||
392 SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 ||
393 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 ||
394 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
395 SimpleTy == MVT::v8i64);
396 }
397
398 /// Return true if this is a 1024-bit vector type.
399 bool is1024BitVector() const {
400 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 ||
401 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 ||
402 SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 ||
403 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 ||
404 SimpleTy == MVT::v64bf16);
405 }
406
407 /// Return true if this is a 2048-bit vector type.
408 bool is2048BitVector() const {
409 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
410 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 ||
411 SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 ||
412 SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16);
413 }
414
415 /// Return true if this is an overloaded type for TableGen.
416 bool isOverloaded() const {
417 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
418 SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
419 SimpleTy == MVT::iPTRAny);
420 }
421
422 /// Return a VT for a vector type with the same element type but
423 /// half the number of elements.
424 MVT getHalfNumVectorElementsVT() const {
425 MVT EltVT = getVectorElementType();
426 auto EltCnt = getVectorElementCount();
427 assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")((EltCnt.isKnownEven() && "Splitting vector, but not in half!"
) ? static_cast<void> (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 427, __PRETTY_FUNCTION__))
;
428 return getVectorVT(EltVT, EltCnt / 2);
429 }
430
431 /// Returns true if the given vector is a power of 2.
432 bool isPow2VectorType() const {
433 unsigned NElts = getVectorNumElements();
434 return !(NElts & (NElts - 1));
435 }
436
437 /// Widens the length of the given vector MVT up to the nearest power of 2
438 /// and returns that type.
439 MVT getPow2VectorType() const {
440 if (isPow2VectorType())
441 return *this;
442
443 unsigned NElts = getVectorNumElements();
444 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
445 return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
446 }
447
448 /// If this is a vector, return the element type, otherwise return this.
449 MVT getScalarType() const {
450 return isVector() ? getVectorElementType() : *this;
451 }
452
453 MVT getVectorElementType() const {
454 switch (SimpleTy) {
455 default:
456 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 456)
;
457 case v1i1:
458 case v2i1:
459 case v4i1:
460 case v8i1:
461 case v16i1:
462 case v32i1:
463 case v64i1:
464 case v128i1:
465 case v256i1:
466 case v512i1:
467 case v1024i1:
468 case nxv1i1:
469 case nxv2i1:
470 case nxv4i1:
471 case nxv8i1:
472 case nxv16i1:
473 case nxv32i1:
474 case nxv64i1: return i1;
475 case v1i8:
476 case v2i8:
477 case v4i8:
478 case v8i8:
479 case v16i8:
480 case v32i8:
481 case v64i8:
482 case v128i8:
483 case v256i8:
484 case nxv1i8:
485 case nxv2i8:
486 case nxv4i8:
487 case nxv8i8:
488 case nxv16i8:
489 case nxv32i8:
490 case nxv64i8: return i8;
491 case v1i16:
492 case v2i16:
493 case v3i16:
494 case v4i16:
495 case v8i16:
496 case v16i16:
497 case v32i16:
498 case v64i16:
499 case v128i16:
500 case nxv1i16:
501 case nxv2i16:
502 case nxv4i16:
503 case nxv8i16:
504 case nxv16i16:
505 case nxv32i16: return i16;
506 case v1i32:
507 case v2i32:
508 case v3i32:
509 case v4i32:
510 case v5i32:
511 case v8i32:
512 case v16i32:
513 case v32i32:
514 case v64i32:
515 case v128i32:
516 case v256i32:
517 case v512i32:
518 case v1024i32:
519 case v2048i32:
520 case nxv1i32:
521 case nxv2i32:
522 case nxv4i32:
523 case nxv8i32:
524 case nxv16i32:
525 case nxv32i32: return i32;
526 case v1i64:
527 case v2i64:
528 case v4i64:
529 case v8i64:
530 case v16i64:
531 case v32i64:
532 case nxv1i64:
533 case nxv2i64:
534 case nxv4i64:
535 case nxv8i64:
536 case nxv16i64:
537 case nxv32i64: return i64;
538 case v1i128: return i128;
539 case v2f16:
540 case v3f16:
541 case v4f16:
542 case v8f16:
543 case v16f16:
544 case v32f16:
545 case v64f16:
546 case v128f16:
547 case nxv1f16:
548 case nxv2f16:
549 case nxv4f16:
550 case nxv8f16:
551 case nxv16f16:
552 case nxv32f16: return f16;
553 case v2bf16:
554 case v3bf16:
555 case v4bf16:
556 case v8bf16:
557 case v16bf16:
558 case v32bf16:
559 case v64bf16:
560 case v128bf16:
561 case nxv2bf16:
562 case nxv4bf16:
563 case nxv8bf16: return bf16;
564 case v1f32:
565 case v2f32:
566 case v3f32:
567 case v4f32:
568 case v5f32:
569 case v8f32:
570 case v16f32:
571 case v32f32:
572 case v64f32:
573 case v128f32:
574 case v256f32:
575 case v512f32:
576 case v1024f32:
577 case v2048f32:
578 case nxv1f32:
579 case nxv2f32:
580 case nxv4f32:
581 case nxv8f32:
582 case nxv16f32: return f32;
583 case v1f64:
584 case v2f64:
585 case v4f64:
586 case v8f64:
587 case v16f64:
588 case v32f64:
589 case nxv1f64:
590 case nxv2f64:
591 case nxv4f64:
592 case nxv8f64: return f64;
593 }
594 }
595
596 unsigned getVectorNumElements() const {
597 switch (SimpleTy) {
598 default:
599 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 599)
;
600 case v2048i32:
601 case v2048f32: return 2048;
602 case v1024i1:
603 case v1024i32:
604 case v1024f32: return 1024;
605 case v512i1:
606 case v512i32:
607 case v512f32: return 512;
608 case v256i1:
609 case v256i8:
610 case v256i32:
611 case v256f32: return 256;
612 case v128i1:
613 case v128i8:
614 case v128i16:
615 case v128i32:
616 case v128f16:
617 case v128bf16:
618 case v128f32: return 128;
619 case v64i1:
620 case v64i8:
621 case v64i16:
622 case v64i32:
623 case v64f16:
624 case v64bf16:
625 case v64f32:
626 case nxv64i1:
627 case nxv64i8: return 64;
628 case v32i1:
629 case v32i8:
630 case v32i16:
631 case v32i32:
632 case v32i64:
633 case v32f16:
634 case v32bf16:
635 case v32f32:
636 case v32f64:
637 case nxv32i1:
638 case nxv32i8:
639 case nxv32i16:
640 case nxv32i32:
641 case nxv32i64:
642 case nxv32f16: return 32;
643 case v16i1:
644 case v16i8:
645 case v16i16:
646 case v16i32:
647 case v16i64:
648 case v16f16:
649 case v16bf16:
650 case v16f32:
651 case v16f64:
652 case nxv16i1:
653 case nxv16i8:
654 case nxv16i16:
655 case nxv16i32:
656 case nxv16i64:
657 case nxv16f16:
658 case nxv16f32: return 16;
659 case v8i1:
660 case v8i8:
661 case v8i16:
662 case v8i32:
663 case v8i64:
664 case v8f16:
665 case v8bf16:
666 case v8f32:
667 case v8f64:
668 case nxv8i1:
669 case nxv8i8:
670 case nxv8i16:
671 case nxv8i32:
672 case nxv8i64:
673 case nxv8f16:
674 case nxv8bf16:
675 case nxv8f32:
676 case nxv8f64: return 8;
677 case v5i32:
678 case v5f32: return 5;
679 case v4i1:
680 case v4i8:
681 case v4i16:
682 case v4i32:
683 case v4i64:
684 case v4f16:
685 case v4bf16:
686 case v4f32:
687 case v4f64:
688 case nxv4i1:
689 case nxv4i8:
690 case nxv4i16:
691 case nxv4i32:
692 case nxv4i64:
693 case nxv4f16:
694 case nxv4bf16:
695 case nxv4f32:
696 case nxv4f64: return 4;
697 case v3i16:
698 case v3i32:
699 case v3f16:
700 case v3bf16:
701 case v3f32: return 3;
702 case v2i1:
703 case v2i8:
704 case v2i16:
705 case v2i32:
706 case v2i64:
707 case v2f16:
708 case v2bf16:
709 case v2f32:
710 case v2f64:
711 case nxv2i1:
712 case nxv2i8:
713 case nxv2i16:
714 case nxv2i32:
715 case nxv2i64:
716 case nxv2f16:
717 case nxv2bf16:
718 case nxv2f32:
719 case nxv2f64: return 2;
720 case v1i1:
721 case v1i8:
722 case v1i16:
723 case v1i32:
724 case v1i64:
725 case v1i128:
726 case v1f32:
727 case v1f64:
728 case nxv1i1:
729 case nxv1i8:
730 case nxv1i16:
731 case nxv1i32:
732 case nxv1i64:
733 case nxv1f16:
734 case nxv1f32:
735 case nxv1f64: return 1;
736 }
737 }
738
739 ElementCount getVectorElementCount() const {
740 return ElementCount::get(getVectorNumElements(), isScalableVector());
741 }
742
743 /// Given a vector type, return the minimum number of elements it contains.
744 unsigned getVectorMinNumElements() const {
745 return getVectorElementCount().getKnownMinValue();
746 }
747
748 /// Returns the size of the specified MVT in bits.
749 ///
750 /// If the value type is a scalable vector type, the scalable property will
751 /// be set and the runtime size will be a positive integer multiple of the
752 /// base size.
753 TypeSize getSizeInBits() const {
754 switch (SimpleTy) {
755 default:
756 llvm_unreachable("getSizeInBits called on extended MVT.")::llvm::llvm_unreachable_internal("getSizeInBits called on extended MVT."
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 756)
;
757 case Other:
758 llvm_unreachable("Value type is non-standard value, Other.")::llvm::llvm_unreachable_internal("Value type is non-standard value, Other."
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 758)
;
759 case iPTR:
760 llvm_unreachable("Value type size is target-dependent. Ask TLI.")::llvm::llvm_unreachable_internal("Value type size is target-dependent. Ask TLI."
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 760)
;
761 case iPTRAny:
762 case iAny:
763 case fAny:
764 case vAny:
765 case Any:
766 llvm_unreachable("Value type is overloaded.")::llvm::llvm_unreachable_internal("Value type is overloaded."
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 766)
;
767 case token:
768 llvm_unreachable("Token type is a sentinel that cannot be used "::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 769)
769 "in codegen and has no size")::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 769)
;
770 case Metadata:
771 llvm_unreachable("Value type is metadata.")::llvm::llvm_unreachable_internal("Value type is metadata.", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 771)
;
772 case i1:
773 case v1i1: return TypeSize::Fixed(1);
774 case nxv1i1: return TypeSize::Scalable(1);
775 case v2i1: return TypeSize::Fixed(2);
776 case nxv2i1: return TypeSize::Scalable(2);
777 case v4i1: return TypeSize::Fixed(4);
778 case nxv4i1: return TypeSize::Scalable(4);
779 case i8 :
780 case v1i8:
781 case v8i1: return TypeSize::Fixed(8);
782 case nxv1i8:
783 case nxv8i1: return TypeSize::Scalable(8);
784 case i16 :
785 case f16:
786 case bf16:
787 case v16i1:
788 case v2i8:
789 case v1i16: return TypeSize::Fixed(16);
790 case nxv16i1:
791 case nxv2i8:
792 case nxv1i16:
793 case nxv1f16: return TypeSize::Scalable(16);
794 case f32 :
795 case i32 :
796 case v32i1:
797 case v4i8:
798 case v2i16:
799 case v2f16:
800 case v2bf16:
801 case v1f32:
802 case v1i32: return TypeSize::Fixed(32);
803 case nxv32i1:
804 case nxv4i8:
805 case nxv2i16:
806 case nxv1i32:
807 case nxv2f16:
808 case nxv2bf16:
809 case nxv1f32: return TypeSize::Scalable(32);
810 case v3i16:
811 case v3f16:
812 case v3bf16: return TypeSize::Fixed(48);
813 case x86mmx:
814 case f64 :
815 case i64 :
816 case v64i1:
817 case v8i8:
818 case v4i16:
819 case v2i32:
820 case v1i64:
821 case v4f16:
822 case v4bf16:
823 case v2f32:
824 case v1f64: return TypeSize::Fixed(64);
825 case nxv64i1:
826 case nxv8i8:
827 case nxv4i16:
828 case nxv2i32:
829 case nxv1i64:
830 case nxv4f16:
831 case nxv4bf16:
832 case nxv2f32:
833 case nxv1f64: return TypeSize::Scalable(64);
834 case f80 : return TypeSize::Fixed(80);
835 case v3i32:
836 case v3f32: return TypeSize::Fixed(96);
837 case f128:
838 case ppcf128:
839 case i128:
840 case v128i1:
841 case v16i8:
842 case v8i16:
843 case v4i32:
844 case v2i64:
845 case v1i128:
846 case v8f16:
847 case v8bf16:
848 case v4f32:
849 case v2f64: return TypeSize::Fixed(128);
850 case nxv16i8:
851 case nxv8i16:
852 case nxv4i32:
853 case nxv2i64:
854 case nxv8f16:
855 case nxv8bf16:
856 case nxv4f32:
857 case nxv2f64: return TypeSize::Scalable(128);
858 case v5i32:
859 case v5f32: return TypeSize::Fixed(160);
860 case v256i1:
861 case v32i8:
862 case v16i16:
863 case v8i32:
864 case v4i64:
865 case v16f16:
866 case v16bf16:
867 case v8f32:
868 case v4f64: return TypeSize::Fixed(256);
869 case nxv32i8:
870 case nxv16i16:
871 case nxv8i32:
872 case nxv4i64:
873 case nxv16f16:
874 case nxv8f32:
875 case nxv4f64: return TypeSize::Scalable(256);
876 case v512i1:
877 case v64i8:
878 case v32i16:
879 case v16i32:
880 case v8i64:
881 case v32f16:
882 case v32bf16:
883 case v16f32:
884 case v8f64: return TypeSize::Fixed(512);
885 case nxv64i8:
886 case nxv32i16:
887 case nxv16i32:
888 case nxv8i64:
889 case nxv32f16:
890 case nxv16f32:
891 case nxv8f64: return TypeSize::Scalable(512);
892 case v1024i1:
893 case v128i8:
894 case v64i16:
895 case v32i32:
896 case v16i64:
897 case v64f16:
898 case v64bf16:
899 case v32f32:
900 case v16f64: return TypeSize::Fixed(1024);
901 case nxv32i32:
902 case nxv16i64: return TypeSize::Scalable(1024);
903 case v256i8:
904 case v128i16:
905 case v64i32:
906 case v32i64:
907 case v128f16:
908 case v128bf16:
909 case v64f32:
910 case v32f64: return TypeSize::Fixed(2048);
911 case nxv32i64: return TypeSize::Scalable(2048);
912 case v128i32:
913 case v128f32: return TypeSize::Fixed(4096);
914 case v256i32:
915 case v256f32: return TypeSize::Fixed(8192);
916 case v512i32:
917 case v512f32: return TypeSize::Fixed(16384);
918 case v1024i32:
919 case v1024f32: return TypeSize::Fixed(32768);
920 case v2048i32:
921 case v2048f32: return TypeSize::Fixed(65536);
922 case exnref: return TypeSize::Fixed(0); // opaque type
923 }
924 }
925
926 uint64_t getScalarSizeInBits() const {
927 return getScalarType().getSizeInBits().getFixedSize();
928 }
929
930 /// Return the number of bytes overwritten by a store of the specified value
931 /// type.
932 ///
933 /// If the value type is a scalable vector type, the scalable property will
934 /// be set and the runtime size will be a positive integer multiple of the
935 /// base size.
936 TypeSize getStoreSize() const {
937 TypeSize BaseSize = getSizeInBits();
938 return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
939 }
940
941 /// Return the number of bits overwritten by a store of the specified value
942 /// type.
943 ///
944 /// If the value type is a scalable vector type, the scalable property will
945 /// be set and the runtime size will be a positive integer multiple of the
946 /// base size.
947 TypeSize getStoreSizeInBits() const {
948 return getStoreSize() * 8;
949 }
950
951 /// Returns true if the number of bits for the type is a multiple of an
952 /// 8-bit byte.
953 bool isByteSized() const {
954 return getSizeInBits().isByteSized();
955 }
956
957 /// Return true if we know at compile time this has more bits than VT.
958 bool knownBitsGT(MVT VT) const {
959 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
960 }
961
962 /// Return true if we know at compile time this has more than or the same
963 /// bits as VT.
964 bool knownBitsGE(MVT VT) const {
965 return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits());
966 }
967
968 /// Return true if we know at compile time this has fewer bits than VT.
969 bool knownBitsLT(MVT VT) const {
970 return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits());
971 }
972
973 /// Return true if we know at compile time this has fewer than or the same
974 /// bits as VT.
975 bool knownBitsLE(MVT VT) const {
976 return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits());
977 }
978
979 /// Return true if this has more bits than VT.
980 bool bitsGT(MVT VT) const {
981 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 982, __PRETTY_FUNCTION__))
982 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 982, __PRETTY_FUNCTION__))
;
983 return knownBitsGT(VT);
984 }
985
986 /// Return true if this has no less bits than VT.
987 bool bitsGE(MVT VT) const {
988 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 989, __PRETTY_FUNCTION__))
989 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 989, __PRETTY_FUNCTION__))
;
990 return knownBitsGE(VT);
991 }
992
993 /// Return true if this has less bits than VT.
994 bool bitsLT(MVT VT) const {
995 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 996, __PRETTY_FUNCTION__))
996 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 996, __PRETTY_FUNCTION__))
;
997 return knownBitsLT(VT);
998 }
999
1000 /// Return true if this has no more bits than VT.
1001 bool bitsLE(MVT VT) const {
1002 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 1003, __PRETTY_FUNCTION__))
1003 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 1003, __PRETTY_FUNCTION__))
;
1004 return knownBitsLE(VT);
1005 }
1006
1007 static MVT getFloatingPointVT(unsigned BitWidth) {
1008 switch (BitWidth) {
1009 default:
1010 llvm_unreachable("Bad bit width!")::llvm::llvm_unreachable_internal("Bad bit width!", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 1010)
;
1011 case 16:
1012 return MVT::f16;
1013 case 32:
1014 return MVT::f32;
1015 case 64:
1016 return MVT::f64;
1017 case 80:
1018 return MVT::f80;
1019 case 128:
1020 return MVT::f128;
1021 }
1022 }
1023
1024 static MVT getIntegerVT(unsigned BitWidth) {
1025 switch (BitWidth) {
1026 default:
1027 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1028 case 1:
1029 return MVT::i1;
1030 case 8:
1031 return MVT::i8;
1032 case 16:
1033 return MVT::i16;
1034 case 32:
1035 return MVT::i32;
1036 case 64:
1037 return MVT::i64;
1038 case 128:
1039 return MVT::i128;
1040 }
1041 }
1042
1043 static MVT getVectorVT(MVT VT, unsigned NumElements) {
1044 switch (VT.SimpleTy) {
1045 default:
1046 break;
1047 case MVT::i1:
1048 if (NumElements == 1) return MVT::v1i1;
1049 if (NumElements == 2) return MVT::v2i1;
1050 if (NumElements == 4) return MVT::v4i1;
1051 if (NumElements == 8) return MVT::v8i1;
1052 if (NumElements == 16) return MVT::v16i1;
1053 if (NumElements == 32) return MVT::v32i1;
1054 if (NumElements == 64) return MVT::v64i1;
1055 if (NumElements == 128) return MVT::v128i1;
1056 if (NumElements == 256) return MVT::v256i1;
1057 if (NumElements == 512) return MVT::v512i1;
1058 if (NumElements == 1024) return MVT::v1024i1;
1059 break;
1060 case MVT::i8:
1061 if (NumElements == 1) return MVT::v1i8;
1062 if (NumElements == 2) return MVT::v2i8;
1063 if (NumElements == 4) return MVT::v4i8;
1064 if (NumElements == 8) return MVT::v8i8;
1065 if (NumElements == 16) return MVT::v16i8;
1066 if (NumElements == 32) return MVT::v32i8;
1067 if (NumElements == 64) return MVT::v64i8;
1068 if (NumElements == 128) return MVT::v128i8;
1069 if (NumElements == 256) return MVT::v256i8;
1070 break;
1071 case MVT::i16:
1072 if (NumElements == 1) return MVT::v1i16;
1073 if (NumElements == 2) return MVT::v2i16;
1074 if (NumElements == 3) return MVT::v3i16;
1075 if (NumElements == 4) return MVT::v4i16;
1076 if (NumElements == 8) return MVT::v8i16;
1077 if (NumElements == 16) return MVT::v16i16;
1078 if (NumElements == 32) return MVT::v32i16;
1079 if (NumElements == 64) return MVT::v64i16;
1080 if (NumElements == 128) return MVT::v128i16;
1081 break;
1082 case MVT::i32:
1083 if (NumElements == 1) return MVT::v1i32;
1084 if (NumElements == 2) return MVT::v2i32;
1085 if (NumElements == 3) return MVT::v3i32;
1086 if (NumElements == 4) return MVT::v4i32;
1087 if (NumElements == 5) return MVT::v5i32;
1088 if (NumElements == 8) return MVT::v8i32;
1089 if (NumElements == 16) return MVT::v16i32;
1090 if (NumElements == 32) return MVT::v32i32;
1091 if (NumElements == 64) return MVT::v64i32;
1092 if (NumElements == 128) return MVT::v128i32;
1093 if (NumElements == 256) return MVT::v256i32;
1094 if (NumElements == 512) return MVT::v512i32;
1095 if (NumElements == 1024) return MVT::v1024i32;
1096 if (NumElements == 2048) return MVT::v2048i32;
1097 break;
1098 case MVT::i64:
1099 if (NumElements == 1) return MVT::v1i64;
1100 if (NumElements == 2) return MVT::v2i64;
1101 if (NumElements == 4) return MVT::v4i64;
1102 if (NumElements == 8) return MVT::v8i64;
1103 if (NumElements == 16) return MVT::v16i64;
1104 if (NumElements == 32) return MVT::v32i64;
1105 break;
1106 case MVT::i128:
1107 if (NumElements == 1) return MVT::v1i128;
1108 break;
1109 case MVT::f16:
1110 if (NumElements == 2) return MVT::v2f16;
1111 if (NumElements == 3) return MVT::v3f16;
1112 if (NumElements == 4) return MVT::v4f16;
1113 if (NumElements == 8) return MVT::v8f16;
1114 if (NumElements == 16) return MVT::v16f16;
1115 if (NumElements == 32) return MVT::v32f16;
1116 if (NumElements == 64) return MVT::v64f16;
1117 if (NumElements == 128) return MVT::v128f16;
1118 break;
1119 case MVT::bf16:
1120 if (NumElements == 2) return MVT::v2bf16;
1121 if (NumElements == 3) return MVT::v3bf16;
1122 if (NumElements == 4) return MVT::v4bf16;
1123 if (NumElements == 8) return MVT::v8bf16;
1124 if (NumElements == 16) return MVT::v16bf16;
1125 if (NumElements == 32) return MVT::v32bf16;
1126 if (NumElements == 64) return MVT::v64bf16;
1127 if (NumElements == 128) return MVT::v128bf16;
1128 break;
1129 case MVT::f32:
1130 if (NumElements == 1) return MVT::v1f32;
1131 if (NumElements == 2) return MVT::v2f32;
1132 if (NumElements == 3) return MVT::v3f32;
1133 if (NumElements == 4) return MVT::v4f32;
1134 if (NumElements == 5) return MVT::v5f32;
1135 if (NumElements == 8) return MVT::v8f32;
1136 if (NumElements == 16) return MVT::v16f32;
1137 if (NumElements == 32) return MVT::v32f32;
1138 if (NumElements == 64) return MVT::v64f32;
1139 if (NumElements == 128) return MVT::v128f32;
1140 if (NumElements == 256) return MVT::v256f32;
1141 if (NumElements == 512) return MVT::v512f32;
1142 if (NumElements == 1024) return MVT::v1024f32;
1143 if (NumElements == 2048) return MVT::v2048f32;
1144 break;
1145 case MVT::f64:
1146 if (NumElements == 1) return MVT::v1f64;
1147 if (NumElements == 2) return MVT::v2f64;
1148 if (NumElements == 4) return MVT::v4f64;
1149 if (NumElements == 8) return MVT::v8f64;
1150 if (NumElements == 16) return MVT::v16f64;
1151 if (NumElements == 32) return MVT::v32f64;
1152 break;
1153 }
1154 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1155 }
1156
1157 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
1158 switch(VT.SimpleTy) {
1159 default:
1160 break;
1161 case MVT::i1:
1162 if (NumElements == 1) return MVT::nxv1i1;
1163 if (NumElements == 2) return MVT::nxv2i1;
1164 if (NumElements == 4) return MVT::nxv4i1;
1165 if (NumElements == 8) return MVT::nxv8i1;
1166 if (NumElements == 16) return MVT::nxv16i1;
1167 if (NumElements == 32) return MVT::nxv32i1;
1168 if (NumElements == 64) return MVT::nxv64i1;
1169 break;
1170 case MVT::i8:
1171 if (NumElements == 1) return MVT::nxv1i8;
1172 if (NumElements == 2) return MVT::nxv2i8;
1173 if (NumElements == 4) return MVT::nxv4i8;
1174 if (NumElements == 8) return MVT::nxv8i8;
1175 if (NumElements == 16) return MVT::nxv16i8;
1176 if (NumElements == 32) return MVT::nxv32i8;
1177 if (NumElements == 64) return MVT::nxv64i8;
1178 break;
1179 case MVT::i16:
1180 if (NumElements == 1) return MVT::nxv1i16;
1181 if (NumElements == 2) return MVT::nxv2i16;
1182 if (NumElements == 4) return MVT::nxv4i16;
1183 if (NumElements == 8) return MVT::nxv8i16;
1184 if (NumElements == 16) return MVT::nxv16i16;
1185 if (NumElements == 32) return MVT::nxv32i16;
1186 break;
1187 case MVT::i32:
1188 if (NumElements == 1) return MVT::nxv1i32;
1189 if (NumElements == 2) return MVT::nxv2i32;
1190 if (NumElements == 4) return MVT::nxv4i32;
1191 if (NumElements == 8) return MVT::nxv8i32;
1192 if (NumElements == 16) return MVT::nxv16i32;
1193 if (NumElements == 32) return MVT::nxv32i32;
1194 break;
1195 case MVT::i64:
1196 if (NumElements == 1) return MVT::nxv1i64;
1197 if (NumElements == 2) return MVT::nxv2i64;
1198 if (NumElements == 4) return MVT::nxv4i64;
1199 if (NumElements == 8) return MVT::nxv8i64;
1200 if (NumElements == 16) return MVT::nxv16i64;
1201 if (NumElements == 32) return MVT::nxv32i64;
1202 break;
1203 case MVT::f16:
1204 if (NumElements == 1) return MVT::nxv1f16;
1205 if (NumElements == 2) return MVT::nxv2f16;
1206 if (NumElements == 4) return MVT::nxv4f16;
1207 if (NumElements == 8) return MVT::nxv8f16;
1208 if (NumElements == 16) return MVT::nxv16f16;
1209 if (NumElements == 32) return MVT::nxv32f16;
1210 break;
1211 case MVT::bf16:
1212 if (NumElements == 2) return MVT::nxv2bf16;
1213 if (NumElements == 4) return MVT::nxv4bf16;
1214 if (NumElements == 8) return MVT::nxv8bf16;
1215 break;
1216 case MVT::f32:
1217 if (NumElements == 1) return MVT::nxv1f32;
1218 if (NumElements == 2) return MVT::nxv2f32;
1219 if (NumElements == 4) return MVT::nxv4f32;
1220 if (NumElements == 8) return MVT::nxv8f32;
1221 if (NumElements == 16) return MVT::nxv16f32;
1222 break;
1223 case MVT::f64:
1224 if (NumElements == 1) return MVT::nxv1f64;
1225 if (NumElements == 2) return MVT::nxv2f64;
1226 if (NumElements == 4) return MVT::nxv4f64;
1227 if (NumElements == 8) return MVT::nxv8f64;
1228 break;
1229 }
1230 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1231 }
1232
1233 static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
1234 if (IsScalable)
1235 return getScalableVectorVT(VT, NumElements);
1236 return getVectorVT(VT, NumElements);
1237 }
1238
1239 static MVT getVectorVT(MVT VT, ElementCount EC) {
1240 if (EC.isScalable())
1241 return getScalableVectorVT(VT, EC.getKnownMinValue());
1242 return getVectorVT(VT, EC.getKnownMinValue());
1243 }
1244
1245 /// Return the value type corresponding to the specified type. This returns
1246 /// all pointers as iPTR. If HandleUnknown is true, unknown types are
1247 /// returned as Other, otherwise they are invalid.
1248 static MVT getVT(Type *Ty, bool HandleUnknown = false);
1249
1250 private:
1251 /// A simple iterator over the MVT::SimpleValueType enum.
1252 struct mvt_iterator {
1253 SimpleValueType VT;
1254
1255 mvt_iterator(SimpleValueType VT) : VT(VT) {}
1256
1257 MVT operator*() const { return VT; }
1258 bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; }
1259
1260 mvt_iterator& operator++() {
1261 VT = (MVT::SimpleValueType)((int)VT + 1);
1262 assert((int)VT <= MVT::MAX_ALLOWED_VALUETYPE &&(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 1263, __PRETTY_FUNCTION__))
1263 "MVT iterator overflowed.")(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/Support/MachineValueType.h"
, 1263, __PRETTY_FUNCTION__))
;
1264 return *this;
1265 }
1266 };
1267
1268 /// A range of the MVT::SimpleValueType enum.
1269 using mvt_range = iterator_range<mvt_iterator>;
1270
1271 public:
1272 /// SimpleValueType Iteration
1273 /// @{
1274 static mvt_range all_valuetypes() {
1275 return mvt_range(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE);
1276 }
1277
1278 static mvt_range integer_valuetypes() {
1279 return mvt_range(MVT::FIRST_INTEGER_VALUETYPE,
1280 (MVT::SimpleValueType)(MVT::LAST_INTEGER_VALUETYPE + 1));
1281 }
1282
1283 static mvt_range fp_valuetypes() {
1284 return mvt_range(MVT::FIRST_FP_VALUETYPE,
1285 (MVT::SimpleValueType)(MVT::LAST_FP_VALUETYPE + 1));
1286 }
1287
1288 static mvt_range vector_valuetypes() {
1289 return mvt_range(MVT::FIRST_VECTOR_VALUETYPE,
1290 (MVT::SimpleValueType)(MVT::LAST_VECTOR_VALUETYPE + 1));
1291 }
1292
1293 static mvt_range fixedlen_vector_valuetypes() {
1294 return mvt_range(
1295 MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE,
1296 (MVT::SimpleValueType)(MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE + 1));
1297 }
1298
1299 static mvt_range scalable_vector_valuetypes() {
1300 return mvt_range(
1301 MVT::FIRST_SCALABLE_VECTOR_VALUETYPE,
1302 (MVT::SimpleValueType)(MVT::LAST_SCALABLE_VECTOR_VALUETYPE + 1));
1303 }
1304
1305 static mvt_range integer_fixedlen_vector_valuetypes() {
1306 return mvt_range(
1307 MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
1308 (MVT::SimpleValueType)(MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE + 1));
1309 }
1310
1311 static mvt_range fp_fixedlen_vector_valuetypes() {
1312 return mvt_range(
1313 MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE,
1314 (MVT::SimpleValueType)(MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE + 1));
1315 }
1316
1317 static mvt_range integer_scalable_vector_valuetypes() {
1318 return mvt_range(
1319 MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
1320 (MVT::SimpleValueType)(MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE + 1));
1321 }
1322
1323 static mvt_range fp_scalable_vector_valuetypes() {
1324 return mvt_range(
1325 MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
1326 (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE + 1));
1327 }
1328 /// @}
1329 };
1330
1331} // end namespace llvm
1332
1333#endif // LLVM_CODEGEN_MACHINEVALUETYPE_H