File: | build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR/AVRISelLowering.cpp |
Warning: | line 1147, column 13 1st function call argument is an uninitialized value |
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1 | //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===// | ||||
2 | // | ||||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||||
4 | // See https://llvm.org/LICENSE.txt for license information. | ||||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||||
6 | // | ||||
7 | //===----------------------------------------------------------------------===// | ||||
8 | // | ||||
9 | // This file defines the interfaces that AVR uses to lower LLVM code into a | ||||
10 | // selection DAG. | ||||
11 | // | ||||
12 | //===----------------------------------------------------------------------===// | ||||
13 | |||||
14 | #include "AVRISelLowering.h" | ||||
15 | |||||
16 | #include "llvm/ADT/STLExtras.h" | ||||
17 | #include "llvm/ADT/StringSwitch.h" | ||||
18 | #include "llvm/CodeGen/CallingConvLower.h" | ||||
19 | #include "llvm/CodeGen/MachineFrameInfo.h" | ||||
20 | #include "llvm/CodeGen/MachineInstrBuilder.h" | ||||
21 | #include "llvm/CodeGen/MachineRegisterInfo.h" | ||||
22 | #include "llvm/CodeGen/SelectionDAG.h" | ||||
23 | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" | ||||
24 | #include "llvm/IR/Function.h" | ||||
25 | #include "llvm/Support/ErrorHandling.h" | ||||
26 | |||||
27 | #include "AVR.h" | ||||
28 | #include "AVRMachineFunctionInfo.h" | ||||
29 | #include "AVRSubtarget.h" | ||||
30 | #include "AVRTargetMachine.h" | ||||
31 | #include "MCTargetDesc/AVRMCTargetDesc.h" | ||||
32 | |||||
33 | namespace llvm { | ||||
34 | |||||
35 | AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM, | ||||
36 | const AVRSubtarget &STI) | ||||
37 | : TargetLowering(TM), Subtarget(STI) { | ||||
38 | // Set up the register classes. | ||||
39 | addRegisterClass(MVT::i8, &AVR::GPR8RegClass); | ||||
40 | addRegisterClass(MVT::i16, &AVR::DREGSRegClass); | ||||
41 | |||||
42 | // Compute derived properties from the register classes. | ||||
43 | computeRegisterProperties(Subtarget.getRegisterInfo()); | ||||
44 | |||||
45 | setBooleanContents(ZeroOrOneBooleanContent); | ||||
46 | setBooleanVectorContents(ZeroOrOneBooleanContent); | ||||
47 | setSchedulingPreference(Sched::RegPressure); | ||||
48 | setStackPointerRegisterToSaveRestore(AVR::SP); | ||||
49 | setSupportsUnalignedAtomics(true); | ||||
50 | |||||
51 | setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); | ||||
52 | setOperationAction(ISD::BlockAddress, MVT::i16, Custom); | ||||
53 | |||||
54 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); | ||||
55 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); | ||||
56 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); | ||||
57 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); | ||||
58 | |||||
59 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
60 | for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { | ||||
61 | setLoadExtAction(N, VT, MVT::i1, Promote); | ||||
62 | setLoadExtAction(N, VT, MVT::i8, Expand); | ||||
63 | } | ||||
64 | } | ||||
65 | |||||
66 | setTruncStoreAction(MVT::i16, MVT::i8, Expand); | ||||
67 | |||||
68 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
69 | setOperationAction(ISD::ADDC, VT, Legal); | ||||
70 | setOperationAction(ISD::SUBC, VT, Legal); | ||||
71 | setOperationAction(ISD::ADDE, VT, Legal); | ||||
72 | setOperationAction(ISD::SUBE, VT, Legal); | ||||
73 | } | ||||
74 | |||||
75 | // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types | ||||
76 | // revert into a sub since we don't have an add with immediate instruction. | ||||
77 | setOperationAction(ISD::ADD, MVT::i32, Custom); | ||||
78 | setOperationAction(ISD::ADD, MVT::i64, Custom); | ||||
79 | |||||
80 | // our shift instructions are only able to shift 1 bit at a time, so handle | ||||
81 | // this in a custom way. | ||||
82 | setOperationAction(ISD::SRA, MVT::i8, Custom); | ||||
83 | setOperationAction(ISD::SHL, MVT::i8, Custom); | ||||
84 | setOperationAction(ISD::SRL, MVT::i8, Custom); | ||||
85 | setOperationAction(ISD::SRA, MVT::i16, Custom); | ||||
86 | setOperationAction(ISD::SHL, MVT::i16, Custom); | ||||
87 | setOperationAction(ISD::SRL, MVT::i16, Custom); | ||||
88 | setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); | ||||
89 | setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); | ||||
90 | setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); | ||||
91 | |||||
92 | setOperationAction(ISD::ROTL, MVT::i8, Custom); | ||||
93 | setOperationAction(ISD::ROTL, MVT::i16, Expand); | ||||
94 | setOperationAction(ISD::ROTR, MVT::i8, Custom); | ||||
95 | setOperationAction(ISD::ROTR, MVT::i16, Expand); | ||||
96 | |||||
97 | setOperationAction(ISD::BR_CC, MVT::i8, Custom); | ||||
98 | setOperationAction(ISD::BR_CC, MVT::i16, Custom); | ||||
99 | setOperationAction(ISD::BR_CC, MVT::i32, Custom); | ||||
100 | setOperationAction(ISD::BR_CC, MVT::i64, Custom); | ||||
101 | setOperationAction(ISD::BRCOND, MVT::Other, Expand); | ||||
102 | |||||
103 | setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); | ||||
104 | setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); | ||||
105 | setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); | ||||
106 | setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); | ||||
107 | setOperationAction(ISD::SETCC, MVT::i8, Custom); | ||||
108 | setOperationAction(ISD::SETCC, MVT::i16, Custom); | ||||
109 | setOperationAction(ISD::SETCC, MVT::i32, Custom); | ||||
110 | setOperationAction(ISD::SETCC, MVT::i64, Custom); | ||||
111 | setOperationAction(ISD::SELECT, MVT::i8, Expand); | ||||
112 | setOperationAction(ISD::SELECT, MVT::i16, Expand); | ||||
113 | |||||
114 | setOperationAction(ISD::BSWAP, MVT::i16, Expand); | ||||
115 | |||||
116 | // Add support for postincrement and predecrement load/stores. | ||||
117 | setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); | ||||
118 | setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); | ||||
119 | setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); | ||||
120 | setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); | ||||
121 | setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); | ||||
122 | setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); | ||||
123 | setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); | ||||
124 | setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); | ||||
125 | |||||
126 | setOperationAction(ISD::BR_JT, MVT::Other, Expand); | ||||
127 | |||||
128 | setOperationAction(ISD::VASTART, MVT::Other, Custom); | ||||
129 | setOperationAction(ISD::VAEND, MVT::Other, Expand); | ||||
130 | setOperationAction(ISD::VAARG, MVT::Other, Expand); | ||||
131 | setOperationAction(ISD::VACOPY, MVT::Other, Expand); | ||||
132 | |||||
133 | // Atomic operations which must be lowered to rtlib calls | ||||
134 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
135 | setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); | ||||
136 | setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); | ||||
137 | setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); | ||||
138 | setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); | ||||
139 | setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); | ||||
140 | setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); | ||||
141 | setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); | ||||
142 | } | ||||
143 | |||||
144 | // Division/remainder | ||||
145 | setOperationAction(ISD::UDIV, MVT::i8, Expand); | ||||
146 | setOperationAction(ISD::UDIV, MVT::i16, Expand); | ||||
147 | setOperationAction(ISD::UREM, MVT::i8, Expand); | ||||
148 | setOperationAction(ISD::UREM, MVT::i16, Expand); | ||||
149 | setOperationAction(ISD::SDIV, MVT::i8, Expand); | ||||
150 | setOperationAction(ISD::SDIV, MVT::i16, Expand); | ||||
151 | setOperationAction(ISD::SREM, MVT::i8, Expand); | ||||
152 | setOperationAction(ISD::SREM, MVT::i16, Expand); | ||||
153 | |||||
154 | // Make division and modulus custom | ||||
155 | setOperationAction(ISD::UDIVREM, MVT::i8, Custom); | ||||
156 | setOperationAction(ISD::UDIVREM, MVT::i16, Custom); | ||||
157 | setOperationAction(ISD::UDIVREM, MVT::i32, Custom); | ||||
158 | setOperationAction(ISD::SDIVREM, MVT::i8, Custom); | ||||
159 | setOperationAction(ISD::SDIVREM, MVT::i16, Custom); | ||||
160 | setOperationAction(ISD::SDIVREM, MVT::i32, Custom); | ||||
161 | |||||
162 | // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co. | ||||
163 | setOperationAction(ISD::MUL, MVT::i8, Expand); | ||||
164 | setOperationAction(ISD::MUL, MVT::i16, Expand); | ||||
165 | |||||
166 | // Expand 16 bit multiplications. | ||||
167 | setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); | ||||
168 | setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); | ||||
169 | |||||
170 | // Expand multiplications to libcalls when there is | ||||
171 | // no hardware MUL. | ||||
172 | if (!Subtarget.supportsMultiplication()) { | ||||
173 | setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); | ||||
174 | setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); | ||||
175 | } | ||||
176 | |||||
177 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
178 | setOperationAction(ISD::MULHS, VT, Expand); | ||||
179 | setOperationAction(ISD::MULHU, VT, Expand); | ||||
180 | } | ||||
181 | |||||
182 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
183 | setOperationAction(ISD::CTPOP, VT, Expand); | ||||
184 | setOperationAction(ISD::CTLZ, VT, Expand); | ||||
185 | setOperationAction(ISD::CTTZ, VT, Expand); | ||||
186 | } | ||||
187 | |||||
188 | for (MVT VT : MVT::integer_valuetypes()) { | ||||
189 | setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | ||||
190 | // TODO: The generated code is pretty poor. Investigate using the | ||||
191 | // same "shift and subtract with carry" trick that we do for | ||||
192 | // extending 8-bit to 16-bit. This may require infrastructure | ||||
193 | // improvements in how we treat 16-bit "registers" to be feasible. | ||||
194 | } | ||||
195 | |||||
196 | // Division rtlib functions (not supported), use divmod functions instead | ||||
197 | setLibcallName(RTLIB::SDIV_I8, nullptr); | ||||
198 | setLibcallName(RTLIB::SDIV_I16, nullptr); | ||||
199 | setLibcallName(RTLIB::SDIV_I32, nullptr); | ||||
200 | setLibcallName(RTLIB::UDIV_I8, nullptr); | ||||
201 | setLibcallName(RTLIB::UDIV_I16, nullptr); | ||||
202 | setLibcallName(RTLIB::UDIV_I32, nullptr); | ||||
203 | |||||
204 | // Modulus rtlib functions (not supported), use divmod functions instead | ||||
205 | setLibcallName(RTLIB::SREM_I8, nullptr); | ||||
206 | setLibcallName(RTLIB::SREM_I16, nullptr); | ||||
207 | setLibcallName(RTLIB::SREM_I32, nullptr); | ||||
208 | setLibcallName(RTLIB::UREM_I8, nullptr); | ||||
209 | setLibcallName(RTLIB::UREM_I16, nullptr); | ||||
210 | setLibcallName(RTLIB::UREM_I32, nullptr); | ||||
211 | |||||
212 | // Division and modulus rtlib functions | ||||
213 | setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4"); | ||||
214 | setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4"); | ||||
215 | setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); | ||||
216 | setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4"); | ||||
217 | setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4"); | ||||
218 | setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); | ||||
219 | |||||
220 | // Several of the runtime library functions use a special calling conv | ||||
221 | setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN); | ||||
222 | setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN); | ||||
223 | setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN); | ||||
224 | setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN); | ||||
225 | |||||
226 | // Trigonometric rtlib functions | ||||
227 | setLibcallName(RTLIB::SIN_F32, "sin"); | ||||
228 | setLibcallName(RTLIB::COS_F32, "cos"); | ||||
229 | |||||
230 | setMinFunctionAlignment(Align(2)); | ||||
231 | setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U)); | ||||
232 | } | ||||
233 | |||||
234 | const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { | ||||
235 | #define NODE(name) \ | ||||
236 | case AVRISD::name: \ | ||||
237 | return #name | ||||
238 | |||||
239 | switch (Opcode) { | ||||
240 | default: | ||||
241 | return nullptr; | ||||
242 | NODE(RET_FLAG); | ||||
243 | NODE(RETI_FLAG); | ||||
244 | NODE(CALL); | ||||
245 | NODE(WRAPPER); | ||||
246 | NODE(LSL); | ||||
247 | NODE(LSR); | ||||
248 | NODE(ROL); | ||||
249 | NODE(ROR); | ||||
250 | NODE(ASR); | ||||
251 | NODE(LSLLOOP); | ||||
252 | NODE(LSRLOOP); | ||||
253 | NODE(ROLLOOP); | ||||
254 | NODE(RORLOOP); | ||||
255 | NODE(ASRLOOP); | ||||
256 | NODE(BRCOND); | ||||
257 | NODE(CMP); | ||||
258 | NODE(CMPC); | ||||
259 | NODE(TST); | ||||
260 | NODE(SELECT_CC); | ||||
261 | #undef NODE | ||||
262 | } | ||||
263 | } | ||||
264 | |||||
265 | EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, | ||||
266 | EVT VT) const { | ||||
267 | assert(!VT.isVector() && "No AVR SetCC type for vectors!")(static_cast <bool> (!VT.isVector() && "No AVR SetCC type for vectors!" ) ? void (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 267, __extension__ __PRETTY_FUNCTION__)); | ||||
268 | return MVT::i8; | ||||
269 | } | ||||
270 | |||||
271 | SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { | ||||
272 | //: TODO: this function has to be completely rewritten to produce optimal | ||||
273 | // code, for now it's producing very long but correct code. | ||||
274 | unsigned Opc8; | ||||
275 | const SDNode *N = Op.getNode(); | ||||
276 | EVT VT = Op.getValueType(); | ||||
277 | SDLoc dl(N); | ||||
278 | assert(isPowerOf2_32(VT.getSizeInBits()) &&(static_cast <bool> (isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount") ? void (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 279, __extension__ __PRETTY_FUNCTION__)) | ||||
279 | "Expected power-of-2 shift amount")(static_cast <bool> (isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount") ? void (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 279, __extension__ __PRETTY_FUNCTION__)); | ||||
280 | |||||
281 | // Expand non-constant shifts to loops. | ||||
282 | if (!isa<ConstantSDNode>(N->getOperand(1))) { | ||||
283 | switch (Op.getOpcode()) { | ||||
284 | default: | ||||
285 | llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 285); | ||||
286 | case ISD::SHL: | ||||
287 | return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), | ||||
288 | N->getOperand(1)); | ||||
289 | case ISD::SRL: | ||||
290 | return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), | ||||
291 | N->getOperand(1)); | ||||
292 | case ISD::ROTL: { | ||||
293 | SDValue Amt = N->getOperand(1); | ||||
294 | EVT AmtVT = Amt.getValueType(); | ||||
295 | Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, | ||||
296 | DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); | ||||
297 | return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); | ||||
298 | } | ||||
299 | case ISD::ROTR: { | ||||
300 | SDValue Amt = N->getOperand(1); | ||||
301 | EVT AmtVT = Amt.getValueType(); | ||||
302 | Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, | ||||
303 | DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); | ||||
304 | return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); | ||||
305 | } | ||||
306 | case ISD::SRA: | ||||
307 | return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), | ||||
308 | N->getOperand(1)); | ||||
309 | } | ||||
310 | } | ||||
311 | |||||
312 | uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); | ||||
313 | SDValue Victim = N->getOperand(0); | ||||
314 | |||||
315 | switch (Op.getOpcode()) { | ||||
316 | case ISD::SRA: | ||||
317 | Opc8 = AVRISD::ASR; | ||||
318 | break; | ||||
319 | case ISD::ROTL: | ||||
320 | Opc8 = AVRISD::ROL; | ||||
321 | ShiftAmount = ShiftAmount % VT.getSizeInBits(); | ||||
322 | break; | ||||
323 | case ISD::ROTR: | ||||
324 | Opc8 = AVRISD::ROR; | ||||
325 | ShiftAmount = ShiftAmount % VT.getSizeInBits(); | ||||
326 | break; | ||||
327 | case ISD::SRL: | ||||
328 | Opc8 = AVRISD::LSR; | ||||
329 | break; | ||||
330 | case ISD::SHL: | ||||
331 | Opc8 = AVRISD::LSL; | ||||
332 | break; | ||||
333 | default: | ||||
334 | llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 334); | ||||
335 | } | ||||
336 | |||||
337 | // Optimize int8/int16 shifts. | ||||
338 | if (VT.getSizeInBits() == 8) { | ||||
339 | if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { | ||||
340 | // Optimize LSL when 4 <= ShiftAmount <= 6. | ||||
341 | Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); | ||||
342 | Victim = | ||||
343 | DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); | ||||
344 | ShiftAmount -= 4; | ||||
345 | } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && | ||||
346 | ShiftAmount < 7) { | ||||
347 | // Optimize LSR when 4 <= ShiftAmount <= 6. | ||||
348 | Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); | ||||
349 | Victim = | ||||
350 | DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); | ||||
351 | ShiftAmount -= 4; | ||||
352 | } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { | ||||
353 | // Optimize LSL when ShiftAmount == 7. | ||||
354 | Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, | ||||
355 | DAG.getConstant(7, dl, VT)); | ||||
356 | ShiftAmount = 0; | ||||
357 | } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { | ||||
358 | // Optimize LSR when ShiftAmount == 7. | ||||
359 | Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, | ||||
360 | DAG.getConstant(7, dl, VT)); | ||||
361 | ShiftAmount = 0; | ||||
362 | } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { | ||||
363 | // Optimize ASR when ShiftAmount == 6. | ||||
364 | Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, | ||||
365 | DAG.getConstant(6, dl, VT)); | ||||
366 | ShiftAmount = 0; | ||||
367 | } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { | ||||
368 | // Optimize ASR when ShiftAmount == 7. | ||||
369 | Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, | ||||
370 | DAG.getConstant(7, dl, VT)); | ||||
371 | ShiftAmount = 0; | ||||
372 | } | ||||
373 | } else if (VT.getSizeInBits() == 16) { | ||||
374 | if (4 <= ShiftAmount && ShiftAmount < 8) | ||||
375 | switch (Op.getOpcode()) { | ||||
376 | case ISD::SHL: | ||||
377 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, | ||||
378 | DAG.getConstant(4, dl, VT)); | ||||
379 | ShiftAmount -= 4; | ||||
380 | break; | ||||
381 | case ISD::SRL: | ||||
382 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, | ||||
383 | DAG.getConstant(4, dl, VT)); | ||||
384 | ShiftAmount -= 4; | ||||
385 | break; | ||||
386 | default: | ||||
387 | break; | ||||
388 | } | ||||
389 | else if (8 <= ShiftAmount && ShiftAmount < 12) | ||||
390 | switch (Op.getOpcode()) { | ||||
391 | case ISD::SHL: | ||||
392 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, | ||||
393 | DAG.getConstant(8, dl, VT)); | ||||
394 | ShiftAmount -= 8; | ||||
395 | // Only operate on the higher byte for remaining shift bits. | ||||
396 | Opc8 = AVRISD::LSLHI; | ||||
397 | break; | ||||
398 | case ISD::SRL: | ||||
399 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, | ||||
400 | DAG.getConstant(8, dl, VT)); | ||||
401 | ShiftAmount -= 8; | ||||
402 | // Only operate on the lower byte for remaining shift bits. | ||||
403 | Opc8 = AVRISD::LSRLO; | ||||
404 | break; | ||||
405 | case ISD::SRA: | ||||
406 | Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, | ||||
407 | DAG.getConstant(8, dl, VT)); | ||||
408 | ShiftAmount -= 8; | ||||
409 | // Only operate on the lower byte for remaining shift bits. | ||||
410 | Opc8 = AVRISD::ASRLO; | ||||
411 | break; | ||||
412 | default: | ||||
413 | break; | ||||
414 | } | ||||
415 | else if (12 <= ShiftAmount) | ||||
416 | switch (Op.getOpcode()) { | ||||
417 | case ISD::SHL: | ||||
418 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, | ||||
419 | DAG.getConstant(12, dl, VT)); | ||||
420 | ShiftAmount -= 12; | ||||
421 | // Only operate on the higher byte for remaining shift bits. | ||||
422 | Opc8 = AVRISD::LSLHI; | ||||
423 | break; | ||||
424 | case ISD::SRL: | ||||
425 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, | ||||
426 | DAG.getConstant(12, dl, VT)); | ||||
427 | ShiftAmount -= 12; | ||||
428 | // Only operate on the lower byte for remaining shift bits. | ||||
429 | Opc8 = AVRISD::LSRLO; | ||||
430 | break; | ||||
431 | case ISD::SRA: | ||||
432 | Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, | ||||
433 | DAG.getConstant(8, dl, VT)); | ||||
434 | ShiftAmount -= 8; | ||||
435 | // Only operate on the lower byte for remaining shift bits. | ||||
436 | Opc8 = AVRISD::ASRLO; | ||||
437 | break; | ||||
438 | default: | ||||
439 | break; | ||||
440 | } | ||||
441 | } | ||||
442 | |||||
443 | while (ShiftAmount--) { | ||||
444 | Victim = DAG.getNode(Opc8, dl, VT, Victim); | ||||
445 | } | ||||
446 | |||||
447 | return Victim; | ||||
448 | } | ||||
449 | |||||
450 | SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { | ||||
451 | unsigned Opcode = Op->getOpcode(); | ||||
452 | assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(static_cast <bool> ((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering" ) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 453, __extension__ __PRETTY_FUNCTION__)) | ||||
453 | "Invalid opcode for Div/Rem lowering")(static_cast <bool> ((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering" ) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 453, __extension__ __PRETTY_FUNCTION__)); | ||||
454 | bool IsSigned = (Opcode == ISD::SDIVREM); | ||||
455 | EVT VT = Op->getValueType(0); | ||||
456 | Type *Ty = VT.getTypeForEVT(*DAG.getContext()); | ||||
457 | |||||
458 | RTLIB::Libcall LC; | ||||
459 | switch (VT.getSimpleVT().SimpleTy) { | ||||
460 | default: | ||||
461 | llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 461); | ||||
462 | case MVT::i8: | ||||
463 | LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; | ||||
464 | break; | ||||
465 | case MVT::i16: | ||||
466 | LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; | ||||
467 | break; | ||||
468 | case MVT::i32: | ||||
469 | LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; | ||||
470 | break; | ||||
471 | } | ||||
472 | |||||
473 | SDValue InChain = DAG.getEntryNode(); | ||||
474 | |||||
475 | TargetLowering::ArgListTy Args; | ||||
476 | TargetLowering::ArgListEntry Entry; | ||||
477 | for (SDValue const &Value : Op->op_values()) { | ||||
478 | Entry.Node = Value; | ||||
479 | Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); | ||||
480 | Entry.IsSExt = IsSigned; | ||||
481 | Entry.IsZExt = !IsSigned; | ||||
482 | Args.push_back(Entry); | ||||
483 | } | ||||
484 | |||||
485 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | ||||
486 | getPointerTy(DAG.getDataLayout())); | ||||
487 | |||||
488 | Type *RetTy = (Type *)StructType::get(Ty, Ty); | ||||
489 | |||||
490 | SDLoc dl(Op); | ||||
491 | TargetLowering::CallLoweringInfo CLI(DAG); | ||||
492 | CLI.setDebugLoc(dl) | ||||
493 | .setChain(InChain) | ||||
494 | .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) | ||||
495 | .setInRegister() | ||||
496 | .setSExtResult(IsSigned) | ||||
497 | .setZExtResult(!IsSigned); | ||||
498 | |||||
499 | std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); | ||||
500 | return CallInfo.first; | ||||
501 | } | ||||
502 | |||||
503 | SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op, | ||||
504 | SelectionDAG &DAG) const { | ||||
505 | auto DL = DAG.getDataLayout(); | ||||
506 | |||||
507 | const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); | ||||
508 | int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); | ||||
509 | |||||
510 | // Create the TargetGlobalAddress node, folding in the constant offset. | ||||
511 | SDValue Result = | ||||
512 | DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset); | ||||
513 | return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); | ||||
514 | } | ||||
515 | |||||
516 | SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op, | ||||
517 | SelectionDAG &DAG) const { | ||||
518 | auto DL = DAG.getDataLayout(); | ||||
519 | const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); | ||||
520 | |||||
521 | SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL)); | ||||
522 | |||||
523 | return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); | ||||
524 | } | ||||
525 | |||||
526 | /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC. | ||||
527 | static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { | ||||
528 | switch (CC) { | ||||
529 | default: | ||||
530 | llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 530); | ||||
531 | case ISD::SETEQ: | ||||
532 | return AVRCC::COND_EQ; | ||||
533 | case ISD::SETNE: | ||||
534 | return AVRCC::COND_NE; | ||||
535 | case ISD::SETGE: | ||||
536 | return AVRCC::COND_GE; | ||||
537 | case ISD::SETLT: | ||||
538 | return AVRCC::COND_LT; | ||||
539 | case ISD::SETUGE: | ||||
540 | return AVRCC::COND_SH; | ||||
541 | case ISD::SETULT: | ||||
542 | return AVRCC::COND_LO; | ||||
543 | } | ||||
544 | } | ||||
545 | |||||
546 | /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands. | ||||
547 | SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, | ||||
548 | SelectionDAG &DAG, SDLoc DL) const { | ||||
549 | assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&(static_cast <bool> ((LHS.getSimpleValueType() == RHS.getSimpleValueType ()) && "LHS and RHS have different types") ? void (0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 550, __extension__ __PRETTY_FUNCTION__)) | ||||
550 | "LHS and RHS have different types")(static_cast <bool> ((LHS.getSimpleValueType() == RHS.getSimpleValueType ()) && "LHS and RHS have different types") ? void (0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 550, __extension__ __PRETTY_FUNCTION__)); | ||||
551 | assert(((LHS.getSimpleValueType() == MVT::i16) ||(static_cast <bool> (((LHS.getSimpleValueType() == MVT:: i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type" ) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__ __PRETTY_FUNCTION__)) | ||||
552 | (LHS.getSimpleValueType() == MVT::i8)) &&(static_cast <bool> (((LHS.getSimpleValueType() == MVT:: i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type" ) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__ __PRETTY_FUNCTION__)) | ||||
553 | "invalid comparison type")(static_cast <bool> (((LHS.getSimpleValueType() == MVT:: i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type" ) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__ __PRETTY_FUNCTION__)); | ||||
554 | |||||
555 | SDValue Cmp; | ||||
556 | |||||
557 | if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) { | ||||
558 | // Generate a CPI/CPC pair if RHS is a 16-bit constant. | ||||
559 | SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, | ||||
560 | DAG.getIntPtrConstant(0, DL)); | ||||
561 | SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, | ||||
562 | DAG.getIntPtrConstant(1, DL)); | ||||
563 | SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, | ||||
564 | DAG.getIntPtrConstant(0, DL)); | ||||
565 | SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, | ||||
566 | DAG.getIntPtrConstant(1, DL)); | ||||
567 | Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo); | ||||
568 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); | ||||
569 | } else { | ||||
570 | // Generate ordinary 16-bit comparison. | ||||
571 | Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS); | ||||
572 | } | ||||
573 | |||||
574 | return Cmp; | ||||
575 | } | ||||
576 | |||||
577 | /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for | ||||
578 | /// the given operands. | ||||
579 | SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, | ||||
580 | SDValue &AVRcc, SelectionDAG &DAG, | ||||
581 | SDLoc DL) const { | ||||
582 | SDValue Cmp; | ||||
583 | EVT VT = LHS.getValueType(); | ||||
584 | bool UseTest = false; | ||||
585 | |||||
586 | switch (CC) { | ||||
587 | default: | ||||
588 | break; | ||||
589 | case ISD::SETLE: { | ||||
590 | // Swap operands and reverse the branching condition. | ||||
591 | std::swap(LHS, RHS); | ||||
592 | CC = ISD::SETGE; | ||||
593 | break; | ||||
594 | } | ||||
595 | case ISD::SETGT: { | ||||
596 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { | ||||
597 | switch (C->getSExtValue()) { | ||||
598 | case -1: { | ||||
599 | // When doing lhs > -1 use a tst instruction on the top part of lhs | ||||
600 | // and use brpl instead of using a chain of cp/cpc. | ||||
601 | UseTest = true; | ||||
602 | AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); | ||||
603 | break; | ||||
604 | } | ||||
605 | case 0: { | ||||
606 | // Turn lhs > 0 into 0 < lhs since 0 can be materialized with | ||||
607 | // __zero_reg__ in lhs. | ||||
608 | RHS = LHS; | ||||
609 | LHS = DAG.getConstant(0, DL, VT); | ||||
610 | CC = ISD::SETLT; | ||||
611 | break; | ||||
612 | } | ||||
613 | default: { | ||||
614 | // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows | ||||
615 | // us to fold the constant into the cmp instruction. | ||||
616 | RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); | ||||
617 | CC = ISD::SETGE; | ||||
618 | break; | ||||
619 | } | ||||
620 | } | ||||
621 | break; | ||||
622 | } | ||||
623 | // Swap operands and reverse the branching condition. | ||||
624 | std::swap(LHS, RHS); | ||||
625 | CC = ISD::SETLT; | ||||
626 | break; | ||||
627 | } | ||||
628 | case ISD::SETLT: { | ||||
629 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { | ||||
630 | switch (C->getSExtValue()) { | ||||
631 | case 1: { | ||||
632 | // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with | ||||
633 | // __zero_reg__ in lhs. | ||||
634 | RHS = LHS; | ||||
635 | LHS = DAG.getConstant(0, DL, VT); | ||||
636 | CC = ISD::SETGE; | ||||
637 | break; | ||||
638 | } | ||||
639 | case 0: { | ||||
640 | // When doing lhs < 0 use a tst instruction on the top part of lhs | ||||
641 | // and use brmi instead of using a chain of cp/cpc. | ||||
642 | UseTest = true; | ||||
643 | AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); | ||||
644 | break; | ||||
645 | } | ||||
646 | } | ||||
647 | } | ||||
648 | break; | ||||
649 | } | ||||
650 | case ISD::SETULE: { | ||||
651 | // Swap operands and reverse the branching condition. | ||||
652 | std::swap(LHS, RHS); | ||||
653 | CC = ISD::SETUGE; | ||||
654 | break; | ||||
655 | } | ||||
656 | case ISD::SETUGT: { | ||||
657 | // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to | ||||
658 | // fold the constant into the cmp instruction. | ||||
659 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { | ||||
660 | RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); | ||||
661 | CC = ISD::SETUGE; | ||||
662 | break; | ||||
663 | } | ||||
664 | // Swap operands and reverse the branching condition. | ||||
665 | std::swap(LHS, RHS); | ||||
666 | CC = ISD::SETULT; | ||||
667 | break; | ||||
668 | } | ||||
669 | } | ||||
670 | |||||
671 | // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of | ||||
672 | // using the default and/or/xor expansion code which is much longer. | ||||
673 | if (VT == MVT::i32) { | ||||
674 | SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, | ||||
675 | DAG.getIntPtrConstant(0, DL)); | ||||
676 | SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, | ||||
677 | DAG.getIntPtrConstant(1, DL)); | ||||
678 | SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, | ||||
679 | DAG.getIntPtrConstant(0, DL)); | ||||
680 | SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, | ||||
681 | DAG.getIntPtrConstant(1, DL)); | ||||
682 | |||||
683 | if (UseTest) { | ||||
684 | // When using tst we only care about the highest part. | ||||
685 | SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, | ||||
686 | DAG.getIntPtrConstant(1, DL)); | ||||
687 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); | ||||
688 | } else { | ||||
689 | Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL); | ||||
690 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); | ||||
691 | } | ||||
692 | } else if (VT == MVT::i64) { | ||||
693 | SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, | ||||
694 | DAG.getIntPtrConstant(0, DL)); | ||||
695 | SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, | ||||
696 | DAG.getIntPtrConstant(1, DL)); | ||||
697 | |||||
698 | SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, | ||||
699 | DAG.getIntPtrConstant(0, DL)); | ||||
700 | SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, | ||||
701 | DAG.getIntPtrConstant(1, DL)); | ||||
702 | SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, | ||||
703 | DAG.getIntPtrConstant(0, DL)); | ||||
704 | SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, | ||||
705 | DAG.getIntPtrConstant(1, DL)); | ||||
706 | |||||
707 | SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, | ||||
708 | DAG.getIntPtrConstant(0, DL)); | ||||
709 | SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, | ||||
710 | DAG.getIntPtrConstant(1, DL)); | ||||
711 | |||||
712 | SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, | ||||
713 | DAG.getIntPtrConstant(0, DL)); | ||||
714 | SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, | ||||
715 | DAG.getIntPtrConstant(1, DL)); | ||||
716 | SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, | ||||
717 | DAG.getIntPtrConstant(0, DL)); | ||||
718 | SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, | ||||
719 | DAG.getIntPtrConstant(1, DL)); | ||||
720 | |||||
721 | if (UseTest) { | ||||
722 | // When using tst we only care about the highest part. | ||||
723 | SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, | ||||
724 | DAG.getIntPtrConstant(1, DL)); | ||||
725 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); | ||||
726 | } else { | ||||
727 | Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); | ||||
728 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); | ||||
729 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); | ||||
730 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp); | ||||
731 | } | ||||
732 | } else if (VT == MVT::i8 || VT == MVT::i16) { | ||||
733 | if (UseTest) { | ||||
734 | // When using tst we only care about the highest part. | ||||
735 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, | ||||
736 | (VT == MVT::i8) | ||||
737 | ? LHS | ||||
738 | : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, | ||||
739 | LHS, DAG.getIntPtrConstant(1, DL))); | ||||
740 | } else { | ||||
741 | Cmp = getAVRCmp(LHS, RHS, DAG, DL); | ||||
742 | } | ||||
743 | } else { | ||||
744 | llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 744); | ||||
745 | } | ||||
746 | |||||
747 | // When using a test instruction AVRcc is already set. | ||||
748 | if (!UseTest) { | ||||
749 | AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); | ||||
750 | } | ||||
751 | |||||
752 | return Cmp; | ||||
753 | } | ||||
754 | |||||
755 | SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { | ||||
756 | SDValue Chain = Op.getOperand(0); | ||||
757 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); | ||||
758 | SDValue LHS = Op.getOperand(2); | ||||
759 | SDValue RHS = Op.getOperand(3); | ||||
760 | SDValue Dest = Op.getOperand(4); | ||||
761 | SDLoc dl(Op); | ||||
762 | |||||
763 | SDValue TargetCC; | ||||
764 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); | ||||
765 | |||||
766 | return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, | ||||
767 | Cmp); | ||||
768 | } | ||||
769 | |||||
770 | SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { | ||||
771 | SDValue LHS = Op.getOperand(0); | ||||
772 | SDValue RHS = Op.getOperand(1); | ||||
773 | SDValue TrueV = Op.getOperand(2); | ||||
774 | SDValue FalseV = Op.getOperand(3); | ||||
775 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); | ||||
776 | SDLoc dl(Op); | ||||
777 | |||||
778 | SDValue TargetCC; | ||||
779 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); | ||||
780 | |||||
781 | SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); | ||||
782 | SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; | ||||
783 | |||||
784 | return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); | ||||
785 | } | ||||
786 | |||||
787 | SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { | ||||
788 | SDValue LHS = Op.getOperand(0); | ||||
789 | SDValue RHS = Op.getOperand(1); | ||||
790 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||
791 | SDLoc DL(Op); | ||||
792 | |||||
793 | SDValue TargetCC; | ||||
794 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL); | ||||
795 | |||||
796 | SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); | ||||
797 | SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); | ||||
798 | SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); | ||||
799 | SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; | ||||
800 | |||||
801 | return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); | ||||
802 | } | ||||
803 | |||||
804 | SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { | ||||
805 | const MachineFunction &MF = DAG.getMachineFunction(); | ||||
806 | const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); | ||||
807 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); | ||||
808 | auto DL = DAG.getDataLayout(); | ||||
809 | SDLoc dl(Op); | ||||
810 | |||||
811 | // Vastart just stores the address of the VarArgsFrameIndex slot into the | ||||
812 | // memory location argument. | ||||
813 | SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); | ||||
814 | |||||
815 | return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), | ||||
816 | MachinePointerInfo(SV)); | ||||
817 | } | ||||
818 | |||||
819 | SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { | ||||
820 | switch (Op.getOpcode()) { | ||||
821 | default: | ||||
822 | llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 822); | ||||
823 | case ISD::SHL: | ||||
824 | case ISD::SRA: | ||||
825 | case ISD::SRL: | ||||
826 | case ISD::ROTL: | ||||
827 | case ISD::ROTR: | ||||
828 | return LowerShifts(Op, DAG); | ||||
829 | case ISD::GlobalAddress: | ||||
830 | return LowerGlobalAddress(Op, DAG); | ||||
831 | case ISD::BlockAddress: | ||||
832 | return LowerBlockAddress(Op, DAG); | ||||
833 | case ISD::BR_CC: | ||||
834 | return LowerBR_CC(Op, DAG); | ||||
835 | case ISD::SELECT_CC: | ||||
836 | return LowerSELECT_CC(Op, DAG); | ||||
837 | case ISD::SETCC: | ||||
838 | return LowerSETCC(Op, DAG); | ||||
839 | case ISD::VASTART: | ||||
840 | return LowerVASTART(Op, DAG); | ||||
841 | case ISD::SDIVREM: | ||||
842 | case ISD::UDIVREM: | ||||
843 | return LowerDivRem(Op, DAG); | ||||
844 | } | ||||
845 | |||||
846 | return SDValue(); | ||||
847 | } | ||||
848 | |||||
849 | /// Replace a node with an illegal result type | ||||
850 | /// with a new node built out of custom code. | ||||
851 | void AVRTargetLowering::ReplaceNodeResults(SDNode *N, | ||||
852 | SmallVectorImpl<SDValue> &Results, | ||||
853 | SelectionDAG &DAG) const { | ||||
854 | SDLoc DL(N); | ||||
855 | |||||
856 | switch (N->getOpcode()) { | ||||
857 | case ISD::ADD: { | ||||
858 | // Convert add (x, imm) into sub (x, -imm). | ||||
859 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { | ||||
860 | SDValue Sub = DAG.getNode( | ||||
861 | ISD::SUB, DL, N->getValueType(0), N->getOperand(0), | ||||
862 | DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0))); | ||||
863 | Results.push_back(Sub); | ||||
864 | } | ||||
865 | break; | ||||
866 | } | ||||
867 | default: { | ||||
868 | SDValue Res = LowerOperation(SDValue(N, 0), DAG); | ||||
869 | |||||
870 | for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) | ||||
871 | Results.push_back(Res.getValue(I)); | ||||
872 | |||||
873 | break; | ||||
874 | } | ||||
875 | } | ||||
876 | } | ||||
877 | |||||
878 | /// Return true if the addressing mode represented | ||||
879 | /// by AM is legal for this target, for a load/store of the specified type. | ||||
880 | bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL, | ||||
881 | const AddrMode &AM, Type *Ty, | ||||
882 | unsigned AS, | ||||
883 | Instruction *I) const { | ||||
884 | int64_t Offs = AM.BaseOffs; | ||||
885 | |||||
886 | // Allow absolute addresses. | ||||
887 | if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { | ||||
888 | return true; | ||||
889 | } | ||||
890 | |||||
891 | // Flash memory instructions only allow zero offsets. | ||||
892 | if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { | ||||
893 | return false; | ||||
894 | } | ||||
895 | |||||
896 | // Allow reg+<6bit> offset. | ||||
897 | if (Offs < 0) | ||||
898 | Offs = -Offs; | ||||
899 | if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && | ||||
900 | isUInt<6>(Offs)) { | ||||
901 | return true; | ||||
902 | } | ||||
903 | |||||
904 | return false; | ||||
905 | } | ||||
906 | |||||
907 | /// Returns true by value, base pointer and | ||||
908 | /// offset pointer and addressing mode by reference if the node's address | ||||
909 | /// can be legally represented as pre-indexed load / store address. | ||||
910 | bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, | ||||
911 | SDValue &Offset, | ||||
912 | ISD::MemIndexedMode &AM, | ||||
913 | SelectionDAG &DAG) const { | ||||
914 | EVT VT; | ||||
915 | const SDNode *Op; | ||||
916 | SDLoc DL(N); | ||||
917 | |||||
918 | if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { | ||||
919 | VT = LD->getMemoryVT(); | ||||
920 | Op = LD->getBasePtr().getNode(); | ||||
921 | if (LD->getExtensionType() != ISD::NON_EXTLOAD) | ||||
922 | return false; | ||||
923 | if (AVR::isProgramMemoryAccess(LD)) { | ||||
924 | return false; | ||||
925 | } | ||||
926 | } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { | ||||
927 | VT = ST->getMemoryVT(); | ||||
928 | Op = ST->getBasePtr().getNode(); | ||||
929 | if (AVR::isProgramMemoryAccess(ST)) { | ||||
930 | return false; | ||||
931 | } | ||||
932 | } else { | ||||
933 | return false; | ||||
934 | } | ||||
935 | |||||
936 | if (VT != MVT::i8 && VT != MVT::i16) { | ||||
937 | return false; | ||||
938 | } | ||||
939 | |||||
940 | if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { | ||||
941 | return false; | ||||
942 | } | ||||
943 | |||||
944 | if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { | ||||
945 | int RHSC = RHS->getSExtValue(); | ||||
946 | if (Op->getOpcode() == ISD::SUB) | ||||
947 | RHSC = -RHSC; | ||||
948 | |||||
949 | if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { | ||||
950 | return false; | ||||
951 | } | ||||
952 | |||||
953 | Base = Op->getOperand(0); | ||||
954 | Offset = DAG.getConstant(RHSC, DL, MVT::i8); | ||||
955 | AM = ISD::PRE_DEC; | ||||
956 | |||||
957 | return true; | ||||
958 | } | ||||
959 | |||||
960 | return false; | ||||
961 | } | ||||
962 | |||||
963 | /// Returns true by value, base pointer and | ||||
964 | /// offset pointer and addressing mode by reference if this node can be | ||||
965 | /// combined with a load / store to form a post-indexed load / store. | ||||
966 | bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, | ||||
967 | SDValue &Base, | ||||
968 | SDValue &Offset, | ||||
969 | ISD::MemIndexedMode &AM, | ||||
970 | SelectionDAG &DAG) const { | ||||
971 | EVT VT; | ||||
972 | SDLoc DL(N); | ||||
973 | |||||
974 | if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { | ||||
975 | VT = LD->getMemoryVT(); | ||||
976 | if (LD->getExtensionType() != ISD::NON_EXTLOAD) | ||||
977 | return false; | ||||
978 | } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { | ||||
979 | VT = ST->getMemoryVT(); | ||||
980 | if (AVR::isProgramMemoryAccess(ST)) { | ||||
981 | return false; | ||||
982 | } | ||||
983 | } else { | ||||
984 | return false; | ||||
985 | } | ||||
986 | |||||
987 | if (VT != MVT::i8 && VT != MVT::i16) { | ||||
988 | return false; | ||||
989 | } | ||||
990 | |||||
991 | if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { | ||||
992 | return false; | ||||
993 | } | ||||
994 | |||||
995 | if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { | ||||
996 | int RHSC = RHS->getSExtValue(); | ||||
997 | if (Op->getOpcode() == ISD::SUB) | ||||
998 | RHSC = -RHSC; | ||||
999 | if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { | ||||
1000 | return false; | ||||
1001 | } | ||||
1002 | |||||
1003 | Base = Op->getOperand(0); | ||||
1004 | Offset = DAG.getConstant(RHSC, DL, MVT::i8); | ||||
1005 | AM = ISD::POST_INC; | ||||
1006 | |||||
1007 | return true; | ||||
1008 | } | ||||
1009 | |||||
1010 | return false; | ||||
1011 | } | ||||
1012 | |||||
1013 | bool AVRTargetLowering::isOffsetFoldingLegal( | ||||
1014 | const GlobalAddressSDNode *GA) const { | ||||
1015 | return true; | ||||
1016 | } | ||||
1017 | |||||
1018 | //===----------------------------------------------------------------------===// | ||||
1019 | // Formal Arguments Calling Convention Implementation | ||||
1020 | //===----------------------------------------------------------------------===// | ||||
1021 | |||||
1022 | #include "AVRGenCallingConv.inc" | ||||
1023 | |||||
1024 | /// Registers for calling conventions, ordered in reverse as required by ABI. | ||||
1025 | /// Both arrays must be of the same length. | ||||
1026 | static const MCPhysReg RegList8[] = { | ||||
1027 | AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, | ||||
1028 | AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, | ||||
1029 | AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8}; | ||||
1030 | static const MCPhysReg RegList16[] = { | ||||
1031 | AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21, | ||||
1032 | AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16, | ||||
1033 | AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11, | ||||
1034 | AVR::R11R10, AVR::R10R9, AVR::R9R8}; | ||||
1035 | |||||
1036 | static_assert(array_lengthof(RegList8) == array_lengthof(RegList16), | ||||
1037 | "8-bit and 16-bit register arrays must be of equal length"); | ||||
1038 | |||||
1039 | /// Analyze incoming and outgoing function arguments. We need custom C++ code | ||||
1040 | /// to handle special constraints in the ABI. | ||||
1041 | /// In addition, all pieces of a certain argument have to be passed either | ||||
1042 | /// using registers or the stack but never mixing both. | ||||
1043 | template <typename ArgT> | ||||
1044 | static void | ||||
1045 | analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, | ||||
1046 | const DataLayout *TD, const SmallVectorImpl<ArgT> &Args, | ||||
1047 | SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) { | ||||
1048 | unsigned NumArgs = Args.size(); | ||||
1049 | // This is the index of the last used register, in RegList*. | ||||
1050 | // -1 means R26 (R26 is never actually used in CC). | ||||
1051 | int RegLastIdx = -1; | ||||
1052 | // Once a value is passed to the stack it will always be used | ||||
1053 | bool UseStack = false; | ||||
1054 | for (unsigned i = 0; i != NumArgs;) { | ||||
1055 | MVT VT = Args[i].VT; | ||||
1056 | // We have to count the number of bytes for each function argument, that is | ||||
1057 | // those Args with the same OrigArgIndex. This is important in case the | ||||
1058 | // function takes an aggregate type. | ||||
1059 | // Current argument will be between [i..j). | ||||
1060 | unsigned ArgIndex = Args[i].OrigArgIndex; | ||||
1061 | unsigned TotalBytes = VT.getStoreSize(); | ||||
1062 | unsigned j = i + 1; | ||||
1063 | for (; j != NumArgs; ++j) { | ||||
1064 | if (Args[j].OrigArgIndex != ArgIndex) | ||||
1065 | break; | ||||
1066 | TotalBytes += Args[j].VT.getStoreSize(); | ||||
1067 | } | ||||
1068 | // Round up to even number of bytes. | ||||
1069 | TotalBytes = alignTo(TotalBytes, 2); | ||||
1070 | // Skip zero sized arguments | ||||
1071 | if (TotalBytes == 0) | ||||
1072 | continue; | ||||
1073 | // The index of the first register to be used | ||||
1074 | unsigned RegIdx = RegLastIdx + TotalBytes; | ||||
1075 | RegLastIdx = RegIdx; | ||||
1076 | // If there are not enough registers, use the stack | ||||
1077 | if (RegIdx >= array_lengthof(RegList8)) { | ||||
1078 | UseStack = true; | ||||
1079 | } | ||||
1080 | for (; i != j; ++i) { | ||||
1081 | MVT VT = Args[i].VT; | ||||
1082 | |||||
1083 | if (UseStack) { | ||||
1084 | auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); | ||||
1085 | unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt), | ||||
1086 | TD->getABITypeAlign(evt)); | ||||
1087 | CCInfo.addLoc( | ||||
1088 | CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); | ||||
1089 | } else { | ||||
1090 | unsigned Reg; | ||||
1091 | if (VT == MVT::i8) { | ||||
1092 | Reg = CCInfo.AllocateReg(RegList8[RegIdx]); | ||||
1093 | } else if (VT == MVT::i16) { | ||||
1094 | Reg = CCInfo.AllocateReg(RegList16[RegIdx]); | ||||
1095 | } else { | ||||
1096 | llvm_unreachable(::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1097) | ||||
1097 | "calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1097); | ||||
1098 | } | ||||
1099 | assert(Reg && "register not available in calling convention")(static_cast <bool> (Reg && "register not available in calling convention" ) ? void (0) : __assert_fail ("Reg && \"register not available in calling convention\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1099, __extension__ __PRETTY_FUNCTION__)); | ||||
1100 | CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); | ||||
1101 | // Registers inside a particular argument are sorted in increasing order | ||||
1102 | // (remember the array is reversed). | ||||
1103 | RegIdx -= VT.getStoreSize(); | ||||
1104 | } | ||||
1105 | } | ||||
1106 | } | ||||
1107 | } | ||||
1108 | |||||
1109 | /// Count the total number of bytes needed to pass or return these arguments. | ||||
1110 | template <typename ArgT> | ||||
1111 | static unsigned | ||||
1112 | getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) { | ||||
1113 | unsigned TotalBytes = 0; | ||||
1114 | |||||
1115 | for (const ArgT &Arg : Args) { | ||||
1116 | TotalBytes += Arg.VT.getStoreSize(); | ||||
1117 | } | ||||
1118 | return TotalBytes; | ||||
1119 | } | ||||
1120 | |||||
1121 | /// Analyze incoming and outgoing value of returning from a function. | ||||
1122 | /// The algorithm is similar to analyzeArguments, but there can only be | ||||
1123 | /// one value, possibly an aggregate, and it is limited to 8 bytes. | ||||
1124 | template <typename ArgT> | ||||
1125 | static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args, | ||||
1126 | CCState &CCInfo) { | ||||
1127 | unsigned NumArgs = Args.size(); | ||||
1128 | unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args); | ||||
1129 | // CanLowerReturn() guarantees this assertion. | ||||
1130 | assert(TotalBytes <= 8 &&(static_cast <bool> (TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered" ) ? void (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1131, __extension__ __PRETTY_FUNCTION__)) | ||||
1131 | "return values greater than 8 bytes cannot be lowered")(static_cast <bool> (TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered" ) ? void (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1131, __extension__ __PRETTY_FUNCTION__)); | ||||
1132 | |||||
1133 | // GCC-ABI says that the size is rounded up to the next even number, | ||||
1134 | // but actually once it is more than 4 it will always round up to 8. | ||||
1135 | if (TotalBytes
| ||||
1136 | TotalBytes = 8; | ||||
1137 | } else { | ||||
1138 | TotalBytes = alignTo(TotalBytes, 2); | ||||
1139 | } | ||||
1140 | |||||
1141 | // The index of the first register to use. | ||||
1142 | int RegIdx = TotalBytes - 1; | ||||
1143 | for (unsigned i = 0; i != NumArgs; ++i) { | ||||
1144 | MVT VT = Args[i].VT; | ||||
1145 | unsigned Reg; | ||||
1146 | if (VT == MVT::i8) { | ||||
1147 | Reg = CCInfo.AllocateReg(RegList8[RegIdx]); | ||||
| |||||
1148 | } else if (VT == MVT::i16) { | ||||
1149 | Reg = CCInfo.AllocateReg(RegList16[RegIdx]); | ||||
1150 | } else { | ||||
1151 | llvm_unreachable("calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1151); | ||||
1152 | } | ||||
1153 | assert(Reg && "register not available in calling convention")(static_cast <bool> (Reg && "register not available in calling convention" ) ? void (0) : __assert_fail ("Reg && \"register not available in calling convention\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1153, __extension__ __PRETTY_FUNCTION__)); | ||||
1154 | CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); | ||||
1155 | // Registers sort in increasing order | ||||
1156 | RegIdx -= VT.getStoreSize(); | ||||
1157 | } | ||||
1158 | } | ||||
1159 | |||||
1160 | SDValue AVRTargetLowering::LowerFormalArguments( | ||||
1161 | SDValue Chain, CallingConv::ID CallConv, bool isVarArg, | ||||
1162 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, | ||||
1163 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { | ||||
1164 | MachineFunction &MF = DAG.getMachineFunction(); | ||||
1165 | MachineFrameInfo &MFI = MF.getFrameInfo(); | ||||
1166 | auto DL = DAG.getDataLayout(); | ||||
1167 | |||||
1168 | // Assign locations to all of the incoming arguments. | ||||
1169 | SmallVector<CCValAssign, 16> ArgLocs; | ||||
1170 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, | ||||
1171 | *DAG.getContext()); | ||||
1172 | |||||
1173 | // Variadic functions do not need all the analysis below. | ||||
1174 | if (isVarArg) { | ||||
1175 | CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg); | ||||
1176 | } else { | ||||
1177 | analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo); | ||||
1178 | } | ||||
1179 | |||||
1180 | SDValue ArgValue; | ||||
1181 | for (CCValAssign &VA : ArgLocs) { | ||||
1182 | |||||
1183 | // Arguments stored on registers. | ||||
1184 | if (VA.isRegLoc()) { | ||||
1185 | EVT RegVT = VA.getLocVT(); | ||||
1186 | const TargetRegisterClass *RC; | ||||
1187 | if (RegVT == MVT::i8) { | ||||
1188 | RC = &AVR::GPR8RegClass; | ||||
1189 | } else if (RegVT == MVT::i16) { | ||||
1190 | RC = &AVR::DREGSRegClass; | ||||
1191 | } else { | ||||
1192 | llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 1192); | ||||
1193 | } | ||||
1194 | |||||
1195 | Register Reg = MF.addLiveIn(VA.getLocReg(), RC); | ||||
1196 | ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); | ||||
1197 | |||||
1198 | // :NOTE: Clang should not promote any i8 into i16 but for safety the | ||||
1199 | // following code will handle zexts or sexts generated by other | ||||
1200 | // front ends. Otherwise: | ||||
1201 | // If this is an 8 bit value, it is really passed promoted | ||||
1202 | // to 16 bits. Insert an assert[sz]ext to capture this, then | ||||
1203 | // truncate to the right size. | ||||
1204 | switch (VA.getLocInfo()) { | ||||
1205 | default: | ||||
1206 | llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 1206); | ||||
1207 | case CCValAssign::Full: | ||||
1208 | break; | ||||
1209 | case CCValAssign::BCvt: | ||||
1210 | ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); | ||||
1211 | break; | ||||
1212 | case CCValAssign::SExt: | ||||
1213 | ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, | ||||
1214 | DAG.getValueType(VA.getValVT())); | ||||
1215 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); | ||||
1216 | break; | ||||
1217 | case CCValAssign::ZExt: | ||||
1218 | ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, | ||||
1219 | DAG.getValueType(VA.getValVT())); | ||||
1220 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); | ||||
1221 | break; | ||||
1222 | } | ||||
1223 | |||||
1224 | InVals.push_back(ArgValue); | ||||
1225 | } else { | ||||
1226 | // Only arguments passed on the stack should make it here. | ||||
1227 | assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail ("VA.isMemLoc()", "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1227, __extension__ __PRETTY_FUNCTION__)); | ||||
1228 | |||||
1229 | EVT LocVT = VA.getLocVT(); | ||||
1230 | |||||
1231 | // Create the frame index object for this incoming parameter. | ||||
1232 | int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, | ||||
1233 | VA.getLocMemOffset(), true); | ||||
1234 | |||||
1235 | // Create the SelectionDAG nodes corresponding to a load | ||||
1236 | // from this parameter. | ||||
1237 | SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); | ||||
1238 | InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, | ||||
1239 | MachinePointerInfo::getFixedStack(MF, FI))); | ||||
1240 | } | ||||
1241 | } | ||||
1242 | |||||
1243 | // If the function takes variable number of arguments, make a frame index for | ||||
1244 | // the start of the first vararg value... for expansion of llvm.va_start. | ||||
1245 | if (isVarArg) { | ||||
1246 | unsigned StackSize = CCInfo.getNextStackOffset(); | ||||
1247 | AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); | ||||
1248 | |||||
1249 | AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true)); | ||||
1250 | } | ||||
1251 | |||||
1252 | return Chain; | ||||
1253 | } | ||||
1254 | |||||
1255 | //===----------------------------------------------------------------------===// | ||||
1256 | // Call Calling Convention Implementation | ||||
1257 | //===----------------------------------------------------------------------===// | ||||
1258 | |||||
1259 | SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, | ||||
1260 | SmallVectorImpl<SDValue> &InVals) const { | ||||
1261 | SelectionDAG &DAG = CLI.DAG; | ||||
1262 | SDLoc &DL = CLI.DL; | ||||
1263 | SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; | ||||
1264 | SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; | ||||
1265 | SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; | ||||
1266 | SDValue Chain = CLI.Chain; | ||||
1267 | SDValue Callee = CLI.Callee; | ||||
1268 | bool &isTailCall = CLI.IsTailCall; | ||||
1269 | CallingConv::ID CallConv = CLI.CallConv; | ||||
1270 | bool isVarArg = CLI.IsVarArg; | ||||
1271 | |||||
1272 | MachineFunction &MF = DAG.getMachineFunction(); | ||||
1273 | |||||
1274 | // AVR does not yet support tail call optimization. | ||||
1275 | isTailCall = false; | ||||
1276 | |||||
1277 | // Analyze operands of the call, assigning locations to each operand. | ||||
1278 | SmallVector<CCValAssign, 16> ArgLocs; | ||||
1279 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, | ||||
1280 | *DAG.getContext()); | ||||
1281 | |||||
1282 | // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every | ||||
1283 | // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol | ||||
1284 | // node so that legalize doesn't hack it. | ||||
1285 | const Function *F = nullptr; | ||||
1286 | if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { | ||||
1287 | const GlobalValue *GV = G->getGlobal(); | ||||
1288 | if (isa<Function>(GV)) | ||||
1289 | F = cast<Function>(GV); | ||||
1290 | Callee = | ||||
1291 | DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout())); | ||||
1292 | } else if (const ExternalSymbolSDNode *ES = | ||||
1293 | dyn_cast<ExternalSymbolSDNode>(Callee)) { | ||||
1294 | Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), | ||||
1295 | getPointerTy(DAG.getDataLayout())); | ||||
1296 | } | ||||
1297 | |||||
1298 | // Variadic functions do not need all the analysis below. | ||||
1299 | if (isVarArg) { | ||||
1300 | CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg); | ||||
1301 | } else { | ||||
1302 | analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo); | ||||
1303 | } | ||||
1304 | |||||
1305 | // Get a count of how many bytes are to be pushed on the stack. | ||||
1306 | unsigned NumBytes = CCInfo.getNextStackOffset(); | ||||
1307 | |||||
1308 | Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL); | ||||
1309 | |||||
1310 | SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; | ||||
1311 | |||||
1312 | // First, walk the register assignments, inserting copies. | ||||
1313 | unsigned AI, AE; | ||||
1314 | bool HasStackArgs = false; | ||||
1315 | for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { | ||||
1316 | CCValAssign &VA = ArgLocs[AI]; | ||||
1317 | EVT RegVT = VA.getLocVT(); | ||||
1318 | SDValue Arg = OutVals[AI]; | ||||
1319 | |||||
1320 | // Promote the value if needed. With Clang this should not happen. | ||||
1321 | switch (VA.getLocInfo()) { | ||||
1322 | default: | ||||
1323 | llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 1323); | ||||
1324 | case CCValAssign::Full: | ||||
1325 | break; | ||||
1326 | case CCValAssign::SExt: | ||||
1327 | Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); | ||||
1328 | break; | ||||
1329 | case CCValAssign::ZExt: | ||||
1330 | Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); | ||||
1331 | break; | ||||
1332 | case CCValAssign::AExt: | ||||
1333 | Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); | ||||
1334 | break; | ||||
1335 | case CCValAssign::BCvt: | ||||
1336 | Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); | ||||
1337 | break; | ||||
1338 | } | ||||
1339 | |||||
1340 | // Stop when we encounter a stack argument, we need to process them | ||||
1341 | // in reverse order in the loop below. | ||||
1342 | if (VA.isMemLoc()) { | ||||
1343 | HasStackArgs = true; | ||||
1344 | break; | ||||
1345 | } | ||||
1346 | |||||
1347 | // Arguments that can be passed on registers must be kept in the RegsToPass | ||||
1348 | // vector. | ||||
1349 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); | ||||
1350 | } | ||||
1351 | |||||
1352 | // Second, stack arguments have to walked. | ||||
1353 | // Previously this code created chained stores but those chained stores appear | ||||
1354 | // to be unchained in the legalization phase. Therefore, do not attempt to | ||||
1355 | // chain them here. In fact, chaining them here somehow causes the first and | ||||
1356 | // second store to be reversed which is the exact opposite of the intended | ||||
1357 | // effect. | ||||
1358 | if (HasStackArgs) { | ||||
1359 | SmallVector<SDValue, 8> MemOpChains; | ||||
1360 | for (; AI != AE; AI++) { | ||||
1361 | CCValAssign &VA = ArgLocs[AI]; | ||||
1362 | SDValue Arg = OutVals[AI]; | ||||
1363 | |||||
1364 | assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail ("VA.isMemLoc()", "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1364, __extension__ __PRETTY_FUNCTION__)); | ||||
1365 | |||||
1366 | // SP points to one stack slot further so add one to adjust it. | ||||
1367 | SDValue PtrOff = DAG.getNode( | ||||
1368 | ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), | ||||
1369 | DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), | ||||
1370 | DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL)); | ||||
1371 | |||||
1372 | MemOpChains.push_back( | ||||
1373 | DAG.getStore(Chain, DL, Arg, PtrOff, | ||||
1374 | MachinePointerInfo::getStack(MF, VA.getLocMemOffset()))); | ||||
1375 | } | ||||
1376 | |||||
1377 | if (!MemOpChains.empty()) | ||||
1378 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); | ||||
1379 | } | ||||
1380 | |||||
1381 | // Build a sequence of copy-to-reg nodes chained together with token chain and | ||||
1382 | // flag operands which copy the outgoing args into registers. The InFlag in | ||||
1383 | // necessary since all emited instructions must be stuck together. | ||||
1384 | SDValue InFlag; | ||||
1385 | for (auto Reg : RegsToPass) { | ||||
1386 | Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag); | ||||
1387 | InFlag = Chain.getValue(1); | ||||
1388 | } | ||||
1389 | |||||
1390 | // Returns a chain & a flag for retval copy to use. | ||||
1391 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | ||||
1392 | SmallVector<SDValue, 8> Ops; | ||||
1393 | Ops.push_back(Chain); | ||||
1394 | Ops.push_back(Callee); | ||||
1395 | |||||
1396 | // Add argument registers to the end of the list so that they are known live | ||||
1397 | // into the call. | ||||
1398 | for (auto Reg : RegsToPass) { | ||||
1399 | Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); | ||||
1400 | } | ||||
1401 | |||||
1402 | // Add a register mask operand representing the call-preserved registers. | ||||
1403 | const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); | ||||
1404 | const uint32_t *Mask = | ||||
1405 | TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); | ||||
1406 | assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention" ) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1406, __extension__ __PRETTY_FUNCTION__)); | ||||
1407 | Ops.push_back(DAG.getRegisterMask(Mask)); | ||||
1408 | |||||
1409 | if (InFlag.getNode()) { | ||||
1410 | Ops.push_back(InFlag); | ||||
1411 | } | ||||
1412 | |||||
1413 | Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops); | ||||
1414 | InFlag = Chain.getValue(1); | ||||
1415 | |||||
1416 | // Create the CALLSEQ_END node. | ||||
1417 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), | ||||
1418 | DAG.getIntPtrConstant(0, DL, true), InFlag, DL); | ||||
1419 | |||||
1420 | if (!Ins.empty()) { | ||||
1421 | InFlag = Chain.getValue(1); | ||||
1422 | } | ||||
1423 | |||||
1424 | // Handle result values, copying them out of physregs into vregs that we | ||||
1425 | // return. | ||||
1426 | return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, | ||||
1427 | InVals); | ||||
1428 | } | ||||
1429 | |||||
1430 | /// Lower the result values of a call into the | ||||
1431 | /// appropriate copies out of appropriate physical registers. | ||||
1432 | /// | ||||
1433 | SDValue AVRTargetLowering::LowerCallResult( | ||||
1434 | SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, | ||||
1435 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, | ||||
1436 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { | ||||
1437 | |||||
1438 | // Assign locations to each value returned by this call. | ||||
1439 | SmallVector<CCValAssign, 16> RVLocs; | ||||
1440 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, | ||||
1441 | *DAG.getContext()); | ||||
1442 | |||||
1443 | // Handle runtime calling convs. | ||||
1444 | if (CallConv == CallingConv::AVR_BUILTIN) { | ||||
1445 | CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN); | ||||
1446 | } else { | ||||
1447 | analyzeReturnValues(Ins, CCInfo); | ||||
1448 | } | ||||
1449 | |||||
1450 | // Copy all of the result registers out of their specified physreg. | ||||
1451 | for (CCValAssign const &RVLoc : RVLocs) { | ||||
1452 | Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), | ||||
1453 | InFlag) | ||||
1454 | .getValue(1); | ||||
1455 | InFlag = Chain.getValue(2); | ||||
1456 | InVals.push_back(Chain.getValue(0)); | ||||
1457 | } | ||||
1458 | |||||
1459 | return Chain; | ||||
1460 | } | ||||
1461 | |||||
1462 | //===----------------------------------------------------------------------===// | ||||
1463 | // Return Value Calling Convention Implementation | ||||
1464 | //===----------------------------------------------------------------------===// | ||||
1465 | |||||
1466 | bool AVRTargetLowering::CanLowerReturn( | ||||
1467 | CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, | ||||
1468 | const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { | ||||
1469 | if (CallConv == CallingConv::AVR_BUILTIN) { | ||||
1470 | SmallVector<CCValAssign, 16> RVLocs; | ||||
1471 | CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); | ||||
1472 | return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN); | ||||
1473 | } | ||||
1474 | |||||
1475 | unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs); | ||||
1476 | return TotalBytes <= 8; | ||||
1477 | } | ||||
1478 | |||||
1479 | SDValue | ||||
1480 | AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, | ||||
1481 | bool isVarArg, | ||||
1482 | const SmallVectorImpl<ISD::OutputArg> &Outs, | ||||
1483 | const SmallVectorImpl<SDValue> &OutVals, | ||||
1484 | const SDLoc &dl, SelectionDAG &DAG) const { | ||||
1485 | // CCValAssign - represent the assignment of the return value to locations. | ||||
1486 | SmallVector<CCValAssign, 16> RVLocs; | ||||
1487 | |||||
1488 | // CCState - Info about the registers and stack slot. | ||||
1489 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, | ||||
1490 | *DAG.getContext()); | ||||
1491 | |||||
1492 | MachineFunction &MF = DAG.getMachineFunction(); | ||||
1493 | |||||
1494 | // Analyze return values. | ||||
1495 | if (CallConv == CallingConv::AVR_BUILTIN) { | ||||
| |||||
1496 | CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN); | ||||
1497 | } else { | ||||
1498 | analyzeReturnValues(Outs, CCInfo); | ||||
1499 | } | ||||
1500 | |||||
1501 | SDValue Flag; | ||||
1502 | SmallVector<SDValue, 4> RetOps(1, Chain); | ||||
1503 | // Copy the result values into the output registers. | ||||
1504 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { | ||||
1505 | CCValAssign &VA = RVLocs[i]; | ||||
1506 | assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!" ) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1506, __extension__ __PRETTY_FUNCTION__)); | ||||
1507 | |||||
1508 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); | ||||
1509 | |||||
1510 | // Guarantee that all emitted copies are stuck together with flags. | ||||
1511 | Flag = Chain.getValue(1); | ||||
1512 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); | ||||
1513 | } | ||||
1514 | |||||
1515 | // Don't emit the ret/reti instruction when the naked attribute is present in | ||||
1516 | // the function being compiled. | ||||
1517 | if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) { | ||||
1518 | return Chain; | ||||
1519 | } | ||||
1520 | |||||
1521 | const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); | ||||
1522 | |||||
1523 | unsigned RetOpc = | ||||
1524 | AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG; | ||||
1525 | |||||
1526 | RetOps[0] = Chain; // Update chain. | ||||
1527 | |||||
1528 | if (Flag.getNode()) { | ||||
1529 | RetOps.push_back(Flag); | ||||
1530 | } | ||||
1531 | |||||
1532 | return DAG.getNode(RetOpc, dl, MVT::Other, RetOps); | ||||
1533 | } | ||||
1534 | |||||
1535 | //===----------------------------------------------------------------------===// | ||||
1536 | // Custom Inserters | ||||
1537 | //===----------------------------------------------------------------------===// | ||||
1538 | |||||
1539 | MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, | ||||
1540 | MachineBasicBlock *BB) const { | ||||
1541 | unsigned Opc; | ||||
1542 | const TargetRegisterClass *RC; | ||||
1543 | bool HasRepeatedOperand = false; | ||||
1544 | MachineFunction *F = BB->getParent(); | ||||
1545 | MachineRegisterInfo &RI = F->getRegInfo(); | ||||
1546 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); | ||||
1547 | DebugLoc dl = MI.getDebugLoc(); | ||||
1548 | |||||
1549 | switch (MI.getOpcode()) { | ||||
1550 | default: | ||||
1551 | llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "llvm/lib/Target/AVR/AVRISelLowering.cpp" , 1551); | ||||
1552 | case AVR::Lsl8: | ||||
1553 | Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd | ||||
1554 | RC = &AVR::GPR8RegClass; | ||||
1555 | HasRepeatedOperand = true; | ||||
1556 | break; | ||||
1557 | case AVR::Lsl16: | ||||
1558 | Opc = AVR::LSLWRd; | ||||
1559 | RC = &AVR::DREGSRegClass; | ||||
1560 | break; | ||||
1561 | case AVR::Asr8: | ||||
1562 | Opc = AVR::ASRRd; | ||||
1563 | RC = &AVR::GPR8RegClass; | ||||
1564 | break; | ||||
1565 | case AVR::Asr16: | ||||
1566 | Opc = AVR::ASRWRd; | ||||
1567 | RC = &AVR::DREGSRegClass; | ||||
1568 | break; | ||||
1569 | case AVR::Lsr8: | ||||
1570 | Opc = AVR::LSRRd; | ||||
1571 | RC = &AVR::GPR8RegClass; | ||||
1572 | break; | ||||
1573 | case AVR::Lsr16: | ||||
1574 | Opc = AVR::LSRWRd; | ||||
1575 | RC = &AVR::DREGSRegClass; | ||||
1576 | break; | ||||
1577 | case AVR::Rol8: | ||||
1578 | Opc = AVR::ROLBRd; | ||||
1579 | RC = &AVR::GPR8RegClass; | ||||
1580 | break; | ||||
1581 | case AVR::Rol16: | ||||
1582 | Opc = AVR::ROLWRd; | ||||
1583 | RC = &AVR::DREGSRegClass; | ||||
1584 | break; | ||||
1585 | case AVR::Ror8: | ||||
1586 | Opc = AVR::RORBRd; | ||||
1587 | RC = &AVR::GPR8RegClass; | ||||
1588 | break; | ||||
1589 | case AVR::Ror16: | ||||
1590 | Opc = AVR::RORWRd; | ||||
1591 | RC = &AVR::DREGSRegClass; | ||||
1592 | break; | ||||
1593 | } | ||||
1594 | |||||
1595 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); | ||||
1596 | |||||
1597 | MachineFunction::iterator I; | ||||
1598 | for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I) | ||||
1599 | ; | ||||
1600 | if (I != F->end()) | ||||
1601 | ++I; | ||||
1602 | |||||
1603 | // Create loop block. | ||||
1604 | MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); | ||||
1605 | MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB); | ||||
1606 | MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); | ||||
1607 | |||||
1608 | F->insert(I, LoopBB); | ||||
1609 | F->insert(I, CheckBB); | ||||
1610 | F->insert(I, RemBB); | ||||
1611 | |||||
1612 | // Update machine-CFG edges by transferring all successors of the current | ||||
1613 | // block to the block containing instructions after shift. | ||||
1614 | RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), | ||||
1615 | BB->end()); | ||||
1616 | RemBB->transferSuccessorsAndUpdatePHIs(BB); | ||||
1617 | |||||
1618 | // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB. | ||||
1619 | BB->addSuccessor(CheckBB); | ||||
1620 | LoopBB->addSuccessor(CheckBB); | ||||
1621 | CheckBB->addSuccessor(LoopBB); | ||||
1622 | CheckBB->addSuccessor(RemBB); | ||||
1623 | |||||
1624 | Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); | ||||
1625 | Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); | ||||
1626 | Register ShiftReg = RI.createVirtualRegister(RC); | ||||
1627 | Register ShiftReg2 = RI.createVirtualRegister(RC); | ||||
1628 | Register ShiftAmtSrcReg = MI.getOperand(2).getReg(); | ||||
1629 | Register SrcReg = MI.getOperand(1).getReg(); | ||||
1630 | Register DstReg = MI.getOperand(0).getReg(); | ||||
1631 | |||||
1632 | // BB: | ||||
1633 | // rjmp CheckBB | ||||
1634 | BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); | ||||
1635 | |||||
1636 | // LoopBB: | ||||
1637 | // ShiftReg2 = shift ShiftReg | ||||
1638 | auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); | ||||
1639 | if (HasRepeatedOperand) | ||||
1640 | ShiftMI.addReg(ShiftReg); | ||||
1641 | |||||
1642 | // CheckBB: | ||||
1643 | // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] | ||||
1644 | // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] | ||||
1645 | // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] | ||||
1646 | // ShiftAmt2 = ShiftAmt - 1; | ||||
1647 | // if (ShiftAmt2 >= 0) goto LoopBB; | ||||
1648 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) | ||||
1649 | .addReg(SrcReg) | ||||
1650 | .addMBB(BB) | ||||
1651 | .addReg(ShiftReg2) | ||||
1652 | .addMBB(LoopBB); | ||||
1653 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) | ||||
1654 | .addReg(ShiftAmtSrcReg) | ||||
1655 | .addMBB(BB) | ||||
1656 | .addReg(ShiftAmtReg2) | ||||
1657 | .addMBB(LoopBB); | ||||
1658 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) | ||||
1659 | .addReg(SrcReg) | ||||
1660 | .addMBB(BB) | ||||
1661 | .addReg(ShiftReg2) | ||||
1662 | .addMBB(LoopBB); | ||||
1663 | |||||
1664 | BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg); | ||||
1665 | BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); | ||||
1666 | |||||
1667 | MI.eraseFromParent(); // The pseudo instruction is gone now. | ||||
1668 | return RemBB; | ||||
1669 | } | ||||
1670 | |||||
1671 | static bool isCopyMulResult(MachineBasicBlock::iterator const &I) { | ||||
1672 | if (I->getOpcode() == AVR::COPY) { | ||||
1673 | Register SrcReg = I->getOperand(1).getReg(); | ||||
1674 | return (SrcReg == AVR::R0 || SrcReg == AVR::R1); | ||||
1675 | } | ||||
1676 | |||||
1677 | return false; | ||||
1678 | } | ||||
1679 | |||||
1680 | // The mul instructions wreak havock on our zero_reg R1. We need to clear it | ||||
1681 | // after the result has been evacuated. This is probably not the best way to do | ||||
1682 | // it, but it works for now. | ||||
1683 | MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI, | ||||
1684 | MachineBasicBlock *BB) const { | ||||
1685 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); | ||||
1686 | MachineBasicBlock::iterator I(MI); | ||||
1687 | ++I; // in any case insert *after* the mul instruction | ||||
1688 | if (isCopyMulResult(I)) | ||||
1689 | ++I; | ||||
1690 | if (isCopyMulResult(I)) | ||||
1691 | ++I; | ||||
1692 | BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) | ||||
1693 | .addReg(AVR::R1) | ||||
1694 | .addReg(AVR::R1); | ||||
1695 | return BB; | ||||
1696 | } | ||||
1697 | |||||
1698 | // Insert a read from R1, which almost always contains the value 0. | ||||
1699 | MachineBasicBlock * | ||||
1700 | AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const { | ||||
1701 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); | ||||
1702 | MachineBasicBlock::iterator I(MI); | ||||
1703 | BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY)) | ||||
1704 | .add(MI.getOperand(0)) | ||||
1705 | .addReg(AVR::R1); | ||||
1706 | MI.eraseFromParent(); | ||||
1707 | return BB; | ||||
1708 | } | ||||
1709 | |||||
1710 | // Lower atomicrmw operation to disable interrupts, do operation, and restore | ||||
1711 | // interrupts. This works because all AVR microcontrollers are single core. | ||||
1712 | MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp( | ||||
1713 | MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const { | ||||
1714 | MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); | ||||
1715 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); | ||||
1716 | MachineBasicBlock::iterator I(MI); | ||||
1717 | const Register SCRATCH_REGISTER = AVR::R0; | ||||
1718 | DebugLoc dl = MI.getDebugLoc(); | ||||
1719 | |||||
1720 | // Example instruction sequence, for an atomic 8-bit add: | ||||
1721 | // ldi r25, 5 | ||||
1722 | // in r0, SREG | ||||
1723 | // cli | ||||
1724 | // ld r24, X | ||||
1725 | // add r25, r24 | ||||
1726 | // st X, r25 | ||||
1727 | // out SREG, r0 | ||||
1728 | |||||
1729 | const TargetRegisterClass *RC = | ||||
1730 | (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass; | ||||
1731 | unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr; | ||||
1732 | unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr; | ||||
1733 | |||||
1734 | // Disable interrupts. | ||||
1735 | BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER) | ||||
1736 | .addImm(Subtarget.getIORegSREG()); | ||||
1737 | BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7); | ||||
1738 | |||||
1739 | // Load the original value. | ||||
1740 | BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg()) | ||||
1741 | .add(MI.getOperand(1)); | ||||
1742 | |||||
1743 | // Do the arithmetic operation. | ||||
1744 | Register Result = MRI.createVirtualRegister(RC); | ||||
1745 | BuildMI(*BB, I, dl, TII.get(Opcode), Result) | ||||
1746 | .addReg(MI.getOperand(0).getReg()) | ||||
1747 | .add(MI.getOperand(2)); | ||||
1748 | |||||
1749 | // Store the result. | ||||
1750 | BuildMI(*BB, I, dl, TII.get(StoreOpcode)) | ||||
1751 | .add(MI.getOperand(1)) | ||||
1752 | .addReg(Result); | ||||
1753 | |||||
1754 | // Restore interrupts. | ||||
1755 | BuildMI(*BB, I, dl, TII.get(AVR::OUTARr)) | ||||
1756 | .addImm(Subtarget.getIORegSREG()) | ||||
1757 | .addReg(SCRATCH_REGISTER); | ||||
1758 | |||||
1759 | // Remove the pseudo instruction. | ||||
1760 | MI.eraseFromParent(); | ||||
1761 | return BB; | ||||
1762 | } | ||||
1763 | |||||
1764 | MachineBasicBlock * | ||||
1765 | AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, | ||||
1766 | MachineBasicBlock *MBB) const { | ||||
1767 | int Opc = MI.getOpcode(); | ||||
1768 | |||||
1769 | // Pseudo shift instructions with a non constant shift amount are expanded | ||||
1770 | // into a loop. | ||||
1771 | switch (Opc) { | ||||
1772 | case AVR::Lsl8: | ||||
1773 | case AVR::Lsl16: | ||||
1774 | case AVR::Lsr8: | ||||
1775 | case AVR::Lsr16: | ||||
1776 | case AVR::Rol8: | ||||
1777 | case AVR::Rol16: | ||||
1778 | case AVR::Ror8: | ||||
1779 | case AVR::Ror16: | ||||
1780 | case AVR::Asr8: | ||||
1781 | case AVR::Asr16: | ||||
1782 | return insertShift(MI, MBB); | ||||
1783 | case AVR::MULRdRr: | ||||
1784 | case AVR::MULSRdRr: | ||||
1785 | return insertMul(MI, MBB); | ||||
1786 | case AVR::CopyR1: | ||||
1787 | return insertCopyR1(MI, MBB); | ||||
1788 | case AVR::AtomicLoadAdd8: | ||||
1789 | return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8); | ||||
1790 | case AVR::AtomicLoadAdd16: | ||||
1791 | return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16); | ||||
1792 | case AVR::AtomicLoadSub8: | ||||
1793 | return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8); | ||||
1794 | case AVR::AtomicLoadSub16: | ||||
1795 | return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16); | ||||
1796 | case AVR::AtomicLoadAnd8: | ||||
1797 | return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8); | ||||
1798 | case AVR::AtomicLoadAnd16: | ||||
1799 | return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16); | ||||
1800 | case AVR::AtomicLoadOr8: | ||||
1801 | return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8); | ||||
1802 | case AVR::AtomicLoadOr16: | ||||
1803 | return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16); | ||||
1804 | case AVR::AtomicLoadXor8: | ||||
1805 | return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8); | ||||
1806 | case AVR::AtomicLoadXor16: | ||||
1807 | return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16); | ||||
1808 | } | ||||
1809 | |||||
1810 | assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(static_cast <bool> ((Opc == AVR::Select16 || Opc == AVR ::Select8) && "Unexpected instr type to insert") ? void (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1811, __extension__ __PRETTY_FUNCTION__)) | ||||
1811 | "Unexpected instr type to insert")(static_cast <bool> ((Opc == AVR::Select16 || Opc == AVR ::Select8) && "Unexpected instr type to insert") ? void (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\"" , "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1811, __extension__ __PRETTY_FUNCTION__)); | ||||
1812 | |||||
1813 | const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() | ||||
1814 | ->getParent() | ||||
1815 | ->getSubtarget() | ||||
1816 | .getInstrInfo(); | ||||
1817 | DebugLoc dl = MI.getDebugLoc(); | ||||
1818 | |||||
1819 | // To "insert" a SELECT instruction, we insert the diamond | ||||
1820 | // control-flow pattern. The incoming instruction knows the | ||||
1821 | // destination vreg to set, the condition code register to branch | ||||
1822 | // on, the true/false values to select between, and a branch opcode | ||||
1823 | // to use. | ||||
1824 | |||||
1825 | MachineFunction *MF = MBB->getParent(); | ||||
1826 | const BasicBlock *LLVM_BB = MBB->getBasicBlock(); | ||||
1827 | MachineBasicBlock *FallThrough = MBB->getFallThrough(); | ||||
1828 | |||||
1829 | // If the current basic block falls through to another basic block, | ||||
1830 | // we must insert an unconditional branch to the fallthrough destination | ||||
1831 | // if we are to insert basic blocks at the prior fallthrough point. | ||||
1832 | if (FallThrough != nullptr) { | ||||
1833 | BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); | ||||
1834 | } | ||||
1835 | |||||
1836 | MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB); | ||||
1837 | MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB); | ||||
1838 | |||||
1839 | MachineFunction::iterator I; | ||||
1840 | for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I) | ||||
1841 | ; | ||||
1842 | if (I != MF->end()) | ||||
1843 | ++I; | ||||
1844 | MF->insert(I, trueMBB); | ||||
1845 | MF->insert(I, falseMBB); | ||||
1846 | |||||
1847 | // Transfer remaining instructions and all successors of the current | ||||
1848 | // block to the block which will contain the Phi node for the | ||||
1849 | // select. | ||||
1850 | trueMBB->splice(trueMBB->begin(), MBB, | ||||
1851 | std::next(MachineBasicBlock::iterator(MI)), MBB->end()); | ||||
1852 | trueMBB->transferSuccessorsAndUpdatePHIs(MBB); | ||||
1853 | |||||
1854 | AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm(); | ||||
1855 | BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB); | ||||
1856 | BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); | ||||
1857 | MBB->addSuccessor(falseMBB); | ||||
1858 | MBB->addSuccessor(trueMBB); | ||||
1859 | |||||
1860 | // Unconditionally flow back to the true block | ||||
1861 | BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); | ||||
1862 | falseMBB->addSuccessor(trueMBB); | ||||
1863 | |||||
1864 | // Set up the Phi node to determine where we came from | ||||
1865 | BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), | ||||
1866 | MI.getOperand(0).getReg()) | ||||
1867 | .addReg(MI.getOperand(1).getReg()) | ||||
1868 | .addMBB(MBB) | ||||
1869 | .addReg(MI.getOperand(2).getReg()) | ||||
1870 | .addMBB(falseMBB); | ||||
1871 | |||||
1872 | MI.eraseFromParent(); // The pseudo instruction is gone now. | ||||
1873 | return trueMBB; | ||||
1874 | } | ||||
1875 | |||||
1876 | //===----------------------------------------------------------------------===// | ||||
1877 | // Inline Asm Support | ||||
1878 | //===----------------------------------------------------------------------===// | ||||
1879 | |||||
1880 | AVRTargetLowering::ConstraintType | ||||
1881 | AVRTargetLowering::getConstraintType(StringRef Constraint) const { | ||||
1882 | if (Constraint.size() == 1) { | ||||
1883 | // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html | ||||
1884 | switch (Constraint[0]) { | ||||
1885 | default: | ||||
1886 | break; | ||||
1887 | case 'a': // Simple upper registers | ||||
1888 | case 'b': // Base pointer registers pairs | ||||
1889 | case 'd': // Upper register | ||||
1890 | case 'l': // Lower registers | ||||
1891 | case 'e': // Pointer register pairs | ||||
1892 | case 'q': // Stack pointer register | ||||
1893 | case 'r': // Any register | ||||
1894 | case 'w': // Special upper register pairs | ||||
1895 | return C_RegisterClass; | ||||
1896 | case 't': // Temporary register | ||||
1897 | case 'x': | ||||
1898 | case 'X': // Pointer register pair X | ||||
1899 | case 'y': | ||||
1900 | case 'Y': // Pointer register pair Y | ||||
1901 | case 'z': | ||||
1902 | case 'Z': // Pointer register pair Z | ||||
1903 | return C_Register; | ||||
1904 | case 'Q': // A memory address based on Y or Z pointer with displacement. | ||||
1905 | return C_Memory; | ||||
1906 | case 'G': // Floating point constant | ||||
1907 | case 'I': // 6-bit positive integer constant | ||||
1908 | case 'J': // 6-bit negative integer constant | ||||
1909 | case 'K': // Integer constant (Range: 2) | ||||
1910 | case 'L': // Integer constant (Range: 0) | ||||
1911 | case 'M': // 8-bit integer constant | ||||
1912 | case 'N': // Integer constant (Range: -1) | ||||
1913 | case 'O': // Integer constant (Range: 8, 16, 24) | ||||
1914 | case 'P': // Integer constant (Range: 1) | ||||
1915 | case 'R': // Integer constant (Range: -6 to 5)x | ||||
1916 | return C_Immediate; | ||||
1917 | } | ||||
1918 | } | ||||
1919 | |||||
1920 | return TargetLowering::getConstraintType(Constraint); | ||||
1921 | } | ||||
1922 | |||||
1923 | unsigned | ||||
1924 | AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { | ||||
1925 | // Not sure if this is actually the right thing to do, but we got to do | ||||
1926 | // *something* [agnat] | ||||
1927 | switch (ConstraintCode[0]) { | ||||
1928 | case 'Q': | ||||
1929 | return InlineAsm::Constraint_Q; | ||||
1930 | } | ||||
1931 | return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); | ||||
1932 | } | ||||
1933 | |||||
1934 | AVRTargetLowering::ConstraintWeight | ||||
1935 | AVRTargetLowering::getSingleConstraintMatchWeight( | ||||
1936 | AsmOperandInfo &info, const char *constraint) const { | ||||
1937 | ConstraintWeight weight = CW_Invalid; | ||||
1938 | Value *CallOperandVal = info.CallOperandVal; | ||||
1939 | |||||
1940 | // If we don't have a value, we can't do a match, | ||||
1941 | // but allow it at the lowest weight. | ||||
1942 | // (this behaviour has been copied from the ARM backend) | ||||
1943 | if (!CallOperandVal) { | ||||
1944 | return CW_Default; | ||||
1945 | } | ||||
1946 | |||||
1947 | // Look at the constraint type. | ||||
1948 | switch (*constraint) { | ||||
1949 | default: | ||||
1950 | weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); | ||||
1951 | break; | ||||
1952 | case 'd': | ||||
1953 | case 'r': | ||||
1954 | case 'l': | ||||
1955 | weight = CW_Register; | ||||
1956 | break; | ||||
1957 | case 'a': | ||||
1958 | case 'b': | ||||
1959 | case 'e': | ||||
1960 | case 'q': | ||||
1961 | case 't': | ||||
1962 | case 'w': | ||||
1963 | case 'x': | ||||
1964 | case 'X': | ||||
1965 | case 'y': | ||||
1966 | case 'Y': | ||||
1967 | case 'z': | ||||
1968 | case 'Z': | ||||
1969 | weight = CW_SpecificReg; | ||||
1970 | break; | ||||
1971 | case 'G': | ||||
1972 | if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) { | ||||
1973 | if (C->isZero()) { | ||||
1974 | weight = CW_Constant; | ||||
1975 | } | ||||
1976 | } | ||||
1977 | break; | ||||
1978 | case 'I': | ||||
1979 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
1980 | if (isUInt<6>(C->getZExtValue())) { | ||||
1981 | weight = CW_Constant; | ||||
1982 | } | ||||
1983 | } | ||||
1984 | break; | ||||
1985 | case 'J': | ||||
1986 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
1987 | if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) { | ||||
1988 | weight = CW_Constant; | ||||
1989 | } | ||||
1990 | } | ||||
1991 | break; | ||||
1992 | case 'K': | ||||
1993 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
1994 | if (C->getZExtValue() == 2) { | ||||
1995 | weight = CW_Constant; | ||||
1996 | } | ||||
1997 | } | ||||
1998 | break; | ||||
1999 | case 'L': | ||||
2000 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2001 | if (C->getZExtValue() == 0) { | ||||
2002 | weight = CW_Constant; | ||||
2003 | } | ||||
2004 | } | ||||
2005 | break; | ||||
2006 | case 'M': | ||||
2007 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2008 | if (isUInt<8>(C->getZExtValue())) { | ||||
2009 | weight = CW_Constant; | ||||
2010 | } | ||||
2011 | } | ||||
2012 | break; | ||||
2013 | case 'N': | ||||
2014 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2015 | if (C->getSExtValue() == -1) { | ||||
2016 | weight = CW_Constant; | ||||
2017 | } | ||||
2018 | } | ||||
2019 | break; | ||||
2020 | case 'O': | ||||
2021 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2022 | if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) || | ||||
2023 | (C->getZExtValue() == 24)) { | ||||
2024 | weight = CW_Constant; | ||||
2025 | } | ||||
2026 | } | ||||
2027 | break; | ||||
2028 | case 'P': | ||||
2029 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2030 | if (C->getZExtValue() == 1) { | ||||
2031 | weight = CW_Constant; | ||||
2032 | } | ||||
2033 | } | ||||
2034 | break; | ||||
2035 | case 'R': | ||||
2036 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { | ||||
2037 | if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) { | ||||
2038 | weight = CW_Constant; | ||||
2039 | } | ||||
2040 | } | ||||
2041 | break; | ||||
2042 | case 'Q': | ||||
2043 | weight = CW_Memory; | ||||
2044 | break; | ||||
2045 | } | ||||
2046 | |||||
2047 | return weight; | ||||
2048 | } | ||||
2049 | |||||
2050 | std::pair<unsigned, const TargetRegisterClass *> | ||||
2051 | AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, | ||||
2052 | StringRef Constraint, | ||||
2053 | MVT VT) const { | ||||
2054 | if (Constraint.size() == 1) { | ||||
2055 | switch (Constraint[0]) { | ||||
2056 | case 'a': // Simple upper registers r16..r23. | ||||
2057 | if (VT == MVT::i8) | ||||
2058 | return std::make_pair(0U, &AVR::LD8loRegClass); | ||||
2059 | else if (VT == MVT::i16) | ||||
2060 | return std::make_pair(0U, &AVR::DREGSLD8loRegClass); | ||||
2061 | break; | ||||
2062 | case 'b': // Base pointer registers: y, z. | ||||
2063 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2064 | return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); | ||||
2065 | break; | ||||
2066 | case 'd': // Upper registers r16..r31. | ||||
2067 | if (VT == MVT::i8) | ||||
2068 | return std::make_pair(0U, &AVR::LD8RegClass); | ||||
2069 | else if (VT == MVT::i16) | ||||
2070 | return std::make_pair(0U, &AVR::DLDREGSRegClass); | ||||
2071 | break; | ||||
2072 | case 'l': // Lower registers r0..r15. | ||||
2073 | if (VT == MVT::i8) | ||||
2074 | return std::make_pair(0U, &AVR::GPR8loRegClass); | ||||
2075 | else if (VT == MVT::i16) | ||||
2076 | return std::make_pair(0U, &AVR::DREGSloRegClass); | ||||
2077 | break; | ||||
2078 | case 'e': // Pointer register pairs: x, y, z. | ||||
2079 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2080 | return std::make_pair(0U, &AVR::PTRREGSRegClass); | ||||
2081 | break; | ||||
2082 | case 'q': // Stack pointer register: SPH:SPL. | ||||
2083 | return std::make_pair(0U, &AVR::GPRSPRegClass); | ||||
2084 | case 'r': // Any register: r0..r31. | ||||
2085 | if (VT == MVT::i8) | ||||
2086 | return std::make_pair(0U, &AVR::GPR8RegClass); | ||||
2087 | else if (VT == MVT::i16) | ||||
2088 | return std::make_pair(0U, &AVR::DREGSRegClass); | ||||
2089 | break; | ||||
2090 | case 't': // Temporary register: r0. | ||||
2091 | if (VT == MVT::i8) | ||||
2092 | return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); | ||||
2093 | break; | ||||
2094 | case 'w': // Special upper register pairs: r24, r26, r28, r30. | ||||
2095 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2096 | return std::make_pair(0U, &AVR::IWREGSRegClass); | ||||
2097 | break; | ||||
2098 | case 'x': // Pointer register pair X: r27:r26. | ||||
2099 | case 'X': | ||||
2100 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2101 | return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); | ||||
2102 | break; | ||||
2103 | case 'y': // Pointer register pair Y: r29:r28. | ||||
2104 | case 'Y': | ||||
2105 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2106 | return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); | ||||
2107 | break; | ||||
2108 | case 'z': // Pointer register pair Z: r31:r30. | ||||
2109 | case 'Z': | ||||
2110 | if (VT == MVT::i8 || VT == MVT::i16) | ||||
2111 | return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); | ||||
2112 | break; | ||||
2113 | default: | ||||
2114 | break; | ||||
2115 | } | ||||
2116 | } | ||||
2117 | |||||
2118 | return TargetLowering::getRegForInlineAsmConstraint( | ||||
2119 | Subtarget.getRegisterInfo(), Constraint, VT); | ||||
2120 | } | ||||
2121 | |||||
2122 | void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, | ||||
2123 | std::string &Constraint, | ||||
2124 | std::vector<SDValue> &Ops, | ||||
2125 | SelectionDAG &DAG) const { | ||||
2126 | SDValue Result; | ||||
2127 | SDLoc DL(Op); | ||||
2128 | EVT Ty = Op.getValueType(); | ||||
2129 | |||||
2130 | // Currently only support length 1 constraints. | ||||
2131 | if (Constraint.length() != 1) { | ||||
2132 | return; | ||||
2133 | } | ||||
2134 | |||||
2135 | char ConstraintLetter = Constraint[0]; | ||||
2136 | switch (ConstraintLetter) { | ||||
2137 | default: | ||||
2138 | break; | ||||
2139 | // Deal with integers first: | ||||
2140 | case 'I': | ||||
2141 | case 'J': | ||||
2142 | case 'K': | ||||
2143 | case 'L': | ||||
2144 | case 'M': | ||||
2145 | case 'N': | ||||
2146 | case 'O': | ||||
2147 | case 'P': | ||||
2148 | case 'R': { | ||||
2149 | const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); | ||||
2150 | if (!C) { | ||||
2151 | return; | ||||
2152 | } | ||||
2153 | |||||
2154 | int64_t CVal64 = C->getSExtValue(); | ||||
2155 | uint64_t CUVal64 = C->getZExtValue(); | ||||
2156 | switch (ConstraintLetter) { | ||||
2157 | case 'I': // 0..63 | ||||
2158 | if (!isUInt<6>(CUVal64)) | ||||
2159 | return; | ||||
2160 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2161 | break; | ||||
2162 | case 'J': // -63..0 | ||||
2163 | if (CVal64 < -63 || CVal64 > 0) | ||||
2164 | return; | ||||
2165 | Result = DAG.getTargetConstant(CVal64, DL, Ty); | ||||
2166 | break; | ||||
2167 | case 'K': // 2 | ||||
2168 | if (CUVal64 != 2) | ||||
2169 | return; | ||||
2170 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2171 | break; | ||||
2172 | case 'L': // 0 | ||||
2173 | if (CUVal64 != 0) | ||||
2174 | return; | ||||
2175 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2176 | break; | ||||
2177 | case 'M': // 0..255 | ||||
2178 | if (!isUInt<8>(CUVal64)) | ||||
2179 | return; | ||||
2180 | // i8 type may be printed as a negative number, | ||||
2181 | // e.g. 254 would be printed as -2, | ||||
2182 | // so we force it to i16 at least. | ||||
2183 | if (Ty.getSimpleVT() == MVT::i8) { | ||||
2184 | Ty = MVT::i16; | ||||
2185 | } | ||||
2186 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2187 | break; | ||||
2188 | case 'N': // -1 | ||||
2189 | if (CVal64 != -1) | ||||
2190 | return; | ||||
2191 | Result = DAG.getTargetConstant(CVal64, DL, Ty); | ||||
2192 | break; | ||||
2193 | case 'O': // 8, 16, 24 | ||||
2194 | if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24) | ||||
2195 | return; | ||||
2196 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2197 | break; | ||||
2198 | case 'P': // 1 | ||||
2199 | if (CUVal64 != 1) | ||||
2200 | return; | ||||
2201 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); | ||||
2202 | break; | ||||
2203 | case 'R': // -6..5 | ||||
2204 | if (CVal64 < -6 || CVal64 > 5) | ||||
2205 | return; | ||||
2206 | Result = DAG.getTargetConstant(CVal64, DL, Ty); | ||||
2207 | break; | ||||
2208 | } | ||||
2209 | |||||
2210 | break; | ||||
2211 | } | ||||
2212 | case 'G': | ||||
2213 | const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op); | ||||
2214 | if (!FC || !FC->isZero()) | ||||
2215 | return; | ||||
2216 | // Soften float to i8 0 | ||||
2217 | Result = DAG.getTargetConstant(0, DL, MVT::i8); | ||||
2218 | break; | ||||
2219 | } | ||||
2220 | |||||
2221 | if (Result.getNode()) { | ||||
2222 | Ops.push_back(Result); | ||||
2223 | return; | ||||
2224 | } | ||||
2225 | |||||
2226 | return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); | ||||
2227 | } | ||||
2228 | |||||
2229 | Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, | ||||
2230 | const MachineFunction &MF) const { | ||||
2231 | Register Reg; | ||||
2232 | |||||
2233 | if (VT == LLT::scalar(8)) { | ||||
2234 | Reg = StringSwitch<unsigned>(RegName) | ||||
2235 | .Case("r0", AVR::R0) | ||||
2236 | .Case("r1", AVR::R1) | ||||
2237 | .Default(0); | ||||
2238 | } else { | ||||
2239 | Reg = StringSwitch<unsigned>(RegName) | ||||
2240 | .Case("r0", AVR::R1R0) | ||||
2241 | .Case("sp", AVR::SP) | ||||
2242 | .Default(0); | ||||
2243 | } | ||||
2244 | |||||
2245 | if (Reg) | ||||
2246 | return Reg; | ||||
2247 | |||||
2248 | report_fatal_error( | ||||
2249 | Twine("Invalid register name \"" + StringRef(RegName) + "\".")); | ||||
2250 | } | ||||
2251 | |||||
2252 | } // end of namespace llvm |
1 | //===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the set of machine-level target independent types which |
10 | // legal values in the code generator use. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H |
15 | #define LLVM_SUPPORT_MACHINEVALUETYPE_H |
16 | |
17 | #include "llvm/ADT/Sequence.h" |
18 | #include "llvm/ADT/iterator_range.h" |
19 | #include "llvm/Support/ErrorHandling.h" |
20 | #include "llvm/Support/MathExtras.h" |
21 | #include "llvm/Support/TypeSize.h" |
22 | #include <cassert> |
23 | |
24 | namespace llvm { |
25 | |
26 | class Type; |
27 | |
28 | /// Machine Value Type. Every type that is supported natively by some |
29 | /// processor targeted by LLVM occurs here. This means that any legal value |
30 | /// type can be represented by an MVT. |
31 | class MVT { |
32 | public: |
33 | enum SimpleValueType : uint8_t { |
34 | // clang-format off |
35 | |
36 | // Simple value types that aren't explicitly part of this enumeration |
37 | // are considered extended value types. |
38 | INVALID_SIMPLE_VALUE_TYPE = 0, |
39 | |
40 | // If you change this numbering, you must change the values in |
41 | // ValueTypes.td as well! |
42 | Other = 1, // This is a non-standard value |
43 | i1 = 2, // This is a 1 bit integer value |
44 | i8 = 3, // This is an 8 bit integer value |
45 | i16 = 4, // This is a 16 bit integer value |
46 | i32 = 5, // This is a 32 bit integer value |
47 | i64 = 6, // This is a 64 bit integer value |
48 | i128 = 7, // This is a 128 bit integer value |
49 | |
50 | FIRST_INTEGER_VALUETYPE = i1, |
51 | LAST_INTEGER_VALUETYPE = i128, |
52 | |
53 | bf16 = 8, // This is a 16 bit brain floating point value |
54 | f16 = 9, // This is a 16 bit floating point value |
55 | f32 = 10, // This is a 32 bit floating point value |
56 | f64 = 11, // This is a 64 bit floating point value |
57 | f80 = 12, // This is a 80 bit floating point value |
58 | f128 = 13, // This is a 128 bit floating point value |
59 | ppcf128 = 14, // This is a PPC 128-bit floating point value |
60 | |
61 | FIRST_FP_VALUETYPE = bf16, |
62 | LAST_FP_VALUETYPE = ppcf128, |
63 | |
64 | v1i1 = 15, // 1 x i1 |
65 | v2i1 = 16, // 2 x i1 |
66 | v4i1 = 17, // 4 x i1 |
67 | v8i1 = 18, // 8 x i1 |
68 | v16i1 = 19, // 16 x i1 |
69 | v32i1 = 20, // 32 x i1 |
70 | v64i1 = 21, // 64 x i1 |
71 | v128i1 = 22, // 128 x i1 |
72 | v256i1 = 23, // 256 x i1 |
73 | v512i1 = 24, // 512 x i1 |
74 | v1024i1 = 25, // 1024 x i1 |
75 | |
76 | v1i8 = 26, // 1 x i8 |
77 | v2i8 = 27, // 2 x i8 |
78 | v4i8 = 28, // 4 x i8 |
79 | v8i8 = 29, // 8 x i8 |
80 | v16i8 = 30, // 16 x i8 |
81 | v32i8 = 31, // 32 x i8 |
82 | v64i8 = 32, // 64 x i8 |
83 | v128i8 = 33, // 128 x i8 |
84 | v256i8 = 34, // 256 x i8 |
85 | v512i8 = 35, // 512 x i8 |
86 | v1024i8 = 36, // 1024 x i8 |
87 | |
88 | v1i16 = 37, // 1 x i16 |
89 | v2i16 = 38, // 2 x i16 |
90 | v3i16 = 39, // 3 x i16 |
91 | v4i16 = 40, // 4 x i16 |
92 | v8i16 = 41, // 8 x i16 |
93 | v16i16 = 42, // 16 x i16 |
94 | v32i16 = 43, // 32 x i16 |
95 | v64i16 = 44, // 64 x i16 |
96 | v128i16 = 45, // 128 x i16 |
97 | v256i16 = 46, // 256 x i16 |
98 | v512i16 = 47, // 512 x i16 |
99 | |
100 | v1i32 = 48, // 1 x i32 |
101 | v2i32 = 49, // 2 x i32 |
102 | v3i32 = 50, // 3 x i32 |
103 | v4i32 = 51, // 4 x i32 |
104 | v5i32 = 52, // 5 x i32 |
105 | v6i32 = 53, // 6 x i32 |
106 | v7i32 = 54, // 7 x i32 |
107 | v8i32 = 55, // 8 x i32 |
108 | v16i32 = 56, // 16 x i32 |
109 | v32i32 = 57, // 32 x i32 |
110 | v64i32 = 58, // 64 x i32 |
111 | v128i32 = 59, // 128 x i32 |
112 | v256i32 = 60, // 256 x i32 |
113 | v512i32 = 61, // 512 x i32 |
114 | v1024i32 = 62, // 1024 x i32 |
115 | v2048i32 = 63, // 2048 x i32 |
116 | |
117 | v1i64 = 64, // 1 x i64 |
118 | v2i64 = 65, // 2 x i64 |
119 | v3i64 = 66, // 3 x i64 |
120 | v4i64 = 67, // 4 x i64 |
121 | v8i64 = 68, // 8 x i64 |
122 | v16i64 = 69, // 16 x i64 |
123 | v32i64 = 70, // 32 x i64 |
124 | v64i64 = 71, // 64 x i64 |
125 | v128i64 = 72, // 128 x i64 |
126 | v256i64 = 73, // 256 x i64 |
127 | |
128 | v1i128 = 74, // 1 x i128 |
129 | |
130 | FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1, |
131 | LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128, |
132 | |
133 | v1f16 = 75, // 1 x f16 |
134 | v2f16 = 76, // 2 x f16 |
135 | v3f16 = 77, // 3 x f16 |
136 | v4f16 = 78, // 4 x f16 |
137 | v8f16 = 79, // 8 x f16 |
138 | v16f16 = 80, // 16 x f16 |
139 | v32f16 = 81, // 32 x f16 |
140 | v64f16 = 82, // 64 x f16 |
141 | v128f16 = 83, // 128 x f16 |
142 | v256f16 = 84, // 256 x f16 |
143 | v512f16 = 85, // 256 x f16 |
144 | |
145 | v2bf16 = 86, // 2 x bf16 |
146 | v3bf16 = 87, // 3 x bf16 |
147 | v4bf16 = 88, // 4 x bf16 |
148 | v8bf16 = 89, // 8 x bf16 |
149 | v16bf16 = 90, // 16 x bf16 |
150 | v32bf16 = 91, // 32 x bf16 |
151 | v64bf16 = 92, // 64 x bf16 |
152 | v128bf16 = 93, // 128 x bf16 |
153 | |
154 | v1f32 = 94, // 1 x f32 |
155 | v2f32 = 95, // 2 x f32 |
156 | v3f32 = 96, // 3 x f32 |
157 | v4f32 = 97, // 4 x f32 |
158 | v5f32 = 98, // 5 x f32 |
159 | v6f32 = 99, // 6 x f32 |
160 | v7f32 = 100, // 7 x f32 |
161 | v8f32 = 101, // 8 x f32 |
162 | v16f32 = 102, // 16 x f32 |
163 | v32f32 = 103, // 32 x f32 |
164 | v64f32 = 104, // 64 x f32 |
165 | v128f32 = 105, // 128 x f32 |
166 | v256f32 = 106, // 256 x f32 |
167 | v512f32 = 107, // 512 x f32 |
168 | v1024f32 = 108, // 1024 x f32 |
169 | v2048f32 = 109, // 2048 x f32 |
170 | |
171 | v1f64 = 110, // 1 x f64 |
172 | v2f64 = 111, // 2 x f64 |
173 | v3f64 = 112, // 3 x f64 |
174 | v4f64 = 113, // 4 x f64 |
175 | v8f64 = 114, // 8 x f64 |
176 | v16f64 = 115, // 16 x f64 |
177 | v32f64 = 116, // 32 x f64 |
178 | v64f64 = 117, // 64 x f64 |
179 | v128f64 = 118, // 128 x f64 |
180 | v256f64 = 119, // 256 x f64 |
181 | |
182 | FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16, |
183 | LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64, |
184 | |
185 | FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1, |
186 | LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64, |
187 | |
188 | nxv1i1 = 120, // n x 1 x i1 |
189 | nxv2i1 = 121, // n x 2 x i1 |
190 | nxv4i1 = 122, // n x 4 x i1 |
191 | nxv8i1 = 123, // n x 8 x i1 |
192 | nxv16i1 = 124, // n x 16 x i1 |
193 | nxv32i1 = 125, // n x 32 x i1 |
194 | nxv64i1 = 126, // n x 64 x i1 |
195 | |
196 | nxv1i8 = 127, // n x 1 x i8 |
197 | nxv2i8 = 128, // n x 2 x i8 |
198 | nxv4i8 = 129, // n x 4 x i8 |
199 | nxv8i8 = 130, // n x 8 x i8 |
200 | nxv16i8 = 131, // n x 16 x i8 |
201 | nxv32i8 = 132, // n x 32 x i8 |
202 | nxv64i8 = 133, // n x 64 x i8 |
203 | |
204 | nxv1i16 = 134, // n x 1 x i16 |
205 | nxv2i16 = 135, // n x 2 x i16 |
206 | nxv4i16 = 136, // n x 4 x i16 |
207 | nxv8i16 = 137, // n x 8 x i16 |
208 | nxv16i16 = 138, // n x 16 x i16 |
209 | nxv32i16 = 139, // n x 32 x i16 |
210 | |
211 | nxv1i32 = 140, // n x 1 x i32 |
212 | nxv2i32 = 141, // n x 2 x i32 |
213 | nxv4i32 = 142, // n x 4 x i32 |
214 | nxv8i32 = 143, // n x 8 x i32 |
215 | nxv16i32 = 144, // n x 16 x i32 |
216 | nxv32i32 = 145, // n x 32 x i32 |
217 | |
218 | nxv1i64 = 146, // n x 1 x i64 |
219 | nxv2i64 = 147, // n x 2 x i64 |
220 | nxv4i64 = 148, // n x 4 x i64 |
221 | nxv8i64 = 149, // n x 8 x i64 |
222 | nxv16i64 = 150, // n x 16 x i64 |
223 | nxv32i64 = 151, // n x 32 x i64 |
224 | |
225 | FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1, |
226 | LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64, |
227 | |
228 | nxv1f16 = 152, // n x 1 x f16 |
229 | nxv2f16 = 153, // n x 2 x f16 |
230 | nxv4f16 = 154, // n x 4 x f16 |
231 | nxv8f16 = 155, // n x 8 x f16 |
232 | nxv16f16 = 156, // n x 16 x f16 |
233 | nxv32f16 = 157, // n x 32 x f16 |
234 | |
235 | nxv1bf16 = 158, // n x 1 x bf16 |
236 | nxv2bf16 = 159, // n x 2 x bf16 |
237 | nxv4bf16 = 160, // n x 4 x bf16 |
238 | nxv8bf16 = 161, // n x 8 x bf16 |
239 | |
240 | nxv1f32 = 162, // n x 1 x f32 |
241 | nxv2f32 = 163, // n x 2 x f32 |
242 | nxv4f32 = 164, // n x 4 x f32 |
243 | nxv8f32 = 165, // n x 8 x f32 |
244 | nxv16f32 = 166, // n x 16 x f32 |
245 | |
246 | nxv1f64 = 167, // n x 1 x f64 |
247 | nxv2f64 = 168, // n x 2 x f64 |
248 | nxv4f64 = 169, // n x 4 x f64 |
249 | nxv8f64 = 170, // n x 8 x f64 |
250 | |
251 | FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16, |
252 | LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64, |
253 | |
254 | FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1, |
255 | LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64, |
256 | |
257 | FIRST_VECTOR_VALUETYPE = v1i1, |
258 | LAST_VECTOR_VALUETYPE = nxv8f64, |
259 | |
260 | x86mmx = 171, // This is an X86 MMX value |
261 | |
262 | Glue = 172, // This glues nodes together during pre-RA sched |
263 | |
264 | isVoid = 173, // This has no value |
265 | |
266 | Untyped = 174, // This value takes a register, but has |
267 | // unspecified type. The register class |
268 | // will be determined by the opcode. |
269 | |
270 | funcref = 175, // WebAssembly's funcref type |
271 | externref = 176, // WebAssembly's externref type |
272 | x86amx = 177, // This is an X86 AMX value |
273 | i64x8 = 178, // 8 Consecutive GPRs (AArch64) |
274 | |
275 | FIRST_VALUETYPE = 1, // This is always the beginning of the list. |
276 | LAST_VALUETYPE = i64x8, // This always remains at the end of the list. |
277 | VALUETYPE_SIZE = LAST_VALUETYPE + 1, |
278 | |
279 | // This is the current maximum for LAST_VALUETYPE. |
280 | // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors |
281 | // This value must be a multiple of 32. |
282 | MAX_ALLOWED_VALUETYPE = 192, |
283 | |
284 | // A value of type llvm::TokenTy |
285 | token = 248, |
286 | |
287 | // This is MDNode or MDString. |
288 | Metadata = 249, |
289 | |
290 | // An int value the size of the pointer of the current |
291 | // target to any address space. This must only be used internal to |
292 | // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR. |
293 | iPTRAny = 250, |
294 | |
295 | // A vector with any length and element size. This is used |
296 | // for intrinsics that have overloadings based on vector types. |
297 | // This is only for tblgen's consumption! |
298 | vAny = 251, |
299 | |
300 | // Any floating-point or vector floating-point value. This is used |
301 | // for intrinsics that have overloadings based on floating-point types. |
302 | // This is only for tblgen's consumption! |
303 | fAny = 252, |
304 | |
305 | // An integer or vector integer value of any bit width. This is |
306 | // used for intrinsics that have overloadings based on integer bit widths. |
307 | // This is only for tblgen's consumption! |
308 | iAny = 253, |
309 | |
310 | // An int value the size of the pointer of the current |
311 | // target. This should only be used internal to tblgen! |
312 | iPTR = 254, |
313 | |
314 | // Any type. This is used for intrinsics that have overloadings. |
315 | // This is only for tblgen's consumption! |
316 | Any = 255 |
317 | |
318 | // clang-format on |
319 | }; |
320 | |
321 | SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE; |
322 | |
323 | constexpr MVT() = default; |
324 | constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} |
325 | |
326 | bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; } |
327 | bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; } |
328 | bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; } |
329 | bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; } |
330 | bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; } |
331 | bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; } |
332 | |
333 | /// Return true if this is a valid simple valuetype. |
334 | bool isValid() const { |
335 | return (SimpleTy >= MVT::FIRST_VALUETYPE && |
336 | SimpleTy <= MVT::LAST_VALUETYPE); |
337 | } |
338 | |
339 | /// Return true if this is a FP or a vector FP type. |
340 | bool isFloatingPoint() const { |
341 | return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && |
342 | SimpleTy <= MVT::LAST_FP_VALUETYPE) || |
343 | (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE && |
344 | SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) || |
345 | (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE && |
346 | SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE)); |
347 | } |
348 | |
349 | /// Return true if this is an integer or a vector integer type. |
350 | bool isInteger() const { |
351 | return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && |
352 | SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || |
353 | (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE && |
354 | SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) || |
355 | (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE && |
356 | SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE)); |
357 | } |
358 | |
359 | /// Return true if this is an integer, not including vectors. |
360 | bool isScalarInteger() const { |
361 | return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && |
362 | SimpleTy <= MVT::LAST_INTEGER_VALUETYPE); |
363 | } |
364 | |
365 | /// Return true if this is a vector value type. |
366 | bool isVector() const { |
367 | return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE && |
368 | SimpleTy <= MVT::LAST_VECTOR_VALUETYPE); |
369 | } |
370 | |
371 | /// Return true if this is a vector value type where the |
372 | /// runtime length is machine dependent |
373 | bool isScalableVector() const { |
374 | return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE && |
375 | SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE); |
376 | } |
377 | |
378 | bool isFixedLengthVector() const { |
379 | return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE && |
380 | SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE); |
381 | } |
382 | |
383 | /// Return true if this is a 16-bit vector type. |
384 | bool is16BitVector() const { |
385 | return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || |
386 | SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16); |
387 | } |
388 | |
389 | /// Return true if this is a 32-bit vector type. |
390 | bool is32BitVector() const { |
391 | return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || |
392 | SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || |
393 | SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 || |
394 | SimpleTy == MVT::v1f32); |
395 | } |
396 | |
397 | /// Return true if this is a 64-bit vector type. |
398 | bool is64BitVector() const { |
399 | return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || |
400 | SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || |
401 | SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || |
402 | SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 || |
403 | SimpleTy == MVT::v1f64); |
404 | } |
405 | |
406 | /// Return true if this is a 128-bit vector type. |
407 | bool is128BitVector() const { |
408 | return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || |
409 | SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 || |
410 | SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 || |
411 | SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 || |
412 | SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); |
413 | } |
414 | |
415 | /// Return true if this is a 256-bit vector type. |
416 | bool is256BitVector() const { |
417 | return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 || |
418 | SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || |
419 | SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || |
420 | SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 || |
421 | SimpleTy == MVT::v256i1); |
422 | } |
423 | |
424 | /// Return true if this is a 512-bit vector type. |
425 | bool is512BitVector() const { |
426 | return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 || |
427 | SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 || |
428 | SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || |
429 | SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || |
430 | SimpleTy == MVT::v8i64); |
431 | } |
432 | |
433 | /// Return true if this is a 1024-bit vector type. |
434 | bool is1024BitVector() const { |
435 | return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || |
436 | SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || |
437 | SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 || |
438 | SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 || |
439 | SimpleTy == MVT::v64bf16); |
440 | } |
441 | |
442 | /// Return true if this is a 2048-bit vector type. |
443 | bool is2048BitVector() const { |
444 | return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || |
445 | SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 || |
446 | SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 || |
447 | SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16); |
448 | } |
449 | |
450 | /// Return true if this is an overloaded type for TableGen. |
451 | bool isOverloaded() const { |
452 | return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || |
453 | SimpleTy == MVT::fAny || SimpleTy == MVT::vAny || |
454 | SimpleTy == MVT::iPTRAny); |
455 | } |
456 | |
457 | /// Return a vector with the same number of elements as this vector, but |
458 | /// with the element type converted to an integer type with the same |
459 | /// bitwidth. |
460 | MVT changeVectorElementTypeToInteger() const { |
461 | MVT EltTy = getVectorElementType(); |
462 | MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits()); |
463 | MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount()); |
464 | assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && "Simple vector VT not representable by simple integer vector VT!" ) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\"" , "llvm/include/llvm/Support/MachineValueType.h", 465, __extension__ __PRETTY_FUNCTION__)) |
465 | "Simple vector VT not representable by simple integer vector VT!")(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && "Simple vector VT not representable by simple integer vector VT!" ) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\"" , "llvm/include/llvm/Support/MachineValueType.h", 465, __extension__ __PRETTY_FUNCTION__)); |
466 | return VecTy; |
467 | } |
468 | |
469 | /// Return a VT for a vector type whose attributes match ourselves |
470 | /// with the exception of the element type that is chosen by the caller. |
471 | MVT changeVectorElementType(MVT EltVT) const { |
472 | MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount()); |
473 | assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && "Simple vector VT not representable by simple integer vector VT!" ) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\"" , "llvm/include/llvm/Support/MachineValueType.h", 474, __extension__ __PRETTY_FUNCTION__)) |
474 | "Simple vector VT not representable by simple integer vector VT!")(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && "Simple vector VT not representable by simple integer vector VT!" ) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\"" , "llvm/include/llvm/Support/MachineValueType.h", 474, __extension__ __PRETTY_FUNCTION__)); |
475 | return VecTy; |
476 | } |
477 | |
478 | /// Return the type converted to an equivalently sized integer or vector |
479 | /// with integer element type. Similar to changeVectorElementTypeToInteger, |
480 | /// but also handles scalars. |
481 | MVT changeTypeToInteger() { |
482 | if (isVector()) |
483 | return changeVectorElementTypeToInteger(); |
484 | return MVT::getIntegerVT(getSizeInBits()); |
485 | } |
486 | |
487 | /// Return a VT for a vector type with the same element type but |
488 | /// half the number of elements. |
489 | MVT getHalfNumVectorElementsVT() const { |
490 | MVT EltVT = getVectorElementType(); |
491 | auto EltCnt = getVectorElementCount(); |
492 | assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")(static_cast <bool> (EltCnt.isKnownEven() && "Splitting vector, but not in half!" ) ? void (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\"" , "llvm/include/llvm/Support/MachineValueType.h", 492, __extension__ __PRETTY_FUNCTION__)); |
493 | return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2)); |
494 | } |
495 | |
496 | /// Returns true if the given vector is a power of 2. |
497 | bool isPow2VectorType() const { |
498 | unsigned NElts = getVectorMinNumElements(); |
499 | return !(NElts & (NElts - 1)); |
500 | } |
501 | |
502 | /// Widens the length of the given vector MVT up to the nearest power of 2 |
503 | /// and returns that type. |
504 | MVT getPow2VectorType() const { |
505 | if (isPow2VectorType()) |
506 | return *this; |
507 | |
508 | ElementCount NElts = getVectorElementCount(); |
509 | unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue()); |
510 | NElts = ElementCount::get(NewMinCount, NElts.isScalable()); |
511 | return MVT::getVectorVT(getVectorElementType(), NElts); |
512 | } |
513 | |
514 | /// If this is a vector, return the element type, otherwise return this. |
515 | MVT getScalarType() const { |
516 | return isVector() ? getVectorElementType() : *this; |
517 | } |
518 | |
519 | MVT getVectorElementType() const { |
520 | switch (SimpleTy) { |
521 | default: |
522 | llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "llvm/include/llvm/Support/MachineValueType.h" , 522); |
523 | case v1i1: |
524 | case v2i1: |
525 | case v4i1: |
526 | case v8i1: |
527 | case v16i1: |
528 | case v32i1: |
529 | case v64i1: |
530 | case v128i1: |
531 | case v256i1: |
532 | case v512i1: |
533 | case v1024i1: |
534 | case nxv1i1: |
535 | case nxv2i1: |
536 | case nxv4i1: |
537 | case nxv8i1: |
538 | case nxv16i1: |
539 | case nxv32i1: |
540 | case nxv64i1: return i1; |
541 | case v1i8: |
542 | case v2i8: |
543 | case v4i8: |
544 | case v8i8: |
545 | case v16i8: |
546 | case v32i8: |
547 | case v64i8: |
548 | case v128i8: |
549 | case v256i8: |
550 | case v512i8: |
551 | case v1024i8: |
552 | case nxv1i8: |
553 | case nxv2i8: |
554 | case nxv4i8: |
555 | case nxv8i8: |
556 | case nxv16i8: |
557 | case nxv32i8: |
558 | case nxv64i8: return i8; |
559 | case v1i16: |
560 | case v2i16: |
561 | case v3i16: |
562 | case v4i16: |
563 | case v8i16: |
564 | case v16i16: |
565 | case v32i16: |
566 | case v64i16: |
567 | case v128i16: |
568 | case v256i16: |
569 | case v512i16: |
570 | case nxv1i16: |
571 | case nxv2i16: |
572 | case nxv4i16: |
573 | case nxv8i16: |
574 | case nxv16i16: |
575 | case nxv32i16: return i16; |
576 | case v1i32: |
577 | case v2i32: |
578 | case v3i32: |
579 | case v4i32: |
580 | case v5i32: |
581 | case v6i32: |
582 | case v7i32: |
583 | case v8i32: |
584 | case v16i32: |
585 | case v32i32: |
586 | case v64i32: |
587 | case v128i32: |
588 | case v256i32: |
589 | case v512i32: |
590 | case v1024i32: |
591 | case v2048i32: |
592 | case nxv1i32: |
593 | case nxv2i32: |
594 | case nxv4i32: |
595 | case nxv8i32: |
596 | case nxv16i32: |
597 | case nxv32i32: return i32; |
598 | case v1i64: |
599 | case v2i64: |
600 | case v3i64: |
601 | case v4i64: |
602 | case v8i64: |
603 | case v16i64: |
604 | case v32i64: |
605 | case v64i64: |
606 | case v128i64: |
607 | case v256i64: |
608 | case nxv1i64: |
609 | case nxv2i64: |
610 | case nxv4i64: |
611 | case nxv8i64: |
612 | case nxv16i64: |
613 | case nxv32i64: return i64; |
614 | case v1i128: return i128; |
615 | case v1f16: |
616 | case v2f16: |
617 | case v3f16: |
618 | case v4f16: |
619 | case v8f16: |
620 | case v16f16: |
621 | case v32f16: |
622 | case v64f16: |
623 | case v128f16: |
624 | case v256f16: |
625 | case v512f16: |
626 | case nxv1f16: |
627 | case nxv2f16: |
628 | case nxv4f16: |
629 | case nxv8f16: |
630 | case nxv16f16: |
631 | case nxv32f16: return f16; |
632 | case v2bf16: |
633 | case v3bf16: |
634 | case v4bf16: |
635 | case v8bf16: |
636 | case v16bf16: |
637 | case v32bf16: |
638 | case v64bf16: |
639 | case v128bf16: |
640 | case nxv1bf16: |
641 | case nxv2bf16: |
642 | case nxv4bf16: |
643 | case nxv8bf16: return bf16; |
644 | case v1f32: |
645 | case v2f32: |
646 | case v3f32: |
647 | case v4f32: |
648 | case v5f32: |
649 | case v6f32: |
650 | case v7f32: |
651 | case v8f32: |
652 | case v16f32: |
653 | case v32f32: |
654 | case v64f32: |
655 | case v128f32: |
656 | case v256f32: |
657 | case v512f32: |
658 | case v1024f32: |
659 | case v2048f32: |
660 | case nxv1f32: |
661 | case nxv2f32: |
662 | case nxv4f32: |
663 | case nxv8f32: |
664 | case nxv16f32: return f32; |
665 | case v1f64: |
666 | case v2f64: |
667 | case v3f64: |
668 | case v4f64: |
669 | case v8f64: |
670 | case v16f64: |
671 | case v32f64: |
672 | case v64f64: |
673 | case v128f64: |
674 | case v256f64: |
675 | case nxv1f64: |
676 | case nxv2f64: |
677 | case nxv4f64: |
678 | case nxv8f64: return f64; |
679 | } |
680 | } |
681 | |
682 | /// Given a vector type, return the minimum number of elements it contains. |
683 | unsigned getVectorMinNumElements() const { |
684 | switch (SimpleTy) { |
685 | default: |
686 | llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "llvm/include/llvm/Support/MachineValueType.h" , 686); |
687 | case v2048i32: |
688 | case v2048f32: return 2048; |
689 | case v1024i1: |
690 | case v1024i8: |
691 | case v1024i32: |
692 | case v1024f32: return 1024; |
693 | case v512i1: |
694 | case v512i8: |
695 | case v512i16: |
696 | case v512i32: |
697 | case v512f16: |
698 | case v512f32: return 512; |
699 | case v256i1: |
700 | case v256i8: |
701 | case v256i16: |
702 | case v256f16: |
703 | case v256i32: |
704 | case v256i64: |
705 | case v256f32: |
706 | case v256f64: return 256; |
707 | case v128i1: |
708 | case v128i8: |
709 | case v128i16: |
710 | case v128i32: |
711 | case v128i64: |
712 | case v128f16: |
713 | case v128bf16: |
714 | case v128f32: |
715 | case v128f64: return 128; |
716 | case v64i1: |
717 | case v64i8: |
718 | case v64i16: |
719 | case v64i32: |
720 | case v64i64: |
721 | case v64f16: |
722 | case v64bf16: |
723 | case v64f32: |
724 | case v64f64: |
725 | case nxv64i1: |
726 | case nxv64i8: return 64; |
727 | case v32i1: |
728 | case v32i8: |
729 | case v32i16: |
730 | case v32i32: |
731 | case v32i64: |
732 | case v32f16: |
733 | case v32bf16: |
734 | case v32f32: |
735 | case v32f64: |
736 | case nxv32i1: |
737 | case nxv32i8: |
738 | case nxv32i16: |
739 | case nxv32i32: |
740 | case nxv32i64: |
741 | case nxv32f16: return 32; |
742 | case v16i1: |
743 | case v16i8: |
744 | case v16i16: |
745 | case v16i32: |
746 | case v16i64: |
747 | case v16f16: |
748 | case v16bf16: |
749 | case v16f32: |
750 | case v16f64: |
751 | case nxv16i1: |
752 | case nxv16i8: |
753 | case nxv16i16: |
754 | case nxv16i32: |
755 | case nxv16i64: |
756 | case nxv16f16: |
757 | case nxv16f32: return 16; |
758 | case v8i1: |
759 | case v8i8: |
760 | case v8i16: |
761 | case v8i32: |
762 | case v8i64: |
763 | case v8f16: |
764 | case v8bf16: |
765 | case v8f32: |
766 | case v8f64: |
767 | case nxv8i1: |
768 | case nxv8i8: |
769 | case nxv8i16: |
770 | case nxv8i32: |
771 | case nxv8i64: |
772 | case nxv8f16: |
773 | case nxv8bf16: |
774 | case nxv8f32: |
775 | case nxv8f64: return 8; |
776 | case v7i32: |
777 | case v7f32: return 7; |
778 | case v6i32: |
779 | case v6f32: return 6; |
780 | case v5i32: |
781 | case v5f32: return 5; |
782 | case v4i1: |
783 | case v4i8: |
784 | case v4i16: |
785 | case v4i32: |
786 | case v4i64: |
787 | case v4f16: |
788 | case v4bf16: |
789 | case v4f32: |
790 | case v4f64: |
791 | case nxv4i1: |
792 | case nxv4i8: |
793 | case nxv4i16: |
794 | case nxv4i32: |
795 | case nxv4i64: |
796 | case nxv4f16: |
797 | case nxv4bf16: |
798 | case nxv4f32: |
799 | case nxv4f64: return 4; |
800 | case v3i16: |
801 | case v3i32: |
802 | case v3i64: |
803 | case v3f16: |
804 | case v3bf16: |
805 | case v3f32: |
806 | case v3f64: return 3; |
807 | case v2i1: |
808 | case v2i8: |
809 | case v2i16: |
810 | case v2i32: |
811 | case v2i64: |
812 | case v2f16: |
813 | case v2bf16: |
814 | case v2f32: |
815 | case v2f64: |
816 | case nxv2i1: |
817 | case nxv2i8: |
818 | case nxv2i16: |
819 | case nxv2i32: |
820 | case nxv2i64: |
821 | case nxv2f16: |
822 | case nxv2bf16: |
823 | case nxv2f32: |
824 | case nxv2f64: return 2; |
825 | case v1i1: |
826 | case v1i8: |
827 | case v1i16: |
828 | case v1i32: |
829 | case v1i64: |
830 | case v1i128: |
831 | case v1f16: |
832 | case v1f32: |
833 | case v1f64: |
834 | case nxv1i1: |
835 | case nxv1i8: |
836 | case nxv1i16: |
837 | case nxv1i32: |
838 | case nxv1i64: |
839 | case nxv1f16: |
840 | case nxv1bf16: |
841 | case nxv1f32: |
842 | case nxv1f64: return 1; |
843 | } |
844 | } |
845 | |
846 | ElementCount getVectorElementCount() const { |
847 | return ElementCount::get(getVectorMinNumElements(), isScalableVector()); |
848 | } |
849 | |
850 | unsigned getVectorNumElements() const { |
851 | if (isScalableVector()) |
852 | llvm::reportInvalidSizeRequest( |
853 | "Possible incorrect use of MVT::getVectorNumElements() for " |
854 | "scalable vector. Scalable flag may be dropped, use " |
855 | "MVT::getVectorElementCount() instead"); |
856 | return getVectorMinNumElements(); |
857 | } |
858 | |
859 | /// Returns the size of the specified MVT in bits. |
860 | /// |
861 | /// If the value type is a scalable vector type, the scalable property will |
862 | /// be set and the runtime size will be a positive integer multiple of the |
863 | /// base size. |
864 | TypeSize getSizeInBits() const { |
865 | switch (SimpleTy) { |
866 | default: |
867 | llvm_unreachable("getSizeInBits called on extended MVT.")::llvm::llvm_unreachable_internal("getSizeInBits called on extended MVT." , "llvm/include/llvm/Support/MachineValueType.h", 867); |
868 | case Other: |
869 | llvm_unreachable("Value type is non-standard value, Other.")::llvm::llvm_unreachable_internal("Value type is non-standard value, Other." , "llvm/include/llvm/Support/MachineValueType.h", 869); |
870 | case iPTR: |
871 | llvm_unreachable("Value type size is target-dependent. Ask TLI.")::llvm::llvm_unreachable_internal("Value type size is target-dependent. Ask TLI." , "llvm/include/llvm/Support/MachineValueType.h", 871); |
872 | case iPTRAny: |
873 | case iAny: |
874 | case fAny: |
875 | case vAny: |
876 | case Any: |
877 | llvm_unreachable("Value type is overloaded.")::llvm::llvm_unreachable_internal("Value type is overloaded." , "llvm/include/llvm/Support/MachineValueType.h", 877); |
878 | case token: |
879 | llvm_unreachable("Token type is a sentinel that cannot be used "::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used " "in codegen and has no size", "llvm/include/llvm/Support/MachineValueType.h" , 880) |
880 | "in codegen and has no size")::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used " "in codegen and has no size", "llvm/include/llvm/Support/MachineValueType.h" , 880); |
881 | case Metadata: |
882 | llvm_unreachable("Value type is metadata.")::llvm::llvm_unreachable_internal("Value type is metadata.", "llvm/include/llvm/Support/MachineValueType.h" , 882); |
883 | case i1: |
884 | case v1i1: return TypeSize::Fixed(1); |
885 | case nxv1i1: return TypeSize::Scalable(1); |
886 | case v2i1: return TypeSize::Fixed(2); |
887 | case nxv2i1: return TypeSize::Scalable(2); |
888 | case v4i1: return TypeSize::Fixed(4); |
889 | case nxv4i1: return TypeSize::Scalable(4); |
890 | case i8 : |
891 | case v1i8: |
892 | case v8i1: return TypeSize::Fixed(8); |
893 | case nxv1i8: |
894 | case nxv8i1: return TypeSize::Scalable(8); |
895 | case i16 : |
896 | case f16: |
897 | case bf16: |
898 | case v16i1: |
899 | case v2i8: |
900 | case v1i16: |
901 | case v1f16: return TypeSize::Fixed(16); |
902 | case nxv16i1: |
903 | case nxv2i8: |
904 | case nxv1i16: |
905 | case nxv1bf16: |
906 | case nxv1f16: return TypeSize::Scalable(16); |
907 | case f32 : |
908 | case i32 : |
909 | case v32i1: |
910 | case v4i8: |
911 | case v2i16: |
912 | case v2f16: |
913 | case v2bf16: |
914 | case v1f32: |
915 | case v1i32: return TypeSize::Fixed(32); |
916 | case nxv32i1: |
917 | case nxv4i8: |
918 | case nxv2i16: |
919 | case nxv1i32: |
920 | case nxv2f16: |
921 | case nxv2bf16: |
922 | case nxv1f32: return TypeSize::Scalable(32); |
923 | case v3i16: |
924 | case v3f16: |
925 | case v3bf16: return TypeSize::Fixed(48); |
926 | case x86mmx: |
927 | case f64 : |
928 | case i64 : |
929 | case v64i1: |
930 | case v8i8: |
931 | case v4i16: |
932 | case v2i32: |
933 | case v1i64: |
934 | case v4f16: |
935 | case v4bf16: |
936 | case v2f32: |
937 | case v1f64: return TypeSize::Fixed(64); |
938 | case nxv64i1: |
939 | case nxv8i8: |
940 | case nxv4i16: |
941 | case nxv2i32: |
942 | case nxv1i64: |
943 | case nxv4f16: |
944 | case nxv4bf16: |
945 | case nxv2f32: |
946 | case nxv1f64: return TypeSize::Scalable(64); |
947 | case f80 : return TypeSize::Fixed(80); |
948 | case v3i32: |
949 | case v3f32: return TypeSize::Fixed(96); |
950 | case f128: |
951 | case ppcf128: |
952 | case i128: |
953 | case v128i1: |
954 | case v16i8: |
955 | case v8i16: |
956 | case v4i32: |
957 | case v2i64: |
958 | case v1i128: |
959 | case v8f16: |
960 | case v8bf16: |
961 | case v4f32: |
962 | case v2f64: return TypeSize::Fixed(128); |
963 | case nxv16i8: |
964 | case nxv8i16: |
965 | case nxv4i32: |
966 | case nxv2i64: |
967 | case nxv8f16: |
968 | case nxv8bf16: |
969 | case nxv4f32: |
970 | case nxv2f64: return TypeSize::Scalable(128); |
971 | case v5i32: |
972 | case v5f32: return TypeSize::Fixed(160); |
973 | case v6i32: |
974 | case v3i64: |
975 | case v6f32: |
976 | case v3f64: return TypeSize::Fixed(192); |
977 | case v7i32: |
978 | case v7f32: return TypeSize::Fixed(224); |
979 | case v256i1: |
980 | case v32i8: |
981 | case v16i16: |
982 | case v8i32: |
983 | case v4i64: |
984 | case v16f16: |
985 | case v16bf16: |
986 | case v8f32: |
987 | case v4f64: return TypeSize::Fixed(256); |
988 | case nxv32i8: |
989 | case nxv16i16: |
990 | case nxv8i32: |
991 | case nxv4i64: |
992 | case nxv16f16: |
993 | case nxv8f32: |
994 | case nxv4f64: return TypeSize::Scalable(256); |
995 | case i64x8: |
996 | case v512i1: |
997 | case v64i8: |
998 | case v32i16: |
999 | case v16i32: |
1000 | case v8i64: |
1001 | case v32f16: |
1002 | case v32bf16: |
1003 | case v16f32: |
1004 | case v8f64: return TypeSize::Fixed(512); |
1005 | case nxv64i8: |
1006 | case nxv32i16: |
1007 | case nxv16i32: |
1008 | case nxv8i64: |
1009 | case nxv32f16: |
1010 | case nxv16f32: |
1011 | case nxv8f64: return TypeSize::Scalable(512); |
1012 | case v1024i1: |
1013 | case v128i8: |
1014 | case v64i16: |
1015 | case v32i32: |
1016 | case v16i64: |
1017 | case v64f16: |
1018 | case v64bf16: |
1019 | case v32f32: |
1020 | case v16f64: return TypeSize::Fixed(1024); |
1021 | case nxv32i32: |
1022 | case nxv16i64: return TypeSize::Scalable(1024); |
1023 | case v256i8: |
1024 | case v128i16: |
1025 | case v64i32: |
1026 | case v32i64: |
1027 | case v128f16: |
1028 | case v128bf16: |
1029 | case v64f32: |
1030 | case v32f64: return TypeSize::Fixed(2048); |
1031 | case nxv32i64: return TypeSize::Scalable(2048); |
1032 | case v512i8: |
1033 | case v256i16: |
1034 | case v128i32: |
1035 | case v64i64: |
1036 | case v256f16: |
1037 | case v128f32: |
1038 | case v64f64: return TypeSize::Fixed(4096); |
1039 | case v1024i8: |
1040 | case v512i16: |
1041 | case v256i32: |
1042 | case v128i64: |
1043 | case v512f16: |
1044 | case v256f32: |
1045 | case x86amx: |
1046 | case v128f64: return TypeSize::Fixed(8192); |
1047 | case v512i32: |
1048 | case v256i64: |
1049 | case v512f32: |
1050 | case v256f64: return TypeSize::Fixed(16384); |
1051 | case v1024i32: |
1052 | case v1024f32: return TypeSize::Fixed(32768); |
1053 | case v2048i32: |
1054 | case v2048f32: return TypeSize::Fixed(65536); |
1055 | case funcref: |
1056 | case externref: return TypeSize::Fixed(0); // opaque type |
1057 | } |
1058 | } |
1059 | |
1060 | /// Return the size of the specified fixed width value type in bits. The |
1061 | /// function will assert if the type is scalable. |
1062 | uint64_t getFixedSizeInBits() const { |
1063 | return getSizeInBits().getFixedSize(); |
1064 | } |
1065 | |
1066 | uint64_t getScalarSizeInBits() const { |
1067 | return getScalarType().getSizeInBits().getFixedSize(); |
1068 | } |
1069 | |
1070 | /// Return the number of bytes overwritten by a store of the specified value |
1071 | /// type. |
1072 | /// |
1073 | /// If the value type is a scalable vector type, the scalable property will |
1074 | /// be set and the runtime size will be a positive integer multiple of the |
1075 | /// base size. |
1076 | TypeSize getStoreSize() const { |
1077 | TypeSize BaseSize = getSizeInBits(); |
1078 | return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; |
1079 | } |
1080 | |
1081 | /// Return the number of bits overwritten by a store of the specified value |
1082 | /// type. |
1083 | /// |
1084 | /// If the value type is a scalable vector type, the scalable property will |
1085 | /// be set and the runtime size will be a positive integer multiple of the |
1086 | /// base size. |
1087 | TypeSize getStoreSizeInBits() const { |
1088 | return getStoreSize() * 8; |
1089 | } |
1090 | |
1091 | /// Returns true if the number of bits for the type is a multiple of an |
1092 | /// 8-bit byte. |
1093 | bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); } |
1094 | |
1095 | /// Return true if we know at compile time this has more bits than VT. |
1096 | bool knownBitsGT(MVT VT) const { |
1097 | return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits()); |
1098 | } |
1099 | |
1100 | /// Return true if we know at compile time this has more than or the same |
1101 | /// bits as VT. |
1102 | bool knownBitsGE(MVT VT) const { |
1103 | return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits()); |
1104 | } |
1105 | |
1106 | /// Return true if we know at compile time this has fewer bits than VT. |
1107 | bool knownBitsLT(MVT VT) const { |
1108 | return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits()); |
1109 | } |
1110 | |
1111 | /// Return true if we know at compile time this has fewer than or the same |
1112 | /// bits as VT. |
1113 | bool knownBitsLE(MVT VT) const { |
1114 | return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits()); |
1115 | } |
1116 | |
1117 | /// Return true if this has more bits than VT. |
1118 | bool bitsGT(MVT VT) const { |
1119 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1120, __extension__ __PRETTY_FUNCTION__)) |
1120 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1120, __extension__ __PRETTY_FUNCTION__)); |
1121 | return knownBitsGT(VT); |
1122 | } |
1123 | |
1124 | /// Return true if this has no less bits than VT. |
1125 | bool bitsGE(MVT VT) const { |
1126 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1127, __extension__ __PRETTY_FUNCTION__)) |
1127 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1127, __extension__ __PRETTY_FUNCTION__)); |
1128 | return knownBitsGE(VT); |
1129 | } |
1130 | |
1131 | /// Return true if this has less bits than VT. |
1132 | bool bitsLT(MVT VT) const { |
1133 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1134, __extension__ __PRETTY_FUNCTION__)) |
1134 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1134, __extension__ __PRETTY_FUNCTION__)); |
1135 | return knownBitsLT(VT); |
1136 | } |
1137 | |
1138 | /// Return true if this has no more bits than VT. |
1139 | bool bitsLE(MVT VT) const { |
1140 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1141, __extension__ __PRETTY_FUNCTION__)) |
1141 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "llvm/include/llvm/Support/MachineValueType.h", 1141, __extension__ __PRETTY_FUNCTION__)); |
1142 | return knownBitsLE(VT); |
1143 | } |
1144 | |
1145 | static MVT getFloatingPointVT(unsigned BitWidth) { |
1146 | switch (BitWidth) { |
1147 | default: |
1148 | llvm_unreachable("Bad bit width!")::llvm::llvm_unreachable_internal("Bad bit width!", "llvm/include/llvm/Support/MachineValueType.h" , 1148); |
1149 | case 16: |
1150 | return MVT::f16; |
1151 | case 32: |
1152 | return MVT::f32; |
1153 | case 64: |
1154 | return MVT::f64; |
1155 | case 80: |
1156 | return MVT::f80; |
1157 | case 128: |
1158 | return MVT::f128; |
1159 | } |
1160 | } |
1161 | |
1162 | static MVT getIntegerVT(unsigned BitWidth) { |
1163 | switch (BitWidth) { |
1164 | default: |
1165 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1166 | case 1: |
1167 | return MVT::i1; |
1168 | case 8: |
1169 | return MVT::i8; |
1170 | case 16: |
1171 | return MVT::i16; |
1172 | case 32: |
1173 | return MVT::i32; |
1174 | case 64: |
1175 | return MVT::i64; |
1176 | case 128: |
1177 | return MVT::i128; |
1178 | } |
1179 | } |
1180 | |
1181 | static MVT getVectorVT(MVT VT, unsigned NumElements) { |
1182 | switch (VT.SimpleTy) { |
1183 | default: |
1184 | break; |
1185 | case MVT::i1: |
1186 | if (NumElements == 1) return MVT::v1i1; |
1187 | if (NumElements == 2) return MVT::v2i1; |
1188 | if (NumElements == 4) return MVT::v4i1; |
1189 | if (NumElements == 8) return MVT::v8i1; |
1190 | if (NumElements == 16) return MVT::v16i1; |
1191 | if (NumElements == 32) return MVT::v32i1; |
1192 | if (NumElements == 64) return MVT::v64i1; |
1193 | if (NumElements == 128) return MVT::v128i1; |
1194 | if (NumElements == 256) return MVT::v256i1; |
1195 | if (NumElements == 512) return MVT::v512i1; |
1196 | if (NumElements == 1024) return MVT::v1024i1; |
1197 | break; |
1198 | case MVT::i8: |
1199 | if (NumElements == 1) return MVT::v1i8; |
1200 | if (NumElements == 2) return MVT::v2i8; |
1201 | if (NumElements == 4) return MVT::v4i8; |
1202 | if (NumElements == 8) return MVT::v8i8; |
1203 | if (NumElements == 16) return MVT::v16i8; |
1204 | if (NumElements == 32) return MVT::v32i8; |
1205 | if (NumElements == 64) return MVT::v64i8; |
1206 | if (NumElements == 128) return MVT::v128i8; |
1207 | if (NumElements == 256) return MVT::v256i8; |
1208 | if (NumElements == 512) return MVT::v512i8; |
1209 | if (NumElements == 1024) return MVT::v1024i8; |
1210 | break; |
1211 | case MVT::i16: |
1212 | if (NumElements == 1) return MVT::v1i16; |
1213 | if (NumElements == 2) return MVT::v2i16; |
1214 | if (NumElements == 3) return MVT::v3i16; |
1215 | if (NumElements == 4) return MVT::v4i16; |
1216 | if (NumElements == 8) return MVT::v8i16; |
1217 | if (NumElements == 16) return MVT::v16i16; |
1218 | if (NumElements == 32) return MVT::v32i16; |
1219 | if (NumElements == 64) return MVT::v64i16; |
1220 | if (NumElements == 128) return MVT::v128i16; |
1221 | if (NumElements == 256) return MVT::v256i16; |
1222 | if (NumElements == 512) return MVT::v512i16; |
1223 | break; |
1224 | case MVT::i32: |
1225 | if (NumElements == 1) return MVT::v1i32; |
1226 | if (NumElements == 2) return MVT::v2i32; |
1227 | if (NumElements == 3) return MVT::v3i32; |
1228 | if (NumElements == 4) return MVT::v4i32; |
1229 | if (NumElements == 5) return MVT::v5i32; |
1230 | if (NumElements == 6) return MVT::v6i32; |
1231 | if (NumElements == 7) return MVT::v7i32; |
1232 | if (NumElements == 8) return MVT::v8i32; |
1233 | if (NumElements == 16) return MVT::v16i32; |
1234 | if (NumElements == 32) return MVT::v32i32; |
1235 | if (NumElements == 64) return MVT::v64i32; |
1236 | if (NumElements == 128) return MVT::v128i32; |
1237 | if (NumElements == 256) return MVT::v256i32; |
1238 | if (NumElements == 512) return MVT::v512i32; |
1239 | if (NumElements == 1024) return MVT::v1024i32; |
1240 | if (NumElements == 2048) return MVT::v2048i32; |
1241 | break; |
1242 | case MVT::i64: |
1243 | if (NumElements == 1) return MVT::v1i64; |
1244 | if (NumElements == 2) return MVT::v2i64; |
1245 | if (NumElements == 3) return MVT::v3i64; |
1246 | if (NumElements == 4) return MVT::v4i64; |
1247 | if (NumElements == 8) return MVT::v8i64; |
1248 | if (NumElements == 16) return MVT::v16i64; |
1249 | if (NumElements == 32) return MVT::v32i64; |
1250 | if (NumElements == 64) return MVT::v64i64; |
1251 | if (NumElements == 128) return MVT::v128i64; |
1252 | if (NumElements == 256) return MVT::v256i64; |
1253 | break; |
1254 | case MVT::i128: |
1255 | if (NumElements == 1) return MVT::v1i128; |
1256 | break; |
1257 | case MVT::f16: |
1258 | if (NumElements == 1) return MVT::v1f16; |
1259 | if (NumElements == 2) return MVT::v2f16; |
1260 | if (NumElements == 3) return MVT::v3f16; |
1261 | if (NumElements == 4) return MVT::v4f16; |
1262 | if (NumElements == 8) return MVT::v8f16; |
1263 | if (NumElements == 16) return MVT::v16f16; |
1264 | if (NumElements == 32) return MVT::v32f16; |
1265 | if (NumElements == 64) return MVT::v64f16; |
1266 | if (NumElements == 128) return MVT::v128f16; |
1267 | if (NumElements == 256) return MVT::v256f16; |
1268 | if (NumElements == 512) return MVT::v512f16; |
1269 | break; |
1270 | case MVT::bf16: |
1271 | if (NumElements == 2) return MVT::v2bf16; |
1272 | if (NumElements == 3) return MVT::v3bf16; |
1273 | if (NumElements == 4) return MVT::v4bf16; |
1274 | if (NumElements == 8) return MVT::v8bf16; |
1275 | if (NumElements == 16) return MVT::v16bf16; |
1276 | if (NumElements == 32) return MVT::v32bf16; |
1277 | if (NumElements == 64) return MVT::v64bf16; |
1278 | if (NumElements == 128) return MVT::v128bf16; |
1279 | break; |
1280 | case MVT::f32: |
1281 | if (NumElements == 1) return MVT::v1f32; |
1282 | if (NumElements == 2) return MVT::v2f32; |
1283 | if (NumElements == 3) return MVT::v3f32; |
1284 | if (NumElements == 4) return MVT::v4f32; |
1285 | if (NumElements == 5) return MVT::v5f32; |
1286 | if (NumElements == 6) return MVT::v6f32; |
1287 | if (NumElements == 7) return MVT::v7f32; |
1288 | if (NumElements == 8) return MVT::v8f32; |
1289 | if (NumElements == 16) return MVT::v16f32; |
1290 | if (NumElements == 32) return MVT::v32f32; |
1291 | if (NumElements == 64) return MVT::v64f32; |
1292 | if (NumElements == 128) return MVT::v128f32; |
1293 | if (NumElements == 256) return MVT::v256f32; |
1294 | if (NumElements == 512) return MVT::v512f32; |
1295 | if (NumElements == 1024) return MVT::v1024f32; |
1296 | if (NumElements == 2048) return MVT::v2048f32; |
1297 | break; |
1298 | case MVT::f64: |
1299 | if (NumElements == 1) return MVT::v1f64; |
1300 | if (NumElements == 2) return MVT::v2f64; |
1301 | if (NumElements == 3) return MVT::v3f64; |
1302 | if (NumElements == 4) return MVT::v4f64; |
1303 | if (NumElements == 8) return MVT::v8f64; |
1304 | if (NumElements == 16) return MVT::v16f64; |
1305 | if (NumElements == 32) return MVT::v32f64; |
1306 | if (NumElements == 64) return MVT::v64f64; |
1307 | if (NumElements == 128) return MVT::v128f64; |
1308 | if (NumElements == 256) return MVT::v256f64; |
1309 | break; |
1310 | } |
1311 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1312 | } |
1313 | |
1314 | static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { |
1315 | switch(VT.SimpleTy) { |
1316 | default: |
1317 | break; |
1318 | case MVT::i1: |
1319 | if (NumElements == 1) return MVT::nxv1i1; |
1320 | if (NumElements == 2) return MVT::nxv2i1; |
1321 | if (NumElements == 4) return MVT::nxv4i1; |
1322 | if (NumElements == 8) return MVT::nxv8i1; |
1323 | if (NumElements == 16) return MVT::nxv16i1; |
1324 | if (NumElements == 32) return MVT::nxv32i1; |
1325 | if (NumElements == 64) return MVT::nxv64i1; |
1326 | break; |
1327 | case MVT::i8: |
1328 | if (NumElements == 1) return MVT::nxv1i8; |
1329 | if (NumElements == 2) return MVT::nxv2i8; |
1330 | if (NumElements == 4) return MVT::nxv4i8; |
1331 | if (NumElements == 8) return MVT::nxv8i8; |
1332 | if (NumElements == 16) return MVT::nxv16i8; |
1333 | if (NumElements == 32) return MVT::nxv32i8; |
1334 | if (NumElements == 64) return MVT::nxv64i8; |
1335 | break; |
1336 | case MVT::i16: |
1337 | if (NumElements == 1) return MVT::nxv1i16; |
1338 | if (NumElements == 2) return MVT::nxv2i16; |
1339 | if (NumElements == 4) return MVT::nxv4i16; |
1340 | if (NumElements == 8) return MVT::nxv8i16; |
1341 | if (NumElements == 16) return MVT::nxv16i16; |
1342 | if (NumElements == 32) return MVT::nxv32i16; |
1343 | break; |
1344 | case MVT::i32: |
1345 | if (NumElements == 1) return MVT::nxv1i32; |
1346 | if (NumElements == 2) return MVT::nxv2i32; |
1347 | if (NumElements == 4) return MVT::nxv4i32; |
1348 | if (NumElements == 8) return MVT::nxv8i32; |
1349 | if (NumElements == 16) return MVT::nxv16i32; |
1350 | if (NumElements == 32) return MVT::nxv32i32; |
1351 | break; |
1352 | case MVT::i64: |
1353 | if (NumElements == 1) return MVT::nxv1i64; |
1354 | if (NumElements == 2) return MVT::nxv2i64; |
1355 | if (NumElements == 4) return MVT::nxv4i64; |
1356 | if (NumElements == 8) return MVT::nxv8i64; |
1357 | if (NumElements == 16) return MVT::nxv16i64; |
1358 | if (NumElements == 32) return MVT::nxv32i64; |
1359 | break; |
1360 | case MVT::f16: |
1361 | if (NumElements == 1) return MVT::nxv1f16; |
1362 | if (NumElements == 2) return MVT::nxv2f16; |
1363 | if (NumElements == 4) return MVT::nxv4f16; |
1364 | if (NumElements == 8) return MVT::nxv8f16; |
1365 | if (NumElements == 16) return MVT::nxv16f16; |
1366 | if (NumElements == 32) return MVT::nxv32f16; |
1367 | break; |
1368 | case MVT::bf16: |
1369 | if (NumElements == 1) return MVT::nxv1bf16; |
1370 | if (NumElements == 2) return MVT::nxv2bf16; |
1371 | if (NumElements == 4) return MVT::nxv4bf16; |
1372 | if (NumElements == 8) return MVT::nxv8bf16; |
1373 | break; |
1374 | case MVT::f32: |
1375 | if (NumElements == 1) return MVT::nxv1f32; |
1376 | if (NumElements == 2) return MVT::nxv2f32; |
1377 | if (NumElements == 4) return MVT::nxv4f32; |
1378 | if (NumElements == 8) return MVT::nxv8f32; |
1379 | if (NumElements == 16) return MVT::nxv16f32; |
1380 | break; |
1381 | case MVT::f64: |
1382 | if (NumElements == 1) return MVT::nxv1f64; |
1383 | if (NumElements == 2) return MVT::nxv2f64; |
1384 | if (NumElements == 4) return MVT::nxv4f64; |
1385 | if (NumElements == 8) return MVT::nxv8f64; |
1386 | break; |
1387 | } |
1388 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1389 | } |
1390 | |
1391 | static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) { |
1392 | if (IsScalable) |
1393 | return getScalableVectorVT(VT, NumElements); |
1394 | return getVectorVT(VT, NumElements); |
1395 | } |
1396 | |
1397 | static MVT getVectorVT(MVT VT, ElementCount EC) { |
1398 | if (EC.isScalable()) |
1399 | return getScalableVectorVT(VT, EC.getKnownMinValue()); |
1400 | return getVectorVT(VT, EC.getKnownMinValue()); |
1401 | } |
1402 | |
1403 | /// Return the value type corresponding to the specified type. This returns |
1404 | /// all pointers as iPTR. If HandleUnknown is true, unknown types are |
1405 | /// returned as Other, otherwise they are invalid. |
1406 | static MVT getVT(Type *Ty, bool HandleUnknown = false); |
1407 | |
1408 | public: |
1409 | /// SimpleValueType Iteration |
1410 | /// @{ |
1411 | static auto all_valuetypes() { |
1412 | return enum_seq_inclusive(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE, |
1413 | force_iteration_on_noniterable_enum); |
1414 | } |
1415 | |
1416 | static auto integer_valuetypes() { |
1417 | return enum_seq_inclusive(MVT::FIRST_INTEGER_VALUETYPE, |
1418 | MVT::LAST_INTEGER_VALUETYPE, |
1419 | force_iteration_on_noniterable_enum); |
1420 | } |
1421 | |
1422 | static auto fp_valuetypes() { |
1423 | return enum_seq_inclusive(MVT::FIRST_FP_VALUETYPE, MVT::LAST_FP_VALUETYPE, |
1424 | force_iteration_on_noniterable_enum); |
1425 | } |
1426 | |
1427 | static auto vector_valuetypes() { |
1428 | return enum_seq_inclusive(MVT::FIRST_VECTOR_VALUETYPE, |
1429 | MVT::LAST_VECTOR_VALUETYPE, |
1430 | force_iteration_on_noniterable_enum); |
1431 | } |
1432 | |
1433 | static auto fixedlen_vector_valuetypes() { |
1434 | return enum_seq_inclusive(MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE, |
1435 | MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE, |
1436 | force_iteration_on_noniterable_enum); |
1437 | } |
1438 | |
1439 | static auto scalable_vector_valuetypes() { |
1440 | return enum_seq_inclusive(MVT::FIRST_SCALABLE_VECTOR_VALUETYPE, |
1441 | MVT::LAST_SCALABLE_VECTOR_VALUETYPE, |
1442 | force_iteration_on_noniterable_enum); |
1443 | } |
1444 | |
1445 | static auto integer_fixedlen_vector_valuetypes() { |
1446 | return enum_seq_inclusive(MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, |
1447 | MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, |
1448 | force_iteration_on_noniterable_enum); |
1449 | } |
1450 | |
1451 | static auto fp_fixedlen_vector_valuetypes() { |
1452 | return enum_seq_inclusive(MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, |
1453 | MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE, |
1454 | force_iteration_on_noniterable_enum); |
1455 | } |
1456 | |
1457 | static auto integer_scalable_vector_valuetypes() { |
1458 | return enum_seq_inclusive(MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, |
1459 | MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, |
1460 | force_iteration_on_noniterable_enum); |
1461 | } |
1462 | |
1463 | static auto fp_scalable_vector_valuetypes() { |
1464 | return enum_seq_inclusive(MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE, |
1465 | MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE, |
1466 | force_iteration_on_noniterable_enum); |
1467 | } |
1468 | /// @} |
1469 | }; |
1470 | |
1471 | } // end namespace llvm |
1472 | |
1473 | #endif // LLVM_SUPPORT_MACHINEVALUETYPE_H |