Bug Summary

File:llvm/lib/Target/AVR/AVRISelLowering.cpp
Warning:line 1069, column 13
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/Target/AVR -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2021-01-24-223304-31662-1 -x c++ /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp

/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp

1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
53
54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
58
59 for (MVT VT : MVT::integer_valuetypes()) {
60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
61 setLoadExtAction(N, VT, MVT::i1, Promote);
62 setLoadExtAction(N, VT, MVT::i8, Expand);
63 }
64 }
65
66 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
67
68 for (MVT VT : MVT::integer_valuetypes()) {
69 setOperationAction(ISD::ADDC, VT, Legal);
70 setOperationAction(ISD::SUBC, VT, Legal);
71 setOperationAction(ISD::ADDE, VT, Legal);
72 setOperationAction(ISD::SUBE, VT, Legal);
73 }
74
75 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76 // revert into a sub since we don't have an add with immediate instruction.
77 setOperationAction(ISD::ADD, MVT::i32, Custom);
78 setOperationAction(ISD::ADD, MVT::i64, Custom);
79
80 // our shift instructions are only able to shift 1 bit at a time, so handle
81 // this in a custom way.
82 setOperationAction(ISD::SRA, MVT::i8, Custom);
83 setOperationAction(ISD::SHL, MVT::i8, Custom);
84 setOperationAction(ISD::SRL, MVT::i8, Custom);
85 setOperationAction(ISD::SRA, MVT::i16, Custom);
86 setOperationAction(ISD::SHL, MVT::i16, Custom);
87 setOperationAction(ISD::SRL, MVT::i16, Custom);
88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
91
92 setOperationAction(ISD::ROTL, MVT::i8, Custom);
93 setOperationAction(ISD::ROTL, MVT::i16, Expand);
94 setOperationAction(ISD::ROTR, MVT::i8, Custom);
95 setOperationAction(ISD::ROTR, MVT::i16, Expand);
96
97 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102
103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
107 setOperationAction(ISD::SETCC, MVT::i8, Custom);
108 setOperationAction(ISD::SETCC, MVT::i16, Custom);
109 setOperationAction(ISD::SETCC, MVT::i32, Custom);
110 setOperationAction(ISD::SETCC, MVT::i64, Custom);
111 setOperationAction(ISD::SELECT, MVT::i8, Expand);
112 setOperationAction(ISD::SELECT, MVT::i16, Expand);
113
114 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
115
116 // Add support for postincrement and predecrement load/stores.
117 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
121 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
125
126 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
127
128 setOperationAction(ISD::VASTART, MVT::Other, Custom);
129 setOperationAction(ISD::VAEND, MVT::Other, Expand);
130 setOperationAction(ISD::VAARG, MVT::Other, Expand);
131 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
132
133 // Atomic operations which must be lowered to rtlib calls
134 for (MVT VT : MVT::integer_valuetypes()) {
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
142 }
143
144 // Division/remainder
145 setOperationAction(ISD::UDIV, MVT::i8, Expand);
146 setOperationAction(ISD::UDIV, MVT::i16, Expand);
147 setOperationAction(ISD::UREM, MVT::i8, Expand);
148 setOperationAction(ISD::UREM, MVT::i16, Expand);
149 setOperationAction(ISD::SDIV, MVT::i8, Expand);
150 setOperationAction(ISD::SDIV, MVT::i16, Expand);
151 setOperationAction(ISD::SREM, MVT::i8, Expand);
152 setOperationAction(ISD::SREM, MVT::i16, Expand);
153
154 // Make division and modulus custom
155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom);
156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Custom);
159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom);
160 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
161
162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
163 setOperationAction(ISD::MUL, MVT::i8, Expand);
164 setOperationAction(ISD::MUL, MVT::i16, Expand);
165
166 // Expand 16 bit multiplications.
167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
169
170 // Expand multiplications to libcalls when there is
171 // no hardware MUL.
172 if (!Subtarget.supportsMultiplication()) {
173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
175 }
176
177 for (MVT VT : MVT::integer_valuetypes()) {
178 setOperationAction(ISD::MULHS, VT, Expand);
179 setOperationAction(ISD::MULHU, VT, Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(ISD::CTPOP, VT, Expand);
184 setOperationAction(ISD::CTLZ, VT, Expand);
185 setOperationAction(ISD::CTTZ, VT, Expand);
186 }
187
188 for (MVT VT : MVT::integer_valuetypes()) {
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 // TODO: The generated code is pretty poor. Investigate using the
191 // same "shift and subtract with carry" trick that we do for
192 // extending 8-bit to 16-bit. This may require infrastructure
193 // improvements in how we treat 16-bit "registers" to be feasible.
194 }
195
196 // Division rtlib functions (not supported), use divmod functions instead
197 setLibcallName(RTLIB::SDIV_I8, nullptr);
198 setLibcallName(RTLIB::SDIV_I16, nullptr);
199 setLibcallName(RTLIB::SDIV_I32, nullptr);
200 setLibcallName(RTLIB::UDIV_I8, nullptr);
201 setLibcallName(RTLIB::UDIV_I16, nullptr);
202 setLibcallName(RTLIB::UDIV_I32, nullptr);
203
204 // Modulus rtlib functions (not supported), use divmod functions instead
205 setLibcallName(RTLIB::SREM_I8, nullptr);
206 setLibcallName(RTLIB::SREM_I16, nullptr);
207 setLibcallName(RTLIB::SREM_I32, nullptr);
208 setLibcallName(RTLIB::UREM_I8, nullptr);
209 setLibcallName(RTLIB::UREM_I16, nullptr);
210 setLibcallName(RTLIB::UREM_I32, nullptr);
211
212 // Division and modulus rtlib functions
213 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219
220 // Several of the runtime library functions use a special calling conv
221 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
222 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
223 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
224 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225
226 // Trigonometric rtlib functions
227 setLibcallName(RTLIB::SIN_F32, "sin");
228 setLibcallName(RTLIB::COS_F32, "cos");
229
230 setMinFunctionAlignment(Align(2));
231 setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U));
232}
233
234const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235#define NODE(name) \
236 case AVRISD::name: \
237 return #name
238
239 switch (Opcode) {
240 default:
241 return nullptr;
242 NODE(RET_FLAG);
243 NODE(RETI_FLAG);
244 NODE(CALL);
245 NODE(WRAPPER);
246 NODE(LSL);
247 NODE(LSR);
248 NODE(ROL);
249 NODE(ROR);
250 NODE(ASR);
251 NODE(LSLLOOP);
252 NODE(LSRLOOP);
253 NODE(ROLLOOP);
254 NODE(RORLOOP);
255 NODE(ASRLOOP);
256 NODE(BRCOND);
257 NODE(CMP);
258 NODE(CMPC);
259 NODE(TST);
260 NODE(SELECT_CC);
261#undef NODE
262 }
263}
264
265EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
266 EVT VT) const {
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!")((!VT.isVector() && "No AVR SetCC type for vectors!")
? static_cast<void> (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 267, __PRETTY_FUNCTION__))
;
268 return MVT::i8;
269}
270
271SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272 //:TODO: this function has to be completely rewritten to produce optimal
273 // code, for now it's producing very long but correct code.
274 unsigned Opc8;
275 const SDNode *N = Op.getNode();
276 EVT VT = Op.getValueType();
277 SDLoc dl(N);
278 assert(isPowerOf2_32(VT.getSizeInBits()) &&((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
279 "Expected power-of-2 shift amount")((isPowerOf2_32(VT.getSizeInBits()) && "Expected power-of-2 shift amount"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 279, __PRETTY_FUNCTION__))
;
280
281 // Expand non-constant shifts to loops.
282 if (!isa<ConstantSDNode>(N->getOperand(1))) {
283 switch (Op.getOpcode()) {
284 default:
285 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 285)
;
286 case ISD::SHL:
287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288 N->getOperand(1));
289 case ISD::SRL:
290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291 N->getOperand(1));
292 case ISD::ROTL: {
293 SDValue Amt = N->getOperand(1);
294 EVT AmtVT = Amt.getValueType();
295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298 }
299 case ISD::ROTR: {
300 SDValue Amt = N->getOperand(1);
301 EVT AmtVT = Amt.getValueType();
302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305 }
306 case ISD::SRA:
307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308 N->getOperand(1));
309 }
310 }
311
312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313 SDValue Victim = N->getOperand(0);
314
315 switch (Op.getOpcode()) {
316 case ISD::SRA:
317 Opc8 = AVRISD::ASR;
318 break;
319 case ISD::ROTL:
320 Opc8 = AVRISD::ROL;
321 ShiftAmount = ShiftAmount % VT.getSizeInBits();
322 break;
323 case ISD::ROTR:
324 Opc8 = AVRISD::ROR;
325 ShiftAmount = ShiftAmount % VT.getSizeInBits();
326 break;
327 case ISD::SRL:
328 Opc8 = AVRISD::LSR;
329 break;
330 case ISD::SHL:
331 Opc8 = AVRISD::LSL;
332 break;
333 default:
334 llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 334)
;
335 }
336
337 // Optimize int8 shifts.
338 if (VT.getSizeInBits() == 8) {
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340 // Optimize LSL when 4 <= ShiftAmount <= 6.
341 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
342 Victim =
343 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
344 ShiftAmount -= 4;
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
346 ShiftAmount < 7) {
347 // Optimize LSR when 4 <= ShiftAmount <= 6.
348 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
349 Victim =
350 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
351 ShiftAmount -= 4;
352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
353 // Optimize LSL when ShiftAmount == 7.
354 Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim);
355 ShiftAmount = 0;
356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
357 // Optimize LSR when ShiftAmount == 7.
358 Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim);
359 ShiftAmount = 0;
360 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
361 // Optimize ASR when ShiftAmount == 7.
362 Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
363 ShiftAmount = 0;
364 }
365 }
366
367 while (ShiftAmount--) {
368 Victim = DAG.getNode(Opc8, dl, VT, Victim);
369 }
370
371 return Victim;
372}
373
374SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
375 unsigned Opcode = Op->getOpcode();
376 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 377, __PRETTY_FUNCTION__))
377 "Invalid opcode for Div/Rem lowering")(((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering") ? static_cast<void
> (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 377, __PRETTY_FUNCTION__))
;
378 bool IsSigned = (Opcode == ISD::SDIVREM);
379 EVT VT = Op->getValueType(0);
380 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
381
382 RTLIB::Libcall LC;
383 switch (VT.getSimpleVT().SimpleTy) {
384 default:
385 llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 385)
;
386 case MVT::i8:
387 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
388 break;
389 case MVT::i16:
390 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
391 break;
392 case MVT::i32:
393 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
394 break;
395 }
396
397 SDValue InChain = DAG.getEntryNode();
398
399 TargetLowering::ArgListTy Args;
400 TargetLowering::ArgListEntry Entry;
401 for (SDValue const &Value : Op->op_values()) {
402 Entry.Node = Value;
403 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
404 Entry.IsSExt = IsSigned;
405 Entry.IsZExt = !IsSigned;
406 Args.push_back(Entry);
407 }
408
409 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
410 getPointerTy(DAG.getDataLayout()));
411
412 Type *RetTy = (Type *)StructType::get(Ty, Ty);
413
414 SDLoc dl(Op);
415 TargetLowering::CallLoweringInfo CLI(DAG);
416 CLI.setDebugLoc(dl)
417 .setChain(InChain)
418 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
419 .setInRegister()
420 .setSExtResult(IsSigned)
421 .setZExtResult(!IsSigned);
422
423 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
424 return CallInfo.first;
425}
426
427SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
428 SelectionDAG &DAG) const {
429 auto DL = DAG.getDataLayout();
430
431 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
432 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
433
434 // Create the TargetGlobalAddress node, folding in the constant offset.
435 SDValue Result =
436 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
437 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
438}
439
440SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
441 SelectionDAG &DAG) const {
442 auto DL = DAG.getDataLayout();
443 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
444
445 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
446
447 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
448}
449
450/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
451static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
452 switch (CC) {
453 default:
454 llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 454)
;
455 case ISD::SETEQ:
456 return AVRCC::COND_EQ;
457 case ISD::SETNE:
458 return AVRCC::COND_NE;
459 case ISD::SETGE:
460 return AVRCC::COND_GE;
461 case ISD::SETLT:
462 return AVRCC::COND_LT;
463 case ISD::SETUGE:
464 return AVRCC::COND_SH;
465 case ISD::SETULT:
466 return AVRCC::COND_LO;
467 }
468}
469
470/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
471SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
472 SelectionDAG &DAG, SDLoc DL) const {
473 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&(((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
"LHS and RHS have different types") ? static_cast<void>
(0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 474, __PRETTY_FUNCTION__))
474 "LHS and RHS have different types")(((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
"LHS and RHS have different types") ? static_cast<void>
(0) : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 474, __PRETTY_FUNCTION__))
;
475 assert(((LHS.getSimpleValueType() == MVT::i16) ||((((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType
() == MVT::i8)) && "invalid comparison type") ? static_cast
<void> (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 476, __PRETTY_FUNCTION__))
476 (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type")((((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType
() == MVT::i8)) && "invalid comparison type") ? static_cast
<void> (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 476, __PRETTY_FUNCTION__))
;
477
478 SDValue Cmp;
479
480 if (LHS.getSimpleValueType() == MVT::i16 && dyn_cast<ConstantSDNode>(RHS)) {
481 // Generate a CPI/CPC pair if RHS is a 16-bit constant.
482 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
483 DAG.getIntPtrConstant(0, DL));
484 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
485 DAG.getIntPtrConstant(1, DL));
486 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
487 DAG.getIntPtrConstant(0, DL));
488 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
489 DAG.getIntPtrConstant(1, DL));
490 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
491 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
492 } else {
493 // Generate ordinary 16-bit comparison.
494 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
495 }
496
497 return Cmp;
498}
499
500/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
501/// the given operands.
502SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
503 SDValue &AVRcc, SelectionDAG &DAG,
504 SDLoc DL) const {
505 SDValue Cmp;
506 EVT VT = LHS.getValueType();
507 bool UseTest = false;
508
509 switch (CC) {
510 default:
511 break;
512 case ISD::SETLE: {
513 // Swap operands and reverse the branching condition.
514 std::swap(LHS, RHS);
515 CC = ISD::SETGE;
516 break;
517 }
518 case ISD::SETGT: {
519 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
520 switch (C->getSExtValue()) {
521 case -1: {
522 // When doing lhs > -1 use a tst instruction on the top part of lhs
523 // and use brpl instead of using a chain of cp/cpc.
524 UseTest = true;
525 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
526 break;
527 }
528 case 0: {
529 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
530 // __zero_reg__ in lhs.
531 RHS = LHS;
532 LHS = DAG.getConstant(0, DL, VT);
533 CC = ISD::SETLT;
534 break;
535 }
536 default: {
537 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
538 // us to fold the constant into the cmp instruction.
539 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
540 CC = ISD::SETGE;
541 break;
542 }
543 }
544 break;
545 }
546 // Swap operands and reverse the branching condition.
547 std::swap(LHS, RHS);
548 CC = ISD::SETLT;
549 break;
550 }
551 case ISD::SETLT: {
552 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
553 switch (C->getSExtValue()) {
554 case 1: {
555 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
556 // __zero_reg__ in lhs.
557 RHS = LHS;
558 LHS = DAG.getConstant(0, DL, VT);
559 CC = ISD::SETGE;
560 break;
561 }
562 case 0: {
563 // When doing lhs < 0 use a tst instruction on the top part of lhs
564 // and use brmi instead of using a chain of cp/cpc.
565 UseTest = true;
566 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
567 break;
568 }
569 }
570 }
571 break;
572 }
573 case ISD::SETULE: {
574 // Swap operands and reverse the branching condition.
575 std::swap(LHS, RHS);
576 CC = ISD::SETUGE;
577 break;
578 }
579 case ISD::SETUGT: {
580 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
581 // fold the constant into the cmp instruction.
582 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
583 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
584 CC = ISD::SETUGE;
585 break;
586 }
587 // Swap operands and reverse the branching condition.
588 std::swap(LHS, RHS);
589 CC = ISD::SETULT;
590 break;
591 }
592 }
593
594 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
595 // using the default and/or/xor expansion code which is much longer.
596 if (VT == MVT::i32) {
597 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
598 DAG.getIntPtrConstant(0, DL));
599 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
600 DAG.getIntPtrConstant(1, DL));
601 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
602 DAG.getIntPtrConstant(0, DL));
603 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
604 DAG.getIntPtrConstant(1, DL));
605
606 if (UseTest) {
607 // When using tst we only care about the highest part.
608 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
609 DAG.getIntPtrConstant(1, DL));
610 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
611 } else {
612 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
613 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
614 }
615 } else if (VT == MVT::i64) {
616 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
617 DAG.getIntPtrConstant(0, DL));
618 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
619 DAG.getIntPtrConstant(1, DL));
620
621 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
622 DAG.getIntPtrConstant(0, DL));
623 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
624 DAG.getIntPtrConstant(1, DL));
625 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
626 DAG.getIntPtrConstant(0, DL));
627 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
628 DAG.getIntPtrConstant(1, DL));
629
630 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
631 DAG.getIntPtrConstant(0, DL));
632 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
633 DAG.getIntPtrConstant(1, DL));
634
635 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
636 DAG.getIntPtrConstant(0, DL));
637 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
638 DAG.getIntPtrConstant(1, DL));
639 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
640 DAG.getIntPtrConstant(0, DL));
641 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
642 DAG.getIntPtrConstant(1, DL));
643
644 if (UseTest) {
645 // When using tst we only care about the highest part.
646 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
647 DAG.getIntPtrConstant(1, DL));
648 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
649 } else {
650 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
651 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
652 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
653 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
654 }
655 } else if (VT == MVT::i8 || VT == MVT::i16) {
656 if (UseTest) {
657 // When using tst we only care about the highest part.
658 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
659 (VT == MVT::i8)
660 ? LHS
661 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
662 LHS, DAG.getIntPtrConstant(1, DL)));
663 } else {
664 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
665 }
666 } else {
667 llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 667)
;
668 }
669
670 // When using a test instruction AVRcc is already set.
671 if (!UseTest) {
672 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
673 }
674
675 return Cmp;
676}
677
678SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
679 SDValue Chain = Op.getOperand(0);
680 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
681 SDValue LHS = Op.getOperand(2);
682 SDValue RHS = Op.getOperand(3);
683 SDValue Dest = Op.getOperand(4);
684 SDLoc dl(Op);
685
686 SDValue TargetCC;
687 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
688
689 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
690 Cmp);
691}
692
693SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
694 SDValue LHS = Op.getOperand(0);
695 SDValue RHS = Op.getOperand(1);
696 SDValue TrueV = Op.getOperand(2);
697 SDValue FalseV = Op.getOperand(3);
698 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
699 SDLoc dl(Op);
700
701 SDValue TargetCC;
702 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
703
704 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
705 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
706
707 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
708}
709
710SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
711 SDValue LHS = Op.getOperand(0);
712 SDValue RHS = Op.getOperand(1);
713 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
714 SDLoc DL(Op);
715
716 SDValue TargetCC;
717 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
718
719 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
720 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
721 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
722 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
723
724 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
725}
726
727SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
728 const MachineFunction &MF = DAG.getMachineFunction();
729 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
730 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
731 auto DL = DAG.getDataLayout();
732 SDLoc dl(Op);
733
734 // Vastart just stores the address of the VarArgsFrameIndex slot into the
735 // memory location argument.
736 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
737
738 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
739 MachinePointerInfo(SV));
740}
741
742SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
743 switch (Op.getOpcode()) {
744 default:
745 llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 745)
;
746 case ISD::SHL:
747 case ISD::SRA:
748 case ISD::SRL:
749 case ISD::ROTL:
750 case ISD::ROTR:
751 return LowerShifts(Op, DAG);
752 case ISD::GlobalAddress:
753 return LowerGlobalAddress(Op, DAG);
754 case ISD::BlockAddress:
755 return LowerBlockAddress(Op, DAG);
756 case ISD::BR_CC:
757 return LowerBR_CC(Op, DAG);
758 case ISD::SELECT_CC:
759 return LowerSELECT_CC(Op, DAG);
760 case ISD::SETCC:
761 return LowerSETCC(Op, DAG);
762 case ISD::VASTART:
763 return LowerVASTART(Op, DAG);
764 case ISD::SDIVREM:
765 case ISD::UDIVREM:
766 return LowerDivRem(Op, DAG);
767 }
768
769 return SDValue();
770}
771
772/// Replace a node with an illegal result type
773/// with a new node built out of custom code.
774void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
775 SmallVectorImpl<SDValue> &Results,
776 SelectionDAG &DAG) const {
777 SDLoc DL(N);
778
779 switch (N->getOpcode()) {
780 case ISD::ADD: {
781 // Convert add (x, imm) into sub (x, -imm).
782 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
783 SDValue Sub = DAG.getNode(
784 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
785 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
786 Results.push_back(Sub);
787 }
788 break;
789 }
790 default: {
791 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
792
793 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
794 Results.push_back(Res.getValue(I));
795
796 break;
797 }
798 }
799}
800
801/// Return true if the addressing mode represented
802/// by AM is legal for this target, for a load/store of the specified type.
803bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
804 const AddrMode &AM, Type *Ty,
805 unsigned AS, Instruction *I) const {
806 int64_t Offs = AM.BaseOffs;
807
808 // Allow absolute addresses.
809 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
810 return true;
811 }
812
813 // Flash memory instructions only allow zero offsets.
814 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
815 return false;
816 }
817
818 // Allow reg+<6bit> offset.
819 if (Offs < 0)
820 Offs = -Offs;
821 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
822 return true;
823 }
824
825 return false;
826}
827
828/// Returns true by value, base pointer and
829/// offset pointer and addressing mode by reference if the node's address
830/// can be legally represented as pre-indexed load / store address.
831bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
832 SDValue &Offset,
833 ISD::MemIndexedMode &AM,
834 SelectionDAG &DAG) const {
835 EVT VT;
836 const SDNode *Op;
837 SDLoc DL(N);
838
839 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
840 VT = LD->getMemoryVT();
841 Op = LD->getBasePtr().getNode();
842 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
843 return false;
844 if (AVR::isProgramMemoryAccess(LD)) {
845 return false;
846 }
847 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
848 VT = ST->getMemoryVT();
849 Op = ST->getBasePtr().getNode();
850 if (AVR::isProgramMemoryAccess(ST)) {
851 return false;
852 }
853 } else {
854 return false;
855 }
856
857 if (VT != MVT::i8 && VT != MVT::i16) {
858 return false;
859 }
860
861 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
862 return false;
863 }
864
865 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
866 int RHSC = RHS->getSExtValue();
867 if (Op->getOpcode() == ISD::SUB)
868 RHSC = -RHSC;
869
870 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
871 return false;
872 }
873
874 Base = Op->getOperand(0);
875 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
876 AM = ISD::PRE_DEC;
877
878 return true;
879 }
880
881 return false;
882}
883
884/// Returns true by value, base pointer and
885/// offset pointer and addressing mode by reference if this node can be
886/// combined with a load / store to form a post-indexed load / store.
887bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
888 SDValue &Base,
889 SDValue &Offset,
890 ISD::MemIndexedMode &AM,
891 SelectionDAG &DAG) const {
892 EVT VT;
893 SDLoc DL(N);
894
895 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
896 VT = LD->getMemoryVT();
897 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
898 return false;
899 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
900 VT = ST->getMemoryVT();
901 if (AVR::isProgramMemoryAccess(ST)) {
902 return false;
903 }
904 } else {
905 return false;
906 }
907
908 if (VT != MVT::i8 && VT != MVT::i16) {
909 return false;
910 }
911
912 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
913 return false;
914 }
915
916 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
917 int RHSC = RHS->getSExtValue();
918 if (Op->getOpcode() == ISD::SUB)
919 RHSC = -RHSC;
920 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
921 return false;
922 }
923
924 Base = Op->getOperand(0);
925 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
926 AM = ISD::POST_INC;
927
928 return true;
929 }
930
931 return false;
932}
933
934bool AVRTargetLowering::isOffsetFoldingLegal(
935 const GlobalAddressSDNode *GA) const {
936 return true;
937}
938
939//===----------------------------------------------------------------------===//
940// Formal Arguments Calling Convention Implementation
941//===----------------------------------------------------------------------===//
942
943#include "AVRGenCallingConv.inc"
944
945/// Registers for calling conventions, ordered in reverse as required by ABI.
946/// Both arrays must be of the same length.
947static const MCPhysReg RegList8[] = {
948 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
949 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
950 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
951static const MCPhysReg RegList16[] = {
952 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
953 AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
954 AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
955 AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
956 AVR::R10R9, AVR::R9R8};
957
958static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
959 "8-bit and 16-bit register arrays must be of equal length");
960
961/// Analyze incoming and outgoing function arguments. We need custom C++ code
962/// to handle special constraints in the ABI.
963/// In addition, all pieces of a certain argument have to be passed either
964/// using registers or the stack but never mixing both.
965template <typename ArgT>
966static void
967analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
968 const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
969 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
970 unsigned NumArgs = Args.size();
971 // This is the index of the last used register, in RegList*.
972 // -1 means R26 (R26 is never actually used in CC).
973 int RegLastIdx = -1;
974 // Once a value is passed to the stack it will always be used
975 bool UseStack = false;
976 for (unsigned i = 0; i != NumArgs;) {
977 MVT VT = Args[i].VT;
978 // We have to count the number of bytes for each function argument, that is
979 // those Args with the same OrigArgIndex. This is important in case the
980 // function takes an aggregate type.
981 // Current argument will be between [i..j).
982 unsigned ArgIndex = Args[i].OrigArgIndex;
983 unsigned TotalBytes = VT.getStoreSize();
984 unsigned j = i + 1;
985 for (; j != NumArgs; ++j) {
986 if (Args[j].OrigArgIndex != ArgIndex)
987 break;
988 TotalBytes += Args[j].VT.getStoreSize();
989 }
990 // Round up to even number of bytes.
991 TotalBytes = alignTo(TotalBytes, 2);
992 // Skip zero sized arguments
993 if (TotalBytes == 0)
994 continue;
995 // The index of the first register to be used
996 unsigned RegIdx = RegLastIdx + TotalBytes;
997 RegLastIdx = RegIdx;
998 // If there are not enough registers, use the stack
999 if (RegIdx >= array_lengthof(RegList8)) {
1000 UseStack = true;
1001 }
1002 for (; i != j; ++i) {
1003 MVT VT = Args[i].VT;
1004
1005 if (UseStack) {
1006 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1007 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1008 TD->getABITypeAlign(evt));
1009 CCInfo.addLoc(
1010 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
1011 } else {
1012 unsigned Reg;
1013 if (VT == MVT::i8) {
1014 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1015 } else if (VT == MVT::i16) {
1016 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1017 } else {
1018 llvm_unreachable(::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1019)
1019 "calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1019)
;
1020 }
1021 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1021, __PRETTY_FUNCTION__))
;
1022 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1023 // Registers inside a particular argument are sorted in increasing order
1024 // (remember the array is reversed).
1025 RegIdx -= VT.getStoreSize();
1026 }
1027 }
1028 }
1029}
1030
1031/// Count the total number of bytes needed to pass or return these arguments.
1032template <typename ArgT>
1033static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
1034 unsigned TotalBytes = 0;
1035
1036 for (const ArgT& Arg : Args) {
1037 TotalBytes += Arg.VT.getStoreSize();
1038 }
1039 return TotalBytes;
1040}
1041
1042/// Analyze incoming and outgoing value of returning from a function.
1043/// The algorithm is similar to analyzeArguments, but there can only be
1044/// one value, possibly an aggregate, and it is limited to 8 bytes.
1045template <typename ArgT>
1046static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
1047 CCState &CCInfo) {
1048 unsigned NumArgs = Args.size();
1049 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1050 // CanLowerReturn() guarantees this assertion.
1051 assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered")((TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"
) ? static_cast<void> (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1051, __PRETTY_FUNCTION__))
;
4
'?' condition is true
1052
1053 // GCC-ABI says that the size is rounded up to the next even number,
1054 // but actually once it is more than 4 it will always round up to 8.
1055 if (TotalBytes
4.1
'TotalBytes' is <= 4
4.1
'TotalBytes' is <= 4
> 4) {
5
Taking false branch
1056 TotalBytes = 8;
1057 } else {
1058 TotalBytes = alignTo(TotalBytes, 2);
1059 }
1060
1061 // The index of the first register to use.
1062 int RegIdx = TotalBytes - 1;
6
'RegIdx' initialized to -1
1063 for (unsigned i = 0; i != NumArgs; ++i) {
7
Assuming 'i' is not equal to 'NumArgs'
8
Loop condition is true. Entering loop body
1064 MVT VT = Args[i].VT;
1065 unsigned Reg;
1066 if (VT == MVT::i8) {
9
Calling 'MVT::operator=='
12
Returning from 'MVT::operator=='
13
Taking false branch
1067 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1068 } else if (VT == MVT::i16) {
14
Taking true branch
1069 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
15
1st function call argument is an uninitialized value
1070 } else {
1071 llvm_unreachable("calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1071)
;
1072 }
1073 assert(Reg && "register not available in calling convention")((Reg && "register not available in calling convention"
) ? static_cast<void> (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1073, __PRETTY_FUNCTION__))
;
1074 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1075 // Registers sort in increasing order
1076 RegIdx -= VT.getStoreSize();
1077 }
1078}
1079
1080SDValue AVRTargetLowering::LowerFormalArguments(
1081 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1082 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1083 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1084 MachineFunction &MF = DAG.getMachineFunction();
1085 MachineFrameInfo &MFI = MF.getFrameInfo();
1086 auto DL = DAG.getDataLayout();
1087
1088 // Assign locations to all of the incoming arguments.
1089 SmallVector<CCValAssign, 16> ArgLocs;
1090 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1091 *DAG.getContext());
1092
1093 // Variadic functions do not need all the analysis below.
1094 if (isVarArg) {
1095 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1096 } else {
1097 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1098 }
1099
1100 SDValue ArgValue;
1101 for (CCValAssign &VA : ArgLocs) {
1102
1103 // Arguments stored on registers.
1104 if (VA.isRegLoc()) {
1105 EVT RegVT = VA.getLocVT();
1106 const TargetRegisterClass *RC;
1107 if (RegVT == MVT::i8) {
1108 RC = &AVR::GPR8RegClass;
1109 } else if (RegVT == MVT::i16) {
1110 RC = &AVR::DREGSRegClass;
1111 } else {
1112 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1112)
;
1113 }
1114
1115 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1116 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1117
1118 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1119 // following code will handle zexts or sexts generated by other
1120 // front ends. Otherwise:
1121 // If this is an 8 bit value, it is really passed promoted
1122 // to 16 bits. Insert an assert[sz]ext to capture this, then
1123 // truncate to the right size.
1124 switch (VA.getLocInfo()) {
1125 default:
1126 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1126)
;
1127 case CCValAssign::Full:
1128 break;
1129 case CCValAssign::BCvt:
1130 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1131 break;
1132 case CCValAssign::SExt:
1133 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1134 DAG.getValueType(VA.getValVT()));
1135 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1136 break;
1137 case CCValAssign::ZExt:
1138 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1139 DAG.getValueType(VA.getValVT()));
1140 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1141 break;
1142 }
1143
1144 InVals.push_back(ArgValue);
1145 } else {
1146 // Sanity check.
1147 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1147, __PRETTY_FUNCTION__))
;
1148
1149 EVT LocVT = VA.getLocVT();
1150
1151 // Create the frame index object for this incoming parameter.
1152 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1153 VA.getLocMemOffset(), true);
1154
1155 // Create the SelectionDAG nodes corresponding to a load
1156 // from this parameter.
1157 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1158 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1159 MachinePointerInfo::getFixedStack(MF, FI)));
1160 }
1161 }
1162
1163 // If the function takes variable number of arguments, make a frame index for
1164 // the start of the first vararg value... for expansion of llvm.va_start.
1165 if (isVarArg) {
1166 unsigned StackSize = CCInfo.getNextStackOffset();
1167 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1168
1169 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1170 }
1171
1172 return Chain;
1173}
1174
1175//===----------------------------------------------------------------------===//
1176// Call Calling Convention Implementation
1177//===----------------------------------------------------------------------===//
1178
1179SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1180 SmallVectorImpl<SDValue> &InVals) const {
1181 SelectionDAG &DAG = CLI.DAG;
1182 SDLoc &DL = CLI.DL;
1183 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1184 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1185 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1186 SDValue Chain = CLI.Chain;
1187 SDValue Callee = CLI.Callee;
1188 bool &isTailCall = CLI.IsTailCall;
1189 CallingConv::ID CallConv = CLI.CallConv;
1190 bool isVarArg = CLI.IsVarArg;
1191
1192 MachineFunction &MF = DAG.getMachineFunction();
1193
1194 // AVR does not yet support tail call optimization.
1195 isTailCall = false;
1196
1197 // Analyze operands of the call, assigning locations to each operand.
1198 SmallVector<CCValAssign, 16> ArgLocs;
1199 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1200 *DAG.getContext());
1201
1202 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1203 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1204 // node so that legalize doesn't hack it.
1205 const Function *F = nullptr;
1206 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1207 const GlobalValue *GV = G->getGlobal();
1208
1209 F = cast<Function>(GV);
1210 Callee =
1211 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1212 } else if (const ExternalSymbolSDNode *ES =
1213 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1214 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1215 getPointerTy(DAG.getDataLayout()));
1216 }
1217
1218 // Variadic functions do not need all the analysis below.
1219 if (isVarArg) {
1220 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1221 } else {
1222 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1223 }
1224
1225 // Get a count of how many bytes are to be pushed on the stack.
1226 unsigned NumBytes = CCInfo.getNextStackOffset();
1227
1228 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1229
1230 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1231
1232 // First, walk the register assignments, inserting copies.
1233 unsigned AI, AE;
1234 bool HasStackArgs = false;
1235 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1236 CCValAssign &VA = ArgLocs[AI];
1237 EVT RegVT = VA.getLocVT();
1238 SDValue Arg = OutVals[AI];
1239
1240 // Promote the value if needed. With Clang this should not happen.
1241 switch (VA.getLocInfo()) {
1242 default:
1243 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1243)
;
1244 case CCValAssign::Full:
1245 break;
1246 case CCValAssign::SExt:
1247 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1248 break;
1249 case CCValAssign::ZExt:
1250 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1251 break;
1252 case CCValAssign::AExt:
1253 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1254 break;
1255 case CCValAssign::BCvt:
1256 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1257 break;
1258 }
1259
1260 // Stop when we encounter a stack argument, we need to process them
1261 // in reverse order in the loop below.
1262 if (VA.isMemLoc()) {
1263 HasStackArgs = true;
1264 break;
1265 }
1266
1267 // Arguments that can be passed on registers must be kept in the RegsToPass
1268 // vector.
1269 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1270 }
1271
1272 // Second, stack arguments have to walked in reverse order by inserting
1273 // chained stores, this ensures their order is not changed by the scheduler
1274 // and that the push instruction sequence generated is correct, otherwise they
1275 // can be freely intermixed.
1276 if (HasStackArgs) {
1277 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1278 unsigned Loc = AI - 1;
1279 CCValAssign &VA = ArgLocs[Loc];
1280 SDValue Arg = OutVals[Loc];
1281
1282 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1282, __PRETTY_FUNCTION__))
;
1283
1284 // SP points to one stack slot further so add one to adjust it.
1285 SDValue PtrOff = DAG.getNode(
1286 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1287 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1288 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1289
1290 Chain =
1291 DAG.getStore(Chain, DL, Arg, PtrOff,
1292 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()));
1293 }
1294 }
1295
1296 // Build a sequence of copy-to-reg nodes chained together with token chain and
1297 // flag operands which copy the outgoing args into registers. The InFlag in
1298 // necessary since all emited instructions must be stuck together.
1299 SDValue InFlag;
1300 for (auto Reg : RegsToPass) {
1301 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1302 InFlag = Chain.getValue(1);
1303 }
1304
1305 // Returns a chain & a flag for retval copy to use.
1306 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1307 SmallVector<SDValue, 8> Ops;
1308 Ops.push_back(Chain);
1309 Ops.push_back(Callee);
1310
1311 // Add argument registers to the end of the list so that they are known live
1312 // into the call.
1313 for (auto Reg : RegsToPass) {
1314 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1315 }
1316
1317 // Add a register mask operand representing the call-preserved registers.
1318 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1319 const uint32_t *Mask =
1320 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1321 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1321, __PRETTY_FUNCTION__))
;
1322 Ops.push_back(DAG.getRegisterMask(Mask));
1323
1324 if (InFlag.getNode()) {
1325 Ops.push_back(InFlag);
1326 }
1327
1328 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1329 InFlag = Chain.getValue(1);
1330
1331 // Create the CALLSEQ_END node.
1332 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1333 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1334
1335 if (!Ins.empty()) {
1336 InFlag = Chain.getValue(1);
1337 }
1338
1339 // Handle result values, copying them out of physregs into vregs that we
1340 // return.
1341 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1342 InVals);
1343}
1344
1345/// Lower the result values of a call into the
1346/// appropriate copies out of appropriate physical registers.
1347///
1348SDValue AVRTargetLowering::LowerCallResult(
1349 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1350 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1351 SmallVectorImpl<SDValue> &InVals) const {
1352
1353 // Assign locations to each value returned by this call.
1354 SmallVector<CCValAssign, 16> RVLocs;
1355 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1356 *DAG.getContext());
1357
1358 // Handle runtime calling convs.
1359 if (CallConv == CallingConv::AVR_BUILTIN) {
1360 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1361 } else {
1362 analyzeReturnValues(Ins, CCInfo);
1363 }
1364
1365 // Copy all of the result registers out of their specified physreg.
1366 for (CCValAssign const &RVLoc : RVLocs) {
1367 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1368 InFlag)
1369 .getValue(1);
1370 InFlag = Chain.getValue(2);
1371 InVals.push_back(Chain.getValue(0));
1372 }
1373
1374 return Chain;
1375}
1376
1377//===----------------------------------------------------------------------===//
1378// Return Value Calling Convention Implementation
1379//===----------------------------------------------------------------------===//
1380
1381bool AVRTargetLowering::CanLowerReturn(
1382 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1383 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1384 if (CallConv == CallingConv::AVR_BUILTIN) {
1385 SmallVector<CCValAssign, 16> RVLocs;
1386 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1387 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1388 }
1389
1390 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1391 return TotalBytes <= 8;
1392}
1393
1394SDValue
1395AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1396 bool isVarArg,
1397 const SmallVectorImpl<ISD::OutputArg> &Outs,
1398 const SmallVectorImpl<SDValue> &OutVals,
1399 const SDLoc &dl, SelectionDAG &DAG) const {
1400 // CCValAssign - represent the assignment of the return value to locations.
1401 SmallVector<CCValAssign, 16> RVLocs;
1402
1403 // CCState - Info about the registers and stack slot.
1404 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1405 *DAG.getContext());
1406
1407 MachineFunction &MF = DAG.getMachineFunction();
1408
1409 // Analyze return values.
1410 if (CallConv == CallingConv::AVR_BUILTIN) {
1
Assuming 'CallConv' is not equal to AVR_BUILTIN
2
Taking false branch
1411 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1412 } else {
1413 analyzeReturnValues(Outs, CCInfo);
3
Calling 'analyzeReturnValues<llvm::ISD::OutputArg>'
1414 }
1415
1416 SDValue Flag;
1417 SmallVector<SDValue, 4> RetOps(1, Chain);
1418 // Copy the result values into the output registers.
1419 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1420 CCValAssign &VA = RVLocs[i];
1421 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1421, __PRETTY_FUNCTION__))
;
1422
1423 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1424
1425 // Guarantee that all emitted copies are stuck together with flags.
1426 Flag = Chain.getValue(1);
1427 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1428 }
1429
1430 // Don't emit the ret/reti instruction when the naked attribute is present in
1431 // the function being compiled.
1432 if (MF.getFunction().getAttributes().hasAttribute(
1433 AttributeList::FunctionIndex, Attribute::Naked)) {
1434 return Chain;
1435 }
1436
1437 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1438
1439 unsigned RetOpc =
1440 AFI->isInterruptOrSignalHandler()
1441 ? AVRISD::RETI_FLAG
1442 : AVRISD::RET_FLAG;
1443
1444 RetOps[0] = Chain; // Update chain.
1445
1446 if (Flag.getNode()) {
1447 RetOps.push_back(Flag);
1448 }
1449
1450 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1451}
1452
1453//===----------------------------------------------------------------------===//
1454// Custom Inserters
1455//===----------------------------------------------------------------------===//
1456
1457MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1458 MachineBasicBlock *BB) const {
1459 unsigned Opc;
1460 const TargetRegisterClass *RC;
1461 bool HasRepeatedOperand = false;
1462 MachineFunction *F = BB->getParent();
1463 MachineRegisterInfo &RI = F->getRegInfo();
1464 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1465 DebugLoc dl = MI.getDebugLoc();
1466
1467 switch (MI.getOpcode()) {
1468 default:
1469 llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1469)
;
1470 case AVR::Lsl8:
1471 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1472 RC = &AVR::GPR8RegClass;
1473 HasRepeatedOperand = true;
1474 break;
1475 case AVR::Lsl16:
1476 Opc = AVR::LSLWRd;
1477 RC = &AVR::DREGSRegClass;
1478 break;
1479 case AVR::Asr8:
1480 Opc = AVR::ASRRd;
1481 RC = &AVR::GPR8RegClass;
1482 break;
1483 case AVR::Asr16:
1484 Opc = AVR::ASRWRd;
1485 RC = &AVR::DREGSRegClass;
1486 break;
1487 case AVR::Lsr8:
1488 Opc = AVR::LSRRd;
1489 RC = &AVR::GPR8RegClass;
1490 break;
1491 case AVR::Lsr16:
1492 Opc = AVR::LSRWRd;
1493 RC = &AVR::DREGSRegClass;
1494 break;
1495 case AVR::Rol8:
1496 Opc = AVR::ROLBRd;
1497 RC = &AVR::GPR8RegClass;
1498 break;
1499 case AVR::Rol16:
1500 Opc = AVR::ROLWRd;
1501 RC = &AVR::DREGSRegClass;
1502 break;
1503 case AVR::Ror8:
1504 Opc = AVR::RORBRd;
1505 RC = &AVR::GPR8RegClass;
1506 break;
1507 case AVR::Ror16:
1508 Opc = AVR::RORWRd;
1509 RC = &AVR::DREGSRegClass;
1510 break;
1511 }
1512
1513 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1514
1515 MachineFunction::iterator I;
1516 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1517 if (I != F->end()) ++I;
1518
1519 // Create loop block.
1520 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1521 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1522 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1523
1524 F->insert(I, LoopBB);
1525 F->insert(I, CheckBB);
1526 F->insert(I, RemBB);
1527
1528 // Update machine-CFG edges by transferring all successors of the current
1529 // block to the block containing instructions after shift.
1530 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1531 BB->end());
1532 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1533
1534 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1535 BB->addSuccessor(CheckBB);
1536 LoopBB->addSuccessor(CheckBB);
1537 CheckBB->addSuccessor(LoopBB);
1538 CheckBB->addSuccessor(RemBB);
1539
1540 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1541 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1542 Register ShiftReg = RI.createVirtualRegister(RC);
1543 Register ShiftReg2 = RI.createVirtualRegister(RC);
1544 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1545 Register SrcReg = MI.getOperand(1).getReg();
1546 Register DstReg = MI.getOperand(0).getReg();
1547
1548 // BB:
1549 // rjmp CheckBB
1550 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1551
1552 // LoopBB:
1553 // ShiftReg2 = shift ShiftReg
1554 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1555 if (HasRepeatedOperand)
1556 ShiftMI.addReg(ShiftReg);
1557
1558 // CheckBB:
1559 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1560 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1561 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1562 // ShiftAmt2 = ShiftAmt - 1;
1563 // if (ShiftAmt2 >= 0) goto LoopBB;
1564 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1565 .addReg(SrcReg)
1566 .addMBB(BB)
1567 .addReg(ShiftReg2)
1568 .addMBB(LoopBB);
1569 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1570 .addReg(ShiftAmtSrcReg)
1571 .addMBB(BB)
1572 .addReg(ShiftAmtReg2)
1573 .addMBB(LoopBB);
1574 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1575 .addReg(SrcReg)
1576 .addMBB(BB)
1577 .addReg(ShiftReg2)
1578 .addMBB(LoopBB);
1579
1580 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2)
1581 .addReg(ShiftAmtReg);
1582 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1583
1584 MI.eraseFromParent(); // The pseudo instruction is gone now.
1585 return RemBB;
1586}
1587
1588static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
1589 if (I->getOpcode() == AVR::COPY) {
1590 Register SrcReg = I->getOperand(1).getReg();
1591 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1592 }
1593
1594 return false;
1595}
1596
1597// The mul instructions wreak havock on our zero_reg R1. We need to clear it
1598// after the result has been evacuated. This is probably not the best way to do
1599// it, but it works for now.
1600MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1601 MachineBasicBlock *BB) const {
1602 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1603 MachineBasicBlock::iterator I(MI);
1604 ++I; // in any case insert *after* the mul instruction
1605 if (isCopyMulResult(I))
1606 ++I;
1607 if (isCopyMulResult(I))
1608 ++I;
1609 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1610 .addReg(AVR::R1)
1611 .addReg(AVR::R1);
1612 return BB;
1613}
1614
1615MachineBasicBlock *
1616AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1617 MachineBasicBlock *MBB) const {
1618 int Opc = MI.getOpcode();
1619
1620 // Pseudo shift instructions with a non constant shift amount are expanded
1621 // into a loop.
1622 switch (Opc) {
1623 case AVR::Lsl8:
1624 case AVR::Lsl16:
1625 case AVR::Lsr8:
1626 case AVR::Lsr16:
1627 case AVR::Rol8:
1628 case AVR::Rol16:
1629 case AVR::Ror8:
1630 case AVR::Ror16:
1631 case AVR::Asr8:
1632 case AVR::Asr16:
1633 return insertShift(MI, MBB);
1634 case AVR::MULRdRr:
1635 case AVR::MULSRdRr:
1636 return insertMul(MI, MBB);
1637 }
1638
1639 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1640, __PRETTY_FUNCTION__))
1640 "Unexpected instr type to insert")(((Opc == AVR::Select16 || Opc == AVR::Select8) && "Unexpected instr type to insert"
) ? static_cast<void> (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1640, __PRETTY_FUNCTION__))
;
1641
1642 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1643 ->getParent()
1644 ->getSubtarget()
1645 .getInstrInfo();
1646 DebugLoc dl = MI.getDebugLoc();
1647
1648 // To "insert" a SELECT instruction, we insert the diamond
1649 // control-flow pattern. The incoming instruction knows the
1650 // destination vreg to set, the condition code register to branch
1651 // on, the true/false values to select between, and a branch opcode
1652 // to use.
1653
1654 MachineFunction *MF = MBB->getParent();
1655 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1656 MachineBasicBlock *FallThrough = MBB->getFallThrough();
1657
1658 // If the current basic block falls through to another basic block,
1659 // we must insert an unconditional branch to the fallthrough destination
1660 // if we are to insert basic blocks at the prior fallthrough point.
1661 if (FallThrough != nullptr) {
1662 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1663 }
1664
1665 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1666 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1667
1668 MachineFunction::iterator I;
1669 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1670 if (I != MF->end()) ++I;
1671 MF->insert(I, trueMBB);
1672 MF->insert(I, falseMBB);
1673
1674 // Transfer remaining instructions and all successors of the current
1675 // block to the block which will contain the Phi node for the
1676 // select.
1677 trueMBB->splice(trueMBB->begin(), MBB,
1678 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1679 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1680
1681 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1682 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1683 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1684 MBB->addSuccessor(falseMBB);
1685 MBB->addSuccessor(trueMBB);
1686
1687 // Unconditionally flow back to the true block
1688 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1689 falseMBB->addSuccessor(trueMBB);
1690
1691 // Set up the Phi node to determine where we came from
1692 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1693 .addReg(MI.getOperand(1).getReg())
1694 .addMBB(MBB)
1695 .addReg(MI.getOperand(2).getReg())
1696 .addMBB(falseMBB) ;
1697
1698 MI.eraseFromParent(); // The pseudo instruction is gone now.
1699 return trueMBB;
1700}
1701
1702//===----------------------------------------------------------------------===//
1703// Inline Asm Support
1704//===----------------------------------------------------------------------===//
1705
1706AVRTargetLowering::ConstraintType
1707AVRTargetLowering::getConstraintType(StringRef Constraint) const {
1708 if (Constraint.size() == 1) {
1709 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1710 switch (Constraint[0]) {
1711 default:
1712 break;
1713 case 'a': // Simple upper registers
1714 case 'b': // Base pointer registers pairs
1715 case 'd': // Upper register
1716 case 'l': // Lower registers
1717 case 'e': // Pointer register pairs
1718 case 'q': // Stack pointer register
1719 case 'r': // Any register
1720 case 'w': // Special upper register pairs
1721 return C_RegisterClass;
1722 case 't': // Temporary register
1723 case 'x': case 'X': // Pointer register pair X
1724 case 'y': case 'Y': // Pointer register pair Y
1725 case 'z': case 'Z': // Pointer register pair Z
1726 return C_Register;
1727 case 'Q': // A memory address based on Y or Z pointer with displacement.
1728 return C_Memory;
1729 case 'G': // Floating point constant
1730 case 'I': // 6-bit positive integer constant
1731 case 'J': // 6-bit negative integer constant
1732 case 'K': // Integer constant (Range: 2)
1733 case 'L': // Integer constant (Range: 0)
1734 case 'M': // 8-bit integer constant
1735 case 'N': // Integer constant (Range: -1)
1736 case 'O': // Integer constant (Range: 8, 16, 24)
1737 case 'P': // Integer constant (Range: 1)
1738 case 'R': // Integer constant (Range: -6 to 5)x
1739 return C_Immediate;
1740 }
1741 }
1742
1743 return TargetLowering::getConstraintType(Constraint);
1744}
1745
1746unsigned
1747AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
1748 // Not sure if this is actually the right thing to do, but we got to do
1749 // *something* [agnat]
1750 switch (ConstraintCode[0]) {
1751 case 'Q':
1752 return InlineAsm::Constraint_Q;
1753 }
1754 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1755}
1756
1757AVRTargetLowering::ConstraintWeight
1758AVRTargetLowering::getSingleConstraintMatchWeight(
1759 AsmOperandInfo &info, const char *constraint) const {
1760 ConstraintWeight weight = CW_Invalid;
1761 Value *CallOperandVal = info.CallOperandVal;
1762
1763 // If we don't have a value, we can't do a match,
1764 // but allow it at the lowest weight.
1765 // (this behaviour has been copied from the ARM backend)
1766 if (!CallOperandVal) {
1767 return CW_Default;
1768 }
1769
1770 // Look at the constraint type.
1771 switch (*constraint) {
1772 default:
1773 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1774 break;
1775 case 'd':
1776 case 'r':
1777 case 'l':
1778 weight = CW_Register;
1779 break;
1780 case 'a':
1781 case 'b':
1782 case 'e':
1783 case 'q':
1784 case 't':
1785 case 'w':
1786 case 'x': case 'X':
1787 case 'y': case 'Y':
1788 case 'z': case 'Z':
1789 weight = CW_SpecificReg;
1790 break;
1791 case 'G':
1792 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1793 if (C->isZero()) {
1794 weight = CW_Constant;
1795 }
1796 }
1797 break;
1798 case 'I':
1799 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1800 if (isUInt<6>(C->getZExtValue())) {
1801 weight = CW_Constant;
1802 }
1803 }
1804 break;
1805 case 'J':
1806 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1807 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1808 weight = CW_Constant;
1809 }
1810 }
1811 break;
1812 case 'K':
1813 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1814 if (C->getZExtValue() == 2) {
1815 weight = CW_Constant;
1816 }
1817 }
1818 break;
1819 case 'L':
1820 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1821 if (C->getZExtValue() == 0) {
1822 weight = CW_Constant;
1823 }
1824 }
1825 break;
1826 case 'M':
1827 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1828 if (isUInt<8>(C->getZExtValue())) {
1829 weight = CW_Constant;
1830 }
1831 }
1832 break;
1833 case 'N':
1834 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1835 if (C->getSExtValue() == -1) {
1836 weight = CW_Constant;
1837 }
1838 }
1839 break;
1840 case 'O':
1841 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1842 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1843 (C->getZExtValue() == 24)) {
1844 weight = CW_Constant;
1845 }
1846 }
1847 break;
1848 case 'P':
1849 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1850 if (C->getZExtValue() == 1) {
1851 weight = CW_Constant;
1852 }
1853 }
1854 break;
1855 case 'R':
1856 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1857 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1858 weight = CW_Constant;
1859 }
1860 }
1861 break;
1862 case 'Q':
1863 weight = CW_Memory;
1864 break;
1865 }
1866
1867 return weight;
1868}
1869
1870std::pair<unsigned, const TargetRegisterClass *>
1871AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1872 StringRef Constraint,
1873 MVT VT) const {
1874 // We only support i8 and i16.
1875 //
1876 //:FIXME: remove this assert for now since it gets sometimes executed
1877 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1878
1879 if (Constraint.size() == 1) {
1880 switch (Constraint[0]) {
1881 case 'a': // Simple upper registers r16..r23.
1882 return std::make_pair(0U, &AVR::LD8loRegClass);
1883 case 'b': // Base pointer registers: y, z.
1884 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1885 case 'd': // Upper registers r16..r31.
1886 return std::make_pair(0U, &AVR::LD8RegClass);
1887 case 'l': // Lower registers r0..r15.
1888 return std::make_pair(0U, &AVR::GPR8loRegClass);
1889 case 'e': // Pointer register pairs: x, y, z.
1890 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1891 case 'q': // Stack pointer register: SPH:SPL.
1892 return std::make_pair(0U, &AVR::GPRSPRegClass);
1893 case 'r': // Any register: r0..r31.
1894 if (VT == MVT::i8)
1895 return std::make_pair(0U, &AVR::GPR8RegClass);
1896
1897 assert(VT == MVT::i16 && "inline asm constraint too large")((VT == MVT::i16 && "inline asm constraint too large"
) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i16 && \"inline asm constraint too large\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1897, __PRETTY_FUNCTION__))
;
1898 return std::make_pair(0U, &AVR::DREGSRegClass);
1899 case 't': // Temporary register: r0.
1900 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1901 case 'w': // Special upper register pairs: r24, r26, r28, r30.
1902 return std::make_pair(0U, &AVR::IWREGSRegClass);
1903 case 'x': // Pointer register pair X: r27:r26.
1904 case 'X':
1905 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1906 case 'y': // Pointer register pair Y: r29:r28.
1907 case 'Y':
1908 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1909 case 'z': // Pointer register pair Z: r31:r30.
1910 case 'Z':
1911 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1912 default:
1913 break;
1914 }
1915 }
1916
1917 return TargetLowering::getRegForInlineAsmConstraint(
1918 Subtarget.getRegisterInfo(), Constraint, VT);
1919}
1920
1921void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1922 std::string &Constraint,
1923 std::vector<SDValue> &Ops,
1924 SelectionDAG &DAG) const {
1925 SDValue Result(0, 0);
1926 SDLoc DL(Op);
1927 EVT Ty = Op.getValueType();
1928
1929 // Currently only support length 1 constraints.
1930 if (Constraint.length() != 1) {
1931 return;
1932 }
1933
1934 char ConstraintLetter = Constraint[0];
1935 switch (ConstraintLetter) {
1936 default:
1937 break;
1938 // Deal with integers first:
1939 case 'I':
1940 case 'J':
1941 case 'K':
1942 case 'L':
1943 case 'M':
1944 case 'N':
1945 case 'O':
1946 case 'P':
1947 case 'R': {
1948 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1949 if (!C) {
1950 return;
1951 }
1952
1953 int64_t CVal64 = C->getSExtValue();
1954 uint64_t CUVal64 = C->getZExtValue();
1955 switch (ConstraintLetter) {
1956 case 'I': // 0..63
1957 if (!isUInt<6>(CUVal64))
1958 return;
1959 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1960 break;
1961 case 'J': // -63..0
1962 if (CVal64 < -63 || CVal64 > 0)
1963 return;
1964 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1965 break;
1966 case 'K': // 2
1967 if (CUVal64 != 2)
1968 return;
1969 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1970 break;
1971 case 'L': // 0
1972 if (CUVal64 != 0)
1973 return;
1974 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1975 break;
1976 case 'M': // 0..255
1977 if (!isUInt<8>(CUVal64))
1978 return;
1979 // i8 type may be printed as a negative number,
1980 // e.g. 254 would be printed as -2,
1981 // so we force it to i16 at least.
1982 if (Ty.getSimpleVT() == MVT::i8) {
1983 Ty = MVT::i16;
1984 }
1985 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1986 break;
1987 case 'N': // -1
1988 if (CVal64 != -1)
1989 return;
1990 Result = DAG.getTargetConstant(CVal64, DL, Ty);
1991 break;
1992 case 'O': // 8, 16, 24
1993 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1994 return;
1995 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1996 break;
1997 case 'P': // 1
1998 if (CUVal64 != 1)
1999 return;
2000 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2001 break;
2002 case 'R': // -6..5
2003 if (CVal64 < -6 || CVal64 > 5)
2004 return;
2005 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2006 break;
2007 }
2008
2009 break;
2010 }
2011 case 'G':
2012 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2013 if (!FC || !FC->isZero())
2014 return;
2015 // Soften float to i8 0
2016 Result = DAG.getTargetConstant(0, DL, MVT::i8);
2017 break;
2018 }
2019
2020 if (Result.getNode()) {
2021 Ops.push_back(Result);
2022 return;
2023 }
2024
2025 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2026}
2027
2028Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2029 const MachineFunction &MF) const {
2030 Register Reg;
2031
2032 if (VT == LLT::scalar(8)) {
2033 Reg = StringSwitch<unsigned>(RegName)
2034 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
2035 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
2036 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
2037 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
2038 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
2039 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
2040 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
2041 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
2042 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2043 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2044 .Case("r30", AVR::R30).Case("r31", AVR::R31)
2045 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2046 .Default(0);
2047 } else {
2048 Reg = StringSwitch<unsigned>(RegName)
2049 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2050 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2051 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2052 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2053 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2054 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2055 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2056 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2057 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2058 .Default(0);
2059 }
2060
2061 if (Reg)
2062 return Reg;
2063
2064 report_fatal_error("Invalid register name global variable");
2065}
2066
2067} // end of namespace llvm

/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h

1//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of machine-level target independent types which
10// legal values in the code generator use.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H
15#define LLVM_SUPPORT_MACHINEVALUETYPE_H
16
17#include "llvm/ADT/iterator_range.h"
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Support/MathExtras.h"
20#include "llvm/Support/TypeSize.h"
21#include <cassert>
22
23namespace llvm {
24
25 class Type;
26
27 /// Machine Value Type. Every type that is supported natively by some
28 /// processor targeted by LLVM occurs here. This means that any legal value
29 /// type can be represented by an MVT.
30 class MVT {
31 public:
32 enum SimpleValueType : uint8_t {
33 // Simple value types that aren't explicitly part of this enumeration
34 // are considered extended value types.
35 INVALID_SIMPLE_VALUE_TYPE = 0,
36
37 // If you change this numbering, you must change the values in
38 // ValueTypes.td as well!
39 Other = 1, // This is a non-standard value
40 i1 = 2, // This is a 1 bit integer value
41 i8 = 3, // This is an 8 bit integer value
42 i16 = 4, // This is a 16 bit integer value
43 i32 = 5, // This is a 32 bit integer value
44 i64 = 6, // This is a 64 bit integer value
45 i128 = 7, // This is a 128 bit integer value
46
47 FIRST_INTEGER_VALUETYPE = i1,
48 LAST_INTEGER_VALUETYPE = i128,
49
50 bf16 = 8, // This is a 16 bit brain floating point value
51 f16 = 9, // This is a 16 bit floating point value
52 f32 = 10, // This is a 32 bit floating point value
53 f64 = 11, // This is a 64 bit floating point value
54 f80 = 12, // This is a 80 bit floating point value
55 f128 = 13, // This is a 128 bit floating point value
56 ppcf128 = 14, // This is a PPC 128-bit floating point value
57
58 FIRST_FP_VALUETYPE = bf16,
59 LAST_FP_VALUETYPE = ppcf128,
60
61 v1i1 = 15, // 1 x i1
62 v2i1 = 16, // 2 x i1
63 v4i1 = 17, // 4 x i1
64 v8i1 = 18, // 8 x i1
65 v16i1 = 19, // 16 x i1
66 v32i1 = 20, // 32 x i1
67 v64i1 = 21, // 64 x i1
68 v128i1 = 22, // 128 x i1
69 v256i1 = 23, // 256 x i1
70 v512i1 = 24, // 512 x i1
71 v1024i1 = 25, // 1024 x i1
72
73 v1i8 = 26, // 1 x i8
74 v2i8 = 27, // 2 x i8
75 v4i8 = 28, // 4 x i8
76 v8i8 = 29, // 8 x i8
77 v16i8 = 30, // 16 x i8
78 v32i8 = 31, // 32 x i8
79 v64i8 = 32, // 64 x i8
80 v128i8 = 33, //128 x i8
81 v256i8 = 34, //256 x i8
82
83 v1i16 = 35, // 1 x i16
84 v2i16 = 36, // 2 x i16
85 v3i16 = 37, // 3 x i16
86 v4i16 = 38, // 4 x i16
87 v8i16 = 39, // 8 x i16
88 v16i16 = 40, // 16 x i16
89 v32i16 = 41, // 32 x i16
90 v64i16 = 42, // 64 x i16
91 v128i16 = 43, //128 x i16
92
93 v1i32 = 44, // 1 x i32
94 v2i32 = 45, // 2 x i32
95 v3i32 = 46, // 3 x i32
96 v4i32 = 47, // 4 x i32
97 v5i32 = 48, // 5 x i32
98 v8i32 = 49, // 8 x i32
99 v16i32 = 50, // 16 x i32
100 v32i32 = 51, // 32 x i32
101 v64i32 = 52, // 64 x i32
102 v128i32 = 53, // 128 x i32
103 v256i32 = 54, // 256 x i32
104 v512i32 = 55, // 512 x i32
105 v1024i32 = 56, // 1024 x i32
106 v2048i32 = 57, // 2048 x i32
107
108 v1i64 = 58, // 1 x i64
109 v2i64 = 59, // 2 x i64
110 v4i64 = 60, // 4 x i64
111 v8i64 = 61, // 8 x i64
112 v16i64 = 62, // 16 x i64
113 v32i64 = 63, // 32 x i64
114 v64i64 = 64, // 64 x i64
115 v128i64 = 65, // 128 x i64
116 v256i64 = 66, // 256 x i64
117
118 v1i128 = 67, // 1 x i128
119
120 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
121 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
122
123 v2f16 = 68, // 2 x f16
124 v3f16 = 69, // 3 x f16
125 v4f16 = 70, // 4 x f16
126 v8f16 = 71, // 8 x f16
127 v16f16 = 72, // 16 x f16
128 v32f16 = 73, // 32 x f16
129 v64f16 = 74, // 64 x f16
130 v128f16 = 75, // 128 x f16
131 v2bf16 = 76, // 2 x bf16
132 v3bf16 = 77, // 3 x bf16
133 v4bf16 = 78, // 4 x bf16
134 v8bf16 = 79, // 8 x bf16
135 v16bf16 = 80, // 16 x bf16
136 v32bf16 = 81, // 32 x bf16
137 v64bf16 = 82, // 64 x bf16
138 v128bf16 = 83, // 128 x bf16
139 v1f32 = 84, // 1 x f32
140 v2f32 = 85, // 2 x f32
141 v3f32 = 86, // 3 x f32
142 v4f32 = 87, // 4 x f32
143 v5f32 = 88, // 5 x f32
144 v8f32 = 89, // 8 x f32
145 v16f32 = 90, // 16 x f32
146 v32f32 = 91, // 32 x f32
147 v64f32 = 92, // 64 x f32
148 v128f32 = 93, // 128 x f32
149 v256f32 = 94, // 256 x f32
150 v512f32 = 95, // 512 x f32
151 v1024f32 = 96, // 1024 x f32
152 v2048f32 = 97, // 2048 x f32
153 v1f64 = 98, // 1 x f64
154 v2f64 = 99, // 2 x f64
155 v4f64 = 100, // 4 x f64
156 v8f64 = 101, // 8 x f64
157 v16f64 = 102, // 16 x f64
158 v32f64 = 103, // 32 x f64
159 v64f64 = 104, // 64 x f64
160 v128f64 = 105, // 128 x f64
161 v256f64 = 106, // 256 x f64
162
163 FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v2f16,
164 LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
165
166 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
167 LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
168
169 nxv1i1 = 107, // n x 1 x i1
170 nxv2i1 = 108, // n x 2 x i1
171 nxv4i1 = 109, // n x 4 x i1
172 nxv8i1 = 110, // n x 8 x i1
173 nxv16i1 = 111, // n x 16 x i1
174 nxv32i1 = 112, // n x 32 x i1
175 nxv64i1 = 113, // n x 64 x i1
176
177 nxv1i8 = 114, // n x 1 x i8
178 nxv2i8 = 115, // n x 2 x i8
179 nxv4i8 = 116, // n x 4 x i8
180 nxv8i8 = 117, // n x 8 x i8
181 nxv16i8 = 118, // n x 16 x i8
182 nxv32i8 = 119, // n x 32 x i8
183 nxv64i8 = 120, // n x 64 x i8
184
185 nxv1i16 = 121, // n x 1 x i16
186 nxv2i16 = 122, // n x 2 x i16
187 nxv4i16 = 123, // n x 4 x i16
188 nxv8i16 = 124, // n x 8 x i16
189 nxv16i16 = 125, // n x 16 x i16
190 nxv32i16 = 126, // n x 32 x i16
191
192 nxv1i32 = 127, // n x 1 x i32
193 nxv2i32 = 128, // n x 2 x i32
194 nxv4i32 = 129, // n x 4 x i32
195 nxv8i32 = 130, // n x 8 x i32
196 nxv16i32 = 131, // n x 16 x i32
197 nxv32i32 = 132, // n x 32 x i32
198
199 nxv1i64 = 133, // n x 1 x i64
200 nxv2i64 = 134, // n x 2 x i64
201 nxv4i64 = 135, // n x 4 x i64
202 nxv8i64 = 136, // n x 8 x i64
203 nxv16i64 = 137, // n x 16 x i64
204 nxv32i64 = 138, // n x 32 x i64
205
206 FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
207 LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
208
209 nxv1f16 = 139, // n x 1 x f16
210 nxv2f16 = 140, // n x 2 x f16
211 nxv4f16 = 141, // n x 4 x f16
212 nxv8f16 = 142, // n x 8 x f16
213 nxv16f16 = 143, // n x 16 x f16
214 nxv32f16 = 144, // n x 32 x f16
215 nxv2bf16 = 145, // n x 2 x bf16
216 nxv4bf16 = 146, // n x 4 x bf16
217 nxv8bf16 = 147, // n x 8 x bf16
218 nxv1f32 = 148, // n x 1 x f32
219 nxv2f32 = 149, // n x 2 x f32
220 nxv4f32 = 150, // n x 4 x f32
221 nxv8f32 = 151, // n x 8 x f32
222 nxv16f32 = 152, // n x 16 x f32
223 nxv1f64 = 153, // n x 1 x f64
224 nxv2f64 = 154, // n x 2 x f64
225 nxv4f64 = 155, // n x 4 x f64
226 nxv8f64 = 156, // n x 8 x f64
227
228 FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
229 LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
230
231 FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
232 LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
233
234 FIRST_VECTOR_VALUETYPE = v1i1,
235 LAST_VECTOR_VALUETYPE = nxv8f64,
236
237 x86mmx = 157, // This is an X86 MMX value
238
239 Glue = 158, // This glues nodes together during pre-RA sched
240
241 isVoid = 159, // This has no value
242
243 Untyped = 160, // This value takes a register, but has
244 // unspecified type. The register class
245 // will be determined by the opcode.
246
247 funcref = 161, // WebAssembly's funcref type
248 externref = 162, // WebAssembly's externref type
249 x86amx = 163, // This is an X86 AMX value
250
251 FIRST_VALUETYPE = 1, // This is always the beginning of the list.
252 LAST_VALUETYPE = 164, // This always remains at the end of the list.
253
254 // This is the current maximum for LAST_VALUETYPE.
255 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
256 // This value must be a multiple of 32.
257 MAX_ALLOWED_VALUETYPE = 192,
258
259 // A value of type llvm::TokenTy
260 token = 248,
261
262 // This is MDNode or MDString.
263 Metadata = 249,
264
265 // An int value the size of the pointer of the current
266 // target to any address space. This must only be used internal to
267 // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR.
268 iPTRAny = 250,
269
270 // A vector with any length and element size. This is used
271 // for intrinsics that have overloadings based on vector types.
272 // This is only for tblgen's consumption!
273 vAny = 251,
274
275 // Any floating-point or vector floating-point value. This is used
276 // for intrinsics that have overloadings based on floating-point types.
277 // This is only for tblgen's consumption!
278 fAny = 252,
279
280 // An integer or vector integer value of any bit width. This is
281 // used for intrinsics that have overloadings based on integer bit widths.
282 // This is only for tblgen's consumption!
283 iAny = 253,
284
285 // An int value the size of the pointer of the current
286 // target. This should only be used internal to tblgen!
287 iPTR = 254,
288
289 // Any type. This is used for intrinsics that have overloadings.
290 // This is only for tblgen's consumption!
291 Any = 255
292 };
293
294 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;
295
296 constexpr MVT() = default;
297 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}
298
299 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
300 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
301 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
10
Assuming 'SimpleTy' is not equal to 'S.SimpleTy'
11
Returning zero, which participates in a condition later
302 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
303 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
304 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
305
306 /// Return true if this is a valid simple valuetype.
307 bool isValid() const {
308 return (SimpleTy >= MVT::FIRST_VALUETYPE &&
309 SimpleTy < MVT::LAST_VALUETYPE);
310 }
311
312 /// Return true if this is a FP or a vector FP type.
313 bool isFloatingPoint() const {
314 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
315 SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
316 (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE &&
317 SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) ||
318 (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE &&
319 SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE));
320 }
321
322 /// Return true if this is an integer or a vector integer type.
323 bool isInteger() const {
324 return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
325 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
326 (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
327 SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
328 (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
329 SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
330 }
331
332 /// Return true if this is an integer, not including vectors.
333 bool isScalarInteger() const {
334 return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
335 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
336 }
337
338 /// Return true if this is a vector value type.
339 bool isVector() const {
340 return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
341 SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
342 }
343
344 /// Return true if this is a vector value type where the
345 /// runtime length is machine dependent
346 bool isScalableVector() const {
347 return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE &&
348 SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
349 }
350
351 bool isFixedLengthVector() const {
352 return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
353 SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
354 }
355
356 /// Return true if this is a 16-bit vector type.
357 bool is16BitVector() const {
358 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 ||
359 SimpleTy == MVT::v16i1);
360 }
361
362 /// Return true if this is a 32-bit vector type.
363 bool is32BitVector() const {
364 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
365 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 ||
366 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
367 SimpleTy == MVT::v1f32);
368 }
369
370 /// Return true if this is a 64-bit vector type.
371 bool is64BitVector() const {
372 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
373 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 ||
374 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 ||
375 SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 ||
376 SimpleTy == MVT::v1f64);
377 }
378
379 /// Return true if this is a 128-bit vector type.
380 bool is128BitVector() const {
381 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 ||
382 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
383 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
384 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 ||
385 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
386 }
387
388 /// Return true if this is a 256-bit vector type.
389 bool is256BitVector() const {
390 return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
391 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
392 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
393 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 ||
394 SimpleTy == MVT::v256i1);
395 }
396
397 /// Return true if this is a 512-bit vector type.
398 bool is512BitVector() const {
399 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 ||
400 SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 ||
401 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 ||
402 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
403 SimpleTy == MVT::v8i64);
404 }
405
406 /// Return true if this is a 1024-bit vector type.
407 bool is1024BitVector() const {
408 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 ||
409 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 ||
410 SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 ||
411 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 ||
412 SimpleTy == MVT::v64bf16);
413 }
414
415 /// Return true if this is a 2048-bit vector type.
416 bool is2048BitVector() const {
417 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
418 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 ||
419 SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 ||
420 SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16);
421 }
422
423 /// Return true if this is an overloaded type for TableGen.
424 bool isOverloaded() const {
425 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
426 SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
427 SimpleTy == MVT::iPTRAny);
428 }
429
430 /// Return a vector with the same number of elements as this vector, but
431 /// with the element type converted to an integer type with the same
432 /// bitwidth.
433 MVT changeVectorElementTypeToInteger() const {
434 MVT EltTy = getVectorElementType();
435 MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits());
436 MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount());
437 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 438, __PRETTY_FUNCTION__))
438 "Simple vector VT not representable by simple integer vector VT!")((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 438, __PRETTY_FUNCTION__))
;
439 return VecTy;
440 }
441
442 /// Return a VT for a vector type whose attributes match ourselves
443 /// with the exception of the element type that is chosen by the caller.
444 MVT changeVectorElementType(MVT EltVT) const {
445 MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount());
446 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 447, __PRETTY_FUNCTION__))
447 "Simple vector VT not representable by simple integer vector VT!")((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 447, __PRETTY_FUNCTION__))
;
448 return VecTy;
449 }
450
451 /// Return the type converted to an equivalently sized integer or vector
452 /// with integer element type. Similar to changeVectorElementTypeToInteger,
453 /// but also handles scalars.
454 MVT changeTypeToInteger() {
455 if (isVector())
456 return changeVectorElementTypeToInteger();
457 return MVT::getIntegerVT(getSizeInBits());
458 }
459
460 /// Return a VT for a vector type with the same element type but
461 /// half the number of elements.
462 MVT getHalfNumVectorElementsVT() const {
463 MVT EltVT = getVectorElementType();
464 auto EltCnt = getVectorElementCount();
465 assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")((EltCnt.isKnownEven() && "Splitting vector, but not in half!"
) ? static_cast<void> (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 465, __PRETTY_FUNCTION__))
;
466 return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2));
467 }
468
469 /// Returns true if the given vector is a power of 2.
470 bool isPow2VectorType() const {
471 unsigned NElts = getVectorNumElements();
472 return !(NElts & (NElts - 1));
473 }
474
475 /// Widens the length of the given vector MVT up to the nearest power of 2
476 /// and returns that type.
477 MVT getPow2VectorType() const {
478 if (isPow2VectorType())
479 return *this;
480
481 unsigned NElts = getVectorNumElements();
482 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
483 return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
484 }
485
486 /// If this is a vector, return the element type, otherwise return this.
487 MVT getScalarType() const {
488 return isVector() ? getVectorElementType() : *this;
489 }
490
491 MVT getVectorElementType() const {
492 switch (SimpleTy) {
493 default:
494 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 494)
;
495 case v1i1:
496 case v2i1:
497 case v4i1:
498 case v8i1:
499 case v16i1:
500 case v32i1:
501 case v64i1:
502 case v128i1:
503 case v256i1:
504 case v512i1:
505 case v1024i1:
506 case nxv1i1:
507 case nxv2i1:
508 case nxv4i1:
509 case nxv8i1:
510 case nxv16i1:
511 case nxv32i1:
512 case nxv64i1: return i1;
513 case v1i8:
514 case v2i8:
515 case v4i8:
516 case v8i8:
517 case v16i8:
518 case v32i8:
519 case v64i8:
520 case v128i8:
521 case v256i8:
522 case nxv1i8:
523 case nxv2i8:
524 case nxv4i8:
525 case nxv8i8:
526 case nxv16i8:
527 case nxv32i8:
528 case nxv64i8: return i8;
529 case v1i16:
530 case v2i16:
531 case v3i16:
532 case v4i16:
533 case v8i16:
534 case v16i16:
535 case v32i16:
536 case v64i16:
537 case v128i16:
538 case nxv1i16:
539 case nxv2i16:
540 case nxv4i16:
541 case nxv8i16:
542 case nxv16i16:
543 case nxv32i16: return i16;
544 case v1i32:
545 case v2i32:
546 case v3i32:
547 case v4i32:
548 case v5i32:
549 case v8i32:
550 case v16i32:
551 case v32i32:
552 case v64i32:
553 case v128i32:
554 case v256i32:
555 case v512i32:
556 case v1024i32:
557 case v2048i32:
558 case nxv1i32:
559 case nxv2i32:
560 case nxv4i32:
561 case nxv8i32:
562 case nxv16i32:
563 case nxv32i32: return i32;
564 case v1i64:
565 case v2i64:
566 case v4i64:
567 case v8i64:
568 case v16i64:
569 case v32i64:
570 case v64i64:
571 case v128i64:
572 case v256i64:
573 case nxv1i64:
574 case nxv2i64:
575 case nxv4i64:
576 case nxv8i64:
577 case nxv16i64:
578 case nxv32i64: return i64;
579 case v1i128: return i128;
580 case v2f16:
581 case v3f16:
582 case v4f16:
583 case v8f16:
584 case v16f16:
585 case v32f16:
586 case v64f16:
587 case v128f16:
588 case nxv1f16:
589 case nxv2f16:
590 case nxv4f16:
591 case nxv8f16:
592 case nxv16f16:
593 case nxv32f16: return f16;
594 case v2bf16:
595 case v3bf16:
596 case v4bf16:
597 case v8bf16:
598 case v16bf16:
599 case v32bf16:
600 case v64bf16:
601 case v128bf16:
602 case nxv2bf16:
603 case nxv4bf16:
604 case nxv8bf16: return bf16;
605 case v1f32:
606 case v2f32:
607 case v3f32:
608 case v4f32:
609 case v5f32:
610 case v8f32:
611 case v16f32:
612 case v32f32:
613 case v64f32:
614 case v128f32:
615 case v256f32:
616 case v512f32:
617 case v1024f32:
618 case v2048f32:
619 case nxv1f32:
620 case nxv2f32:
621 case nxv4f32:
622 case nxv8f32:
623 case nxv16f32: return f32;
624 case v1f64:
625 case v2f64:
626 case v4f64:
627 case v8f64:
628 case v16f64:
629 case v32f64:
630 case v64f64:
631 case v128f64:
632 case v256f64:
633 case nxv1f64:
634 case nxv2f64:
635 case nxv4f64:
636 case nxv8f64: return f64;
637 }
638 }
639
640 unsigned getVectorNumElements() const {
641 switch (SimpleTy) {
642 default:
643 llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 643)
;
644 case v2048i32:
645 case v2048f32: return 2048;
646 case v1024i1:
647 case v1024i32:
648 case v1024f32: return 1024;
649 case v512i1:
650 case v512i32:
651 case v512f32: return 512;
652 case v256i1:
653 case v256i8:
654 case v256i32:
655 case v256i64:
656 case v256f32:
657 case v256f64: return 256;
658 case v128i1:
659 case v128i8:
660 case v128i16:
661 case v128i32:
662 case v128i64:
663 case v128f16:
664 case v128bf16:
665 case v128f32:
666 case v128f64: return 128;
667 case v64i1:
668 case v64i8:
669 case v64i16:
670 case v64i32:
671 case v64i64:
672 case v64f16:
673 case v64bf16:
674 case v64f32:
675 case v64f64:
676 case nxv64i1:
677 case nxv64i8: return 64;
678 case v32i1:
679 case v32i8:
680 case v32i16:
681 case v32i32:
682 case v32i64:
683 case v32f16:
684 case v32bf16:
685 case v32f32:
686 case v32f64:
687 case nxv32i1:
688 case nxv32i8:
689 case nxv32i16:
690 case nxv32i32:
691 case nxv32i64:
692 case nxv32f16: return 32;
693 case v16i1:
694 case v16i8:
695 case v16i16:
696 case v16i32:
697 case v16i64:
698 case v16f16:
699 case v16bf16:
700 case v16f32:
701 case v16f64:
702 case nxv16i1:
703 case nxv16i8:
704 case nxv16i16:
705 case nxv16i32:
706 case nxv16i64:
707 case nxv16f16:
708 case nxv16f32: return 16;
709 case v8i1:
710 case v8i8:
711 case v8i16:
712 case v8i32:
713 case v8i64:
714 case v8f16:
715 case v8bf16:
716 case v8f32:
717 case v8f64:
718 case nxv8i1:
719 case nxv8i8:
720 case nxv8i16:
721 case nxv8i32:
722 case nxv8i64:
723 case nxv8f16:
724 case nxv8bf16:
725 case nxv8f32:
726 case nxv8f64: return 8;
727 case v5i32:
728 case v5f32: return 5;
729 case v4i1:
730 case v4i8:
731 case v4i16:
732 case v4i32:
733 case v4i64:
734 case v4f16:
735 case v4bf16:
736 case v4f32:
737 case v4f64:
738 case nxv4i1:
739 case nxv4i8:
740 case nxv4i16:
741 case nxv4i32:
742 case nxv4i64:
743 case nxv4f16:
744 case nxv4bf16:
745 case nxv4f32:
746 case nxv4f64: return 4;
747 case v3i16:
748 case v3i32:
749 case v3f16:
750 case v3bf16:
751 case v3f32: return 3;
752 case v2i1:
753 case v2i8:
754 case v2i16:
755 case v2i32:
756 case v2i64:
757 case v2f16:
758 case v2bf16:
759 case v2f32:
760 case v2f64:
761 case nxv2i1:
762 case nxv2i8:
763 case nxv2i16:
764 case nxv2i32:
765 case nxv2i64:
766 case nxv2f16:
767 case nxv2bf16:
768 case nxv2f32:
769 case nxv2f64: return 2;
770 case v1i1:
771 case v1i8:
772 case v1i16:
773 case v1i32:
774 case v1i64:
775 case v1i128:
776 case v1f32:
777 case v1f64:
778 case nxv1i1:
779 case nxv1i8:
780 case nxv1i16:
781 case nxv1i32:
782 case nxv1i64:
783 case nxv1f16:
784 case nxv1f32:
785 case nxv1f64: return 1;
786 }
787 }
788
789 ElementCount getVectorElementCount() const {
790 return ElementCount::get(getVectorNumElements(), isScalableVector());
791 }
792
793 /// Given a vector type, return the minimum number of elements it contains.
794 unsigned getVectorMinNumElements() const {
795 return getVectorElementCount().getKnownMinValue();
796 }
797
798 /// Returns the size of the specified MVT in bits.
799 ///
800 /// If the value type is a scalable vector type, the scalable property will
801 /// be set and the runtime size will be a positive integer multiple of the
802 /// base size.
803 TypeSize getSizeInBits() const {
804 switch (SimpleTy) {
805 default:
806 llvm_unreachable("getSizeInBits called on extended MVT.")::llvm::llvm_unreachable_internal("getSizeInBits called on extended MVT."
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 806)
;
807 case Other:
808 llvm_unreachable("Value type is non-standard value, Other.")::llvm::llvm_unreachable_internal("Value type is non-standard value, Other."
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 808)
;
809 case iPTR:
810 llvm_unreachable("Value type size is target-dependent. Ask TLI.")::llvm::llvm_unreachable_internal("Value type size is target-dependent. Ask TLI."
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 810)
;
811 case iPTRAny:
812 case iAny:
813 case fAny:
814 case vAny:
815 case Any:
816 llvm_unreachable("Value type is overloaded.")::llvm::llvm_unreachable_internal("Value type is overloaded."
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 816)
;
817 case token:
818 llvm_unreachable("Token type is a sentinel that cannot be used "::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 819)
819 "in codegen and has no size")::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
"in codegen and has no size", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 819)
;
820 case Metadata:
821 llvm_unreachable("Value type is metadata.")::llvm::llvm_unreachable_internal("Value type is metadata.", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 821)
;
822 case i1:
823 case v1i1: return TypeSize::Fixed(1);
824 case nxv1i1: return TypeSize::Scalable(1);
825 case v2i1: return TypeSize::Fixed(2);
826 case nxv2i1: return TypeSize::Scalable(2);
827 case v4i1: return TypeSize::Fixed(4);
828 case nxv4i1: return TypeSize::Scalable(4);
829 case i8 :
830 case v1i8:
831 case v8i1: return TypeSize::Fixed(8);
832 case nxv1i8:
833 case nxv8i1: return TypeSize::Scalable(8);
834 case i16 :
835 case f16:
836 case bf16:
837 case v16i1:
838 case v2i8:
839 case v1i16: return TypeSize::Fixed(16);
840 case nxv16i1:
841 case nxv2i8:
842 case nxv1i16:
843 case nxv1f16: return TypeSize::Scalable(16);
844 case f32 :
845 case i32 :
846 case v32i1:
847 case v4i8:
848 case v2i16:
849 case v2f16:
850 case v2bf16:
851 case v1f32:
852 case v1i32: return TypeSize::Fixed(32);
853 case nxv32i1:
854 case nxv4i8:
855 case nxv2i16:
856 case nxv1i32:
857 case nxv2f16:
858 case nxv2bf16:
859 case nxv1f32: return TypeSize::Scalable(32);
860 case v3i16:
861 case v3f16:
862 case v3bf16: return TypeSize::Fixed(48);
863 case x86mmx:
864 case f64 :
865 case i64 :
866 case v64i1:
867 case v8i8:
868 case v4i16:
869 case v2i32:
870 case v1i64:
871 case v4f16:
872 case v4bf16:
873 case v2f32:
874 case v1f64: return TypeSize::Fixed(64);
875 case nxv64i1:
876 case nxv8i8:
877 case nxv4i16:
878 case nxv2i32:
879 case nxv1i64:
880 case nxv4f16:
881 case nxv4bf16:
882 case nxv2f32:
883 case nxv1f64: return TypeSize::Scalable(64);
884 case f80 : return TypeSize::Fixed(80);
885 case v3i32:
886 case v3f32: return TypeSize::Fixed(96);
887 case f128:
888 case ppcf128:
889 case i128:
890 case v128i1:
891 case v16i8:
892 case v8i16:
893 case v4i32:
894 case v2i64:
895 case v1i128:
896 case v8f16:
897 case v8bf16:
898 case v4f32:
899 case v2f64: return TypeSize::Fixed(128);
900 case nxv16i8:
901 case nxv8i16:
902 case nxv4i32:
903 case nxv2i64:
904 case nxv8f16:
905 case nxv8bf16:
906 case nxv4f32:
907 case nxv2f64: return TypeSize::Scalable(128);
908 case v5i32:
909 case v5f32: return TypeSize::Fixed(160);
910 case v256i1:
911 case v32i8:
912 case v16i16:
913 case v8i32:
914 case v4i64:
915 case v16f16:
916 case v16bf16:
917 case v8f32:
918 case v4f64: return TypeSize::Fixed(256);
919 case nxv32i8:
920 case nxv16i16:
921 case nxv8i32:
922 case nxv4i64:
923 case nxv16f16:
924 case nxv8f32:
925 case nxv4f64: return TypeSize::Scalable(256);
926 case v512i1:
927 case v64i8:
928 case v32i16:
929 case v16i32:
930 case v8i64:
931 case v32f16:
932 case v32bf16:
933 case v16f32:
934 case v8f64: return TypeSize::Fixed(512);
935 case nxv64i8:
936 case nxv32i16:
937 case nxv16i32:
938 case nxv8i64:
939 case nxv32f16:
940 case nxv16f32:
941 case nxv8f64: return TypeSize::Scalable(512);
942 case v1024i1:
943 case v128i8:
944 case v64i16:
945 case v32i32:
946 case v16i64:
947 case v64f16:
948 case v64bf16:
949 case v32f32:
950 case v16f64: return TypeSize::Fixed(1024);
951 case nxv32i32:
952 case nxv16i64: return TypeSize::Scalable(1024);
953 case v256i8:
954 case v128i16:
955 case v64i32:
956 case v32i64:
957 case v128f16:
958 case v128bf16:
959 case v64f32:
960 case v32f64: return TypeSize::Fixed(2048);
961 case nxv32i64: return TypeSize::Scalable(2048);
962 case v128i32:
963 case v64i64:
964 case v128f32:
965 case v64f64: return TypeSize::Fixed(4096);
966 case v256i32:
967 case v128i64:
968 case v256f32:
969 case x86amx:
970 case v128f64: return TypeSize::Fixed(8192);
971 case v512i32:
972 case v256i64:
973 case v512f32:
974 case v256f64: return TypeSize::Fixed(16384);
975 case v1024i32:
976 case v1024f32: return TypeSize::Fixed(32768);
977 case v2048i32:
978 case v2048f32: return TypeSize::Fixed(65536);
979 case funcref:
980 case externref: return TypeSize::Fixed(0); // opaque type
981 }
982 }
983
984 /// Return the size of the specified fixed width value type in bits. The
985 /// function will assert if the type is scalable.
986 uint64_t getFixedSizeInBits() const {
987 return getSizeInBits().getFixedSize();
988 }
989
990 uint64_t getScalarSizeInBits() const {
991 return getScalarType().getSizeInBits().getFixedSize();
992 }
993
994 /// Return the number of bytes overwritten by a store of the specified value
995 /// type.
996 ///
997 /// If the value type is a scalable vector type, the scalable property will
998 /// be set and the runtime size will be a positive integer multiple of the
999 /// base size.
1000 TypeSize getStoreSize() const {
1001 TypeSize BaseSize = getSizeInBits();
1002 return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
1003 }
1004
1005 /// Return the number of bits overwritten by a store of the specified value
1006 /// type.
1007 ///
1008 /// If the value type is a scalable vector type, the scalable property will
1009 /// be set and the runtime size will be a positive integer multiple of the
1010 /// base size.
1011 TypeSize getStoreSizeInBits() const {
1012 return getStoreSize() * 8;
1013 }
1014
1015 /// Returns true if the number of bits for the type is a multiple of an
1016 /// 8-bit byte.
1017 bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }
1018
1019 /// Return true if we know at compile time this has more bits than VT.
1020 bool knownBitsGT(MVT VT) const {
1021 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
1022 }
1023
1024 /// Return true if we know at compile time this has more than or the same
1025 /// bits as VT.
1026 bool knownBitsGE(MVT VT) const {
1027 return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits());
1028 }
1029
1030 /// Return true if we know at compile time this has fewer bits than VT.
1031 bool knownBitsLT(MVT VT) const {
1032 return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits());
1033 }
1034
1035 /// Return true if we know at compile time this has fewer than or the same
1036 /// bits as VT.
1037 bool knownBitsLE(MVT VT) const {
1038 return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits());
1039 }
1040
1041 /// Return true if this has more bits than VT.
1042 bool bitsGT(MVT VT) const {
1043 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1044, __PRETTY_FUNCTION__))
1044 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1044, __PRETTY_FUNCTION__))
;
1045 return knownBitsGT(VT);
1046 }
1047
1048 /// Return true if this has no less bits than VT.
1049 bool bitsGE(MVT VT) const {
1050 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1051, __PRETTY_FUNCTION__))
1051 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1051, __PRETTY_FUNCTION__))
;
1052 return knownBitsGE(VT);
1053 }
1054
1055 /// Return true if this has less bits than VT.
1056 bool bitsLT(MVT VT) const {
1057 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1058, __PRETTY_FUNCTION__))
1058 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1058, __PRETTY_FUNCTION__))
;
1059 return knownBitsLT(VT);
1060 }
1061
1062 /// Return true if this has no more bits than VT.
1063 bool bitsLE(MVT VT) const {
1064 assert(isScalableVector() == VT.isScalableVector() &&((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1065, __PRETTY_FUNCTION__))
1065 "Comparison between scalable and fixed types")((isScalableVector() == VT.isScalableVector() && "Comparison between scalable and fixed types"
) ? static_cast<void> (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1065, __PRETTY_FUNCTION__))
;
1066 return knownBitsLE(VT);
1067 }
1068
1069 static MVT getFloatingPointVT(unsigned BitWidth) {
1070 switch (BitWidth) {
1071 default:
1072 llvm_unreachable("Bad bit width!")::llvm::llvm_unreachable_internal("Bad bit width!", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1072)
;
1073 case 16:
1074 return MVT::f16;
1075 case 32:
1076 return MVT::f32;
1077 case 64:
1078 return MVT::f64;
1079 case 80:
1080 return MVT::f80;
1081 case 128:
1082 return MVT::f128;
1083 }
1084 }
1085
1086 static MVT getIntegerVT(unsigned BitWidth) {
1087 switch (BitWidth) {
1088 default:
1089 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1090 case 1:
1091 return MVT::i1;
1092 case 8:
1093 return MVT::i8;
1094 case 16:
1095 return MVT::i16;
1096 case 32:
1097 return MVT::i32;
1098 case 64:
1099 return MVT::i64;
1100 case 128:
1101 return MVT::i128;
1102 }
1103 }
1104
1105 static MVT getVectorVT(MVT VT, unsigned NumElements) {
1106 switch (VT.SimpleTy) {
1107 default:
1108 break;
1109 case MVT::i1:
1110 if (NumElements == 1) return MVT::v1i1;
1111 if (NumElements == 2) return MVT::v2i1;
1112 if (NumElements == 4) return MVT::v4i1;
1113 if (NumElements == 8) return MVT::v8i1;
1114 if (NumElements == 16) return MVT::v16i1;
1115 if (NumElements == 32) return MVT::v32i1;
1116 if (NumElements == 64) return MVT::v64i1;
1117 if (NumElements == 128) return MVT::v128i1;
1118 if (NumElements == 256) return MVT::v256i1;
1119 if (NumElements == 512) return MVT::v512i1;
1120 if (NumElements == 1024) return MVT::v1024i1;
1121 break;
1122 case MVT::i8:
1123 if (NumElements == 1) return MVT::v1i8;
1124 if (NumElements == 2) return MVT::v2i8;
1125 if (NumElements == 4) return MVT::v4i8;
1126 if (NumElements == 8) return MVT::v8i8;
1127 if (NumElements == 16) return MVT::v16i8;
1128 if (NumElements == 32) return MVT::v32i8;
1129 if (NumElements == 64) return MVT::v64i8;
1130 if (NumElements == 128) return MVT::v128i8;
1131 if (NumElements == 256) return MVT::v256i8;
1132 break;
1133 case MVT::i16:
1134 if (NumElements == 1) return MVT::v1i16;
1135 if (NumElements == 2) return MVT::v2i16;
1136 if (NumElements == 3) return MVT::v3i16;
1137 if (NumElements == 4) return MVT::v4i16;
1138 if (NumElements == 8) return MVT::v8i16;
1139 if (NumElements == 16) return MVT::v16i16;
1140 if (NumElements == 32) return MVT::v32i16;
1141 if (NumElements == 64) return MVT::v64i16;
1142 if (NumElements == 128) return MVT::v128i16;
1143 break;
1144 case MVT::i32:
1145 if (NumElements == 1) return MVT::v1i32;
1146 if (NumElements == 2) return MVT::v2i32;
1147 if (NumElements == 3) return MVT::v3i32;
1148 if (NumElements == 4) return MVT::v4i32;
1149 if (NumElements == 5) return MVT::v5i32;
1150 if (NumElements == 8) return MVT::v8i32;
1151 if (NumElements == 16) return MVT::v16i32;
1152 if (NumElements == 32) return MVT::v32i32;
1153 if (NumElements == 64) return MVT::v64i32;
1154 if (NumElements == 128) return MVT::v128i32;
1155 if (NumElements == 256) return MVT::v256i32;
1156 if (NumElements == 512) return MVT::v512i32;
1157 if (NumElements == 1024) return MVT::v1024i32;
1158 if (NumElements == 2048) return MVT::v2048i32;
1159 break;
1160 case MVT::i64:
1161 if (NumElements == 1) return MVT::v1i64;
1162 if (NumElements == 2) return MVT::v2i64;
1163 if (NumElements == 4) return MVT::v4i64;
1164 if (NumElements == 8) return MVT::v8i64;
1165 if (NumElements == 16) return MVT::v16i64;
1166 if (NumElements == 32) return MVT::v32i64;
1167 if (NumElements == 64) return MVT::v64i64;
1168 if (NumElements == 128) return MVT::v128i64;
1169 if (NumElements == 256) return MVT::v256i64;
1170 break;
1171 case MVT::i128:
1172 if (NumElements == 1) return MVT::v1i128;
1173 break;
1174 case MVT::f16:
1175 if (NumElements == 2) return MVT::v2f16;
1176 if (NumElements == 3) return MVT::v3f16;
1177 if (NumElements == 4) return MVT::v4f16;
1178 if (NumElements == 8) return MVT::v8f16;
1179 if (NumElements == 16) return MVT::v16f16;
1180 if (NumElements == 32) return MVT::v32f16;
1181 if (NumElements == 64) return MVT::v64f16;
1182 if (NumElements == 128) return MVT::v128f16;
1183 break;
1184 case MVT::bf16:
1185 if (NumElements == 2) return MVT::v2bf16;
1186 if (NumElements == 3) return MVT::v3bf16;
1187 if (NumElements == 4) return MVT::v4bf16;
1188 if (NumElements == 8) return MVT::v8bf16;
1189 if (NumElements == 16) return MVT::v16bf16;
1190 if (NumElements == 32) return MVT::v32bf16;
1191 if (NumElements == 64) return MVT::v64bf16;
1192 if (NumElements == 128) return MVT::v128bf16;
1193 break;
1194 case MVT::f32:
1195 if (NumElements == 1) return MVT::v1f32;
1196 if (NumElements == 2) return MVT::v2f32;
1197 if (NumElements == 3) return MVT::v3f32;
1198 if (NumElements == 4) return MVT::v4f32;
1199 if (NumElements == 5) return MVT::v5f32;
1200 if (NumElements == 8) return MVT::v8f32;
1201 if (NumElements == 16) return MVT::v16f32;
1202 if (NumElements == 32) return MVT::v32f32;
1203 if (NumElements == 64) return MVT::v64f32;
1204 if (NumElements == 128) return MVT::v128f32;
1205 if (NumElements == 256) return MVT::v256f32;
1206 if (NumElements == 512) return MVT::v512f32;
1207 if (NumElements == 1024) return MVT::v1024f32;
1208 if (NumElements == 2048) return MVT::v2048f32;
1209 break;
1210 case MVT::f64:
1211 if (NumElements == 1) return MVT::v1f64;
1212 if (NumElements == 2) return MVT::v2f64;
1213 if (NumElements == 4) return MVT::v4f64;
1214 if (NumElements == 8) return MVT::v8f64;
1215 if (NumElements == 16) return MVT::v16f64;
1216 if (NumElements == 32) return MVT::v32f64;
1217 if (NumElements == 64) return MVT::v64f64;
1218 if (NumElements == 128) return MVT::v128f64;
1219 if (NumElements == 256) return MVT::v256f64;
1220 break;
1221 }
1222 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1223 }
1224
1225 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
1226 switch(VT.SimpleTy) {
1227 default:
1228 break;
1229 case MVT::i1:
1230 if (NumElements == 1) return MVT::nxv1i1;
1231 if (NumElements == 2) return MVT::nxv2i1;
1232 if (NumElements == 4) return MVT::nxv4i1;
1233 if (NumElements == 8) return MVT::nxv8i1;
1234 if (NumElements == 16) return MVT::nxv16i1;
1235 if (NumElements == 32) return MVT::nxv32i1;
1236 if (NumElements == 64) return MVT::nxv64i1;
1237 break;
1238 case MVT::i8:
1239 if (NumElements == 1) return MVT::nxv1i8;
1240 if (NumElements == 2) return MVT::nxv2i8;
1241 if (NumElements == 4) return MVT::nxv4i8;
1242 if (NumElements == 8) return MVT::nxv8i8;
1243 if (NumElements == 16) return MVT::nxv16i8;
1244 if (NumElements == 32) return MVT::nxv32i8;
1245 if (NumElements == 64) return MVT::nxv64i8;
1246 break;
1247 case MVT::i16:
1248 if (NumElements == 1) return MVT::nxv1i16;
1249 if (NumElements == 2) return MVT::nxv2i16;
1250 if (NumElements == 4) return MVT::nxv4i16;
1251 if (NumElements == 8) return MVT::nxv8i16;
1252 if (NumElements == 16) return MVT::nxv16i16;
1253 if (NumElements == 32) return MVT::nxv32i16;
1254 break;
1255 case MVT::i32:
1256 if (NumElements == 1) return MVT::nxv1i32;
1257 if (NumElements == 2) return MVT::nxv2i32;
1258 if (NumElements == 4) return MVT::nxv4i32;
1259 if (NumElements == 8) return MVT::nxv8i32;
1260 if (NumElements == 16) return MVT::nxv16i32;
1261 if (NumElements == 32) return MVT::nxv32i32;
1262 break;
1263 case MVT::i64:
1264 if (NumElements == 1) return MVT::nxv1i64;
1265 if (NumElements == 2) return MVT::nxv2i64;
1266 if (NumElements == 4) return MVT::nxv4i64;
1267 if (NumElements == 8) return MVT::nxv8i64;
1268 if (NumElements == 16) return MVT::nxv16i64;
1269 if (NumElements == 32) return MVT::nxv32i64;
1270 break;
1271 case MVT::f16:
1272 if (NumElements == 1) return MVT::nxv1f16;
1273 if (NumElements == 2) return MVT::nxv2f16;
1274 if (NumElements == 4) return MVT::nxv4f16;
1275 if (NumElements == 8) return MVT::nxv8f16;
1276 if (NumElements == 16) return MVT::nxv16f16;
1277 if (NumElements == 32) return MVT::nxv32f16;
1278 break;
1279 case MVT::bf16:
1280 if (NumElements == 2) return MVT::nxv2bf16;
1281 if (NumElements == 4) return MVT::nxv4bf16;
1282 if (NumElements == 8) return MVT::nxv8bf16;
1283 break;
1284 case MVT::f32:
1285 if (NumElements == 1) return MVT::nxv1f32;
1286 if (NumElements == 2) return MVT::nxv2f32;
1287 if (NumElements == 4) return MVT::nxv4f32;
1288 if (NumElements == 8) return MVT::nxv8f32;
1289 if (NumElements == 16) return MVT::nxv16f32;
1290 break;
1291 case MVT::f64:
1292 if (NumElements == 1) return MVT::nxv1f64;
1293 if (NumElements == 2) return MVT::nxv2f64;
1294 if (NumElements == 4) return MVT::nxv4f64;
1295 if (NumElements == 8) return MVT::nxv8f64;
1296 break;
1297 }
1298 return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
1299 }
1300
1301 static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
1302 if (IsScalable)
1303 return getScalableVectorVT(VT, NumElements);
1304 return getVectorVT(VT, NumElements);
1305 }
1306
1307 static MVT getVectorVT(MVT VT, ElementCount EC) {
1308 if (EC.isScalable())
1309 return getScalableVectorVT(VT, EC.getKnownMinValue());
1310 return getVectorVT(VT, EC.getKnownMinValue());
1311 }
1312
1313 /// Return the value type corresponding to the specified type. This returns
1314 /// all pointers as iPTR. If HandleUnknown is true, unknown types are
1315 /// returned as Other, otherwise they are invalid.
1316 static MVT getVT(Type *Ty, bool HandleUnknown = false);
1317
1318 private:
1319 /// A simple iterator over the MVT::SimpleValueType enum.
1320 struct mvt_iterator {
1321 SimpleValueType VT;
1322
1323 mvt_iterator(SimpleValueType VT) : VT(VT) {}
1324
1325 MVT operator*() const { return VT; }
1326 bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; }
1327
1328 mvt_iterator& operator++() {
1329 VT = (MVT::SimpleValueType)((int)VT + 1);
1330 assert((int)VT <= MVT::MAX_ALLOWED_VALUETYPE &&(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1331, __PRETTY_FUNCTION__))
1331 "MVT iterator overflowed.")(((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && "MVT iterator overflowed."
) ? static_cast<void> (0) : __assert_fail ("(int)VT <= MVT::MAX_ALLOWED_VALUETYPE && \"MVT iterator overflowed.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include/llvm/Support/MachineValueType.h"
, 1331, __PRETTY_FUNCTION__))
;
1332 return *this;
1333 }
1334 };
1335
1336 /// A range of the MVT::SimpleValueType enum.
1337 using mvt_range = iterator_range<mvt_iterator>;
1338
1339 public:
1340 /// SimpleValueType Iteration
1341 /// @{
1342 static mvt_range all_valuetypes() {
1343 return mvt_range(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE);
1344 }
1345
1346 static mvt_range integer_valuetypes() {
1347 return mvt_range(MVT::FIRST_INTEGER_VALUETYPE,
1348 (MVT::SimpleValueType)(MVT::LAST_INTEGER_VALUETYPE + 1));
1349 }
1350
1351 static mvt_range fp_valuetypes() {
1352 return mvt_range(MVT::FIRST_FP_VALUETYPE,
1353 (MVT::SimpleValueType)(MVT::LAST_FP_VALUETYPE + 1));
1354 }
1355
1356 static mvt_range vector_valuetypes() {
1357 return mvt_range(MVT::FIRST_VECTOR_VALUETYPE,
1358 (MVT::SimpleValueType)(MVT::LAST_VECTOR_VALUETYPE + 1));
1359 }
1360
1361 static mvt_range fixedlen_vector_valuetypes() {
1362 return mvt_range(
1363 MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE,
1364 (MVT::SimpleValueType)(MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE + 1));
1365 }
1366
1367 static mvt_range scalable_vector_valuetypes() {
1368 return mvt_range(
1369 MVT::FIRST_SCALABLE_VECTOR_VALUETYPE,
1370 (MVT::SimpleValueType)(MVT::LAST_SCALABLE_VECTOR_VALUETYPE + 1));
1371 }
1372
1373 static mvt_range integer_fixedlen_vector_valuetypes() {
1374 return mvt_range(
1375 MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
1376 (MVT::SimpleValueType)(MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE + 1));
1377 }
1378
1379 static mvt_range fp_fixedlen_vector_valuetypes() {
1380 return mvt_range(
1381 MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE,
1382 (MVT::SimpleValueType)(MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE + 1));
1383 }
1384
1385 static mvt_range integer_scalable_vector_valuetypes() {
1386 return mvt_range(
1387 MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
1388 (MVT::SimpleValueType)(MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE + 1));
1389 }
1390
1391 static mvt_range fp_scalable_vector_valuetypes() {
1392 return mvt_range(
1393 MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
1394 (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE + 1));
1395 }
1396 /// @}
1397 };
1398
1399} // end namespace llvm
1400
1401#endif // LLVM_CODEGEN_MACHINEVALUETYPE_H