clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/AVR -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/AVR -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/AVR -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/AVR/AVRISelLowering.cpp
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | |
14 | #include "AVRISelLowering.h" |
15 | |
16 | #include "llvm/ADT/StringSwitch.h" |
17 | #include "llvm/ADT/STLExtras.h" |
18 | #include "llvm/CodeGen/CallingConvLower.h" |
19 | #include "llvm/CodeGen/MachineFrameInfo.h" |
20 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
21 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
22 | #include "llvm/CodeGen/SelectionDAG.h" |
23 | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" |
24 | #include "llvm/IR/Function.h" |
25 | #include "llvm/Support/ErrorHandling.h" |
26 | |
27 | #include "AVR.h" |
28 | #include "AVRMachineFunctionInfo.h" |
29 | #include "AVRSubtarget.h" |
30 | #include "AVRTargetMachine.h" |
31 | #include "MCTargetDesc/AVRMCTargetDesc.h" |
32 | |
33 | namespace llvm { |
34 | |
35 | AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM, |
36 | const AVRSubtarget &STI) |
37 | : TargetLowering(TM), Subtarget(STI) { |
38 | |
39 | addRegisterClass(MVT::i8, &AVR::GPR8RegClass); |
40 | addRegisterClass(MVT::i16, &AVR::DREGSRegClass); |
41 | |
42 | |
43 | computeRegisterProperties(Subtarget.getRegisterInfo()); |
44 | |
45 | setBooleanContents(ZeroOrOneBooleanContent); |
46 | setBooleanVectorContents(ZeroOrOneBooleanContent); |
47 | setSchedulingPreference(Sched::RegPressure); |
48 | setStackPointerRegisterToSaveRestore(AVR::SP); |
49 | setSupportsUnalignedAtomics(true); |
50 | |
51 | setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); |
52 | setOperationAction(ISD::BlockAddress, MVT::i16, Custom); |
53 | |
54 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
55 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
56 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); |
57 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); |
58 | |
59 | for (MVT VT : MVT::integer_valuetypes()) { |
60 | for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { |
61 | setLoadExtAction(N, VT, MVT::i1, Promote); |
62 | setLoadExtAction(N, VT, MVT::i8, Expand); |
63 | } |
64 | } |
65 | |
66 | setTruncStoreAction(MVT::i16, MVT::i8, Expand); |
67 | |
68 | for (MVT VT : MVT::integer_valuetypes()) { |
69 | setOperationAction(ISD::ADDC, VT, Legal); |
70 | setOperationAction(ISD::SUBC, VT, Legal); |
71 | setOperationAction(ISD::ADDE, VT, Legal); |
72 | setOperationAction(ISD::SUBE, VT, Legal); |
73 | } |
74 | |
75 | |
76 | |
77 | setOperationAction(ISD::ADD, MVT::i32, Custom); |
78 | setOperationAction(ISD::ADD, MVT::i64, Custom); |
79 | |
80 | |
81 | |
82 | setOperationAction(ISD::SRA, MVT::i8, Custom); |
83 | setOperationAction(ISD::SHL, MVT::i8, Custom); |
84 | setOperationAction(ISD::SRL, MVT::i8, Custom); |
85 | setOperationAction(ISD::SRA, MVT::i16, Custom); |
86 | setOperationAction(ISD::SHL, MVT::i16, Custom); |
87 | setOperationAction(ISD::SRL, MVT::i16, Custom); |
88 | setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); |
89 | setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); |
90 | setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); |
91 | |
92 | setOperationAction(ISD::ROTL, MVT::i8, Custom); |
93 | setOperationAction(ISD::ROTL, MVT::i16, Expand); |
94 | setOperationAction(ISD::ROTR, MVT::i8, Custom); |
95 | setOperationAction(ISD::ROTR, MVT::i16, Expand); |
96 | |
97 | setOperationAction(ISD::BR_CC, MVT::i8, Custom); |
98 | setOperationAction(ISD::BR_CC, MVT::i16, Custom); |
99 | setOperationAction(ISD::BR_CC, MVT::i32, Custom); |
100 | setOperationAction(ISD::BR_CC, MVT::i64, Custom); |
101 | setOperationAction(ISD::BRCOND, MVT::Other, Expand); |
102 | |
103 | setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); |
104 | setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); |
105 | setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); |
106 | setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); |
107 | setOperationAction(ISD::SETCC, MVT::i8, Custom); |
108 | setOperationAction(ISD::SETCC, MVT::i16, Custom); |
109 | setOperationAction(ISD::SETCC, MVT::i32, Custom); |
110 | setOperationAction(ISD::SETCC, MVT::i64, Custom); |
111 | setOperationAction(ISD::SELECT, MVT::i8, Expand); |
112 | setOperationAction(ISD::SELECT, MVT::i16, Expand); |
113 | |
114 | setOperationAction(ISD::BSWAP, MVT::i16, Expand); |
115 | |
116 | |
117 | setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); |
118 | setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); |
119 | setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); |
120 | setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); |
121 | setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); |
122 | setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); |
123 | setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); |
124 | setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); |
125 | |
126 | setOperationAction(ISD::BR_JT, MVT::Other, Expand); |
127 | |
128 | setOperationAction(ISD::VASTART, MVT::Other, Custom); |
129 | setOperationAction(ISD::VAEND, MVT::Other, Expand); |
130 | setOperationAction(ISD::VAARG, MVT::Other, Expand); |
131 | setOperationAction(ISD::VACOPY, MVT::Other, Expand); |
132 | |
133 | |
134 | for (MVT VT : MVT::integer_valuetypes()) { |
135 | setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); |
136 | setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); |
137 | setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); |
138 | setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); |
139 | setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); |
140 | setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); |
141 | setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); |
142 | } |
143 | |
144 | |
145 | setOperationAction(ISD::UDIV, MVT::i8, Expand); |
146 | setOperationAction(ISD::UDIV, MVT::i16, Expand); |
147 | setOperationAction(ISD::UREM, MVT::i8, Expand); |
148 | setOperationAction(ISD::UREM, MVT::i16, Expand); |
149 | setOperationAction(ISD::SDIV, MVT::i8, Expand); |
150 | setOperationAction(ISD::SDIV, MVT::i16, Expand); |
151 | setOperationAction(ISD::SREM, MVT::i8, Expand); |
152 | setOperationAction(ISD::SREM, MVT::i16, Expand); |
153 | |
154 | |
155 | setOperationAction(ISD::UDIVREM, MVT::i8, Custom); |
156 | setOperationAction(ISD::UDIVREM, MVT::i16, Custom); |
157 | setOperationAction(ISD::UDIVREM, MVT::i32, Custom); |
158 | setOperationAction(ISD::SDIVREM, MVT::i8, Custom); |
159 | setOperationAction(ISD::SDIVREM, MVT::i16, Custom); |
160 | setOperationAction(ISD::SDIVREM, MVT::i32, Custom); |
161 | |
162 | |
163 | setOperationAction(ISD::MUL, MVT::i8, Expand); |
164 | setOperationAction(ISD::MUL, MVT::i16, Expand); |
165 | |
166 | |
167 | setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); |
168 | setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); |
169 | |
170 | |
171 | |
172 | if (!Subtarget.supportsMultiplication()) { |
173 | setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); |
174 | setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); |
175 | } |
176 | |
177 | for (MVT VT : MVT::integer_valuetypes()) { |
178 | setOperationAction(ISD::MULHS, VT, Expand); |
179 | setOperationAction(ISD::MULHU, VT, Expand); |
180 | } |
181 | |
182 | for (MVT VT : MVT::integer_valuetypes()) { |
183 | setOperationAction(ISD::CTPOP, VT, Expand); |
184 | setOperationAction(ISD::CTLZ, VT, Expand); |
185 | setOperationAction(ISD::CTTZ, VT, Expand); |
186 | } |
187 | |
188 | for (MVT VT : MVT::integer_valuetypes()) { |
189 | setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); |
190 | |
191 | |
192 | |
193 | |
194 | } |
195 | |
196 | |
197 | setLibcallName(RTLIB::SDIV_I8, nullptr); |
198 | setLibcallName(RTLIB::SDIV_I16, nullptr); |
199 | setLibcallName(RTLIB::SDIV_I32, nullptr); |
200 | setLibcallName(RTLIB::UDIV_I8, nullptr); |
201 | setLibcallName(RTLIB::UDIV_I16, nullptr); |
202 | setLibcallName(RTLIB::UDIV_I32, nullptr); |
203 | |
204 | |
205 | setLibcallName(RTLIB::SREM_I8, nullptr); |
206 | setLibcallName(RTLIB::SREM_I16, nullptr); |
207 | setLibcallName(RTLIB::SREM_I32, nullptr); |
208 | setLibcallName(RTLIB::UREM_I8, nullptr); |
209 | setLibcallName(RTLIB::UREM_I16, nullptr); |
210 | setLibcallName(RTLIB::UREM_I32, nullptr); |
211 | |
212 | |
213 | setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4"); |
214 | setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4"); |
215 | setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); |
216 | setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4"); |
217 | setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4"); |
218 | setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); |
219 | |
220 | |
221 | setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN); |
222 | setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN); |
223 | setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN); |
224 | setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN); |
225 | |
226 | |
227 | setLibcallName(RTLIB::SIN_F32, "sin"); |
228 | setLibcallName(RTLIB::COS_F32, "cos"); |
229 | |
230 | setMinFunctionAlignment(Align(2)); |
231 | setMinimumJumpTableEntries(UINT_MAX); |
232 | } |
233 | |
234 | const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { |
235 | #define NODE(name) \ |
236 | case AVRISD::name: \ |
237 | return #name |
238 | |
239 | switch (Opcode) { |
240 | default: |
241 | return nullptr; |
242 | NODE(RET_FLAG); |
243 | NODE(RETI_FLAG); |
244 | NODE(CALL); |
245 | NODE(WRAPPER); |
246 | NODE(LSL); |
247 | NODE(LSR); |
248 | NODE(ROL); |
249 | NODE(ROR); |
250 | NODE(ASR); |
251 | NODE(LSLLOOP); |
252 | NODE(LSRLOOP); |
253 | NODE(ROLLOOP); |
254 | NODE(RORLOOP); |
255 | NODE(ASRLOOP); |
256 | NODE(BRCOND); |
257 | NODE(CMP); |
258 | NODE(CMPC); |
259 | NODE(TST); |
260 | NODE(SELECT_CC); |
261 | #undef NODE |
262 | } |
263 | } |
264 | |
265 | EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, |
266 | EVT VT) const { |
267 | assert(!VT.isVector() && "No AVR SetCC type for vectors!"); |
268 | return MVT::i8; |
269 | } |
270 | |
271 | SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { |
272 | |
273 | |
274 | unsigned Opc8; |
275 | const SDNode *N = Op.getNode(); |
276 | EVT VT = Op.getValueType(); |
277 | SDLoc dl(N); |
278 | assert(isPowerOf2_32(VT.getSizeInBits()) && |
279 | "Expected power-of-2 shift amount"); |
280 | |
281 | |
282 | if (!isa<ConstantSDNode>(N->getOperand(1))) { |
283 | switch (Op.getOpcode()) { |
284 | default: |
285 | llvm_unreachable("Invalid shift opcode!"); |
286 | case ISD::SHL: |
287 | return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), |
288 | N->getOperand(1)); |
289 | case ISD::SRL: |
290 | return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), |
291 | N->getOperand(1)); |
292 | case ISD::ROTL: { |
293 | SDValue Amt = N->getOperand(1); |
294 | EVT AmtVT = Amt.getValueType(); |
295 | Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, |
296 | DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); |
297 | return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); |
298 | } |
299 | case ISD::ROTR: { |
300 | SDValue Amt = N->getOperand(1); |
301 | EVT AmtVT = Amt.getValueType(); |
302 | Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, |
303 | DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); |
304 | return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); |
305 | } |
306 | case ISD::SRA: |
307 | return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), |
308 | N->getOperand(1)); |
309 | } |
310 | } |
311 | |
312 | uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); |
313 | SDValue Victim = N->getOperand(0); |
314 | |
315 | switch (Op.getOpcode()) { |
316 | case ISD::SRA: |
317 | Opc8 = AVRISD::ASR; |
318 | break; |
319 | case ISD::ROTL: |
320 | Opc8 = AVRISD::ROL; |
321 | ShiftAmount = ShiftAmount % VT.getSizeInBits(); |
322 | break; |
323 | case ISD::ROTR: |
324 | Opc8 = AVRISD::ROR; |
325 | ShiftAmount = ShiftAmount % VT.getSizeInBits(); |
326 | break; |
327 | case ISD::SRL: |
328 | Opc8 = AVRISD::LSR; |
329 | break; |
330 | case ISD::SHL: |
331 | Opc8 = AVRISD::LSL; |
332 | break; |
333 | default: |
334 | llvm_unreachable("Invalid shift opcode"); |
335 | } |
336 | |
337 | |
338 | if (VT.getSizeInBits() == 8) { |
339 | if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { |
340 | |
341 | Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); |
342 | Victim = |
343 | DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); |
344 | ShiftAmount -= 4; |
345 | } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && |
346 | ShiftAmount < 7) { |
347 | |
348 | Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); |
349 | Victim = |
350 | DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); |
351 | ShiftAmount -= 4; |
352 | } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { |
353 | |
354 | Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, |
355 | DAG.getConstant(7, dl, VT)); |
356 | ShiftAmount = 0; |
357 | } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { |
358 | |
359 | Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, |
360 | DAG.getConstant(7, dl, VT)); |
361 | ShiftAmount = 0; |
362 | } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { |
363 | |
364 | Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, |
365 | DAG.getConstant(7, dl, VT)); |
366 | ShiftAmount = 0; |
367 | } |
368 | } else if (VT.getSizeInBits() == 16) { |
369 | if (4 <= ShiftAmount && ShiftAmount < 8) |
370 | switch (Op.getOpcode()) { |
371 | case ISD::SHL: |
372 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, |
373 | DAG.getConstant(4, dl, VT)); |
374 | ShiftAmount -= 4; |
375 | break; |
376 | case ISD::SRL: |
377 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, |
378 | DAG.getConstant(4, dl, VT)); |
379 | ShiftAmount -= 4; |
380 | break; |
381 | default: |
382 | break; |
383 | } |
384 | else if (8 <= ShiftAmount && ShiftAmount < 12) |
385 | switch (Op.getOpcode()) { |
386 | case ISD::SHL: |
387 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, |
388 | DAG.getConstant(8, dl, VT)); |
389 | ShiftAmount -= 8; |
390 | break; |
391 | case ISD::SRL: |
392 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, |
393 | DAG.getConstant(8, dl, VT)); |
394 | ShiftAmount -= 8; |
395 | break; |
396 | case ISD::SRA: |
397 | Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, |
398 | DAG.getConstant(8, dl, VT)); |
399 | ShiftAmount -= 8; |
400 | break; |
401 | default: |
402 | break; |
403 | } |
404 | else if (12 <= ShiftAmount) |
405 | switch (Op.getOpcode()) { |
406 | case ISD::SHL: |
407 | Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, |
408 | DAG.getConstant(12, dl, VT)); |
409 | ShiftAmount -= 12; |
410 | break; |
411 | case ISD::SRL: |
412 | Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, |
413 | DAG.getConstant(12, dl, VT)); |
414 | ShiftAmount -= 12; |
415 | break; |
416 | default: |
417 | break; |
418 | } |
419 | } |
420 | |
421 | while (ShiftAmount--) { |
422 | Victim = DAG.getNode(Opc8, dl, VT, Victim); |
423 | } |
424 | |
425 | return Victim; |
426 | } |
427 | |
428 | SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { |
429 | unsigned Opcode = Op->getOpcode(); |
430 | assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && |
431 | "Invalid opcode for Div/Rem lowering"); |
432 | bool IsSigned = (Opcode == ISD::SDIVREM); |
433 | EVT VT = Op->getValueType(0); |
434 | Type *Ty = VT.getTypeForEVT(*DAG.getContext()); |
435 | |
436 | RTLIB::Libcall LC; |
437 | switch (VT.getSimpleVT().SimpleTy) { |
438 | default: |
439 | llvm_unreachable("Unexpected request for libcall!"); |
440 | case MVT::i8: |
441 | LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; |
442 | break; |
443 | case MVT::i16: |
444 | LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; |
445 | break; |
446 | case MVT::i32: |
447 | LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; |
448 | break; |
449 | } |
450 | |
451 | SDValue InChain = DAG.getEntryNode(); |
452 | |
453 | TargetLowering::ArgListTy Args; |
454 | TargetLowering::ArgListEntry Entry; |
455 | for (SDValue const &Value : Op->op_values()) { |
456 | Entry.Node = Value; |
457 | Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); |
458 | Entry.IsSExt = IsSigned; |
459 | Entry.IsZExt = !IsSigned; |
460 | Args.push_back(Entry); |
461 | } |
462 | |
463 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), |
464 | getPointerTy(DAG.getDataLayout())); |
465 | |
466 | Type *RetTy = (Type *)StructType::get(Ty, Ty); |
467 | |
468 | SDLoc dl(Op); |
469 | TargetLowering::CallLoweringInfo CLI(DAG); |
470 | CLI.setDebugLoc(dl) |
471 | .setChain(InChain) |
472 | .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) |
473 | .setInRegister() |
474 | .setSExtResult(IsSigned) |
475 | .setZExtResult(!IsSigned); |
476 | |
477 | std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); |
478 | return CallInfo.first; |
479 | } |
480 | |
481 | SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op, |
482 | SelectionDAG &DAG) const { |
483 | auto DL = DAG.getDataLayout(); |
484 | |
485 | const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); |
486 | int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); |
487 | |
488 | |
489 | SDValue Result = |
490 | DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset); |
491 | return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); |
492 | } |
493 | |
494 | SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op, |
495 | SelectionDAG &DAG) const { |
496 | auto DL = DAG.getDataLayout(); |
497 | const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); |
498 | |
499 | SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL)); |
500 | |
501 | return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); |
502 | } |
503 | |
504 | |
505 | static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { |
506 | switch (CC) { |
507 | default: |
508 | llvm_unreachable("Unknown condition code!"); |
509 | case ISD::SETEQ: |
510 | return AVRCC::COND_EQ; |
511 | case ISD::SETNE: |
512 | return AVRCC::COND_NE; |
513 | case ISD::SETGE: |
514 | return AVRCC::COND_GE; |
515 | case ISD::SETLT: |
516 | return AVRCC::COND_LT; |
517 | case ISD::SETUGE: |
518 | return AVRCC::COND_SH; |
519 | case ISD::SETULT: |
520 | return AVRCC::COND_LO; |
521 | } |
522 | } |
523 | |
524 | |
525 | SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, |
526 | SelectionDAG &DAG, SDLoc DL) const { |
527 | assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) && |
528 | "LHS and RHS have different types"); |
529 | assert(((LHS.getSimpleValueType() == MVT::i16) || |
530 | (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type"); |
531 | |
532 | SDValue Cmp; |
533 | |
534 | if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) { |
535 | |
536 | SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, |
537 | DAG.getIntPtrConstant(0, DL)); |
538 | SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, |
539 | DAG.getIntPtrConstant(1, DL)); |
540 | SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, |
541 | DAG.getIntPtrConstant(0, DL)); |
542 | SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, |
543 | DAG.getIntPtrConstant(1, DL)); |
544 | Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo); |
545 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); |
546 | } else { |
547 | |
548 | Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS); |
549 | } |
550 | |
551 | return Cmp; |
552 | } |
553 | |
554 | |
555 | |
556 | SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, |
557 | SDValue &AVRcc, SelectionDAG &DAG, |
558 | SDLoc DL) const { |
559 | SDValue Cmp; |
560 | EVT VT = LHS.getValueType(); |
561 | bool UseTest = false; |
562 | |
563 | switch (CC) { |
564 | default: |
565 | break; |
566 | case ISD::SETLE: { |
567 | |
568 | std::swap(LHS, RHS); |
569 | CC = ISD::SETGE; |
570 | break; |
571 | } |
572 | case ISD::SETGT: { |
573 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { |
574 | switch (C->getSExtValue()) { |
575 | case -1: { |
576 | |
577 | |
578 | UseTest = true; |
579 | AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); |
580 | break; |
581 | } |
582 | case 0: { |
583 | |
584 | |
585 | RHS = LHS; |
586 | LHS = DAG.getConstant(0, DL, VT); |
587 | CC = ISD::SETLT; |
588 | break; |
589 | } |
590 | default: { |
591 | |
592 | |
593 | RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); |
594 | CC = ISD::SETGE; |
595 | break; |
596 | } |
597 | } |
598 | break; |
599 | } |
600 | |
601 | std::swap(LHS, RHS); |
602 | CC = ISD::SETLT; |
603 | break; |
604 | } |
605 | case ISD::SETLT: { |
606 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { |
607 | switch (C->getSExtValue()) { |
608 | case 1: { |
609 | |
610 | |
611 | RHS = LHS; |
612 | LHS = DAG.getConstant(0, DL, VT); |
613 | CC = ISD::SETGE; |
614 | break; |
615 | } |
616 | case 0: { |
617 | |
618 | |
619 | UseTest = true; |
620 | AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); |
621 | break; |
622 | } |
623 | } |
624 | } |
625 | break; |
626 | } |
627 | case ISD::SETULE: { |
628 | |
629 | std::swap(LHS, RHS); |
630 | CC = ISD::SETUGE; |
631 | break; |
632 | } |
633 | case ISD::SETUGT: { |
634 | |
635 | |
636 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { |
637 | RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); |
638 | CC = ISD::SETUGE; |
639 | break; |
640 | } |
641 | |
642 | std::swap(LHS, RHS); |
643 | CC = ISD::SETULT; |
644 | break; |
645 | } |
646 | } |
647 | |
648 | |
649 | |
650 | if (VT == MVT::i32) { |
651 | SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, |
652 | DAG.getIntPtrConstant(0, DL)); |
653 | SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, |
654 | DAG.getIntPtrConstant(1, DL)); |
655 | SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, |
656 | DAG.getIntPtrConstant(0, DL)); |
657 | SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, |
658 | DAG.getIntPtrConstant(1, DL)); |
659 | |
660 | if (UseTest) { |
661 | |
662 | SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, |
663 | DAG.getIntPtrConstant(1, DL)); |
664 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); |
665 | } else { |
666 | Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL); |
667 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); |
668 | } |
669 | } else if (VT == MVT::i64) { |
670 | SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, |
671 | DAG.getIntPtrConstant(0, DL)); |
672 | SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, |
673 | DAG.getIntPtrConstant(1, DL)); |
674 | |
675 | SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, |
676 | DAG.getIntPtrConstant(0, DL)); |
677 | SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, |
678 | DAG.getIntPtrConstant(1, DL)); |
679 | SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, |
680 | DAG.getIntPtrConstant(0, DL)); |
681 | SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, |
682 | DAG.getIntPtrConstant(1, DL)); |
683 | |
684 | SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, |
685 | DAG.getIntPtrConstant(0, DL)); |
686 | SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, |
687 | DAG.getIntPtrConstant(1, DL)); |
688 | |
689 | SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, |
690 | DAG.getIntPtrConstant(0, DL)); |
691 | SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, |
692 | DAG.getIntPtrConstant(1, DL)); |
693 | SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, |
694 | DAG.getIntPtrConstant(0, DL)); |
695 | SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, |
696 | DAG.getIntPtrConstant(1, DL)); |
697 | |
698 | if (UseTest) { |
699 | |
700 | SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, |
701 | DAG.getIntPtrConstant(1, DL)); |
702 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); |
703 | } else { |
704 | Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); |
705 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); |
706 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); |
707 | Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp); |
708 | } |
709 | } else if (VT == MVT::i8 || VT == MVT::i16) { |
710 | if (UseTest) { |
711 | |
712 | Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, |
713 | (VT == MVT::i8) |
714 | ? LHS |
715 | : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, |
716 | LHS, DAG.getIntPtrConstant(1, DL))); |
717 | } else { |
718 | Cmp = getAVRCmp(LHS, RHS, DAG, DL); |
719 | } |
720 | } else { |
721 | llvm_unreachable("Invalid comparison size"); |
722 | } |
723 | |
724 | |
725 | if (!UseTest) { |
726 | AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); |
727 | } |
728 | |
729 | return Cmp; |
730 | } |
731 | |
732 | SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { |
733 | SDValue Chain = Op.getOperand(0); |
734 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); |
735 | SDValue LHS = Op.getOperand(2); |
736 | SDValue RHS = Op.getOperand(3); |
737 | SDValue Dest = Op.getOperand(4); |
738 | SDLoc dl(Op); |
739 | |
740 | SDValue TargetCC; |
741 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); |
742 | |
743 | return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, |
744 | Cmp); |
745 | } |
746 | |
747 | SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { |
748 | SDValue LHS = Op.getOperand(0); |
749 | SDValue RHS = Op.getOperand(1); |
750 | SDValue TrueV = Op.getOperand(2); |
751 | SDValue FalseV = Op.getOperand(3); |
752 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); |
753 | SDLoc dl(Op); |
754 | |
755 | SDValue TargetCC; |
756 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); |
757 | |
758 | SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); |
759 | SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; |
760 | |
761 | return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); |
762 | } |
763 | |
764 | SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { |
765 | SDValue LHS = Op.getOperand(0); |
766 | SDValue RHS = Op.getOperand(1); |
767 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); |
768 | SDLoc DL(Op); |
769 | |
770 | SDValue TargetCC; |
771 | SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL); |
772 | |
773 | SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); |
774 | SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); |
775 | SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); |
776 | SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; |
777 | |
778 | return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); |
779 | } |
780 | |
781 | SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { |
782 | const MachineFunction &MF = DAG.getMachineFunction(); |
783 | const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); |
784 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
785 | auto DL = DAG.getDataLayout(); |
786 | SDLoc dl(Op); |
787 | |
788 | |
789 | |
790 | SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); |
791 | |
792 | return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), |
793 | MachinePointerInfo(SV)); |
794 | } |
795 | |
796 | SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { |
797 | switch (Op.getOpcode()) { |
798 | default: |
799 | llvm_unreachable("Don't know how to custom lower this!"); |
800 | case ISD::SHL: |
801 | case ISD::SRA: |
802 | case ISD::SRL: |
803 | case ISD::ROTL: |
804 | case ISD::ROTR: |
805 | return LowerShifts(Op, DAG); |
806 | case ISD::GlobalAddress: |
807 | return LowerGlobalAddress(Op, DAG); |
808 | case ISD::BlockAddress: |
809 | return LowerBlockAddress(Op, DAG); |
810 | case ISD::BR_CC: |
811 | return LowerBR_CC(Op, DAG); |
812 | case ISD::SELECT_CC: |
813 | return LowerSELECT_CC(Op, DAG); |
814 | case ISD::SETCC: |
815 | return LowerSETCC(Op, DAG); |
816 | case ISD::VASTART: |
817 | return LowerVASTART(Op, DAG); |
818 | case ISD::SDIVREM: |
819 | case ISD::UDIVREM: |
820 | return LowerDivRem(Op, DAG); |
821 | } |
822 | |
823 | return SDValue(); |
824 | } |
825 | |
826 | |
827 | |
828 | void AVRTargetLowering::ReplaceNodeResults(SDNode *N, |
829 | SmallVectorImpl<SDValue> &Results, |
830 | SelectionDAG &DAG) const { |
831 | SDLoc DL(N); |
832 | |
833 | switch (N->getOpcode()) { |
834 | case ISD::ADD: { |
835 | |
836 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { |
837 | SDValue Sub = DAG.getNode( |
838 | ISD::SUB, DL, N->getValueType(0), N->getOperand(0), |
839 | DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0))); |
840 | Results.push_back(Sub); |
841 | } |
842 | break; |
843 | } |
844 | default: { |
845 | SDValue Res = LowerOperation(SDValue(N, 0), DAG); |
846 | |
847 | for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) |
848 | Results.push_back(Res.getValue(I)); |
849 | |
850 | break; |
851 | } |
852 | } |
853 | } |
854 | |
855 | |
856 | |
857 | bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL, |
858 | const AddrMode &AM, Type *Ty, |
859 | unsigned AS, Instruction *I) const { |
860 | int64_t Offs = AM.BaseOffs; |
861 | |
862 | |
863 | if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { |
864 | return true; |
865 | } |
866 | |
867 | |
868 | if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { |
869 | return false; |
870 | } |
871 | |
872 | |
873 | if (Offs < 0) |
874 | Offs = -Offs; |
875 | if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { |
876 | return true; |
877 | } |
878 | |
879 | return false; |
880 | } |
881 | |
882 | |
883 | |
884 | |
885 | bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, |
886 | SDValue &Offset, |
887 | ISD::MemIndexedMode &AM, |
888 | SelectionDAG &DAG) const { |
889 | EVT VT; |
890 | const SDNode *Op; |
891 | SDLoc DL(N); |
892 | |
893 | if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
894 | VT = LD->getMemoryVT(); |
895 | Op = LD->getBasePtr().getNode(); |
896 | if (LD->getExtensionType() != ISD::NON_EXTLOAD) |
897 | return false; |
898 | if (AVR::isProgramMemoryAccess(LD)) { |
899 | return false; |
900 | } |
901 | } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
902 | VT = ST->getMemoryVT(); |
903 | Op = ST->getBasePtr().getNode(); |
904 | if (AVR::isProgramMemoryAccess(ST)) { |
905 | return false; |
906 | } |
907 | } else { |
908 | return false; |
909 | } |
910 | |
911 | if (VT != MVT::i8 && VT != MVT::i16) { |
912 | return false; |
913 | } |
914 | |
915 | if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { |
916 | return false; |
917 | } |
918 | |
919 | if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { |
920 | int RHSC = RHS->getSExtValue(); |
921 | if (Op->getOpcode() == ISD::SUB) |
922 | RHSC = -RHSC; |
923 | |
924 | if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { |
925 | return false; |
926 | } |
927 | |
928 | Base = Op->getOperand(0); |
929 | Offset = DAG.getConstant(RHSC, DL, MVT::i8); |
930 | AM = ISD::PRE_DEC; |
931 | |
932 | return true; |
933 | } |
934 | |
935 | return false; |
936 | } |
937 | |
938 | |
939 | |
940 | |
941 | bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, |
942 | SDValue &Base, |
943 | SDValue &Offset, |
944 | ISD::MemIndexedMode &AM, |
945 | SelectionDAG &DAG) const { |
946 | EVT VT; |
947 | SDLoc DL(N); |
948 | |
949 | if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
950 | VT = LD->getMemoryVT(); |
951 | if (LD->getExtensionType() != ISD::NON_EXTLOAD) |
952 | return false; |
953 | } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
954 | VT = ST->getMemoryVT(); |
955 | if (AVR::isProgramMemoryAccess(ST)) { |
956 | return false; |
957 | } |
958 | } else { |
959 | return false; |
960 | } |
961 | |
962 | if (VT != MVT::i8 && VT != MVT::i16) { |
963 | return false; |
964 | } |
965 | |
966 | if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { |
967 | return false; |
968 | } |
969 | |
970 | if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { |
971 | int RHSC = RHS->getSExtValue(); |
972 | if (Op->getOpcode() == ISD::SUB) |
973 | RHSC = -RHSC; |
974 | if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { |
975 | return false; |
976 | } |
977 | |
978 | Base = Op->getOperand(0); |
979 | Offset = DAG.getConstant(RHSC, DL, MVT::i8); |
980 | AM = ISD::POST_INC; |
981 | |
982 | return true; |
983 | } |
984 | |
985 | return false; |
986 | } |
987 | |
988 | bool AVRTargetLowering::isOffsetFoldingLegal( |
989 | const GlobalAddressSDNode *GA) const { |
990 | return true; |
991 | } |
992 | |
993 | |
994 | |
995 | |
996 | |
997 | #include "AVRGenCallingConv.inc" |
998 | |
999 | |
1000 | |
1001 | static const MCPhysReg RegList8[] = { |
1002 | AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, |
1003 | AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, |
1004 | AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8}; |
1005 | static const MCPhysReg RegList16[] = { |
1006 | AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, |
1007 | AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18, |
1008 | AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14, |
1009 | AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10, |
1010 | AVR::R10R9, AVR::R9R8}; |
1011 | |
1012 | static_assert(array_lengthof(RegList8) == array_lengthof(RegList16), |
1013 | "8-bit and 16-bit register arrays must be of equal length"); |
1014 | |
1015 | |
1016 | |
1017 | |
1018 | |
1019 | template <typename ArgT> |
1020 | static void |
1021 | analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, |
1022 | const DataLayout *TD, const SmallVectorImpl<ArgT> &Args, |
1023 | SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) { |
1024 | unsigned NumArgs = Args.size(); |
1025 | |
1026 | |
1027 | int RegLastIdx = -1; |
1028 | |
1029 | bool UseStack = false; |
1030 | for (unsigned i = 0; i != NumArgs;) { |
1031 | MVT VT = Args[i].VT; |
1032 | |
1033 | |
1034 | |
1035 | |
1036 | unsigned ArgIndex = Args[i].OrigArgIndex; |
1037 | unsigned TotalBytes = VT.getStoreSize(); |
1038 | unsigned j = i + 1; |
1039 | for (; j != NumArgs; ++j) { |
1040 | if (Args[j].OrigArgIndex != ArgIndex) |
1041 | break; |
1042 | TotalBytes += Args[j].VT.getStoreSize(); |
1043 | } |
1044 | |
1045 | TotalBytes = alignTo(TotalBytes, 2); |
1046 | |
1047 | if (TotalBytes == 0) |
1048 | continue; |
1049 | |
1050 | unsigned RegIdx = RegLastIdx + TotalBytes; |
1051 | RegLastIdx = RegIdx; |
1052 | |
1053 | if (RegIdx >= array_lengthof(RegList8)) { |
1054 | UseStack = true; |
1055 | } |
1056 | for (; i != j; ++i) { |
1057 | MVT VT = Args[i].VT; |
1058 | |
1059 | if (UseStack) { |
1060 | auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); |
1061 | unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt), |
1062 | TD->getABITypeAlign(evt)); |
1063 | CCInfo.addLoc( |
1064 | CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); |
1065 | } else { |
1066 | unsigned Reg; |
1067 | if (VT == MVT::i8) { |
1068 | Reg = CCInfo.AllocateReg(RegList8[RegIdx]); |
1069 | } else if (VT == MVT::i16) { |
1070 | Reg = CCInfo.AllocateReg(RegList16[RegIdx]); |
1071 | } else { |
1072 | llvm_unreachable( |
1073 | "calling convention can only manage i8 and i16 types"); |
1074 | } |
1075 | assert(Reg && "register not available in calling convention"); |
1076 | CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); |
1077 | |
1078 | |
1079 | RegIdx -= VT.getStoreSize(); |
1080 | } |
1081 | } |
1082 | } |
1083 | } |
1084 | |
1085 | |
1086 | template <typename ArgT> |
1087 | static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) { |
1088 | unsigned TotalBytes = 0; |
1089 | |
1090 | for (const ArgT& Arg : Args) { |
1091 | TotalBytes += Arg.VT.getStoreSize(); |
1092 | } |
1093 | return TotalBytes; |
1094 | } |
1095 | |
1096 | |
1097 | |
1098 | |
1099 | template <typename ArgT> |
1100 | static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args, |
1101 | CCState &CCInfo) { |
1102 | unsigned NumArgs = Args.size(); |
1103 | unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args); |
1104 | |
1105 | assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"); |
1106 | |
1107 | |
1108 | |
1109 | if (TotalBytes > 4) { |
| |
1110 | TotalBytes = 8; |
1111 | } else { |
1112 | TotalBytes = alignTo(TotalBytes, 2); |
1113 | } |
1114 | |
1115 | |
1116 | int RegIdx = TotalBytes - 1; |
| 5 | | 'RegIdx' initialized to -1 | |
|
1117 | for (unsigned i = 0; i != NumArgs; ++i) { |
| 6 | | Assuming 'i' is not equal to 'NumArgs' | |
|
| 7 | | Loop condition is true. Entering loop body | |
|
1118 | MVT VT = Args[i].VT; |
1119 | unsigned Reg; |
1120 | if (VT == MVT::i8) { |
| 8 | | Calling 'MVT::operator==' | |
|
| 11 | | Returning from 'MVT::operator==' | |
|
| |
1121 | Reg = CCInfo.AllocateReg(RegList8[RegIdx]); |
1122 | } else if (VT == MVT::i16) { |
| |
1123 | Reg = CCInfo.AllocateReg(RegList16[RegIdx]); |
| 14 | | 1st function call argument is an uninitialized value |
|
1124 | } else { |
1125 | llvm_unreachable("calling convention can only manage i8 and i16 types"); |
1126 | } |
1127 | assert(Reg && "register not available in calling convention"); |
1128 | CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); |
1129 | |
1130 | RegIdx -= VT.getStoreSize(); |
1131 | } |
1132 | } |
1133 | |
1134 | SDValue AVRTargetLowering::LowerFormalArguments( |
1135 | SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
1136 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, |
1137 | SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { |
1138 | MachineFunction &MF = DAG.getMachineFunction(); |
1139 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
1140 | auto DL = DAG.getDataLayout(); |
1141 | |
1142 | |
1143 | SmallVector<CCValAssign, 16> ArgLocs; |
1144 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
1145 | *DAG.getContext()); |
1146 | |
1147 | |
1148 | if (isVarArg) { |
1149 | CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg); |
1150 | } else { |
1151 | analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo); |
1152 | } |
1153 | |
1154 | SDValue ArgValue; |
1155 | for (CCValAssign &VA : ArgLocs) { |
1156 | |
1157 | |
1158 | if (VA.isRegLoc()) { |
1159 | EVT RegVT = VA.getLocVT(); |
1160 | const TargetRegisterClass *RC; |
1161 | if (RegVT == MVT::i8) { |
1162 | RC = &AVR::GPR8RegClass; |
1163 | } else if (RegVT == MVT::i16) { |
1164 | RC = &AVR::DREGSRegClass; |
1165 | } else { |
1166 | llvm_unreachable("Unknown argument type!"); |
1167 | } |
1168 | |
1169 | unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); |
1170 | ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); |
1171 | |
1172 | |
1173 | |
1174 | |
1175 | |
1176 | |
1177 | |
1178 | switch (VA.getLocInfo()) { |
1179 | default: |
1180 | llvm_unreachable("Unknown loc info!"); |
1181 | case CCValAssign::Full: |
1182 | break; |
1183 | case CCValAssign::BCvt: |
1184 | ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); |
1185 | break; |
1186 | case CCValAssign::SExt: |
1187 | ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, |
1188 | DAG.getValueType(VA.getValVT())); |
1189 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); |
1190 | break; |
1191 | case CCValAssign::ZExt: |
1192 | ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, |
1193 | DAG.getValueType(VA.getValVT())); |
1194 | ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); |
1195 | break; |
1196 | } |
1197 | |
1198 | InVals.push_back(ArgValue); |
1199 | } else { |
1200 | |
1201 | assert(VA.isMemLoc()); |
1202 | |
1203 | EVT LocVT = VA.getLocVT(); |
1204 | |
1205 | |
1206 | int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, |
1207 | VA.getLocMemOffset(), true); |
1208 | |
1209 | |
1210 | |
1211 | SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); |
1212 | InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, |
1213 | MachinePointerInfo::getFixedStack(MF, FI))); |
1214 | } |
1215 | } |
1216 | |
1217 | |
1218 | |
1219 | if (isVarArg) { |
1220 | unsigned StackSize = CCInfo.getNextStackOffset(); |
1221 | AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); |
1222 | |
1223 | AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true)); |
1224 | } |
1225 | |
1226 | return Chain; |
1227 | } |
1228 | |
1229 | |
1230 | |
1231 | |
1232 | |
1233 | SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, |
1234 | SmallVectorImpl<SDValue> &InVals) const { |
1235 | SelectionDAG &DAG = CLI.DAG; |
1236 | SDLoc &DL = CLI.DL; |
1237 | SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; |
1238 | SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; |
1239 | SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; |
1240 | SDValue Chain = CLI.Chain; |
1241 | SDValue Callee = CLI.Callee; |
1242 | bool &isTailCall = CLI.IsTailCall; |
1243 | CallingConv::ID CallConv = CLI.CallConv; |
1244 | bool isVarArg = CLI.IsVarArg; |
1245 | |
1246 | MachineFunction &MF = DAG.getMachineFunction(); |
1247 | |
1248 | |
1249 | isTailCall = false; |
1250 | |
1251 | |
1252 | SmallVector<CCValAssign, 16> ArgLocs; |
1253 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
1254 | *DAG.getContext()); |
1255 | |
1256 | |
1257 | |
1258 | |
1259 | const Function *F = nullptr; |
1260 | if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { |
1261 | const GlobalValue *GV = G->getGlobal(); |
1262 | |
1263 | F = cast<Function>(GV); |
1264 | Callee = |
1265 | DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout())); |
1266 | } else if (const ExternalSymbolSDNode *ES = |
1267 | dyn_cast<ExternalSymbolSDNode>(Callee)) { |
1268 | Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), |
1269 | getPointerTy(DAG.getDataLayout())); |
1270 | } |
1271 | |
1272 | |
1273 | if (isVarArg) { |
1274 | CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg); |
1275 | } else { |
1276 | analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo); |
1277 | } |
1278 | |
1279 | |
1280 | unsigned NumBytes = CCInfo.getNextStackOffset(); |
1281 | |
1282 | Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL); |
1283 | |
1284 | SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; |
1285 | |
1286 | |
1287 | unsigned AI, AE; |
1288 | bool HasStackArgs = false; |
1289 | for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { |
1290 | CCValAssign &VA = ArgLocs[AI]; |
1291 | EVT RegVT = VA.getLocVT(); |
1292 | SDValue Arg = OutVals[AI]; |
1293 | |
1294 | |
1295 | switch (VA.getLocInfo()) { |
1296 | default: |
1297 | llvm_unreachable("Unknown loc info!"); |
1298 | case CCValAssign::Full: |
1299 | break; |
1300 | case CCValAssign::SExt: |
1301 | Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); |
1302 | break; |
1303 | case CCValAssign::ZExt: |
1304 | Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); |
1305 | break; |
1306 | case CCValAssign::AExt: |
1307 | Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); |
1308 | break; |
1309 | case CCValAssign::BCvt: |
1310 | Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); |
1311 | break; |
1312 | } |
1313 | |
1314 | |
1315 | |
1316 | if (VA.isMemLoc()) { |
1317 | HasStackArgs = true; |
1318 | break; |
1319 | } |
1320 | |
1321 | |
1322 | |
1323 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); |
1324 | } |
1325 | |
1326 | |
1327 | |
1328 | |
1329 | |
1330 | |
1331 | |
1332 | if (HasStackArgs) { |
1333 | SmallVector<SDValue, 8> MemOpChains; |
1334 | for (; AI != AE; AI++) { |
1335 | CCValAssign &VA = ArgLocs[AI]; |
1336 | SDValue Arg = OutVals[AI]; |
1337 | |
1338 | assert(VA.isMemLoc()); |
1339 | |
1340 | |
1341 | SDValue PtrOff = DAG.getNode( |
1342 | ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), |
1343 | DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), |
1344 | DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL)); |
1345 | |
1346 | MemOpChains.push_back( |
1347 | DAG.getStore(Chain, DL, Arg, PtrOff, |
1348 | MachinePointerInfo::getStack(MF, VA.getLocMemOffset()))); |
1349 | } |
1350 | |
1351 | if (!MemOpChains.empty()) |
1352 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); |
1353 | } |
1354 | |
1355 | |
1356 | |
1357 | |
1358 | SDValue InFlag; |
1359 | for (auto Reg : RegsToPass) { |
1360 | Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag); |
1361 | InFlag = Chain.getValue(1); |
1362 | } |
1363 | |
1364 | |
1365 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
1366 | SmallVector<SDValue, 8> Ops; |
1367 | Ops.push_back(Chain); |
1368 | Ops.push_back(Callee); |
1369 | |
1370 | |
1371 | |
1372 | for (auto Reg : RegsToPass) { |
1373 | Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); |
1374 | } |
1375 | |
1376 | |
1377 | const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); |
1378 | const uint32_t *Mask = |
1379 | TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); |
1380 | assert(Mask && "Missing call preserved mask for calling convention"); |
1381 | Ops.push_back(DAG.getRegisterMask(Mask)); |
1382 | |
1383 | if (InFlag.getNode()) { |
1384 | Ops.push_back(InFlag); |
1385 | } |
1386 | |
1387 | Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops); |
1388 | InFlag = Chain.getValue(1); |
1389 | |
1390 | |
1391 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), |
1392 | DAG.getIntPtrConstant(0, DL, true), InFlag, DL); |
1393 | |
1394 | if (!Ins.empty()) { |
1395 | InFlag = Chain.getValue(1); |
1396 | } |
1397 | |
1398 | |
1399 | |
1400 | return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, |
1401 | InVals); |
1402 | } |
1403 | |
1404 | |
1405 | |
1406 | |
1407 | SDValue AVRTargetLowering::LowerCallResult( |
1408 | SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, |
1409 | const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, |
1410 | SmallVectorImpl<SDValue> &InVals) const { |
1411 | |
1412 | |
1413 | SmallVector<CCValAssign, 16> RVLocs; |
1414 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, |
1415 | *DAG.getContext()); |
1416 | |
1417 | |
1418 | if (CallConv == CallingConv::AVR_BUILTIN) { |
1419 | CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN); |
1420 | } else { |
1421 | analyzeReturnValues(Ins, CCInfo); |
1422 | } |
1423 | |
1424 | |
1425 | for (CCValAssign const &RVLoc : RVLocs) { |
1426 | Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), |
1427 | InFlag) |
1428 | .getValue(1); |
1429 | InFlag = Chain.getValue(2); |
1430 | InVals.push_back(Chain.getValue(0)); |
1431 | } |
1432 | |
1433 | return Chain; |
1434 | } |
1435 | |
1436 | |
1437 | |
1438 | |
1439 | |
1440 | bool AVRTargetLowering::CanLowerReturn( |
1441 | CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, |
1442 | const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { |
1443 | if (CallConv == CallingConv::AVR_BUILTIN) { |
1444 | SmallVector<CCValAssign, 16> RVLocs; |
1445 | CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); |
1446 | return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN); |
1447 | } |
1448 | |
1449 | unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs); |
1450 | return TotalBytes <= 8; |
1451 | } |
1452 | |
1453 | SDValue |
1454 | AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, |
1455 | bool isVarArg, |
1456 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
1457 | const SmallVectorImpl<SDValue> &OutVals, |
1458 | const SDLoc &dl, SelectionDAG &DAG) const { |
1459 | |
1460 | SmallVector<CCValAssign, 16> RVLocs; |
1461 | |
1462 | |
1463 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, |
1464 | *DAG.getContext()); |
1465 | |
1466 | MachineFunction &MF = DAG.getMachineFunction(); |
1467 | |
1468 | |
1469 | if (CallConv == CallingConv::AVR_BUILTIN) { |
| 1 | Assuming 'CallConv' is not equal to AVR_BUILTIN | |
|
| |
1470 | CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN); |
1471 | } else { |
1472 | analyzeReturnValues(Outs, CCInfo); |
| 3 | | Calling 'analyzeReturnValues<llvm::ISD::OutputArg>' | |
|
1473 | } |
1474 | |
1475 | SDValue Flag; |
1476 | SmallVector<SDValue, 4> RetOps(1, Chain); |
1477 | |
1478 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { |
1479 | CCValAssign &VA = RVLocs[i]; |
1480 | assert(VA.isRegLoc() && "Can only return in registers!"); |
1481 | |
1482 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); |
1483 | |
1484 | |
1485 | Flag = Chain.getValue(1); |
1486 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); |
1487 | } |
1488 | |
1489 | |
1490 | |
1491 | if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) { |
1492 | return Chain; |
1493 | } |
1494 | |
1495 | const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); |
1496 | |
1497 | unsigned RetOpc = |
1498 | AFI->isInterruptOrSignalHandler() |
1499 | ? AVRISD::RETI_FLAG |
1500 | : AVRISD::RET_FLAG; |
1501 | |
1502 | RetOps[0] = Chain; |
1503 | |
1504 | if (Flag.getNode()) { |
1505 | RetOps.push_back(Flag); |
1506 | } |
1507 | |
1508 | return DAG.getNode(RetOpc, dl, MVT::Other, RetOps); |
1509 | } |
1510 | |
1511 | |
1512 | |
1513 | |
1514 | |
1515 | MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, |
1516 | MachineBasicBlock *BB) const { |
1517 | unsigned Opc; |
1518 | const TargetRegisterClass *RC; |
1519 | bool HasRepeatedOperand = false; |
1520 | MachineFunction *F = BB->getParent(); |
1521 | MachineRegisterInfo &RI = F->getRegInfo(); |
1522 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1523 | DebugLoc dl = MI.getDebugLoc(); |
1524 | |
1525 | switch (MI.getOpcode()) { |
1526 | default: |
1527 | llvm_unreachable("Invalid shift opcode!"); |
1528 | case AVR::Lsl8: |
1529 | Opc = AVR::ADDRdRr; |
1530 | RC = &AVR::GPR8RegClass; |
1531 | HasRepeatedOperand = true; |
1532 | break; |
1533 | case AVR::Lsl16: |
1534 | Opc = AVR::LSLWRd; |
1535 | RC = &AVR::DREGSRegClass; |
1536 | break; |
1537 | case AVR::Asr8: |
1538 | Opc = AVR::ASRRd; |
1539 | RC = &AVR::GPR8RegClass; |
1540 | break; |
1541 | case AVR::Asr16: |
1542 | Opc = AVR::ASRWRd; |
1543 | RC = &AVR::DREGSRegClass; |
1544 | break; |
1545 | case AVR::Lsr8: |
1546 | Opc = AVR::LSRRd; |
1547 | RC = &AVR::GPR8RegClass; |
1548 | break; |
1549 | case AVR::Lsr16: |
1550 | Opc = AVR::LSRWRd; |
1551 | RC = &AVR::DREGSRegClass; |
1552 | break; |
1553 | case AVR::Rol8: |
1554 | Opc = AVR::ROLBRd; |
1555 | RC = &AVR::GPR8RegClass; |
1556 | break; |
1557 | case AVR::Rol16: |
1558 | Opc = AVR::ROLWRd; |
1559 | RC = &AVR::DREGSRegClass; |
1560 | break; |
1561 | case AVR::Ror8: |
1562 | Opc = AVR::RORBRd; |
1563 | RC = &AVR::GPR8RegClass; |
1564 | break; |
1565 | case AVR::Ror16: |
1566 | Opc = AVR::RORWRd; |
1567 | RC = &AVR::DREGSRegClass; |
1568 | break; |
1569 | } |
1570 | |
1571 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
1572 | |
1573 | MachineFunction::iterator I; |
1574 | for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I); |
1575 | if (I != F->end()) ++I; |
1576 | |
1577 | |
1578 | MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); |
1579 | MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB); |
1580 | MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); |
1581 | |
1582 | F->insert(I, LoopBB); |
1583 | F->insert(I, CheckBB); |
1584 | F->insert(I, RemBB); |
1585 | |
1586 | |
1587 | |
1588 | RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), |
1589 | BB->end()); |
1590 | RemBB->transferSuccessorsAndUpdatePHIs(BB); |
1591 | |
1592 | |
1593 | BB->addSuccessor(CheckBB); |
1594 | LoopBB->addSuccessor(CheckBB); |
1595 | CheckBB->addSuccessor(LoopBB); |
1596 | CheckBB->addSuccessor(RemBB); |
1597 | |
1598 | Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); |
1599 | Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); |
1600 | Register ShiftReg = RI.createVirtualRegister(RC); |
1601 | Register ShiftReg2 = RI.createVirtualRegister(RC); |
1602 | Register ShiftAmtSrcReg = MI.getOperand(2).getReg(); |
1603 | Register SrcReg = MI.getOperand(1).getReg(); |
1604 | Register DstReg = MI.getOperand(0).getReg(); |
1605 | |
1606 | |
1607 | |
1608 | BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); |
1609 | |
1610 | |
1611 | |
1612 | auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); |
1613 | if (HasRepeatedOperand) |
1614 | ShiftMI.addReg(ShiftReg); |
1615 | |
1616 | |
1617 | |
1618 | |
1619 | |
1620 | |
1621 | |
1622 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) |
1623 | .addReg(SrcReg) |
1624 | .addMBB(BB) |
1625 | .addReg(ShiftReg2) |
1626 | .addMBB(LoopBB); |
1627 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) |
1628 | .addReg(ShiftAmtSrcReg) |
1629 | .addMBB(BB) |
1630 | .addReg(ShiftAmtReg2) |
1631 | .addMBB(LoopBB); |
1632 | BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) |
1633 | .addReg(SrcReg) |
1634 | .addMBB(BB) |
1635 | .addReg(ShiftReg2) |
1636 | .addMBB(LoopBB); |
1637 | |
1638 | BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2) |
1639 | .addReg(ShiftAmtReg); |
1640 | BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); |
1641 | |
1642 | MI.eraseFromParent(); |
1643 | return RemBB; |
1644 | } |
1645 | |
1646 | static bool isCopyMulResult(MachineBasicBlock::iterator const &I) { |
1647 | if (I->getOpcode() == AVR::COPY) { |
1648 | Register SrcReg = I->getOperand(1).getReg(); |
1649 | return (SrcReg == AVR::R0 || SrcReg == AVR::R1); |
1650 | } |
1651 | |
1652 | return false; |
1653 | } |
1654 | |
1655 | |
1656 | |
1657 | |
1658 | MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI, |
1659 | MachineBasicBlock *BB) const { |
1660 | const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); |
1661 | MachineBasicBlock::iterator I(MI); |
1662 | ++I; |
1663 | if (isCopyMulResult(I)) |
1664 | ++I; |
1665 | if (isCopyMulResult(I)) |
1666 | ++I; |
1667 | BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) |
1668 | .addReg(AVR::R1) |
1669 | .addReg(AVR::R1); |
1670 | return BB; |
1671 | } |
1672 | |
1673 | MachineBasicBlock * |
1674 | AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, |
1675 | MachineBasicBlock *MBB) const { |
1676 | int Opc = MI.getOpcode(); |
1677 | |
1678 | |
1679 | |
1680 | switch (Opc) { |
1681 | case AVR::Lsl8: |
1682 | case AVR::Lsl16: |
1683 | case AVR::Lsr8: |
1684 | case AVR::Lsr16: |
1685 | case AVR::Rol8: |
1686 | case AVR::Rol16: |
1687 | case AVR::Ror8: |
1688 | case AVR::Ror16: |
1689 | case AVR::Asr8: |
1690 | case AVR::Asr16: |
1691 | return insertShift(MI, MBB); |
1692 | case AVR::MULRdRr: |
1693 | case AVR::MULSRdRr: |
1694 | return insertMul(MI, MBB); |
1695 | } |
1696 | |
1697 | assert((Opc == AVR::Select16 || Opc == AVR::Select8) && |
1698 | "Unexpected instr type to insert"); |
1699 | |
1700 | const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() |
1701 | ->getParent() |
1702 | ->getSubtarget() |
1703 | .getInstrInfo(); |
1704 | DebugLoc dl = MI.getDebugLoc(); |
1705 | |
1706 | |
1707 | |
1708 | |
1709 | |
1710 | |
1711 | |
1712 | MachineFunction *MF = MBB->getParent(); |
1713 | const BasicBlock *LLVM_BB = MBB->getBasicBlock(); |
1714 | MachineBasicBlock *FallThrough = MBB->getFallThrough(); |
1715 | |
1716 | |
1717 | |
1718 | |
1719 | if (FallThrough != nullptr) { |
1720 | BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); |
1721 | } |
1722 | |
1723 | MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB); |
1724 | MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB); |
1725 | |
1726 | MachineFunction::iterator I; |
1727 | for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I); |
1728 | if (I != MF->end()) ++I; |
1729 | MF->insert(I, trueMBB); |
1730 | MF->insert(I, falseMBB); |
1731 | |
1732 | |
1733 | |
1734 | |
1735 | trueMBB->splice(trueMBB->begin(), MBB, |
1736 | std::next(MachineBasicBlock::iterator(MI)), MBB->end()); |
1737 | trueMBB->transferSuccessorsAndUpdatePHIs(MBB); |
1738 | |
1739 | AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm(); |
1740 | BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB); |
1741 | BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); |
1742 | MBB->addSuccessor(falseMBB); |
1743 | MBB->addSuccessor(trueMBB); |
1744 | |
1745 | |
1746 | BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); |
1747 | falseMBB->addSuccessor(trueMBB); |
1748 | |
1749 | |
1750 | BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg()) |
1751 | .addReg(MI.getOperand(1).getReg()) |
1752 | .addMBB(MBB) |
1753 | .addReg(MI.getOperand(2).getReg()) |
1754 | .addMBB(falseMBB) ; |
1755 | |
1756 | MI.eraseFromParent(); |
1757 | return trueMBB; |
1758 | } |
1759 | |
1760 | |
1761 | |
1762 | |
1763 | |
1764 | AVRTargetLowering::ConstraintType |
1765 | AVRTargetLowering::getConstraintType(StringRef Constraint) const { |
1766 | if (Constraint.size() == 1) { |
1767 | |
1768 | switch (Constraint[0]) { |
1769 | default: |
1770 | break; |
1771 | case 'a': |
1772 | case 'b': |
1773 | case 'd': |
1774 | case 'l': |
1775 | case 'e': |
1776 | case 'q': |
1777 | case 'r': |
1778 | case 'w': |
1779 | return C_RegisterClass; |
1780 | case 't': |
1781 | case 'x': case 'X': |
1782 | case 'y': case 'Y': |
1783 | case 'z': case 'Z': |
1784 | return C_Register; |
1785 | case 'Q': |
1786 | return C_Memory; |
1787 | case 'G': |
1788 | case 'I': |
1789 | case 'J': |
1790 | case 'K': |
1791 | case 'L': |
1792 | case 'M': |
1793 | case 'N': |
1794 | case 'O': |
1795 | case 'P': |
1796 | case 'R': |
1797 | return C_Immediate; |
1798 | } |
1799 | } |
1800 | |
1801 | return TargetLowering::getConstraintType(Constraint); |
1802 | } |
1803 | |
1804 | unsigned |
1805 | AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { |
1806 | |
1807 | |
1808 | switch (ConstraintCode[0]) { |
1809 | case 'Q': |
1810 | return InlineAsm::Constraint_Q; |
1811 | } |
1812 | return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); |
1813 | } |
1814 | |
1815 | AVRTargetLowering::ConstraintWeight |
1816 | AVRTargetLowering::getSingleConstraintMatchWeight( |
1817 | AsmOperandInfo &info, const char *constraint) const { |
1818 | ConstraintWeight weight = CW_Invalid; |
1819 | Value *CallOperandVal = info.CallOperandVal; |
1820 | |
1821 | |
1822 | |
1823 | |
1824 | if (!CallOperandVal) { |
1825 | return CW_Default; |
1826 | } |
1827 | |
1828 | |
1829 | switch (*constraint) { |
1830 | default: |
1831 | weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); |
1832 | break; |
1833 | case 'd': |
1834 | case 'r': |
1835 | case 'l': |
1836 | weight = CW_Register; |
1837 | break; |
1838 | case 'a': |
1839 | case 'b': |
1840 | case 'e': |
1841 | case 'q': |
1842 | case 't': |
1843 | case 'w': |
1844 | case 'x': case 'X': |
1845 | case 'y': case 'Y': |
1846 | case 'z': case 'Z': |
1847 | weight = CW_SpecificReg; |
1848 | break; |
1849 | case 'G': |
1850 | if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) { |
1851 | if (C->isZero()) { |
1852 | weight = CW_Constant; |
1853 | } |
1854 | } |
1855 | break; |
1856 | case 'I': |
1857 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1858 | if (isUInt<6>(C->getZExtValue())) { |
1859 | weight = CW_Constant; |
1860 | } |
1861 | } |
1862 | break; |
1863 | case 'J': |
1864 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1865 | if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) { |
1866 | weight = CW_Constant; |
1867 | } |
1868 | } |
1869 | break; |
1870 | case 'K': |
1871 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1872 | if (C->getZExtValue() == 2) { |
1873 | weight = CW_Constant; |
1874 | } |
1875 | } |
1876 | break; |
1877 | case 'L': |
1878 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1879 | if (C->getZExtValue() == 0) { |
1880 | weight = CW_Constant; |
1881 | } |
1882 | } |
1883 | break; |
1884 | case 'M': |
1885 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1886 | if (isUInt<8>(C->getZExtValue())) { |
1887 | weight = CW_Constant; |
1888 | } |
1889 | } |
1890 | break; |
1891 | case 'N': |
1892 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1893 | if (C->getSExtValue() == -1) { |
1894 | weight = CW_Constant; |
1895 | } |
1896 | } |
1897 | break; |
1898 | case 'O': |
1899 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1900 | if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) || |
1901 | (C->getZExtValue() == 24)) { |
1902 | weight = CW_Constant; |
1903 | } |
1904 | } |
1905 | break; |
1906 | case 'P': |
1907 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1908 | if (C->getZExtValue() == 1) { |
1909 | weight = CW_Constant; |
1910 | } |
1911 | } |
1912 | break; |
1913 | case 'R': |
1914 | if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { |
1915 | if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) { |
1916 | weight = CW_Constant; |
1917 | } |
1918 | } |
1919 | break; |
1920 | case 'Q': |
1921 | weight = CW_Memory; |
1922 | break; |
1923 | } |
1924 | |
1925 | return weight; |
1926 | } |
1927 | |
1928 | std::pair<unsigned, const TargetRegisterClass *> |
1929 | AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
1930 | StringRef Constraint, |
1931 | MVT VT) const { |
1932 | if (Constraint.size() == 1) { |
1933 | switch (Constraint[0]) { |
1934 | case 'a': |
1935 | if (VT == MVT::i8) |
1936 | return std::make_pair(0U, &AVR::LD8loRegClass); |
1937 | else if (VT == MVT::i16) |
1938 | return std::make_pair(0U, &AVR::DREGSLD8loRegClass); |
1939 | break; |
1940 | case 'b': |
1941 | if (VT == MVT::i8 || VT == MVT::i16) |
1942 | return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); |
1943 | break; |
1944 | case 'd': |
1945 | if (VT == MVT::i8) |
1946 | return std::make_pair(0U, &AVR::LD8RegClass); |
1947 | else if (VT == MVT::i16) |
1948 | return std::make_pair(0U, &AVR::DLDREGSRegClass); |
1949 | break; |
1950 | case 'l': |
1951 | if (VT == MVT::i8) |
1952 | return std::make_pair(0U, &AVR::GPR8loRegClass); |
1953 | else if (VT == MVT::i16) |
1954 | return std::make_pair(0U, &AVR::DREGSloRegClass); |
1955 | break; |
1956 | case 'e': |
1957 | if (VT == MVT::i8 || VT == MVT::i16) |
1958 | return std::make_pair(0U, &AVR::PTRREGSRegClass); |
1959 | break; |
1960 | case 'q': |
1961 | return std::make_pair(0U, &AVR::GPRSPRegClass); |
1962 | case 'r': |
1963 | if (VT == MVT::i8) |
1964 | return std::make_pair(0U, &AVR::GPR8RegClass); |
1965 | else if (VT == MVT::i16) |
1966 | return std::make_pair(0U, &AVR::DREGSRegClass); |
1967 | break; |
1968 | case 't': |
1969 | if (VT == MVT::i8) |
1970 | return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); |
1971 | break; |
1972 | case 'w': |
1973 | if (VT == MVT::i8 || VT == MVT::i16) |
1974 | return std::make_pair(0U, &AVR::IWREGSRegClass); |
1975 | break; |
1976 | case 'x': |
1977 | case 'X': |
1978 | if (VT == MVT::i8 || VT == MVT::i16) |
1979 | return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); |
1980 | break; |
1981 | case 'y': |
1982 | case 'Y': |
1983 | if (VT == MVT::i8 || VT == MVT::i16) |
1984 | return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); |
1985 | break; |
1986 | case 'z': |
1987 | case 'Z': |
1988 | if (VT == MVT::i8 || VT == MVT::i16) |
1989 | return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); |
1990 | break; |
1991 | default: |
1992 | break; |
1993 | } |
1994 | } |
1995 | |
1996 | return TargetLowering::getRegForInlineAsmConstraint( |
1997 | Subtarget.getRegisterInfo(), Constraint, VT); |
1998 | } |
1999 | |
2000 | void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, |
2001 | std::string &Constraint, |
2002 | std::vector<SDValue> &Ops, |
2003 | SelectionDAG &DAG) const { |
2004 | SDValue Result(0, 0); |
2005 | SDLoc DL(Op); |
2006 | EVT Ty = Op.getValueType(); |
2007 | |
2008 | |
2009 | if (Constraint.length() != 1) { |
2010 | return; |
2011 | } |
2012 | |
2013 | char ConstraintLetter = Constraint[0]; |
2014 | switch (ConstraintLetter) { |
2015 | default: |
2016 | break; |
2017 | |
2018 | case 'I': |
2019 | case 'J': |
2020 | case 'K': |
2021 | case 'L': |
2022 | case 'M': |
2023 | case 'N': |
2024 | case 'O': |
2025 | case 'P': |
2026 | case 'R': { |
2027 | const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); |
2028 | if (!C) { |
2029 | return; |
2030 | } |
2031 | |
2032 | int64_t CVal64 = C->getSExtValue(); |
2033 | uint64_t CUVal64 = C->getZExtValue(); |
2034 | switch (ConstraintLetter) { |
2035 | case 'I': |
2036 | if (!isUInt<6>(CUVal64)) |
2037 | return; |
2038 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2039 | break; |
2040 | case 'J': |
2041 | if (CVal64 < -63 || CVal64 > 0) |
2042 | return; |
2043 | Result = DAG.getTargetConstant(CVal64, DL, Ty); |
2044 | break; |
2045 | case 'K': |
2046 | if (CUVal64 != 2) |
2047 | return; |
2048 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2049 | break; |
2050 | case 'L': |
2051 | if (CUVal64 != 0) |
2052 | return; |
2053 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2054 | break; |
2055 | case 'M': |
2056 | if (!isUInt<8>(CUVal64)) |
2057 | return; |
2058 | |
2059 | |
2060 | |
2061 | if (Ty.getSimpleVT() == MVT::i8) { |
2062 | Ty = MVT::i16; |
2063 | } |
2064 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2065 | break; |
2066 | case 'N': |
2067 | if (CVal64 != -1) |
2068 | return; |
2069 | Result = DAG.getTargetConstant(CVal64, DL, Ty); |
2070 | break; |
2071 | case 'O': |
2072 | if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24) |
2073 | return; |
2074 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2075 | break; |
2076 | case 'P': |
2077 | if (CUVal64 != 1) |
2078 | return; |
2079 | Result = DAG.getTargetConstant(CUVal64, DL, Ty); |
2080 | break; |
2081 | case 'R': |
2082 | if (CVal64 < -6 || CVal64 > 5) |
2083 | return; |
2084 | Result = DAG.getTargetConstant(CVal64, DL, Ty); |
2085 | break; |
2086 | } |
2087 | |
2088 | break; |
2089 | } |
2090 | case 'G': |
2091 | const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op); |
2092 | if (!FC || !FC->isZero()) |
2093 | return; |
2094 | |
2095 | Result = DAG.getTargetConstant(0, DL, MVT::i8); |
2096 | break; |
2097 | } |
2098 | |
2099 | if (Result.getNode()) { |
2100 | Ops.push_back(Result); |
2101 | return; |
2102 | } |
2103 | |
2104 | return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); |
2105 | } |
2106 | |
2107 | Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, |
2108 | const MachineFunction &MF) const { |
2109 | Register Reg; |
2110 | |
2111 | if (VT == LLT::scalar(8)) { |
2112 | Reg = StringSwitch<unsigned>(RegName) |
2113 | .Case("r0", AVR::R0) |
2114 | .Case("r1", AVR::R1) |
2115 | .Default(0); |
2116 | } else { |
2117 | Reg = StringSwitch<unsigned>(RegName) |
2118 | .Case("r0", AVR::R1R0) |
2119 | .Case("sp", AVR::SP) |
2120 | .Default(0); |
2121 | } |
2122 | |
2123 | if (Reg) |
2124 | return Reg; |
2125 | |
2126 | report_fatal_error( |
2127 | Twine("Invalid register name \"" + StringRef(RegName) + "\".")); |
2128 | } |
2129 | |
2130 | } |
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | |
14 | #ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H |
15 | #define LLVM_SUPPORT_MACHINEVALUETYPE_H |
16 | |
17 | #include "llvm/ADT/Sequence.h" |
18 | #include "llvm/ADT/iterator_range.h" |
19 | #include "llvm/Support/ErrorHandling.h" |
20 | #include "llvm/Support/MathExtras.h" |
21 | #include "llvm/Support/TypeSize.h" |
22 | #include <cassert> |
23 | |
24 | namespace llvm { |
25 | |
26 | class Type; |
27 | |
28 | |
29 | |
30 | |
31 | class MVT { |
32 | public: |
33 | enum SimpleValueType : uint8_t { |
34 | |
35 | |
36 | |
37 | |
38 | INVALID_SIMPLE_VALUE_TYPE = 0, |
39 | |
40 | |
41 | |
42 | Other = 1, |
43 | i1 = 2, |
44 | i8 = 3, |
45 | i16 = 4, |
46 | i32 = 5, |
47 | i64 = 6, |
48 | i128 = 7, |
49 | |
50 | FIRST_INTEGER_VALUETYPE = i1, |
51 | LAST_INTEGER_VALUETYPE = i128, |
52 | |
53 | bf16 = 8, |
54 | f16 = 9, |
55 | f32 = 10, |
56 | f64 = 11, |
57 | f80 = 12, |
58 | f128 = 13, |
59 | ppcf128 = 14, |
60 | |
61 | FIRST_FP_VALUETYPE = bf16, |
62 | LAST_FP_VALUETYPE = ppcf128, |
63 | |
64 | v1i1 = 15, |
65 | v2i1 = 16, |
66 | v4i1 = 17, |
67 | v8i1 = 18, |
68 | v16i1 = 19, |
69 | v32i1 = 20, |
70 | v64i1 = 21, |
71 | v128i1 = 22, |
72 | v256i1 = 23, |
73 | v512i1 = 24, |
74 | v1024i1 = 25, |
75 | |
76 | v1i8 = 26, |
77 | v2i8 = 27, |
78 | v4i8 = 28, |
79 | v8i8 = 29, |
80 | v16i8 = 30, |
81 | v32i8 = 31, |
82 | v64i8 = 32, |
83 | v128i8 = 33, |
84 | v256i8 = 34, |
85 | v512i8 = 35, |
86 | v1024i8 = 36, |
87 | |
88 | v1i16 = 37, |
89 | v2i16 = 38, |
90 | v3i16 = 39, |
91 | v4i16 = 40, |
92 | v8i16 = 41, |
93 | v16i16 = 42, |
94 | v32i16 = 43, |
95 | v64i16 = 44, |
96 | v128i16 = 45, |
97 | v256i16 = 46, |
98 | v512i16 = 47, |
99 | |
100 | v1i32 = 48, |
101 | v2i32 = 49, |
102 | v3i32 = 50, |
103 | v4i32 = 51, |
104 | v5i32 = 52, |
105 | v6i32 = 53, |
106 | v7i32 = 54, |
107 | v8i32 = 55, |
108 | v16i32 = 56, |
109 | v32i32 = 57, |
110 | v64i32 = 58, |
111 | v128i32 = 59, |
112 | v256i32 = 60, |
113 | v512i32 = 61, |
114 | v1024i32 = 62, |
115 | v2048i32 = 63, |
116 | |
117 | v1i64 = 64, |
118 | v2i64 = 65, |
119 | v3i64 = 66, |
120 | v4i64 = 67, |
121 | v8i64 = 68, |
122 | v16i64 = 69, |
123 | v32i64 = 70, |
124 | v64i64 = 71, |
125 | v128i64 = 72, |
126 | v256i64 = 73, |
127 | |
128 | v1i128 = 74, |
129 | |
130 | FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1, |
131 | LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128, |
132 | |
133 | v1f16 = 75, |
134 | v2f16 = 76, |
135 | v3f16 = 77, |
136 | v4f16 = 78, |
137 | v8f16 = 79, |
138 | v16f16 = 80, |
139 | v32f16 = 81, |
140 | v64f16 = 82, |
141 | v128f16 = 83, |
142 | v256f16 = 84, |
143 | v512f16 = 85, |
144 | |
145 | v2bf16 = 86, |
146 | v3bf16 = 87, |
147 | v4bf16 = 88, |
148 | v8bf16 = 89, |
149 | v16bf16 = 90, |
150 | v32bf16 = 91, |
151 | v64bf16 = 92, |
152 | v128bf16 = 93, |
153 | |
154 | v1f32 = 94, |
155 | v2f32 = 95, |
156 | v3f32 = 96, |
157 | v4f32 = 97, |
158 | v5f32 = 98, |
159 | v6f32 = 99, |
160 | v7f32 = 100, |
161 | v8f32 = 101, |
162 | v16f32 = 102, |
163 | v32f32 = 103, |
164 | v64f32 = 104, |
165 | v128f32 = 105, |
166 | v256f32 = 106, |
167 | v512f32 = 107, |
168 | v1024f32 = 108, |
169 | v2048f32 = 109, |
170 | |
171 | v1f64 = 110, |
172 | v2f64 = 111, |
173 | v3f64 = 112, |
174 | v4f64 = 113, |
175 | v8f64 = 114, |
176 | v16f64 = 115, |
177 | v32f64 = 116, |
178 | v64f64 = 117, |
179 | v128f64 = 118, |
180 | v256f64 = 119, |
181 | |
182 | FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16, |
183 | LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64, |
184 | |
185 | FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1, |
186 | LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64, |
187 | |
188 | nxv1i1 = 120, |
189 | nxv2i1 = 121, |
190 | nxv4i1 = 122, |
191 | nxv8i1 = 123, |
192 | nxv16i1 = 124, |
193 | nxv32i1 = 125, |
194 | nxv64i1 = 126, |
195 | |
196 | nxv1i8 = 127, |
197 | nxv2i8 = 128, |
198 | nxv4i8 = 129, |
199 | nxv8i8 = 130, |
200 | nxv16i8 = 131, |
201 | nxv32i8 = 132, |
202 | nxv64i8 = 133, |
203 | |
204 | nxv1i16 = 134, |
205 | nxv2i16 = 135, |
206 | nxv4i16 = 136, |
207 | nxv8i16 = 137, |
208 | nxv16i16 = 138, |
209 | nxv32i16 = 139, |
210 | |
211 | nxv1i32 = 140, |
212 | nxv2i32 = 141, |
213 | nxv4i32 = 142, |
214 | nxv8i32 = 143, |
215 | nxv16i32 = 144, |
216 | nxv32i32 = 145, |
217 | |
218 | nxv1i64 = 146, |
219 | nxv2i64 = 147, |
220 | nxv4i64 = 148, |
221 | nxv8i64 = 149, |
222 | nxv16i64 = 150, |
223 | nxv32i64 = 151, |
224 | |
225 | FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1, |
226 | LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64, |
227 | |
228 | nxv1f16 = 152, |
229 | nxv2f16 = 153, |
230 | nxv4f16 = 154, |
231 | nxv8f16 = 155, |
232 | nxv16f16 = 156, |
233 | nxv32f16 = 157, |
234 | |
235 | nxv1bf16 = 158, |
236 | nxv2bf16 = 159, |
237 | nxv4bf16 = 160, |
238 | nxv8bf16 = 161, |
239 | |
240 | nxv1f32 = 162, |
241 | nxv2f32 = 163, |
242 | nxv4f32 = 164, |
243 | nxv8f32 = 165, |
244 | nxv16f32 = 166, |
245 | |
246 | nxv1f64 = 167, |
247 | nxv2f64 = 168, |
248 | nxv4f64 = 169, |
249 | nxv8f64 = 170, |
250 | |
251 | FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16, |
252 | LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64, |
253 | |
254 | FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1, |
255 | LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64, |
256 | |
257 | FIRST_VECTOR_VALUETYPE = v1i1, |
258 | LAST_VECTOR_VALUETYPE = nxv8f64, |
259 | |
260 | x86mmx = 171, |
261 | |
262 | Glue = 172, |
263 | |
264 | isVoid = 173, |
265 | |
266 | Untyped = 174, |
267 | |
268 | |
269 | |
270 | funcref = 175, |
271 | externref = 176, |
272 | x86amx = 177, |
273 | i64x8 = 178, |
274 | |
275 | FIRST_VALUETYPE = 1, |
276 | LAST_VALUETYPE = i64x8, |
277 | VALUETYPE_SIZE = LAST_VALUETYPE + 1, |
278 | |
279 | |
280 | |
281 | |
282 | MAX_ALLOWED_VALUETYPE = 192, |
283 | |
284 | |
285 | token = 248, |
286 | |
287 | |
288 | Metadata = 249, |
289 | |
290 | |
291 | |
292 | |
293 | iPTRAny = 250, |
294 | |
295 | |
296 | |
297 | |
298 | vAny = 251, |
299 | |
300 | |
301 | |
302 | |
303 | fAny = 252, |
304 | |
305 | |
306 | |
307 | |
308 | iAny = 253, |
309 | |
310 | |
311 | |
312 | iPTR = 254, |
313 | |
314 | |
315 | |
316 | Any = 255 |
317 | |
318 | |
319 | }; |
320 | |
321 | SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE; |
322 | |
323 | constexpr MVT() = default; |
324 | constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} |
325 | |
326 | bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; } |
327 | bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; } |
328 | bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; } |
| 9 | | Assuming 'SimpleTy' is not equal to 'S.SimpleTy' | |
|
| 10 | | Returning zero, which participates in a condition later | |
|
329 | bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; } |
330 | bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; } |
331 | bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; } |
332 | |
333 | |
334 | bool isValid() const { |
335 | return (SimpleTy >= MVT::FIRST_VALUETYPE && |
336 | SimpleTy <= MVT::LAST_VALUETYPE); |
337 | } |
338 | |
339 | |
340 | bool isFloatingPoint() const { |
341 | return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && |
342 | SimpleTy <= MVT::LAST_FP_VALUETYPE) || |
343 | (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE && |
344 | SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) || |
345 | (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE && |
346 | SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE)); |
347 | } |
348 | |
349 | |
350 | bool isInteger() const { |
351 | return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && |
352 | SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || |
353 | (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE && |
354 | SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) || |
355 | (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE && |
356 | SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE)); |
357 | } |
358 | |
359 | |
360 | bool isScalarInteger() const { |
361 | return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && |
362 | SimpleTy <= MVT::LAST_INTEGER_VALUETYPE); |
363 | } |
364 | |
365 | |
366 | bool isVector() const { |
367 | return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE && |
368 | SimpleTy <= MVT::LAST_VECTOR_VALUETYPE); |
369 | } |
370 | |
371 | |
372 | |
373 | bool isScalableVector() const { |
374 | return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE && |
375 | SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE); |
376 | } |
377 | |
378 | bool isFixedLengthVector() const { |
379 | return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE && |
380 | SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE); |
381 | } |
382 | |
383 | |
384 | bool is16BitVector() const { |
385 | return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || |
386 | SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16); |
387 | } |
388 | |
389 | |
390 | bool is32BitVector() const { |
391 | return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || |
392 | SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || |
393 | SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 || |
394 | SimpleTy == MVT::v1f32); |
395 | } |
396 | |
397 | |
398 | bool is64BitVector() const { |
399 | return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || |
400 | SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || |
401 | SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || |
402 | SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 || |
403 | SimpleTy == MVT::v1f64); |
404 | } |
405 | |
406 | |
407 | bool is128BitVector() const { |
408 | return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || |
409 | SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 || |
410 | SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 || |
411 | SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 || |
412 | SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); |
413 | } |
414 | |
415 | |
416 | bool is256BitVector() const { |
417 | return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 || |
418 | SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || |
419 | SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || |
420 | SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 || |
421 | SimpleTy == MVT::v256i1); |
422 | } |
423 | |
424 | |
425 | bool is512BitVector() const { |
426 | return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 || |
427 | SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 || |
428 | SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || |
429 | SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || |
430 | SimpleTy == MVT::v8i64); |
431 | } |
432 | |
433 | |
434 | bool is1024BitVector() const { |
435 | return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || |
436 | SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || |
437 | SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 || |
438 | SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 || |
439 | SimpleTy == MVT::v64bf16); |
440 | } |
441 | |
442 | |
443 | bool is2048BitVector() const { |
444 | return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || |
445 | SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 || |
446 | SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 || |
447 | SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16); |
448 | } |
449 | |
450 | |
451 | bool isOverloaded() const { |
452 | return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || |
453 | SimpleTy == MVT::fAny || SimpleTy == MVT::vAny || |
454 | SimpleTy == MVT::iPTRAny); |
455 | } |
456 | |
457 | |
458 | |
459 | |
460 | MVT changeVectorElementTypeToInteger() const { |
461 | MVT EltTy = getVectorElementType(); |
462 | MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits()); |
463 | MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount()); |
464 | assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && |
465 | "Simple vector VT not representable by simple integer vector VT!"); |
466 | return VecTy; |
467 | } |
468 | |
469 | |
470 | |
471 | MVT changeVectorElementType(MVT EltVT) const { |
472 | MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount()); |
473 | assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && |
474 | "Simple vector VT not representable by simple integer vector VT!"); |
475 | return VecTy; |
476 | } |
477 | |
478 | |
479 | |
480 | |
481 | MVT changeTypeToInteger() { |
482 | if (isVector()) |
483 | return changeVectorElementTypeToInteger(); |
484 | return MVT::getIntegerVT(getSizeInBits()); |
485 | } |
486 | |
487 | |
488 | |
489 | MVT getHalfNumVectorElementsVT() const { |
490 | MVT EltVT = getVectorElementType(); |
491 | auto EltCnt = getVectorElementCount(); |
492 | assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!"); |
493 | return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2)); |
494 | } |
495 | |
496 | |
497 | bool isPow2VectorType() const { |
498 | unsigned NElts = getVectorMinNumElements(); |
499 | return !(NElts & (NElts - 1)); |
500 | } |
501 | |
502 | |
503 | |
504 | MVT getPow2VectorType() const { |
505 | if (isPow2VectorType()) |
506 | return *this; |
507 | |
508 | ElementCount NElts = getVectorElementCount(); |
509 | unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue()); |
510 | NElts = ElementCount::get(NewMinCount, NElts.isScalable()); |
511 | return MVT::getVectorVT(getVectorElementType(), NElts); |
512 | } |
513 | |
514 | |
515 | MVT getScalarType() const { |
516 | return isVector() ? getVectorElementType() : *this; |
517 | } |
518 | |
519 | MVT getVectorElementType() const { |
520 | switch (SimpleTy) { |
521 | default: |
522 | llvm_unreachable("Not a vector MVT!"); |
523 | case v1i1: |
524 | case v2i1: |
525 | case v4i1: |
526 | case v8i1: |
527 | case v16i1: |
528 | case v32i1: |
529 | case v64i1: |
530 | case v128i1: |
531 | case v256i1: |
532 | case v512i1: |
533 | case v1024i1: |
534 | case nxv1i1: |
535 | case nxv2i1: |
536 | case nxv4i1: |
537 | case nxv8i1: |
538 | case nxv16i1: |
539 | case nxv32i1: |
540 | case nxv64i1: return i1; |
541 | case v1i8: |
542 | case v2i8: |
543 | case v4i8: |
544 | case v8i8: |
545 | case v16i8: |
546 | case v32i8: |
547 | case v64i8: |
548 | case v128i8: |
549 | case v256i8: |
550 | case v512i8: |
551 | case v1024i8: |
552 | case nxv1i8: |
553 | case nxv2i8: |
554 | case nxv4i8: |
555 | case nxv8i8: |
556 | case nxv16i8: |
557 | case nxv32i8: |
558 | case nxv64i8: return i8; |
559 | case v1i16: |
560 | case v2i16: |
561 | case v3i16: |
562 | case v4i16: |
563 | case v8i16: |
564 | case v16i16: |
565 | case v32i16: |
566 | case v64i16: |
567 | case v128i16: |
568 | case v256i16: |
569 | case v512i16: |
570 | case nxv1i16: |
571 | case nxv2i16: |
572 | case nxv4i16: |
573 | case nxv8i16: |
574 | case nxv16i16: |
575 | case nxv32i16: return i16; |
576 | case v1i32: |
577 | case v2i32: |
578 | case v3i32: |
579 | case v4i32: |
580 | case v5i32: |
581 | case v6i32: |
582 | case v7i32: |
583 | case v8i32: |
584 | case v16i32: |
585 | case v32i32: |
586 | case v64i32: |
587 | case v128i32: |
588 | case v256i32: |
589 | case v512i32: |
590 | case v1024i32: |
591 | case v2048i32: |
592 | case nxv1i32: |
593 | case nxv2i32: |
594 | case nxv4i32: |
595 | case nxv8i32: |
596 | case nxv16i32: |
597 | case nxv32i32: return i32; |
598 | case v1i64: |
599 | case v2i64: |
600 | case v3i64: |
601 | case v4i64: |
602 | case v8i64: |
603 | case v16i64: |
604 | case v32i64: |
605 | case v64i64: |
606 | case v128i64: |
607 | case v256i64: |
608 | case nxv1i64: |
609 | case nxv2i64: |
610 | case nxv4i64: |
611 | case nxv8i64: |
612 | case nxv16i64: |
613 | case nxv32i64: return i64; |
614 | case v1i128: return i128; |
615 | case v1f16: |
616 | case v2f16: |
617 | case v3f16: |
618 | case v4f16: |
619 | case v8f16: |
620 | case v16f16: |
621 | case v32f16: |
622 | case v64f16: |
623 | case v128f16: |
624 | case v256f16: |
625 | case v512f16: |
626 | case nxv1f16: |
627 | case nxv2f16: |
628 | case nxv4f16: |
629 | case nxv8f16: |
630 | case nxv16f16: |
631 | case nxv32f16: return f16; |
632 | case v2bf16: |
633 | case v3bf16: |
634 | case v4bf16: |
635 | case v8bf16: |
636 | case v16bf16: |
637 | case v32bf16: |
638 | case v64bf16: |
639 | case v128bf16: |
640 | case nxv1bf16: |
641 | case nxv2bf16: |
642 | case nxv4bf16: |
643 | case nxv8bf16: return bf16; |
644 | case v1f32: |
645 | case v2f32: |
646 | case v3f32: |
647 | case v4f32: |
648 | case v5f32: |
649 | case v6f32: |
650 | case v7f32: |
651 | case v8f32: |
652 | case v16f32: |
653 | case v32f32: |
654 | case v64f32: |
655 | case v128f32: |
656 | case v256f32: |
657 | case v512f32: |
658 | case v1024f32: |
659 | case v2048f32: |
660 | case nxv1f32: |
661 | case nxv2f32: |
662 | case nxv4f32: |
663 | case nxv8f32: |
664 | case nxv16f32: return f32; |
665 | case v1f64: |
666 | case v2f64: |
667 | case v3f64: |
668 | case v4f64: |
669 | case v8f64: |
670 | case v16f64: |
671 | case v32f64: |
672 | case v64f64: |
673 | case v128f64: |
674 | case v256f64: |
675 | case nxv1f64: |
676 | case nxv2f64: |
677 | case nxv4f64: |
678 | case nxv8f64: return f64; |
679 | } |
680 | } |
681 | |
682 | |
683 | unsigned getVectorMinNumElements() const { |
684 | switch (SimpleTy) { |
685 | default: |
686 | llvm_unreachable("Not a vector MVT!"); |
687 | case v2048i32: |
688 | case v2048f32: return 2048; |
689 | case v1024i1: |
690 | case v1024i8: |
691 | case v1024i32: |
692 | case v1024f32: return 1024; |
693 | case v512i1: |
694 | case v512i8: |
695 | case v512i16: |
696 | case v512i32: |
697 | case v512f16: |
698 | case v512f32: return 512; |
699 | case v256i1: |
700 | case v256i8: |
701 | case v256i16: |
702 | case v256f16: |
703 | case v256i32: |
704 | case v256i64: |
705 | case v256f32: |
706 | case v256f64: return 256; |
707 | case v128i1: |
708 | case v128i8: |
709 | case v128i16: |
710 | case v128i32: |
711 | case v128i64: |
712 | case v128f16: |
713 | case v128bf16: |
714 | case v128f32: |
715 | case v128f64: return 128; |
716 | case v64i1: |
717 | case v64i8: |
718 | case v64i16: |
719 | case v64i32: |
720 | case v64i64: |
721 | case v64f16: |
722 | case v64bf16: |
723 | case v64f32: |
724 | case v64f64: |
725 | case nxv64i1: |
726 | case nxv64i8: return 64; |
727 | case v32i1: |
728 | case v32i8: |
729 | case v32i16: |
730 | case v32i32: |
731 | case v32i64: |
732 | case v32f16: |
733 | case v32bf16: |
734 | case v32f32: |
735 | case v32f64: |
736 | case nxv32i1: |
737 | case nxv32i8: |
738 | case nxv32i16: |
739 | case nxv32i32: |
740 | case nxv32i64: |
741 | case nxv32f16: return 32; |
742 | case v16i1: |
743 | case v16i8: |
744 | case v16i16: |
745 | case v16i32: |
746 | case v16i64: |
747 | case v16f16: |
748 | case v16bf16: |
749 | case v16f32: |
750 | case v16f64: |
751 | case nxv16i1: |
752 | case nxv16i8: |
753 | case nxv16i16: |
754 | case nxv16i32: |
755 | case nxv16i64: |
756 | case nxv16f16: |
757 | case nxv16f32: return 16; |
758 | case v8i1: |
759 | case v8i8: |
760 | case v8i16: |
761 | case v8i32: |
762 | case v8i64: |
763 | case v8f16: |
764 | case v8bf16: |
765 | case v8f32: |
766 | case v8f64: |
767 | case nxv8i1: |
768 | case nxv8i8: |
769 | case nxv8i16: |
770 | case nxv8i32: |
771 | case nxv8i64: |
772 | case nxv8f16: |
773 | case nxv8bf16: |
774 | case nxv8f32: |
775 | case nxv8f64: return 8; |
776 | case v7i32: |
777 | case v7f32: return 7; |
778 | case v6i32: |
779 | case v6f32: return 6; |
780 | case v5i32: |
781 | case v5f32: return 5; |
782 | case v4i1: |
783 | case v4i8: |
784 | case v4i16: |
785 | case v4i32: |
786 | case v4i64: |
787 | case v4f16: |
788 | case v4bf16: |
789 | case v4f32: |
790 | case v4f64: |
791 | case nxv4i1: |
792 | case nxv4i8: |
793 | case nxv4i16: |
794 | case nxv4i32: |
795 | case nxv4i64: |
796 | case nxv4f16: |
797 | case nxv4bf16: |
798 | case nxv4f32: |
799 | case nxv4f64: return 4; |
800 | case v3i16: |
801 | case v3i32: |
802 | case v3i64: |
803 | case v3f16: |
804 | case v3bf16: |
805 | case v3f32: |
806 | case v3f64: return 3; |
807 | case v2i1: |
808 | case v2i8: |
809 | case v2i16: |
810 | case v2i32: |
811 | case v2i64: |
812 | case v2f16: |
813 | case v2bf16: |
814 | case v2f32: |
815 | case v2f64: |
816 | case nxv2i1: |
817 | case nxv2i8: |
818 | case nxv2i16: |
819 | case nxv2i32: |
820 | case nxv2i64: |
821 | case nxv2f16: |
822 | case nxv2bf16: |
823 | case nxv2f32: |
824 | case nxv2f64: return 2; |
825 | case v1i1: |
826 | case v1i8: |
827 | case v1i16: |
828 | case v1i32: |
829 | case v1i64: |
830 | case v1i128: |
831 | case v1f16: |
832 | case v1f32: |
833 | case v1f64: |
834 | case nxv1i1: |
835 | case nxv1i8: |
836 | case nxv1i16: |
837 | case nxv1i32: |
838 | case nxv1i64: |
839 | case nxv1f16: |
840 | case nxv1bf16: |
841 | case nxv1f32: |
842 | case nxv1f64: return 1; |
843 | } |
844 | } |
845 | |
846 | ElementCount getVectorElementCount() const { |
847 | return ElementCount::get(getVectorMinNumElements(), isScalableVector()); |
848 | } |
849 | |
850 | unsigned getVectorNumElements() const { |
851 | |
852 | return getVectorMinNumElements(); |
853 | } |
854 | |
855 | |
856 | |
857 | |
858 | |
859 | |
860 | TypeSize getSizeInBits() const { |
861 | switch (SimpleTy) { |
862 | default: |
863 | llvm_unreachable("getSizeInBits called on extended MVT."); |
864 | case Other: |
865 | llvm_unreachable("Value type is non-standard value, Other."); |
866 | case iPTR: |
867 | llvm_unreachable("Value type size is target-dependent. Ask TLI."); |
868 | case iPTRAny: |
869 | case iAny: |
870 | case fAny: |
871 | case vAny: |
872 | case Any: |
873 | llvm_unreachable("Value type is overloaded."); |
874 | case token: |
875 | llvm_unreachable("Token type is a sentinel that cannot be used " |
876 | "in codegen and has no size"); |
877 | case Metadata: |
878 | llvm_unreachable("Value type is metadata."); |
879 | case i1: |
880 | case v1i1: return TypeSize::Fixed(1); |
881 | case nxv1i1: return TypeSize::Scalable(1); |
882 | case v2i1: return TypeSize::Fixed(2); |
883 | case nxv2i1: return TypeSize::Scalable(2); |
884 | case v4i1: return TypeSize::Fixed(4); |
885 | case nxv4i1: return TypeSize::Scalable(4); |
886 | case i8 : |
887 | case v1i8: |
888 | case v8i1: return TypeSize::Fixed(8); |
889 | case nxv1i8: |
890 | case nxv8i1: return TypeSize::Scalable(8); |
891 | case i16 : |
892 | case f16: |
893 | case bf16: |
894 | case v16i1: |
895 | case v2i8: |
896 | case v1i16: |
897 | case v1f16: return TypeSize::Fixed(16); |
898 | case nxv16i1: |
899 | case nxv2i8: |
900 | case nxv1i16: |
901 | case nxv1bf16: |
902 | case nxv1f16: return TypeSize::Scalable(16); |
903 | case f32 : |
904 | case i32 : |
905 | case v32i1: |
906 | case v4i8: |
907 | case v2i16: |
908 | case v2f16: |
909 | case v2bf16: |
910 | case v1f32: |
911 | case v1i32: return TypeSize::Fixed(32); |
912 | case nxv32i1: |
913 | case nxv4i8: |
914 | case nxv2i16: |
915 | case nxv1i32: |
916 | case nxv2f16: |
917 | case nxv2bf16: |
918 | case nxv1f32: return TypeSize::Scalable(32); |
919 | case v3i16: |
920 | case v3f16: |
921 | case v3bf16: return TypeSize::Fixed(48); |
922 | case x86mmx: |
923 | case f64 : |
924 | case i64 : |
925 | case v64i1: |
926 | case v8i8: |
927 | case v4i16: |
928 | case v2i32: |
929 | case v1i64: |
930 | case v4f16: |
931 | case v4bf16: |
932 | case v2f32: |
933 | case v1f64: return TypeSize::Fixed(64); |
934 | case nxv64i1: |
935 | case nxv8i8: |
936 | case nxv4i16: |
937 | case nxv2i32: |
938 | case nxv1i64: |
939 | case nxv4f16: |
940 | case nxv4bf16: |
941 | case nxv2f32: |
942 | case nxv1f64: return TypeSize::Scalable(64); |
943 | case f80 : return TypeSize::Fixed(80); |
944 | case v3i32: |
945 | case v3f32: return TypeSize::Fixed(96); |
946 | case f128: |
947 | case ppcf128: |
948 | case i128: |
949 | case v128i1: |
950 | case v16i8: |
951 | case v8i16: |
952 | case v4i32: |
953 | case v2i64: |
954 | case v1i128: |
955 | case v8f16: |
956 | case v8bf16: |
957 | case v4f32: |
958 | case v2f64: return TypeSize::Fixed(128); |
959 | case nxv16i8: |
960 | case nxv8i16: |
961 | case nxv4i32: |
962 | case nxv2i64: |
963 | case nxv8f16: |
964 | case nxv8bf16: |
965 | case nxv4f32: |
966 | case nxv2f64: return TypeSize::Scalable(128); |
967 | case v5i32: |
968 | case v5f32: return TypeSize::Fixed(160); |
969 | case v6i32: |
970 | case v3i64: |
971 | case v6f32: |
972 | case v3f64: return TypeSize::Fixed(192); |
973 | case v7i32: |
974 | case v7f32: return TypeSize::Fixed(224); |
975 | case v256i1: |
976 | case v32i8: |
977 | case v16i16: |
978 | case v8i32: |
979 | case v4i64: |
980 | case v16f16: |
981 | case v16bf16: |
982 | case v8f32: |
983 | case v4f64: return TypeSize::Fixed(256); |
984 | case nxv32i8: |
985 | case nxv16i16: |
986 | case nxv8i32: |
987 | case nxv4i64: |
988 | case nxv16f16: |
989 | case nxv8f32: |
990 | case nxv4f64: return TypeSize::Scalable(256); |
991 | case i64x8: |
992 | case v512i1: |
993 | case v64i8: |
994 | case v32i16: |
995 | case v16i32: |
996 | case v8i64: |
997 | case v32f16: |
998 | case v32bf16: |
999 | case v16f32: |
1000 | case v8f64: return TypeSize::Fixed(512); |
1001 | case nxv64i8: |
1002 | case nxv32i16: |
1003 | case nxv16i32: |
1004 | case nxv8i64: |
1005 | case nxv32f16: |
1006 | case nxv16f32: |
1007 | case nxv8f64: return TypeSize::Scalable(512); |
1008 | case v1024i1: |
1009 | case v128i8: |
1010 | case v64i16: |
1011 | case v32i32: |
1012 | case v16i64: |
1013 | case v64f16: |
1014 | case v64bf16: |
1015 | case v32f32: |
1016 | case v16f64: return TypeSize::Fixed(1024); |
1017 | case nxv32i32: |
1018 | case nxv16i64: return TypeSize::Scalable(1024); |
1019 | case v256i8: |
1020 | case v128i16: |
1021 | case v64i32: |
1022 | case v32i64: |
1023 | case v128f16: |
1024 | case v128bf16: |
1025 | case v64f32: |
1026 | case v32f64: return TypeSize::Fixed(2048); |
1027 | case nxv32i64: return TypeSize::Scalable(2048); |
1028 | case v512i8: |
1029 | case v256i16: |
1030 | case v128i32: |
1031 | case v64i64: |
1032 | case v256f16: |
1033 | case v128f32: |
1034 | case v64f64: return TypeSize::Fixed(4096); |
1035 | case v1024i8: |
1036 | case v512i16: |
1037 | case v256i32: |
1038 | case v128i64: |
1039 | case v512f16: |
1040 | case v256f32: |
1041 | case x86amx: |
1042 | case v128f64: return TypeSize::Fixed(8192); |
1043 | case v512i32: |
1044 | case v256i64: |
1045 | case v512f32: |
1046 | case v256f64: return TypeSize::Fixed(16384); |
1047 | case v1024i32: |
1048 | case v1024f32: return TypeSize::Fixed(32768); |
1049 | case v2048i32: |
1050 | case v2048f32: return TypeSize::Fixed(65536); |
1051 | case funcref: |
1052 | case externref: return TypeSize::Fixed(0); |
1053 | } |
1054 | } |
1055 | |
1056 | |
1057 | |
1058 | uint64_t getFixedSizeInBits() const { |
1059 | return getSizeInBits().getFixedSize(); |
1060 | } |
1061 | |
1062 | uint64_t getScalarSizeInBits() const { |
1063 | return getScalarType().getSizeInBits().getFixedSize(); |
1064 | } |
1065 | |
1066 | |
1067 | |
1068 | |
1069 | |
1070 | |
1071 | |
1072 | TypeSize getStoreSize() const { |
1073 | TypeSize BaseSize = getSizeInBits(); |
1074 | return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; |
1075 | } |
1076 | |
1077 | |
1078 | |
1079 | |
1080 | |
1081 | |
1082 | |
1083 | TypeSize getStoreSizeInBits() const { |
1084 | return getStoreSize() * 8; |
1085 | } |
1086 | |
1087 | |
1088 | |
1089 | bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); } |
1090 | |
1091 | |
1092 | bool knownBitsGT(MVT VT) const { |
1093 | return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits()); |
1094 | } |
1095 | |
1096 | |
1097 | |
1098 | bool knownBitsGE(MVT VT) const { |
1099 | return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits()); |
1100 | } |
1101 | |
1102 | |
1103 | bool knownBitsLT(MVT VT) const { |
1104 | return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits()); |
1105 | } |
1106 | |
1107 | |
1108 | |
1109 | bool knownBitsLE(MVT VT) const { |
1110 | return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits()); |
1111 | } |
1112 | |
1113 | |
1114 | bool bitsGT(MVT VT) const { |
1115 | assert(isScalableVector() == VT.isScalableVector() && |
1116 | "Comparison between scalable and fixed types"); |
1117 | return knownBitsGT(VT); |
1118 | } |
1119 | |
1120 | |
1121 | bool bitsGE(MVT VT) const { |
1122 | assert(isScalableVector() == VT.isScalableVector() && |
1123 | "Comparison between scalable and fixed types"); |
1124 | return knownBitsGE(VT); |
1125 | } |
1126 | |
1127 | |
1128 | bool bitsLT(MVT VT) const { |
1129 | assert(isScalableVector() == VT.isScalableVector() && |
1130 | "Comparison between scalable and fixed types"); |
1131 | return knownBitsLT(VT); |
1132 | } |
1133 | |
1134 | |
1135 | bool bitsLE(MVT VT) const { |
1136 | assert(isScalableVector() == VT.isScalableVector() && |
1137 | "Comparison between scalable and fixed types"); |
1138 | return knownBitsLE(VT); |
1139 | } |
1140 | |
1141 | static MVT getFloatingPointVT(unsigned BitWidth) { |
1142 | switch (BitWidth) { |
1143 | default: |
1144 | llvm_unreachable("Bad bit width!"); |
1145 | case 16: |
1146 | return MVT::f16; |
1147 | case 32: |
1148 | return MVT::f32; |
1149 | case 64: |
1150 | return MVT::f64; |
1151 | case 80: |
1152 | return MVT::f80; |
1153 | case 128: |
1154 | return MVT::f128; |
1155 | } |
1156 | } |
1157 | |
1158 | static MVT getIntegerVT(unsigned BitWidth) { |
1159 | switch (BitWidth) { |
1160 | default: |
1161 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1162 | case 1: |
1163 | return MVT::i1; |
1164 | case 8: |
1165 | return MVT::i8; |
1166 | case 16: |
1167 | return MVT::i16; |
1168 | case 32: |
1169 | return MVT::i32; |
1170 | case 64: |
1171 | return MVT::i64; |
1172 | case 128: |
1173 | return MVT::i128; |
1174 | } |
1175 | } |
1176 | |
1177 | static MVT getVectorVT(MVT VT, unsigned NumElements) { |
1178 | switch (VT.SimpleTy) { |
1179 | default: |
1180 | break; |
1181 | case MVT::i1: |
1182 | if (NumElements == 1) return MVT::v1i1; |
1183 | if (NumElements == 2) return MVT::v2i1; |
1184 | if (NumElements == 4) return MVT::v4i1; |
1185 | if (NumElements == 8) return MVT::v8i1; |
1186 | if (NumElements == 16) return MVT::v16i1; |
1187 | if (NumElements == 32) return MVT::v32i1; |
1188 | if (NumElements == 64) return MVT::v64i1; |
1189 | if (NumElements == 128) return MVT::v128i1; |
1190 | if (NumElements == 256) return MVT::v256i1; |
1191 | if (NumElements == 512) return MVT::v512i1; |
1192 | if (NumElements == 1024) return MVT::v1024i1; |
1193 | break; |
1194 | case MVT::i8: |
1195 | if (NumElements == 1) return MVT::v1i8; |
1196 | if (NumElements == 2) return MVT::v2i8; |
1197 | if (NumElements == 4) return MVT::v4i8; |
1198 | if (NumElements == 8) return MVT::v8i8; |
1199 | if (NumElements == 16) return MVT::v16i8; |
1200 | if (NumElements == 32) return MVT::v32i8; |
1201 | if (NumElements == 64) return MVT::v64i8; |
1202 | if (NumElements == 128) return MVT::v128i8; |
1203 | if (NumElements == 256) return MVT::v256i8; |
1204 | if (NumElements == 512) return MVT::v512i8; |
1205 | if (NumElements == 1024) return MVT::v1024i8; |
1206 | break; |
1207 | case MVT::i16: |
1208 | if (NumElements == 1) return MVT::v1i16; |
1209 | if (NumElements == 2) return MVT::v2i16; |
1210 | if (NumElements == 3) return MVT::v3i16; |
1211 | if (NumElements == 4) return MVT::v4i16; |
1212 | if (NumElements == 8) return MVT::v8i16; |
1213 | if (NumElements == 16) return MVT::v16i16; |
1214 | if (NumElements == 32) return MVT::v32i16; |
1215 | if (NumElements == 64) return MVT::v64i16; |
1216 | if (NumElements == 128) return MVT::v128i16; |
1217 | if (NumElements == 256) return MVT::v256i16; |
1218 | if (NumElements == 512) return MVT::v512i16; |
1219 | break; |
1220 | case MVT::i32: |
1221 | if (NumElements == 1) return MVT::v1i32; |
1222 | if (NumElements == 2) return MVT::v2i32; |
1223 | if (NumElements == 3) return MVT::v3i32; |
1224 | if (NumElements == 4) return MVT::v4i32; |
1225 | if (NumElements == 5) return MVT::v5i32; |
1226 | if (NumElements == 6) return MVT::v6i32; |
1227 | if (NumElements == 7) return MVT::v7i32; |
1228 | if (NumElements == 8) return MVT::v8i32; |
1229 | if (NumElements == 16) return MVT::v16i32; |
1230 | if (NumElements == 32) return MVT::v32i32; |
1231 | if (NumElements == 64) return MVT::v64i32; |
1232 | if (NumElements == 128) return MVT::v128i32; |
1233 | if (NumElements == 256) return MVT::v256i32; |
1234 | if (NumElements == 512) return MVT::v512i32; |
1235 | if (NumElements == 1024) return MVT::v1024i32; |
1236 | if (NumElements == 2048) return MVT::v2048i32; |
1237 | break; |
1238 | case MVT::i64: |
1239 | if (NumElements == 1) return MVT::v1i64; |
1240 | if (NumElements == 2) return MVT::v2i64; |
1241 | if (NumElements == 3) return MVT::v3i64; |
1242 | if (NumElements == 4) return MVT::v4i64; |
1243 | if (NumElements == 8) return MVT::v8i64; |
1244 | if (NumElements == 16) return MVT::v16i64; |
1245 | if (NumElements == 32) return MVT::v32i64; |
1246 | if (NumElements == 64) return MVT::v64i64; |
1247 | if (NumElements == 128) return MVT::v128i64; |
1248 | if (NumElements == 256) return MVT::v256i64; |
1249 | break; |
1250 | case MVT::i128: |
1251 | if (NumElements == 1) return MVT::v1i128; |
1252 | break; |
1253 | case MVT::f16: |
1254 | if (NumElements == 1) return MVT::v1f16; |
1255 | if (NumElements == 2) return MVT::v2f16; |
1256 | if (NumElements == 3) return MVT::v3f16; |
1257 | if (NumElements == 4) return MVT::v4f16; |
1258 | if (NumElements == 8) return MVT::v8f16; |
1259 | if (NumElements == 16) return MVT::v16f16; |
1260 | if (NumElements == 32) return MVT::v32f16; |
1261 | if (NumElements == 64) return MVT::v64f16; |
1262 | if (NumElements == 128) return MVT::v128f16; |
1263 | if (NumElements == 256) return MVT::v256f16; |
1264 | if (NumElements == 512) return MVT::v512f16; |
1265 | break; |
1266 | case MVT::bf16: |
1267 | if (NumElements == 2) return MVT::v2bf16; |
1268 | if (NumElements == 3) return MVT::v3bf16; |
1269 | if (NumElements == 4) return MVT::v4bf16; |
1270 | if (NumElements == 8) return MVT::v8bf16; |
1271 | if (NumElements == 16) return MVT::v16bf16; |
1272 | if (NumElements == 32) return MVT::v32bf16; |
1273 | if (NumElements == 64) return MVT::v64bf16; |
1274 | if (NumElements == 128) return MVT::v128bf16; |
1275 | break; |
1276 | case MVT::f32: |
1277 | if (NumElements == 1) return MVT::v1f32; |
1278 | if (NumElements == 2) return MVT::v2f32; |
1279 | if (NumElements == 3) return MVT::v3f32; |
1280 | if (NumElements == 4) return MVT::v4f32; |
1281 | if (NumElements == 5) return MVT::v5f32; |
1282 | if (NumElements == 6) return MVT::v6f32; |
1283 | if (NumElements == 7) return MVT::v7f32; |
1284 | if (NumElements == 8) return MVT::v8f32; |
1285 | if (NumElements == 16) return MVT::v16f32; |
1286 | if (NumElements == 32) return MVT::v32f32; |
1287 | if (NumElements == 64) return MVT::v64f32; |
1288 | if (NumElements == 128) return MVT::v128f32; |
1289 | if (NumElements == 256) return MVT::v256f32; |
1290 | if (NumElements == 512) return MVT::v512f32; |
1291 | if (NumElements == 1024) return MVT::v1024f32; |
1292 | if (NumElements == 2048) return MVT::v2048f32; |
1293 | break; |
1294 | case MVT::f64: |
1295 | if (NumElements == 1) return MVT::v1f64; |
1296 | if (NumElements == 2) return MVT::v2f64; |
1297 | if (NumElements == 3) return MVT::v3f64; |
1298 | if (NumElements == 4) return MVT::v4f64; |
1299 | if (NumElements == 8) return MVT::v8f64; |
1300 | if (NumElements == 16) return MVT::v16f64; |
1301 | if (NumElements == 32) return MVT::v32f64; |
1302 | if (NumElements == 64) return MVT::v64f64; |
1303 | if (NumElements == 128) return MVT::v128f64; |
1304 | if (NumElements == 256) return MVT::v256f64; |
1305 | break; |
1306 | } |
1307 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1308 | } |
1309 | |
1310 | static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { |
1311 | switch(VT.SimpleTy) { |
1312 | default: |
1313 | break; |
1314 | case MVT::i1: |
1315 | if (NumElements == 1) return MVT::nxv1i1; |
1316 | if (NumElements == 2) return MVT::nxv2i1; |
1317 | if (NumElements == 4) return MVT::nxv4i1; |
1318 | if (NumElements == 8) return MVT::nxv8i1; |
1319 | if (NumElements == 16) return MVT::nxv16i1; |
1320 | if (NumElements == 32) return MVT::nxv32i1; |
1321 | if (NumElements == 64) return MVT::nxv64i1; |
1322 | break; |
1323 | case MVT::i8: |
1324 | if (NumElements == 1) return MVT::nxv1i8; |
1325 | if (NumElements == 2) return MVT::nxv2i8; |
1326 | if (NumElements == 4) return MVT::nxv4i8; |
1327 | if (NumElements == 8) return MVT::nxv8i8; |
1328 | if (NumElements == 16) return MVT::nxv16i8; |
1329 | if (NumElements == 32) return MVT::nxv32i8; |
1330 | if (NumElements == 64) return MVT::nxv64i8; |
1331 | break; |
1332 | case MVT::i16: |
1333 | if (NumElements == 1) return MVT::nxv1i16; |
1334 | if (NumElements == 2) return MVT::nxv2i16; |
1335 | if (NumElements == 4) return MVT::nxv4i16; |
1336 | if (NumElements == 8) return MVT::nxv8i16; |
1337 | if (NumElements == 16) return MVT::nxv16i16; |
1338 | if (NumElements == 32) return MVT::nxv32i16; |
1339 | break; |
1340 | case MVT::i32: |
1341 | if (NumElements == 1) return MVT::nxv1i32; |
1342 | if (NumElements == 2) return MVT::nxv2i32; |
1343 | if (NumElements == 4) return MVT::nxv4i32; |
1344 | if (NumElements == 8) return MVT::nxv8i32; |
1345 | if (NumElements == 16) return MVT::nxv16i32; |
1346 | if (NumElements == 32) return MVT::nxv32i32; |
1347 | break; |
1348 | case MVT::i64: |
1349 | if (NumElements == 1) return MVT::nxv1i64; |
1350 | if (NumElements == 2) return MVT::nxv2i64; |
1351 | if (NumElements == 4) return MVT::nxv4i64; |
1352 | if (NumElements == 8) return MVT::nxv8i64; |
1353 | if (NumElements == 16) return MVT::nxv16i64; |
1354 | if (NumElements == 32) return MVT::nxv32i64; |
1355 | break; |
1356 | case MVT::f16: |
1357 | if (NumElements == 1) return MVT::nxv1f16; |
1358 | if (NumElements == 2) return MVT::nxv2f16; |
1359 | if (NumElements == 4) return MVT::nxv4f16; |
1360 | if (NumElements == 8) return MVT::nxv8f16; |
1361 | if (NumElements == 16) return MVT::nxv16f16; |
1362 | if (NumElements == 32) return MVT::nxv32f16; |
1363 | break; |
1364 | case MVT::bf16: |
1365 | if (NumElements == 1) return MVT::nxv1bf16; |
1366 | if (NumElements == 2) return MVT::nxv2bf16; |
1367 | if (NumElements == 4) return MVT::nxv4bf16; |
1368 | if (NumElements == 8) return MVT::nxv8bf16; |
1369 | break; |
1370 | case MVT::f32: |
1371 | if (NumElements == 1) return MVT::nxv1f32; |
1372 | if (NumElements == 2) return MVT::nxv2f32; |
1373 | if (NumElements == 4) return MVT::nxv4f32; |
1374 | if (NumElements == 8) return MVT::nxv8f32; |
1375 | if (NumElements == 16) return MVT::nxv16f32; |
1376 | break; |
1377 | case MVT::f64: |
1378 | if (NumElements == 1) return MVT::nxv1f64; |
1379 | if (NumElements == 2) return MVT::nxv2f64; |
1380 | if (NumElements == 4) return MVT::nxv4f64; |
1381 | if (NumElements == 8) return MVT::nxv8f64; |
1382 | break; |
1383 | } |
1384 | return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); |
1385 | } |
1386 | |
1387 | static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) { |
1388 | if (IsScalable) |
1389 | return getScalableVectorVT(VT, NumElements); |
1390 | return getVectorVT(VT, NumElements); |
1391 | } |
1392 | |
1393 | static MVT getVectorVT(MVT VT, ElementCount EC) { |
1394 | if (EC.isScalable()) |
1395 | return getScalableVectorVT(VT, EC.getKnownMinValue()); |
1396 | return getVectorVT(VT, EC.getKnownMinValue()); |
1397 | } |
1398 | |
1399 | |
1400 | |
1401 | |
1402 | static MVT getVT(Type *Ty, bool HandleUnknown = false); |
1403 | |
1404 | public: |
1405 | |
1406 | |
1407 | static auto all_valuetypes() { |
1408 | return seq_inclusive(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE); |
1409 | } |
1410 | |
1411 | static auto integer_valuetypes() { |
1412 | return seq_inclusive(MVT::FIRST_INTEGER_VALUETYPE, |
1413 | MVT::LAST_INTEGER_VALUETYPE); |
1414 | } |
1415 | |
1416 | static auto fp_valuetypes() { |
1417 | return seq_inclusive(MVT::FIRST_FP_VALUETYPE, MVT::LAST_FP_VALUETYPE); |
1418 | } |
1419 | |
1420 | static auto vector_valuetypes() { |
1421 | return seq_inclusive(MVT::FIRST_VECTOR_VALUETYPE, |
1422 | MVT::LAST_VECTOR_VALUETYPE); |
1423 | } |
1424 | |
1425 | static auto fixedlen_vector_valuetypes() { |
1426 | return seq_inclusive(MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE, |
1427 | MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE); |
1428 | } |
1429 | |
1430 | static auto scalable_vector_valuetypes() { |
1431 | return seq_inclusive(MVT::FIRST_SCALABLE_VECTOR_VALUETYPE, |
1432 | MVT::LAST_SCALABLE_VECTOR_VALUETYPE); |
1433 | } |
1434 | |
1435 | static auto integer_fixedlen_vector_valuetypes() { |
1436 | return seq_inclusive(MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, |
1437 | MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE); |
1438 | } |
1439 | |
1440 | static auto fp_fixedlen_vector_valuetypes() { |
1441 | return seq_inclusive(MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, |
1442 | MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE); |
1443 | } |
1444 | |
1445 | static auto integer_scalable_vector_valuetypes() { |
1446 | return seq_inclusive(MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, |
1447 | MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE); |
1448 | } |
1449 | |
1450 | static auto fp_scalable_vector_valuetypes() { |
1451 | return seq_inclusive(MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE, |
1452 | MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE); |
1453 | } |
1454 | |
1455 | }; |
1456 | |
1457 | } |
1458 | |
1459 | #endif // LLVM_SUPPORT_MACHINEVALUETYPE_H |