/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR/AVRISelLowering.cpp

Bug Summary

File:	build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR/AVRISelLowering.cpp
Warning:	line 1149, column 13 1st function call argument is an uninitialized value

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name AVRISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-15/lib/clang/15.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AVR -I /build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR -I include -I /build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-15/lib/clang/15.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-03-20-232535-108605-1 -x c++ /build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR/AVRISelLowering.cpp

/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/lib/Target/AVR/AVRISelLowering.cpp

→

1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//

14#include "AVRISelLowering.h"

16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"

27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"

33namespace llvm {

35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
                                   const AVRSubtarget &STI)
  : TargetLowering(TM), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);

// Compute derived properties from the register classes.
computeRegisterProperties(Subtarget.getRegisterInfo());

setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrOneBooleanContent);
setSchedulingPreference(Sched::RegPressure);
setStackPointerRegisterToSaveRestore(AVR::SP);
setSupportsUnalignedAtomics(true);

setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
setOperationAction(ISD::BlockAddress, MVT::i16, Custom);

setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);

for (MVT VT : MVT::integer_valuetypes()) {
  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
    setLoadExtAction(N, VT, MVT::i1, Promote);
    setLoadExtAction(N, VT, MVT::i8, Expand);
  }
}

setTruncStoreAction(MVT::i16, MVT::i8, Expand);

for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::ADDC, VT, Legal);
  setOperationAction(ISD::SUBC, VT, Legal);
  setOperationAction(ISD::ADDE, VT, Legal);
  setOperationAction(ISD::SUBE, VT, Legal);
}

// sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
// revert into a sub since we don't have an add with immediate instruction.
setOperationAction(ISD::ADD, MVT::i32, Custom);
setOperationAction(ISD::ADD, MVT::i64, Custom);

// our shift instructions are only able to shift 1 bit at a time, so handle
// this in a custom way.
setOperationAction(ISD::SRA, MVT::i8, Custom);
setOperationAction(ISD::SHL, MVT::i8, Custom);
setOperationAction(ISD::SRL, MVT::i8, Custom);
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::SHL, MVT::i16, Custom);
setOperationAction(ISD::SRL, MVT::i16, Custom);
setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);

setOperationAction(ISD::ROTL, MVT::i8, Custom);
setOperationAction(ISD::ROTL, MVT::i16, Expand);
setOperationAction(ISD::ROTR, MVT::i8, Custom);
setOperationAction(ISD::ROTR, MVT::i16, Expand);

setOperationAction(ISD::BR_CC, MVT::i8, Custom);
setOperationAction(ISD::BR_CC, MVT::i16, Custom);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::i64, Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Expand);

setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
setOperationAction(ISD::SETCC, MVT::i8, Custom);
setOperationAction(ISD::SETCC, MVT::i16, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::i64, Custom);
setOperationAction(ISD::SELECT, MVT::i8, Expand);
setOperationAction(ISD::SELECT, MVT::i16, Expand);

setOperationAction(ISD::BSWAP, MVT::i16, Expand);

// Add support for postincrement and predecrement load/stores.
setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal);
setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal);
setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);

setOperationAction(ISD::BR_JT, MVT::Other, Expand);

setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
setOperationAction(ISD::VAARG, MVT::Other, Expand);
setOperationAction(ISD::VACOPY, MVT::Other, Expand);

// Atomic operations which must be lowered to rtlib calls
for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::ATOMIC_SWAP, VT, Expand);
  setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);
  setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand);
  setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand);
  setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand);
  setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
  setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand);
}

// Division/remainder
setOperationAction(ISD::UDIV, MVT::i8, Expand);
setOperationAction(ISD::UDIV, MVT::i16, Expand);
setOperationAction(ISD::UREM, MVT::i8, Expand);
setOperationAction(ISD::UREM, MVT::i16, Expand);
setOperationAction(ISD::SDIV, MVT::i8, Expand);
setOperationAction(ISD::SDIV, MVT::i16, Expand);
setOperationAction(ISD::SREM, MVT::i8, Expand);
setOperationAction(ISD::SREM, MVT::i16, Expand);

// Make division and modulus custom
setOperationAction(ISD::UDIVREM, MVT::i8, Custom);
setOperationAction(ISD::UDIVREM, MVT::i16, Custom);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::SDIVREM, MVT::i8, Custom);
setOperationAction(ISD::SDIVREM, MVT::i16, Custom);
setOperationAction(ISD::SDIVREM, MVT::i32, Custom);

// Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
setOperationAction(ISD::MUL, MVT::i8, Expand);
setOperationAction(ISD::MUL, MVT::i16, Expand);

// Expand 16 bit multiplications.
setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);

// Expand multiplications to libcalls when there is
// no hardware MUL.
if (!Subtarget.supportsMultiplication()) {
  setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
  setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
}

for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::MULHS, VT, Expand);
  setOperationAction(ISD::MULHU, VT, Expand);
}

for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::CTPOP, VT, Expand);
  setOperationAction(ISD::CTLZ, VT, Expand);
  setOperationAction(ISD::CTTZ, VT, Expand);
}

for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
  // TODO: The generated code is pretty poor. Investigate using the
  // same "shift and subtract with carry" trick that we do for
  // extending 8-bit to 16-bit. This may require infrastructure
  // improvements in how we treat 16-bit "registers" to be feasible.
}

// Division rtlib functions (not supported), use divmod functions instead
setLibcallName(RTLIB::SDIV_I8, nullptr);
setLibcallName(RTLIB::SDIV_I16, nullptr);
setLibcallName(RTLIB::SDIV_I32, nullptr);
setLibcallName(RTLIB::UDIV_I8, nullptr);
setLibcallName(RTLIB::UDIV_I16, nullptr);
setLibcallName(RTLIB::UDIV_I32, nullptr);

// Modulus rtlib functions (not supported), use divmod functions instead
setLibcallName(RTLIB::SREM_I8, nullptr);
setLibcallName(RTLIB::SREM_I16, nullptr);
setLibcallName(RTLIB::SREM_I32, nullptr);
setLibcallName(RTLIB::UREM_I8, nullptr);
setLibcallName(RTLIB::UREM_I16, nullptr);
setLibcallName(RTLIB::UREM_I32, nullptr);

// Division and modulus rtlib functions
setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");

// Several of the runtime library functions use a special calling conv
setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN);
setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);

// Trigonometric rtlib functions
setLibcallName(RTLIB::SIN_F32, "sin");
setLibcallName(RTLIB::COS_F32, "cos");

setMinFunctionAlignment(Align(2));
setMinimumJumpTableEntries(UINT_MAX(2147483647 *2U +1U));
232}

234const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235#define NODE(name)                                                             \
case AVRISD::name:                                                           \
  return #name

switch (Opcode) {
default:
  return nullptr;
  NODE(RET_FLAG);
  NODE(RETI_FLAG);
  NODE(CALL);
  NODE(WRAPPER);
  NODE(LSL);
  NODE(LSR);
  NODE(ROL);
  NODE(ROR);
  NODE(ASR);
  NODE(LSLLOOP);
  NODE(LSRLOOP);
  NODE(ROLLOOP);
  NODE(RORLOOP);
  NODE(ASRLOOP);
  NODE(BRCOND);
  NODE(CMP);
  NODE(CMPC);
  NODE(TST);
  NODE(SELECT_CC);
261#undef NODE
}
263}

265EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                        EVT VT) const {
assert(!VT.isVector() && "No AVR SetCC type for vectors!")(static_cast <bool> (!VT.isVector() && "No AVR SetCC type for vectors!"
) ? void (0) : __assert_fail ("!VT.isVector() && \"No AVR SetCC type for vectors!\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 267, __extension__
 __PRETTY_FUNCTION__));
return MVT::i8;
269}

271SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
//: TODO: this function has to be completely rewritten to produce optimal
// code, for now it's producing very long but correct code.
unsigned Opc8;
const SDNode *N = Op.getNode();
EVT VT = Op.getValueType();
SDLoc dl(N);
assert(isPowerOf2_32(VT.getSizeInBits()) &&(static_cast <bool> (isPowerOf2_32(VT.getSizeInBits()) &&
 "Expected power-of-2 shift amount") ? void (0) : __assert_fail
 ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 279, __extension__
 __PRETTY_FUNCTION__))
       "Expected power-of-2 shift amount")(static_cast <bool> (isPowerOf2_32(VT.getSizeInBits()) &&
 "Expected power-of-2 shift amount") ? void (0) : __assert_fail
 ("isPowerOf2_32(VT.getSizeInBits()) && \"Expected power-of-2 shift amount\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 279, __extension__
 __PRETTY_FUNCTION__));

// Expand non-constant shifts to loops.
if (!isa<ConstantSDNode>(N->getOperand(1))) {
  switch (Op.getOpcode()) {
  default:
    llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 285);
  case ISD::SHL:
    return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
                       N->getOperand(1));
  case ISD::SRL:
    return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
                       N->getOperand(1));
  case ISD::ROTL: {
    SDValue Amt = N->getOperand(1);
    EVT AmtVT = Amt.getValueType();
    Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
                      DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
    return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
  }
  case ISD::ROTR: {
    SDValue Amt = N->getOperand(1);
    EVT AmtVT = Amt.getValueType();
    Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
                      DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
    return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
  }
  case ISD::SRA:
    return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
                       N->getOperand(1));
  }
}

uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
SDValue Victim = N->getOperand(0);

switch (Op.getOpcode()) {
case ISD::SRA:
  Opc8 = AVRISD::ASR;
  break;
case ISD::ROTL:
  Opc8 = AVRISD::ROL;
  ShiftAmount = ShiftAmount % VT.getSizeInBits();
  break;
case ISD::ROTR:
  Opc8 = AVRISD::ROR;
  ShiftAmount = ShiftAmount % VT.getSizeInBits();
  break;
case ISD::SRL:
  Opc8 = AVRISD::LSR;
  break;
case ISD::SHL:
  Opc8 = AVRISD::LSL;
  break;
default:
  llvm_unreachable("Invalid shift opcode")::llvm::llvm_unreachable_internal("Invalid shift opcode", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 334);
}

// Optimize int8/int16 shifts.
if (VT.getSizeInBits() == 8) {
  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
    // Optimize LSL when 4 <= ShiftAmount <= 6.
    Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
    Victim =
        DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
    ShiftAmount -= 4;
  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
             ShiftAmount < 7) {
    // Optimize LSR when 4 <= ShiftAmount <= 6.
    Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
    Victim =
        DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
    ShiftAmount -= 4;
  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
    // Optimize LSL when ShiftAmount == 7.
    Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
                         DAG.getConstant(7, dl, VT));
    ShiftAmount = 0;
  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
    // Optimize LSR when ShiftAmount == 7.
    Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
                         DAG.getConstant(7, dl, VT));
    ShiftAmount = 0;
  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
    // Optimize ASR when ShiftAmount == 6.
    Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                         DAG.getConstant(6, dl, VT));
    ShiftAmount = 0;
  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
    // Optimize ASR when ShiftAmount == 7.
    Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                         DAG.getConstant(7, dl, VT));
    ShiftAmount = 0;
  }
} else if (VT.getSizeInBits() == 16) {
  if (4 <= ShiftAmount && ShiftAmount < 8)
    switch (Op.getOpcode()) {
    case ISD::SHL:
      Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
                           DAG.getConstant(4, dl, VT));
      ShiftAmount -= 4;
      break;
    case ISD::SRL:
      Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
                           DAG.getConstant(4, dl, VT));
      ShiftAmount -= 4;
      break;
    default:
      break;
    }
  else if (8 <= ShiftAmount && ShiftAmount < 12)
    switch (Op.getOpcode()) {
    case ISD::SHL:
      Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
                           DAG.getConstant(8, dl, VT));
      ShiftAmount -= 8;
      // Only operate on the higher byte for remaining shift bits.
      Opc8 = AVRISD::LSLHI;
      break;
    case ISD::SRL:
      Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
                           DAG.getConstant(8, dl, VT));
      ShiftAmount -= 8;
      // Only operate on the lower byte for remaining shift bits.
      Opc8 = AVRISD::LSRLO;
      break;
    case ISD::SRA:
      Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
                           DAG.getConstant(8, dl, VT));
      ShiftAmount -= 8;
      // Only operate on the lower byte for remaining shift bits.
      Opc8 = AVRISD::ASRLO;
      break;
    default:
      break;
    }
  else if (12 <= ShiftAmount)
    switch (Op.getOpcode()) {
    case ISD::SHL:
      Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
                           DAG.getConstant(12, dl, VT));
      ShiftAmount -= 12;
      // Only operate on the higher byte for remaining shift bits.
      Opc8 = AVRISD::LSLHI;
      break;
    case ISD::SRL:
      Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
                           DAG.getConstant(12, dl, VT));
      ShiftAmount -= 12;
      // Only operate on the lower byte for remaining shift bits.
      Opc8 = AVRISD::LSRLO;
      break;
    case ISD::SRA:
      Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
                           DAG.getConstant(8, dl, VT));
      ShiftAmount -= 8;
      // Only operate on the lower byte for remaining shift bits.
      Opc8 = AVRISD::ASRLO;
      break;
    default:
      break;
    }
}

while (ShiftAmount--) {
  Victim = DAG.getNode(Opc8, dl, VT, Victim);
}

return Victim;
448}

450SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
unsigned Opcode = Op->getOpcode();
assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&(static_cast <bool> ((Opcode == ISD::SDIVREM || Opcode ==
 ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering"
) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 453, __extension__
 __PRETTY_FUNCTION__))
       "Invalid opcode for Div/Rem lowering")(static_cast <bool> ((Opcode == ISD::SDIVREM || Opcode ==
 ISD::UDIVREM) && "Invalid opcode for Div/Rem lowering"
) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && \"Invalid opcode for Div/Rem lowering\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 453, __extension__
 __PRETTY_FUNCTION__));
bool IsSigned = (Opcode == ISD::SDIVREM);
EVT VT = Op->getValueType(0);
Type *Ty = VT.getTypeForEVT(*DAG.getContext());

RTLIB::Libcall LC;
switch (VT.getSimpleVT().SimpleTy) {
default:
  llvm_unreachable("Unexpected request for libcall!")::llvm::llvm_unreachable_internal("Unexpected request for libcall!"
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 461);
case MVT::i8:
  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
  break;
case MVT::i16:
  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
  break;
case MVT::i32:
  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
  break;
}

SDValue InChain = DAG.getEntryNode();

TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (SDValue const &Value : Op->op_values()) {
  Entry.Node = Value;
  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
  Entry.IsSExt = IsSigned;
  Entry.IsZExt = !IsSigned;
  Args.push_back(Entry);
}

SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
                                       getPointerTy(DAG.getDataLayout()));

Type *RetTy = (Type *)StructType::get(Ty, Ty);

SDLoc dl(Op);
TargetLowering::CallLoweringInfo CLI(DAG);
CLI.setDebugLoc(dl)
    .setChain(InChain)
    .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
    .setInRegister()
    .setSExtResult(IsSigned)
    .setZExtResult(!IsSigned);

std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
return CallInfo.first;
501}

503SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
                                            SelectionDAG &DAG) const {
auto DL = DAG.getDataLayout();

const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();

// Create the TargetGlobalAddress node, folding in the constant offset.
SDValue Result =
    DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
514}

516SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
                                           SelectionDAG &DAG) const {
auto DL = DAG.getDataLayout();
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();

SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));

return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
524}

526/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
527static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
switch (CC) {
default:
  llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 530);
case ISD::SETEQ:
  return AVRCC::COND_EQ;
case ISD::SETNE:
  return AVRCC::COND_NE;
case ISD::SETGE:
  return AVRCC::COND_GE;
case ISD::SETLT:
  return AVRCC::COND_LT;
case ISD::SETUGE:
  return AVRCC::COND_SH;
case ISD::SETULT:
  return AVRCC::COND_LO;
}
544}

546/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
547SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
                                   SelectionDAG &DAG, SDLoc DL) const {
assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&(static_cast <bool> ((LHS.getSimpleValueType() == RHS.getSimpleValueType
()) && "LHS and RHS have different types") ? void (0)
 : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 550, __extension__
 __PRETTY_FUNCTION__))
       "LHS and RHS have different types")(static_cast <bool> ((LHS.getSimpleValueType() == RHS.getSimpleValueType
()) && "LHS and RHS have different types") ? void (0)
 : __assert_fail ("(LHS.getSimpleValueType() == RHS.getSimpleValueType()) && \"LHS and RHS have different types\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 550, __extension__
 __PRETTY_FUNCTION__));
assert(((LHS.getSimpleValueType() == MVT::i16) ||(static_cast <bool> (((LHS.getSimpleValueType() == MVT::
i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type"
) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__
 __PRETTY_FUNCTION__))
        (LHS.getSimpleValueType() == MVT::i8)) &&(static_cast <bool> (((LHS.getSimpleValueType() == MVT::
i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type"
) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__
 __PRETTY_FUNCTION__))
       "invalid comparison type")(static_cast <bool> (((LHS.getSimpleValueType() == MVT::
i16) || (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type"
) ? void (0) : __assert_fail ("((LHS.getSimpleValueType() == MVT::i16) || (LHS.getSimpleValueType() == MVT::i8)) && \"invalid comparison type\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 553, __extension__
 __PRETTY_FUNCTION__));

SDValue Cmp;

if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                              DAG.getIntPtrConstant(1, DL));
  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
                              DAG.getIntPtrConstant(1, DL));
  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
} else {
  // Generate ordinary 16-bit comparison.
  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
}

return Cmp;
575}

577/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
578/// the given operands.
579SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                   SDValue &AVRcc, SelectionDAG &DAG,
                                   SDLoc DL) const {
SDValue Cmp;
EVT VT = LHS.getValueType();
bool UseTest = false;

switch (CC) {
default:
  break;
case ISD::SETLE: {
  // Swap operands and reverse the branching condition.
  std::swap(LHS, RHS);
  CC = ISD::SETGE;
  break;
}
case ISD::SETGT: {
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
    switch (C->getSExtValue()) {
    case -1: {
      // When doing lhs > -1 use a tst instruction on the top part of lhs
      // and use brpl instead of using a chain of cp/cpc.
      UseTest = true;
      AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
      break;
    }
    case 0: {
      // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
      // __zero_reg__ in lhs.
      RHS = LHS;
      LHS = DAG.getConstant(0, DL, VT);
      CC = ISD::SETLT;
      break;
    }
    default: {
      // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
      // us to  fold the constant into the cmp instruction.
      RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
      CC = ISD::SETGE;
      break;
    }
    }
    break;
  }
  // Swap operands and reverse the branching condition.
  std::swap(LHS, RHS);
  CC = ISD::SETLT;
  break;
}
case ISD::SETLT: {
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
    switch (C->getSExtValue()) {
    case 1: {
      // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
      // __zero_reg__ in lhs.
      RHS = LHS;
      LHS = DAG.getConstant(0, DL, VT);
      CC = ISD::SETGE;
      break;
    }
    case 0: {
      // When doing lhs < 0 use a tst instruction on the top part of lhs
      // and use brmi instead of using a chain of cp/cpc.
      UseTest = true;
      AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
      break;
    }
    }
  }
  break;
}
case ISD::SETULE: {
  // Swap operands and reverse the branching condition.
  std::swap(LHS, RHS);
  CC = ISD::SETUGE;
  break;
}
case ISD::SETUGT: {
  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
  // fold the constant into the cmp instruction.
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
    RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
    CC = ISD::SETUGE;
    break;
  }
  // Swap operands and reverse the branching condition.
  std::swap(LHS, RHS);
  CC = ISD::SETULT;
  break;
}
}

// Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
// using the default and/or/xor expansion code which is much longer.
if (VT == MVT::i32) {
  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
                              DAG.getIntPtrConstant(1, DL));
  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
                              DAG.getIntPtrConstant(1, DL));

  if (UseTest) {
    // When using tst we only care about the highest part.
    SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
                              DAG.getIntPtrConstant(1, DL));
    Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
  } else {
    Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
  }
} else if (VT == MVT::i64) {
  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
                              DAG.getIntPtrConstant(1, DL));

  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
                             DAG.getIntPtrConstant(0, DL));
  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
                             DAG.getIntPtrConstant(1, DL));
  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
                             DAG.getIntPtrConstant(0, DL));
  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
                             DAG.getIntPtrConstant(1, DL));

  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
                              DAG.getIntPtrConstant(0, DL));
  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
                              DAG.getIntPtrConstant(1, DL));

  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
                             DAG.getIntPtrConstant(0, DL));
  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
                             DAG.getIntPtrConstant(1, DL));
  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
                             DAG.getIntPtrConstant(0, DL));
  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
                             DAG.getIntPtrConstant(1, DL));

  if (UseTest) {
    // When using tst we only care about the highest part.
    SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
                              DAG.getIntPtrConstant(1, DL));
    Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
  } else {
    Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
  }
} else if (VT == MVT::i8 || VT == MVT::i16) {
  if (UseTest) {
    // When using tst we only care about the highest part.
    Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
                      (VT == MVT::i8)
                          ? LHS
                          : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
                                        LHS, DAG.getIntPtrConstant(1, DL)));
  } else {
    Cmp = getAVRCmp(LHS, RHS, DAG, DL);
  }
} else {
  llvm_unreachable("Invalid comparison size")::llvm::llvm_unreachable_internal("Invalid comparison size", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 744);
}

// When using a test instruction AVRcc is already set.
if (!UseTest) {
  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
}

return Cmp;
753}

755SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
SDLoc dl(Op);

SDValue TargetCC;
SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);

return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
                   Cmp);
768}

770SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue TrueV = Op.getOperand(2);
SDValue FalseV = Op.getOperand(3);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDLoc dl(Op);

SDValue TargetCC;
SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);

SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};

return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
785}

787SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
SDLoc DL(Op);

SDValue TargetCC;
SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);

SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};

return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
802}

804SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
const MachineFunction &MF = DAG.getMachineFunction();
const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
auto DL = DAG.getDataLayout();
SDLoc dl(Op);

// Vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));

return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
                    MachinePointerInfo(SV));
817}

819SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
  llvm_unreachable("Don't know how to custom lower this!")::llvm::llvm_unreachable_internal("Don't know how to custom lower this!"
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 822);
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
case ISD::ROTL:
case ISD::ROTR:
  return LowerShifts(Op, DAG);
case ISD::GlobalAddress:
  return LowerGlobalAddress(Op, DAG);
case ISD::BlockAddress:
  return LowerBlockAddress(Op, DAG);
case ISD::BR_CC:
  return LowerBR_CC(Op, DAG);
case ISD::SELECT_CC:
  return LowerSELECT_CC(Op, DAG);
case ISD::SETCC:
  return LowerSETCC(Op, DAG);
case ISD::VASTART:
  return LowerVASTART(Op, DAG);
case ISD::SDIVREM:
case ISD::UDIVREM:
  return LowerDivRem(Op, DAG);
}

return SDValue();
847}

849/// Replace a node with an illegal result type
850/// with a new node built out of custom code.
851void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
                                         SmallVectorImpl<SDValue> &Results,
                                         SelectionDAG &DAG) const {
SDLoc DL(N);

switch (N->getOpcode()) {
case ISD::ADD: {
  // Convert add (x, imm) into sub (x, -imm).
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
    SDValue Sub = DAG.getNode(
        ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
        DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
    Results.push_back(Sub);
  }
  break;
}
default: {
  SDValue Res = LowerOperation(SDValue(N, 0), DAG);

  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
    Results.push_back(Res.getValue(I));

  break;
}
}
876}

878/// Return true if the addressing mode represented
879/// by AM is legal for this target, for a load/store of the specified type.
880bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                            const AddrMode &AM, Type *Ty,
                                            unsigned AS,
                                            Instruction *I) const {
int64_t Offs = AM.BaseOffs;

// Allow absolute addresses.
if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
  return true;
}

// Flash memory instructions only allow zero offsets.
if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
  return false;
}

// Allow reg+<6bit> offset.
if (Offs < 0)
  Offs = -Offs;
if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
    isUInt<6>(Offs)) {
  return true;
}

return false;
905}

907/// Returns true by value, base pointer and
908/// offset pointer and addressing mode by reference if the node's address
909/// can be legally represented as pre-indexed load / store address.
910bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
                                                SDValue &Offset,
                                                ISD::MemIndexedMode &AM,
                                                SelectionDAG &DAG) const {
EVT VT;
const SDNode *Op;
SDLoc DL(N);

if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
  VT = LD->getMemoryVT();
  Op = LD->getBasePtr().getNode();
  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
    return false;
  if (AVR::isProgramMemoryAccess(LD)) {
    return false;
  }
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
  VT = ST->getMemoryVT();
  Op = ST->getBasePtr().getNode();
  if (AVR::isProgramMemoryAccess(ST)) {
    return false;
  }
} else {
  return false;
}

if (VT != MVT::i8 && VT != MVT::i16) {
  return false;
}

if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
  return false;
}

if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
  int RHSC = RHS->getSExtValue();
  if (Op->getOpcode() == ISD::SUB)
    RHSC = -RHSC;

  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
    return false;
  }

  Base = Op->getOperand(0);
  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
  AM = ISD::PRE_DEC;

  return true;
}

return false;
961}

963/// Returns true by value, base pointer and
964/// offset pointer and addressing mode by reference if this node can be
965/// combined with a load / store to form a post-indexed load / store.
966bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                                 SDValue &Base,
                                                 SDValue &Offset,
                                                 ISD::MemIndexedMode &AM,
                                                 SelectionDAG &DAG) const {
EVT VT;
SDLoc DL(N);

if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
  VT = LD->getMemoryVT();
  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
    return false;
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
  VT = ST->getMemoryVT();
  if (AVR::isProgramMemoryAccess(ST)) {
    return false;
  }
} else {
  return false;
}

if (VT != MVT::i8 && VT != MVT::i16) {
  return false;
}

if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
  return false;
}

if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
  int RHSC = RHS->getSExtValue();
  if (Op->getOpcode() == ISD::SUB)
    RHSC = -RHSC;
  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
    return false;
  }

  Base = Op->getOperand(0);
  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
  AM = ISD::POST_INC;

  return true;
}

return false;
1011}

1013bool AVRTargetLowering::isOffsetFoldingLegal(
  const GlobalAddressSDNode *GA) const {
return true;
1016}

1018//===----------------------------------------------------------------------===//
1019//             Formal Arguments Calling Convention Implementation
1020//===----------------------------------------------------------------------===//

1022#include "AVRGenCallingConv.inc"

1024/// Registers for calling conventions, ordered in reverse as required by ABI.
1025/// Both arrays must be of the same length.
1026static const MCPhysReg RegList8[] = {
  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9,  AVR::R8};
1030static const MCPhysReg RegList16[] = {
  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
  AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
  AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
  AVR::R11R10, AVR::R10R9,  AVR::R9R8};

1036static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
            "8-bit and 16-bit register arrays must be of equal length");

1039/// Analyze incoming and outgoing function arguments. We need custom C++ code
1040/// to handle special constraints in the ABI.
1041/// In addition, all pieces of a certain argument have to be passed either
1042/// using registers or the stack but never mixing both.
1043template <typename ArgT>
1044static void
1045analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
               const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
               SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
unsigned NumArgs = Args.size();
// This is the index of the last used register, in RegList*.
// -1 means R26 (R26 is never actually used in CC).
int RegLastIdx = -1;
// Once a value is passed to the stack it will always be used
bool UseStack = false;
for (unsigned i = 0; i != NumArgs;) {
  MVT VT = Args[i].VT;
  // We have to count the number of bytes for each function argument, that is
  // those Args with the same OrigArgIndex. This is important in case the
  // function takes an aggregate type.
  // Current argument will be between [i..j).
  unsigned ArgIndex = Args[i].OrigArgIndex;
  unsigned TotalBytes = VT.getStoreSize();
  unsigned j = i + 1;
  for (; j != NumArgs; ++j) {
    if (Args[j].OrigArgIndex != ArgIndex)
      break;
    TotalBytes += Args[j].VT.getStoreSize();
  }
  // Round up to even number of bytes.
  TotalBytes = alignTo(TotalBytes, 2);
  // Skip zero sized arguments
  if (TotalBytes == 0)
    continue;
  // The index of the first register to be used
  unsigned RegIdx = RegLastIdx + TotalBytes;
  RegLastIdx = RegIdx;
  // If there are not enough registers, use the stack
  if (RegIdx >= array_lengthof(RegList8)) {
    UseStack = true;
  }
  for (; i != j; ++i) {
    MVT VT = Args[i].VT;

    if (UseStack) {
      auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
      unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
                                             TD->getABITypeAlign(evt));
      CCInfo.addLoc(
          CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
    } else {
      unsigned Reg;
      if (VT == MVT::i8) {
        Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
      } else if (VT == MVT::i16) {
        Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
      } else {
        llvm_unreachable(::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1097)
            "calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1097);
      }
      assert(Reg && "register not available in calling convention")(static_cast <bool> (Reg && "register not available in calling convention"
) ? void (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1099, __extension__
 __PRETTY_FUNCTION__));
      CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
      // Registers inside a particular argument are sorted in increasing order
      // (remember the array is reversed).
      RegIdx -= VT.getStoreSize();
    }
  }
}
1107}

1109/// Count the total number of bytes needed to pass or return these arguments.
1110template <typename ArgT>
1111static unsigned
1112getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
unsigned TotalBytes = 0;

for (const ArgT &Arg : Args) {
  TotalBytes += Arg.VT.getStoreSize();
}
return TotalBytes;
1119}

1121/// Analyze incoming and outgoing value of returning from a function.
1122/// The algorithm is similar to analyzeArguments, but there can only be
1123/// one value, possibly an aggregate, and it is limited to 8 bytes.
1124template <typename ArgT>
1125static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
                              CCState &CCInfo) {
unsigned NumArgs = Args.size();
unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
// CanLowerReturn() guarantees this assertion.
assert(TotalBytes <= 8 &&(static_cast <bool> (TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"
) ? void (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1131, __extension__
 __PRETTY_FUNCTION__))
4
←
'?' condition is true→
       "return values greater than 8 bytes cannot be lowered")(static_cast <bool> (TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered"
) ? void (0) : __assert_fail ("TotalBytes <= 8 && \"return values greater than 8 bytes cannot be lowered\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1131, __extension__
 __PRETTY_FUNCTION__));

// GCC-ABI says that the size is rounded up to the next even number,
// but actually once it is more than 4 it will always round up to 8.
if (TotalBytes4.1
'TotalBytes' is <= 4
1
'TotalBytes' is <= 4
 > 4) {
5
←
Taking false branch→
  TotalBytes = 8;
} else {
  TotalBytes = alignTo(TotalBytes, 2);
}

// The index of the first register to use.
int RegIdx = TotalBytes - 1;
6
←
'RegIdx' initialized to -1→
for (unsigned i = 0; i != NumArgs; ++i) {
7
←
Assuming 'i' is not equal to 'NumArgs'→
8
←
Loop condition is true.  Entering loop body→
  MVT VT = Args[i].VT;
  unsigned Reg;
  if (VT == MVT::i8) {
9
←
Calling 'MVT::operator=='→
12
←
Returning from 'MVT::operator=='→
13
←
Taking false branch→
    Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
  } else if (VT == MVT::i16) {
14
←
Taking true branch→
    Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
15
←
1st function call argument is an uninitialized value
  } else {
    llvm_unreachable("calling convention can only manage i8 and i16 types")::llvm::llvm_unreachable_internal("calling convention can only manage i8 and i16 types"
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1151);
  }
  assert(Reg && "register not available in calling convention")(static_cast <bool> (Reg && "register not available in calling convention"
) ? void (0) : __assert_fail ("Reg && \"register not available in calling convention\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1153, __extension__
 __PRETTY_FUNCTION__));
  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
  // Registers sort in increasing order
  RegIdx -= VT.getStoreSize();
}
1158}

1160SDValue AVRTargetLowering::LowerFormalArguments(
  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
auto DL = DAG.getDataLayout();

// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
               *DAG.getContext());

// Variadic functions do not need all the analysis below.
if (isVarArg) {
  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
} else {
  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
}

SDValue ArgValue;
for (CCValAssign &VA : ArgLocs) {

  // Arguments stored on registers.
  if (VA.isRegLoc()) {
    EVT RegVT = VA.getLocVT();
    const TargetRegisterClass *RC;
    if (RegVT == MVT::i8) {
      RC = &AVR::GPR8RegClass;
    } else if (RegVT == MVT::i16) {
      RC = &AVR::DREGSRegClass;
    } else {
      llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1192);
    }

    Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
    ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);

    // :NOTE: Clang should not promote any i8 into i16 but for safety the
    // following code will handle zexts or sexts generated by other
    // front ends. Otherwise:
    // If this is an 8 bit value, it is really passed promoted
    // to 16 bits. Insert an assert[sz]ext to capture this, then
    // truncate to the right size.
    switch (VA.getLocInfo()) {
    default:
      llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1206);
    case CCValAssign::Full:
      break;
    case CCValAssign::BCvt:
      ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
      break;
    case CCValAssign::SExt:
      ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
                             DAG.getValueType(VA.getValVT()));
      ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
      break;
    case CCValAssign::ZExt:
      ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
                             DAG.getValueType(VA.getValVT()));
      ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
      break;
    }

    InVals.push_back(ArgValue);
  } else {
    // Only arguments passed on the stack should make it here.
    assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
 ("VA.isMemLoc()", "llvm/lib/Target/AVR/AVRISelLowering.cpp",
 1227, __extension__ __PRETTY_FUNCTION__));

    EVT LocVT = VA.getLocVT();

    // Create the frame index object for this incoming parameter.
    int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
                                   VA.getLocMemOffset(), true);

    // Create the SelectionDAG nodes corresponding to a load
    // from this parameter.
    SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
    InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
                                 MachinePointerInfo::getFixedStack(MF, FI)));
  }
}

// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (isVarArg) {
  unsigned StackSize = CCInfo.getNextStackOffset();
  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();

  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
}

return Chain;
1253}

1255//===----------------------------------------------------------------------===//
1256//                  Call Calling Convention Implementation
1257//===----------------------------------------------------------------------===//

1259SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                                   SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;
SDLoc &DL = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;
bool &isTailCall = CLI.IsTailCall;
CallingConv::ID CallConv = CLI.CallConv;
bool isVarArg = CLI.IsVarArg;

MachineFunction &MF = DAG.getMachineFunction();

// AVR does not yet support tail call optimization.
isTailCall = false;

// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
               *DAG.getContext());

// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
const Function *F = nullptr;
if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
  const GlobalValue *GV = G->getGlobal();
  if (isa<Function>(GV))
    F = cast<Function>(GV);
  Callee =
      DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
} else if (const ExternalSymbolSDNode *ES =
               dyn_cast<ExternalSymbolSDNode>(Callee)) {
  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
                                       getPointerTy(DAG.getDataLayout()));
}

// Variadic functions do not need all the analysis below.
if (isVarArg) {
  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
} else {
  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
}

// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();

Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);

SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

// First, walk the register assignments, inserting copies.
unsigned AI, AE;
bool HasStackArgs = false;
for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
  CCValAssign &VA = ArgLocs[AI];
  EVT RegVT = VA.getLocVT();
  SDValue Arg = OutVals[AI];

  // Promote the value if needed. With Clang this should not happen.
  switch (VA.getLocInfo()) {
  default:
    llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1323);
  case CCValAssign::Full:
    break;
  case CCValAssign::SExt:
    Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
    break;
  case CCValAssign::ZExt:
    Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
    break;
  case CCValAssign::AExt:
    Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
    break;
  case CCValAssign::BCvt:
    Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
    break;
  }

  // Stop when we encounter a stack argument, we need to process them
  // in reverse order in the loop below.
  if (VA.isMemLoc()) {
    HasStackArgs = true;
    break;
  }

  // Arguments that can be passed on registers must be kept in the RegsToPass
  // vector.
  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
}

// Second, stack arguments have to walked.
// Previously this code created chained stores but those chained stores appear
// to be unchained in the legalization phase. Therefore, do not attempt to
// chain them here. In fact, chaining them here somehow causes the first and
// second store to be reversed which is the exact opposite of the intended
// effect.
if (HasStackArgs) {
  SmallVector<SDValue, 8> MemOpChains;
  for (; AI != AE; AI++) {
    CCValAssign &VA = ArgLocs[AI];
    SDValue Arg = OutVals[AI];

    assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
 ("VA.isMemLoc()", "llvm/lib/Target/AVR/AVRISelLowering.cpp",
 1364, __extension__ __PRETTY_FUNCTION__));

    // SP points to one stack slot further so add one to adjust it.
    SDValue PtrOff = DAG.getNode(
        ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
        DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
        DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

    MemOpChains.push_back(
        DAG.getStore(Chain, DL, Arg, PtrOff,
                     MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
  }

  if (!MemOpChains.empty())
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
}

// Build a sequence of copy-to-reg nodes chained together with token chain and
// flag operands which copy the outgoing args into registers.  The InFlag in
// necessary since all emited instructions must be stuck together.
SDValue InFlag;
for (auto Reg : RegsToPass) {
  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
  InFlag = Chain.getValue(1);
}

// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);

// Add argument registers to the end of the list so that they are known live
// into the call.
for (auto Reg : RegsToPass) {
  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
}

// Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
const uint32_t *Mask =
    TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1406, __extension__
 __PRETTY_FUNCTION__));
Ops.push_back(DAG.getRegisterMask(Mask));

if (InFlag.getNode()) {
  Ops.push_back(InFlag);
}

Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
InFlag = Chain.getValue(1);

// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
                           DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

if (!Ins.empty()) {
  InFlag = Chain.getValue(1);
}

// Handle result values, copying them out of physregs into vregs that we
// return.
return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
                       InVals);
1428}

1430/// Lower the result values of a call into the
1431/// appropriate copies out of appropriate physical registers.
1432///
1433SDValue AVRTargetLowering::LowerCallResult(
  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
               *DAG.getContext());

// Handle runtime calling convs.
if (CallConv == CallingConv::AVR_BUILTIN) {
  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
} else {
  analyzeReturnValues(Ins, CCInfo);
}

// Copy all of the result registers out of their specified physreg.
for (CCValAssign const &RVLoc : RVLocs) {
  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
                             InFlag)
              .getValue(1);
  InFlag = Chain.getValue(2);
  InVals.push_back(Chain.getValue(0));
}

return Chain;
1460}

1462//===----------------------------------------------------------------------===//
1463//               Return Value Calling Convention Implementation
1464//===----------------------------------------------------------------------===//

1466bool AVRTargetLowering::CanLowerReturn(
  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
if (CallConv == CallingConv::AVR_BUILTIN) {
  SmallVector<CCValAssign, 16> RVLocs;
  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
}

unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
return TotalBytes <= 8;
1477}

1479SDValue
1480AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                             bool isVarArg,
                             const SmallVectorImpl<ISD::OutputArg> &Outs,
                             const SmallVectorImpl<SDValue> &OutVals,
                             const SDLoc &dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs;

// CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
               *DAG.getContext());

MachineFunction &MF = DAG.getMachineFunction();

// Analyze return values.
if (CallConv == CallingConv::AVR_BUILTIN) {
1
Assuming 'CallConv' is not equal to AVR_BUILTIN→
2
←
Taking false branch→
  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
} else {
  analyzeReturnValues(Outs, CCInfo);
3
←
Calling 'analyzeReturnValues<llvm::ISD::OutputArg>'→
}

SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);
// Copy the result values into the output registers.
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
  CCValAssign &VA = RVLocs[i];
  assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1506, __extension__
 __PRETTY_FUNCTION__));

  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);

  // Guarantee that all emitted copies are stuck together with flags.
  Flag = Chain.getValue(1);
  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}

// Don't emit the ret/reti instruction when the naked attribute is present in
// the function being compiled.
if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
  return Chain;
}

const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();

unsigned RetOpc =
    AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;

RetOps[0] = Chain; // Update chain.

if (Flag.getNode()) {
  RetOps.push_back(Flag);
}

return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1533}

1535//===----------------------------------------------------------------------===//
1536//  Custom Inserters
1537//===----------------------------------------------------------------------===//

1539MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
                                                MachineBasicBlock *BB) const {
unsigned Opc;
const TargetRegisterClass *RC;
bool HasRepeatedOperand = false;
MachineFunction *F = BB->getParent();
MachineRegisterInfo &RI = F->getRegInfo();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc dl = MI.getDebugLoc();

switch (MI.getOpcode()) {
default:
  llvm_unreachable("Invalid shift opcode!")::llvm::llvm_unreachable_internal("Invalid shift opcode!", "llvm/lib/Target/AVR/AVRISelLowering.cpp"
, 1551);
case AVR::Lsl8:
  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
  RC = &AVR::GPR8RegClass;
  HasRepeatedOperand = true;
  break;
case AVR::Lsl16:
  Opc = AVR::LSLWRd;
  RC = &AVR::DREGSRegClass;
  break;
case AVR::Asr8:
  Opc = AVR::ASRRd;
  RC = &AVR::GPR8RegClass;
  break;
case AVR::Asr16:
  Opc = AVR::ASRWRd;
  RC = &AVR::DREGSRegClass;
  break;
case AVR::Lsr8:
  Opc = AVR::LSRRd;
  RC = &AVR::GPR8RegClass;
  break;
case AVR::Lsr16:
  Opc = AVR::LSRWRd;
  RC = &AVR::DREGSRegClass;
  break;
case AVR::Rol8:
  Opc = AVR::ROLBRd;
  RC = &AVR::GPR8RegClass;
  break;
case AVR::Rol16:
  Opc = AVR::ROLWRd;
  RC = &AVR::DREGSRegClass;
  break;
case AVR::Ror8:
  Opc = AVR::RORBRd;
  RC = &AVR::GPR8RegClass;
  break;
case AVR::Ror16:
  Opc = AVR::RORWRd;
  RC = &AVR::DREGSRegClass;
  break;
}

const BasicBlock *LLVM_BB = BB->getBasicBlock();

MachineFunction::iterator I;
for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
  ;
if (I != F->end())
  ++I;

// Create loop block.
MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);

F->insert(I, LoopBB);
F->insert(I, CheckBB);
F->insert(I, RemBB);

// Update machine-CFG edges by transferring all successors of the current
// block to the block containing instructions after shift.
RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
              BB->end());
RemBB->transferSuccessorsAndUpdatePHIs(BB);

// Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
BB->addSuccessor(CheckBB);
LoopBB->addSuccessor(CheckBB);
CheckBB->addSuccessor(LoopBB);
CheckBB->addSuccessor(RemBB);

Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
Register ShiftReg = RI.createVirtualRegister(RC);
Register ShiftReg2 = RI.createVirtualRegister(RC);
Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();

// BB:
// rjmp CheckBB
BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);

// LoopBB:
// ShiftReg2 = shift ShiftReg
auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
if (HasRepeatedOperand)
  ShiftMI.addReg(ShiftReg);

// CheckBB:
// ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
// ShiftAmt = phi [%N,      BB], [%ShiftAmt2, LoopBB]
// DestReg  = phi [%SrcReg, BB], [%ShiftReg,  LoopBB]
// ShiftAmt2 = ShiftAmt - 1;
// if (ShiftAmt2 >= 0) goto LoopBB;
BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
    .addReg(SrcReg)
    .addMBB(BB)
    .addReg(ShiftReg2)
    .addMBB(LoopBB);
BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
    .addReg(ShiftAmtSrcReg)
    .addMBB(BB)
    .addReg(ShiftAmtReg2)
    .addMBB(LoopBB);
BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
    .addReg(SrcReg)
    .addMBB(BB)
    .addReg(ShiftReg2)
    .addMBB(LoopBB);

BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);

MI.eraseFromParent(); // The pseudo instruction is gone now.
return RemBB;
1669}

1671static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
if (I->getOpcode() == AVR::COPY) {
  Register SrcReg = I->getOperand(1).getReg();
  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
}

return false;
1678}

1680// The mul instructions wreak havock on our zero_reg R1. We need to clear it
1681// after the result has been evacuated. This is probably not the best way to do
1682// it, but it works for now.
1683MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
                                              MachineBasicBlock *BB) const {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
MachineBasicBlock::iterator I(MI);
++I; // in any case insert *after* the mul instruction
if (isCopyMulResult(I))
  ++I;
if (isCopyMulResult(I))
  ++I;
BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
    .addReg(AVR::R1)
    .addReg(AVR::R1);
return BB;
1696}

1698// Insert a read from R1, which almost always contains the value 0.
1699MachineBasicBlock *
1700AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
MachineBasicBlock::iterator I(MI);
BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
    .add(MI.getOperand(0))
    .addReg(AVR::R1);
MI.eraseFromParent();
return BB;
1708}

1710// Lower atomicrmw operation to disable interrupts, do operation, and restore
1711// interrupts. This works because all AVR microcontrollers are single core.
1712MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
  MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
MachineBasicBlock::iterator I(MI);
const Register SCRATCH_REGISTER = AVR::R0;
DebugLoc dl = MI.getDebugLoc();

// Example instruction sequence, for an atomic 8-bit add:
//   ldi r25, 5
//   in r0, SREG
//   cli
//   ld r24, X
//   add r25, r24
//   st X, r25
//   out SREG, r0

const TargetRegisterClass *RC =
    (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;

// Disable interrupts.
BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER)
    .addImm(Subtarget.getIORegSREG());
BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);

// Load the original value.
BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
    .add(MI.getOperand(1));

// Do the arithmetic operation.
Register Result = MRI.createVirtualRegister(RC);
BuildMI(*BB, I, dl, TII.get(Opcode), Result)
    .addReg(MI.getOperand(0).getReg())
    .add(MI.getOperand(2));

// Store the result.
BuildMI(*BB, I, dl, TII.get(StoreOpcode))
    .add(MI.getOperand(1))
    .addReg(Result);

// Restore interrupts.
BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
    .addImm(Subtarget.getIORegSREG())
    .addReg(SCRATCH_REGISTER);

// Remove the pseudo instruction.
MI.eraseFromParent();
return BB;
1762}

1764MachineBasicBlock *
1765AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                             MachineBasicBlock *MBB) const {
int Opc = MI.getOpcode();

// Pseudo shift instructions with a non constant shift amount are expanded
// into a loop.
switch (Opc) {
case AVR::Lsl8:
case AVR::Lsl16:
case AVR::Lsr8:
case AVR::Lsr16:
case AVR::Rol8:
case AVR::Rol16:
case AVR::Ror8:
case AVR::Ror16:
case AVR::Asr8:
case AVR::Asr16:
  return insertShift(MI, MBB);
case AVR::MULRdRr:
case AVR::MULSRdRr:
  return insertMul(MI, MBB);
case AVR::CopyR1:
  return insertCopyR1(MI, MBB);
case AVR::AtomicLoadAdd8:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
case AVR::AtomicLoadAdd16:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
case AVR::AtomicLoadSub8:
  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
case AVR::AtomicLoadSub16:
  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
case AVR::AtomicLoadAnd8:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8);
case AVR::AtomicLoadAnd16:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16);
case AVR::AtomicLoadOr8:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8);
case AVR::AtomicLoadOr16:
  return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16);
case AVR::AtomicLoadXor8:
  return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8);
case AVR::AtomicLoadXor16:
  return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16);
}

assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&(static_cast <bool> ((Opc == AVR::Select16 || Opc == AVR
::Select8) && "Unexpected instr type to insert") ? void
 (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1811, __extension__
 __PRETTY_FUNCTION__))
       "Unexpected instr type to insert")(static_cast <bool> ((Opc == AVR::Select16 || Opc == AVR
::Select8) && "Unexpected instr type to insert") ? void
 (0) : __assert_fail ("(Opc == AVR::Select16 || Opc == AVR::Select8) && \"Unexpected instr type to insert\""
, "llvm/lib/Target/AVR/AVRISelLowering.cpp", 1811, __extension__
 __PRETTY_FUNCTION__));

const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
                              ->getParent()
                              ->getSubtarget()
                              .getInstrInfo();
DebugLoc dl = MI.getDebugLoc();

// To "insert" a SELECT instruction, we insert the diamond
// control-flow pattern. The incoming instruction knows the
// destination vreg to set, the condition code register to branch
// on, the true/false values to select between, and a branch opcode
// to use.

MachineFunction *MF = MBB->getParent();
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
MachineBasicBlock *FallThrough = MBB->getFallThrough();

// If the current basic block falls through to another basic block,
// we must insert an unconditional branch to the fallthrough destination
// if we are to insert basic blocks at the prior fallthrough point.
if (FallThrough != nullptr) {
  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
}

MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);

MachineFunction::iterator I;
for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
  ;
if (I != MF->end())
  ++I;
MF->insert(I, trueMBB);
MF->insert(I, falseMBB);

// Transfer remaining instructions and all successors of the current
// block to the block which will contain the Phi node for the
// select.
trueMBB->splice(trueMBB->begin(), MBB,
                std::next(MachineBasicBlock::iterator(MI)), MBB->end());
trueMBB->transferSuccessorsAndUpdatePHIs(MBB);

AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
MBB->addSuccessor(falseMBB);
MBB->addSuccessor(trueMBB);

// Unconditionally flow back to the true block
BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
falseMBB->addSuccessor(trueMBB);

// Set up the Phi node to determine where we came from
BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
        MI.getOperand(0).getReg())
    .addReg(MI.getOperand(1).getReg())
    .addMBB(MBB)
    .addReg(MI.getOperand(2).getReg())
    .addMBB(falseMBB);

MI.eraseFromParent(); // The pseudo instruction is gone now.
return trueMBB;
1874}

1876//===----------------------------------------------------------------------===//
1877//  Inline Asm Support
1878//===----------------------------------------------------------------------===//

1880AVRTargetLowering::ConstraintType
1881AVRTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
  switch (Constraint[0]) {
  default:
    break;
  case 'a': // Simple upper registers
  case 'b': // Base pointer registers pairs
  case 'd': // Upper register
  case 'l': // Lower registers
  case 'e': // Pointer register pairs
  case 'q': // Stack pointer register
  case 'r': // Any register
  case 'w': // Special upper register pairs
    return C_RegisterClass;
  case 't': // Temporary register
  case 'x':
  case 'X': // Pointer register pair X
  case 'y':
  case 'Y': // Pointer register pair Y
  case 'z':
  case 'Z': // Pointer register pair Z
    return C_Register;
  case 'Q': // A memory address based on Y or Z pointer with displacement.
    return C_Memory;
  case 'G': // Floating point constant
  case 'I': // 6-bit positive integer constant
  case 'J': // 6-bit negative integer constant
  case 'K': // Integer constant (Range: 2)
  case 'L': // Integer constant (Range: 0)
  case 'M': // 8-bit integer constant
  case 'N': // Integer constant (Range: -1)
  case 'O': // Integer constant (Range: 8, 16, 24)
  case 'P': // Integer constant (Range: 1)
  case 'R': // Integer constant (Range: -6 to 5)x
    return C_Immediate;
  }
}

return TargetLowering::getConstraintType(Constraint);
1921}

1923unsigned
1924AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Not sure if this is actually the right thing to do, but we got to do
// *something* [agnat]
switch (ConstraintCode[0]) {
case 'Q':
  return InlineAsm::Constraint_Q;
}
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1932}

1934AVRTargetLowering::ConstraintWeight
1935AVRTargetLowering::getSingleConstraintMatchWeight(
  AsmOperandInfo &info, const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;

// If we don't have a value, we can't do a match,
// but allow it at the lowest weight.
// (this behaviour has been copied from the ARM backend)
if (!CallOperandVal) {
  return CW_Default;
}

// Look at the constraint type.
switch (*constraint) {
default:
  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
  break;
case 'd':
case 'r':
case 'l':
  weight = CW_Register;
  break;
case 'a':
case 'b':
case 'e':
case 'q':
case 't':
case 'w':
case 'x':
case 'X':
case 'y':
case 'Y':
case 'z':
case 'Z':
  weight = CW_SpecificReg;
  break;
case 'G':
  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
    if (C->isZero()) {
      weight = CW_Constant;
    }
  }
  break;
case 'I':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (isUInt<6>(C->getZExtValue())) {
      weight = CW_Constant;
    }
  }
  break;
case 'J':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
      weight = CW_Constant;
    }
  }
  break;
case 'K':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (C->getZExtValue() == 2) {
      weight = CW_Constant;
    }
  }
  break;
case 'L':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (C->getZExtValue() == 0) {
      weight = CW_Constant;
    }
  }
  break;
case 'M':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (isUInt<8>(C->getZExtValue())) {
      weight = CW_Constant;
    }
  }
  break;
case 'N':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (C->getSExtValue() == -1) {
      weight = CW_Constant;
    }
  }
  break;
case 'O':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
        (C->getZExtValue() == 24)) {
      weight = CW_Constant;
    }
  }
  break;
case 'P':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if (C->getZExtValue() == 1) {
      weight = CW_Constant;
    }
  }
  break;
case 'R':
  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
    if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
      weight = CW_Constant;
    }
  }
  break;
case 'Q':
  weight = CW_Memory;
  break;
}

return weight;
2048}

2050std::pair<unsigned, const TargetRegisterClass *>
2051AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                              StringRef Constraint,
                                              MVT VT) const {
if (Constraint.size() == 1) {
  switch (Constraint[0]) {
  case 'a': // Simple upper registers r16..r23.
    if (VT == MVT::i8)
      return std::make_pair(0U, &AVR::LD8loRegClass);
    else if (VT == MVT::i16)
      return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
    break;
  case 'b': // Base pointer registers: y, z.
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
    break;
  case 'd': // Upper registers r16..r31.
    if (VT == MVT::i8)
      return std::make_pair(0U, &AVR::LD8RegClass);
    else if (VT == MVT::i16)
      return std::make_pair(0U, &AVR::DLDREGSRegClass);
    break;
  case 'l': // Lower registers r0..r15.
    if (VT == MVT::i8)
      return std::make_pair(0U, &AVR::GPR8loRegClass);
    else if (VT == MVT::i16)
      return std::make_pair(0U, &AVR::DREGSloRegClass);
    break;
  case 'e': // Pointer register pairs: x, y, z.
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(0U, &AVR::PTRREGSRegClass);
    break;
  case 'q': // Stack pointer register: SPH:SPL.
    return std::make_pair(0U, &AVR::GPRSPRegClass);
  case 'r': // Any register: r0..r31.
    if (VT == MVT::i8)
      return std::make_pair(0U, &AVR::GPR8RegClass);
    else if (VT == MVT::i16)
      return std::make_pair(0U, &AVR::DREGSRegClass);
    break;
  case 't': // Temporary register: r0.
    if (VT == MVT::i8)
      return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
    break;
  case 'w': // Special upper register pairs: r24, r26, r28, r30.
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(0U, &AVR::IWREGSRegClass);
    break;
  case 'x': // Pointer register pair X: r27:r26.
  case 'X':
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
    break;
  case 'y': // Pointer register pair Y: r29:r28.
  case 'Y':
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
    break;
  case 'z': // Pointer register pair Z: r31:r30.
  case 'Z':
    if (VT == MVT::i8 || VT == MVT::i16)
      return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
    break;
  default:
    break;
  }
}

return TargetLowering::getRegForInlineAsmConstraint(
    Subtarget.getRegisterInfo(), Constraint, VT);
2120}

2122void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
                                                   std::string &Constraint,
                                                   std::vector<SDValue> &Ops,
                                                   SelectionDAG &DAG) const {
SDValue Result;
SDLoc DL(Op);
EVT Ty = Op.getValueType();

// Currently only support length 1 constraints.
if (Constraint.length() != 1) {
  return;
}

char ConstraintLetter = Constraint[0];
switch (ConstraintLetter) {
default:
  break;
// Deal with integers first:
case 'I':
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P':
case 'R': {
  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
  if (!C) {
    return;
  }

  int64_t CVal64 = C->getSExtValue();
  uint64_t CUVal64 = C->getZExtValue();
  switch (ConstraintLetter) {
  case 'I': // 0..63
    if (!isUInt<6>(CUVal64))
      return;
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'J': // -63..0
    if (CVal64 < -63 || CVal64 > 0)
      return;
    Result = DAG.getTargetConstant(CVal64, DL, Ty);
    break;
  case 'K': // 2
    if (CUVal64 != 2)
      return;
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'L': // 0
    if (CUVal64 != 0)
      return;
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'M': // 0..255
    if (!isUInt<8>(CUVal64))
      return;
    // i8 type may be printed as a negative number,
    // e.g. 254 would be printed as -2,
    // so we force it to i16 at least.
    if (Ty.getSimpleVT() == MVT::i8) {
      Ty = MVT::i16;
    }
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'N': // -1
    if (CVal64 != -1)
      return;
    Result = DAG.getTargetConstant(CVal64, DL, Ty);
    break;
  case 'O': // 8, 16, 24
    if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
      return;
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'P': // 1
    if (CUVal64 != 1)
      return;
    Result = DAG.getTargetConstant(CUVal64, DL, Ty);
    break;
  case 'R': // -6..5
    if (CVal64 < -6 || CVal64 > 5)
      return;
    Result = DAG.getTargetConstant(CVal64, DL, Ty);
    break;
  }

  break;
}
case 'G':
  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
  if (!FC || !FC->isZero())
    return;
  // Soften float to i8 0
  Result = DAG.getTargetConstant(0, DL, MVT::i8);
  break;
}

if (Result.getNode()) {
  Ops.push_back(Result);
  return;
}

return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2227}

2229Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                            const MachineFunction &MF) const {
Register Reg;

if (VT == LLT::scalar(8)) {
  Reg = StringSwitch<unsigned>(RegName)
            .Case("r0", AVR::R0)
            .Case("r1", AVR::R1)
            .Default(0);
} else {
  Reg = StringSwitch<unsigned>(RegName)
            .Case("r0", AVR::R1R0)
            .Case("sp", AVR::SP)
            .Default(0);
}

if (Reg)
  return Reg;

report_fatal_error(
    Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2250}

2252} // end of namespace llvm

←

/build/llvm-toolchain-snapshot-15~++20220320100729+487629cc61b5/llvm/include/llvm/Support/MachineValueType.h

1//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of machine-level target independent types which
10// legal values in the code generator use.
11//
12//===----------------------------------------------------------------------===//

14#ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H
15#define LLVM_SUPPORT_MACHINEVALUETYPE_H

17#include "llvm/ADT/Sequence.h"
18#include "llvm/ADT/iterator_range.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/MathExtras.h"
21#include "llvm/Support/TypeSize.h"
22#include <cassert>

24namespace llvm {

class Type;

/// Machine Value Type. Every type that is supported natively by some
/// processor targeted by LLVM occurs here. This means that any legal value
/// type can be represented by an MVT.
class MVT {
public:
  enum SimpleValueType : uint8_t {
    // clang-format off

    // Simple value types that aren't explicitly part of this enumeration
    // are considered extended value types.
    INVALID_SIMPLE_VALUE_TYPE = 0,

    // If you change this numbering, you must change the values in
    // ValueTypes.td as well!
    Other          =   1,   // This is a non-standard value
    i1             =   2,   // This is a 1 bit integer value
    i8             =   3,   // This is an 8 bit integer value
    i16            =   4,   // This is a 16 bit integer value
    i32            =   5,   // This is a 32 bit integer value
    i64            =   6,   // This is a 64 bit integer value
    i128           =   7,   // This is a 128 bit integer value

    FIRST_INTEGER_VALUETYPE = i1,
    LAST_INTEGER_VALUETYPE  = i128,

    bf16           =   8,   // This is a 16 bit brain floating point value
    f16            =   9,   // This is a 16 bit floating point value
    f32            =  10,   // This is a 32 bit floating point value
    f64            =  11,   // This is a 64 bit floating point value
    f80            =  12,   // This is a 80 bit floating point value
    f128           =  13,   // This is a 128 bit floating point value
    ppcf128        =  14,   // This is a PPC 128-bit floating point value

    FIRST_FP_VALUETYPE = bf16,
    LAST_FP_VALUETYPE  = ppcf128,

    v1i1           =  15,   //    1 x i1
    v2i1           =  16,   //    2 x i1
    v4i1           =  17,   //    4 x i1
    v8i1           =  18,   //    8 x i1
    v16i1          =  19,   //   16 x i1
    v32i1          =  20,   //   32 x i1
    v64i1          =  21,   //   64 x i1
    v128i1         =  22,   //  128 x i1
    v256i1         =  23,   //  256 x i1
    v512i1         =  24,   //  512 x i1
    v1024i1        =  25,   // 1024 x i1

    v1i8           =  26,   //    1 x i8
    v2i8           =  27,   //    2 x i8
    v4i8           =  28,   //    4 x i8
    v8i8           =  29,   //    8 x i8
    v16i8          =  30,   //   16 x i8
    v32i8          =  31,   //   32 x i8
    v64i8          =  32,   //   64 x i8
    v128i8         =  33,   //  128 x i8
    v256i8         =  34,   //  256 x i8
    v512i8         =  35,   //  512 x i8
    v1024i8        =  36,   // 1024 x i8

    v1i16          =  37,   //   1 x i16
    v2i16          =  38,   //   2 x i16
    v3i16          =  39,   //   3 x i16
    v4i16          =  40,   //   4 x i16
    v8i16          =  41,   //   8 x i16
    v16i16         =  42,   //  16 x i16
    v32i16         =  43,   //  32 x i16
    v64i16         =  44,   //  64 x i16
    v128i16        =  45,   // 128 x i16
    v256i16        =  46,   // 256 x i16
    v512i16        =  47,   // 512 x i16

    v1i32          =  48,   //    1 x i32
    v2i32          =  49,   //    2 x i32
    v3i32          =  50,   //    3 x i32
    v4i32          =  51,   //    4 x i32
    v5i32          =  52,   //    5 x i32
    v6i32          =  53,   //    6 x i32
    v7i32          =  54,   //    7 x i32
    v8i32          =  55,   //    8 x i32
    v16i32         =  56,   //   16 x i32
    v32i32         =  57,   //   32 x i32
    v64i32         =  58,   //   64 x i32
    v128i32        =  59,   //  128 x i32
    v256i32        =  60,   //  256 x i32
    v512i32        =  61,   //  512 x i32
    v1024i32       =  62,   // 1024 x i32
    v2048i32       =  63,   // 2048 x i32

    v1i64          =  64,   //   1 x i64
    v2i64          =  65,   //   2 x i64
    v3i64          =  66,   //   3 x i64
    v4i64          =  67,   //   4 x i64
    v8i64          =  68,   //   8 x i64
    v16i64         =  69,   //  16 x i64
    v32i64         =  70,   //  32 x i64
    v64i64         =  71,   //  64 x i64
    v128i64        =  72,   // 128 x i64
    v256i64        =  73,   // 256 x i64

    v1i128         =  74,   //  1 x i128

    FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
    LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,

    v1f16          =  75,   //    1 x f16
    v2f16          =  76,   //    2 x f16
    v3f16          =  77,   //    3 x f16
    v4f16          =  78,   //    4 x f16
    v8f16          =  79,   //    8 x f16
    v16f16         =  80,   //   16 x f16
    v32f16         =  81,   //   32 x f16
    v64f16         =  82,   //   64 x f16
    v128f16        =  83,   //  128 x f16
    v256f16        =  84,   //  256 x f16
    v512f16        =  85,   //  256 x f16

    v2bf16         =  86,   //    2 x bf16
    v3bf16         =  87,   //    3 x bf16
    v4bf16         =  88,   //    4 x bf16
    v8bf16         =  89,   //    8 x bf16
    v16bf16        =  90,   //   16 x bf16
    v32bf16        =  91,   //   32 x bf16
    v64bf16        =  92,   //   64 x bf16
    v128bf16       =  93,   //  128 x bf16

    v1f32          =  94,   //    1 x f32
    v2f32          =  95,   //    2 x f32
    v3f32          =  96,   //    3 x f32
    v4f32          =  97,   //    4 x f32
    v5f32          =  98,   //    5 x f32
    v6f32          =  99,   //    6 x f32
    v7f32          = 100,   //    7 x f32
    v8f32          = 101,   //    8 x f32
    v16f32         = 102,   //   16 x f32
    v32f32         = 103,   //   32 x f32
    v64f32         = 104,   //   64 x f32
    v128f32        = 105,   //  128 x f32
    v256f32        = 106,   //  256 x f32
    v512f32        = 107,   //  512 x f32
    v1024f32       = 108,   // 1024 x f32
    v2048f32       = 109,   // 2048 x f32

    v1f64          = 110,   //    1 x f64
    v2f64          = 111,   //    2 x f64
    v3f64          = 112,   //    3 x f64
    v4f64          = 113,   //    4 x f64
    v8f64          = 114,   //    8 x f64
    v16f64         = 115,   //   16 x f64
    v32f64         = 116,   //   32 x f64
    v64f64         = 117,   //   64 x f64
    v128f64        = 118,   //  128 x f64
    v256f64        = 119,   //  256 x f64

    FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
    LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,

    FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
    LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,

    nxv1i1         = 120,   // n x  1 x i1
    nxv2i1         = 121,   // n x  2 x i1
    nxv4i1         = 122,   // n x  4 x i1
    nxv8i1         = 123,   // n x  8 x i1
    nxv16i1        = 124,   // n x 16 x i1
    nxv32i1        = 125,   // n x 32 x i1
    nxv64i1        = 126,   // n x 64 x i1

    nxv1i8         = 127,   // n x  1 x i8
    nxv2i8         = 128,   // n x  2 x i8
    nxv4i8         = 129,   // n x  4 x i8
    nxv8i8         = 130,   // n x  8 x i8
    nxv16i8        = 131,   // n x 16 x i8
    nxv32i8        = 132,   // n x 32 x i8
    nxv64i8        = 133,   // n x 64 x i8

    nxv1i16        = 134,  // n x  1 x i16
    nxv2i16        = 135,  // n x  2 x i16
    nxv4i16        = 136,  // n x  4 x i16
    nxv8i16        = 137,  // n x  8 x i16
    nxv16i16       = 138,  // n x 16 x i16
    nxv32i16       = 139,  // n x 32 x i16

    nxv1i32        = 140,  // n x  1 x i32
    nxv2i32        = 141,  // n x  2 x i32
    nxv4i32        = 142,  // n x  4 x i32
    nxv8i32        = 143,  // n x  8 x i32
    nxv16i32       = 144,  // n x 16 x i32
    nxv32i32       = 145,  // n x 32 x i32

    nxv1i64        = 146,  // n x  1 x i64
    nxv2i64        = 147,  // n x  2 x i64
    nxv4i64        = 148,  // n x  4 x i64
    nxv8i64        = 149,  // n x  8 x i64
    nxv16i64       = 150,  // n x 16 x i64
    nxv32i64       = 151,  // n x 32 x i64

    FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
    LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,

    nxv1f16        = 152,  // n x  1 x f16
    nxv2f16        = 153,  // n x  2 x f16
    nxv4f16        = 154,  // n x  4 x f16
    nxv8f16        = 155,  // n x  8 x f16
    nxv16f16       = 156,  // n x 16 x f16
    nxv32f16       = 157,  // n x 32 x f16

    nxv1bf16       = 158,  // n x  1 x bf16
    nxv2bf16       = 159,  // n x  2 x bf16
    nxv4bf16       = 160,  // n x  4 x bf16
    nxv8bf16       = 161,  // n x  8 x bf16

    nxv1f32        = 162,  // n x  1 x f32
    nxv2f32        = 163,  // n x  2 x f32
    nxv4f32        = 164,  // n x  4 x f32
    nxv8f32        = 165,  // n x  8 x f32
    nxv16f32       = 166,  // n x 16 x f32

    nxv1f64        = 167,  // n x  1 x f64
    nxv2f64        = 168,  // n x  2 x f64
    nxv4f64        = 169,  // n x  4 x f64
    nxv8f64        = 170,  // n x  8 x f64

    FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
    LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,

    FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
    LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,

    FIRST_VECTOR_VALUETYPE = v1i1,
    LAST_VECTOR_VALUETYPE  = nxv8f64,

    x86mmx         = 171,    // This is an X86 MMX value

    Glue           = 172,    // This glues nodes together during pre-RA sched

    isVoid         = 173,    // This has no value

    Untyped        = 174,    // This value takes a register, but has
                             // unspecified type.  The register class
                             // will be determined by the opcode.

    funcref        = 175,    // WebAssembly's funcref type
    externref      = 176,    // WebAssembly's externref type
    x86amx         = 177,    // This is an X86 AMX value
    i64x8          = 178,    // 8 Consecutive GPRs (AArch64)

    FIRST_VALUETYPE =  1,    // This is always the beginning of the list.
    LAST_VALUETYPE = i64x8,  // This always remains at the end of the list.
    VALUETYPE_SIZE = LAST_VALUETYPE + 1,

    // This is the current maximum for LAST_VALUETYPE.
    // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
    // This value must be a multiple of 32.
    MAX_ALLOWED_VALUETYPE = 192,

    // A value of type llvm::TokenTy
    token          = 248,

    // This is MDNode or MDString.
    Metadata       = 249,

    // An int value the size of the pointer of the current
    // target to any address space. This must only be used internal to
    // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR.
    iPTRAny        = 250,

    // A vector with any length and element size. This is used
    // for intrinsics that have overloadings based on vector types.
    // This is only for tblgen's consumption!
    vAny           = 251,

    // Any floating-point or vector floating-point value. This is used
    // for intrinsics that have overloadings based on floating-point types.
    // This is only for tblgen's consumption!
    fAny           = 252,

    // An integer or vector integer value of any bit width. This is
    // used for intrinsics that have overloadings based on integer bit widths.
    // This is only for tblgen's consumption!
    iAny           = 253,

    // An int value the size of the pointer of the current
    // target.  This should only be used internal to tblgen!
    iPTR           = 254,

    // Any type. This is used for intrinsics that have overloadings.
    // This is only for tblgen's consumption!
    Any            = 255

    // clang-format on
  };

  SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;

  constexpr MVT() = default;
  constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}

  bool operator>(const MVT& S)  const { return SimpleTy >  S.SimpleTy; }
  bool operator<(const MVT& S)  const { return SimpleTy <  S.SimpleTy; }
  bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
10
←
Assuming 'SimpleTy' is not equal to 'S.SimpleTy'→
11
←
Returning zero, which participates in a condition later→
  bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
  bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
  bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }

  /// Return true if this is a valid simple valuetype.
  bool isValid() const {
    return (SimpleTy >= MVT::FIRST_VALUETYPE &&
            SimpleTy <= MVT::LAST_VALUETYPE);
  }

  /// Return true if this is a FP or a vector FP type.
  bool isFloatingPoint() const {
    return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE));
  }

  /// Return true if this is an integer or a vector integer type.
  bool isInteger() const {
    return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
  }

  /// Return true if this is an integer, not including vectors.
  bool isScalarInteger() const {
    return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
            SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
  }

  /// Return true if this is a vector value type.
  bool isVector() const {
    return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
            SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
  }

  /// Return true if this is a vector value type where the
  /// runtime length is machine dependent
  bool isScalableVector() const {
    return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE &&
            SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
  }

  bool isFixedLengthVector() const {
    return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
            SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
  }

  /// Return true if this is a 16-bit vector type.
  bool is16BitVector() const {
    return (SimpleTy == MVT::v2i8  || SimpleTy == MVT::v1i16 ||
            SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16);
  }

  /// Return true if this is a 32-bit vector type.
  bool is32BitVector() const {
    return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8   ||
            SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32  ||
            SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
            SimpleTy == MVT::v1f32);
  }

  /// Return true if this is a 64-bit vector type.
  bool is64BitVector() const {
    return (SimpleTy == MVT::v64i1  || SimpleTy == MVT::v8i8  ||
            SimpleTy == MVT::v4i16  || SimpleTy == MVT::v2i32 ||
            SimpleTy == MVT::v1i64  || SimpleTy == MVT::v4f16 ||
            SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32  ||
            SimpleTy == MVT::v1f64);
  }

  /// Return true if this is a 128-bit vector type.
  bool is128BitVector() const {
    return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8  ||
            SimpleTy == MVT::v8i16  || SimpleTy == MVT::v4i32  ||
            SimpleTy == MVT::v2i64  || SimpleTy == MVT::v1i128 ||
            SimpleTy == MVT::v8f16  || SimpleTy == MVT::v8bf16 ||
            SimpleTy == MVT::v4f32  || SimpleTy == MVT::v2f64);
  }

  /// Return true if this is a 256-bit vector type.
  bool is256BitVector() const {
    return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
            SimpleTy == MVT::v8f32  || SimpleTy == MVT::v4f64   ||
            SimpleTy == MVT::v32i8  || SimpleTy == MVT::v16i16  ||
            SimpleTy == MVT::v8i32  || SimpleTy == MVT::v4i64   ||
            SimpleTy == MVT::v256i1);
  }

  /// Return true if this is a 512-bit vector type.
  bool is512BitVector() const {
    return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 ||
            SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64   ||
            SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8   ||
            SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32  ||
            SimpleTy == MVT::v8i64);
  }

  /// Return true if this is a 1024-bit vector type.
  bool is1024BitVector() const {
    return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 ||
            SimpleTy == MVT::v64i16  || SimpleTy == MVT::v32i32 ||
            SimpleTy == MVT::v16i64  || SimpleTy == MVT::v64f16 ||
            SimpleTy == MVT::v32f32  || SimpleTy == MVT::v16f64 ||
            SimpleTy == MVT::v64bf16);
  }

  /// Return true if this is a 2048-bit vector type.
  bool is2048BitVector() const {
    return (SimpleTy == MVT::v256i8  || SimpleTy == MVT::v128i16 ||
            SimpleTy == MVT::v64i32  || SimpleTy == MVT::v32i64  ||
            SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32  ||
            SimpleTy == MVT::v32f64  || SimpleTy == MVT::v128bf16);
  }

  /// Return true if this is an overloaded type for TableGen.
  bool isOverloaded() const {
    return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
            SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
            SimpleTy == MVT::iPTRAny);
  }

  /// Return a vector with the same number of elements as this vector, but
  /// with the element type converted to an integer type with the same
  /// bitwidth.
  MVT changeVectorElementTypeToInteger() const {
    MVT EltTy = getVectorElementType();
    MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits());
    MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount());
    assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
 && "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "llvm/include/llvm/Support/MachineValueType.h", 465, __extension__
 __PRETTY_FUNCTION__))
           "Simple vector VT not representable by simple integer vector VT!")(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
 && "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "llvm/include/llvm/Support/MachineValueType.h", 465, __extension__
 __PRETTY_FUNCTION__));
    return VecTy;
  }

  /// Return a VT for a vector type whose attributes match ourselves
  /// with the exception of the element type that is chosen by the caller.
  MVT changeVectorElementType(MVT EltVT) const {
    MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount());
    assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
 && "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "llvm/include/llvm/Support/MachineValueType.h", 474, __extension__
 __PRETTY_FUNCTION__))
           "Simple vector VT not representable by simple integer vector VT!")(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
 && "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "llvm/include/llvm/Support/MachineValueType.h", 474, __extension__
 __PRETTY_FUNCTION__));
    return VecTy;
  }

  /// Return the type converted to an equivalently sized integer or vector
  /// with integer element type. Similar to changeVectorElementTypeToInteger,
  /// but also handles scalars.
  MVT changeTypeToInteger() {
    if (isVector())
      return changeVectorElementTypeToInteger();
    return MVT::getIntegerVT(getSizeInBits());
  }

  /// Return a VT for a vector type with the same element type but
  /// half the number of elements.
  MVT getHalfNumVectorElementsVT() const {
    MVT EltVT = getVectorElementType();
    auto EltCnt = getVectorElementCount();
    assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")(static_cast <bool> (EltCnt.isKnownEven() && "Splitting vector, but not in half!"
) ? void (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\""
, "llvm/include/llvm/Support/MachineValueType.h", 492, __extension__
 __PRETTY_FUNCTION__));
    return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2));
  }

  /// Returns true if the given vector is a power of 2.
  bool isPow2VectorType() const {
    unsigned NElts = getVectorMinNumElements();
    return !(NElts & (NElts - 1));
  }

  /// Widens the length of the given vector MVT up to the nearest power of 2
  /// and returns that type.
  MVT getPow2VectorType() const {
    if (isPow2VectorType())
      return *this;

    ElementCount NElts = getVectorElementCount();
    unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue());
    NElts = ElementCount::get(NewMinCount, NElts.isScalable());
    return MVT::getVectorVT(getVectorElementType(), NElts);
  }

  /// If this is a vector, return the element type, otherwise return this.
  MVT getScalarType() const {
    return isVector() ? getVectorElementType() : *this;
  }

  MVT getVectorElementType() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "llvm/include/llvm/Support/MachineValueType.h"
, 522);
    case v1i1:
    case v2i1:
    case v4i1:
    case v8i1:
    case v16i1:
    case v32i1:
    case v64i1:
    case v128i1:
    case v256i1:
    case v512i1:
    case v1024i1:
    case nxv1i1:
    case nxv2i1:
    case nxv4i1:
    case nxv8i1:
    case nxv16i1:
    case nxv32i1:
    case nxv64i1: return i1;
    case v1i8:
    case v2i8:
    case v4i8:
    case v8i8:
    case v16i8:
    case v32i8:
    case v64i8:
    case v128i8:
    case v256i8:
    case v512i8:
    case v1024i8:
    case nxv1i8:
    case nxv2i8:
    case nxv4i8:
    case nxv8i8:
    case nxv16i8:
    case nxv32i8:
    case nxv64i8: return i8;
    case v1i16:
    case v2i16:
    case v3i16:
    case v4i16:
    case v8i16:
    case v16i16:
    case v32i16:
    case v64i16:
    case v128i16:
    case v256i16:
    case v512i16:
    case nxv1i16:
    case nxv2i16:
    case nxv4i16:
    case nxv8i16:
    case nxv16i16:
    case nxv32i16: return i16;
    case v1i32:
    case v2i32:
    case v3i32:
    case v4i32:
    case v5i32:
    case v6i32:
    case v7i32:
    case v8i32:
    case v16i32:
    case v32i32:
    case v64i32:
    case v128i32:
    case v256i32:
    case v512i32:
    case v1024i32:
    case v2048i32:
    case nxv1i32:
    case nxv2i32:
    case nxv4i32:
    case nxv8i32:
    case nxv16i32:
    case nxv32i32: return i32;
    case v1i64:
    case v2i64:
    case v3i64:
    case v4i64:
    case v8i64:
    case v16i64:
    case v32i64:
    case v64i64:
    case v128i64:
    case v256i64:
    case nxv1i64:
    case nxv2i64:
    case nxv4i64:
    case nxv8i64:
    case nxv16i64:
    case nxv32i64: return i64;
    case v1i128: return i128;
    case v1f16:
    case v2f16:
    case v3f16:
    case v4f16:
    case v8f16:
    case v16f16:
    case v32f16:
    case v64f16:
    case v128f16:
    case v256f16:
    case v512f16:
    case nxv1f16:
    case nxv2f16:
    case nxv4f16:
    case nxv8f16:
    case nxv16f16:
    case nxv32f16: return f16;
    case v2bf16:
    case v3bf16:
    case v4bf16:
    case v8bf16:
    case v16bf16:
    case v32bf16:
    case v64bf16:
    case v128bf16:
    case nxv1bf16:
    case nxv2bf16:
    case nxv4bf16:
    case nxv8bf16: return bf16;
    case v1f32:
    case v2f32:
    case v3f32:
    case v4f32:
    case v5f32:
    case v6f32:
    case v7f32:
    case v8f32:
    case v16f32:
    case v32f32:
    case v64f32:
    case v128f32:
    case v256f32:
    case v512f32:
    case v1024f32:
    case v2048f32:
    case nxv1f32:
    case nxv2f32:
    case nxv4f32:
    case nxv8f32:
    case nxv16f32: return f32;
    case v1f64:
    case v2f64:
    case v3f64:
    case v4f64:
    case v8f64:
    case v16f64:
    case v32f64:
    case v64f64:
    case v128f64:
    case v256f64:
    case nxv1f64:
    case nxv2f64:
    case nxv4f64:
    case nxv8f64: return f64;
    }
  }

  /// Given a vector type, return the minimum number of elements it contains.
  unsigned getVectorMinNumElements() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("Not a vector MVT!")::llvm::llvm_unreachable_internal("Not a vector MVT!", "llvm/include/llvm/Support/MachineValueType.h"
, 686);
    case v2048i32:
    case v2048f32: return 2048;
    case v1024i1:
    case v1024i8:
    case v1024i32:
    case v1024f32: return 1024;
    case v512i1:
    case v512i8:
    case v512i16:
    case v512i32:
    case v512f16:
    case v512f32: return 512;
    case v256i1:
    case v256i8:
    case v256i16:
    case v256f16:
    case v256i32:
    case v256i64:
    case v256f32:
    case v256f64: return 256;
    case v128i1:
    case v128i8:
    case v128i16:
    case v128i32:
    case v128i64:
    case v128f16:
    case v128bf16:
    case v128f32:
    case v128f64: return 128;
    case v64i1:
    case v64i8:
    case v64i16:
    case v64i32:
    case v64i64:
    case v64f16:
    case v64bf16:
    case v64f32:
    case v64f64:
    case nxv64i1:
    case nxv64i8: return 64;
    case v32i1:
    case v32i8:
    case v32i16:
    case v32i32:
    case v32i64:
    case v32f16:
    case v32bf16:
    case v32f32:
    case v32f64:
    case nxv32i1:
    case nxv32i8:
    case nxv32i16:
    case nxv32i32:
    case nxv32i64:
    case nxv32f16: return 32;
    case v16i1:
    case v16i8:
    case v16i16:
    case v16i32:
    case v16i64:
    case v16f16:
    case v16bf16:
    case v16f32:
    case v16f64:
    case nxv16i1:
    case nxv16i8:
    case nxv16i16:
    case nxv16i32:
    case nxv16i64:
    case nxv16f16:
    case nxv16f32: return 16;
    case v8i1:
    case v8i8:
    case v8i16:
    case v8i32:
    case v8i64:
    case v8f16:
    case v8bf16:
    case v8f32:
    case v8f64:
    case nxv8i1:
    case nxv8i8:
    case nxv8i16:
    case nxv8i32:
    case nxv8i64:
    case nxv8f16:
    case nxv8bf16:
    case nxv8f32:
    case nxv8f64: return 8;
    case v7i32:
    case v7f32: return 7;
    case v6i32:
    case v6f32: return 6;
    case v5i32:
    case v5f32: return 5;
    case v4i1:
    case v4i8:
    case v4i16:
    case v4i32:
    case v4i64:
    case v4f16:
    case v4bf16:
    case v4f32:
    case v4f64:
    case nxv4i1:
    case nxv4i8:
    case nxv4i16:
    case nxv4i32:
    case nxv4i64:
    case nxv4f16:
    case nxv4bf16:
    case nxv4f32:
    case nxv4f64: return 4;
    case v3i16:
    case v3i32:
    case v3i64:
    case v3f16:
    case v3bf16:
    case v3f32:
    case v3f64: return 3;
    case v2i1:
    case v2i8:
    case v2i16:
    case v2i32:
    case v2i64:
    case v2f16:
    case v2bf16:
    case v2f32:
    case v2f64:
    case nxv2i1:
    case nxv2i8:
    case nxv2i16:
    case nxv2i32:
    case nxv2i64:
    case nxv2f16:
    case nxv2bf16:
    case nxv2f32:
    case nxv2f64: return 2;
    case v1i1:
    case v1i8:
    case v1i16:
    case v1i32:
    case v1i64:
    case v1i128:
    case v1f16:
    case v1f32:
    case v1f64:
    case nxv1i1:
    case nxv1i8:
    case nxv1i16:
    case nxv1i32:
    case nxv1i64:
    case nxv1f16:
    case nxv1bf16:
    case nxv1f32:
    case nxv1f64: return 1;
    }
  }

  ElementCount getVectorElementCount() const {
    return ElementCount::get(getVectorMinNumElements(), isScalableVector());
  }

  unsigned getVectorNumElements() const {
    if (isScalableVector())
      llvm::reportInvalidSizeRequest(
          "Possible incorrect use of MVT::getVectorNumElements() for "
          "scalable vector. Scalable flag may be dropped, use "
          "MVT::getVectorElementCount() instead");
    return getVectorMinNumElements();
  }

  /// Returns the size of the specified MVT in bits.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getSizeInBits() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("getSizeInBits called on extended MVT.")::llvm::llvm_unreachable_internal("getSizeInBits called on extended MVT."
, "llvm/include/llvm/Support/MachineValueType.h", 867);
    case Other:
      llvm_unreachable("Value type is non-standard value, Other.")::llvm::llvm_unreachable_internal("Value type is non-standard value, Other."
, "llvm/include/llvm/Support/MachineValueType.h", 869);
    case iPTR:
      llvm_unreachable("Value type size is target-dependent. Ask TLI.")::llvm::llvm_unreachable_internal("Value type size is target-dependent. Ask TLI."
, "llvm/include/llvm/Support/MachineValueType.h", 871);
    case iPTRAny:
    case iAny:
    case fAny:
    case vAny:
    case Any:
      llvm_unreachable("Value type is overloaded.")::llvm::llvm_unreachable_internal("Value type is overloaded."
, "llvm/include/llvm/Support/MachineValueType.h", 877);
    case token:
      llvm_unreachable("Token type is a sentinel that cannot be used "::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
 "in codegen and has no size", "llvm/include/llvm/Support/MachineValueType.h"
, 880)
                       "in codegen and has no size")::llvm::llvm_unreachable_internal("Token type is a sentinel that cannot be used "
 "in codegen and has no size", "llvm/include/llvm/Support/MachineValueType.h"
, 880);
    case Metadata:
      llvm_unreachable("Value type is metadata.")::llvm::llvm_unreachable_internal("Value type is metadata.", "llvm/include/llvm/Support/MachineValueType.h"
, 882);
    case i1:
    case v1i1: return TypeSize::Fixed(1);
    case nxv1i1: return TypeSize::Scalable(1);
    case v2i1: return TypeSize::Fixed(2);
    case nxv2i1: return TypeSize::Scalable(2);
    case v4i1: return TypeSize::Fixed(4);
    case nxv4i1: return TypeSize::Scalable(4);
    case i8  :
    case v1i8:
    case v8i1: return TypeSize::Fixed(8);
    case nxv1i8:
    case nxv8i1: return TypeSize::Scalable(8);
    case i16 :
    case f16:
    case bf16:
    case v16i1:
    case v2i8:
    case v1i16:
    case v1f16: return TypeSize::Fixed(16);
    case nxv16i1:
    case nxv2i8:
    case nxv1i16:
    case nxv1bf16:
    case nxv1f16: return TypeSize::Scalable(16);
    case f32 :
    case i32 :
    case v32i1:
    case v4i8:
    case v2i16:
    case v2f16:
    case v2bf16:
    case v1f32:
    case v1i32: return TypeSize::Fixed(32);
    case nxv32i1:
    case nxv4i8:
    case nxv2i16:
    case nxv1i32:
    case nxv2f16:
    case nxv2bf16:
    case nxv1f32: return TypeSize::Scalable(32);
    case v3i16:
    case v3f16:
    case v3bf16: return TypeSize::Fixed(48);
    case x86mmx:
    case f64 :
    case i64 :
    case v64i1:
    case v8i8:
    case v4i16:
    case v2i32:
    case v1i64:
    case v4f16:
    case v4bf16:
    case v2f32:
    case v1f64: return TypeSize::Fixed(64);
    case nxv64i1:
    case nxv8i8:
    case nxv4i16:
    case nxv2i32:
    case nxv1i64:
    case nxv4f16:
    case nxv4bf16:
    case nxv2f32:
    case nxv1f64: return TypeSize::Scalable(64);
    case f80 :  return TypeSize::Fixed(80);
    case v3i32:
    case v3f32: return TypeSize::Fixed(96);
    case f128:
    case ppcf128:
    case i128:
    case v128i1:
    case v16i8:
    case v8i16:
    case v4i32:
    case v2i64:
    case v1i128:
    case v8f16:
    case v8bf16:
    case v4f32:
    case v2f64: return TypeSize::Fixed(128);
    case nxv16i8:
    case nxv8i16:
    case nxv4i32:
    case nxv2i64:
    case nxv8f16:
    case nxv8bf16:
    case nxv4f32:
    case nxv2f64: return TypeSize::Scalable(128);
    case v5i32:
    case v5f32: return TypeSize::Fixed(160);
    case v6i32:
    case v3i64:
    case v6f32:
    case v3f64: return TypeSize::Fixed(192);
    case v7i32:
    case v7f32: return TypeSize::Fixed(224);
    case v256i1:
    case v32i8:
    case v16i16:
    case v8i32:
    case v4i64:
    case v16f16:
    case v16bf16:
    case v8f32:
    case v4f64: return TypeSize::Fixed(256);
    case nxv32i8:
    case nxv16i16:
    case nxv8i32:
    case nxv4i64:
    case nxv16f16:
    case nxv8f32:
    case nxv4f64: return TypeSize::Scalable(256);
    case i64x8:
    case v512i1:
    case v64i8:
    case v32i16:
    case v16i32:
    case v8i64:
    case v32f16:
    case v32bf16:
    case v16f32:
    case v8f64: return TypeSize::Fixed(512);
    case nxv64i8:
    case nxv32i16:
    case nxv16i32:
    case nxv8i64:
    case nxv32f16:
    case nxv16f32:
    case nxv8f64: return TypeSize::Scalable(512);
    case v1024i1:
    case v128i8:
    case v64i16:
    case v32i32:
    case v16i64:
    case v64f16:
    case v64bf16:
    case v32f32:
    case v16f64: return TypeSize::Fixed(1024);
    case nxv32i32:
    case nxv16i64: return TypeSize::Scalable(1024);
    case v256i8:
    case v128i16:
    case v64i32:
    case v32i64:
    case v128f16:
    case v128bf16:
    case v64f32:
    case v32f64: return TypeSize::Fixed(2048);
    case nxv32i64: return TypeSize::Scalable(2048);
    case v512i8:
    case v256i16:
    case v128i32:
    case v64i64:
    case v256f16:
    case v128f32:
    case v64f64:  return TypeSize::Fixed(4096);
    case v1024i8:
    case v512i16:
    case v256i32:
    case v128i64:
    case v512f16:
    case v256f32:
    case x86amx:
    case v128f64:  return TypeSize::Fixed(8192);
    case v512i32:
    case v256i64:
    case v512f32:
    case v256f64:  return TypeSize::Fixed(16384);
    case v1024i32:
    case v1024f32:  return TypeSize::Fixed(32768);
    case v2048i32:
    case v2048f32:  return TypeSize::Fixed(65536);
    case funcref:
    case externref: return TypeSize::Fixed(0); // opaque type
    }
  }

  /// Return the size of the specified fixed width value type in bits. The
  /// function will assert if the type is scalable.
  uint64_t getFixedSizeInBits() const {
    return getSizeInBits().getFixedSize();
  }

  uint64_t getScalarSizeInBits() const {
    return getScalarType().getSizeInBits().getFixedSize();
  }

  /// Return the number of bytes overwritten by a store of the specified value
  /// type.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getStoreSize() const {
    TypeSize BaseSize = getSizeInBits();
    return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
  }

  /// Return the number of bits overwritten by a store of the specified value
  /// type.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getStoreSizeInBits() const {
    return getStoreSize() * 8;
  }

  /// Returns true if the number of bits for the type is a multiple of an
  /// 8-bit byte.
  bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }

  /// Return true if we know at compile time this has more bits than VT.
  bool knownBitsGT(MVT VT) const {
    return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has more than or the same
  /// bits as VT.
  bool knownBitsGE(MVT VT) const {
    return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has fewer bits than VT.
  bool knownBitsLT(MVT VT) const {
    return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has fewer than or the same
  /// bits as VT.
  bool knownBitsLE(MVT VT) const {
    return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if this has more bits than VT.
  bool bitsGT(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1120, __extension__
 __PRETTY_FUNCTION__))
           "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1120, __extension__
 __PRETTY_FUNCTION__));
    return knownBitsGT(VT);
  }

  /// Return true if this has no less bits than VT.
  bool bitsGE(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1127, __extension__
 __PRETTY_FUNCTION__))
           "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1127, __extension__
 __PRETTY_FUNCTION__));
    return knownBitsGE(VT);
  }

  /// Return true if this has less bits than VT.
  bool bitsLT(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1134, __extension__
 __PRETTY_FUNCTION__))
           "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1134, __extension__
 __PRETTY_FUNCTION__));
    return knownBitsLT(VT);
  }

  /// Return true if this has no more bits than VT.
  bool bitsLE(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1141, __extension__
 __PRETTY_FUNCTION__))
           "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector
() && "Comparison between scalable and fixed types") ?
 void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\""
, "llvm/include/llvm/Support/MachineValueType.h", 1141, __extension__
 __PRETTY_FUNCTION__));
    return knownBitsLE(VT);
  }

  static MVT getFloatingPointVT(unsigned BitWidth) {
    switch (BitWidth) {
    default:
      llvm_unreachable("Bad bit width!")::llvm::llvm_unreachable_internal("Bad bit width!", "llvm/include/llvm/Support/MachineValueType.h"
, 1148);
    case 16:
      return MVT::f16;
    case 32:
      return MVT::f32;
    case 64:
      return MVT::f64;
    case 80:
      return MVT::f80;
    case 128:
      return MVT::f128;
    }
  }

  static MVT getIntegerVT(unsigned BitWidth) {
    switch (BitWidth) {
    default:
      return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
    case 1:
      return MVT::i1;
    case 8:
      return MVT::i8;
    case 16:
      return MVT::i16;
    case 32:
      return MVT::i32;
    case 64:
      return MVT::i64;
    case 128:
      return MVT::i128;
    }
  }

  static MVT getVectorVT(MVT VT, unsigned NumElements) {
    switch (VT.SimpleTy) {
    default:
      break;
    case MVT::i1:
      if (NumElements == 1)    return MVT::v1i1;
      if (NumElements == 2)    return MVT::v2i1;
      if (NumElements == 4)    return MVT::v4i1;
      if (NumElements == 8)    return MVT::v8i1;
      if (NumElements == 16)   return MVT::v16i1;
      if (NumElements == 32)   return MVT::v32i1;
      if (NumElements == 64)   return MVT::v64i1;
      if (NumElements == 128)  return MVT::v128i1;
      if (NumElements == 256)  return MVT::v256i1;
      if (NumElements == 512)  return MVT::v512i1;
      if (NumElements == 1024) return MVT::v1024i1;
      break;
    case MVT::i8:
      if (NumElements == 1)   return MVT::v1i8;
      if (NumElements == 2)   return MVT::v2i8;
      if (NumElements == 4)   return MVT::v4i8;
      if (NumElements == 8)   return MVT::v8i8;
      if (NumElements == 16)  return MVT::v16i8;
      if (NumElements == 32)  return MVT::v32i8;
      if (NumElements == 64)  return MVT::v64i8;
      if (NumElements == 128) return MVT::v128i8;
      if (NumElements == 256) return MVT::v256i8;
      if (NumElements == 512) return MVT::v512i8;
      if (NumElements == 1024) return MVT::v1024i8;
      break;
    case MVT::i16:
      if (NumElements == 1)   return MVT::v1i16;
      if (NumElements == 2)   return MVT::v2i16;
      if (NumElements == 3)   return MVT::v3i16;
      if (NumElements == 4)   return MVT::v4i16;
      if (NumElements == 8)   return MVT::v8i16;
      if (NumElements == 16)  return MVT::v16i16;
      if (NumElements == 32)  return MVT::v32i16;
      if (NumElements == 64)  return MVT::v64i16;
      if (NumElements == 128) return MVT::v128i16;
      if (NumElements == 256) return MVT::v256i16;
      if (NumElements == 512) return MVT::v512i16;
      break;
    case MVT::i32:
      if (NumElements == 1)    return MVT::v1i32;
      if (NumElements == 2)    return MVT::v2i32;
      if (NumElements == 3)    return MVT::v3i32;
      if (NumElements == 4)    return MVT::v4i32;
      if (NumElements == 5)    return MVT::v5i32;
      if (NumElements == 6)    return MVT::v6i32;
      if (NumElements == 7)    return MVT::v7i32;
      if (NumElements == 8)    return MVT::v8i32;
      if (NumElements == 16)   return MVT::v16i32;
      if (NumElements == 32)   return MVT::v32i32;
      if (NumElements == 64)   return MVT::v64i32;
      if (NumElements == 128)  return MVT::v128i32;
      if (NumElements == 256)  return MVT::v256i32;
      if (NumElements == 512)  return MVT::v512i32;
      if (NumElements == 1024) return MVT::v1024i32;
      if (NumElements == 2048) return MVT::v2048i32;
      break;
    case MVT::i64:
      if (NumElements == 1)  return MVT::v1i64;
      if (NumElements == 2)  return MVT::v2i64;
      if (NumElements == 3)  return MVT::v3i64;
      if (NumElements == 4)  return MVT::v4i64;
      if (NumElements == 8)  return MVT::v8i64;
      if (NumElements == 16) return MVT::v16i64;
      if (NumElements == 32) return MVT::v32i64;
      if (NumElements == 64) return MVT::v64i64;
      if (NumElements == 128) return MVT::v128i64;
      if (NumElements == 256) return MVT::v256i64;
      break;
    case MVT::i128:
      if (NumElements == 1)  return MVT::v1i128;
      break;
    case MVT::f16:
      if (NumElements == 1)   return MVT::v1f16;
      if (NumElements == 2)   return MVT::v2f16;
      if (NumElements == 3)   return MVT::v3f16;
      if (NumElements == 4)   return MVT::v4f16;
      if (NumElements == 8)   return MVT::v8f16;
      if (NumElements == 16)  return MVT::v16f16;
      if (NumElements == 32)  return MVT::v32f16;
      if (NumElements == 64)  return MVT::v64f16;
      if (NumElements == 128) return MVT::v128f16;
      if (NumElements == 256) return MVT::v256f16;
      if (NumElements == 512) return MVT::v512f16;
      break;
    case MVT::bf16:
      if (NumElements == 2)   return MVT::v2bf16;
      if (NumElements == 3)   return MVT::v3bf16;
      if (NumElements == 4)   return MVT::v4bf16;
      if (NumElements == 8)   return MVT::v8bf16;
      if (NumElements == 16)  return MVT::v16bf16;
      if (NumElements == 32)  return MVT::v32bf16;
      if (NumElements == 64)  return MVT::v64bf16;
      if (NumElements == 128) return MVT::v128bf16;
      break;
    case MVT::f32:
      if (NumElements == 1)    return MVT::v1f32;
      if (NumElements == 2)    return MVT::v2f32;
      if (NumElements == 3)    return MVT::v3f32;
      if (NumElements == 4)    return MVT::v4f32;
      if (NumElements == 5)    return MVT::v5f32;
      if (NumElements == 6)    return MVT::v6f32;
      if (NumElements == 7)    return MVT::v7f32;
      if (NumElements == 8)    return MVT::v8f32;
      if (NumElements == 16)   return MVT::v16f32;
      if (NumElements == 32)   return MVT::v32f32;
      if (NumElements == 64)   return MVT::v64f32;
      if (NumElements == 128)  return MVT::v128f32;
      if (NumElements == 256)  return MVT::v256f32;
      if (NumElements == 512)  return MVT::v512f32;
      if (NumElements == 1024) return MVT::v1024f32;
      if (NumElements == 2048) return MVT::v2048f32;
      break;
    case MVT::f64:
      if (NumElements == 1)  return MVT::v1f64;
      if (NumElements == 2)  return MVT::v2f64;
      if (NumElements == 3)  return MVT::v3f64;
      if (NumElements == 4)  return MVT::v4f64;
      if (NumElements == 8)  return MVT::v8f64;
      if (NumElements == 16) return MVT::v16f64;
      if (NumElements == 32) return MVT::v32f64;
      if (NumElements == 64) return MVT::v64f64;
      if (NumElements == 128) return MVT::v128f64;
      if (NumElements == 256) return MVT::v256f64;
      break;
    }
    return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
  }

  static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
    switch(VT.SimpleTy) {
      default:
        break;
      case MVT::i1:
        if (NumElements == 1)  return MVT::nxv1i1;
        if (NumElements == 2)  return MVT::nxv2i1;
        if (NumElements == 4)  return MVT::nxv4i1;
        if (NumElements == 8)  return MVT::nxv8i1;
        if (NumElements == 16) return MVT::nxv16i1;
        if (NumElements == 32) return MVT::nxv32i1;
        if (NumElements == 64) return MVT::nxv64i1;
        break;
      case MVT::i8:
        if (NumElements == 1)  return MVT::nxv1i8;
        if (NumElements == 2)  return MVT::nxv2i8;
        if (NumElements == 4)  return MVT::nxv4i8;
        if (NumElements == 8)  return MVT::nxv8i8;
        if (NumElements == 16) return MVT::nxv16i8;
        if (NumElements == 32) return MVT::nxv32i8;
        if (NumElements == 64) return MVT::nxv64i8;
        break;
      case MVT::i16:
        if (NumElements == 1)  return MVT::nxv1i16;
        if (NumElements == 2)  return MVT::nxv2i16;
        if (NumElements == 4)  return MVT::nxv4i16;
        if (NumElements == 8)  return MVT::nxv8i16;
        if (NumElements == 16) return MVT::nxv16i16;
        if (NumElements == 32) return MVT::nxv32i16;
        break;
      case MVT::i32:
        if (NumElements == 1)  return MVT::nxv1i32;
        if (NumElements == 2)  return MVT::nxv2i32;
        if (NumElements == 4)  return MVT::nxv4i32;
        if (NumElements == 8)  return MVT::nxv8i32;
        if (NumElements == 16) return MVT::nxv16i32;
        if (NumElements == 32) return MVT::nxv32i32;
        break;
      case MVT::i64:
        if (NumElements == 1)  return MVT::nxv1i64;
        if (NumElements == 2)  return MVT::nxv2i64;
        if (NumElements == 4)  return MVT::nxv4i64;
        if (NumElements == 8)  return MVT::nxv8i64;
        if (NumElements == 16) return MVT::nxv16i64;
        if (NumElements == 32) return MVT::nxv32i64;
        break;
      case MVT::f16:
        if (NumElements == 1)  return MVT::nxv1f16;
        if (NumElements == 2)  return MVT::nxv2f16;
        if (NumElements == 4)  return MVT::nxv4f16;
        if (NumElements == 8)  return MVT::nxv8f16;
        if (NumElements == 16)  return MVT::nxv16f16;
        if (NumElements == 32)  return MVT::nxv32f16;
        break;
      case MVT::bf16:
        if (NumElements == 1)  return MVT::nxv1bf16;
        if (NumElements == 2)  return MVT::nxv2bf16;
        if (NumElements == 4)  return MVT::nxv4bf16;
        if (NumElements == 8)  return MVT::nxv8bf16;
        break;
      case MVT::f32:
        if (NumElements == 1)  return MVT::nxv1f32;
        if (NumElements == 2)  return MVT::nxv2f32;
        if (NumElements == 4)  return MVT::nxv4f32;
        if (NumElements == 8)  return MVT::nxv8f32;
        if (NumElements == 16) return MVT::nxv16f32;
        break;
      case MVT::f64:
        if (NumElements == 1)  return MVT::nxv1f64;
        if (NumElements == 2)  return MVT::nxv2f64;
        if (NumElements == 4)  return MVT::nxv4f64;
        if (NumElements == 8)  return MVT::nxv8f64;
        break;
    }
    return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
  }

  static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
    if (IsScalable)
      return getScalableVectorVT(VT, NumElements);
    return getVectorVT(VT, NumElements);
  }

  static MVT getVectorVT(MVT VT, ElementCount EC) {
    if (EC.isScalable())
      return getScalableVectorVT(VT, EC.getKnownMinValue());
    return getVectorVT(VT, EC.getKnownMinValue());
  }

  /// Return the value type corresponding to the specified type.  This returns
  /// all pointers as iPTR.  If HandleUnknown is true, unknown types are
  /// returned as Other, otherwise they are invalid.
  static MVT getVT(Type *Ty, bool HandleUnknown = false);

public:
  /// SimpleValueType Iteration
  /// @{
  static auto all_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto integer_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_INTEGER_VALUETYPE,
                              MVT::LAST_INTEGER_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto fp_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_FP_VALUETYPE, MVT::LAST_FP_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_VECTOR_VALUETYPE,
                              MVT::LAST_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto fixedlen_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE,
                              MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto scalable_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_SCALABLE_VECTOR_VALUETYPE,
                              MVT::LAST_SCALABLE_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto integer_fixedlen_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
                              MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto fp_fixedlen_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE,
                              MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto integer_scalable_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
                              MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }

  static auto fp_scalable_vector_valuetypes() {
    return enum_seq_inclusive(MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
                              MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE,
                              force_iteration_on_noniterable_enum);
  }
  /// @}
};

1471} // end namespace llvm

1473#endif // LLVM_SUPPORT_MACHINEVALUETYPE_H