Bug Summary

File:build/source/llvm/include/llvm/CodeGen/CallingConvLower.h
Warning:line 394, column 54
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PPCCallingConv.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-17/lib/clang/17 -D _DEBUG -D _GLIBCXX_ASSERTIONS -D _GNU_SOURCE -D _LIBCPP_ENABLE_ASSERTIONS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/PowerPC -I /build/source/llvm/lib/Target/PowerPC -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-17/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1683717183 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-05-10-133810-16478-1 -x c++ /build/source/llvm/lib/Target/PowerPC/PPCCallingConv.cpp

/build/source/llvm/lib/Target/PowerPC/PPCCallingConv.cpp

→
1//===-- PPCCallingConv.cpp - ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "PPCRegisterInfo.h"
10#include "PPCCallingConv.h"
11#include "PPCSubtarget.h"
12#include "PPCCCState.h"
13using namespace llvm;
14
15inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
16 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
17 CCState &) {
18 llvm_unreachable("The AnyReg calling convention is only supported by the " \::llvm::llvm_unreachable_internal("The AnyReg calling convention is only supported by the "
"stackmap and patchpoint intrinsics.", "llvm/lib/Target/PowerPC/PPCCallingConv.cpp"
, 19)
19 "stackmap and patchpoint intrinsics.")::llvm::llvm_unreachable_internal("The AnyReg calling convention is only supported by the "
"stackmap and patchpoint intrinsics.", "llvm/lib/Target/PowerPC/PPCCallingConv.cpp"
, 19);
20 // gracefully fallback to PPC C calling convention on Release builds.
21 return false;
22}
23
24// This function handles the shadowing of GPRs for fp and vector types,
25// and is a depiction of the algorithm described in the ELFv2 ABI,
26// Section 2.2.4.1: Parameter Passing Register Selection Algorithm.
27inline bool CC_PPC64_ELF_Shadow_GPR_Regs(unsigned &ValNo, MVT &ValVT,
28 MVT &LocVT,
29 CCValAssign::LocInfo &LocInfo,
30 ISD::ArgFlagsTy &ArgFlags,
31 CCState &State) {
32
33 // The 64-bit ELFv2 ABI-defined parameter passing general purpose registers.
34 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
35 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
36 const unsigned ELF64NumArgGPRs = std::size(ELF64ArgGPRs);
37
38 unsigned FirstUnallocGPR = State.getFirstUnallocated(ELF64ArgGPRs);
39 if (FirstUnallocGPR == ELF64NumArgGPRs)
40 return false;
41
42 // As described in 2.2.4.1 under the "float" section, shadow a single GPR
43 // for single/double precision. ppcf128 gets broken up into two doubles
44 // and will also shadow GPRs within this section.
45 if (LocVT == MVT::f32 || LocVT == MVT::f64)
46 State.AllocateReg(ELF64ArgGPRs);
47 else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) {
48 // For vector and __float128 (which is represents the "vector" section
49 // in 2.2.4.1), shadow two even GPRs (skipping the odd one if it is next
50 // in the allocation order). To check if the GPR is even, the specific
51 // condition checks if the register allocated is odd, because the even
52 // physical registers are odd values.
53 if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1)
54 State.AllocateReg(ELF64ArgGPRs);
55 State.AllocateReg(ELF64ArgGPRs);
56 }
57 return false;
58}
59
60static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
61 CCValAssign::LocInfo &LocInfo,
62 ISD::ArgFlagsTy &ArgFlags,
63 CCState &State) {
64 return true;
65}
66
67static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
68 MVT &LocVT,
69 CCValAssign::LocInfo &LocInfo,
70 ISD::ArgFlagsTy &ArgFlags,
71 CCState &State) {
72 static const MCPhysReg ArgRegs[] = {
73 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
74 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
75 };
76 const unsigned NumArgRegs = std::size(ArgRegs);
77
78 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
79
80 // Skip one register if the first unallocated register has an even register
81 // number and there are still argument registers available which have not been
82 // allocated yet. RegNum is actually an index into ArgRegs, which means we
83 // need to skip a register if RegNum is odd.
84 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
85 State.AllocateReg(ArgRegs[RegNum]);
86 }
87
88 // Always return false here, as this function only makes sure that the first
89 // unallocated register has an odd register number and does not actually
90 // allocate a register for the current argument.
91 return false;
92}
93
94static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(
95 unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
96 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
97 static const MCPhysReg ArgRegs[] = {
98 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
99 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
100 };
101 const unsigned NumArgRegs = std::size(ArgRegs);
102
103 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
104 int RegsLeft = NumArgRegs - RegNum;
105
106 // Skip if there is not enough registers left for long double type (4 gpr regs
107 // in soft float mode) and put long double argument on the stack.
108 if (RegNum != NumArgRegs && RegsLeft < 4) {
109 for (int i = 0; i < RegsLeft; i++) {
110 State.AllocateReg(ArgRegs[RegNum + i]);
111 }
112 }
113
114 return false;
115}
116
117static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
118 MVT &LocVT,
119 CCValAssign::LocInfo &LocInfo,
120 ISD::ArgFlagsTy &ArgFlags,
121 CCState &State) {
122 static const MCPhysReg ArgRegs[] = {
123 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
124 PPC::F8
125 };
126
127 const unsigned NumArgRegs = std::size(ArgRegs);
128
129 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
130
131 // If there is only one Floating-point register left we need to put both f64
132 // values of a split ppc_fp128 value on the stack.
133 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
134 State.AllocateReg(ArgRegs[RegNum]);
135 }
136
137 // Always return false here, as this function only makes sure that the two f64
138 // values a ppc_fp128 value is split into are both passed in registers or both
139 // passed on the stack and does not actually allocate a register for the
140 // current argument.
141 return false;
142}
143
144// Split F64 arguments into two 32-bit consecutive registers.
145static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
146 MVT &LocVT,
147 CCValAssign::LocInfo &LocInfo,
148 ISD::ArgFlagsTy &ArgFlags,
149 CCState &State) {
150 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
151 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
152
153 // Try to get the first register.
154 unsigned Reg = State.AllocateReg(HiRegList);
155 if (!Reg)
156 return false;
157
158 unsigned i;
159 for (i = 0; i < std::size(HiRegList); ++i)
160 if (HiRegList[i] == Reg)
161 break;
162
163 unsigned T = State.AllocateReg(LoRegList[i]);
164 (void)T;
165 assert(T == LoRegList[i] && "Could not allocate register")(static_cast <bool> (T == LoRegList[i] && "Could not allocate register"
) ? void (0) : __assert_fail ("T == LoRegList[i] && \"Could not allocate register\""
, "llvm/lib/Target/PowerPC/PPCCallingConv.cpp", 165, __extension__
__PRETTY_FUNCTION__));
166
167 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
168 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
169 LocVT, LocInfo));
170 return true;
171}
172
173// Same as above, but for return values, so only allocate for R3 and R4
174static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
175 MVT &LocVT,
176 CCValAssign::LocInfo &LocInfo,
177 ISD::ArgFlagsTy &ArgFlags,
178 CCState &State) {
179 static const MCPhysReg HiRegList[] = { PPC::R3 };
180 static const MCPhysReg LoRegList[] = { PPC::R4 };
181
182 // Try to get the first register.
183 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
1
Calling 'CCState::AllocateReg'
→
184 if (!Reg)
185 return false;
186
187 unsigned i;
188 for (i = 0; i < std::size(HiRegList); ++i)
189 if (HiRegList[i] == Reg)
190 break;
191
192 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
194 LocVT, LocInfo));
195 return true;
196}
197
198#include "PPCGenCallingConv.inc"
←

/build/source/llvm/include/llvm/CodeGen/CallingConvLower.h

1//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the CCState and CCValAssign classes, used for lowering
10// and implementing calling conventions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
15#define LLVM_CODEGEN_CALLINGCONVLOWER_H
16
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/Register.h"
19#include "llvm/CodeGen/TargetCallingConv.h"
20#include "llvm/IR/CallingConv.h"
21#include "llvm/Support/Alignment.h"
22
23namespace llvm {
24
25class CCState;
26class MachineFunction;
27class MVT;
28class TargetRegisterInfo;
29
30/// CCValAssign - Represent assignment of one arg/retval to a location.
31class CCValAssign {
32public:
33 enum LocInfo {
34 Full, // The value fills the full location.
35 SExt, // The value is sign extended in the location.
36 ZExt, // The value is zero extended in the location.
37 AExt, // The value is extended with undefined upper bits.
38 SExtUpper, // The value is in the upper bits of the location and should be
39 // sign extended when retrieved.
40 ZExtUpper, // The value is in the upper bits of the location and should be
41 // zero extended when retrieved.
42 AExtUpper, // The value is in the upper bits of the location and should be
43 // extended with undefined upper bits when retrieved.
44 BCvt, // The value is bit-converted in the location.
45 Trunc, // The value is truncated in the location.
46 VExt, // The value is vector-widened in the location.
47 // FIXME: Not implemented yet. Code that uses AExt to mean
48 // vector-widen should be fixed to use VExt instead.
49 FPExt, // The floating-point value is fp-extended in the location.
50 Indirect // The location contains pointer to the value.
51 // TODO: a subset of the value is in the location.
52 };
53
54private:
55 // Holds one of:
56 // - the register that the value is assigned to;
57 // - the memory offset at which the value resides;
58 // - additional information about pending location; the exact interpretation
59 // of the data is target-dependent.
60 std::variant<Register, int64_t, unsigned> Data;
61
62 /// ValNo - This is the value number being assigned (e.g. an argument number).
63 unsigned ValNo;
64
65 /// isCustom - True if this arg/retval requires special handling.
66 unsigned isCustom : 1;
67
68 /// Information about how the value is assigned.
69 LocInfo HTP : 6;
70
71 /// ValVT - The type of the value being assigned.
72 MVT ValVT;
73
74 /// LocVT - The type of the location being assigned to.
75 MVT LocVT;
76
77 CCValAssign(LocInfo HTP, unsigned ValNo, MVT ValVT, MVT LocVT, bool IsCustom)
78 : ValNo(ValNo), isCustom(IsCustom), HTP(HTP), ValVT(ValVT), LocVT(LocVT) {
79 }
80
81public:
82 static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
83 MVT LocVT, LocInfo HTP, bool IsCustom = false) {
84 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, IsCustom);
85 Ret.Data = Register(RegNo);
86 return Ret;
87 }
88
89 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
90 MVT LocVT, LocInfo HTP) {
91 return getReg(ValNo, ValVT, RegNo, LocVT, HTP, /*IsCustom=*/true);
92 }
93
94 static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset,
95 MVT LocVT, LocInfo HTP, bool IsCustom = false) {
96 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, IsCustom);
97 Ret.Data = int64_t(Offset);
98 return Ret;
99 }
100
101 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset,
102 MVT LocVT, LocInfo HTP) {
103 return getMem(ValNo, ValVT, Offset, LocVT, HTP, /*IsCustom=*/true);
104 }
105
106 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
107 LocInfo HTP, unsigned ExtraInfo = 0) {
108 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, false);
109 Ret.Data = ExtraInfo;
110 return Ret;
111 }
112
113 void convertToReg(unsigned RegNo) { Data = Register(RegNo); }
114
115 void convertToMem(unsigned Offset) { Data = int64_t(Offset); }
116
117 unsigned getValNo() const { return ValNo; }
118 MVT getValVT() const { return ValVT; }
119
120 bool isRegLoc() const { return std::holds_alternative<Register>(Data); }
121 bool isMemLoc() const { return std::holds_alternative<int64_t>(Data); }
122 bool isPendingLoc() const { return std::holds_alternative<unsigned>(Data); }
123
124 bool needsCustom() const { return isCustom; }
125
126 Register getLocReg() const { return std::get<Register>(Data); }
127 unsigned getLocMemOffset() const { return std::get<int64_t>(Data); }
128 unsigned getExtraInfo() const { return std::get<unsigned>(Data); }
129
130 MVT getLocVT() const { return LocVT; }
131
132 LocInfo getLocInfo() const { return HTP; }
133 bool isExtInLoc() const {
134 return (HTP == AExt || HTP == SExt || HTP == ZExt);
135 }
136
137 bool isUpperBitsInLoc() const {
138 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
139 }
140};
141
142/// Describes a register that needs to be forwarded from the prologue to a
143/// musttail call.
144struct ForwardedRegister {
145 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT)
146 : VReg(VReg), PReg(PReg), VT(VT) {}
147 Register VReg;
148 MCPhysReg PReg;
149 MVT VT;
150};
151
152/// CCAssignFn - This function assigns a location for Val, updating State to
153/// reflect the change. It returns 'true' if it failed to handle Val.
154typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
155 MVT LocVT, CCValAssign::LocInfo LocInfo,
156 ISD::ArgFlagsTy ArgFlags, CCState &State);
157
158/// CCCustomFn - This function assigns a location for Val, possibly updating
159/// all args to reflect changes and indicates if it handled it. It must set
160/// isCustom if it handles the arg and returns true.
161typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
162 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
163 ISD::ArgFlagsTy &ArgFlags, CCState &State);
164
165/// CCState - This class holds information needed while lowering arguments and
166/// return values. It captures which registers are already assigned and which
167/// stack slots are used. It provides accessors to allocate these values.
168class CCState {
169private:
170 CallingConv::ID CallingConv;
171 bool IsVarArg;
172 bool AnalyzingMustTailForwardedRegs = false;
173 MachineFunction &MF;
174 const TargetRegisterInfo &TRI;
175 SmallVectorImpl<CCValAssign> &Locs;
176 LLVMContext &Context;
177
178 unsigned StackOffset;
179 Align MaxStackArgAlign;
180 SmallVector<uint32_t, 16> UsedRegs;
181 SmallVector<CCValAssign, 4> PendingLocs;
182 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
183
184 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
185 //
186 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
187 // tracking.
188 // Or, in another words it tracks byval parameters that are stored in
189 // general purpose registers.
190 //
191 // For 4 byte stack alignment,
192 // instance index means byval parameter number in formal
193 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
194 // then, for function "foo":
195 //
196 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
197 //
198 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
199 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
200 //
201 // In case of 8 bytes stack alignment,
202 // In function shown above, r3 would be wasted according to AAPCS rules.
203 // ByValRegs vector size still would be 2,
204 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
205 //
206 // Supposed use-case for this collection:
207 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
208 // 2. HandleByVal fills up ByValRegs.
209 // 3. Argument analysis (LowerFormatArguments, for example). After
210 // some byval argument was analyzed, InRegsParamsProcessed is increased.
211 struct ByValInfo {
212 ByValInfo(unsigned B, unsigned E) : Begin(B), End(E) {}
213
214 // First register allocated for current parameter.
215 unsigned Begin;
216
217 // First after last register allocated for current parameter.
218 unsigned End;
219 };
220 SmallVector<ByValInfo, 4 > ByValRegs;
221
222 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
223 // during argument analysis.
224 unsigned InRegsParamsProcessed;
225
226public:
227 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
228 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
229
230 void addLoc(const CCValAssign &V) {
231 Locs.push_back(V);
232 }
233
234 LLVMContext &getContext() const { return Context; }
235 MachineFunction &getMachineFunction() const { return MF; }
236 CallingConv::ID getCallingConv() const { return CallingConv; }
237 bool isVarArg() const { return IsVarArg; }
238
239 /// getNextStackOffset - Return the next stack offset such that all stack
240 /// slots satisfy their alignment requirements.
241 unsigned getNextStackOffset() const {
242 return StackOffset;
243 }
244
245 /// getAlignedCallFrameSize - Return the size of the call frame needed to
246 /// be able to store all arguments and such that the alignment requirement
247 /// of each of the arguments is satisfied.
248 unsigned getAlignedCallFrameSize() const {
249 return alignTo(StackOffset, MaxStackArgAlign);
250 }
251
252 /// isAllocated - Return true if the specified register (or an alias) is
253 /// allocated.
254 bool isAllocated(MCRegister Reg) const {
255 return UsedRegs[Reg / 32] & (1 << (Reg & 31));
256 }
257
258 /// AnalyzeFormalArguments - Analyze an array of argument values,
259 /// incorporating info about the formals into this state.
260 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
261 CCAssignFn Fn);
262
263 /// The function will invoke AnalyzeFormalArguments.
264 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
265 CCAssignFn Fn) {
266 AnalyzeFormalArguments(Ins, Fn);
267 }
268
269 /// AnalyzeReturn - Analyze the returned values of a return,
270 /// incorporating info about the result values into this state.
271 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
272 CCAssignFn Fn);
273
274 /// CheckReturn - Analyze the return values of a function, returning
275 /// true if the return can be performed without sret-demotion, and
276 /// false otherwise.
277 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
278 CCAssignFn Fn);
279
280 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
281 /// incorporating info about the passed values into this state.
282 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
283 CCAssignFn Fn);
284
285 /// AnalyzeCallOperands - Same as above except it takes vectors of types
286 /// and argument flags.
287 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
288 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
289 CCAssignFn Fn);
290
291 /// The function will invoke AnalyzeCallOperands.
292 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
293 CCAssignFn Fn) {
294 AnalyzeCallOperands(Outs, Fn);
295 }
296
297 /// AnalyzeCallResult - Analyze the return values of a call,
298 /// incorporating info about the passed values into this state.
299 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
300 CCAssignFn Fn);
301
302 /// A shadow allocated register is a register that was allocated
303 /// but wasn't added to the location list (Locs).
304 /// \returns true if the register was allocated as shadow or false otherwise.
305 bool IsShadowAllocatedReg(MCRegister Reg) const;
306
307 /// AnalyzeCallResult - Same as above except it's specialized for calls which
308 /// produce a single value.
309 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
310
311 /// getFirstUnallocated - Return the index of the first unallocated register
312 /// in the set, or Regs.size() if they are all allocated.
313 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
314 for (unsigned i = 0; i < Regs.size(); ++i)
3
←
Assuming the condition is true
→
4
←
Loop condition is true. Entering loop body
→
7
←
The value 1 is assigned to 'i'
→
8
←
Assuming the condition is true
→
9
←
Loop condition is true. Entering loop body
→
315 if (!isAllocated(Regs[i]))
5
←
Assuming the condition is false
→
6
←
Taking false branch
→
10
←
Assuming the condition is true
→
11
←
Taking true branch
→
316 return i;
12
←
Returning the value 1 (loaded from 'i')
→
317 return Regs.size();
318 }
319
320 void DeallocateReg(MCPhysReg Reg) {
321 assert(isAllocated(Reg) && "Trying to deallocate an unallocated register")(static_cast <bool> (isAllocated(Reg) && "Trying to deallocate an unallocated register"
) ? void (0) : __assert_fail ("isAllocated(Reg) && \"Trying to deallocate an unallocated register\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 321, __extension__
__PRETTY_FUNCTION__));
322 MarkUnallocated(Reg);
323 }
324
325 /// AllocateReg - Attempt to allocate one register. If it is not available,
326 /// return zero. Otherwise, return the register, marking it and any aliases
327 /// as allocated.
328 MCRegister AllocateReg(MCPhysReg Reg) {
329 if (isAllocated(Reg))
330 return MCRegister();
331 MarkAllocated(Reg);
332 return Reg;
333 }
334
335 /// Version of AllocateReg with extra register to be shadowed.
336 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) {
337 if (isAllocated(Reg))
338 return MCRegister();
339 MarkAllocated(Reg);
340 MarkAllocated(ShadowReg);
341 return Reg;
342 }
343
344 /// AllocateReg - Attempt to allocate one of the specified registers. If none
345 /// are available, return zero. Otherwise, return the first one available,
346 /// marking it and any aliases as allocated.
347 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
348 unsigned FirstUnalloc = getFirstUnallocated(Regs);
349 if (FirstUnalloc == Regs.size())
350 return MCRegister(); // Didn't find the reg.
351
352 // Mark the register and any aliases as allocated.
353 MCPhysReg Reg = Regs[FirstUnalloc];
354 MarkAllocated(Reg);
355 return Reg;
356 }
357
358 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
359 /// registers. If this is not possible, return zero. Otherwise, return the first
360 /// register of the block that were allocated, marking the entire block as allocated.
361 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
362 if (RegsRequired > Regs.size())
363 return 0;
364
365 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
366 ++StartIdx) {
367 bool BlockAvailable = true;
368 // Check for already-allocated regs in this block
369 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
370 if (isAllocated(Regs[StartIdx + BlockIdx])) {
371 BlockAvailable = false;
372 break;
373 }
374 }
375 if (BlockAvailable) {
376 // Mark the entire block as allocated
377 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
378 MarkAllocated(Regs[StartIdx + BlockIdx]);
379 }
380 return Regs[StartIdx];
381 }
382 }
383 // No block was available
384 return 0;
385 }
386
387 /// Version of AllocateReg with list of registers to be shadowed.
388 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
389 unsigned FirstUnalloc = getFirstUnallocated(Regs);
2
←
Calling 'CCState::getFirstUnallocated'
→
13
←
Returning from 'CCState::getFirstUnallocated'
→
14
←
'FirstUnalloc' initialized to 1
→
390 if (FirstUnalloc == Regs.size())
15
←
Assuming the condition is false
→
16
←
Taking false branch
→
391 return MCRegister(); // Didn't find the reg.
392
393 // Mark the register and any aliases as allocated.
394 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
17
←
1st function call argument is an uninitialized value
395 MarkAllocated(Reg);
396 MarkAllocated(ShadowReg);
397 return Reg;
398 }
399
400 /// AllocateStack - Allocate a chunk of stack space with the specified size
401 /// and alignment.
402 unsigned AllocateStack(unsigned Size, Align Alignment) {
403 StackOffset = alignTo(StackOffset, Alignment);
404 unsigned Result = StackOffset;
405 StackOffset += Size;
406 MaxStackArgAlign = std::max(Alignment, MaxStackArgAlign);
407 ensureMaxAlignment(Alignment);
408 return Result;
409 }
410
411 void ensureMaxAlignment(Align Alignment);
412
413 /// Version of AllocateStack with list of extra registers to be shadowed.
414 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
415 unsigned AllocateStack(unsigned Size, Align Alignment,
416 ArrayRef<MCPhysReg> ShadowRegs) {
417 for (MCPhysReg Reg : ShadowRegs)
418 MarkAllocated(Reg);
419 return AllocateStack(Size, Alignment);
420 }
421
422 // HandleByVal - Allocate a stack slot large enough to pass an argument by
423 // value. The size and alignment information of the argument is encoded in its
424 // parameter attribute.
425 void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
426 CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign,
427 ISD::ArgFlagsTy ArgFlags);
428
429 // Returns count of byval arguments that are to be stored (even partly)
430 // in registers.
431 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
432
433 // Returns count of byval in-regs arguments processed.
434 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
435
436 // Get information about N-th byval parameter that is stored in registers.
437 // Here "ByValParamIndex" is N.
438 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
439 unsigned& BeginReg, unsigned& EndReg) const {
440 assert(InRegsParamRecordIndex < ByValRegs.size() &&(static_cast <bool> (InRegsParamRecordIndex < ByValRegs
.size() && "Wrong ByVal parameter index") ? void (0) :
__assert_fail ("InRegsParamRecordIndex < ByValRegs.size() && \"Wrong ByVal parameter index\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 441, __extension__
__PRETTY_FUNCTION__))
441 "Wrong ByVal parameter index")(static_cast <bool> (InRegsParamRecordIndex < ByValRegs
.size() && "Wrong ByVal parameter index") ? void (0) :
__assert_fail ("InRegsParamRecordIndex < ByValRegs.size() && \"Wrong ByVal parameter index\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 441, __extension__
__PRETTY_FUNCTION__));
442
443 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
444 BeginReg = info.Begin;
445 EndReg = info.End;
446 }
447
448 // Add information about parameter that is kept in registers.
449 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
450 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
451 }
452
453 // Goes either to next byval parameter (excluding "waste" record), or
454 // to the end of collection.
455 // Returns false, if end is reached.
456 bool nextInRegsParam() {
457 unsigned e = ByValRegs.size();
458 if (InRegsParamsProcessed < e)
459 ++InRegsParamsProcessed;
460 return InRegsParamsProcessed < e;
461 }
462
463 // Clear byval registers tracking info.
464 void clearByValRegsInfo() {
465 InRegsParamsProcessed = 0;
466 ByValRegs.clear();
467 }
468
469 // Rewind byval registers tracking info.
470 void rewindByValRegsInfo() {
471 InRegsParamsProcessed = 0;
472 }
473
474 // Get list of pending assignments
475 SmallVectorImpl<CCValAssign> &getPendingLocs() {
476 return PendingLocs;
477 }
478
479 // Get a list of argflags for pending assignments.
480 SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
481 return PendingArgFlags;
482 }
483
484 /// Compute the remaining unused register parameters that would be used for
485 /// the given value type. This is useful when varargs are passed in the
486 /// registers that normal prototyped parameters would be passed in, or for
487 /// implementing perfect forwarding.
488 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
489 CCAssignFn Fn);
490
491 /// Compute the set of registers that need to be preserved and forwarded to
492 /// any musttail calls.
493 void analyzeMustTailForwardedRegisters(
494 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
495 CCAssignFn Fn);
496
497 /// Returns true if the results of the two calling conventions are compatible.
498 /// This is usually part of the check for tailcall eligibility.
499 static bool resultsCompatible(CallingConv::ID CalleeCC,
500 CallingConv::ID CallerCC, MachineFunction &MF,
501 LLVMContext &C,
502 const SmallVectorImpl<ISD::InputArg> &Ins,
503 CCAssignFn CalleeFn, CCAssignFn CallerFn);
504
505 /// The function runs an additional analysis pass over function arguments.
506 /// It will mark each argument with the attribute flag SecArgPass.
507 /// After running, it will sort the locs list.
508 template <class T>
509 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
510 CCAssignFn Fn) {
511 unsigned NumFirstPassLocs = Locs.size();
512
513 /// Creates similar argument list to \p Args in which each argument is
514 /// marked using SecArgPass flag.
515 SmallVector<T, 16> SecPassArg;
516 // SmallVector<ISD::InputArg, 16> SecPassArg;
517 for (auto Arg : Args) {
518 Arg.Flags.setSecArgPass();
519 SecPassArg.push_back(Arg);
520 }
521
522 // Run the second argument pass
523 AnalyzeArguments(SecPassArg, Fn);
524
525 // Sort the locations of the arguments according to their original position.
526 SmallVector<CCValAssign, 16> TmpArgLocs;
527 TmpArgLocs.swap(Locs);
528 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
529 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
530 std::back_inserter(Locs),
531 [](const CCValAssign &A, const CCValAssign &B) -> bool {
532 return A.getValNo() < B.getValNo();
533 });
534 }
535
536private:
537 /// MarkAllocated - Mark a register and all of its aliases as allocated.
538 void MarkAllocated(MCPhysReg Reg);
539
540 void MarkUnallocated(MCPhysReg Reg);
541};
542
543} // end namespace llvm
544
545#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H