Bug Summary

File:build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include/llvm/CodeGen/CallingConvLower.h
Warning:line 415, column 54
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PPCCallingConv.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC -I include -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-09-04-125545-48738-1 -x c++ /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC/PPCCallingConv.cpp

/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC/PPCCallingConv.cpp

1//===-- PPCCallingConv.h - --------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "PPCRegisterInfo.h"
10#include "PPCCallingConv.h"
11#include "PPCSubtarget.h"
12#include "PPCCCState.h"
13using namespace llvm;
14
15inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
16 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
17 CCState &) {
18 llvm_unreachable("The AnyReg calling convention is only supported by the " \::llvm::llvm_unreachable_internal("The AnyReg calling convention is only supported by the "
"stackmap and patchpoint intrinsics.", "llvm/lib/Target/PowerPC/PPCCallingConv.cpp"
, 19)
19 "stackmap and patchpoint intrinsics.")::llvm::llvm_unreachable_internal("The AnyReg calling convention is only supported by the "
"stackmap and patchpoint intrinsics.", "llvm/lib/Target/PowerPC/PPCCallingConv.cpp"
, 19)
;
20 // gracefully fallback to PPC C calling convention on Release builds.
21 return false;
22}
23
24static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
25 CCValAssign::LocInfo &LocInfo,
26 ISD::ArgFlagsTy &ArgFlags,
27 CCState &State) {
28 return true;
29}
30
31static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
32 MVT &LocVT,
33 CCValAssign::LocInfo &LocInfo,
34 ISD::ArgFlagsTy &ArgFlags,
35 CCState &State) {
36 static const MCPhysReg ArgRegs[] = {
37 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
38 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
39 };
40 const unsigned NumArgRegs = array_lengthof(ArgRegs);
41
42 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
43
44 // Skip one register if the first unallocated register has an even register
45 // number and there are still argument registers available which have not been
46 // allocated yet. RegNum is actually an index into ArgRegs, which means we
47 // need to skip a register if RegNum is odd.
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
49 State.AllocateReg(ArgRegs[RegNum]);
50 }
51
52 // Always return false here, as this function only makes sure that the first
53 // unallocated register has an odd register number and does not actually
54 // allocate a register for the current argument.
55 return false;
56}
57
58static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(
59 unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
60 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
61 static const MCPhysReg ArgRegs[] = {
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
64 };
65 const unsigned NumArgRegs = array_lengthof(ArgRegs);
66
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
68 int RegsLeft = NumArgRegs - RegNum;
69
70 // Skip if there is not enough registers left for long double type (4 gpr regs
71 // in soft float mode) and put long double argument on the stack.
72 if (RegNum != NumArgRegs && RegsLeft < 4) {
73 for (int i = 0; i < RegsLeft; i++) {
74 State.AllocateReg(ArgRegs[RegNum + i]);
75 }
76 }
77
78 return false;
79}
80
81static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT,
83 CCValAssign::LocInfo &LocInfo,
84 ISD::ArgFlagsTy &ArgFlags,
85 CCState &State) {
86 static const MCPhysReg ArgRegs[] = {
87 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
88 PPC::F8
89 };
90
91 const unsigned NumArgRegs = array_lengthof(ArgRegs);
92
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
94
95 // If there is only one Floating-point register left we need to put both f64
96 // values of a split ppc_fp128 value on the stack.
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
98 State.AllocateReg(ArgRegs[RegNum]);
99 }
100
101 // Always return false here, as this function only makes sure that the two f64
102 // values a ppc_fp128 value is split into are both passed in registers or both
103 // passed on the stack and does not actually allocate a register for the
104 // current argument.
105 return false;
106}
107
108// Split F64 arguments into two 32-bit consecutive registers.
109static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
110 MVT &LocVT,
111 CCValAssign::LocInfo &LocInfo,
112 ISD::ArgFlagsTy &ArgFlags,
113 CCState &State) {
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
116
117 // Try to get the first register.
118 unsigned Reg = State.AllocateReg(HiRegList);
119 if (!Reg)
120 return false;
121
122 unsigned i;
123 for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
124 if (HiRegList[i] == Reg)
125 break;
126
127 unsigned T = State.AllocateReg(LoRegList[i]);
128 (void)T;
129 assert(T == LoRegList[i] && "Could not allocate register")(static_cast <bool> (T == LoRegList[i] && "Could not allocate register"
) ? void (0) : __assert_fail ("T == LoRegList[i] && \"Could not allocate register\""
, "llvm/lib/Target/PowerPC/PPCCallingConv.cpp", 129, __extension__
__PRETTY_FUNCTION__))
;
130
131 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
132 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
133 LocVT, LocInfo));
134 return true;
135}
136
137// Same as above, but for return values, so only allocate for R3 and R4
138static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
139 MVT &LocVT,
140 CCValAssign::LocInfo &LocInfo,
141 ISD::ArgFlagsTy &ArgFlags,
142 CCState &State) {
143 static const MCPhysReg HiRegList[] = { PPC::R3 };
144 static const MCPhysReg LoRegList[] = { PPC::R4 };
145
146 // Try to get the first register.
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
1
Calling 'CCState::AllocateReg'
148 if (!Reg)
149 return false;
150
151 unsigned i;
152 for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
153 if (HiRegList[i] == Reg)
154 break;
155
156 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
157 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
158 LocVT, LocInfo));
159 return true;
160}
161
162#include "PPCGenCallingConv.inc"

/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include/llvm/CodeGen/CallingConvLower.h

1//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the CCState and CCValAssign classes, used for lowering
10// and implementing calling conventions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
15#define LLVM_CODEGEN_CALLINGCONVLOWER_H
16
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/Register.h"
19#include "llvm/CodeGen/TargetCallingConv.h"
20#include "llvm/IR/CallingConv.h"
21#include "llvm/Support/Alignment.h"
22
23namespace llvm {
24
25class CCState;
26class MachineFunction;
27class MVT;
28class TargetRegisterInfo;
29
30/// CCValAssign - Represent assignment of one arg/retval to a location.
31class CCValAssign {
32public:
33 enum LocInfo {
34 Full, // The value fills the full location.
35 SExt, // The value is sign extended in the location.
36 ZExt, // The value is zero extended in the location.
37 AExt, // The value is extended with undefined upper bits.
38 SExtUpper, // The value is in the upper bits of the location and should be
39 // sign extended when retrieved.
40 ZExtUpper, // The value is in the upper bits of the location and should be
41 // zero extended when retrieved.
42 AExtUpper, // The value is in the upper bits of the location and should be
43 // extended with undefined upper bits when retrieved.
44 BCvt, // The value is bit-converted in the location.
45 Trunc, // The value is truncated in the location.
46 VExt, // The value is vector-widened in the location.
47 // FIXME: Not implemented yet. Code that uses AExt to mean
48 // vector-widen should be fixed to use VExt instead.
49 FPExt, // The floating-point value is fp-extended in the location.
50 Indirect // The location contains pointer to the value.
51 // TODO: a subset of the value is in the location.
52 };
53
54private:
55 /// ValNo - This is the value number being assigned (e.g. an argument number).
56 unsigned ValNo;
57
58 /// Loc is either a stack offset or a register number.
59 unsigned Loc;
60
61 /// isMem - True if this is a memory loc, false if it is a register loc.
62 unsigned isMem : 1;
63
64 /// isCustom - True if this arg/retval requires special handling.
65 unsigned isCustom : 1;
66
67 /// Information about how the value is assigned.
68 LocInfo HTP : 6;
69
70 /// ValVT - The type of the value being assigned.
71 MVT ValVT;
72
73 /// LocVT - The type of the location being assigned to.
74 MVT LocVT;
75public:
76
77 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
78 unsigned RegNo, MVT LocVT,
79 LocInfo HTP) {
80 CCValAssign Ret;
81 Ret.ValNo = ValNo;
82 Ret.Loc = RegNo;
83 Ret.isMem = false;
84 Ret.isCustom = false;
85 Ret.HTP = HTP;
86 Ret.ValVT = ValVT;
87 Ret.LocVT = LocVT;
88 return Ret;
89 }
90
91 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
92 unsigned RegNo, MVT LocVT,
93 LocInfo HTP) {
94 CCValAssign Ret;
95 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
96 Ret.isCustom = true;
97 return Ret;
98 }
99
100 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
101 unsigned Offset, MVT LocVT,
102 LocInfo HTP) {
103 CCValAssign Ret;
104 Ret.ValNo = ValNo;
105 Ret.Loc = Offset;
106 Ret.isMem = true;
107 Ret.isCustom = false;
108 Ret.HTP = HTP;
109 Ret.ValVT = ValVT;
110 Ret.LocVT = LocVT;
111 return Ret;
112 }
113
114 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
115 unsigned Offset, MVT LocVT,
116 LocInfo HTP) {
117 CCValAssign Ret;
118 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
119 Ret.isCustom = true;
120 return Ret;
121 }
122
123 // There is no need to differentiate between a pending CCValAssign and other
124 // kinds, as they are stored in a different list.
125 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
126 LocInfo HTP, unsigned ExtraInfo = 0) {
127 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
128 }
129
130 void convertToReg(unsigned RegNo) {
131 Loc = RegNo;
132 isMem = false;
133 }
134
135 void convertToMem(unsigned Offset) {
136 Loc = Offset;
137 isMem = true;
138 }
139
140 unsigned getValNo() const { return ValNo; }
141 MVT getValVT() const { return ValVT; }
142
143 bool isRegLoc() const { return !isMem; }
144 bool isMemLoc() const { return isMem; }
145
146 bool needsCustom() const { return isCustom; }
147
148 Register getLocReg() const { assert(isRegLoc())(static_cast <bool> (isRegLoc()) ? void (0) : __assert_fail
("isRegLoc()", "llvm/include/llvm/CodeGen/CallingConvLower.h"
, 148, __extension__ __PRETTY_FUNCTION__))
; return Loc; }
149 unsigned getLocMemOffset() const { assert(isMemLoc())(static_cast <bool> (isMemLoc()) ? void (0) : __assert_fail
("isMemLoc()", "llvm/include/llvm/CodeGen/CallingConvLower.h"
, 149, __extension__ __PRETTY_FUNCTION__))
; return Loc; }
150 unsigned getExtraInfo() const { return Loc; }
151 MVT getLocVT() const { return LocVT; }
152
153 LocInfo getLocInfo() const { return HTP; }
154 bool isExtInLoc() const {
155 return (HTP == AExt || HTP == SExt || HTP == ZExt);
156 }
157
158 bool isUpperBitsInLoc() const {
159 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
160 }
161};
162
163/// Describes a register that needs to be forwarded from the prologue to a
164/// musttail call.
165struct ForwardedRegister {
166 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT)
167 : VReg(VReg), PReg(PReg), VT(VT) {}
168 Register VReg;
169 MCPhysReg PReg;
170 MVT VT;
171};
172
173/// CCAssignFn - This function assigns a location for Val, updating State to
174/// reflect the change. It returns 'true' if it failed to handle Val.
175typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State);
178
179/// CCCustomFn - This function assigns a location for Val, possibly updating
180/// all args to reflect changes and indicates if it handled it. It must set
181/// isCustom if it handles the arg and returns true.
182typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
183 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
184 ISD::ArgFlagsTy &ArgFlags, CCState &State);
185
186/// CCState - This class holds information needed while lowering arguments and
187/// return values. It captures which registers are already assigned and which
188/// stack slots are used. It provides accessors to allocate these values.
189class CCState {
190private:
191 CallingConv::ID CallingConv;
192 bool IsVarArg;
193 bool AnalyzingMustTailForwardedRegs = false;
194 MachineFunction &MF;
195 const TargetRegisterInfo &TRI;
196 SmallVectorImpl<CCValAssign> &Locs;
197 LLVMContext &Context;
198
199 unsigned StackOffset;
200 Align MaxStackArgAlign;
201 SmallVector<uint32_t, 16> UsedRegs;
202 SmallVector<CCValAssign, 4> PendingLocs;
203 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
204
205 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
206 //
207 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
208 // tracking.
209 // Or, in another words it tracks byval parameters that are stored in
210 // general purpose registers.
211 //
212 // For 4 byte stack alignment,
213 // instance index means byval parameter number in formal
214 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
215 // then, for function "foo":
216 //
217 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
218 //
219 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
220 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
221 //
222 // In case of 8 bytes stack alignment,
223 // In function shown above, r3 would be wasted according to AAPCS rules.
224 // ByValRegs vector size still would be 2,
225 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
226 //
227 // Supposed use-case for this collection:
228 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
229 // 2. HandleByVal fills up ByValRegs.
230 // 3. Argument analysis (LowerFormatArguments, for example). After
231 // some byval argument was analyzed, InRegsParamsProcessed is increased.
232 struct ByValInfo {
233 ByValInfo(unsigned B, unsigned E) : Begin(B), End(E) {}
234
235 // First register allocated for current parameter.
236 unsigned Begin;
237
238 // First after last register allocated for current parameter.
239 unsigned End;
240 };
241 SmallVector<ByValInfo, 4 > ByValRegs;
242
243 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
244 // during argument analysis.
245 unsigned InRegsParamsProcessed;
246
247public:
248 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
249 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
250
251 void addLoc(const CCValAssign &V) {
252 Locs.push_back(V);
253 }
254
255 LLVMContext &getContext() const { return Context; }
256 MachineFunction &getMachineFunction() const { return MF; }
257 CallingConv::ID getCallingConv() const { return CallingConv; }
258 bool isVarArg() const { return IsVarArg; }
259
260 /// getNextStackOffset - Return the next stack offset such that all stack
261 /// slots satisfy their alignment requirements.
262 unsigned getNextStackOffset() const {
263 return StackOffset;
264 }
265
266 /// getAlignedCallFrameSize - Return the size of the call frame needed to
267 /// be able to store all arguments and such that the alignment requirement
268 /// of each of the arguments is satisfied.
269 unsigned getAlignedCallFrameSize() const {
270 return alignTo(StackOffset, MaxStackArgAlign);
271 }
272
273 /// isAllocated - Return true if the specified register (or an alias) is
274 /// allocated.
275 bool isAllocated(MCRegister Reg) const {
276 return UsedRegs[Reg / 32] & (1 << (Reg & 31));
277 }
278
279 /// AnalyzeFormalArguments - Analyze an array of argument values,
280 /// incorporating info about the formals into this state.
281 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
282 CCAssignFn Fn);
283
284 /// The function will invoke AnalyzeFormalArguments.
285 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
286 CCAssignFn Fn) {
287 AnalyzeFormalArguments(Ins, Fn);
288 }
289
290 /// AnalyzeReturn - Analyze the returned values of a return,
291 /// incorporating info about the result values into this state.
292 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
293 CCAssignFn Fn);
294
295 /// CheckReturn - Analyze the return values of a function, returning
296 /// true if the return can be performed without sret-demotion, and
297 /// false otherwise.
298 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
299 CCAssignFn Fn);
300
301 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
302 /// incorporating info about the passed values into this state.
303 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
304 CCAssignFn Fn);
305
306 /// AnalyzeCallOperands - Same as above except it takes vectors of types
307 /// and argument flags.
308 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
309 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
310 CCAssignFn Fn);
311
312 /// The function will invoke AnalyzeCallOperands.
313 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
314 CCAssignFn Fn) {
315 AnalyzeCallOperands(Outs, Fn);
316 }
317
318 /// AnalyzeCallResult - Analyze the return values of a call,
319 /// incorporating info about the passed values into this state.
320 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
321 CCAssignFn Fn);
322
323 /// A shadow allocated register is a register that was allocated
324 /// but wasn't added to the location list (Locs).
325 /// \returns true if the register was allocated as shadow or false otherwise.
326 bool IsShadowAllocatedReg(MCRegister Reg) const;
327
328 /// AnalyzeCallResult - Same as above except it's specialized for calls which
329 /// produce a single value.
330 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
331
332 /// getFirstUnallocated - Return the index of the first unallocated register
333 /// in the set, or Regs.size() if they are all allocated.
334 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
335 for (unsigned i = 0; i < Regs.size(); ++i)
3
Assuming the condition is true
4
Loop condition is true. Entering loop body
7
The value 1 is assigned to 'i'
8
Assuming the condition is true
9
Loop condition is true. Entering loop body
336 if (!isAllocated(Regs[i]))
5
Assuming the condition is false
6
Taking false branch
10
Assuming the condition is true
11
Taking true branch
337 return i;
12
Returning the value 1 (loaded from 'i')
338 return Regs.size();
339 }
340
341 void DeallocateReg(MCPhysReg Reg) {
342 assert(isAllocated(Reg) && "Trying to deallocate an unallocated register")(static_cast <bool> (isAllocated(Reg) && "Trying to deallocate an unallocated register"
) ? void (0) : __assert_fail ("isAllocated(Reg) && \"Trying to deallocate an unallocated register\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 342, __extension__
__PRETTY_FUNCTION__))
;
343 MarkUnallocated(Reg);
344 }
345
346 /// AllocateReg - Attempt to allocate one register. If it is not available,
347 /// return zero. Otherwise, return the register, marking it and any aliases
348 /// as allocated.
349 MCRegister AllocateReg(MCPhysReg Reg) {
350 if (isAllocated(Reg))
351 return MCRegister();
352 MarkAllocated(Reg);
353 return Reg;
354 }
355
356 /// Version of AllocateReg with extra register to be shadowed.
357 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) {
358 if (isAllocated(Reg))
359 return MCRegister();
360 MarkAllocated(Reg);
361 MarkAllocated(ShadowReg);
362 return Reg;
363 }
364
365 /// AllocateReg - Attempt to allocate one of the specified registers. If none
366 /// are available, return zero. Otherwise, return the first one available,
367 /// marking it and any aliases as allocated.
368 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
369 unsigned FirstUnalloc = getFirstUnallocated(Regs);
370 if (FirstUnalloc == Regs.size())
371 return MCRegister(); // Didn't find the reg.
372
373 // Mark the register and any aliases as allocated.
374 MCPhysReg Reg = Regs[FirstUnalloc];
375 MarkAllocated(Reg);
376 return Reg;
377 }
378
379 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
380 /// registers. If this is not possible, return zero. Otherwise, return the first
381 /// register of the block that were allocated, marking the entire block as allocated.
382 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
383 if (RegsRequired > Regs.size())
384 return 0;
385
386 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
387 ++StartIdx) {
388 bool BlockAvailable = true;
389 // Check for already-allocated regs in this block
390 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
391 if (isAllocated(Regs[StartIdx + BlockIdx])) {
392 BlockAvailable = false;
393 break;
394 }
395 }
396 if (BlockAvailable) {
397 // Mark the entire block as allocated
398 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
399 MarkAllocated(Regs[StartIdx + BlockIdx]);
400 }
401 return Regs[StartIdx];
402 }
403 }
404 // No block was available
405 return 0;
406 }
407
408 /// Version of AllocateReg with list of registers to be shadowed.
409 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
410 unsigned FirstUnalloc = getFirstUnallocated(Regs);
2
Calling 'CCState::getFirstUnallocated'
13
Returning from 'CCState::getFirstUnallocated'
14
'FirstUnalloc' initialized to 1
411 if (FirstUnalloc == Regs.size())
15
Assuming the condition is false
16
Taking false branch
412 return MCRegister(); // Didn't find the reg.
413
414 // Mark the register and any aliases as allocated.
415 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
17
1st function call argument is an uninitialized value
416 MarkAllocated(Reg);
417 MarkAllocated(ShadowReg);
418 return Reg;
419 }
420
421 /// AllocateStack - Allocate a chunk of stack space with the specified size
422 /// and alignment.
423 unsigned AllocateStack(unsigned Size, Align Alignment) {
424 StackOffset = alignTo(StackOffset, Alignment);
425 unsigned Result = StackOffset;
426 StackOffset += Size;
427 MaxStackArgAlign = std::max(Alignment, MaxStackArgAlign);
428 ensureMaxAlignment(Alignment);
429 return Result;
430 }
431
432 void ensureMaxAlignment(Align Alignment);
433
434 /// Version of AllocateStack with list of extra registers to be shadowed.
435 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
436 unsigned AllocateStack(unsigned Size, Align Alignment,
437 ArrayRef<MCPhysReg> ShadowRegs) {
438 for (MCPhysReg Reg : ShadowRegs)
439 MarkAllocated(Reg);
440 return AllocateStack(Size, Alignment);
441 }
442
443 // HandleByVal - Allocate a stack slot large enough to pass an argument by
444 // value. The size and alignment information of the argument is encoded in its
445 // parameter attribute.
446 void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
447 CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign,
448 ISD::ArgFlagsTy ArgFlags);
449
450 // Returns count of byval arguments that are to be stored (even partly)
451 // in registers.
452 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
453
454 // Returns count of byval in-regs arguments processed.
455 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
456
457 // Get information about N-th byval parameter that is stored in registers.
458 // Here "ByValParamIndex" is N.
459 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
460 unsigned& BeginReg, unsigned& EndReg) const {
461 assert(InRegsParamRecordIndex < ByValRegs.size() &&(static_cast <bool> (InRegsParamRecordIndex < ByValRegs
.size() && "Wrong ByVal parameter index") ? void (0) :
__assert_fail ("InRegsParamRecordIndex < ByValRegs.size() && \"Wrong ByVal parameter index\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 462, __extension__
__PRETTY_FUNCTION__))
462 "Wrong ByVal parameter index")(static_cast <bool> (InRegsParamRecordIndex < ByValRegs
.size() && "Wrong ByVal parameter index") ? void (0) :
__assert_fail ("InRegsParamRecordIndex < ByValRegs.size() && \"Wrong ByVal parameter index\""
, "llvm/include/llvm/CodeGen/CallingConvLower.h", 462, __extension__
__PRETTY_FUNCTION__))
;
463
464 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
465 BeginReg = info.Begin;
466 EndReg = info.End;
467 }
468
469 // Add information about parameter that is kept in registers.
470 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
471 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
472 }
473
474 // Goes either to next byval parameter (excluding "waste" record), or
475 // to the end of collection.
476 // Returns false, if end is reached.
477 bool nextInRegsParam() {
478 unsigned e = ByValRegs.size();
479 if (InRegsParamsProcessed < e)
480 ++InRegsParamsProcessed;
481 return InRegsParamsProcessed < e;
482 }
483
484 // Clear byval registers tracking info.
485 void clearByValRegsInfo() {
486 InRegsParamsProcessed = 0;
487 ByValRegs.clear();
488 }
489
490 // Rewind byval registers tracking info.
491 void rewindByValRegsInfo() {
492 InRegsParamsProcessed = 0;
493 }
494
495 // Get list of pending assignments
496 SmallVectorImpl<CCValAssign> &getPendingLocs() {
497 return PendingLocs;
498 }
499
500 // Get a list of argflags for pending assignments.
501 SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
502 return PendingArgFlags;
503 }
504
505 /// Compute the remaining unused register parameters that would be used for
506 /// the given value type. This is useful when varargs are passed in the
507 /// registers that normal prototyped parameters would be passed in, or for
508 /// implementing perfect forwarding.
509 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
510 CCAssignFn Fn);
511
512 /// Compute the set of registers that need to be preserved and forwarded to
513 /// any musttail calls.
514 void analyzeMustTailForwardedRegisters(
515 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
516 CCAssignFn Fn);
517
518 /// Returns true if the results of the two calling conventions are compatible.
519 /// This is usually part of the check for tailcall eligibility.
520 static bool resultsCompatible(CallingConv::ID CalleeCC,
521 CallingConv::ID CallerCC, MachineFunction &MF,
522 LLVMContext &C,
523 const SmallVectorImpl<ISD::InputArg> &Ins,
524 CCAssignFn CalleeFn, CCAssignFn CallerFn);
525
526 /// The function runs an additional analysis pass over function arguments.
527 /// It will mark each argument with the attribute flag SecArgPass.
528 /// After running, it will sort the locs list.
529 template <class T>
530 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
531 CCAssignFn Fn) {
532 unsigned NumFirstPassLocs = Locs.size();
533
534 /// Creates similar argument list to \p Args in which each argument is
535 /// marked using SecArgPass flag.
536 SmallVector<T, 16> SecPassArg;
537 // SmallVector<ISD::InputArg, 16> SecPassArg;
538 for (auto Arg : Args) {
539 Arg.Flags.setSecArgPass();
540 SecPassArg.push_back(Arg);
541 }
542
543 // Run the second argument pass
544 AnalyzeArguments(SecPassArg, Fn);
545
546 // Sort the locations of the arguments according to their original position.
547 SmallVector<CCValAssign, 16> TmpArgLocs;
548 TmpArgLocs.swap(Locs);
549 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
550 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
551 std::back_inserter(Locs),
552 [](const CCValAssign &A, const CCValAssign &B) -> bool {
553 return A.getValNo() < B.getValNo();
554 });
555 }
556
557private:
558 /// MarkAllocated - Mark a register and all of its aliases as allocated.
559 void MarkAllocated(MCPhysReg Reg);
560
561 void MarkUnallocated(MCPhysReg Reg);
562};
563
564} // end namespace llvm
565
566#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H